REF2025AIDDCR [TI]
8ppm/°C 温漂、低功耗、双输出 Vref 和 Vref/2 电压基准 | DDC | 5 | -40 to 125;
| 型号： | REF2025AIDDCR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8ppm/°C 温漂、低功耗、双输出 Vref 和 Vref/2 电压基准 | DDC | 5 | -40 to 125 光电二极管 |
| 文件： | 总35页 (文件大小：4045K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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REF20xx 低漂移、低功率、双路输出、VREF 和VREF/2 电压基准
1 特性
3 说明
• 两个输出，VREF 和VREF/2，方便用于单电源系统
• 出色的温漂性能：
– –40°C 至125°C 范围内为8ppm/°C（最大值）
• 高初始精度：±0.05%（最大值）
• VREF 和VBIAS 跟踪过热：
仅具有正向电源电压的应用通常需要使用一个处于模数
转换器 (ADC) 输入范围中间位置的附加稳定电压来偏
置输入双极信号。REF20xx 提供了一个可供 ADC 使
用的基准电压 (VREF) 和一个可用于偏置输入双极信号
的高精度电压(VBIAS)。
– –40°C 至85°C 范围内为6ppm/°C（最大值）
– –40°C 至125°C 范围内为7ppm/°C（最大值）
• 微型封装：SOT 23-5
• 低压降：10 mV
• 高输出电流：±20mA
• 低静态电流：360μA
• 线性调节：3ppm/V
• 负载调节：8ppm/mA
• Matte-Sn 版本(REF2025AISDDCR) 在Battelle
REF20xx 在VREF 和VBIAS 输出端具有出色的温漂
（最大8ppm/°C）和初始精度 (0.05%)，同时可保持静
态工作电流低于 430µA。此外，VREF 和 VBIAS 输出端
在 –40°C 至 125°C 的温度范围内相互跟踪，精度为
6ppm/°C（最大值）。与分立式解决方案相比，所有这
些特性使得 REF20xx 提升了信号链的精度、节省了布
板空间并降低了系统成本。仅 10mV 的超低压降允许
器件在极低输入电压条件下工作，这一特性在电池供电
系统中非常适用。
Class III 和类似严苛环境中的抗腐蚀性得以改进
VREF 和 VBIAS 电压具有同样出色的技术规范，而且灌
电流和拉电流能力同样强大。这些器件具有优异的长期
稳定性和低噪声级别，是高精度工业应用的理想选择。
2 应用
• 电表
• 模拟输入模块
• 模拟输出模块
• 伺服驱动器控制模块
• 断路器（ACB、MCCB、VCB）
• 临床数字温度计
• 实验室和现场仪表
• 电池测试
器件信息
封装(1)
封装尺寸（标称值）
器件名称
REF20xx
SOT-23 (5)
2.90mm × 1.60mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
Power
Supply
0.05
0.04
0.03
VBIAS
0.02
0.01
0
VIN+
VOUT
ADC
INA213
REF
RSHUNT
ISENSE
-0.01
-0.02
VREF
-0.03
VIN-
-0.04
-0.05
VBIAS
1.5 V
VREF
3.0 V
œ75 œ50 œ25
0
25
50
75
100 125 150
Temperature (°C)
C001
REF2030
V
REF 和VBIAS 与温度间的关系
VIN
EN
GND
应用示例
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS600
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Table of Contents
9.1 Overview...................................................................17
9.2 Functional Block Diagram.........................................17
9.3 Feature Description...................................................17
9.4 Device Functional Modes..........................................18
10 Applications and Implementation..............................19
10.1 Application Information........................................... 19
10.2 Typical Application.................................................. 20
11 Power-Supply Recommendations..............................25
12 Layout...........................................................................26
12.1 Layout Guidelines................................................... 26
12.2 Layout Example...................................................... 26
13 Device and Documentation Support..........................27
13.1 Documentation Support.......................................... 27
13.2 接收文档更新通知................................................... 27
13.3 支持资源..................................................................27
13.4 Trademarks.............................................................27
13.5 Electrostatic Discharge Caution..............................27
13.6 术语表..................................................................... 27
14 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
Pin Functions.................................................................... 3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 ESD Ratings............................................................... 4
7.3 Recommended Operating Conditions.........................4
7.4 Thermal Information....................................................4
7.5 Electrical Characteristics.............................................5
7.6 Typical Characteristics................................................6
8 Parameter Measurement Information..........................13
8.1 Solder Heat Shift.......................................................13
8.2 Long-Term Stability................................................... 14
8.3 Thermal Hysteresis...................................................15
8.4 Noise Performance................................................... 16
9 Detailed Description......................................................17
Information.................................................................... 27
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision D (May 2018) to Revision E (January 2022)
Page
• 更新了“应用”部分........................................................................................................................................... 1
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• Changed ESD Rating table: changed HBM rating from ±4000 V to ±2500 V.....................................................4
• Updated Long-term stability value...................................................................................................................... 5
• Added Long-Term Stability sub-section under Parameter Measurement Information section..........................14
Changes from Revision C (January 2017) to Revision D (May 2018)
Page
• Changed application information to include corrosion resistance advantages. ...............................................19
Changes from Revision B (July 2014) to Revision C (January 2017)
Page
• Added I/O column to Pin Functions table .......................................................................................................... 3
• Added Storage temperature parameter to Absolute Maximum Ratings table (moved from ESD Ratings table)
............................................................................................................................................................................4
• Changed ESD Rating table: changed title, updated table format ...................................................................... 4
Changes from Revision A (June 2014) to Revision B (July 2014)
Page
• 将器件状态从“量产数据”更改为“混合状态”................................................................................................ 1
• 删除了“器件信息”表中的脚注2...................................................................................................................... 1
• Deleted footnote from Device Comparison Table .............................................................................................. 3
• Added Thermal Information table....................................................................................................................... 4
Changes from Revision * (May 2014) to Revision A (June 2014)
Page
• 更改了产品预发布数据表.................................................................................................................................... 1
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5 Device Comparison Table
PRODUCT
REF2025
REF2030
REF2033
REF2041
VREF
2.5 V
VBIAS
1.25 V
1.5 V
3.0 V
3.3 V
1.65 V
2.048 V
4.096 V
6 Pin Configuration and Functions
5
VREF
VBIAS
GND
EN
1
2
3
4
VIN
图6-1. DDC Package SOT23-5 (Top View)
Pin Functions
PIN
I/O
DESCRIPTION
NO.
1
NAME
VBIAS
GND
EN
Output
Bias voltage output (VREF / 2)
Ground
2
—
3
Input
Input
Output
Enable (EN ≥VIN –0.7 V, device enabled)
Input supply voltage
4
VIN
5
VREF
Reference voltage output (VREF)
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–55
MAX
6
UNIT
VIN
Input voltage
EN
V
VIN + 0.3
150
Operating
Temperature
Junction, Tj
150
°C
Storage, Tstg
170
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
7.2 ESD Ratings
VALUE
±2500
±1500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VIN
Supply input voltage range (IL = 0 mA, TA = 25°C)
VREF + 0.02(1)
5.5
V
(1) See 图7-28 in 节7.6 for minimum input voltage at different load currents and temperature
7.4 Thermal Information
REF20xx
THERMAL METRIC(1)
DDC (SOT23)
5 PINS
193.6
40.2
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
34.5
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.9
ψJT
34.3
ψJB
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
At TA = 25°C, IL = 0 mA, and VIN = 5 V, unless otherwise noted. Both VREF and VBIAS have the same specifications.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ACCURACY AND DRIFT
Output voltage accuracy
0.05%
–0.05%
Output voltage temperature coefficient(1)
±3
±1.5
±2
±8 ppm/°C
–40°C ≤TA ≤125°C
±6
–40°C ≤TA ≤85°C
–40°C ≤TA ≤125°C
VREF and VBIAS tracking over temperature(2)
ppm/°C
±7
LINE AND LOAD REGULATION
Line regulation
3
8
35 ppm/V
ΔVO(ΔVI)
VREF + 0.02 V ≤VIN ≤5.5 V
0 mA ≤IL ≤20 mA ,
VREF + 0.6 V ≤VIN ≤5.5 V
Sourcing
Sinking
20
Load regulation
ppm/mA
20
ΔVO(ΔIL)
0 mA ≤IL ≤–20 mA,
VREF + 0.02 V ≤VIN ≤5.5 V
8
POWER SUPPLY
360
3.3
430
Active mode
460
5
–40°C ≤TA ≤125°C
ICC
Supply current
µA
Shutdown mode
9
–40°C ≤TA ≤125°C
Device in shutdown mode (EN = 0)
Device in active mode (EN = 1)
0
0.7
VIN
20
600
Enable voltage
Dropout voltage
V
VIN –0.7
10
mV
IL = 20 mA
ISC
Short-circuit current
Turn-on time
50
mA
µs
ton
0.1% settling, CL = 1 µF
500
NOISE
Low-frequency noise(3)
12
ppmPP
0.1 Hz ≤f ≤10 Hz
ppm/√
Hz
Output voltage noise density
f = 100 Hz
0.25
CAPACITIVE LOAD
Stable output capacitor range
0
10
µF
HYSTERESIS AND LONG TERM STABILITY
Long-term stability(4)
0 to 1000 hours
25
ppm
ppm
Cycle 1
Cycle 2
60
35
Output voltage hysteresis(5)
25°C, –40°C, 125°C, 25°C
(1) Temperature drift is specified according to the box method. See the 节9.3 section for more details.
(2) The VREF and VBIAS tracking over temperature specification is explained in more detail in the 节9.3 section.
(3) The peak-to-peak noise measurement procedure is explained in more detail in the 节8.4 section.
(4) Long-term stability measurement procedure is explained in more in detail in the 节8.2 section.
(5) The thermal hysteresis measurement procedure is explained in more detail in the 节8.3 section.
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7.6 Typical Characteristics
At TA = 25°C, IL = 0 mA, VIN = 5-V power supply, CL = 0 µF, and 2.5-V output, unless otherwise noted.
70
60
50
40
30
20
10
0
50
40
30
20
10
0
0
1
2
3
4
5
6
7
8
VREF Drift Distribution (ppm/°C)
VREF Initial Accuracy (%)
C010
C008
C004
C015
C015
C016
图7-1. Initial Accuracy Distribution (VREF
)
–40°C ≤TA ≤125°C
图7-2. Drift Distribution (VREF
)
80
70
60
50
40
30
20
10
0
50
40
30
20
10
0
0
1
2
3
4
5
6
7
8
VBIAS Drift Distribution (ppm/°C)
VBIAS Initial Accuracy (%)
图7-3. Initial Accuracy Distribution (VBIAS
)
–40°C ≤TA ≤125°C
图7-4. Drift Distribution (VBIAS
)
40
30
20
10
0
60
50
40
30
20
10
0
0
1
2
3
4
5
6
VREF and VBIAS Tracking Over Temperature (ppm/°C)
VREF and VBIAS Matching (ppm)
图7-5. VREF –2 × VBIAS Distribution
–40°C ≤TA ≤85°C
图7-6. Distribution of VREF –2 × VBIAS Drift Tracking Over
Temperature
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7.6 Typical Characteristics (continued)
At TA = 25°C, IL = 0 mA, VIN = 5-V power supply, CL = 0 µF, and 2.5-V output, unless otherwise noted.
60
50
40
30
20
10
0
50
40
30
20
10
0
0
1
2
3
4
5
6
7
-0.0125 -0.01 -0.0075 -0.005 -0.0025
0
0.0025
VREF and VBIAS Tracking Over Temperature (ppm/°C)
Solder Heat Shift Histogram - VREF (%)
C017
C041
–40°C ≤TA ≤125°C
Refer to the 节8.1 section for more information.
图7-7. Distribution of VREF –2 × VBIAS Drift Tracking Over
图7-8. Solder Heat Shift Distribution (VREF
)
Temperature
60
50
40
30
20
10
0
0.05
0.04
0.03
0.02
0.01
0
VBIAS
-0.01
-0.02
-0.03
-0.04
-0.05
VREF
-0.0125 -0.01 -0.0075 -0.005 -0.0025
0
0.0025
œ75 œ50 œ25
0
25
50
75
100 125 150
Solder Heat Shift Histogram - VBIAS (%)
Temperature (°C)
C001
C040
图7-10. Output Voltage Accuracy (VREF) vs Temperature
Refer to the 节8.1 section for more information.
图7-9. Solder Heat Shift Distribution (VBIAS
)
1000
2.5005
750
500
-40°C
2.5000
2.4995
2.4990
2.4985
2.4980
250
25°C
0
œ250
œ500
œ750
œ1000
125°C
œ75 œ50 œ25
0
25
50
75
100 125 150
œ20
œ15
œ10
œ5
0
Load Current (mA)
5
10
15
20
Temperature (°C)
C003
C038
图7-11. VREF –2 × VBIAS Tracking vs Temperature
VREF output
图7-12. Output Voltage Change vs Load Current (VREF
)
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7.6 Typical Characteristics (continued)
At TA = 25°C, IL = 0 mA, VIN = 5-V power supply, CL = 0 µF, and 2.5-V output, unless otherwise noted.
1.2503
1.2501
1.2499
1.2497
1.2495
1.2493
12
11
10
9
-40°C
8
7
25°C
6
125°C
15
5
4
œ20
œ15
œ10
œ5
0
5
10
20
œ75 œ50 œ25
0
25
50
75
100 125 150
Load Current (mA)
Temperature (°C)
C025
C039
VREF output
IL = 20 mA
VBIAS output
图7-14. Load Regulation Sourcing vs Temperature (VREF
)
图7-13. Output Voltage Change vs Load Current (VBIAS
)
12
11
10
9
12
11
10
9
8
8
7
7
6
6
5
5
4
4
œ75 œ50 œ25
0
25
50
75
100 125 150
œ75 œ50 œ25
0
25
50
75
100 125 150
Temperature (°C)
Temperature (°C)
C020
C021
VBIAS output
IL = 20 mA
VREF output
IL = –20 mA
图7-15. Load Regulation Sourcing vs Temperature (VBIAS
)
图7-16. Load Regulation Sinking vs Temperature (VREF
)
12
11
10
9
5
4.5
4
8
3.5
3
7
6
2.5
2
5
4
œ75 œ50 œ25
0
25
50
75
100 125 150
œ75 œ50 œ25
0
25
50
75
100 125 150
Temperature (°C)
IL = –20 mA
Temperature (°C)
C022
C019
VBIAS output
VREF output
图7-18. Line Regulation vs Temperature (VREF
)
图7-17. Load Regulation Sinking vs Temperature (VBIAS
)
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7.6 Typical Characteristics (continued)
At TA = 25°C, IL = 0 mA, VIN = 5-V power supply, CL = 0 µF, and 2.5-V output, unless otherwise noted.
5
4.5
4
100
VBIAS
80
VREF
3.5
3
60
40
2.5
2
20
œ75 œ50 œ25
0
25
50
75
100 125 150
1
10
100
1k
10k
100k
Temperature (°C)
Frequency (Hz)
C018
C026
VBIAS output
CL = 0 µF
图7-19. Line Regulation vs Temperature (VBIAS
)
图7-20. Power-Supply Rejection Ratio vs Frequency
100
VIN + 0.25 V
VIN + 0.25 V
VBIAS
500 mV/div
40 mV/div
VIN - 0.25 V
80
VREF
VREF
60
40
20
Time (500 µs/div)
1
10
100
1k
10k
100k
Frequency (Hz)
C006
C027
CL = 1 µF
图7-22. Line Transient Response
CL = 10 µF
图7-21. Power-Supply Rejection Ratio vs Frequency
VIN + 0.25 V
VIN + 0.25V
500 mV/div
40 mV/div
+1 mA
+1 mA
VIN - 0.25V
2 mA/div
- 1 mA
VREF
VREF
20 mV/div
Time (500 µs/div)
Time (500 µs/div)
C006
C032
CL = 10 µF
图7-23. Line Transient Response
CL = 1 µF
IL = ±1-mA step
图7-24. Load Transient Response
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7.6 Typical Characteristics (continued)
At TA = 25°C, IL = 0 mA, VIN = 5-V power supply, CL = 0 µF, and 2.5-V output, unless otherwise noted.
+20 mA
+20 mA
+1 mA
+1 mA
40 mA/div
2 mA/div
-20 mA
- 1 mA
VREF
VREF
20 mV/div
40 mV/div
Time (500 µs/div)
Time (500 µs/div)
C037
C031
CL = 10 µF
IL = ±1-mA step
CL = 1 µF
IL = ±20-mA step
图7-25. Load Transient Response
图7-26. Load Transient Response
400
300
200
100
0
125°C
+20 mA
+20 mA
40 mA/div
40 mV/div
25°C
-20 mA
œ40°C
VREF
Time (500 µs/div)
œ30
œ20
œ10
0
10
20
30
Load Current (mA)
C036
C005
CL = 10 µF
IL = ±20-mA step
图7-28. Minimum Dropout Voltage vs Load Current
图7-27. Load Transient Response
VIN
VIN
2 V/div
2 V/div
VREF
VREF
Time (100 µs/div)
Time (100 µs/div)
C033
C034
CL = 1 µF
CL = 10 µF
图7-29. Turn-On Settling Time
图7-30. Turn-On Settling Time
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7.6 Typical Characteristics (continued)
At TA = 25°C, IL = 0 mA, VIN = 5-V power supply, CL = 0 µF, and 2.5-V output, unless otherwise noted.
500
450
400
350
300
250
200
500
450
400
350
300
250
200
œ75 œ50 œ25
0
25
50
75
100 125 150
2
3
4
5
6
Temperature (°C)
Input Voltage (V)
C006
C007
图7-31. Quiescent Current vs Temperature
图7-32. Quiescent Current vs Input Voltage
Time (1 s/div)
Time (1 s/div)
C028
C029
VREF output
VBIAS output
图7-33. 0.1-Hz to 10-Hz Noise (VREF
)
图7-34. 0.1-Hz to 10-Hz Noise (VBIAS)
1
100
10
CL = 0 ꢁF
CL = 0 µF
CL = 1µF
0.1
1
CL = 4.7 ꢀF
CL = 10 ꢁF
0.1
CL = 10 µF
0.01
0.01
1
10
100
1k
10k
0.01
0.1
1
10
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
C024
C030
图7-35. Output Voltage Noise Spectrum
VREF output
图7-36. Output Impedance vs Frequency (VREF
)
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7.6 Typical Characteristics (continued)
At TA = 25°C, IL = 0 mA, VIN = 5-V power supply, CL = 0 µF, and 2.5-V output, unless otherwise noted.
100
10
40
35
30
25
20
15
10
5
CL = 0 ꢁF
CL = 1µF
1
CL = 10 ꢁF
0.1
0.01
0
0.01
0.1
1
10
100
1k
10k
100k
Thermal Hysterisis - VREF (ppm)
Frequency (Hz)
C023
C013
VBIAS output
图7-38. Thermal Hysteresis Distribution (VREF
)
图7-37. Output Impedance vs Frequency (VBIAS
)
50
45
40
35
30
25
20
15
10
5
40
35
30
25
20
15
10
5
0
-5
0
-10
0
100 200 300 400 500 600 700 800 900 1000
Time (hr)
Thermal Hysteresis - VBIAS (ppm)
图7-40. Long-Term Stability (First 1000 hours)
C014
图7-39. Thermal Hysteresis Distribution (VBIAS
)
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8 Parameter Measurement Information
8.1 Solder Heat Shift
The materials used in the manufacture of the REF20xx have differing coefficients of thermal expansion, resulting
in stress on the device die when the part is heated. Mechanical and thermal stress on the device die can cause
the output voltages to shift, degrading the initial accuracy specifications of the product. Reflow soldering is a
common cause of this error.
In order to illustrate this effect, a total of 92 devices were soldered on four printed circuit boards [23 devices on
each printed circuit board (PCB)] using lead-free solder paste and the paste manufacturer suggested reflow
profile. The reflow profile is as shown in 图 8-1. The printed circuit board is comprised of FR4 material. The
board thickness is 1.57 mm and the area is 171.54 mm × 165.1 mm.
The reference and bias output voltages are measured before and after the reflow process; the typical shift is
displayed in 图 8-2 and 图 8-3. Although all tested units exhibit very low shifts (< 0.01%), higher shifts are also
possible depending on the size, thickness, and material of the printed circuit board. An important note is that the
histograms display the typical shift for exposure to a single reflow profile. Exposure to multiple reflows, as is
common on PCBs with surface-mount components on both sides, causes additional shifts in the output bias
voltage. If the PCB is exposed to multiple reflows, the device should be soldered in the second pass to minimize
its exposure to thermal stress.
300
250
200
150
100
50
0
0
50
100
150
200
250
300
350
400
Time (seconds)
C01
图8-1. Reflow Profile
50
40
30
20
10
0
60
50
40
30
20
10
0
-0.0125 -0.01 -0.0075 -0.005 -0.0025
0
0.0025
-0.0125 -0.01 -0.0075 -0.005 -0.0025
0
0.0025
Solder Heat Shift Histogram - VREF (%)
Solder Heat Shift Histogram - VBIAS (%)
C040
C041
图8-3. Solder Heat Shift Distribution, VBIAS (%)
图8-2. Solder Heat Shift Distribution, VREF (%)
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8.2 Long-Term Stability
The long term stability of the REF20xx was collected on 32 parts that were soldered onto Printed Circuit Boards
without any slots or special layout considerations. The boards were then placed into an oven with air
temperature maintained at TA = 35°C. The VREF output of the 32 parts was measured regularly. Typical long term
stability is as shown in 图8-4.
50
45
40
35
30
25
20
15
10
5
0
-5
-10
0
100 200 300 400 500 600 700 800 900 1000
Time (hr)
图8-4. Long Term Stability –1000 hours (VREF
)
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8.3 Thermal Hysteresis
Thermal hysteresis is measured with the REF20xx soldered to a PCB, similar to a real-world application.
Thermal hysteresis for the device is defined as the change in output voltage after operating the device at 25°C,
cycling the device through the specified temperature range, and returning to 25°C. Hysteresis can be expressed
by 方程式1:
≈
’
VPRE - VPOST
VHYST
=
ñ 106 (ppm)
∆
∆
÷
÷
VNOM
«
◊
(1)
where
• VHYST = thermal hysteresis (in units of ppm),
• VNOM = the specified output voltage,
• VPRE = output voltage measured at 25°C pre-temperature cycling, and
• VPOST = output voltage measured after the device has cycled from 25°C through the specified temperature
range of –40°C to 125°C and returns to 25°C.
Typical thermal hysteresis distribution is as shown in 图8-5 and 图8-6.
40
35
30
25
20
15
10
5
40
35
30
25
20
15
10
5
0
0
Thermal Hysterisis - VREF (ppm)
Thermal Hysteresis - VBIAS (ppm)
C013
C014
图8-5. Thermal Hysteresis Distribution (VREF
)
图8-6. Thermal Hysteresis Distribution (VBIAS
)
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8.4 Noise Performance
Typical 0.1-Hz to 10-Hz voltage noise can be seen in 图 8-7 and 图 8-8. Device noise increases with output
voltage and operating temperature. Additional filtering can be used to improve output noise levels, although care
should be taken to ensure the output impedance does not degrade ac performance. Peak-to-peak noise
measurement setup is shown in 图8-9.
Time (1 s/div)
Time (1 s/div)
C028
C029
图8-7. 0.1-Hz to 10-Hz Noise (VREF
)
图8-8. 0.1-Hz to 10-Hz Noise (VBIAS)
10 kꢁ
100 ꢁ
40 mF
VIN
To scope
VREF
+
10 ꢀF
EN
1 kꢁ
2-Pole High-pass
4-Pole Low-pass
0.1 Hz to 10 Hz Filter
REF20xx
0.1 ꢀF
GND
VBIAS
图8-9. 0.1-Hz to 10-Hz Noise Measurement Setup
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9 Detailed Description
9.1 Overview
The REF20xx are a family of dual-output, VREF and VBIAS (VREF / 2) band-gap voltage references. The 节 9.2
section provides a block diagram of the basic band-gap topology and the two buffers used to derive the VREF
and VBIAS outputs. Transistors Q1 and Q2 are biased such that the current density of Q1 is greater than that of
Q2. The difference of the two base emitter voltages (VBE1 – VBE2) has a positive temperature coefficient and is
forced across resistor R5. The voltage is amplified and added to the base emitter voltage of Q2, which has a
negative temperature coefficient. The resulting band-gap output voltage is almost independent of temperature.
Two independent buffers are used to generate VREF and VBIAS from the band-gap voltage. The resistors R1, R2
and R3, R4 are sized such that VBIAS = VREF / 2.
e-Trim™ is a method of package-level trim for the initial accuracy and temperature coefficient of VREF and VBIAS
,
implemented during the final steps of manufacturing after the plastic molding process. This method minimizes
the influence of inherent transistor mismatch, as well as errors induced during package molding. e-Trim is
implemented in the REF20xx to minimize the temperature drift and maximize the initial accuracy of both the VREF
and VBIAS outputs.
9.2 Functional Block Diagram
R2
R1
R6
R7
VREF
+
+
e-Trim
R5
+
+
R4
VBE1 VBE2
-
-
R3
Q2
VBIAS
Q1
+
e-Trim
9.3 Feature Description
9.3.1 VREF and VBIAS Tracking
Most single-supply systems require an additional stable voltage in the middle of the analog-to-digital converter
(ADC) input range to bias input bipolar signals. The VREF and VBIAS outputs of the REF20xx are generated from
the same band-gap voltage as shown in the 节 9.2 section. Hence, both outputs track each other over the full
temperature range of –40°C to 125°C with an accuracy of 7 ppm/°C (maximum). The tracking accuracy
increases to 6 ppm/°C (maximum) when the temperature range is limited to –40°C to 85°C. The tracking error is
calculated using the box method, as described by 方程式2:
VDIFF(MAX) - VDIFF (MIN)
≈
∆
«
’
÷
◊
Tracking Error =
ñ106 (ppm)
VREF ñTemperature Range
(2)
where
VDIFF = VREF - 2• VBIAS
•
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The tracking accuracy is as shown in 图9-1.
0.05
0.04
0.03
0.02
0.01
0
VBIAS
-0.01
-0.02
-0.03
-0.04
-0.05
VREF
œ75 œ50 œ25
0
25
50
75
100 125 150
Temperature (°C)
C001
图9-1. VREF and VBIAS Tracking vs Temperature
9.3.2 Low Temperature Drift
The REF20xx is designed for minimal drift error, which is defined as the change in output voltage over
temperature. The drift is calculated using the box method, as described by 方程式3:
VREF(MAX)-VREF(MIN)
≈
∆
«
’
÷
◊
Drift =
ñ106 (ppm)
VREFñTemperature Range
(3)
9.3.3 Load Current
The REF20xx family is specified to deliver a current load of ±20 mA per output. Both the VREF and VBIAS outputs
of the device are protected from short circuits by limiting the output short-circuit current to 50 mA. The device
temperature increases according to 方程式4:
TJ = TA +P •RꢀJA
D
(4)
where
• TJ = junction temperature (°C),
• TA = ambient temperature (°C),
• PD = power dissipated (W), and
• RθJA = junction-to-ambient thermal resistance (°C/W)
The REF20xx maximum junction temperature must not exceed the absolute maximum rating of 150°C.
9.4 Device Functional Modes
When the EN pin of the REF20xx is pulled high, the device is in active mode. The device should be in active
mode for normal operation. The REF20xx can be placed in a low-power mode by pulling the ENABLE pin low.
When in shutdown mode, the output of the device becomes high impedance and the quiescent current of the
device reduces to 5 µA in shutdown mode. See the 节7.5 for logic high and logic low voltage levels.
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10 Applications and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
10.1 Application Information
The low-drift, bidirectional, single-supply, low-side, current-sensing solution, described in this section, can
accurately detect load currents from –2.5 A to 2.5 A. The linear range of the output is from 250 mV to 2.75 V.
Positive current is represented by output voltages from 1.5 V to 2.75 V, whereas negative current is represented
by output voltages from 250 mV to 1.5 V. The difference amplifier is the INA213 current-shunt monitor, whose
supply and reference voltages are supplied by the low-drift REF2030.
Industrial applications with electronics in corrosive environments are susceptible to corrosive damage due to the
exposure to heat, moisture, and corrosive gases. The combination of the following conditions in a given system
lead to higher risk of corrosive damage:
1. Ventilated enclosures exposing underlying PCB.
2. PCBs not conformally coated.
3. Exposed-lead components with plating susceptible to corrosion.
4. Changes in plating techniques for RoHS compliance (e.g. removal of Pb (lead) and certain types of plating).
To improve resistance to corrosion in harsh environments, the REF2025AISDDCR uses Matte-Sn plating with
improved assembly process to reduce exposed Cu, leading to improved corrosion resistance in the Battelle
Class III and similar harsh environments. The “S” in the part number identifies this special plating option.
REF2025 versions that do not have the “S” will continue to be available in industry standard NiPdAu
processing technique.
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10.2 Typical Application
10.2.1 Low-Side, Current-Sensing Application
REF20xx
VREF
+
VIN
Bandgap
EN
+
VBIAS
+
VCC
œ
GND
REF
V+
ILOAD
VREF
ADC
+
IN+
+
OUT
VBUS
œ
RSHUNT
VOUT
IN-
GND
INA213B
图10-1. Low-Side, Current-Sensing Application
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10.2.1.1 Design Requirements
The design requirements are as follows:
1. Supply voltage: 5.0 V
2. Load current: ±2.5 A
3. Output: 250 mV to 2.75 V
4. Maximum shunt voltage: ±25 mV
10.2.1.2 Detailed Design Procedure
Low-side current sensing is desirable because the common-mode voltage is near ground. Therefore, the current-
sensing solution is independent of the bus voltage, VBUS. When sensing bidirectional currents, use a differential
amplifier with a reference pin. This procedure allows for the differentiation between positive and negative
currents by biasing the output stage such that it can respond to negative input voltages. There are a variety of
methods for supplying power (V+) and the reference voltage (VREF, or VBIAS) to the differential amplifier. For a
low-drift solution, use a monolithic reference that supplies both power and the reference voltage. 图 10-2 shows
the general circuit topology for a low-drift, low-side, bidirectional, current-sensing solution. This topology is
particularly useful when interfacing with an ADC; see 图 10-1. Not only do VREF and VBIAS track over
temperature, but their matching is much better than alternate topologies. For a more detailed version of the
design procedure, refer to TIDU357.
REF20xx
VREF
+
VIN
Bandgap
EN
+
VBIAS
+
VCC
œ
GND
REF
V+
ILOAD
+
IN+
+
OUT
VBUS
œ
RSHUNT
VSHUNT
VOUT
IN-
GND
INA213B
图10-2. Low-Drift, Low-side, Bidirectional, Current-Sensing Circuit Topology
The transfer function for the circuit given in 图10-2 is as shown in 方程式5:
VOUT = G • (êVSHUNT ) + VBIAS
= G • (êILOAD • RSHUNT) + VBIAS
(5)
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10.2.1.2.1 Shunt Resistor
As illustrated in 图10-2, the value of VSHUNT is the ground potential for the system load. If the value of VSHUNT is
too large, issues may arise when interfacing with systems whose ground potential is actually 0 V. Also, a value of
VSHUNT that is too negative may violate the input common-mode voltage of the differential amplifier in addition to
potential interfacing issues. Therefore, limiting the voltage across the shunt resistor is important. 方程式6 can be
used to calculate the maximum value of RSHUNT
.
VSHUNT(max)
RSHUNT(max)
=
ILOAD(max)
(6)
Given that the maximum shunt voltage is ±25 mV and the load current range is ±2.5 A, the maximum shunt
resistance is calculated as shown in 方程式7.
VSHUNT (max)
25mV
2.5A
RSHUNT (max)
=
=
=10mW
ILOAD(max)
(7)
To minimize errors over temperature, select a low-drift shunt resistor. To minimize offset error, select a shunt
resistor with the lowest tolerance. For this design, the Y14870R01000B9W resistor is used.
10.2.1.2.2 Differential Amplifier
The differential amplifier used for this design should have the following features:
1. Single-supply (3 V),
2. Reference voltage input,
3. Low initial input offset voltage (VOS),
4. Low-drift,
5. Fixed gain, and
6. Low-side sensing (input common-mode range below ground).
For this design, a current-shunt monitor (INA213) is used. The INA21x family topology is shown in 图 10-3. The
INA213B specifications can be found in the INA213 product data sheet.
V+
-
IN-
OUT
REF
IN+
+
GND
Copyright © 2017, Texas Instruments Incorporated
图10-3. INA21x Current-Shunt Monitor Topology
The INA213B is an excellent choice for this application because all the required features are included. In
general, instrumentation amplifiers (INAs) do not have the input common-mode swing to ground that is essential
for this application. In addition, INAs require external resistors to set their gain, which is not desirable for low-drift
applications. Difference amplifiers typically have larger input bias currents, which reduce solution accuracy at
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small load currents. Difference amplifiers typically have a gain of 1 V/V. When the gain is adjustable, these
amplifiers use external resistors that are not conducive to low-drift applications.
10.2.1.2.3 Voltage Reference
The voltage reference for this application should have the following features:
1. Dual output (3.0 V and 1.5 V),
2. Low drift, and
3. Low tracking errors between the two outputs.
For this design, the REF2030 is used. The REF20xx topology is as shown in the 节9.2 section.
The REF2030 is an excellent choice for this application because of its dual output. The temperature drift of
8 ppm/°C and initial accuracy of 0.05% make the errors resulting from the voltage reference minimal in this
application. In addition, there is minimal mismatch between the two outputs and both outputs track very well
across temperature, as shown in 图10-4 and 图10-5.
40
30
20
10
0
60
50
40
30
20
10
0
0
1
2
3
4
5
6
VREF and VBIAS Tracking Over Temperature (ppm/°C)
VREF and VBIAS Matching (ppm)
C016
C004
图10-5. Distribution of VREF –2 × VBIAS Drift
图10-4. VREF –2 × VBIAS Distribution (At TA =
Tracking Over Temperature
25°C)
10.2.1.2.4 Results
表10-1 summarizes the measured results.
表10-1. Measured Results
ERROR
UNCALIBRATED (%)
CALIBRATED (%)
±0.004
Error across the full load current range (25°C)
Error across the full load current range (–40°C to 125°C)
±0.0355
±0.0522
±0.0606
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10.2.1.3 Application Curves
Performing a two-point calibration at 25°C removes the errors associated with offset voltage, gain error, and so
forth. 图 10-6 to 图 10-8 show the measured error at different conditions. For a more detailed description on
measurement procedure, calibration, and calculations, please refer to TIDU357.
3
2.5
2
800
600
-40°C
0°C
400
200
1.5
1
0
25°C
85°C
œ200
œ400
œ600
œ800
0.5
0
125°C
-3
-2
-1
0
1
2
3
œ3
œ2
œ1
0
1
2
3
Load current (mA)
Load current (mA)
C00
C00
图10-6. Measured Transfer Function
图10-7. Uncalibrated Error vs Load Current
800
-40°C
0°C
600
400
200
0
25°C
85°C
œ200
œ400
œ600
œ800
125°C
œ3
œ2
œ1
0
1
2
3
Load current (mA)
C00
图10-8. Calibrated Error vs Load Current
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11 Power-Supply Recommendations
The REF20xx family of references feature an extremely low-dropout voltage. These references can be operated
with a supply of only 20 mV above the output voltage. For loaded reference conditions, a typical dropout voltage
versus load is shown in 图11-1. A supply bypass capacitor ranging between 0.1 µF to 10 µF is recommended.
400
125°C
300
25°C
œ40°C
200
100
0
œ30
œ20
œ10
0
10
20
30
Load Current (mA)
C005
图11-1. Dropout Voltage vs Load Current
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12 Layout
12.1 Layout Guidelines
图 12-1 shows an example of a PCB layout for a data acquisition system using the REF2030. Some key
considerations are:
• Connect low-ESR, 0.1-μF ceramic bypass capacitors at VIN, VREF, and VBIAS of the REF2030.
• Decouple other active devices in the system per the device specifications.
• Using a solid ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise
pickup.
• Place the external components as close to the device as possible. This configuration prevents parasitic errors
(such as the Seebeck effect) from occurring.
• Minimize trace length between the reference and bias connections to the INA and ADC to reduce noise
pickup.
• Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when absolutely necessary.
12.2 Layout Example
V+
IN+
Via to
Input Power
C
IN-
GND
REF
C
OUT
REF
VREF
VBIAS
GND
Via
to GND
Plane
Analog Input
C
C
Microcontroller
A/D Input
C
EN
VIN
DIG1
AIN
图12-1. Layout Example
Copyright © 2022 Texas Instruments Incorporated
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Product Folder Links: REF2025 REF2030 REF2033 REF2041
REF2025, REF2030, REF2033, REF2041
ZHCSCM7E –JULY 2018 –REVISED FEBRUARY 2022
www.ti.com.cn
13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation see the following:
• INA21x Voltage Output, Low- or High-Side Measurement, Bidirectional, Zero-Drift Series, Current-Shunt
Monitors (SBOS437)
• Low-Drift Bidirectional Single-Supply Low-Side Current Sensing Reference Design (TIDU357)
13.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
13.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
13.4 Trademarks
e-Trim™ is a trademark of Texas Instruments, Inc.
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
13.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
9-Mar-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
REF2025AIDDCR
REF2025AIDDCT
REF2025AISDDCR
REF2030AIDDCR
REF2030AIDDCT
REF2033AIDDCR
REF2033AIDDCT
REF2041AIDDCR
REF2041AIDDCT
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
5
5
5
5
5
5
5
5
5
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
GACM
NIPDAU
Call TI
GACM
1M98
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
GADM
GADM
GAEM
GAEM
GAFM
GAFM
250
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
9-Mar-2021
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Mar-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
REF2025AIDDCR
REF2025AIDDCT
REF2025AISDDCR
REF2030AIDDCR
REF2030AIDDCT
REF2033AIDDCR
REF2033AIDDCT
REF2041AIDDCR
REF2041AIDDCT
SOT-
23-THIN
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
5
5
5
5
5
5
5
5
5
3000
250
179.0
179.0
180.0
179.0
179.0
179.0
179.0
179.0
179.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
SOT-
23-THIN
SOT-
23-THIN
3000
3000
250
SOT-
23-THIN
SOT-
23-THIN
SOT-
23-THIN
3000
250
SOT-
23-THIN
SOT-
23-THIN
3000
250
SOT-
23-THIN
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Mar-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
REF2025AIDDCR
REF2025AIDDCT
REF2025AISDDCR
REF2030AIDDCR
REF2030AIDDCT
REF2033AIDDCR
REF2033AIDDCT
REF2041AIDDCR
REF2041AIDDCT
SOT-23-THIN
SOT-23-THIN
SOT-23-THIN
SOT-23-THIN
SOT-23-THIN
SOT-23-THIN
SOT-23-THIN
SOT-23-THIN
SOT-23-THIN
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
5
5
5
5
5
5
5
5
5
3000
250
213.0
213.0
213.0
213.0
213.0
213.0
213.0
213.0
213.0
191.0
191.0
191.0
191.0
191.0
191.0
191.0
191.0
191.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
3000
3000
250
3000
250
3000
250
Pack Materials-Page 2
PACKAGE OUTLINE
DDC0005A
SOT-23 - 1.1 max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
3.05
2.55
1.1
0.7
1.75
1.45
0.1 C
B
A
PIN 1
INDEX AREA
5
1
NOTE 4
(0.15)
0.95
3.05
2.75
1.9
2
3
(0.2)
4
0.1
TYP
0.0
0.5
0.3
5X
0.2
C A B
0.25
GAGE PLANE
0.20
0.12
TYP
0 -8 TYP
C
SEATING PLANE
0.6
0.3
TYP
4220752/A 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC MO-193.
4. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DDC0005A
SOT-23 - 1.1 max height
SMALL OUTLINE TRANSISTOR
SYMM
5X (1.1)
5X (0.6)
1
5
SYMM
2
3
4X (0.95)
4
(R0.05) TYP
(2.7)
LAND PATTERN EXAMPLE
EXPLOSED METAL SHOWN
SCALE:15X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDERMASK DETAILS
4220752/A 03/2023
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DDC0005A
SOT-23 - 1.1 max height
SMALL OUTLINE TRANSISTOR
SYMM
5X (1.1)
5X (0.6)
1
5
SYMM
2
3
4X(0.95)
4
(R0.05) TYP
(2.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:15X
4220752/A 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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Copyright © 2023，德州仪器 (TI) 公司
相关型号：
REF2025QDDCRQ1
REF20xx-Q1 Low-Drift, Low-Power, Dual-Output, VREF and VREF / 2 Voltage References
TI
REF2030QDDCRQ1
REF20xx-Q1 Low-Drift, Low-Power, Dual-Output, VREF and VREF / 2 Voltage References
TI
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