REF35409QDBVR [TI]
650nA 静态电流、12ppm/°C 温漂、超低功耗精密电压基准 | DBV | 6 | -40 to 125;
| 型号： | REF35409QDBVR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 650nA 静态电流、12ppm/°C 温漂、超低功耗精密电压基准 | DBV | 6 | -40 to 125 |
| 文件： | 总38页 (文件大小：2340K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
REF35
ZHCSPK8A –DECEMBER 2021 –REVISED AUGUST 2022
REF35 超低功耗高精度电压基准
1 特性
3 说明
• 超低静态电流：
REF35 是毫微功耗、低漂移、高精度基准器件系列。
REF35 系列具有 ±0.05% 初始精度，典型功耗为
650nA。该器件的温度系数 (12ppm/°C) 和长期稳定性
（1000 小时内为 40ppm）有助于提高系统稳定性和可
靠性。凭借低功耗以及高精度规格，此器件适用于多种
便携式应用和低电流应用。
– 650nA（典型值）
• 初始精度：±0.05%（最大值）
• 温度系数：
– 12ppm/°C（−40°C 至105°C 时的最大值）
• 输出1/f 噪声（0.1Hz 至10Hz）：3.3ppmP-P
• NR 引脚可降低噪声
• EN 引脚可降低关断电流消耗
• 长期稳定性：1k 小时内为40ppm
• 热迟滞：70ppm
REF35 可提供高达 10mA 电流，噪声为 3.3ppmp-p
，
负载调节为 20ppm/mA。借助这一功能集，REF35 可
为精密传感器和 12 至 16 位数据转换器提供强大的低
噪声高精度电源。
• 额定温度范围：-40°C 至+105°C
• 工作温度范围：-55°C 至+125°C
• 输出电流：+10mA，−5mA
• 输入电压：VREF + VDO 至6V
• 输出电压选项：
– 1.024V、1.2V、1.25V、1.6V、1.8V、2.048V、
2.5V、3.0V、3.3V、4.096V、5.0V
• 小型6 引脚SOT−23 封装
此系列的额定工作温度范围为 -40°C 至 105°C，并且
在 -55°C 至 125°C 也可以正常运行。凭借宽温度范
围，此系列适用于工业应用。
REF35 提供 1.024V 至 5.0V 的宽输出电压范围。该器
件具有节省空间的 6 引脚 SOT-23 和 4 引脚 WCSP 封
装选项。有关可用的电压和封装选项，请联系您当地的
TI 销售代表。
• 尺寸超小的4 引脚WCSP 封装
封装信息
器件型号
封装(1)
封装尺寸（标称值）
2.90mm × 1.60mm
1.05mm × 0.84mm
2 应用
SOT-23 (6)
WCSP (4) (2)
REF35xxx
• 流量变送器
• 血糖监控
• 伺服驱动器控制模块
• 电能质量分析仪
• 故障指示灯
• 示波器
(1) 如需了解所有可用电压选项和封装，请参阅数据表末尾的可订
购产品附录。
(2) 产品预发布。
• 过程分析
• 光学模块
Connection Diagram
Typical Application Use Cases
REF35
REF35
REF35
EN
Input
Output
Current
SENSE
VIN
REF
ADC / DAC
VREF
NR
VDD
GND
1 μF
0.1 μF
V
GND
REF35
GND
Optional
GND
GND
GND
GND
Amplifier Biasing
CSA, INA, DFA etc
Sensor power supply
Bridge, Thermocouple etc
Data Converter power supply
REF35 用例
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNAS809
REF35
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ZHCSPK8A –DECEMBER 2021 –REVISED AUGUST 2022
Table of Contents
9 Detailed Description......................................................19
9.1 Overview...................................................................19
9.2 Functional Block Diagram.........................................19
9.3 Feature Description...................................................19
9.4 Device Functional Modes .........................................20
10 Application and Implementation................................22
10.1 Application Information........................................... 22
10.2 Typical Applications................................................ 22
10.3 Power Supply Recommendations...........................25
10.4 Layout..................................................................... 25
11 Device and Documentation Support..........................27
11.1 Documentation Support.......................................... 27
11.2 接收文档更新通知................................................... 27
11.3 支持资源..................................................................27
11.4 Trademarks............................................................. 27
11.5 Electrostatic Discharge Caution..............................27
11.6 术语表..................................................................... 27
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison.........................................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings........................................ 4
7.2 ESD Ratings............................................................... 4
7.3 Recommended Operating Conditions.........................4
7.4 Thermal Information....................................................4
7.5 Electrical Characteristics.............................................5
7.6 Typical Characteristics................................................7
8 Parameter Measurement Information..........................12
8.1 Solder Heat Shift.......................................................12
8.2 Temperature Coefficient............................................13
8.3 Long-Term Stability................................................... 13
8.4 Thermal Hysteresis...................................................14
8.5 Noise Performance................................................... 15
8.6 Power Dissipation..................................................... 18
Information.................................................................... 27
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (December 2021) to Revision A (August 2022)
Page
• 量产数据发布...................................................................................................................................................... 1
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ZHCSPK8A –DECEMBER 2021 –REVISED AUGUST 2022
5 Device Comparison
PRODUCT
VREF
SOT-23 (6)
WCSP (4) (1)
REF35102QDBVR
REF35120QDBVR
REF35125QDBVR
REF35160QDBVR
REF35180QDBVR
REF35205QDBVR
REF35250QDBVR
REF35300QDBVR
REF35330QDBVR
REF35409QDBVR
REF35500QDBVR
REF35102YBHR
REF35120YBHR
REF35125YBHR
REF35160YBHR
REF35180YBHR
REF35205YBHR
REF35250YBHR
REF35300YBHR
REF35330YBHR
REF35409YBHR
REF35500YBHR
1.024 V
1.2 V
1.25 V
1.6 V
1.8 V
2.048 V
2.5 V
3.0 V
3.3 V
4.096 V
5.0 V
(1) Product preview. Contact local TI support for samples.
6 Pin Configuration and Functions
VREF
A1
VIN
A2
GND
GND
EN
1
VREF
NR
6
5
4
2
3
GND
B1
EN
B2
VIN
Not to scale
图6-1. DBV Package
6-Pin SOT-23
Top View
Not to scale
Preview only
图6-2. YBH Package
4-Pin WCSP
Top View
表6-1. Pin Functions
PIN
TYPE
DESCRIPTION
NAME
GND
GND
EN
SOT-23
WCSP
1
2
3
4
5
6
B1
-
Ground
Ground
Input
Device ground connection
Device ground connection
B2
A2
-
Enable connection. Enables or disables the device.
Input supply voltage connection
VIN
Power
Output
Output
NR
Noise reduction pin. Connect a capacitor to reduce noise.
Reference voltage output
VREF
A1
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
–0.3
–0.3
–0.3
MAX
6.5
UNIT
V
Input voltage
IN
Enable voltage
EN
VREF
ISC
TA
IN + 0.3 (2)
IN + 0.3 (2)
20
V
Output voltage
V
Output short circuit current
Operating temperature range
Storage temperature range
mA
°C
°C
125
–55
–65
Tstg
170
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) IN + 0.3 V or 6.5 V, whichever is lower
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001,
all pins (1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per ANSI/ESDA/JEDEC
JS-002, all pins (2)
±750
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
6
UNIT
(2)
IN
EN
IL
Input voltage (1)
Enable voltage
VOUT + VDO
V
V
0
–5
IN
Output current
10
mA
°C
TA
Operating temperature
25
125
–40
(1) For VREF = 1.024 V to 1.5 V, minimum VIN = 1.7 V
(2) VDO = Dropout voltage
7.4 Thermal Information
REF35
DBV (SOT-23)
6 PINS
164.4
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
102.5
59.6
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
44.0
ΨJT
59.4
ΨJB
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
At VIN = VREF + 0.5 V, VEN = VIN, CL = 10 µF, CIN = 0.1 µF, IL = 0 mA, minimum and maximum specifications at TA = –40℃to
125℃, typical specifications TA = 25℃; unless otherwise noted
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
ACCURACY AND DRIFT
Output voltage accuracy
0.05
12
%
TA = 25℃
–0.05
Output voltage
temperature coefficient
–40℃≤TA ≤105℃
ppm/℃
LINE AND LOAD REGULATION
VREF < 2.5 V; VIN = VREF + VDO to VINMAX;–40℃
≤TA ≤105℃
40
160
120
ppm/V
ppm/V
ΔVREF
ΔVIN
/
Line regulation
Load regulation
V
REF ≥2.5 V; VIN = VREF + VDO to VINMAX;–40℃
40
20
40
≤TA ≤105℃
IL = 0 mA to 10 mA,
VIN = VREF + VDO
Source
Sink
60 ppm/mA
350 ppm/mA
ΔVREF
ΔIL
/
IL = 0 mA to 5 mA,
VIN = VREF + VDO
POWER SUPPLY
VIN
Input voltage (1)
VREF + VDO
6
0.9
1.3
2.6
0.1
0.5
V
0.65
TA = 25℃
Active mode
–40℃≤TA ≤85℃
–40℃≤TA ≤125℃
TA = 25℃
IQ
Quiescent current
µA
Shutdown mode
–40℃≤TA ≤125℃
Active mode (EN = 1 or Float)
Shutdown mode (EN = 0)
VEN = VIN
0.7 x VIN
VEN
IEN
Enable pin voltage
Enable pin current
Dropout voltage
V
0.3 x VIN
0.1
0.05
uA
mV
IL = 5 mA
120
VDO
IL = 10 mA
250
Short circuit current,
Sourcing
ISC
ISC
33
21
mA
mA
VREF = 0 V, TA = 25℃
VREF = VIN V, TA = 25℃
Short circuit current,
Sinking
TURN-ON TIME
tON
Turn-on time (2)
0.1% settling, CL = 1 µF, VREF = 2.5 V
2
ms
NOISE
en
Output voltage noise
Low-frequency noise
0.7
3.8
3.3
ppmrms
ppmp-p
ppmp-p
ƒ= 10 Hz to 1 kHz, CL = 1 µF
ƒ= 0.1 Hz to 10 Hz, VREF ≥2.5 V
ƒ= 0.1 Hz to 10 Hz, VREF < 2.5 V
enp-p
HYSTERESIS AND LONG-TERM STABILITY
Long-term stability
0 to 1000h at 35°C
40
70
ppm
ppm
Output voltage
hysteresis
25°C, –40°C, 105°C, 25°C (cycle 1)
25°C, –40°C, 105°C, 25°C (cycle 2)
25°C, –40°C, 85°C, 25°C (cycle 1)
25°C, –40°C, 85°C, 25°C (cycle 2)
Output voltage
hysteresis
20
50
13
ppm
ppm
ppm
Output voltage
hysteresis
Output voltage
hysteresis
STABLE CAPACITANCE RANGE
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At VIN = VREF + 0.5 V, VEN = VIN, CL = 10 µF, CIN = 0.1 µF, IL = 0 mA, minimum and maximum specifications at TA = –40℃to
125℃, typical specifications TA = 25℃; unless otherwise noted
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
Input capacitor range
0.1
µF
Output capacitor
range (3)
0.1
10
µF
(1) For VREF = 1.024 V to 1.5 V, minimum VIN = 1.7 V
(2) Scales linearly with VREF
(3) ESR for the capacitor <= 400 mΩ
.
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7.6 Typical Characteristics
at TA = 25°C, VIN = VEN = VREF + 0.3 V, IL = 0 mA, CL = 10 µF, CIN = 0.1 µF (unless otherwise noted)
1000
50
VREF = 5V
VREF = 2.5V
VREF = 1.25V
−40C to 85C
−40C to 105C
750
500
250
0
40
30
20
10
0
-250
-40
0
40
80
120
Temperature (C)
0
1
2
3
4
5
6
7
8
9
10 11
.
Temperature Coefficient (ppm/C)
图7-2. Temperature Coefficient Distribution (VREF = 1.25 V)
图7-1. Output Voltage Drift vs Free-Air Temperature
60
50
−40C to 85C
−40C to 105C
−40C to 85C
−40C to 105C
48
36
24
12
0
40
30
20
10
0
0
1
2
3
4
5
6
7
8
9
10 11
0
1
2
3
4
5
6
7
8
9
10 11
Temperature Coefficient (ppm/C)
图7-4. Temperature Coefficient Distribution (VREF = 5.0 V)
Temperature Coefficient (ppm/C)
图7-3. Temperature Coefficient Distribution (VREF = 2.5 V)
60
40
CL = 10uF
CL = 1uF
48
36
24
12
0
32
24
16
8
0
-0.05
-0.03
-0.01
Initial Accuracy (%)
图7-5. Initial Accuracy Distribution
0.01
0.03
0.05
1.2
2
2.8 3.6 4.4 5.2
6
6.8 7.6 8.4 9.2 10 10.8
Noise Bin (ppmp-p
)
图7-6. 0.1 Hz to 10 Hz Noise Distribution
(VREF = 1.25 V, CNR = Open, IL = 0 mA)
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7.6 Typical Characteristics (continued)
at TA = 25°C, VIN = VEN = VREF + 0.3 V, IL = 0 mA, CL = 10 µF, CIN = 0.1 µF (unless otherwise noted)
40
32
24
16
8
40
32
24
16
8
CL= 10uF
CL = 1uF
CL = 10uF
CL = 1uF
0
0
1.2
2
2.8 3.6 4.4 5.2
6
6.8 7.6 8.4 9.2 10 10.8
1.2
2
2.8 3.6 4.4 5.2
6
6.8 7.6 8.4 9.2 10 10.8
Noise Bin (ppmp-p
)
Noise Bin (ppmp-p)
图7-7. 0.1 Hz to 10 Hz Noise Distribution
图7-8. 0.1 Hz to 10 Hz Noise Distribution
(VREF = 2.5 V, CNR = Open, IL = 0 mA)
(VREF = 5 V, CNR = Open, IL = 0 mA)
40
32
24
16
8
80
CNR = Open
CNR = 1uF
CNR = 10uF
IL = 0mA
IL = 1mA
IL = 10mA
64
48
32
16
0
0
1.2
2
2.8 3.6 4.4 5.2
6
6.8 7.6 8.4 9.2 10 10.8
1.2
2
2.8 3.6 4.4 5.2
6
6.8 7.6 8.4 9.2 10 10.8
Noise Bin (ppmp-p
)
Noise Bin (ppmp-p)
图7-9. 0.1 Hz to 10 Hz Noise Distribution
(VREF = 2.5 V, CL = 1 μF, IL = 0 mA)
图7-10. 0.1 Hz to 10 Hz Noise Distribution
(VREF = 2.5 V, CL = 1 μF, CNR = Open)
750
600
450
300
150
0
1000
800
600
400
200
0
CL = 0.1F
CL = 0.1F
CL = 1F
CL = 1F
CL = 10F
CL = 10F
10
100
1000
Frequency (Hz)
10000
100000
10
100
1000
Frequency (Hz)
10000
100000
图7-12. Noise Density vs Frequency
图7-11. Noise Density vs Frequency
(VREF = 2.5 V, IL = 0 mA)
(VREF = 1.25 V, IL = 0 mA)
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7.6 Typical Characteristics (continued)
at TA = 25°C, VIN = VEN = VREF + 0.3 V, IL = 0 mA, CL = 10 µF, CIN = 0.1 µF (unless otherwise noted)
0
-2
-4
-6
-8
-10
-40
0
40
80
120
Temperature (C)
图7-13. Noise Density vs Frequency
图7-14. Load Regulation (Sourcing 10 mA) vs Free-Air
(VREF = 5 V, IL = 0 mA)
Temperature
75
60
45
30
15
0
IL = 1 mA
IL = -1 mA
VREF (50 mV/div)
Time (1 ms/div)
-40
0
40
80
120
Temperature (C)
图7-16. Load Transient Response
(VREF = 2.5 V, CL = 10 μF)
图7-15. Load Regulation (Sinking 5 mA) vs Free-Air
Temperature
IL = 10 mA
IL = 1 mA
IL = -5 mA
IL = -1 mA
VREF (400 mV/div)
VREF (100 mV/div)
Time (1 ms/div)
Time (1 ms/div)
图7-17. Load Transient Response
(VREF = 2.5 V, CL = 10 μF)
图7-18. Load Transient Response
(VREF = 2.5 V, CL = 1 μF)
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7.6 Typical Characteristics (continued)
at TA = 25°C, VIN = VEN = VREF + 0.3 V, IL = 0 mA, CL = 10 µF, CIN = 0.1 µF (unless otherwise noted)
IL = 1mA
IL = 10 mA
IL = -5 mA
IL = -1mA
VREF (600 mV/div)
VREF (90mV/div)
Time (1ms/div)
Time (1ms/div)
图7-19. Load Transient Response
(VREF = 2.5 V, CL = 1 μF)
图7-20. Load Transient Response
(VREF = 1.25 V, CL = 1 μF)
50
40
30
20
10
0
IL = 10 mA
IL = -5 mA
VREF (650 mV/div)
Time (1ms/div)
-40
0
40
80
120
Temperature (C)
图7-21. Load Transient Response
(VREF = 1.25 V, CL = 1 μF)
图7-22. Line Regulation vs Free-Air Temperature
VIN (4.3V/div)
VIN (3V/div)
IL = 0mA (100mV/div)
IL = 0mA (160mV/div)
IL = 1mA (160mV/div)
IL = 1mA (100mV/div)
Time (1ms/div)
Time (1ms/div)
图7-23. Line Transient Response
(VREF = 1.25 V, CL = 1 μF)
图7-24. Line Transient Response
(VREF = 2.5 V, CL = 1 μF)
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7.6 Typical Characteristics (continued)
at TA = 25°C, VIN = VEN = VREF + 0.3 V, IL = 0 mA, CL = 10 µF, CIN = 0.1 µF (unless otherwise noted)
10000
1000
100
10
120
90
60
30
0
CL = 0.1 F
CL = 1 F
CIN=0.1F, CL=1F
CL = 10 F
1
0.05
10
100
1000
10000 100000 1000000 1E+7
10
100
1000
10000 100000 1000000 1E+7
Frequency (Hz)
Frequency (Hz)
图7-26. Output Impedance
图7-25. Power Supply Rejection Ratio
(VREF = 2.5 V, IL = 0 mA)
2.5
2
1.5
1
0.5
0
-40
0
40
80
120
Temperature (C)
图7-28. Dropout Voltage vs Free-Air Temperature
200
图7-27. Quiescent Current vs Free-Air Temperature
60
160
120
80
48
36
24
12
0
40
0
-40
-80
-120
-160
-200
0
400
800
1200
1600
2000
-0.03
-0.02
-0.01
Solder Heat Shift %
图7-29. Solder Heat Shift Distribution
0
0.01
0.02
0.03
Time (hr)
图7-30. Long Term Stability - 2000 hours (VREF
)
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8 Parameter Measurement Information
8.1 Solder Heat Shift
The materials used in the manufacture of the REF35 have differing coefficients of thermal expansion, resulting in
stress on the device die when the part is heated. Mechanical and thermal stress on the device die can cause the
output voltages to shift, degrading the initial accuracy specifications of the product. Reflow soldering is a
common cause of this error.
To illustrate this effect, a total of 32 devices were soldered on one printed circuit board using lead-free solder
paste and the paste manufacturer suggested reflow profile. 图 8-1 shows the reflow profile. The printed circuit
board is comprised of FR4 material. The board thickness is 1.66 mm and the area is
174 mm × 135 mm.
300
250
200
150
100
50
0
0
50
100
150
200
250
300
350
400
Time (seconds)
C01
图8-1. Reflow Profile
The reference output voltage is measured before and after the reflow process; 图 8-2 shows the typical shift.
Although all tested units exhibit very low shifts (< 0.03%), higher shifts are also possible depending on the size,
thickness, and material of the printed circuit board (PCB). An important note is that the histograms display the
typical shift for exposure to a single reflow profile. Exposure to multiple reflows, as is common on PCBs with
surface-mount components on both sides, causes additional shifts in the output bias voltage. If the PCB is
exposed to multiple reflows, the device must be soldered in the last pass to minimize its exposure to thermal
stress.
60
48
36
24
12
0
-0.03
-0.02
-0.01
0
0.01
0.02
0.03
Solder Heat Shift %
图8-2. Solder Heat Shift Distribution, VREF (%)
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8.2 Temperature Coefficient
The REF35 is designed and tested for a low output voltage temperature coefficient. The temperature coefficient
is defined as the change in output voltage over temperature. The temperature coefficient is calculated using the
box method in which a box is formed by the minimum/maximum values for the nominal output voltage over the
operating temperature range. REF35 has a low maximum temperature coefficient of 12 ppm/°C from –40°C to
+105°C. The box method specifies limits for the temperature error but does not specify the exact shape and
slope of the device under test. Due to temperature curvature correction to achieve low-temperature drift, the
temperature drift is expected to be non-linear. See TI's Analog Design Journal, Precision voltage references, for
more information on the box method. Use 方程式1 for the box method.
≈
’
VREF(MAX) - VREF(MIN)
Drift =
ì106
∆
∆
«
÷
÷
◊
VREF(25èC) ìTemperature Range
(1)
图 8-3 shows a typical voltage versus temperature curves for various reference voltages. 图 8-4 shows the
distribution of temperature coefficients for REF35250 devices.
1000
60
VREF = 5V
VREF = 2.5V
VREF = 1.25V
−40C to 85C
−40C to 105C
750
500
250
0
48
36
24
12
0
-250
-40
0
40
80
120
Temperature (C)
0
1
2
3
4
5
6
7
8
9
10 11
Temperature Coefficient (ppm/C)
图8-3. Output Voltage Drift Vs Free-Air
图8-4. Temperature Coefficient Distribution
Temperature
8.3 Long-Term Stability
One of the key performance parameters of the REF35 references is long-term stability also known as long-term
drift. The long-term stability value is tested in a setup that reflects standard PCB board manufacturing practices.
The boards are made of standard FR4 material and the board does not have special cuts or grooves around the
devices to relieve the mechanical stress of the PCB. The devices and boards in this test do not undergo high
temperature burn in post-soldering prior to testing. These conditions reflect a real world use case scenario and
common manufacturing techniques.
During the long-term stability testing, precautions are taken to ensure that only the long-term stability drift is
measured. The boards are maintained at 35°C in an oil bath. The oil bath ensures that the temperature is
constant across the device over time compared to an air oven. The measurements are captured every 30
minutes with a calibrated 8.5 digit multimeter.
The typical long-term stability characteristic is expressed as a deviation of the reference voltage output over
time.
图 8-5 shows that the typical drift value for the REF35 6-pin SOT-23 package is 40 ppm from 0 to 1000 hours
and 55 ppm from 0 to 2000 hours. It is important to understand that long-term stability is not ensured by design
and that the value is typical. The REF35 will experience the highest drift in the initial 1000 hr. Subsequent
deviation is typically lower than first 1000 hr.
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200
160
120
80
40
0
-40
-80
-120
-160
-200
0
400
800
1200
1600
2000
Time (hr)
图8-5. Long Term Stability - 2000 hours (VREF
)
8.4 Thermal Hysteresis
Thermal hysteresis is measured with the REF35 soldered to a PCB, similar to a real-world application. Thermal
hysteresis for the device is defined as the change in output voltage after operating the device at 25°C, cycling
the device through the specified temperature range, and returning to 25°C. The PCB was baked at 150°C for 30
minutes before thermal hysteresis was measured. Use 方程式2 to calculate the thermal hysteresis:
≈
∆
«
’
÷
◊
| VPRE - VPOST
VNOM
|
VHYST
=
ì106 ppm
(
)
(2)
where
• VHYST = thermal hysteresis (in units of ppm)
• VNOM = the specified output voltage
• VPRE = output voltage measured at 25°C pre-temperature cycling
• VPOST = output voltage measured after the device has cycled from 25°C through the specified temperature
range of –40°C to +85°C or –40°C to +105°C and returns to 25°C.
The graphs below show the typical thermal hysteresis distribution across various temperature ranges in two
cycles.
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50
50
40
30
20
10
0
40
30
20
10
0
0
10
20
30
40
50
60
70
80
90
0
10
20
30
40
50
60
70
Thermal Hysteresis - Cycle 1 (ppm)
Thermal Hysteresis - Cycle 2 (ppm)
图8-6. Thermal Hysteresis Distribution
–40ºC to 85ºC, Cycle 1
图8-7. Thermal Hysteresis Distribution
–40ºC to 85ºC, Cycle 2
30
24
18
12
6
50
40
30
20
10
0
0
20 30 40 50 60 70 80 90 100 110 120 130
Thermal Hysteresis - Cycle 1 (ppm)
0
10
20
30
40
50
60
70
80
Thermal Hysteresis - Cycle 2 (ppm)
图8-8. Thermal Hysteresis Distribution
–40ºC to 105ºC, Cycle 1
图8-9. Thermal Hysteresis Distribution
–40ºC to 105ºC, Cycle 2
8.5 Noise Performance
The reference pin output noise is categorized as low frequency and broadband noise. The following sections
describe these categories in detail.
8.5.1 Low-Frequency (1/f) Noise
Flicker noise, also known as 1/f noise, is a low-frequency noise that affects the device output voltage which can
affect precision measurements in ADCs. This noise increases proportionally with output voltage and operating
temperature. Noise is measured by filtering the output from 0.1 Hz to 10 Hz. The 1/f noise is an extremely low
value, therefore the frequency of interest must be amplified and band-pass filtered. This is done by using a high-
pass filter to block the DC voltage. The resulting noise is then amplified by a gain of 1000. The bandpass filter is
created by a series of high-pass and low-pass filter that adds additional gain to make it more visible on a
oscilloscope as shown in 图8-10. 图8-11 shows the effect of flicker noise over 10 second for REF35250. Flicker
noise must be tested in a Faraday cage enclosure to block environmental noise.
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Supply
VIN
VREF
EN
CIN
Low Noise
Preamplifier
G = 1000
High-pass
Filter
Fc = 0.07Hz
Buffer
REF35xxx
CL
NR
GND
Optional
GND
2nd Order
Low-pass
Filter
2nd Order
High-pass
Filter
2nd Order
Low-pass
Filter
Oscilloscope
Fc = 10Hz
G = 1
Fc = 0.1Hz
G = 10
Fc = 10Hz
G = 10
图8-10. Low-Frequency (1/f) Noise Test Setup
GND
Time (1sec/div)
图8-11. 0.1 Hz to 10 Hz Voltage Noise
图 8-12 shows the typical 1/f noise (0.1 Hz to 10 Hz) distribution across various load conditions. REF35 device
also offers noise reduction functionality by adding an optional capacitor between NR (pin 5) and ground pins.
图8-13 shows the typical 1/f noise (0.1 Hz to 10 Hz) distribution across REF35 devices with various capacitance
between NR pin and GND.
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80
40
32
24
16
8
IL = 0mA
IL = 1mA
IL = 10mA
CNR = Open
CNR = 1uF
CNR = 10uF
64
48
32
16
0
0
1.2
2
2.8 3.6 4.4 5.2
6
6.8 7.6 8.4 9.2 10 10.8
1.2
2
2.8 3.6 4.4 5.2
6
6.8 7.6 8.4 9.2 10 10.8
Noise Bin (ppmp-p
)
Noise Bin (ppmp-p)
图8-12. 0.1 Hz to 10 Hz Noise Distribution vs Load 图8-13. 0.1 Hz to 10 Hz Noise Distribution vs NR
Conditions Capacitance
8.5.2 Broadband Noise
Broadband noise is a noise that appears at higher frequency compared to 1/f noise. The broadband noise is
measured by high-pass filtering the output of the reference device, followed by a gain stage and measuring the
result on a spectrum analyzer as shown in 图8-14.
Supply
VIN
VREF
High-pass
EN
CIN
Spectrum
Analyzer
Amplifier
G = 11
Filter
Fc = 10Hz
G = 11
REF35xxx
GND
CL
NR
Optional
GND
图8-14. Broadband Noise Test Setup
For noise sensitive designs, a low-pass filter can be used to reduce broadband output noise. When designing a
low-pass filter, take special care to ensure the output impedance of the filter does not degrade AC performance.
This can occur in RC low-pass filters where a large series resistance can impact the load transients due to
output current fluctuations. The REF35 device also offers noise reduction functionality by adding an optional
capacitor between NR (pin 5) and ground pins. 图8-15 and 图8-16 show the noise spectrum for REF35250 and
REF35500 devices respectively across various load capacitance.
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1000
CL = 0.1F
CL = 1F
CL = 10F
800
600
400
200
0
10
100
1000
10000
100000
Frequency (Hz)
图8-15. Noise Spectrum 10 Hz to 100 kHz (VREF = 图8-16. Noise Spectrum 10 Hz to 100 kHz (VREF = 5
2.5 V) V)
8.6 Power Dissipation
The REF35 voltage references are capable of source up to 10 mA and sink up to 5 mA of load current across the
rated input voltage range. However, when used in applications subject to high ambient temperatures, the input
voltage and load current must be carefully monitored to ensure that the device does not exceeded its maximum
power dissipation rating. The maximum power dissipation of the device can be calculated with 方程式3:
TJ = TA +P ì RqJA
D
(3)
where
• PD is the device power dissipation
• TJ is the device junction temperature
• TA is the ambient temperature
• RθJA is the package (junction-to-air) thermal resistance
Because of this relationship, acceptable load current in high temperature conditions may be less than the
maximum current-sourcing capability of the device. In no case should the device be operated outside of its
maximum power rating because doing so can result in premature failure or permanent damage to the device.
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9 Detailed Description
9.1 Overview
The REF35 is family of ultra-low current, low-noise, precision band-gap voltage references that are specifically
designed for excellent initial voltage accuracy and drift. The Functional Block Diagram is a simplified block
diagram of the REF35 showing basic band-gap topology.
9.2 Functional Block Diagram
VIN
VIN
Rp
EN
Digital
Core
EN
Control
Rp for
Open Drain
EN control
R
Band-Gap
Core
Buffer
VREF
GND
NR
9.3 Feature Description
9.3.1 Supply Voltage
The REF35 family of references features an extremely low dropout voltage. For 10 mA loaded conditions, a
maximum dropout voltage is 250 mV. 图 7-28 shows a typical dropout voltage (VDO) versus load current. The
device supports operation with input voltage range from VREF + VDO to 6 V. The typical quiescent current is 650
nA and maximum quiescent current over temperature is only 2.6 μA. The low dropout voltage coupled with
ultra-low current enable the operation across multiple battery powered applications.
9.3.2 EN Pin
The REF35 family supports device enable and disable functionality through logic level control on EN pin. The EN
pin of REF35 does not use an internal pull-up resistor. Instead, the pin uses new 'clean EN' technology. This
allows the EN pin to be in a no connect condition at start-up, and no extra current is drawn from the supply when
the EN pin is pulled low in shutdown mode. When EN pin is pulled high or left unconnected at start-up, the
device is in active mode. When EN pin is driven by an open-drain output, a pull-up resistor to VIN is required.
The device must be in active mode for normal operation. The EN pin must not be pulled higher than VIN supply
voltage.
The device can be placed in shutdown mode by pulling the EN pin low. When in shutdown mode, the output of
the device becomes high impedance and the quiescent current of the device drops to 100 nA at room
temperature. When changing the device state from shutdown to active state, ensure the EN pin is not left
floating.
Also note that for applications where EN pin is no-connect, total parasitic capacitance on EN pin should be
restricted within 30 pF.
See the Electrical Characteristics table for logic high and logic low voltage levels.
9.3.3 NR Pin
The REF35 pin allows access to the band-gap through the NR pin. Placing a capacitor from the NR pin to GND
creates a low-pass filter in combination with the internal resistance of 60 kΩ. Leakage of the capacitance directly
impacts the accuracy and temperature drift. If NR functionality is used, choose a low leakage capacitor. A
capacitance of 1 μF creates a low-pass filter with corner frequency around 2.7 Hz. Such a filter decreases the
overall noise on the VREF pin. Higher capacitance results in a lower filter cut off frequency, further reducing
output noise. Please note, using the capacitor on NR pin also increases start-up time.
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9.4 Device Functional Modes
9.4.1 Basic Connections
图 9-1 shows the typical connections for the REF35. TI recommends a supply bypass capacitor (CIN) ranging
from 0.1 μF to 10 μF. A 0.1 μF to 10 μF output capacitor (CL) must be connected from REF to GND. The
equivalent series resistance (ESR) value of CL must be lower than 400 mΩ to ensure output stability.
EN
AVDD
REF
CL
VIN
REF35
VREF
NR
CIN
GND
GND
Optional
GND
GND
GND
图9-1. Basic Connections
9.4.2 Start-Up
图 9-2 shows the start-up behavior of REF35250 device with 1 μF load capacitance. REF35 device ensures the
output voltage settles to the expected output voltage within specified accuracy without oscillations. The start-up
time is dependent on the output voltage variant, output capacitance and NR pin capacitance. Higher capacitance
leads to longer start-up time.
VIN (1.5V/div)
VREF (1.25V/div)
Time (5 ms/div)
图9-2. REF35250 Start-Up Behavior, CL = 1 μF
9.4.3 Output Transient Behavior
The REF35 output buffer is capable of sourcing 10 mA load current as well as sink 5 mA of load current. The
output stage is designed using class AB architecture with ultra-low quiescent current. This architecture avoids
the dead zone around the no load condition. The output buffer uses a fast start-up implementation to achieve
2ms typical turn-on time at CL = 1 μF and no-load current condition.
图9-3 and 图9-4 show the output settling behavior for light load transient and high load transient respectively.
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IL = 100A
IL = 10mA
IL = 0A
IL = 1mA
VREF (10mV/div)
VREF (75mV/div)
Time (1ms/div)
Time (1ms/div)
图9-4. Load Transient Response 1 mA to 10 mA,
CL = 1 μF
图9-3. Load Transient Response 0 μA to 100 μA,
CL = 1 μF
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10 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
10.1 Application Information
REF35 with low current consumption and class leading performance specifications is suitable reference for
multiple applications. The device can also be used as a precision low noise power supply to sensor or data
converter instead of traditional LDO or DC/DC based power supply. Basic applications includes positive/negative
voltage reference and data acquisition systems. The table below shows the typical application of REF35 and its
companion ADC/DAC.
表10-1. Typical Applications and Companion ADC/DAC
APPLICATIONS
ADC/DAC
ADS7028, DAC8881, ADS1287, ADS7953
ADS7028, ADS7128, ADS7138
ADS124S08
PLC - DCS
Rack Server
Field Transmitters - Pressure, Flow
Optical Module, Optical Line Card
Medical Blood Glucose Meter
Power quality analyzer
ADS7068, ADS7138
ADS1112
ADC3662
Thermal imaging
ADC3541
10.2 Typical Applications
10.2.1 Negative Reference Voltage
For applications requiring a negative and positive reference voltage, the REF35 and OPA735 can be used to
provide a dual-supply reference from a 5 V supply. 图 10-1 shows the REF35250 used to provide a 2.5 V supply
reference voltage. The low drift performance of the REF35250 complements the low offset voltage and zero drift
of the OPA735 to provide an accurate solution for split-supply applications. Take care to match the temperature
coefficients of R1 and R2.
+5 V
4
3
5
REF35250
+2.5 V
6
1
2
R2
10 k
+5 V
-
OPA735
+
-2.5 V
-5 V
GND
图10-1. REF35 and OPA735 Create Positive and Negative Reference Voltages
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10.2.2 Precision Power Supply and Reference
图 10-2 shows the basic configuration for the REF35 device as precision power supply to ADS7038 data
converter which uses its power supply AVDD as reference. Connect bypass capacitors according to the
guidelines in the Input and Output Capacitors section.
+6 V
0.1 μF
1 μF
4
REF35500
6
3
1
2
5
GND
10 μF
0.1 μF
AVDD
ADS7038
-
Input
+
0 V to 5 V
GND
GND
图10-2. Basic Reference Connection
10.2.2.1 Design Requirements
A detailed design procedure is described based on a design example. For this design example, use the
parameters listed in 表10-2 as the input parameters.
表10-2. Design Example Parameters
DESIGN PARAMETER
VALUE
0 V - 5 V
12-bit
Input voltage range VIN
Output resolution
REF35 input capacitor
REF35 output capacitor
1 µF
10 µF
10.2.2.2 Detailed Design Procedure
10.2.2.2.1 Selection of Reference
The REF35500 reference is selected for this design. The REF35500 device operates of very low quiescent
current while offering ±0.05% initial accuracy and very low noise. These parameters help improve system
accuracy as compared to external LDO based power supply. The 5 V reference voltage supports the 0 V to 5 V
input range specification.
10.2.2.2.2 Input and Output Capacitors
A 1 μF to 10 μF electrolytic or ceramic capacitor can be connected to the input to improve transient response
in applications where the supply voltage may fluctuate.
A ceramic capacitor of at least a 0.1 μF must be connected to the output to improve stability and help filter out
high frequency noise. Add an additional 10 μF capacitor in parallel to improve transient performance in
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response to sudden changes in load current; however, keep in mind that doing so increases the start-up time of
the device.
Best performance and stability is attained with low-ESR, low-inductance ceramic chip-type output capacitors
(X5R, X7R, or similar). If using an electrolytic capacitor on the output, place a 0.1 μF ceramic capacitor in
parallel to reduce overall ESR on the output. Place the input and output capacitors as close as possible to the
device.
10.2.2.2.3 Selection of ADC
ADS7038 12-bit 8 channel multiplexed ADC is chosen for this application. The ADC offers low current operation
with averaging mode to increase the resolution to 16-bit with internal averaging modes while operating with slow
sampling speed.
10.2.2.3 Application Curves
表 10-3 and 图 10-3 show the captured measurement results for various DC inputs. The ADC output is captured
and analyzed for output accuracy error and code spread with REF35500 as power supply versus LDO as power
supply.
REF35 offers better accuracy and lower noise than the LDO device at lower quiescent current. This results in
lower error in measurement as well as lower ADC output code variation across various OSR settings.
表10-3. DC Input Performance Test Results
REF35500
LDO
INPUT V
ADC OSR SETTING
ERROR
0.01 mV
0.3 mV
CODE SPREAD
ERROR
8.9 mV
CODE SPREAD
48 LSB
16 LSB
6 LSB
1.0 V
0
8
32 LSB
10 LSB
6 LSB
9.21 mV
9.26 mV
22.89 mV
23.63 mV
23.41 mV
37.84 mV
38.62 mV
38.09 mV
128
0
0.38 mV
0.69 mV
1.44 mV
1.17 mV
2.27 mV
3.01 mV
2.46 mV
2.5 V
4 V
32 LSB
10 LSB
3 LSB
64 LSB
18 LSB
5 LSB
8
128
0
32 LSB
24 LSB
3 LSB
48 LSB
24 LSB
17 LSB
8
128
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50
40
30
20
10
0
REF35-OSR0
REF35-OSR8
REF35-OSR128
LDO-OSR0
LDO-OSR8
LDO-OSR128
0
1
2
3
4
5
Input voltage (V)
图10-3. Error vs Input Voltage
10.3 Power Supply Recommendations
The REF35 family of references feature an extremely low-dropout voltage. These references can be operated
with a supply of only 50 mV above the output voltage at no load. TI recommends a supply bypass capacitor
ranging between 0.1 µF to 10 µF.
10.4 Layout
10.4.1 Layout Guidelines
图 10-4 shows an example of a PCB layout for a data acquisition system using the REF35. Some key
considerations are:
• Connect low-ESR, 0.1 μF ceramic bypass capacitors at VIN, VREF of the REF35.
• Decouple other active devices in the system per the device specifications.
• Using a solid ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise
pickup.
• Place the external components as close to the device as possible.
• Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when absolutely necessary.
图 10-5 shows the pin compatibility with TI REF30xx, REF31xx and REF33xx series references in the 3-pin
SOT-23 package when using the REF35xxx family footprint. You must rotate the REF30xx, REF31xx and
REF33xx reference devices by 180º before assembly.
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10.4.2 Layout Examples
C
C
GND
GND
EN
1
VREF
NR
GND
GND (Pin 3) GND
EN
1
VREF OUT (Pin 2)
6
5
4
6
5
4
REF35
REF30
REF31
REF33
NR
2
3
2
3
VIN
VIN
IN (Pin 1)
C Optional
C Optional
C
C
Not to scale
Not to scale
图10-4. Layout Example
图10-5. Pin Compatibility With REF30xx, REF31xx
and REF33xx
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, INA21x Voltage Output, Low- or High-Side Measurement, Bidirectional, Zero-Drift Series,
Current-Shunt Monitors data sheet
• Texas Instruments, Low-Drift Bidirectional Single-Supply Low-Side Current Sensing Reference Design
• Texas Instruments, Precision voltage references Analog Design Journal
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
27
Product Folder Links: REF35
PACKAGE OPTION ADDENDUM
www.ti.com
19-May-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PREF35180YBHR
REF35102QDBVR
REF35120QDBVR
REF35125QDBVR
REF35160QDBVR
REF35170QDBVR
REF35180QDBVR
REF35205QDBVR
REF35250QDBVR
REF35300QDBVR
REF35330QDBVR
REF35360QDBVR
REF35409QDBVR
REF35500QDBVR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DSBGA
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
YBH
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
4
6
6
6
6
6
6
6
6
6
6
6
6
6
3000
TBD
Call TI
Call TI
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
2RTI
2RVI
2RUI
2UII
31QI
2J2I
2UKI
2RSI
2SLI
2ULI
31RI
2UMI
2RWI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
19-May-2023
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Mar-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
REF35102QDBVR
REF35120QDBVR
REF35125QDBVR
REF35160QDBVR
REF35170QDBVR
REF35180QDBVR
REF35205QDBVR
REF35250QDBVR
REF35300QDBVR
REF35330QDBVR
REF35360QDBVR
REF35409QDBVR
REF35500QDBVR
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
6
6
6
6
6
6
6
6
6
6
6
6
6
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
3.23
3.23
3.23
3.23
3.23
3.23
3.23
3.23
3.23
3.23
3.23
3.23
3.23
3.17
3.17
3.17
3.17
3.17
3.17
3.17
3.17
3.17
3.17
3.17
3.17
3.17
1.37
1.37
1.37
1.37
1.37
1.37
1.37
1.37
1.37
1.37
1.37
1.37
1.37
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Mar-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
REF35102QDBVR
REF35120QDBVR
REF35125QDBVR
REF35160QDBVR
REF35170QDBVR
REF35180QDBVR
REF35205QDBVR
REF35250QDBVR
REF35300QDBVR
REF35330QDBVR
REF35360QDBVR
REF35409QDBVR
REF35500QDBVR
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
6
6
6
6
6
6
6
6
6
6
6
6
6
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
213.0
213.0
213.0
213.0
213.0
213.0
213.0
213.0
213.0
213.0
213.0
213.0
213.0
191.0
191.0
191.0
191.0
191.0
191.0
191.0
191.0
191.0
191.0
191.0
191.0
191.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
B
1.45 MAX
A
PIN 1
INDEX AREA
1
2
6
5
2X 0.95
1.9
3.05
2.75
4
3
0.50
6X
0.25
C A B
0.15
0.00
0.2
(1.1)
TYP
0.25
GAGE PLANE
0.22
0.08
TYP
8
TYP
0
0.6
0.3
TYP
SEATING PLANE
4214840/C 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214840/C 06/2021
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/C 06/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
YBH0004
DSBGA - 0.4 mm max height
SCALE 12.000
DIE SIZE BALL GRID ARRAY
A
D
B
E
BALL A1
CORNER
C
0.4 MAX
SEATING PLANE
0.05 C
0.16
0.10
BALL TYP
0.4
TYP
B
SYMM
0.4
TYP
A
1
2
0.225
0.185
4X
0.015
SYMM
C A B
4224051/A 11/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YBH0004
DSBGA - 0.4 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
4X ( 0.2)
2
1
A
B
SYMM
(0.4) TYP
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 50X
0.05 MIN
0.05 MAX
METAL UNDER
SOLDER MASK
(
0.2)
METAL
(
0.2)
EXPOSED
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
(PREFERRED)
NON-SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4224051/A 11/2017
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YBH0004
DSBGA - 0.4 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
(R0.05) TYP
4X ( 0.21)
1
2
A
B
SYMM
(0.4) TYP
METAL
TYP
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.075 mm THICK STENCIL
SCALE: 50X
4224051/A 11/2017
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
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