REF7012 [TI]
REF70 2 ppm/°C Maximum Drift, 0.23 ppmp-p 1/f Noise, Precision Voltage Reference;型号: | REF7012 |
厂家: | TEXAS INSTRUMENTS |
描述: | REF70 2 ppm/°C Maximum Drift, 0.23 ppmp-p 1/f Noise, Precision Voltage Reference |
文件: | 总40页 (文件大小:2646K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
REF70
SNAS781D – OCTOBER 2020 – REVISED DECEMBER 2021
REF70 2 ppm/°C Maximum Drift, 0.23 ppmp-p 1/f Noise, Precision Voltage Reference
1 Features
3 Description
•
Low noise enables precision measurements:
– 1/f Noise (0.1 Hz to 10 Hz): 0.23 ppmp-p
– 10 Hz to 1 kHz: 0.35 ppmrms
Low temperature drift coefficient:
– 2 ppm/°C maximum (-40°C to 125°C)
High accuracy: ±0.025% maximum
Humidity resistant hermetic ceramic package
(LCCC)
Low long-term stability (1k hr): 28 ppm
Low dropout: 400 mV
Designed for a wide range of applications:
– Wide input voltage up to 18 V
– Output current: ±10 mA
The REF70 is a family of high precision series voltage
references that offers the industry’s lowest noise
(0.23 ppmp-p), very low temperature drift coefficient
(2 ppm/°C), and high accuracy (±0.025%). The
REF70 offers a high PSRR, low drop-out voltage
and excellent load and line regulation to help meet
strict transient requirements. This combination of
precision and features is designed for applications
such as test and measurement that demand a precise
reference to be paired with precision, high-resolution
data converters such as ADS8900B, ADS127L01 and
DAC11001A, to achieve optimal performance in the
signal chain. The REF70 is also designed for noise-
sensitive medical applications such as ultrasound and
X-ray to help enable low-noise measurements from
the analog front end.
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•
•
•
•
•
– Voltage options: 1.25 V, 2.5 V, 3 V, 3.3 V, 4.096
V, 5 V
Ultra-flexible solution:
•
– Stable with 1-μF to 100-μF output low-ESR
capacitor
– High PSRR: 107 dB at 1 kHz
– Operating temperature range: −40°C to +125°C
The REF70 family is available in VSSOP and LCCC
package options. The LCCC (FKH) package is a
hermetically sealed ceramic package that allows for
low, long-term drift for applications that require a
stable reference over a long time period without
calibration.
2 Applications
•
•
•
•
•
•
•
•
•
Semiconductor test equipment
Precision data acquisition systems
Precision weight scales
Ultrasound scanner
The REF70 is specified for the wide temperature
range of −40°C to +125°C. The wide temperature
range enables operation across various industrial
applications.
X-ray systems
Industrial instrumentation
PLC analog I/O modules
Field transmitters
Device Information
PART NAME
REF70
PACKAGE (1)
BODY SIZE (NOM)
5.00 mm × 5.00 mm
3.00 mm x 3.00 mm
LCCC (8)
VSSOP (8)
Power monitoring
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2.501
2.50075
2.5005
2.50025
2.5
0.64
0.56
0.48
0.4
0.32
0.24
0.16
0.08
0
2.49975
2.4995
2.49925
2.499
-50
-25
0
25 50
Temperature (°C)
75
100
125
Noise (ppmp-p
)
Output Voltage Vs Free-Air-Temperature
0.1-Hz to 10-Hz Voltage Noise Distribution
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
REF70
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SNAS781D – OCTOBER 2020 – REVISED DECEMBER 2021
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................4
6 Pin Configuration and Functions...................................5
7 Specifications.................................................................. 6
7.1 Absolute Maximum Ratings........................................ 6
7.2 ESD Ratings............................................................... 6
7.3 Recommended Operating Conditions.........................6
7.4 Thermal Information....................................................6
7.5 REF7012 Electrical Characteristics............................ 7
7.6 REF7025 Electrical Characteristics............................ 8
7.7 REF7030 Electrical Characteristics............................ 9
7.8 REF7033 Electrical Characteristics.......................... 10
7.9 REF7040 Electrical Characteristics...........................11
7.10 REF7050 Electrical Characteristics........................ 12
7.11 Typical Characteristics............................................ 13
8 Parameter Measurement Information..........................17
8.1 Solder Heat Shift.......................................................17
8.2 Long-Term Stability................................................... 18
8.3 Thermal Hysteresis...................................................18
8.4 Noise Performance................................................... 19
8.5 Temperature Drift...................................................... 21
8.6 Power Dissipation..................................................... 21
9 Detailed Description......................................................23
9.1 Overview...................................................................23
9.2 Functional Block Diagram.........................................23
9.3 Feature Description...................................................23
9.4 Device Functional Modes..........................................23
10 Application and Implementation................................25
10.1 Application Information........................................... 25
10.2 Typical Applications................................................ 25
11 Power Supply Recommendation................................30
12 Layout...........................................................................31
12.1 Layout Guidelines................................................... 31
12.2 Layout Example...................................................... 31
13 Device and Documentation Support..........................32
13.1 Documentation Support.......................................... 32
13.2 Receiving Notification of Documentation Updates..32
13.3 Support Resources................................................. 32
13.4 Trademarks.............................................................32
13.5 Electrostatic Discharge Caution..............................32
13.6 Glossary..................................................................32
14 Mechanical, Packaging, and Orderable
Information.................................................................... 32
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (September 2021) to Revision D (November 2021)
Page
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•
•
•
•
•
•
Changed REF7012 status from Preproduction device to Released device........................................................4
Changed REF7012 status to Released Device. Updated specifications to meet production release device.....7
Added REF7030 Electrical Characteristics table................................................................................................9
Added REF7033 Electrical Characteritics table................................................................................................10
Added REF7012 Thermal Hysteresis figure..................................................................................................... 13
Added JEDEC standard details to follow for solder reflow profiles. Updated solder shift histogram plot......... 17
Added Thermal Hysteresis plots for REF7012 device .....................................................................................18
Changes from Revision B (April 2021) to Revision C (September 2021)
Page
•
•
Add 1.25 V variant to Features on page1...........................................................................................................1
In the Device Comparison Table, added the 1.25V variant and added foot notes to indicate which devices are
released vs pre-production ................................................................................................................................ 4
Changed Dropout voltage to min VIN = 2.75 V for VOUT < 2.5 V. .................................................................... 6
Added Electrical Characteristics table for REF7012 (Product Preview)............................................................. 7
Changed VINMIN from 3 V to VOUT + VDO ...........................................................................................................8
Added Electrical Characteristics table for REF7040 (Product Preview)............................................................11
Added Electrical Characteristics table for REF7050 (Product Preview)........................................................... 12
Added to the notes above the Typical Characteristics plots, Vref = 2.5 V to the default conditions................. 13
Under Temperature Drift section of the Parameter Measurement Information, corrected the figure from Long
Term Drift plot to Temperature Drift...................................................................................................................21
•
•
•
•
•
•
•
Changes from Revision A (December 2020) to Revision B (April 2021)
Changed REF7025 to more general REF70 series in heading and device information. Added ADC companion
products..............................................................................................................................................................1
Page
•
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SNAS781D – OCTOBER 2020 – REVISED DECEMBER 2021
•
•
•
•
•
•
•
•
•
•
Changed Figures 7-2 and 7-20, Long-Term Stability (First 1000 Hours), to longer duration (2000 hours).......13
Corrected typical shift from 0.021% to 0.009%.................................................................................................17
Changed Figure 8-3, Long-Term Stability LCCC -1000 hours), to longer duration (2000 hours)..................... 18
Corrected Figure 8-5, Thermal Hysteresis Distribution Cycle 2 (-40°C to 125°C), data and title..................... 18
Reordered figures and paragraphs for better flow............................................................................................ 20
Changed VREF to VREF(25°C) in Equation 2........................................................................................................21
Added missing supply bypass capacitor value (10-μF).................................................................................... 23
Clarified piezoelectric contribution to noise and added links to resources....................................................... 26
Added clarification on how to connect OUTF and OUTS in specific load current condition............................. 27
Corrected part numbers and added links in Table 10-2, Reference Op Amp Options .....................................28
Changes from Revision * (October 2020) to Revision A (December 2020)
Page
•
APL to RTM release............................................................................................................................................1
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SNAS781D – OCTOBER 2020 – REVISED DECEMBER 2021
5 Device Comparison Table
PRODUCT (2)
REF7012 (1)
REF7025 (1)
REF7030
VOUT
1.25 V
2.5 V
3.0 V
REF7033
3.3 V
REF7040
4.096 V
5.0 V
REF7050
(1) Released device - REF7012, REF7025.
(2) Preproduction device - REF7030, REF7033, REF7040, REF7050.
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SNAS781D – OCTOBER 2020 – REVISED DECEMBER 2021
6 Pin Configuration and Functions
GND
8
OUTF
1
2
3
7
6
5
EN
VIN
OUTS
GND
GND
4
GND
Figure 6-1. FKH Package
8-Pin LCCC
Top View
GND
1
2
8
7
EN
VIN
OUTF
3
4
6
5
GND
GND
OUTS
GND
Figure 6-2. DGK Package
8-Pin VSSOP
Top View
Table 6-1. Pin Functions
PIN
FKH
TYPE
DESCRIPTION
NAME
DGK
Device enable control. Low level input disables the reference output
and device enters shutdown mode. Device can be enabled by
driving voltage > 1.6V. If the pin is left floating, the internal pull up
will enable the device.
EN
1
1
Input
Input supply voltage connection. Connect a minimum 0.1-μF
decoupling capacitor to ground for the best performance.
VIN
2
2
Power
GND
GND
GND
OUTS
3
4
5
6
3
4
5
6
Ground
Ground
Ground
Input
Ground connection.
Ground connection.
Ground connection
Reference voltage output sense connection.
Reference voltage output force connection. Connect a output
capacitor between 1-μF to 100-μF for the best performance.
OUTF
GND
7
8
7
8
Output
Ground
Ground connection.
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SNAS781D – OCTOBER 2020 – REVISED DECEMBER 2021
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
-0.3
-0.3
-0.3
MAX
UNIT
V
Input voltage
VIN
EN
20
VIN + 0.3
6
Enable voltage
V
Output voltage
VOUT
ISC
V
Output short circuit current
Operating temperature range
Storage temperature range
25
mA
°C
°C
TA
-55
-65
150
Tstg
170
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied. These are stress ratings only and functional operation of the device at these or any other conditions
beyond those specified in the Electrical Characteristics Table is not implied.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001,
all pins(1)
± 1000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins(2)
± 500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX UNIT
(1)
VIN
EN
IL
Input voltage
VOUT + VDO
18
VIN
10
V
V
Enable voltage
Output current
0
–10
–40
mA
°C
TA
Operating temperature
25
125
(1) VDO = Dropout voltage. For VOUT < 2.5 V minimum VIN = 2.75 V
7.4 Thermal Information
REF70xx
THERMAL METRIC(1)
FKH (CERAMIC)
DGK (MSOP)
8 PINS
201.2
UNIT
8 PINS
95.8
59.0
58.3
48.2
58.1
28.5
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
85.7
122.9
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
21.2
ΨJB
121.4
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SNAS781D – OCTOBER 2020 – REVISED DECEMBER 2021
7.5 REF7012 Electrical Characteristics
Specifications are tested at TA = 25°C, IL = 0 mA, CIN = 0.1 µF, COUT = 10 µF, VIN = 3 V, OUTS connected to OUTF, unless
otherwise noted
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
ACCURACY AND DRIFT
Output voltage accuracy TA = 25°C
–0.025
0.025
2
%
Output voltage
–40°C ≤ TA ≤ 125°C
ppm/℃
temperature coefficient
LINE AND LOAD REGULATION
2.7 V ≤ VIN ≤ 18 V
4
5
ΔVO / ΔVIN Line regulation
ppm/V
2.7 V ≤ VIN ≤ 18 V, –40°C ≤ TA ≤ 125°C
IL = 0 mA to 10mA, VIN = 3 V
30
15
IL = 0 mA to 10mA, VIN = 3 V, –40°C ≤ TA ≤ 125°C
IL = 0 mA to –10mA, VIN = 3 V
ΔVO / ΔIL
Load regulation
ppm/mA
15
IL = 0 mA to –10mA, VIN = 3 V,
–40°C ≤ TA ≤ 125°C
30
NOISE
enp-p
en
Low frequency noise
Output voltage noise
ƒ = 0.1 Hz to 10 Hz
ƒ = 10 Hz to 1 kHz
0.25
0.35
ppmp-p
ppmrms
HYSTERESIS AND LONG-TERM STABILITY
0 to 250h at 35°C –FKH package
15
35
18
11
11
Long-term stability
ppm
ppm
0 to 1000h at 35°C – FKH package
25°C, –40°C, 125°C, 25°C – FKH package
25°C, –40°C, 85°C, 25°C – FKH package
25°C, 0°C, 70°C, 25°C – FKH package
Output voltage
hysteresis
TURN ON TIME
tON Turn-on time
CAPACITIVE LOAD
0.1% settling, COUT = 1µF
0.5
ms
Stable input capacitor
range
CIN
–40℃ ≤ TA ≤ 125℃
–40℃ ≤ TA ≤ 125℃
0.1
1
µF
µF
Stable output capacitor
range (1)
COUT
100
POWER SUPPLY
VIN Input voltage
2.75
18
6.5
7.5
10
V
mA
mA
uA
uA
V
TA = 25°C
4
5
Active mode
–40°C ≤ TA ≤ 125°C
IQ
Quiescent current
Enable pin voltage
TA = 25°C
Shutdown mode
–40°C ≤ TA ≤ 125°C
12
Active mode (EN=1)
Shutdown mode (EN=0)
VIN = VEN = 18V
1.6
VEN
0.5
4
V
3.2
30
uA
uA
mA
IEN
ISC
Enable pin current
Short circuit current
VIN = VEN = 18V, –40°C ≤ TA ≤ 125°C
VOUT = 0V
5
(1) ESR for the capacitor can range from 10mΩ to 400mΩ
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7.6 REF7025 Electrical Characteristics
Specifications are tested at TA = 25°C, IL = 0 mA, CIN = 0.1 µF, COUT = 10 µF, VIN = VOUT + 0.5V, OUTS connected to OUTF,
unless otherwise noted
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
ACCURACY AND DRIFT
Output voltage accuracy TA = 25°C
–0.025
0.025
2
%
Output voltage
–40°C ≤ TA ≤ 125°C
ppm/℃
temperature coefficient
LINE AND LOAD REGULATION
VOUT + VDO ≤ VIN ≤ 18 V
4
5
ΔVO / ΔVIN Line regulation
ppm/V
VOUT + VDO ≤ VIN ≤ 18 V, –40°C ≤ TA ≤ 125°C
IL = 0 mA to 10mA, VIN = VOUT + VDO
30
10
IL = 0 mA to 10mA, VIN = VOUT + VDO, –40°C ≤
TA ≤ 125°C
ΔVO / ΔIL
Load regulation
ppm/mA
IL = 0 mA to –10mA, VIN = VOUT + VDO
5
IL = 0 mA to –10mA, VIN = VOUT + VDO, –40°C ≤
TA ≤ 125°C
15
NOISE
enp-p
en
Low frequency noise
Output voltage noise
ƒ = 0.1 Hz to 10 Hz
ƒ = 10 Hz to 1 kHz
0.23
0.35
ppmp-p
ppmrms
HYSTERESIS AND LONG-TERM STABILITY
0 to 250h at 35°C - FKH package
10
28
Long-term stability
ppm
ppm
0 to 1000h at 35°C - FKH package
25°C, –40°C, 125°C, 25°C – FKH package
25°C, –40°C, 85°C, 25°C – FKH package
25°C, 0°C, 70°C, 25°C – FKH package
180
100
40
Output voltage
hysteresis
TURN ON TIME
tON Turn-on time
CAPACITIVE LOAD
0.1% settling, COUT = 1µF
0.5
ms
Stable input capacitor
range
CIN
–40℃ ≤ TA ≤ 125℃
–40℃ ≤ TA ≤ 125℃
0.1
1
µF
µF
Stable output capacitor
range (1)
COUT
100
18
POWER SUPPLY
VIN Input voltage
VOUT
+
V
VDO
TA = 25°C
4
5
6
6.5
10
mA
mA
uA
uA
V
Active mode
–40°C ≤ TA ≤ 125°C
IQ
Quiescent current
TA = 25°C
Shutdown mode
–40°C ≤ TA ≤ 125°C
12
Active mode (EN=1)
1.6
VEN
Enable pin voltage
Enable pin current
Shutdown mode (EN=0)
VIN = VEN = 18V
0.5
4
V
3.2
25
uA
uA
mV
mV
mA
IEN
VIN = VEN = 18V, –40°C ≤ TA ≤ 125°C
IL = 5mA, –40°C ≤ TA ≤ 125°C
IL = 10mA, –40°C ≤ TA ≤ 125°C
VOUT = 0V
5
250
400
VDO
ISC
Dropout voltage
Short circuit current
(1) ESR for the capacitor can range from 10mΩ to 400mΩ
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7.7 REF7030 Electrical Characteristics
Specifications are tested at TA = 25°C, IL = 0 mA, CIN = 0.1 µF, COUT = 10 µF, VIN = VOUT + 0.5V, OUTS connected to OUTF,
unless otherwise noted
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
ACCURACY AND DRIFT
Output voltage accuracy TA = 25°C
–0.025
0.025
2
%
Output voltage
–40°C ≤ TA ≤ 125°C
ppm/℃
temperature coefficient
LINE AND LOAD REGULATION
3.2 V ≤ VIN ≤ 18 V
4
5
ΔVO / ΔVIN Line regulation
ppm/V
3.2 V ≤ VIN ≤ 18 V, –40°C ≤ TA ≤ 125°C
IL = 0 mA to 10mA, VIN = 3.5 V
30
10
IL = 0 mA to 10mA, VIN = 3.5 V, –40°C ≤ TA ≤
125°C
ΔVO / ΔIL
Load regulation
ppm/mA
IL = 0 mA to –10mA, VIN = 3.5 V
5
IL = 0 mA to –10mA, VIN = 3.5 V, –40°C ≤ TA ≤
125°C
15
NOISE
enp-p
en
Low frequency noise
Output voltage noise
ƒ = 0.1 Hz to 10 Hz
ƒ = 10 Hz to 1 kHz
0.23
0.35
ppmp-p
ppmrms
HYSTERESIS AND LONG-TERM STABILITY
0 to 250h at 35°C - FKH package
10
28
Long-term stability
ppm
ppm
0 to 1000h at 35°C - FKH package
25°C, –40°C, 125°C, 25°C – FKH package
25°C, –40°C, 85°C, 25°C – FKH package
25°C, 0°C, 70°C, 25°C – FKH package
180
100
40
Output voltage
hysteresis
TURN ON TIME
tON Turn-on time
CAPACITIVE LOAD
0.1% settling, COUT = 1µF
0.5
ms
Stable input capacitor
range
CIN
–40℃ ≤ TA ≤ 125℃
–40℃ ≤ TA ≤ 125℃
0.1
1
µF
µF
Stable output capacitor
range (1)
COUT
100
18
POWER SUPPLY
VIN Input voltage
VOUT
+
V
VDO
TA = 25°C
4
5
6
6.5
10
mA
mA
uA
uA
V
Active mode
–40°C ≤ TA ≤ 125°C
IQ
Quiescent current
TA = 25°C
Shutdown mode
–40°C ≤ TA ≤ 125°C
12
Active mode (EN=1)
1.6
VEN
Enable pin voltage
Enable pin current
Shutdown mode (EN=0)
VIN = VEN = 18V
0.5
4
V
3.2
25
uA
uA
mV
mV
mA
IEN
VIN = VEN = 18V, –40°C ≤ TA ≤ 125°C
IL = 5mA, –40°C ≤ TA ≤ 125°C
IL = 10mA, –40°C ≤ TA ≤ 125°C
VOUT = 0V
5
250
400
VDO
ISC
Dropout voltage
Short circuit current
(1) ESR for the capacitor can range from 10mΩ to 400mΩ
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7.8 REF7033 Electrical Characteristics
Specifications are tested at TA = 25°C, IL = 0 mA, CIN = 0.1 µF, COUT = 10 µF, VIN = VOUT + 0.5V, OUTS connected to OUTF,
unless otherwise noted
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
ACCURACY AND DRIFT
Output voltage accuracy TA = 25°C
–0.025
0.025
2
%
Output voltage
–40°C ≤ TA ≤ 125°C
ppm/℃
temperature coefficient
LINE AND LOAD REGULATION
3.5 V ≤ VIN ≤ 18 V
4
5
ΔVO / ΔVIN Line regulation
ppm/V
3.5 V ≤ VIN ≤ 18 V, –40°C ≤ TA ≤ 125°C
IL = 0 mA to 10mA, VIN = 3.8 V
30
10
IL = 0 mA to 10mA, VIN = 3.8 V, –40°C ≤ TA ≤
125°C
ΔVO / ΔIL
Load regulation
ppm/mA
IL = 0 mA to –10mA, VIN = 3.8 V
5
IL = 0 mA to –10mA, VIN = 3.8 V, –40°C ≤ TA ≤
125°C
15
NOISE
enp-p
en
Low frequency noise
Output voltage noise
ƒ = 0.1 Hz to 10 Hz
ƒ = 10 Hz to 1 kHz
0.23
0.35
ppmp-p
ppmrms
HYSTERESIS AND LONG-TERM STABILITY
0 to 250h at 35°C - FKH package
10
28
Long-term stability
ppm
ppm
0 to 1000h at 35°C - FKH package
25°C, –40°C, 125°C, 25°C – FKH package
25°C, –40°C, 85°C, 25°C – FKH package
25°C, 0°C, 70°C, 25°C – FKH package
180
100
40
Output voltage
hysteresis
TURN ON TIME
tON Turn-on time
CAPACITIVE LOAD
0.1% settling, COUT = 1µF
0.5
ms
Stable input capacitor
range
CIN
–40℃ ≤ TA ≤ 125℃
–40℃ ≤ TA ≤ 125℃
0.1
1
µF
µF
Stable output capacitor
range (1)
COUT
100
18
POWER SUPPLY
VIN Input voltage
VOUT
+
V
VDO
TA = 25°C
4
5
6
6.5
10
mA
mA
uA
uA
V
Active mode
–40°C ≤ TA ≤ 125°C
IQ
Quiescent current
TA = 25°C
Shutdown mode
–40°C ≤ TA ≤ 125°C
12
Active mode (EN=1)
1.6
VEN
Enable pin voltage
Enable pin current
Shutdown mode (EN=0)
VIN = VEN = 18V
0.5
4
V
3.2
25
uA
uA
mV
mV
mA
IEN
VIN = VEN = 18V, –40°C ≤ TA ≤ 125°C
IL = 5mA, –40°C ≤ TA ≤ 125°C
IL = 10mA, –40°C ≤ TA ≤ 125°C
VOUT = 0V
5
250
400
VDO
ISC
Dropout voltage
Short circuit current
(1) ESR for the capacitor can range from 10mΩ to 400mΩ
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7.9 REF7040 Electrical Characteristics
Specifications are tested at TA = 25°C, IL = 0 mA, CIN = 0.1 µF, COUT = 10 µF, VIN = VOUT + 0.5V, OUTS connected to OUTF,
unless otherwise noted
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
ACCURACY AND DRIFT
Output voltage accuracy TA = 25°C
–0.025
0.025
2
%
Output voltage
–40°C ≤ TA ≤ 125°C
ppm/℃
temperature coefficient
LINE AND LOAD REGULATION
VOUT + VDO ≤ VIN ≤ 18 V
4
5
ΔVO / ΔVIN Line regulation
ppm/V
VOUT + VDO ≤ VIN ≤ 18 V, –40°C ≤ TA ≤ 125°C
IL = 0 mA to 10mA, VIN = VOUT + VDO
30
10
IL = 0 mA to 10mA, VIN = VOUT + VDO, –40°C ≤
TA ≤ 125°C
ΔVO / ΔIL
Load regulation
ppm/mA
IL = 0 mA to –10mA, VIN = VOUT + VDO
5
IL = 0 mA to –10mA, VIN = VOUT + VDO, –40°C ≤
TA ≤ 125°C
15
NOISE
enp-p
en
Low frequency noise
Output voltage noise
ƒ = 0.1 Hz to 10 Hz
ƒ = 10 Hz to 1 kHz
0.23
0.35
ppmp-p
ppmrms
HYSTERESIS AND LONG-TERM STABILITY
0 to 250h at 35°C - FKH package
10
28
Long-term stability
ppm
ppm
0 to 1000h at 35°C - FKH package
25°C, –40°C, 125°C, 25°C – FKH package
25°C, –40°C, 85°C, 25°C – FKH package
25°C, 0°C, 70°C, 25°C – FKH package
180
100
40
Output voltage
hysteresis
TURN ON TIME
tON Turn-on time
CAPACITIVE LOAD
0.1% settling, COUT = 1µF
0.5
ms
Stable input capacitor
range
CIN
–40℃ ≤ TA ≤ 125℃
–40℃ ≤ TA ≤ 125℃
0.1
1
µF
µF
Stable output capacitor
range (1)
COUT
100
18
POWER SUPPLY
VIN Input voltage
VOUT
+
V
VDO
TA = 25°C
4
5
6
6.5
10
mA
mA
uA
uA
V
Active mode
–40°C ≤ TA ≤ 125°C
IQ
Quiescent current
TA = 25°C
Shutdown mode
–40°C ≤ TA ≤ 125°C
12
Active mode (EN=1)
1.6
VEN
Enable pin voltage
Enable pin current
Shutdown mode (EN=0)
VIN = VEN = 18V
0.5
4
V
3.2
25
uA
uA
mV
mV
mA
IEN
VIN = VEN = 18V, –40°C ≤ TA ≤ 125°C
IL = 5mA, –40°C ≤ TA ≤ 125°C
IL = 10mA, –40°C ≤ TA ≤ 125°C
VOUT = 0V
5
250
400
VDO
ISC
Dropout voltage
Short circuit current
(1) ESR for the capacitor can range from 10mΩ to 400mΩ
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7.10 REF7050 Electrical Characteristics
Specifications are tested at TA = 25°C, IL = 0 mA, CIN = 0.1 µF, COUT = 10 µF, VIN = VOUT + 0.5V, OUTS connected to OUTF,
unless otherwise noted
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
ACCURACY AND DRIFT
Output voltage accuracy TA = 25°C
–0.025
0.025
2
%
Output voltage
–40°C ≤ TA ≤ 125°C
ppm/℃
temperature coefficient
LINE AND LOAD REGULATION
VOUT + VDO ≤ VIN ≤ 18 V
4
5
ΔVO / ΔVIN Line regulation
ppm/V
VOUT + VDO ≤ VIN ≤ 18 V, –40°C ≤ TA ≤ 125°C
IL = 0 mA to 10mA, VIN = VOUT + VDO
30
10
IL = 0 mA to 10mA, VIN = VOUT + VDO, –40°C ≤
TA ≤ 125°C
ΔVO / ΔIL
Load regulation
ppm/mA
IL = 0 mA to –10mA, VIN = VOUT + VDO
5
IL = 0 mA to –10mA, VIN = VOUT + VDO, –40°C ≤
TA ≤ 125°C
15
NOISE
enp-p
en
Low frequency noise
Output voltage noise
ƒ = 0.1 Hz to 10 Hz
ƒ = 10 Hz to 1 kHz
0.23
0.35
ppmp-p
ppmrms
HYSTERESIS AND LONG-TERM STABILITY
0 to 250h at 35°C - FKH package
10
28
Long-term stability
ppm
ppm
0 to 1000h at 35°C - FKH package
25°C, –40°C, 125°C, 25°C – FKH package
25°C, –40°C, 85°C, 25°C – FKH package
25°C, 0°C, 70°C, 25°C – FKH package
180
100
40
Output voltage
hysteresis
TURN ON TIME
tON Turn-on time
CAPACITIVE LOAD
0.1% settling, COUT = 1µF
0.5
ms
Stable input capacitor
range
CIN
–40℃ ≤ TA ≤ 125℃
–40℃ ≤ TA ≤ 125℃
0.1
1
µF
µF
Stable output capacitor
range (1)
COUT
100
18
POWER SUPPLY
VIN Input voltage
VOUT
+
V
VDO
TA = 25°C
4
5
6
6.5
10
mA
mA
uA
uA
V
Active mode
–40°C ≤ TA ≤ 125°C
IQ
Quiescent current
TA = 25°C
Shutdown mode
–40°C ≤ TA ≤ 125°C
12
Active mode (EN=1)
1.6
VEN
Enable pin voltage
Enable pin current
Shutdown mode (EN=0)
VIN = VEN = 18V
0.5
4
V
3.2
25
uA
uA
mV
mV
mA
IEN
VIN = VEN = 18V, –40°C ≤ TA ≤ 125°C
IL = 5mA, –40°C ≤ TA ≤ 125°C
IL = 10mA, –40°C ≤ TA ≤ 125°C
VOUT = 0V
5
250
400
VDO
ISC
Dropout voltage
Short circuit current
(1) ESR for the capacitor can range from 10mΩ to 400mΩ
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7.11 Typical Characteristics
at TA = 25°C, VIN = VEN = VREF + 0.5 V, IL = 0 mA, CL = 10 μF, CIN = 0.1 μF, VREF = 2.5 V (unless otherwise noted)
2.501
50%
2.50075
40%
2.5005
2.50025
30%
2.5
2.49975
20%
2.4995
10%
2.49925
2.499
-50
-25
0
25 50
Temperature (°C)
75
100
125
0
Figure 7-1. Output Voltage Vs Free-Air Temperature
Temperature Drift -40°C to 125°C (ppm/°C)
Figure 7-2. Temperature Drift Distribution
16
14
12
10
8
50%
40%
30%
20%
10%
0
6
4
2
0
-50
-25
0
25
50
75
100
125
Temperature (èC)
Figure 7-4. Line Regulation vs Temperature
Output Initial Accuracy (%)
Figure 7-3. Accuracy Distribution
16
14
12
10
8
16
14
12
10
8
6
6
4
4
2
2
0
0
-50
-25
0
25 50
Temperature (°C)
75
100
125
-50
-25
0
25 50
Temperature (°C)
75
100
125
Figure 7-5. Load Regulation (Sourcing) vs Temperature
Figure 7-6. Load Regulation (Sinking) vs Temperature
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7.11 Typical Characteristics (continued)
at TA = 25°C, VIN = VEN = VREF + 0.5 V, IL = 0 mA, CL = 10 μF, CIN = 0.1 μF, VREF = 2.5 V (unless otherwise noted)
10mA
10 mA/div
VIN
-10mA
-10mA
5 V/div
VOUT
100 mV/div
10 mV/div
100µs/div
200µs/div
Figure 7-7. Line Regulation Response
Figure 7-8. Load Transient Response (CL = 1 μF)
2
10mA
1mF
10 mA/div
10mF
1.75
1.5
1.25
1
100mF
-10mA
-10mA
0.75
0.5
0.25
0
10 mV/div
200µs/div
10 20 50 100
1000 10000
Frequency (Hz)
100000
1000000
Figure 7-9. Load Transient Response (CL = 10 μF)
Figure 7-10. Output Impedance
6
2.4
2
5
4
3
2
1
0
1.6
1.2
0.8
0.4
0
-50
-25
0
25 50
Temperature (°C)
75
100
125
-50
-25
0
25 50
Temperature (°C)
75
100
125
Figure 7-11. Quiescent Current vs Temperature
Figure 7-12. Shutdown Current vs Temperature
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7.11 Typical Characteristics (continued)
at TA = 25°C, VIN = VEN = VREF + 0.5 V, IL = 0 mA, CL = 10 μF, CIN = 0.1 μF, VREF = 2.5 V (unless otherwise noted)
1.5
1.2
0.9
0.6
0.3
0
300
250
200
150
100
50
VEN_HIGH
VEN_LOW
0mA
5mA
10mA
0
0
4
8 12
Input Voltage (V)
16
20
-50
-25
0
25 50
Temperature (°C)
75
100
125
Figure 7-13. Enable Threshold vs VIN
Figure 7-14. Dropout Voltage vs Temperature
100
90
80
70
60
50
40
30
20
10
0
0.64
0.56
0.48
0.4
0.32
0.24
0.16
0.08
0
10
100
1k
Frequency (Hz)
10k
100k
Noise (ppmp-p
)
Figure 7-16. Noise Performance 10 Hz to 100 kHz
Figure 7-15. 0.1-Hz to 10-Hz Voltage Noise Distribution (300
units)
120
35%
1uF
10uF
30%
25%
20%
15%
10%
5%
100
80
60
40
20
0
100uF
0
10
100
1k
10k
100k
0
10
20
30
40
50
60
70
80
90 100
Frequency (Hz)
Thermal Hysteresis (ppm)
Figure 7-17. Power-Supply Rejection Ratio vs Frequency
Figure 7-18. REF7025 FKH Thermal Hysteresis Distribution (0°C
to 70°C)
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7.11 Typical Characteristics (continued)
at TA = 25°C, VIN = VEN = VREF + 0.5 V, IL = 0 mA, CL = 10 μF, CIN = 0.1 μF, VREF = 2.5 V (unless otherwise noted)
150
100
50
50
40
30
20
10
0
0
-50
-100
-150
0
5
10
20
25
30
0
400
800
1200
1600
2000
Thermal Hysteresis (ppm)
Time (hr)
Figure 7-19. REF7012 FKH Thermal Hysteresis Distribution (0°C
to 70°C)
Figure 7-20. Long-Term Stability (First 2000 Hours)
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8 Parameter Measurement Information
8.1 Solder Heat Shift
The materials used in the manufacture of the REF70 have differing coefficients of thermal expansion, resulting
in stress on the device die when the part is heated during soldering process. Mechanical and thermal stress on
the device die can cause the output voltages to shift, degrading the initial accuracy specifications of the product.
Reflow soldering is a common cause of this error. In order to illustrate this effect, a total of 32 devices were
soldered on two printed circuit boards [16 devices on each printed circuit board (PCB)] using lead-free solder
paste and the paste manufacturer suggested reflow profile. The reflow profile is as shown in Figure 8-1. The
printed circuit board is comprised of FR4 material. The board thickness is 1.65 mm and the area is 114 mm ×
152 mm.
For recommended reflow profiles using 'Sn-Pb Eutectic Assembly' or 'Pb-Free Assembly' please refer JEDEC
J-STD-020 standard.
300
250
200
150
100
50
0
0
50
100
150
200
250
300
350
400
Time (seconds)
C01
Figure 8-1. Reflow Profile
The reference output voltage is measured before and after the reflow process. Although all tested units exhibit
very low shifts, higher shifts are also possible depending on the size, thickness, and material of the printed circuit
board. An important note is that the Figure 8-2 display the typical shift for exposure to a single reflow profile.
Exposure to multiple reflows, as is common on PCBs with surface-mount components on both sides, causes
additional shifts in the output bias voltage. If the PCB is exposed to multiple reflows, the device must be soldered
in the last pass to minimize its exposure to thermal stress.
80%
60%
40%
20%
0
0
0.01
0.02
0.03
0.04
0.05
Solder Shift (%)
Figure 8-2. Solder Shift
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8.2 Long-Term Stability
One of the key parameters of the REF70 references is long-term stability also known as long-term drift. The
long-term stability value was tested in a typical setup that reflects standard PCB board manufacturing practices.
The boards are made of standard FR4 material and the board does not have special cuts or grooves around the
devices to relieve the mechanical stress of the PCB. The devices and boards in this test do not undergo high
temperature burn in post-soldering prior to testing. These conditions reflect a real world use case scenario and
common manufacturing techniques.
During the long-term stability testing, precautions are taken to ensure that only the long-term stability drift is
being measured. The boards are maintained at 35°C in an oil bath. The oil bath ensures that the temperature
is constant across the device over time compared to an air oven. The measurements are captured every 30
minutes with a calibrated 8.5 digit multimeter.
Typical long-term stability characteristic is expressed as a deviation over time. Figure 8-3 shows the typical drift
value for the REF70 FKH VOUT is 28 ppm from 0 to 1000 hours. It is important to understand that long-term
stability is not ensured by design and that the value is typical. The REF70 will experience the highest drift in the
initial 1000 hr. Subsequent deviation is typically lower than 13 ppm for the next 1000 hr.
150
100
50
0
-50
-100
-150
0
400
800
1200
1600
2000
Time (hr)
Figure 8-3. Long Term Stability LCCC -2000 hours (VOUT
)
8.3 Thermal Hysteresis
Thermal hysteresis is measured with the REF70 FKH soldered to a PCB, similar to a real-world application.
Thermal hysteresis for the device is defined as the change in output voltage after operating the device at 25°C,
cycling the device through the specified temperature range, and returning to 25°C. This can be seen in Figure
8-4 to Figure 8-5. Hysteresis can be expressed by Equation 1:
≈
∆
«
’
÷
◊
| VPRE - VPOST
VNOM
|
VHYST
=
ì106 ppm
(
)
(1)
where
•
•
•
•
VHYST = thermal hysteresis (in units of ppm)
VNOM = the specified output voltage
VPRE = output voltage measured at 25°C pre-temperature cycling
VPOST = output voltage measured after the device has cycled from 25°C through the specified temperature
range of –40°C to +125°C and returns to 25°C.
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50%
50%
40%
30%
20%
10%
0
40%
30%
20%
10%
0
120 130 140 150 160 170 180 190 200 210 220 230 240
0
10
20
30
40
Thermal Hysteresis (ppm)
Thermal Hysteresis (ppm)
Figure 8-4. REF7025 Thermal Hysteresis
Distribution (-40°C to 125°C)
Figure 8-5. REF7012 Thermal Hysteresis
Distribution (-40°C to 125°C)
8.4 Noise Performance
8.4.1 1/f Noise
1/f noise, also known as flicker noise, is a low frequency noise that affects the device output voltage which can
affect precision measurements in ADCs. This noise increases proportionally with output voltage and operating
temperature. It is measured by filtering the output from 0.1-Hz to 10-Hz. Since the 1/f noise is an extremely
low value, the frequency of interest needs to be amplified and band-pass filtered. This is done by using a
high-pass filter to block the DC voltage. The resulting noise is then amplified by a gain of 1000. The bandpass
filter is created by a series of high-pass and low-pass filter that adds additional gain to make it more visible
on a oscilloscope as shown in Figure 8-6. 1/f noise must be tested in a Faraday cage enclosure to block
environmental noise.
VIN
VREFP
VIN EN
REF70xx
CIN
OUTF
OUTS
Low Noise
Preamplifier
G = 1000
High-pass Filter
FC = 0.07 Hz
CL
GND
2nd Order
High-pass Filter
FC = 0.1 Hz
G = 10
2nd Order
Low-pass Filter
FC = 10 Hz
G = 10
2nd Order
Low-pass Filter
FC = 10 Hz
G = 1
Scope
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Figure 8-6. 1/f Noise Test Setup
Typical 1/f noise (0.1-Hz to 10-Hz) distribution can be seen in Figure 8-7.
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0.64
0.56
0.48
0.4
0.32
0.24
0.16
0.08
0
Noise (ppmp-p
)
Figure 8-7. 0.1-Hz to 10-Hz Voltage Noise Distribution
The 1/f noise is in such a low frequency range that it is not practical to filter out which makes it a key parameter
for ultra-low noise measurements. Noise sensitive designs must use the lowest 1/f noise for the highest precision
measurements. Figure 8-8 shows the effect of 1/f noise over 10s.
Time 1s/div
Figure 8-8. 0.1-Hz to 10-Hz Voltage Noise
8.4.2 Broadband Noise
Broadband noise is a noise that appears at higher frequency compared to 1/f noise. The broadband noise is
usually flat and uniform over frequency as shown in Figure 8-10. The broadband noise is measured by high-pass
filtering the output of the REF70 and measuring the result on a spectrum analyzer as shown in Figure 8-9.
The DC component of the REF70 is removed by using a high-pass filter and then amplified. When measuring
broadband noise, it is not necessary to have high gain in order to achieve maximum bandwidth.
VIN
VREFP
VIN EN
REF70xx
CIN
OUTF
OUTS
High-pass Filter
G = 11
Post Amplifier
G = 11
Spectrum
Analyzer
CL
GND
Figure 8-9. Broadband Noise Test Setup
For noise sensitive designs, a low-pass filter can be used to reduce broadband noise output noise levels by
removing the high frequency components. When designing a low-pass filter special care must be taken to
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ensure the output impedance of the filter does not degrade ac performance. This can occur in RC low-pass
filters where a large series resistance can impact the load transients due to output current fluctuations.
100
90
80
70
60
50
40
30
20
10
0
10
100
1k
Frequency (Hz)
10k
100k
Figure 8-10. Noise Performance 10 Hz to 100 kHz
8.5 Temperature Drift
The REF70 is designed and tested for a minimal output voltage temperature drift, which is defined as the
change in output voltage over temperature. Every unit shipped is tested at multiple temperatures to ensure that
the product meets data sheet specifications. The temperature coefficient is calculated using the box method
in which a box is formed by the min/max limits for the nominal output voltage over the operating temperature
range. REF70 has a low maximum temperature coefficient of 2 ppm/°C from –40°C to +125°C. This method
corresponds more accurately to the method of test and provides a closer estimate of actual error than the other
methods. The box method specifies limits for the temperature error but does not specify the exact shape and
slope of the device under test. Due to temperature curvature correction to achieve low-temperature drift, the
temperature drift is expected to be non-linear. See SLYT183 for more information on the box method. The box
method equation is shown in Equation 2:
≈
’
VREF(MAX) - VREF(MIN)
Drift =
ì106
∆
∆
«
÷
÷
◊
VREF(25èC) ìTemperature Range
(2)
2.501
2.50075
2.5005
2.50025
2.5
2.49975
2.4995
2.49925
2.499
-50
-25
0
25 50
Temperature (°C)
75
100
125
Figure 8-11. Output Voltage Vs Free-Air Temperature
8.6 Power Dissipation
The REF70 voltage references are capable of source and sink up to 10 mA of load current across the rated
input voltage range. However, when used in applications subject to high ambient temperatures, the input voltage
and load current must be carefully monitored to ensure that the device does not exceeded its maximum power
dissipation rating. The maximum power dissipation of the device can be calculated with Equation 3:
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TJ = TA +P ì RqJA
D
(3)
where
•
•
•
•
PD is the device power dissipation
TJ is the device junction temperature
TA is the ambient temperature
RθJA is the package (junction-to-air) thermal resistance
Because of this relationship, acceptable load current in high temperature conditions may be less than the
maximum current-sourcing capability of the device. In no case should the device be operated outside of its
maximum power rating because doing so can result in premature failure or permanent damage to the device.
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9 Detailed Description
9.1 Overview
The REF70 is family of ultra low-noise, precision bandgap voltage references that are specifically designed for
excellent initial voltage accuracy and drift. The Section 9.2 is a simplified block diagram of the REF70 showing
basic band-gap topology.
9.2 Functional Block Diagram
VIN
Digital
Core
Bandgap
Core
+
Reference
Buffer
Å
VIN
OUTF
OUTS
REN
Enable
Controller
EN
GND
9.3 Feature Description
9.3.1 EN Pin
The EN pin of the REF70 has an internal 16 MΩ pull-up resistor (REN) to VIN. This allows the EN pin of the
REF70 to be left floating. When the EN pin of the REF70 is pulled high, the device is in active mode. The device
must be in active mode for normal operation. The REF70 can be placed in shutdown mode by pulling the EN pin
low. When in shutdown mode, the output of the device becomes high impedance and the quiescent current of
the device reduces to 12 µA in shutdown mode. The EN pin must not be pulled higher than VIN supply voltage.
See the Section 7.6 for logic high and logic low voltage levels.
9.4 Device Functional Modes
9.4.1 Basic Connections
Figure 9-1 shows the typical connections for the REF70. TI recommends a supply bypass capacitor (CIN)
ranging from 0.1-μF to 10-μF. A 1-μF to 100-μF output capacitor (CL) must be connected from OUTF to GND.
The equivalent series resistance (ESR) value of CL must be 10mΩ to 400mΩ to ensure output stability.
AVDD
VOUT
VIN
EN
OUTF
OUTS
REF7025
GND
CIN
CL
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Figure 9-1. Basic Connections
9.4.2 Negative Reference Voltage
For applications requiring a negative and positive reference voltage, the REF70 and OPA211 can be used to
provide a dual-supply reference from a 5-V supply. Figure 9-2 shows the REF70 used to provide a 2.5-V supply
reference voltage and -2.5V negative reference voltage. The low noise performance of the REF70 complements
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the low noise of the OPA211 to provide an accurate solution for split-supply applications. Take care to match the
temperature coefficients of R1 and R2.
+5V
VIN EN
OUTF
+2.5V
REF7025
OUTS
R1
GND
10 kꢀ
R2
10 kꢀ
+5V
-2.5V
OPA211
-5V
Copyright © 2020, Texas Instruments Incorporated
Figure 9-2. The REF70 and OPA211 Create Positive and Negative Reference Voltages
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10 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
10.1 Application Information
This device is a natural fit for many precision applications and it can be connected to system components
in various ways and thus there are many situations that this data sheet can not characterize in detail. Basic
applications include positive/negative voltage reference and data acquisition systems. The table below shows
the typical applications of REF70 and its companion data converters.
APPLICATION
DATA CONVERTER
Precision Data Acquisition
Industrial Instrumentation
Semiconductor Test
ADS124S08, ADS8900B, ADS1278, ADS1262, DAC80501,
DAC8562
ADS127L01, ADS8699, ADS1256, ADS1251, DAC9881, DAC8811,
DAC1220, DAC80508
ADS8598H, ADS131M08, ADS8686S, ADS8881, DAC11001A,
DAC91001A, DAC7744
Power Monitoring, PLC Analog I/O
Field Transmitters
ADS131E04, ADS131A02,
ADS1247, ADS1220
10.2 Typical Applications
10.2.1 Typical Application: Basic Voltage Reference Connection
The circuit shown in Figure 10-1 shows the basic configuration for the REF70 references. Connect bypass
capacitors according to the guidelines in Section 10.2.1.2.1.
AVDD
VIN EN
OUTF
REF7025
OUTS
GND
AVDD
OPA2320
REFN0 REFP0
AVDD
AIN0
AVDD
ADS124S08
AIN
AVDD
AVSS
AIN1
OPA2320
Copyright © 2020, Texas Instruments Incorporated
Figure 10-1. Basic Reference Connection
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10.2.1.1 Design Requirements
A detailed design procedure is based on a design example. For this design example, use the parameters listed
in Table 10-1 as the input parameters.
Table 10-1. Design Example Parameters
DESIGN PARAMETER
VALUE
Input voltage VIN
5.5 V
Output voltage VOUT
2.5 V
REF7025 input capacitor
REF7025 output capacitor
10-µF
10-µF
10.2.1.2 Detailed Design Procedure
10.2.1.2.1 Input and Output Capacitors
A 1 μF to 10 μF bypass capacitor should be connected to the input to improve transient response in applications
where the supply voltage may fluctuate. Connect an additional 0.1 μF capacitor in parallel to reduce high
frequency supply noise.
A low ESR capacitor of 1 μF to 100 μF must be connected to the output to improve stability and help filter
out high frequency noise. Best performance and stability is attained with low-ESR output capacitors with an
ESR from 10 mΩ to 400 mΩ. For very low noise applications, special care must be taken with X7R and
other MLCC capacitors due to their piezoelectric effect. Mechanical vibration can transduce to voltage via the
piezoelectric effect which appears as noise in the μV range, potentially dominating the noise of the REF70. More
information on how the piezoelectric effect can be explored in systems can be found in Stress-induced outbursts:
Microphonics in ceramic capacitors (Part 1) and Stress-induced outbursts: Microphonics in ceramic capacitors
(Part 2). It is recommended that to use film capacitors for noise sensitive applications.
The transient startup response of the REF70 is shown in Figure 10-2. The startup response of the REF70 family
is dependent on the output capacitor. While larger capacitors will decrease the output noise, they will increase
the startup response.
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10.2.1.2.1.1 Application Curve
Figure 10-2. REF7025 Startup (C = 10 μF)
10.2.1.2.2 Force and Sense Connection
Current flowing through a PCB trace produces an IR voltage drop, and with longer traces, this drop can reach
several millivolts or more, introducing a considerable error into the output voltage of the reference. A 3000-mil
long, 15-mil wide trace of 1-ounce copper has a resistance of approximately 100 mΩ at room temperature; at a
load current of 10 mA, this can introduce a full millivolt of error. In an ideal board layout, the reference must be
mounted as close as possible to the load to minimize the length of the output traces, and, therefore, the error
introduced by voltage drop. However, in applications where this is not possible or convenient, force and sense
connections (sometimes referred to as Kelvin sensing connections) are provided as a means of minimizing the
IR drop and improving accuracy.
Kelvin connections work by providing a set of high impedance voltage-sensing lines to the output and ground
nodes. Because very little current flows through these connections, the IR drop across their traces is negligible,
and the output and ground. The REF70 has kelvin connection capabilities due to its output force (OUTF) and
input sense (OUTS) connection as shown in Basic Reference Connection. The output force voltage will vary
upwards from the internal VREF voltage to ensure that at VOUT, which is where the OUTF and OUTS connect at
the point-of-load, the voltage will be precisely VREF. The sense connection on the REF70 requires 4 mA due to
its architecture, therefore if the load current is expected to be less than 4mA, then OUTF should be shorted to
OUTS.
It is always advantageous to use Kelvin connections whenever possible. However, in applications where the IR
drop is negligible or an extra set of traces cannot be routed to the load, the force and sense pins for VOUT can
simply be tied together close to the pins, and the device can be used in the same fashion as a normal 3-terminal
reference.
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10.2.2 Typical Application: DAC Force and Sense Reference Drive Circuit
Certain DACs require external voltage references to operate properly. There are DACs that only require a
positive voltage for operating in which the basic connection will work. For other DACs there can be a need a
positive and negative reference voltage due to their bipolar output.
The circuit shown in Figure 10-3 shows a DAC force and sense reference drive circuit for the DACx1001 using
the REF70. This circuit takes advantage of the DACx1001 RCM circuit to remove the need of additional external
resistors to make a negative reference due to the integrated precision resistors. This circuit requires additional
buffers due to undesired series resistance on the reference input of the DAC.
VIN
VREFP
VIN EN
CIN
OUTF
OUTS
REFPF
REFPS
REF7050
CL
C1
GND
ROFS
RCM
RFB
DACx1001
REFNS
REFNF
C2
VREFN
Copyright © 2020, Texas Instruments Incorporated
Figure 10-3. Basic Force and Sense Reference Drive Circuit Connections with DACx1001
10.2.2.1 Design Requirements
For this design example, use the reference op amp recommendation listed in Table 10-2 for the buffer circuit.
Table 10-2. Reference Op Amp Options
SELECTION PARAMETERS
Low voltage and current noise
Low offset and drift
OP AMPS
OPA211, OPA827, OPA828
OPA189
The REF70 turn-on time is dependent on the output capacitor. In certain applications that require a fast turn-on
can require a smaller output capacitor as shown in Figure 10-4
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2
1.6
1.2
0.8
0.4
0
1mF
10mF
-50
-25
0
25 50
Temperature (°C)
75
100
125
Figure 10-4. REF70 Turn-on Time
For DAC designs that do not have the RCM feature, use Figure 10-5 as it in generates the negative reference
circuit to create the VREFN. More details on this type of design can be found in SBAA322.
VIN
VCC
VIN EN
CIN
OUTF
OUTS
VREFH-F
REF7050
C1
CL
GND
VSS
VREFH-S
DAC8871
R1
10 kꢀ
R2
10 kꢀ
VREFL-S
VCC
C2
VCC
VREFL-F
VSS
VSS
Copyright © 2020, Texas Instruments Incorporated
Figure 10-5. Basic Force and Sense Reference Drive Circuit Connections
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11 Power Supply Recommendation
The REF70 family of references features a low-dropout voltage. These references can be operated with a supply
of only 50 mV above the output voltage for 0-mA output current conditions. The dropout voltage will vary with
the output current so refer to the dropout voltage to see typical dropout voltage requirements. TI recommends a
supply bypass capacitor ranging between 0.1 µF to 10 µF.
During start-up the REF70 can experience moments of high input current due to the output capacitors. The input
current can momentarily rise to ISC
.
300
250
200
150
100
50
0mA
5mA
10mA
0
-50
-25
0
25 50
Temperature (°C)
75
100
125
Figure 11-1. Dropout Voltage vs Temperature
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12 Layout
12.1 Layout Guidelines
Figure 12-1 illustrates an example of a PCB layout for a data acquisition system using the REF70. Some key
considerations are:
•
•
•
•
Connect low-ESR, 0.1-μF ceramic bypass capacitors at VIN of the REF70.
Connect low-ESR, 1-uF to 100-uF capacitor at OUTF of the REF70.
Decouple other active devices in the system per the device specifications.
Using a solid ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise
pickup.
•
•
Place the external components as close to the device as possible. This configuration prevents parasitic errors
(such as the Seebeck effect) from occurring.
Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when absolutely necessary.
12.2 Layout Example
Analog GND
OUTF
GND
8
Enable Control
Input Voltage
7
EN 1
VIN
GND 3
VREF
CL
CIN
6 OUTS
GND
2
5
4
GND
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Figure 12-1. Layout Example
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation see the following:
•
•
Texas Instruments, Voltage Reference Design Tips For Data Converters
Texas Instruments, Voltage Reference Selection Basics
13.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
13.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
5-Jan-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PREF7030QFKHT
PREF7033QFKHT
PREF7040QFKHT
PREF7050QFKHT
REF7012QFKHT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LCCC
LCCC
LCCC
LCCC
LCCC
FKH
FKH
FKH
FKH
FKH
8
8
8
8
8
250
250
250
250
250
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
RoHS-Exempt
& Green
N / A for Pkg Type
REF12FKH
REF25FKH
REF7025QFKHT
ACTIVE
LCCC
FKH
8
250
RoHS-Exempt
& Green
Call TI
Level-2-260C-1 YEAR
-40 to 125
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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5-Jan-2022
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Dec-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
REF7012QFKHT
REF7025QFKHT
LCCC
LCCC
FKH
FKH
8
8
250
250
180.0
180.0
12.4
12.4
5.35
5.35
5.35
5.35
1.57
1.57
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Dec-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
REF7012QFKHT
REF7025QFKHT
LCCC
LCCC
FKH
FKH
8
8
250
250
210.0
210.0
185.0
185.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
FKH0008A
LCCC - 1.6 mm max height
S
C
A
L
E
2
.
5
0
0
LEADLESS CERAMIC CHIP CARRIER
5.15
4.85
4.58 MAX
(R0.2) TYP
1.6 MAX
NOTE 3
PKG
(0.65) TYP
(0.1) TYP
4
NOTE 3
TYP
4X 1.27 0.2
3
5
PKG
2X
2.54 0.2
(2)
1
7
0.84
8X
0.44
NOTE 3
TYP
8
1.2
0.8
7X
4222330/C 12/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M
2. This drawing is subject to change without notice.
3. Terminals are gold plated.
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EXAMPLE BOARD LAYOUT
FKH0008A
LCCC - 1.6 mm max height
LEADLESS CERAMIC CHIP CARRIER
SYMM
PKG
8
7X (1.6)
(2.5)
1
7
(1.75)
8X (0.7)
PKG
4X (1.27)
(R0.05)
(2.2)
5
3
4
(4.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:10X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222330/C 12/2020
NOTES: (continued)
4. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
FKH0008A
LCCC - 1.6 mm max height
LEADLESS CERAMIC CHIP CARRIER
SYMM
8
7X (1.6)
(2.5)
1
7
(1.75)
9X (0.7)
PKG
4X (1.27)
(2.2)
5
3
4
(4.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:12X
4222330/C 12/2020
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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