REG102UA-2.8/2K5G4 [TI]
2.8V FIXED POSITIVE LDO REGULATOR, 0.27V DROPOUT, PDSO6, GREEN, PLASTIC, MS-012AA, SOIC-8;
| 型号： | REG102UA-2.8/2K5G4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2.8V FIXED POSITIVE LDO REGULATOR, 0.27V DROPOUT, PDSO6, GREEN, PLASTIC, MS-012AA, SOIC-8 光电二极管 输出元件 调节器 |
| 文件： | 总28页 (文件大小：1405K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
REG102
R
E
G
1
0
2
R
E
G
1
0
2
SBVS024F – NOVEMBER 2000 – REVISED SEPTEMBER 2005
DMOS
250mA Low-Dropout Regulator
DESCRIPTION
FEATURES
The REG102 is a family of low-noise, low-dropout linear
regulators with low ground pin current. The new DMOS
topology provides significant improvement over previous
designs, including low-dropout voltage (only 150mV typ at
full load), and better transient performance. In addition, no
output capacitor is required for stability, unlike conventional
low-dropout regulators that are difficult to compensate and
require expensive low ESR capacitors greater than 1µF.
● NEW DMOS TOPOLOGY:
Ultra Low Dropout Voltage:
150mV typ at 250mA
Output Capacitor not Required for Stability
● FAST TRANSIENT RESPONSE
●
VERY LOW NOISE: 28µVrms
● HIGH ACCURACY: ±1.5% max
● HIGH EFFICIENCY:
Typical ground pin current is only 600µA (at IOUT = 250mA)
and drops to 10nA when not enabled. Unlike regulators with
PNP pass devices, quiescent current remains relatively con-
stant over load variations and under dropout conditions.
IGND = 600µA at IOUT = 250mA
Not Enabled: IGND = 0.01µA
● 2.5V, 2.8V, 2.85V, 3.0V, 3.3V, AND 5.0V
ADJUSTABLE OUTPUT VERSIONS
The REG102 has very low output noise (typically 28µVrms
for VOUT = 3.3V with CNR = 0.01µF), making it ideal for use
in portable communications equipment. On-chip trimming
results in high output voltage accuracy. Accuracy is main-
tained over temperature, line, and load variations. Key pa-
rameters are tested over the specified temperature range
(–40°C to +85°C).
● OTHER OUTPUT VOLTAGES AVAILABLE UPON
REQUEST
● FOLDBACK CURRENT LIMIT
● THERMAL PROTECTION
● SMALL SURFACE-MOUNT PACKAGES:
SOT23-5, SOT223-5, and SO-8
The REG102 is well protected—internal circuitry provides a
current limit that protects the load from damage; furthermore,
thermal protection circuitry keeps the chip from being dam-
aged by excessive temperature. The REG102 is available in
SOT23-5, SOT223-5, and SO-8 packages.
APPLICATIONS
● PORTABLE COMMUNICATION DEVICES
● BATTERY-POWERED EQUIPMENT
● PERSONAL DIGITAL ASSISTANTS
● MODEMS
● BAR-CODE SCANNERS
● BACKUP POWER SUPPLIES
Enable
Enable
VOUT
VIN
VOUT
VIN
REG102
(Fixed Voltage
Versions)
+
R1
Adj
R2
+
+
+
0.1µF
(1)
(1)
COUT
REG102-A
COUT
0.1µF
NR
GND
GND
NOTE: (1) Optional.
NR = Noise Reduction
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 2000-2005, Texas Instruments Incorporated
www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper han-
dling and installation procedures can cause damage.
Supply Input Voltage, VIN .......................................................–0.3V to 12V
Enable Input Voltage, VEN ....................................................... –0.3V to VIN
Feedback Voltage, VFB ........................................................ –0.3V to 6.0V
NR Pin Voltage, VNR .............................................................–0.3V to 6.0V
Output Short-Circuit Duration ...................................................... Indefinite
Operating Temperature Range (TJ) ................................ –55°C to +125°C
Storage Temperature Range (TA) ................................... –65°C to +150°C
Lead Temperature (soldering, 3s).................................................. +240°C
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
NOTE: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability.
PACKAGE/ORDERING INFORMATION(1)
(2)
PRODUCT
VOUT
REG102xx-yyyy/zzz
XX is package designator.
YYYY is typical output voltage (5 = 5.0V, 2.85 = 2.85V, A = Adjustable).
ZZZ is package quantity.
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com.
(2) Output voltages from 2.5V to 5.1V in 50mV increments are available; minimum order quantities apply. Contact factory for details and availability.
PIN CONFIGURATIONS
Top View
SOT23-5
SO-8
SOT223-5
(2)
(2)
(3)
(3)
VIN
GND
1
2
3
5
4
VOUT
VOUT
VOUT
1
2
3
4
8
7
6
5
VIN
VIN
Tab is GND
Enable
NR/Adjust(1)
NR/Adjust(1)
GND
NC
1
2
3
4
5
Enable
(N Package)
VIN
GND
NR/Adjust(1)
Enable
(U Package)
VOUT
(G Package)
NOTES: (1) For REG102A-A: voltage setting resistor pin.
All other models: noise reduction capacitor pin.
(2) Both pin 1 and pin 2 must be connected.
(3) Both pin 7 and pin 8 must be connected.
REG102
2
SBVS024F
www.ti.com
ELECTRICAL CHARACTERISTICS
Boldface limits apply over the specified temperature range, TJ = –40°C to +85°C.
At TJ = +25°C, VIN = VOUT + 1V (VOUT = 2.5V for REG102-A), VENABLE = 1.8V, IOUT = 5mA, CNR = 0.01µF, and COUT = 0.1µF(1), unless otherwise noted.
REG102NA
REG102GA
REG102UA
PARAMETER
CONDITION
MIN
TYP
MAX
UNITS
OUTPUT VOLTAGE
Output Voltage Range
REG102-2.5
REG102-2.8
REG102-2.85
REG102-3.0
REG102-3.3
REG102-5
REG102-A
VOUT
2.5
2.8
2.85
3.0
3.3
5
V
V
V
V
V
V
V
2.5
5.5
Reference Voltage
Adjust Pin Current
Accuracy
Over Temperature
vs Temperature
vs Line and Load
Over Temperature
VREF
IADJ
1.26
0.2
±0.5
V
µA
%
%
ppm/°C
%
1
±1.5
±2.3
dVOUT/dT
50
±0.8
IOUT = 5mA to 250mA, VIN = (VOUT + 0.4V) to 10V
±2.0
±2.8
VIN = (VOUT + 0.6V) to 10V
%
DC DROPOUT VOLTAGE(2)
For all models
Over Temperature
VDROP
IOUT = 5mA
IOUT = 250mA
IOUT = 250mA
4
150
10
220
270
mV
mV
mV
VOLTAGE NOISE
f = 10Hz to 100kHz
Vn
Without CNR (all models)
With CNR (all fixed voltage models)
CNR = 0, COUT = 0
CNR = 0.01µF, COUT = 10µF
23µVrms/V • VOUT
7µVrms/V • VOUT
µVrms
µVrms
OUTPUT CURRENT
Current Limit(3)
Over Temperature
Short-Circuit Current Limit
ICL
ISC
340
300
400
150
470
490
mA
mA
mA
RIPPLE REJECTION
f = 120Hz
65
dB
ENABLE CONTROL
V
ENABLE High (output enabled)
VENABLE Low (output disabled)
ENABLE High (output enabled)
VENABLE
IENABLE
1.8
–0.2
VIN
0.5
100
100
V
V
nA
nA
µs
ms
I
VENABLE = 1.8V to VIN, VIN = 1.8V to 6.5(4)
VENABLE = 0V to 0.5V
1
2
50
1.5
IENABLE Low (output disabled)
Output Disable Time
Output Enable Softstart Time
COUT = 1.0µF, RLOAD = 13Ω
COUT = 1.0µF, RLOAD = 13Ω
THERMAL SHUTDOWN
Junction Temperature
Shutdown
160
140
°C
°C
Reset from Shutdown
GROUND PIN CURRENT
Ground Pin Current
IGND
IOUT = 5mA
OUT = 250mA
VENABLE ≤ 0.5V
400
600
0.01
500
800
0.2
µA
µA
µA
I
Enable Pin Low
INPUT VOLTAGE
VIN
Operating Input Voltage Range(5)
Specified Input Voltage Range
Over Temperature
1.8
VOUT + 0.4
VOUT + 0.6
10
10
10
V
V
V
VIN > 1.8V
VIN > 1.8V
TEMPERATURE RANGE
Specified Range
Operating Range
TJ
TJ
TA
–40
–55
–65
+85
+125
+150
°C
°C
°C
Storage Range
Thermal Resistance
SOT23-5 Surface-Mount
SO-8 Surface-Mount
SOT223-5 Surface-Mount
θJA
θJA
θJC
θJA
Junction-to-Ambient
Junction-to-Ambient
Junction-to-Case
200
150
15
°C/W
°C/W
°C/W
°C/W
Junction-to-Ambient
See Figure 8
NOTES: (1) The REG102 does not require a minimum output capacitor for stability, however, transient response can be improved with proper capacitor selection.
(2) Dropout voltage is defined as the input voltage minus the output voltage that produces a 2% change in the output voltage from the value at VIN = VOUT
+ 1V at fixed load.
(3) Current limit is the output current that produces a 10% change in output voltage from VIN = VOUT + 1V and IOUT = 5mA.
(4) For VENABLE > 6.5V, see typical characteristic IENABLE vs VENABLE
.
(5) The REG102 no longer regulates when VIN < VOUT + VDROP (MAX). In dropout, the impedance from VIN to VOUT is typically less than 1Ω at TJ = +25°C.
REG102
SBVS024F
3
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TYPICAL CHARACTERISTICS
For all models, at TJ = +25°C and VENABLE = 1.8V, unless otherwise noted.
OUTPUT VOLTAGE CHANGE vs IOUT
(VIN = VOUT + 1V, Output Voltage % Change
Referred to IOUT = 125mA at +25°C)
0.80
LOAD REGULATION vs TEMPERATURE
(VIN = VOUT + 1V)
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
0.60
0.40
+25°C
25mA < IOUT < 250mA
5mA < IOUT < 250mA
0.20
+125°C
0
–0.20
–0.40
–55°C
–0.60
–0.80
0
0
0
25 50
75 100 125 150 175 200 225 250
IOUT (mA)
–50
–25
0
25
50
75
100
125
125
125
Temperature (°C)
LINE REGULATION
(Referred to VIN = VOUT + 1V at IOUT = 125mA)
LINE REGULATION vs TEMPERATURE
IOUT = 250mA
0
–0.05
–0.10
–0.15
–0.20
–0.25
–0.30
20
15
All Fixed Output
Voltage Versions
10
IOUT = 5mA
5
(VOUT + 1V) < VIN < 10V
IOUT = 125mA
0
–5
–10
–15
–20
(VOUT + 0.4V) < VIN < 10V
IOUT = 250mA
–50
–25
0
25
50
75
100
1
2
3
4
5
6
7
8
Temperature (°C)
VIN – VOUT (V)
DC DROPOUT VOLTAGE vs IOUT
DC DROPOUT VOLTAGE vs TEMPERATURE
IOUT = 250mA
250
200
150
100
50
250
200
150
100
50
+125°C
+25°C
–55°C
0
–50
0
–25
0
25
50
75
100
50
100
150
200
250
Temperature (°C)
IOUT (mA)
REG102
4
SBVS024F
www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
For all models, at TJ = +25°C and VENABLE = 1.8V, unless otherwise noted.
OUTPUT VOLTAGE DRIFT HISTOGRAM
OUTPUT VOLTAGE ACCURACY HISTOGRAM
18
30
25
20
15
10
5
16
14
12
10
8
6
4
2
0
0
VOUT Drift (ppm/°C)
Error (%)
OUTPUT VOLTAGE vs TEMPERATURE
(Output Voltage % Change Refered
to IOUT = 125mA at +25°C)
GROUND PIN CURRENT, NOT ENABLED
vs TEMPERATURE
1µ
100n
10n
0.80
VENABLE = 0.5V
0.60
0.40
VIN = VOUT + 1V
IOUT = 5mA
IOUT = 125mA
0.20
0
–0.20
–0.40
–0.60
–0.80
–1.00
IOUT = 250mA
1n
100p
–50
–25
0
25
50
75
100
125
–50
–25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
GROUND PIN CURRENT vs TEMPERATURE
VOUT = 5V
GROUND PIN CURRENT vs IOUT
VOUT = 5.0V
750
725
700
675
650
625
600
575
550
800
700
600
500
400
300
200
100
0
IOUT = 250mA
VOUT = 3.3V
VOUT = 3.3V
VOUT = 2.5V
VOUT = 2.5V
–50
–25
0
25
50
75
100
125
0
25
50 75 100 125 150 175 200 225 250
IOUT (mA)
Temperature (°C)
REG102
SBVS024F
5
www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
For all models, at TJ = +25°C and VENABLE = 1.8V, unless otherwise noted.
RIPPLE REJECTION vs FREQUENCY
RIPPLE REJECTION vs (VIN – VOUT
)
80
30
25
20
15
10
5
IOUT = 2mA
70
IOUT = 2mA
OUT = 10µF
60
C
IOUT = 100mA
50
40
30
20
10
0
COUT = 10µF
IOUT = 100mA
Frequency = 100kHz
OUT = 10µF
OUT = 3.3V
IOUT = 100mA
C
V
COUT = 0µF
0
10
100
1k
10k
100k
1M
10M
1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1
0
Frequency (Hz)
VIN – VOUT (V)
RMS NOISE VOLTAGE vs CNR
RMS NOISE VOLTAGE vs COUT
110
100
90
80
70
60
50
40
30
20
60
50
40
30
20
10
0
REG102-5.0
REG102-5.0
REG102-3.3
REG102-3.3
REG102-2.5
REG102-2.5
COUT = 0µF
10Hz < BW < 100kHz
COUT = 0.01µF
10Hz < BW < 100kHz
1
10
100
1k
10k
0.1
1
10
CNR (pF)
COUT (µF)
NOISE SPECTRAL DENSITY
NOISE SPECTRAL DENSITY
10
1
10
1
IOUT = 100mA
NR = 0µF
IOUT = 100mA
NR = 0.01µF
C
C
COUT = 1µF
COUT = 1µF
COUT = 0µF
0.1
0.01
0.1
0.01
COUT = 0µF
COUT = 10µF
COUT = 10µF
10
100
1k
10k
100k
10
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
REG102
6
SBVS024F
www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
For all models, at TJ = +25°C and VENABLE = 1.8V, unless otherwise noted.
CURRENT LIMIT FOLDBACK
3.5
CURRENT LIMIT vs TEMPERATURE
VIN = VOUT + 1V
450
400
350
300
250
200
150
100
3.0
ICL = Current Limit
REG102-3.3
2.5
ICL
2.0
1.5
ISC = Short-Circuit Current
1.0
ISC
0.5
0
0
50
100 150 200 250 300 350 400 450
Output Current (mA)
–50
–25
0
25
50
75
100
125
Temperature (°C)
LINE TRANSIENT RESPONSE
LOAD TRANSIENT RESPONSE
REG102-3.3
OUT = 250mA
REG102-3.3
IN = 4.3V
I
V
COUT = 0
COUT = 0µF
VOUT
VOUT
COUT = 10µF
VOUT
COUT = 10µF
VOUT
IOUT
5.3V
4.3V
250mA
25mA
VIN
50µs/div
10µs/div
TURN-ON
TURN-OFF
COUT = 0µF
RLOAD = 660Ω
COUT = 10µF
RLOAD = 13Ω
VOUT
VOUT
COUT = 0µF
RLOAD = 13Ω
COUT = 1.0µF
RLOAD = 13Ω
COUT = 10µF
RLOAD = 13Ω
COUT = 0µF
RLOAD = 660Ω
VENABLE
VENABLE
REG102-3.3
V
IN = VOUT + 1V
C
NR = 0.01µF
REG102-3.3
250µs/div
200µs/div
REG102
SBVS024F
7
www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
For all models, at TJ = +25°C and VENABLE = 1.8V, unless otherwise noted.
I
ENABLE vs VENABLE
POWER UP/POWER DOWN
10µ
1.0µ
100n
10n
VOUT = 3.0V
RLOAD = 12Ω
T = +25°C
T = –55°C
T = +125°C
1n
1s/div
6
7
8
9
10
VENABLE (V)
RMS NOISE VOLTAGE vs CADJ
ADJUST PIN CURRENT vs TEMPERATURE
80
70
60
50
40
30
20
0.350
0.300
0.250
0.200
0.150
0.100
0.050
0
VOUT = 3.3V
COUT = 0.1µF
10Hz < frequency < 100kHz
10
100
1k
10k
100k
–50
–25
0
25
50
75
100
125
CADJ (pF)
Temperature (°C)
LOAD TRANSIENT-ADJUSTABLE VERSION
COUT = 0
LINE TRANSIENT-ADJUSTABLE VERSION
COUT = 0
VOUT
200mV/div
200mV/div
VOUT
VOUT
IOUT
50mV/div
50mV/div
COUT = 10µF
VOUT
COUT = 10µF
REG102–A
REG102–A
VIN = 4.3V
IOUT = 250mA
CFB = 0.01µF
VOUT = 3.3V
250mA
25mA
5.3V
4.3V
VOUT = 3.3V
VIN
REG102
8
SBVS024F
www.ti.com
BASIC OPERATION
The REG102 series of LDO (low dropout) linear regulators
offers a wide selection of fixed output voltage versions and
an adjustable output version as well. The REG102 belongs
to a family of new generation LDO regulators that use a
DMOS pass transistor to achieve ultra low-dropout perfor-
mance and freedom from output capacitor constraints. Ground
pin current remains under 1mA over all line, load, and
temperature conditions. All versions have thermal and over-
current protection, including foldback current limit.
Enable
REG102
GND NR
VIN
VOUT
In
Out
COUT
0.1µF
CNR
0.01µF
Optional
The REG102 does not require an output capacitor for regulator
stability and is stable over most output currents and with almost
any value and type of output capacitor up to 10µF or more. For
applications where the regulator output current drops below
several milliamps, stability can be enhanced by adding a 1kΩ
to 2kΩ load resistor, using capacitance values smaller than
10µF, or keeping the effective series resistance greater than
0.05Ω including the capacitor ESR and parasitic resistance in
printed circuit board traces, solder joints, and sockets.
FIGURE 1. Fixed Voltage Nominal Circuit for the REG102.
the regulator from damage under all load conditions. A
characteristic of VOUT versus IOUT is given in Figure 3 and in
the Typical Characteristics section.
Although an input capacitor is not required, it is a good
standard analog design practice to connect a 0.1µF low ESR
capacitor across the input supply voltage. This is recom-
mended to counteract reactive input sources and improve
ripple rejection by reducing input voltage ripple.
CURRENT LIMIT FOLDBACK
3.5
3
REG102-3.3
2.5
ICL
2
Figure 1 shows the basic circuit connections for the fixed
voltage models. Figure 2 gives the connections for the adjust-
able output version (REG102A) and example resistor values for
some commonly used output voltages. Values for other volt-
ages can be calculated from the equation shown in Figure 2.
1.5
1
ISC
0.5
0
0
50
100 150 200 250 300 350 400 450
Output Current (mA)
INTERNAL CURRENT LIMIT
The REG102 internal current limit has a typical value of
400mA. A foldback feature limits the short-circuit current to a
typical short-circuit value of 150mA, which helps to protect
FIGURE 3. Foldback Current Limit of the REG102-3.3 at 25°C.
Enable
5
EXAMPLE RESISTOR VALUES
2
VOUT
1
VOUT (V)
2.5
R1 (Ω)(1)
R2 (Ω)(1)
VIN
CFB
0.01µF
REG102
R1
COUT
IADJ
11.3k
1.13k
11.5k
1.15k
4
0.1µF
Load
Adj
R2
3.0
3.3
5.0
15.8k
1.58k
11.5k
1.15k
3
Gnd
18.7k
1.87k
11.5k
1.15k
34.0k
3.40k
11.5k
1.15k
Optional
NOTE: (1) Resistors are standard 1% values.
Pin numbers for the SOT-223 package.
VOUT = (1 + R1/R2) • 1.26V
To reduce current through divider, increase resistor
values (see table at right).
As the impedance of the resistor divider increases,
I
ADJ (~200nA) may introduce an error.
CFB improves noise and transient response.
FIGURE 2. Adjustable Voltage Circuit for the REG102A.
REG102
SBVS024F
9
www.ti.com
ENABLE
RMS NOISE VOLTAGE vs CNR
The Enable pin is active high and compatible with standard
TTL-CMOS levels. Inputs below 0.5V (max) turn the regula-
tor off and all circuitry is disabled. Under this condition,
ground pin current drops to approximately 10nA. When not
used, the Enable pin can be connected to VIN. When a pull-
up resistor is used, and operation below 1.8V is required, use
pull-up resistor values below 50kΩ.
110
100
90
80
70
60
50
40
30
20
REG102-5.0
REG102-3.3
REG102-2.5
OUTPUT NOISE
COUT = 0µF
10Hz < BW < 100kHz
A precision bandgap reference is used to generate the
internal reference voltage, VREF. This reference is the domi-
nant noise source within the REG102 and generates approxi-
mately 29µVrms in the 10Hz to 100kHz bandwidth at the
reference output. The regulator control loop gains up the
reference noise, so that the noise voltage of the regulator is
approximately given by:
0.1
10
100
1k
10k
CNR (pF)
FIGURE 5. Output Noise versus Noise Reduction Capacitor.
Noise can be further reduced by carefully choosing an output
capacitor, COUT. Best overall noise performance is achieved
with very low (< 0.22µF) or very high (> 2.2µF) values of COUT
(see the RMS Noise Voltage vs COUT typical characteristic).
R1 +R2
VOUT
VREF
VN = 29µVrms
= 29µVrms•
(1)
R2
As the value of VREF is 1.26V, this relationship reduces to:
µVrms
The REG102 uses an internal charge pump to develop an
internal supply voltage sufficient to drive the gate of the
DMOS pass element above VIN. The charge-pump switching
noise (nominal switching frequency = 2MHz) is not measur-
able at the output of the regulator over most values of IOUT
VN = 23
• VOUT
(2)
V
Connecting a capacitor, CNR, from the Noise Reduction (NR)
pin to ground forms a low-pass filter for the voltage refer-
ence. Adding CNR (as shown in Figure 4) forms a low-pass
filter for the voltage reference. For CNR = 10nF, the total noise
in the 10Hz to 100kHz bandwidth is reduced by approxi-
mately a factor of 2.8 for VOUT = 3.3V. This noise reduction
effect is shown in Figure 5 and as RMS Noise Voltage vs CNR
in the Typical Characteristics section.
and COUT
.
The REG102 adjustable version does not have the noise-
reduction pin available; however, the adjust pin is the sum-
ming junction of the error amplifier. A capacitor, CFB, con-
nected from the output to the adjust pin can reduce both the
output noise and the peak error from a load transient (see the
typical characteristics for output noise performance).
VIN
NR
(fixed output
versions only)
CNR
Low-Noise
Charge Pump
VREF
(optional)
(1.26V)
DMOS
Output
VOUT
Over-Current
Over Temp
Protection
R1
R2
Enable
Adj
(adjustable
versions)
REG102
NOTE: R1 and R2 are internal
on fixed output versions.
FIGURE 4. Block Diagram.
10
REG102
SBVS024F
www.ti.com
DROPOUT VOLTAGE
case conditions (full-scale load change with (VIN – VOUT)
voltage drop close to DC dropout levels), the REG102 can
take several hundred microseconds to re-enter the specified
window of regulation.
The REG102 uses an N-channel DMOS as the pass element.
When (VIN – VOUT) is less than the drop-out voltage (VDROP),
the DMOS pass device behaves like a resistor; therefore, for
low values of (VIN – VOUT), the regulator input-to-output
resistance is the RdsON of the DMOS pass element (typically
600mΩ). For static (DC) loads, the REG102 typically main-
tains regulation down to a (VIN – VOUT) voltage drop of 150mV
at full rated output current. In Figure 6, the bottom line (DC
dropout) shows the minimum VIN to VOUT voltage drop re-
quired to prevent dropout under DC load conditions.
TRANSIENT RESPONSE
The REG102 response to transient line and load conditions
improves at lower output voltages. The addition of a capacitor
(nominal value 0.47µF) from the output pin to ground can
improve the transient response. In the adjustable version, the
addition of a capacitor, CFB (nominal value 10nF), from the
output to the adjust pin can also improve the transient
response.
For large step changes in load current, the REG102 requires
a larger voltage drop across it to avoid degraded transient
response. The boundary of this transient drop-out region is
shown as the top line in Figure 6 and values of VIN to VOUT
voltage drop above this line insure normal transient re-
sponse.
THERMAL PROTECTION
Power dissipated within the REG102 can cause the junction
temperature to rise. The REG102 has thermal shutdown
circuitry that protects the regulator from damage which dis-
ables the output when the junction temperature reaches
approximately 160°C, allowing the device to cool. When the
junction temperature cools to approximately 140°C, the out-
put circuitry is again enabled. Depending on various condi-
tions, the thermal protection circuit can cycle on and off. This
limits the dissipation of the regulator, but can have an
undesirable effect on the load.
DROPOUT VOLTAGE vs IOUT
350
300
250
0mA to IOUT Transient
200
Any tendency to activate the thermal protection circuit indi-
cates excessive power dissipation or an inadequate heat
sink. For reliable operation, junction temperature must be
limited to 125°C, maximum. To estimate the margin of safety
in a complete design (including heat sink), increase the
ambient temperature until the thermal protection is triggered;
use worst-case loads and signal conditions. For good reliabil-
ity, thermal protection should trigger more than 35°C above
the maximum expected ambient condition of the application.
This produces a worst-case junction temperature of 125°C at
the highest expected ambient temperature and worst-case
load.
150
DC
100
50
0
0
50
100
150
200
250
IOUT (mA)
FIGURE 6. Transient and DC Dropout.
In the transient dropout region between DC and Transient,
transient response recovery time increases. The time required
to recover from a load transient is a function of both the
magnitude and rate of the step change in load current and the
available headroom VIN to VOUT voltage drop. Under worst-
The internal protection circuitry of the REG102 is designed to
protect against overload conditions and is not intended to
replace proper heat sinking. Continuously running the REG102
into thermal shutdown will degrade reliability.
REG102
SBVS024F
11
www.ti.com
POWER DISSIPATION
PD = (VIN – VOUT) • IOUT
(3)
The REG102 is available in three different package configu-
rations. The ability to remove heat from the die is different for
each package type and, therefore, presents different consid-
erations in the printed circuit board (PCB) layout. The PCB
area around the device that is free of other components
moves the heat from the device to the ambient air. Although
it is difficult to impossible to quantify all of the variables in a
thermal design of this type, performance data for several
simplified configurations are shown in Figure 7. In all cases,
the PCB copper area is bare copper (free of solder resist
mask), not solder plated, and are for 1-ounce copper. Using
heavier copper will increase the effectiveness in moving the
heat from the device. In those examples where there is
copper on both sides of the PCB, no connection has been
provided between the two sides. The addition of plated
through holes will improve the heat sink effectiveness.
Power dissipation can be minimized by using the lowest
possible input voltage necessary to assure the required
output voltage.
REGULATOR MOUNTING
The tab of the SOT-223 package is electrically connected to
ground. For best thermal performance, this tab must be
soldered directly to a circuit-board copper area. Increasing
the copper area improves heat dissipation, as shown in
Figure 8.
Although the tab of the SOT-223 is electrical ground, it is not
intended to carry current. The copper pad that acts as a heat
sink should be isolated from the rest of the circuit to prevent
current flow through the device from the tab to the ground
pin. Solder pad footprint recommendations for the various
REG102 devices are presented in Application Bulletin Solder
Pad Recommendations for Surface-Mount Devices
(SBFA015), available from the Texas Instruments web site
(www.ti.com).
Power dissipation depends on input voltage, load conditions,
and duty cycle and is equal to the product of the average
output current times the voltage across the output element,
VIN to VOUT voltage drop.
DEVICE DISSIPATION vs TEMPERATURE
2.5
CONDITIONS
#1
2
1.5
1
#2
#3
#4
CONDITION
PACKAGE
PCB AREA
θJA
1
2
3
4
SOT-223
SOT-223
SO-8
4in2 Top Side Only
0.5in2 Top Side Only
53°C/W
110°C/W
150°C/W
200°C/W
—
—
SOT-23
0.5
0
0
25
50
75
100
125
Ambient Temperature (°C)
FIGURE 7. Maximum Power Dissipation versus Ambient Temperature for the Various Packages and PCB Heat Sink Configurations.
THERMAL RESISTANCE vs PCB COPPER AREA
180
160
140
120
100
80
Circuit-Board Copper Area
REG102
Surface-Mount Package
1 oz. copper
θ
60
40
20
REG102
SOT-223 Surface-Mount Package
0
0
1
2
3
4
5
Copper Area (inches2)
FIGURE 8. Thermal Resistance versus PCB Area for the Five-Lead SOT-223.
REG102
12
SBVS024F
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
22-Jun-2017
PACKAGING INFORMATION
Orderable Device
REG102GA-2.5
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
SOT-223
SOT-223
SOT-223
SOT-223
SOT-223
SOT-223
SOT-223
SOT-223
SOT-223
SOT-223
SOT-223
SOT-223
SOT-223
SOT-223
SOT-223
SOT-23
DCQ
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
5
5
78
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
R102G25
REG102GA-2.5G4
REG102GA-2.85
REG102GA-2.85G4
REG102GA-3
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DCQ
DCQ
DCQ
DCQ
DCQ
DCQ
DCQ
DCQ
DCQ
DCQ
DCQ
DCQ
DCQ
DCQ
DBV
DBV
78
78
Green (RoHS
& no Sb/Br)
R102G25
R102285
R102285
R102G30
R102G33
R102G33
R102G33
R102G30
R102G50
R102G50
R102GA
R102GA
R102GA
R102GA
RO2D
Green (RoHS
& no Sb/Br)
78
Green (RoHS
& no Sb/Br)
78
Green (RoHS
& no Sb/Br)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
REG102GA-3.3
78
Green (RoHS
& no Sb/Br)
REG102GA-3.3/2K5
REG102GA-3.3G4
REG102GA-3G4
REG102GA-5
2500
78
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
78
Green (RoHS
& no Sb/Br)
78
Green (RoHS
& no Sb/Br)
REG102GA-5G4
REG102GA-A
78
Green (RoHS
& no Sb/Br)
78
Green (RoHS
& no Sb/Br)
REG102GA-A/2K5
REG102GA-A/2K5G4
REG102GA-AG4
REG102NA-2.5/250
REG102NA-2.5/250G4
2500
2500
78
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
250
250
Green (RoHS
& no Sb/Br)
SOT-23
Green (RoHS
& no Sb/Br)
RO2D
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
22-Jun-2017
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
REG102NA-2.8/250
REG102NA-2.8/250G4
REG102NA-2.85/250
REG102NA-2.85/3K
REG102NA-3.3/250
REG102NA-3.3/250G4
REG102NA-3.3/3K
REG102NA-3.3/3KG4
REG102NA-3/250
ACTIVE
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
RO2E
RO2E
RO2N
RO2N
RO2C
RO2C
RO2C
RO2C
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
250
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
250
Green (RoHS
& no Sb/Br)
3000
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
RO2G
RO2G
RO2G
RO2G
RO2B
RO2B
RO2B
RO2B
RO2A
RO2A
REG102NA-3/250G4
REG102NA-3/3K
250
Green (RoHS
& no Sb/Br)
3000
3000
250
Green (RoHS
& no Sb/Br)
REG102NA-3/3KG4
REG102NA-5/250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
REG102NA-5/250G4
REG102NA-5/3K
250
Green (RoHS
& no Sb/Br)
3000
3000
250
Green (RoHS
& no Sb/Br)
REG102NA-5/3KG4
REG102NA-A/250
REG102NA-A/250G4
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
250
Green (RoHS
& no Sb/Br)
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
22-Jun-2017
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
REG102NA-A/3K
REG102UA-2.5
REG102UA-3
ACTIVE
SOT-23
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
DBV
5
8
8
8
8
8
8
8
8
8
8
8
8
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
RO2A
REG
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
NRND
D
D
D
D
D
D
D
D
D
D
D
D
D
75
75
Green (RoHS
& no Sb/Br)
102U25
Green (RoHS
& no Sb/Br)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
REG
102U30
REG102UA-3.3
REG102UA-3.3/2K5
REG102UA-3.3G4
REG102UA-3G4
REG102UA-5
75
Green (RoHS
& no Sb/Br)
REG
102U33
2500
75
Green (RoHS
& no Sb/Br)
REG
102U33
Green (RoHS
& no Sb/Br)
REG
102U33
75
Green (RoHS
& no Sb/Br)
REG
102U30
75
Green (RoHS
& no Sb/Br)
REG
102U50
REG102UA-5/2K5
REG102UA-5/2K5G4
REG102UA-5G4
REG102UA-A
2500
2500
75
Green (RoHS
& no Sb/Br)
REG
102U50
Green (RoHS
& no Sb/Br)
REG
102U50
Green (RoHS
& no Sb/Br)
REG
102U50
75
Green (RoHS
& no Sb/Br)
REG
102UA
REG102UA-A/2K5
REG102UA-AG4
NRND
2500
75
Green (RoHS
& no Sb/Br)
REG
102UA
NRND
Green (RoHS
& no Sb/Br)
REG
102UA
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
22-Jun-2017
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
REG102GA-3.3/2K5
REG102GA-A/2K5
REG102NA-2.5/250
REG102NA-2.8/250
REG102NA-2.8/250
REG102NA-2.85/250
REG102NA-2.85/250
REG102NA-2.85/3K
REG102NA-2.85/3K
REG102NA-3.3/250
REG102NA-3.3/250
REG102NA-3.3/3K
REG102NA-3.3/3K
REG102NA-3/250
REG102NA-3/250
REG102NA-3/3K
SOT-223 DCQ
SOT-223 DCQ
6
6
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
2500
2500
250
330.0
330.0
179.0
178.0
179.0
179.0
178.0
179.0
178.0
179.0
178.0
179.0
178.0
178.0
179.0
179.0
178.0
178.0
12.4
12.4
8.4
9.0
8.4
8.4
9.0
8.4
9.0
8.4
9.0
8.4
9.0
9.0
8.4
8.4
9.0
9.0
7.1
7.1
7.45
7.45
3.2
1.88
1.88
1.4
8.0
8.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
12.0
12.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
3.2
250
3.23
3.2
3.17
3.2
1.37
1.4
250
250
3.2
3.2
1.4
250
3.23
3.2
3.17
3.2
1.37
1.4
3000
3000
250
3.23
3.2
3.17
3.2
1.37
1.4
250
3.23
3.2
3.17
3.2
1.37
1.4
3000
3000
250
3.23
3.23
3.2
3.17
3.17
3.2
1.37
1.37
1.4
250
3000
3000
250
3.2
3.2
1.4
REG102NA-3/3K
3.23
3.23
3.17
3.17
1.37
1.37
REG102NA-5/250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
REG102NA-5/250
REG102NA-5/3K
REG102NA-5/3K
REG102NA-A/250
REG102NA-A/3K
REG102UA-3.3/2K5
REG102UA-5/2K5
REG102UA-A/2K5
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOIC
DBV
DBV
DBV
DBV
DBV
D
5
5
5
5
5
8
8
8
250
3000
3000
250
179.0
179.0
178.0
179.0
179.0
330.0
330.0
330.0
8.4
8.4
3.2
3.2
3.23
3.2
3.2
6.4
6.4
6.4
3.2
3.2
3.17
3.2
3.2
5.2
5.2
5.2
1.4
1.4
1.37
1.4
1.4
2.1
2.1
2.1
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
Q3
Q1
Q1
Q1
9.0
8.0
8.4
8.0
3000
2500
2500
2500
8.4
8.0
12.4
12.4
12.4
12.0
12.0
12.0
SOIC
D
SOIC
D
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
REG102GA-3.3/2K5
REG102GA-A/2K5
REG102NA-2.5/250
REG102NA-2.8/250
REG102NA-2.8/250
REG102NA-2.85/250
REG102NA-2.85/250
REG102NA-2.85/3K
REG102NA-2.85/3K
SOT-223
SOT-223
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DCQ
DCQ
DBV
DBV
DBV
DBV
DBV
DBV
DBV
6
6
5
5
5
5
5
5
5
2500
2500
250
346.0
346.0
203.0
180.0
203.0
203.0
180.0
203.0
180.0
346.0
346.0
203.0
180.0
203.0
203.0
180.0
203.0
180.0
29.0
29.0
35.0
18.0
35.0
35.0
18.0
35.0
18.0
250
250
250
250
3000
3000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
REG102NA-3.3/250
REG102NA-3.3/250
REG102NA-3.3/3K
REG102NA-3.3/3K
REG102NA-3/250
REG102NA-3/250
REG102NA-3/3K
REG102NA-3/3K
REG102NA-5/250
REG102NA-5/250
REG102NA-5/3K
REG102NA-5/3K
REG102NA-A/250
REG102NA-A/3K
REG102UA-3.3/2K5
REG102UA-5/2K5
REG102UA-A/2K5
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOIC
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
D
5
5
5
5
5
5
5
5
5
5
5
5
5
5
8
8
8
250
250
203.0
180.0
203.0
180.0
180.0
203.0
203.0
180.0
180.0
203.0
203.0
180.0
203.0
203.0
367.0
367.0
367.0
203.0
180.0
203.0
180.0
180.0
203.0
203.0
180.0
180.0
203.0
203.0
180.0
203.0
203.0
367.0
367.0
367.0
35.0
18.0
35.0
18.0
18.0
35.0
35.0
18.0
18.0
35.0
35.0
18.0
35.0
35.0
35.0
35.0
35.0
3000
3000
250
250
3000
3000
250
250
3000
3000
250
3000
2500
2500
2500
SOIC
D
SOIC
D
Pack Materials-Page 3
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
B
1.45 MAX
A
PIN 1
INDEX AREA
1
2
5
2X 0.95
1.9
3.05
2.75
1.9
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/C 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/C 04/2017
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/C 04/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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