SC1200UFH-266B [TI]
暂无描述;
| 型号： | SC1200UFH-266B |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 暂无描述 时钟 外围集成电路 |
| 文件： | 总447页 (文件大小：3841K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 2003
Revision 6.0
Geode™ SC1200/SC1201
Set-Top Box On a Chip
General Description
The Geode™ SC1200/SC1201 Set-Top Box On a Chip
device is a member of the National Semiconductor® IA
(Information Appliance) On a Chip family of fully integrated
x86 system chips. The Geode SC1200/SC1201 includes:
• The Core Logic module includes: PC/AT functionality, a
USB interface, an IDE interface, a PCI bus interface, an
LPC bus interface, Advanced Configuration Power Inter-
face (ACPI) version 1.0 compliant power management,
and an audio codec interface.
• The Geode GX1 processor module combines advanced
CPU performance with Intel MMX support, fully acceler-
ated 2D graphics, a 64-bit synchronous DRAM
(SDRAM) interface, a PCI bus controller, and a display
controller.
• The SuperI/O module has: three serial ports (UART1,
UART2, and UART3 with fast infrared), a parallel port,
two ACCESS.bus (ACB) interfaces, and a real-time
clock (RTC).
• A low-power CRT and TFT Video Processor module with
a hardware video accelerator for scaling, filtering, and
color space conversion, a Video Input Port (VIP), and an
NTSC/PAL TV encoder. The SC1201 (only) has Macro-
vision copy protection support (see "Macrovision
Product Notice" on page 445).
The block diagram shows the relationships between the
modules.
These features, combined with the device’s small form fac-
tor and low power consumption, make it ideal as the core
for a set-top box or an advanced multimedia-type device.
Block Diagram
GX1
Video Processor
Memory Controller
Display
CRT I/F
Controller
2D Graphics
Accelerator
Video
Scaling
Video
Mixer
TFT I/F
TV I/F
CPU
Core
Config.
Block
PCI Bus
Controller
VOP
Video Input Port (VIP)
Host Interface
Fast-PCI Bus
Clock & Reset Logic
Fast X-Bus
Parallel
Port
Core Logic
IDE I/F
RTC
ACB1
I/F
Bridge
USB
PIT
PIC
ACB2
I/F
SuperI/O
PCI/Sub-ISA
Bus I/F
DMAC
UART1
UART2
GPIO
Pwr Mgmnt
Configuration
ISA Bus I/F
Audio Codec I/F
LPC I/F
ISA Bus
I/F
UART3
& IR
X-Bus
National Semiconductor and Virtual System Architecture are registered trademarks of National Semiconductor Corporation.
Geode and VSA are trademarks of National Semiconductor Corporation.
For a complete listing of National Semiconductor trademarks, please visit www.national.com/trademarks.
© 2003 National Semiconductor Corporation
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Features
Video Processor Module
General Features
■ Video Accelerator:
■ 32-Bit x86 processor, up to 266 MHz, with MMX instruc-
— Flexible video scaling support of up to 8x (horizon-
tally and vertically)
— Bilinear interpolation filters (with two taps, and eight
phases) to smooth output video
tion set support
■ Memory controller with 64-bit SDRAM interface
■ 2D graphics accelerator
■ Video/Graphics Mixer:
■ CRT controller with hardware video accelerator
— 8-Bit value alpha blending
— Three blending windows with constant alpha value
— Color key
■ CCIR-656 video input port with direct video for full
screen display
■ PC/AT functionality
■ Video Input Port (VIP):
— Video capture or display
— CCIR-656 and VESA Video Interface Port Rev 1.1
compliant
■ PCI bus controller
■ IDE interface, two channels
— Lock display timing to video input timing (GenLock)
— Able to transfer video data into main memory
— Direct video transfer for full screen display
— Separate memory location for VBI
■ USB, three ports, OHCI (OpenHost Controller Interface)
version 1.0 compliant
■ Audio, AC97/AMC97 version 2.0 compliant
■ Virtual System Architecture® technology (VSA™)
■ Video Output Port (VOP):
support
— VESA Video Interface Port Rev. 1.1 Task B format
■ Power management, ACPI (Advanced Configuration
■ CRT Interface:
Power Interface) version 1.0 compliant
— Uses three 8-bit DACs
— Support up to 135 MHz
— 1280x1024 non-interlaced CRT @ 8 bpp, up to 75 Hz
— 1024x768 non-interlaced CRT @ 16 bpp, up to 85 Hz
■ Package:
— 432-Terminal EBGA (Enhanced Ball Grid Array)
— 481-Terminal TEPBGA (Thermally Enhanced Plastic
Ball Grid Array)
■ TFT Interface:
— Direct connection to TFT panels
— 800x600 non-interlaced TFT @ 16 bpp graphics, up
to 75 Hz
— 1024x768 non-interlaced TFT @ 16 bpp graphics, up
to 75 Hz
— Connects to Geode CS9211 companion for DSTN
panel support
— TFT on IDE: FPCLK max is 40 MHz
— TFT on Parallel Port: FPCLK max is 80 MHz
GX1 Processor Module
■ CPU Core:
— 32-Bit x86, 266 MHz, with MMX compatible instruc-
tion set support
— 16 KB unified L1 cache
— Integrated Floating Point Unit (FPU)
— Re-entrant SMM (System Management Mode)
enhanced for VSA
■ TV Interface:
■ 2D Graphics Accelerator:
— TEPBGA package does not support simultaneous
TV/CRT or TV/TFT operation
— Uses four 10-bit DACs
— 720x480 NTSC @ 60 Hz or 720x576 PAL @ 50 Hz
— NTSC-M, PAL-M/B/D/G/H/I
— Accelerates BitBLTs, line draw and text
— Supports all 256 raster operations
— Supports transparent BLTs
— Runs at core clock frequency
— Luminance filtering with 2x oversampling and sinx/x
correction
■ Memory Controller:
— 64-Bit SDRAM interface
— Chrominance filtering with 4x oversampling
— Flicker filter with a three-line buffer for graphics
display on TV
— 66 MHz to 100 MHz frequency range
— Direct interface with CPU/cache, display controller
and 2D graphic accelerator
— Composite, S-Video and YCrCb component video
outputs
— Supports clock suspend and power-down/self-
refresh
— Analog video output interface supports SCART stan-
dard (both RGBCvbs and YCCvbs)
— Support for VBI (Vertical Blanking Interval) transfer
from Video Port input to TV Encoder
— Up to two banks of SDRAM (8 devices total) or one
SODIMM
■ Display Controller:
— Hardware graphics frame buffer compress/decom-
press
— Hardware cursor, 32x32 pixels
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2
Revision 6.0
Features (Continued)
— VBI Generation Support:
■ IDE Interface:
– Wide Screen Signaling (WSS)
– Closed caption
– Extended Data Services (EDS)
— Two IDE channels for up to four external IDE devices
— Supports ATA-33 synchronous DMA mode transfers,
up to 33 MB/s
– Copy Generation Management System (CGMS)
— Four-field NTSC or eight-field PAL generation
— Macrovision copy protection version 7.1.L1 (SC1201
only, see "Macrovision Product Notice" on page 445)
■ Universal Serial Bus (USB):
— USB OpenHCI 1.0 compliant
— Three ports
SuperI/O Module
Core Logic Module
■ Real-Time Clock (RTC):
■ Audio Codec Interface:
— DS1287, MC146818 and PC87911 compatible
— Multi-century calendar
— AC97/AMC97 (Rev. 2.0) codec interface
— Six DMA channels
■ ACCESS.bus (ACB) Interface:
■ PC/AT Functionality:
— Two ACB interface ports
— Programmable Interrupt Controller (PIC), 8259A-
equivalent
■ Parallel Port:
— Programmable Interval Timer (PIT), 8254-equivalent
— DMA Controller (DMAC), 8237-equivalent
— EPP 1.9 compliant
— IEEE 1284 ECP compliant, including level 2
■ Power Management:
■ Serial Port (UART):
— ACPI 1.0 compliant
— UART1, 16550A compatible (SIN, SOUT, BOUT
pins), used for SmartCard interface
— UART2, 16550A compatible
— Sx state control of three power planes
— Cx/Sx state control of clocks and PLLs
— Thermal event input
— Enhanced UART with fast Infrared (IR)
— Wakeup event support:
– Three general-purpose events
– AC97 codec event
Other Features
■ High-Resolution Timer:
– UART2 RI# signal
– Infrared (IR) event
— 32-Bit counter with 1 µs count interval
■ WATCHDOG Timer:
■ General Purpose I/Os (GPIOs):
— Interfaces to INTR, SMI, Reset
— 27 multiplexed GPIO signals
■ Clocks:
■ Low Pin Count (LPC) Bus Interface:
— Input (external crystals):
– 32.768 KHz (internal clock oscillator)
– 27 MHz (internal clock oscillator)
— Output:
— Specification version 1.0 compatible
■ PCI Bus Interface:
— PCI version 2.1 compliant with wakeup capability
— 32-Bit data path, up to 33 MHz
— Glueless interface for an external PCI device
— Fixed priority
– AC97 clock (24.576 MHz)
– Memory controller clock (66 MHz to 100 MHz)
– PCI clock (33 MHz)
— 3.3V signal support only
■ JTAG Testability:
■ Sub-ISA Bus Interface:
— Bypass, Extest, Sample/Preload, IDcode, Clamp, HiZ
— Up to 16 MB addressing
— Supports a chip select for ROM or Flash EPROM
boot device
■ Voltages:
— Internal logic: 266 MHz @ 1.8V
— Battery: 3V
— I/O: 3.3V
— Supports either:
– M-Systems DiskOnChip DOC2000 Flash file
system
— Standby: 3.3V
– NAND EEPROM
— Supports up to two chip selects for external I/O
devices
— 8-Bit (optional 16-bit) data bus width
— Shares balls with PCI signals
— Is not a subtractive agent
Revision 6.0
3
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Table of Contents
1.0 Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.1
GX1 MODULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.1.1
1.1.2
1.1.3
Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Fast-PCI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.2
VIDEO PROCESSOR MODULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.2.1
1.2.2
1.2.3
1.2.4
GX1 Module Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Video Input Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Core Logic Module Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
CRT DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.3
CORE LOGIC MODULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.3.1 Other Interfaces of the Core Logic Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.4
1.5
SUPERI/O MODULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
CLOCK, TIMERS, AND RESET LOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.5.1
Reset Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.5.1.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.5.1.2 System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.0 Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.1
2.2
2.3
2.4
BALL ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
STRAP OPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
MULTIPLEXING CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
2.4.6
2.4.7
2.4.8
2.4.9
System Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Memory Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Video Port Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
CRT/TFT Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
TV Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
ACCESS.bus Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
PCI Bus Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Sub-ISA Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Low Pin Count (LPC) Bus Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
2.4.10 IDE Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
2.4.11 Universal Serial Bus (USB) Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
2.4.12 Serial Ports (UARTs) Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
2.4.13 Parallel Port Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
2.4.14 Fast Infrared (IR) Port Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
2.4.15 AC97 Audio Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
2.4.16 Power Management Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
2.4.17 GPIO Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
2.4.18 Debug Monitoring Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
2.4.19 JTAG Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
2.4.20 Test and Measurement Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
2.4.21 Power and Ground Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
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4
Revision 6.0
Table of Contents (Continued)
3.0 General Configuration Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.1
3.2
3.3
CONFIGURATION BLOCK ADDRESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
MULTIPLEXING, INTERRUPT SELECTION, AND BASE ADDRESS REGISTERS . . . . . . . . 86
WATCHDOG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
3.3.1
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
3.3.1.1 WATCHDOG Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
WATCHDOG Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
3.3.2.1 Usage Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
3.3.2
3.4
3.5
HIGH-RESOLUTION TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
3.4.1
3.4.2
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
High-Resolution Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
3.4.2.1 Usage Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
CLOCK GENERATORS AND PLLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
3.5.1
3.5.2
3.5.3
3.5.4
3.5.5
3.5.6
3.5.7
27 MHz Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
GX1 Module Core Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Internal Fast-PCI Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
SuperI/O Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Core Logic Module Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Video Processor Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Clock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.0 SuperI/O Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.1
4.2
4.3
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
MODULE ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
CONFIGURATION STRUCTURE / ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
4.3.1
4.3.2
4.3.3
4.3.4
Index-Data Register Pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Banked Logical Device Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Default Configuration Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Address Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
4.4
STANDARD CONFIGURATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
4.4.1
4.4.2
SIO Control and Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Logical Device Control and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
4.4.2.1 LDN 00h - Real-Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
4.4.2.2 LDN 01h - System Wakeup Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
4.4.2.3 LDN 02h - Infrared Communication Port or Serial Port 3 . . . . . . . . . . . . . . . . . . . . 115
4.4.2.4 LDN 03h and 08h - Serial Ports 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
4.4.2.5 LDN 05h and 06h - ACCESS.bus Ports 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
4.4.2.6 LDN 07h - Parallel Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
4.5
REAL-TIME CLOCK (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
4.5.1
4.5.2
Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
RTC Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
4.5.2.1 Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
4.5.2.2 External Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
4.5.2.3 Timing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
4.5.2.4 Timekeeping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
4.5.2.5 Alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
4.5.2.6 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
4.5.2.7 System Power States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
4.5.2.8 Oscillator Activity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
4.5.2.9 Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
4.5.2.10 Battery-Backed RAMs and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
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4.5.3
RTC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
4.5.3.1 Usage Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
4.5.4
RTC General-Purpose RAM Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
4.6
4.7
SYSTEM WAKEUP CONTROL (SWC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
4.6.1
Event Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
4.6.1.1 Audio Codec Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
4.6.1.2 CEIR Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
4.6.2
SWC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
ACCESS.BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
4.7.1
4.7.2
4.7.3
4.7.4
4.7.5
4.7.6
4.7.7
Data Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Start and Stop Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Acknowledge (ACK) Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Acknowledge After Every Byte Rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Addressing Transfer Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Arbitration on the Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
4.7.7.1 Master Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
4.7.8
4.7.9
4.7.10 ACB Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
LEGACY FUNCTIONAL BLOCKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
4.8
4.8.1
Parallel Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
4.8.1.1 Parallel Port Register and Bit Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
UART Functionality (SP1 and SP2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
4.8.2
4.8.2.1 UART Mode Register Bank Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
4.8.2.2 SP1 and SP2 Register and Bit Maps for UART Functionality . . . . . . . . . . . . . . . . . 145
4.8.3
IR Communications Port (IRCP) / Serial Port 3 (SP3) Functionality . . . . . . . . . . . . 149
4.8.3.1 IR/SP3 Mode Register Bank Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
4.8.3.2 IRCP/SP3 Register and Bit Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
5.0 Core Logic Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
5.1
5.2
FEATURE LIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
MODULE ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
5.2.1
Fast-PCI Interface to External PCI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
5.2.1.1 Processor Mastered Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
5.2.1.2 External PCI Mastered Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
5.2.1.3 Core Logic Internal or Sub-ISA Mastered Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . 157
5.2.1.4 External PCI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
5.2.1.5
Bus Master Request Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
5.2.2
5.2.3
PSERIAL Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
5.2.2.1 Video Retrace Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
IDE Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
5.2.3.1 IDE Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
5.2.3.2 PIO Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
5.2.3.3 Bus Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
5.2.3.4 UltraDMA/33 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
5.2.4
Universal Serial Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
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5.2.5
Sub-ISA Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
5.2.5.1 Sub-ISA Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
5.2.5.2 Sub-ISA Support of Delayed PCI Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
5.2.5.3 Sub-ISA Bus Data Steering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
5.2.5.4 I/O Recovery Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
5.2.5.5 ISA DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
5.2.5.6 ROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
5.2.5.7 PCI and Sub-ISA Signal Cycle Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
5.2.6
5.2.7
AT Compatibility Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
5.2.6.1 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
5.2.6.2 Programmable Interval Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
5.2.6.3 Programmable Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
I/O Ports 092h and 061h System Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
5.2.7.1 I/O Port 092h System Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
5.2.7.2 I/O Port 061h System Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
5.2.7.3 SMI Generation for NMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
5.2.8
5.2.9
Keyboard Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
5.2.8.1 Fast Keyboard Gate Address 20 and CPU Reset . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Power Management Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
5.2.9.1 CPU States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
5.2.9.2 Sleep States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
5.2.9.3 Power Planes Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
5.2.9.4 Power Management Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
5.2.9.5 Usage Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
5.2.10 Power Management Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
5.2.10.1 APM Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
5.2.10.2 CPU Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
5.2.10.3 Peripheral Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
5.2.10.4 Power Management Programming Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
5.2.11 GPIO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
5.2.12 Integrated Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
5.2.12.1 Data Transport Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
5.2.12.2 AC97 Codec Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
5.2.12.3 VSA Technology Support Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
5.2.12.4 IRQ Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
5.2.12.5 LPC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
5.2.12.6 LPC Interface Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
5.2.12.7 Cycle Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
5.2.12.8 LPC Interface Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
5.3
5.4
REGISTER DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
5.3.1
5.3.2
PCI Configuration Space and Access Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
CHIPSET REGISTER SPACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
5.4.1
Bridge, GPIO, and LPC Registers - Function 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
5.4.1.1 GPIO Support Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
5.4.1.2 LPC Support Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
5.4.2
SMI Status and ACPI Registers - Function 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
5.4.2.1 SMI Status Support Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
5.4.2.2 ACPI Support Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
5.4.3
5.4.4
5.4.5
IDE Controller Registers - Function 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
5.4.3.1 IDE Controller Support Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Audio Registers - Function 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
5.4.4.1 Audio Support Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
X-Bus Expansion Interface - Function 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
5.4.5.1 X-Bus Expansion Support Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
USB Controller Registers - PCIUSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
ISA Legacy Register Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
5.4.6
5.4.7
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6.0 Video Processor Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
6.1
6.2
MODULE ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
6.2.1
Video Input Port (VIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
6.2.1.1 Direct Video Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
6.2.1.2 Direct VBI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
6.2.1.3 Capture Video Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
6.2.1.4 Capture VBI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
6.2.2
Video Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
6.2.2.1 Video Input Formatter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
6.2.2.2 Horizontal Downscaler with 4-Tap Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
6.2.2.3 Line Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
6.2.2.4 Formatter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
6.2.2.5 2-Tap Vertical and Horizontal Upscalers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
6.2.3
6.2.4
Mixer/Blender Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
6.2.3.1 YUV to RGB CSC in Video Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
6.2.3.2 Gamma Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
6.2.3.3 RGB to YUV CSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
6.2.3.4 1/2 Y Flicker Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
6.2.3.5 Color/Chroma Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
6.2.3.6 Color/Chroma Key and Mixer/Blender . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
TVOUT Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
6.2.4.1 Flicker Filter and Scan Rate Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
6.2.4.2 Pre-Encoder Horizontal Scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
6.2.4.3 Video Output Port (VOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
6.2.4.4 TV Encoder Timing Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
6.2.4.5 TV Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
6.2.5
6.2.6
6.2.7
6.2.8
VESA DDSC2B and DPMS Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
Integrated DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
TFT Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
Integrated PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
6.3
REGISTER DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
6.3.1
6.3.2
Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
Video Processor Registers - Function 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
6.3.2.1 Video Processor Support Registers - F4BAR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
6.3.2.2 VIP Support Registers - F4BAR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
7.0 Debugging and Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
7.1
TESTABILITY (JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
7.1.1
7.1.2
7.1.3
Mandatory Instruction Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
Optional Instruction Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
JTAG Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
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Revision 6.0
Table of Contents (Continued)
8.0 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
8.1
GENERAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
8.1.1
8.1.2
8.1.3
8.1.4
Power/Ground Connections and Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
DC Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
8.1.4.1 Power State Parameter Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
8.1.4.2 Definition and Measurement Techniques of SC1200/SC1201 Current Parameters 373
8.1.4.3 Definition of System Conditions for Measuring On Parameters . . . . . . . . . . . . . . . . 374
8.1.4.4 DC Current Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
8.1.5
8.1.6
Ball Capacitance and Inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
Pull-Up and Pull-Down Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
8.2
DC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
8.2.8
8.2.9
IN DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
AB
IN
IN
IN
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
BTN
PCI
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
STRP
IN DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
T
IN DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
TS
IN
IN
O
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
TS1
USB
AC97
8.2.10 OD DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
n
8.2.11 OD
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
PCI
8.2.12
8.2.13
8.2.14
O
O
O
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
p/n
PCI
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
USB
8.2.15 TS DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
p/n
8.2.15.1 Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
8.3
AC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
Memory Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
Video Port (VP) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
CRT and TFT Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
TV Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
ACCESS.bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
PCI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
8.3.6.1 Measurement and Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
Sub-ISA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
LPC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
IDE Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
8.3.7
8.3.8
8.3.9
8.3.10 Universal Serial Bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
8.3.11 Serial Port (UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
8.3.12 Fast IR Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
8.3.13 Parallel Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
8.3.13.1 Extended Capabilities Port (ECP) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
8.3.14 Audio Interface Timing (AC97) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
8.3.15 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438
8.3.16 Power-Up Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
8.3.17 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
Revision 6.0
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Table of Contents (Continued)
9.0 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
Appendix A Support Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
A.1
A.2
A.3
ORDER INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
MACROVISION PRODUCT NOTICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
DATASHEET REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
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Revision 6.0
1.0 Architecture Overview
As illustrated in Figure 1-1, the SC1200/SC1201 contains
• Core Logic Module:
the following modules in one integrated device:
— Includes PC/AT functionality, an IDE interface, a
Universal Serial Bus (USB) interface, ACPI 1.0
compliant power management, and an audio codec
interface.
• GX1 Module:
— Combines advanced CPU performance with MMX
support, fully accelerated 2D graphics, a 64-bit
synchronous DRAM (SDRAM) interface and a PCI
bus controller. Integrates GX1 silicon revision 8.1.1.
• SuperI/O Module:
— Includes two Serial Ports, an Infrared (IR) Port, a
Parallel Port, two ACCESS.bus interfaces, and a
Real-Time Clock (RTC).
• Video Processor Module:
— A low-power CRT and TFT support module with a
hardware video accelerator for scaling, filtering and
color space conversion, and a video input port (VIP).
Includes an NTSC/PAL TV encoder.
GX1
Video Processor
Memory Controller
Display
CRT I/F
Controller
2D Graphics
Accelerator
Video
Scaling
Video
Mixer
TFT I/F
TV I/F
CPU
Core
Config.
Block
PCI Bus
Controller
VOP
Video Input Port (VIP)
Host Interface
Fast-PCI Bus
Clock & Reset Logic
Fast X-Bus
Parallel
Port
Core Logic
IDE I/F
RTC
ACB1
I/F
Bridge
USB
PIT
PIC
ACB2
I/F
SuperI/O
PCI/Sub-ISA
Bus I/F
DMAC
UART1
UART2
GPIO
Pwr Mgmnt
Configuration
ISA Bus I/F
Audio Codec I/F
LPC I/F
ISA Bus
I/F
UART3
& IR
X-Bus
Figure 1-1. SC1200/SC1201 Block Diagram
Revision 6.0
11
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Architecture Overview (Continued)
1.1 GX1 MODULE
The GX1 processor (silicon revision 8.1.1) is the central
module of the SC1200/SC1201. For detailed information
regarding the GX1 module, refer to the Geode GX1 Pro-
cessor Series datasheet and the Geode GX1 Processor
Series Silicon Revision 8.1.1 errata.
There are some differences in the SC1200/SC1201’s mem-
ory controller and the stand-alone GX1 processor’s mem-
ory controller:
1) There is drive strength/slew control in the
SC1200/SC1201 that is not in the GX1. The bits that
control this function are in the MC_MEM_CNTRL1 and
MC_MEM_CNTRL2 registers. In the GX1 processor,
these bits are marked as reserved.
The SC1200/SC1201’s device ID is contained in the GX1
module. Software can detect the revision by reading the
DIR0 and DIR1 Configuration registers (see Configuration
registers in the Geode GX1 Processor Series datasheet).
The SC1200/SC1201 device errata contains the specific
values.
2) The SC1200/SC1201 supports two banks of memory.
The GX1 supports four banks of memory. In addition,
the SC1200/SC1201 supports a maximum of eight
devices and the GX1 supports up to 32 devices. With
this difference, the MC_BANK_CFG register is differ-
ent.
1.1.1 Memory Controller
The GX1 module is connected to external SDRAM devices.
For more information see Section 2.4.2 "Memory Interface
Signals" on page 61, and the “Memory Controller” chapter
in the GX1 Processor Series datasheet.
Table 1-1 summarizes the 32-bit registers contained in the
SC1200/SC1201’s memory controller. Table 1-2 gives
detailed register/bit formats.
Table 1-1. SC1200/SC1201 Memory Controller Register Summary
Width
GX_BASE+
Memory Offset
(Bits)
Type
Name/Function
Reset Value
8400h-8403h
8404h-8407h
8408h-840Bh
840Ch-840Fh
32
32
32
32
R/W
R/W
R/W
R/W
MC_MEM_CNTRL1. Memory Controller Control Register 1
MC_MEM_CNTRL2. Memory Controller Control Register 2
MC_BANK_CFG. Memory Controller Bank Configuration
248C0040h
00000801h
41104110h
2A733225h
MC_SYNC_TIM1. Memory Controller Synchronous Timing
Register 1
8414h-8417h
8418h-841Bh
841Ch-841Fh
32
32
32
R/W
R/W
R/W
MC_GBASE_ADD. Memory Controller Graphics Base
Address Register
00000000h
00000000h
0000000xh
MC_DR_ADD. Memory Controller Dirty RAM Address
Register
MC_DR_ACC. Memory Controller Dirty RAM Access
Register
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12
Revision 6.0
Architecture Overview (Continued)
Table 1-2. SC1200/SC1201 Memory Controller Registers
Bit
Description
GX_BASE+ 8400h-8403h
MC_MEM_CNTRL1 (R/W)
Reset Value: 248C0040h
31:30
29
MDCTL (MD[63:0] Drive Strength). 11 is strongest, 00 is weakest.
RSVD (Reserved) Write as 0.
28:27
26
MABACTL (MA[12:0] and BA[1:0] Drive Strength). 11 is strongest, 00 is weakest.
RSVD (Reserved). Write as 0.
25:24
23:22
21
MEMCTL (RASA#, CASA#, WEA#, CS[1:0]#, CKEA, DQM[7:0] Drive Strength). 11 is strongest, 00 is weakest.
RSVD (Reserved). Write as 0.
RSVD (Reserved). Must be written as 0. Wait state on the X-Bus x_data during read cycles - for debug only.
SDCLKRATE (SDRAM Clock Ratio). Selects SDRAM clock ratio.
20:18
000: Reserved
001: ÷ 2
100: ÷ 3.5
101: ÷ 4
010: ÷ 2.5
011: ÷ 3 (Default)
110: ÷ 4.5
111: ÷ 5
Ratio does not take effect until the SDCLKSTRT bit (bit 17 of this register) transitions from 0 to 1.
17
SDCLKSTRT (Start SDCLK). Start operating SDCLK using the new ratio and shift value (selected in bits [20:18] of this reg-
ister).
0: Clear.
1: Enable.
This bit must transition from zero (written to zero) to one (written to one) in order to start SDCLK or to change the shift value.
16:8
7:6
RFSHRATE (Refresh Interval). This field determines the number of processor core clocks multiplied by 64 between refresh
cycles to the DRAM. By default, the refresh interval is 00h. Refresh is turned off by default.
RFSHSTAG (Refresh Staggering). This field determines number of clocks between the RFSH commands to each of the
four banks during refresh cycles:
00: 0 SDRAM clocks
01: 1 SDRAM clocks (Default)
10: 2 SDRAM clocks
11: 4 SDRAM clocks
Staggering is used to help reduce power spikes during refresh by refreshing one bank at a time. If only one bank is installed,
this field must be written as 00.
5
2CLKADDR (Two Clock Address Setup). Assert memory address for one extra clock before CS# is asserted.
0: Disable.
1: Enable.
This can be used to compensate for address setup at high frequencies and/or high loads.
4
3
RFSHTST (Test Refresh). This bit, when set high, generates a refresh request. This bit is only used for testing purposes.
XBUSARB (X-Bus Round Robin). When enabled, processor, graphics pipeline and non-critical display controller requests
are arbitrated at the same priority level. When disabled, processor requests are arbitrated at a higher priority level. High pri-
ority display controller requests always have the highest arbitration priority.
0: Enable.
1: Disable.
2
SMM_MAP (SMM Region Mapping). Maps the SMM memory region at GX_BASE+400000 to physical address A0000 to
BFFFF in SDRAM.
0: Disable.
1: Enable.
1
0
RSVD (Reserved). Write as 0.
SDRAMPRG (Program SDRAM). When this bit is set, the memory controller will program the SDRAM MRS register using
LTMODE in MC_SYNC_TIM1.
This bit must transition from zero (written to zero) to one (written to one) in order to program the SDRAM devices.
GX_BASE+8404h-8407h
MC_MEM_CNTRL2 (R/W)
Reset Value: 00000801h
31:14
13:12
RSVD (Reserved). Write as 0.
SDCLKCTL (SDCLK High Drive/Slew Control). Controls the high drive and slew rate of SDCLK[3:0] and SDCLK_OUT.
11 is strongest, 00 is weakest.
11
RSVD (Reserved). Write as 0.
Revision 6.0
13
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Architecture Overview (Continued)
Table 1-2. SC1200/SC1201 Memory Controller Registers (Continued)
Bit
Description
10
SDCLKOMSK# (Enable SDCLK_OUT). Turns on the output.
0: Enable.
1: Disable.
9
8
SDCLK3MSK# (Enable SDCLK3). Turns on the output.
0: Enable.
1: Disable.
SDCLK2MSK# (Enable SDCLK2). Turns on the output.
0: Enable.
1: Disable.
7
SDCLK1MSK# (Enable SDCLK1). Turns on the output. 0
0: Enable.
1: Disable.
6
SDCLK0MSK# (Enable SDCLK0). Turns on the output.
0: Enable.
1: Disable.
5:3
SHFTSDCLK (Shift SDCLK). This function allows shifting SDCLK to meet SDRAM setup and hold time requirements. The
shift function will not take effect until the SDCLKSTRT bit (bit 17 of MC_MEM_CNTRL1) transitions from 0 to 1:
000: No shift
100: Shift 2 core clocks
101: Shift 2.5 core clocks
110: Shift 3 core clocks
111: Reserved
001: Shift 0.5 core clock
010: Shift 1 core clock
011: Shift 1.5 core clock
2
1
RSVD (Reserved). Write as 0.
RD (Read Data Phase). Selects if read data is latched one or two core clock after the rising edge of SDCLK.
0: 1 Core clock.
1: 2 Core clocks.
0
FSTRDMSK (Fast Read Mask). Do not allow core reads to bypass the request FIFO.
0: Disable.
1: Enable.
GX_BASE+8408h-840Bh
MC_BANK_CFG (R/W)
Reset Value: 41104110h
31:16
15
RSVD (Reserved). Write as 0070h
RSVD (Reserved). Write as 0.
14
SODIMM_MOD_BNK (SODIMM Module Banks - Banks 0 and 1). Selects number of module banks installed per SODIMM
for SODIMM:
0: 1 Module bank (Bank 0 only)
1: 2 Module banks (Bank 0 and 1)
13
12
RSVD (Reserved). Write as 0.
SODIMM_COMP_BNK (SODIMM Component Banks - Banks 0 and 1). Selects the number of component banks per
module bank for SODIMM:
0: 2 Component banks
1: 4 Component banks
Banks 0 and 1 must have the same number of component banks.
RSVD (Reserved). Write as 0.
11
10:8
SODIMM_SZ (SODIMM Size - Banks 0 and 1). Selects the size of SODIMM:
000: 4 MB
001: 8 MB
010: 16 MB
011: 32 MB
100: 64 MB
101: 128 MB
110: 256 MB
111: 512 MB
This size is the total of both banks 0 and 1. Also, banks 0 and 1 must be the same size.
RSVD (Reserved). Write as 0.
7
6:4
SODIMM_PG_SZ (SODIMM Page Size - Banks 0 and 1). Selects the page size of SODIMM:
000: 1 KB
001: 2 KB
010: 4 KB
011: 8 KB
1xx: 16 KB
111: SODIMM not installed
Both banks 0 and 1 must have the same page size.
3:0
RSVD (Reserved). Write as 0.
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14
Revision 6.0
Architecture Overview (Continued)
Table 1-2. SC1200/SC1201 Memory Controller Registers (Continued)
Bit
Description
GX_BASE+840Ch-840Fh
MC_SYNC_TIM1 (R/W)
Reset Value: 2A733225h
31
RSVD (Reserved). Write as 0.
30:28
LTMODE (CAS Latency). CAS latency is the delay, in SDRAM clock cycles, between the registration of a read command
and the availability of the first piece of output data. This parameter significantly affects system performance. Optimal setting
should be used. If an SODIMM is used, BIOS can interrogate EEPROM across the ACCESS.bus interface to determine this
value:
000: Reserved
001: Reserved
010: 2 CLK
011: 3 CLK
100: 4 CLK
101: 5 CLK
110: 6 CLK
111: 7 CLK
This field will not take effect until SDRAMPRG (bit 0 of MC_MEM_CNTRL1) transitions from 0 to 1.
27:24
23:20
RC (RFSH to RFSH/ACT Command Period, tRC). Minimum number of SDRAM clock between RFSH and RFSH/ACT
commands:
0000: Reserved
0001: 2 CLK
0010: 3 CLK
0011: 4 CLK
0100: 5 CLK
0101: 6 CLK
0110: 7 CLK
0111: 8 CLK
1000: 9 CLK
1001: 10 CLK
1010: 11 CLK
1011: 12 CLK
1100: 13 CLK
1101: 14 CLK
1110: 15 CLK
1111: 16 CLK
RAS (ACT to PRE Command Period, tRAS). Minimum number of SDRAM clocks between ACT and PRE commands:
0000: Reserved
0001: 2 CLK
0010: 3 CLK
0011: 4 CLK
0100: 5 CLK
0101: 6 CLK
0110: 7 CLK
0111: 8 CLK
1000: 9 CLK
1001: 10 CLK
1010: 11 CLK
1011: 12 CLK
1100: 13 CLK
1101: 14 CLK
1110: 15 CLK
1111: 16 CLK
19
RSVD (Reserved). Write as 0.
RP (PRE to ACT Command Period, tRP). Minimum number of SDRAM clocks between PRE and ACT commands:
18:16
000: Reserved
001: 1 CLK
010: 2 CLK
011: 3 CLK
100: 4 CLK
101: 5 CLK
110: 6 CLK
111: 7 CLK
15
RSVD (Reserved). Write as 0.
14:12
RCD (Delay Time ACT to READ/WRT Command, tRCD). Minimum number of SDRAM clock between ACT and
READ/WRT commands. This parameter significantly affects system performance. Optimal setting should be used:
000: Reserved
001: 1 CLK
010: 2 CLK
011: 3 CLK
100: 4 CLK
101: 5 CLK
110: 6 CLK
111: 7 CLK
11
RSVD (Reserved). Write as 0.
10:8
RRD (ACT(0) to ACT(1) Command Period, tRRD). Minimum number of SDRAM clocks between ACT and ACT command
to two different component banks within the same module bank. The memory controller does not perform back-to-back Acti-
vate commands to two different component banks without a READ or WRITE command between them. Hence, this field
should be written as 001.
7
RSVD (Reserved). Write as 0.
6:4
DPL (Data-in to PRE Command Period, tDPL). Minimum number of SDRAM clocks from the time the last write datum is
sampled till the bank is precharged:
000: Reserved
001: 1 CLK
010: 2 CLK
011: 3 CLK
100: 4 CLK
101: 5 CLK
110: 6 CLK
111: 7 CLK
3:0
RSVD (Reserved). Leave unchanged. Always returns a 101h.
Note: Refer to the SDRAM manufacturer’s specification for more information on component banks.
GX_BASE+8414h-8417h MC_GBASE_ADD (R/W)
Reset Value: 00000000h
31:18
17
RSVD (Reserved). Write as 0.
TE (Test Enable TEST[3:0]).
0: TEST[3:0] are driven low (normal operation).
1: TEST[3:0] pins are used to output test information
16
TECTL (Test Enable Shared Control Pins).
0: RASB#, CASB#, CKEB, WEB# (normal operation).
1: RASB#, CASB#, CKEB, WEB# are used to output test information
15:12
11
SEL (Select). This field is used for debug purposes only and should be left at zero for normal operation.
RSVD (Reserved). Write as 0.
10:0
GBADD (Graphics Base Address). This field indicates the graphics memory base address, which is programmable on 512
KB boundaries. This field corresponds to address bits [29:19].
Note that BC_DRAM_TOP must be set to a value lower than the Graphics Base Address.
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Architecture Overview (Continued)
Table 1-2. SC1200/SC1201 Memory Controller Registers (Continued)
Bit
Description
GX_BASE+8418h-841Bh
MC_DR_ADD (R/W)
Reset Value: 00000000h
31:10
9:0
RSVD (Reserved). Write as 0.
DRADD (Dirty RAM Address). This field is the address index that is used to access the Dirty RAM with the MC_DR_ACC
register. This field does not auto increment.
GX_BASE+841Ch-841Fh
MC_DR_ACC (R/W)
Reset Value: 0000000xh
31:2
1
RSVD (Reserved). Write as 0.
D (Dirty Bit). This bit is read/write accessible.
V (Valid Bit). This bit is read/write accessible.
0
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Revision 6.0
Architecture Overview (Continued)
1.1.2 Fast-PCI Bus
1.2.1 GX1 Module Interface
The GX1 module communicates with the Core Logic mod-
ule via a Fast-PCI bus that can work at up to 66 MHz. The
Fast-PCI bus is internal for the SC1200/SC1201 and is
connected to the General Configuration Block.
The Video Processor is connected to the GX1 module in
the following way:
• The Video Processor DOTCLK output signal is used as
the GX1 module’s DCLK input signal.
This bus supports seven bus masters. The requests
(REQs) are fixed in priority. The seven bus masters in order
of priority are:
• The GX1 module’s PCLK output signal is used as the
GFXCLK input signal of the Video Processor.
1.2.2 Video Input Port
1) VIP
The Video Input Port (VIP) within the Video Processor con-
tains a standard interface that is typically connected to a
media processor or TV encoder. The clock is supplied by
the externally connected device; typically at 27 MHz.
2) IDE Channel 0
3) IDE Channel 1
4) Audio
Video input can be sent to the GX1 module’s video frame
buffer (Capture Video mode) or can be used directly (Direct
Video mode).
5) USB
6) External REQ0#
7) External REQ1#
1.2.3 Core Logic Module Interface
The Video Processor interfaces to the Core Logic module
for accessing PCI function configuration registers.
1.1.3 Display
The GX1 module generates display timing, and controls
internal signals CRT_VSYNC and CRT_HSYNC of the
Video Processor module.
1.2.4 CRT DAC
The Video Processor drives three CRT DACs with up to
135M pixels per second.
The GX1 module interfaces with the Video Processor via a
video data bus and a graphics data bus.
The interface for these DACs can be monitored via external
balls of the SC1200/SC1201. For more information, see
Section 2.4.4 "CRT/TFT Interface Signals" on page 64.
• Video data. The GX1 module uses the core clock,
divided by 2 or 4 (typically 100 to 133 MHz). It drives the
video data using this clock. Internal signals VID_VAL
and VID_RDY are used as data-flow handshake signals
between the GX1 module and the Video Processor.
1.3 CORE LOGIC MODULE
The Core Logic module is described in detail in Section 5.0
"Core Logic Module" on page 155.
• Graphics data. The GX1 module uses internal signal
DCLK, supplied by the PLL of the Video Processor, to
drive the 18-bit graphics-data bus of the Video
Processor. Each six bits of this bus define a different
color. Each of these six-bit color definitions is expanded
(by adding two zero LSB lines) to form an eight-bit bus,
at the Video Processor.
The Core Logic module is connected to the Fast-PCI bus. It
uses signal AD28 as the IDSEL for all PCI configuration
functions except for USB which uses AD29.
1.3.1 Other Interfaces of the Core Logic Module
All the following interfaces of the Core Logic module are
implemented via external balls of the SC1200/SC1201.
Each interface is listed below with a reference to the
descriptions of the relevant balls.
For more information about the GX1 module’s interface to
the Video Processor, see the "Display Controller" chapter
in the GX1 Processor Series datasheet.
• IDE: See Section 2.4.10 "IDE Interface Signals" on page
72.
1.2 VIDEO PROCESSOR MODULE
The Video Processor provides high resolution and graphics
for a CRT, TV, or TFT/DSTN interface. The following para-
graphs provide a summary of how this Video Processor
interfaces with the other modules of the SC1200/SC1201.
For detailed information about the Video Processor, see
Section 6.0 "Video Processor Module" on page 319.
• AC97: See Section 2.4.15 "AC97 Audio Interface
Signals" on page 77.
• PCI: See Section 2.4.7 "PCI Bus Interface Signals" on
page 66.
• USB: See Section 5.2.4 "Universal Serial Bus" on page
161. The USB function uses signal AD29 as the IDSEL
for PCI configuration.
• LPC: See Section 2.4.9 "Low Pin Count (LPC) Bus Inter-
face Signals" on page 72.
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Architecture Overview (Continued)
• Sub-ISA: See Section 2.4.8 "Sub-ISA Interface Signals"
on page 71, Section 5.2.5 "Sub-ISA Bus Interface" on
page 161, and Section 3.2 "Multiplexing, Interrupt Selec-
tion, and Base Address Registers" on page 86
The SIO module incorporates: two Serial Ports, an Infrared
Communication Port that supports FIR, MIR, HP-SIR,
Sharp-IR, and Consumer Electronics-IR, a full IEEE 1284
Parallel Port, two ACCESS.bus Interface (ACB) ports, Sys-
tem Wakeup Control (SWC), and a Real-Time Clock (RTC)
that provides RTC timekeeping.
• GPIO: See Section 2.4.17 "GPIO Interface Signals" on
page 80.
• More detailed information about each of these interfaces
is provided in Section 5.2 "Module Architecture" on page
156.
1.5 CLOCK, TIMERS, AND RESET LOGIC
In addition to the four main modules (i.e., GX1, Core Logic,
Video Processor and SIO) that make up the
SC1200/SC1201, the following blocks of logic have also
been integrated into the SC1200/SC1201:
• Super/IO Block Interfaces: See Section 3.2 "Multi-
plexing, Interrupt Selection, and Base Address Regis-
ters" on page 86, Section 2.4.6 "ACCESS.bus Interface
Signals" on page 66, Section 2.4.14 "Fast Infrared (IR)
Port Interface Signals" on page 77, and Section 2.4.13
"Parallel Port Interface Signals" on page 76.
• Clock Generators as described in Section 3.5 "Clock
Generators and PLLs" on page 97.
• Configuration Registers as described in Section 3.2
"Multiplexing, Interrupt Selection, and Base Address
Registers" on page 86.
The Core Logic module interface to the GX1 module con-
sists of seven miscellaneous connections, the PCI bus
interface signals, plus the display controller connections.
Note that the PC/AT legacy signals NMI, WM_RST, and
A20M are all virtual functions executed in SMM (System
Management Mode) by the BIOS.
• A WATCHDOG timer as described in Section 3.3
"WATCHDOG" on page 93.
• A High-Resolution timer as described in Section 3.4
"High-Resolution Timer" on page 95.
• PSERIAL is a one-way serial bus from the GX1 to the
Core Logic module used to communicate power-
management states and VSYNC information for VGA
emulation.
1.5.1 Reset Logic
This section provides a description of the reset flow of the
SC1200/SC1201.
• IRQ13 is an input from the processor indicating that a
floating point error was detected and that INTR should
be asserted.
1.5.1.1 Power-On Reset
Power-On reset is triggered by assertion of the POR# sig-
nal. Upon power-on reset, the following things happen:
• INTR is the level output from the integrated 8259A PICs
and is asserted if an unmasked interrupt request (IRQn)
is sampled active.
• Strap balls are sampled.
• PLL4, PLL5, PLL6 are reset, disabling their output.
When the POR# signal is negated, the clocks lock and
then each PLL outputs its clock. PLL6 is the last clock
generator to output a clock. See Section 3.5 "Clock
Generators and PLLs" on page 97.
• SMI# is a level-sensitive interrupt to the GX1 that can be
configured to assert on a number of different system
events. After an SMI# assertion, SMM is entered and
program execution begins at the base of the SMM
address space. Once asserted, SMI# remains active
until the SMI source is cleared.
• Certain WATCHDOG and High-Resolution Timer
register bits are cleared.
• SUSP# and SUSPA# are handshake signals for imple-
1.5.1.2 System Reset
menting CPU Clock Stop and clock throttling.
System reset causes signal PCIRST# to be issued, thus
triggering reset of all PCI and LPC agents. A system reset
is triggered by any of the following events:
• CPU_RST resets the CPU and is asserted for approxi-
mately 100 µs after the negation of POR#.
• Power-on, as indicated by POR# signal assertion.
• PCI bus interface signals.
• A WATCHDOG reset event (see Section 3.3.2
1.4 SUPERI/O MODULE
"WATCHDOG Registers" on page 94).
The SuperI/O (SIO) module is a member of National Semi-
conductor’s SuperI/O family of integrated PC peripherals. It
is a PC98 and ACPI compliant SIO that offers a single-cell
solution to the most commonly used ISA peripherals.
• Software initiated system reset.
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Revision 6.0
2.0 Signal Definitions
This section defines the signals and describes the external
interface of the SC1200/SC1201. Figure 2-1 shows the sig-
nals organized by their functional groups. Where signals
are multiplexed, the default signal name is listed first and is
separated by a plus sign (+). A slash (/) in a signal name
means that the function is always enabled and available
(i.e., cycle multiplexed).
according to ball number and alphabetically by signal
name.
• Section 2.2 "Strap Options": Several balls are read at
power-up that set up the state of the SC1200/SC1201.
This section provides details regarding those balls.
• Section 2.3 "Multiplexing Configuration": Lists multi-
plexing options and their configurations.
The remaining subsections of this chapter describe:
• Section 2.4 "Signal Descriptions": Detailed descriptions
• Section 2.1 "Ball Assignments": Provides a ball assign-
of each signal according to functional group.
ment diagram and tables listing the signals sorted
POR#
X32I
X32O
X27I
CVBS+Cr+TVB
SVY+Cb+TVR+CVBS
SVC+Cr+Cb+TVB+TVR
TV
Interface
CVBS+Y+TVG
X27O
PCIRST#
BOOT16+ROMCS#
LPC_ROM+PCICLK1
TVCOMP
System
Interface
TVRSET
TVREF
TVIOM
TFT_PRSNT+SDATA_OUT
FPCI_MON+PCICLK0
DID0+GNT0#, DID1+GNT1#
Straps
HSYNC
VSYNC
CRT
Interface
VREF
SETRES
MD[63:0]
MA[12:0]
BA[1:0]
RED, GREEN, BLUE
CS[1:0]#
RASA#
CASA#
WEA#
DQM[7:0]
CKEA
SDCLK[3:0]
SDCLK_IN
SDCLK_OUT
IDE_ADDR2+TFTD4
IDE_ADDR1+TFTD2
IDE_ADDR0+TFTD3
IDE_DATA15+TFTD7
Geode™
SC1200/SC1201
Memory
Interface
IDE_DATA14+TFTD17
IDE_DATA13+TFTD15
IDE_DATA12+TFTD13
IDE_DATA11+GPIO41
IDE_DATA10+DDC_SCL
IDE_DATA9+DDC_SDA
IDE_DATA8+GPIO40
IDE_DATA7+INTD#
AB1C+GPIO20+DOCCS#
AB1D+GPIO1+IOCS1#
GPIO12+AB2C
ACCESS.bus
Interface
IDE_DATA6+IRQ9
GPIO13+AB2D
IDE_DATA5+CLK27M
IDE_DATA4+FP_VDD_ON
IDE_DATA3+TFTD12
IDE_DATA2+TFTD14
IDE_DATA1+TFTD16
IDE_DATA0+TFTD6
IDE/TFT
Interface
ACK#+TFTDE+VOPCK
AFD#/DSTRB#+TFTD2+VOPD1
BUSY/WAIT#+TFTD3+VOPD2
ERR#+TFTD4+VOPD3
INIT#+TFTD5+VOPD4
PD7+TFTD13
PD6+TFTD1+VOPD0
PD[5:0]+TFTD[11:6]+VOPD[7:5]
PE+TFTD14
IDE_IOR0#+TFTD10
IDE_IOW0#+TFTD9
IDE_CS0#+TFTD5
IDE_CS1#+TFTDE
IDE_IORDY0+TFTD11
IDE_DREQ0+TFTD8
Parallel Port/
TFT/VOP Interface
SLCT+TFTD15
SLIN#/ASTRB#+TFTD16
STB#/WRITE#+TFTD17
IDE_DACK0#+TFTD0
IDE_RST#+TFTDCK
IRQ14+TFTD1
Video Port
Interface
VPD[7:0]
VPCKIN
Note:
Straps are not the default signal, shown with system signals for reader convenience. However, also listed in figure with the
appropriate functional group.
Figure 2-1. Signal Groups
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Signal Definitions (Continued)
POWER_EN
PCICLK0+FPCI_MON
PCICLK1+LPC_ROM
PCICLK
OVER_CUR#
DPOS_PORT1
DNEG_PORT1
DPOS_PORT2
DNEG_PORT2
DPOS_PORT3
DNEG_PORT3
USB
Interface
INTA#, INTB#
FRAME#
Geode™
SC1200/SC1201
LOCK#
PERR#
SERR#
REQ[1:0]#
GNT0#+DID0
GNT1#+DID1
A[23:0]/AD[23:0]
D[7:0]/AD[31:24]
D[11:8]/C/BE[3:0]#
D12/PAR
SIN1
SIN2+SDTEST3
SOUT1+CLKSEL1
SOUT2+CLKSEL2
GPIO7+RTS2#+IDE_DACK1#+SDTEST0
GPIO8+CTS2#+IDE_DREQ1+SDTEST4
GPIO18+DTR1#/BOUT1
GPIO6+DTR2#/BOUT2+IDE_IOR1#+SDTEST5
GPIO11+RI2#+IRQ15
GPIO9+DCD2#+IDE_IOW1#+SDTEST2
Sub-ISA/PCI Bus
Interface
Serial Ports
(UARTs)/IDE
Interface
D13/TRDY#
D14/IRDY#
D15/STOP#
BHE#/DEVSEL#
GPIO17+TFTDCK+IOCS0#
GPIO1+IOCS1+TFTD12
ROMCS#/BOOT16
GPIO10+DSR2#+IDE_IORDY1+SDTEST1
IR Port
Interface
IRRX1+SIN3
IRTX+SOUT3
GPIO20+DOCCS#+TFTD0
RD#+CLKSEL0
WR#
GPIO14+DOCR#+IOR#
GPIO15+DOCW#+IOW#
GPIO0+TRDE#
BIT_CLK
SDATA_OUT+TFT_PRSNT
SDATA_IN
GPIO19+INTC#+IOCHRDY
AC97 Audio
Interface
SDATA_IN2
SYNC+CLKSEL3
AC97_CLK
AC97_RST#
GPIO32+LAD0
GPIO33+LAD1
GPIO16+PC_BEEP
GPIO34+LAD2
GPIO/LPC Bus
Interface
GPIO35+LAD3
GPIO36+LDRQ#
GPIO37+LFRAME#
GPIO38+IRRX2+LPCPD
GPIO39+SERIRQ
CLK32
GPWIO[2:0]
LED#
ONCTL#
PWRBTN#
PWRCNT[1:2]
THRM#
Power
Management
Interface
PLL6B+TEST1
PLL2B+TEST0
GXCLK+FP_VDD_ON+TEST3
PLL5B+TEST2
GTEST
Test and
Measurement
Interface
TCK
TDI
TDO
TMS
TRST#
JTAG
Interface
TDP, TDN
Figure 2-1. Signal Groups (Continued)
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20
Revision 6.0
Signal Definitions (Continued)
2.1 BALL ASSIGNMENTS
Table 2-1. Signal Definitions Legend
The SC1200/SC1201 is highly configurable as illustrated in
Figure 2-1 on page 19. Strap options and register program-
ming are used to set various modes of operation and spe-
cific signals on specific balls. This section describes which
signals are available on which balls and provides configura-
tion information:
Mnemonic
Definition
A
Analog
AVSS
Ground ball: Analog
AVCC
GCB
Power ball: Analog
• Figure 2-2 on page 22 and Figure 2-3 on page 38: Illus-
General Configuration Block registers.
Refer to Section 3.0 "General Configura-
tion Block" on page 85.
trations of EBGA and TEPBGA ball assignments.
• Table 2-2 on page 23 and Table 2-4 on page 39: Lists
signals according to ball number. Power Rail, Signal
Type, Buffer Type and, where relevant, Pull-Up or Pull-
Down resistors are indicated for each ball in this table.
For multiplexed balls, the necessary configuration for
each signal is listed as well.
Location of the General Configuration
Block cannot be determined by software.
See SC1200/SC1201 Set-Top Box On a
Chip device errata.
I
Input ball
• Table 2-3 on page 34 and Table 2-5 on page 50: Quick
reference signal list sorted alphabetically - listing all
signal names and ball numbers.
I/O
Bidirectional ball
MCR[x]
Miscellaneous Configuration Register
Bit x: A register, located in the GCB.
Refer to Section 3.1 "Configuration
Block Addresses" on page 85 for further
details.
The tables in this chapter use several common abbrevia-
tions. Table 2-1 lists the mnemonics and their meanings
Notes:
O
Output ball
Open-drain
Pull-down
1) For each GPIO signal, there is an optional pull-up
resistor on the relevant ball. After system reset, the
pull-up is present.
OD
PD
This pull-up resistor can be disabled via registers in the
Core Logic module. The configuration is without regard to
the selected ball function (except for GPIO12, GPIO13,
and GPIO16). Alternate functions for GPIO12, GPIO13,
and GPIO16 control pull-up resistors.
PMR[x]
Pin Multiplexing Register Bit x: A regis-
ter, located in the GCB, used to config-
ure balls with multiple functions. Refer to
Section 3.1 "Configuration Block
Addresses" on page 85 for further
details.
For more information, see Section 5.4.1 "Bridge,
GPIO, and LPC Registers - Function 0" on page 204.
PU
Pull-up
2) Configuration settings listed in this table are with
regard to the Pin Multiplexing Register (PMR). See
Section 3.2 "Multiplexing, Interrupt Selection, and
Base Address Registers" on page 86 for a detailed
description of this register.
TS
TRI-STATE
Power ball: 1.2V
VCORE
VIO
VSS
#
Power ball: 3.3V
Ground ball
The # symbol in a signal name indicates
that the active or asserted state occurs
when the signal is at a low voltage level.
Otherwise, the signal is asserted when
at a high voltage level.
/
A / in a signal name indicates both func-
tions are always enabled (i.e., cycle mul-
tiplexed).
+
A + in signal name indicates the function
is available on the ball, but that either
strapping options or register program-
ming is required to select the desired
function.
Revision 6.0
21
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Signal Definitions (Continued)
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
A
B
A
VSS
VIO
RQ0# AD30 VIO AD28 AD24 AD21 AD17 IRDY# LOCK# PAR AD13 AD11 AD10 AD8 AD6 ICS1# IAD2 IDAT14 IDAT11 IDAT9 IIOR0# IDAT6 IDAT3 IDRQ0 IDCK0# IAD1 OVCR# PLL6B VIO X32I VPLL3
VIO AD29 AD26 AD22 AD19 AD16 CBE3# SERR# CBE1# AD14 AD12 CBE0# AD5 AD3 AD4 AD0 AD2 IDAT13 IDAT10 IDAT8 IRST# IDAT5 IDAT1 IORDY0 IAD0 ICS0# GP18 X27I VIO
VSS
S
B
VSS AD31 AD27 DVSL# VIO
VSS TRDY# PERR# AD15 VIO
VSS AD9 AD7 VSS
VIO
VSS IDAT15 IDAT12 VIO
VSS IDAT7 IDAT4 IDAT0 VIO
VSS SOUT1 PWRE PLL5B VSS
VIO
C
C
S
S
S
D
D
PRST# GNT1# PCK0 GNT0# AD25 AD20 AD18 CBE2# STP# VSS VCORE VSS VCORE VSS VCORE AD1 VCORE VSS VCORE VSS VCORE VSS IDAT2 IIOW0# IRQ14 SIN1 X27O PLL2B X32O VBAT LED#
S
E
E
FRM# PCLK REQ1# PCK1
AVSSP3 PBTN# OCTL# GPW0
THRM# VSB VSS PCNT1
GPW1 GPW2 VIO PCNT2
VSBL CK32 GP11 SDIN2
IRRX1 POR# MD0 MD1
VSS MD2 MD3 MD4
VCORE MD5 VSS MD6
VSS MD7 VIO DQM0
VCORE WEA# CASA# RASA#
VSS CS0# BA0 BA1
VCORE MA10 VSS MA0
DQM4 MA2 VCORE MA1
VCORE MD33 VSS MD32
VSS MD36 MD35 MD34
VCORE MD39 MD38 MD37
VSS MD46 VIO MD47
VCORE MD44 VSS MD45
VSS MD41 MD42 MD43
CKEA SDCK0 DQM5 MD40
MA6 MA7 MA8 MA9
MA3 MA4 VIO MA5
MD14 MD15 VSS DQM1
MA11 MD9 MD8 MD13
S
F
F
IOR# VSS RD# AD23
S
G
G
WR# VIO IOW# RMCS#
H
H
TRDE# GP1 GP20 GP19
HSYN VSYN IRTX GP17
J
J
K
K
RED VSSCRTVCCCRT VSS
AVSSCRT VSS AVCCCRTVCORE
L
L
M
M
N
VCCCRT VIO GREEN VSS
AVCCCRT BLUE AVSSCRTVCORE
VREF STRS AVSSCRT VSS
VPLL2 VSS AVSSP2 VCORE
Geode™
N
P
P
R
R
T
T
BSY VIO
PE SLCT
U
SC1200/SC1201
Set-Top Box
On a Chip
U
PD7 VSS ACK# VCORE
PD4 PD5 PD6 VSS
SLIN# PD3 PD2 VCORE
PD1 VIO INIT# VSS
PD0 VSS ERR# VCORE
STB# AFD# CVBS VSS
TVIOM SVC AVCCTV AVSSTV
SVY TVREF CVBS TVCOMP
V
V
W
Y
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
TVRST VIO INTA# D+P3
INTB# VSS D-P3 AVCCUSB
AVSSUSB D-P2 D-P1 GP9
(Top View)
D+P2 D+P1 GP6 GP7 TDP TDO VPCKI VPD4 VPD0 VSS VCORE VSS VCORE VSS VCORE SDCK1 VCORE VSS VCORE VSS VCORE VSS MD28 MD55 MD51 MD48 MD23 SDCKO MA12 MD11 MD10
GP10 GP8 VIO SIN2 TMS VPD7 VPD6 VPD2 GP38 GP35 GP32 GP12 AB1C ACCK ACRT# SDCK3 MD56 MD58 MD61 DQM7 DQM3 MD25 MD29 MD54 MD50 DQM6 MD22 MD19 VIO SDCKI MD12
S
S
VIO
VSS
1
VSS SOUT2 TRST# TDI
VIO
VSS VPD1 GP37 GP34 VIO
VSS SDATO SDATI VSS
S
VIO
VSS MD59 MD62 VIO
VSS MD26 MD30 MD53 VIO
VSS MD21 MD18 CS1# VSS
VIO
VIO TDN TCK GTST VPD5 VPD3 GP39 GP36 GP33 GP13 AB1D SYNC BITCK GP16 GXCK MD57 MD60 MD63 SDCK2 MD24 MD27 MD31 MD52 MD49 DQM2 MD20 MD17 MD16 VIO
VSS
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Note: Signal names have been abbreviated in this figure due to space constraints.
= GND Ball
= PWR Ball
= Strap Option Ball
S
= Multiplexed Ball
Figure 2-2. 432-EBGA Ball Assignment Diagram
www.national.com
22
Revision 6.0
Signal Definitions (Continued)
Table 2-2. 432-EBGA Ball Assignment - Sorted by Ball Number
1
1
Ball
No.
I/O
Buffer Power
Rail Configuration
Ball
No.
I/O
Buffer Power
Rail Configuration
Signal Name
(PU/PD) Type
Signal Name
(PU/PD) Type
A1
A2
A3
V
V
GND
PWR
I/O
---
---
---
---
---
A19
IDE_DATA13
I/O
IN
TS
,
V
V
V
PMR[24] = 0
SS
TS1
IO
IO
IO
1/4
---
IO
TFTD15
O
O
PMR[24] = 1
PMR[24] = 0
1/4
AD29
IN
,
V
Cycle Multiplexed
PCI
IO
2
O
IDE_DATA10
I/O
IN
TS
,
PCI
A20
A21
TS1
1/4
D5
I/O
I/O
I/O
I/O
IN
O
,
PCI
PCI
DDC_SCL
O
OD
PMR[24] = 1
PMR[24] = 0
4
A4
AD26
D2
IN
O
,
V
Cycle Multiplexed
IDE_DATA8
I/O
IN
TS1
TS
,
PCI
PCI
IO
1/4
IN
O
,
GPIO40
I/O
IN
O
,
PMR[24] = 1
PCI
PCI
TS1
1/4
1/4
1/4
A5
A6
A7
A8
AD22
IN
O
,
V
V
V
V
Cycle Multiplexed
Cycle Multiplexed
Cycle Multiplexed
Cycle Multiplexed
A22
A23
IDE_RST#
TFTDCK
O
O
O
V
V
PMR[24] = 0
PMR[24] = 1
PMR[24] = 0
PCI
PCI
IO
IO
IO
IO
IO
IO
O
A22
O
O
PCI
IDE_DATA5
I/O
IN
TS1
TS
1/4
,
AD19
I/O
IN
O
,
PCI
PCI
CLK27M
O
O
PMR[24] = 1
PMR[24] = 0
1/4
A19
O
O
PCI
A24
IDE_DATA1
I/O
IN
TS
1/4
,
V
TS1
IO
AD16
I/O
IN
O
,
PCI
PCI
TFTD16
O
I
O
PMR[24] = 1
PMR[24] = 0
PMR[24] = 1
PMR[24] = 0
PMR[24] = 1
PMR[24] = 0
PMR[24] = 1
PMR[16] = 0
1/4
A16
O
O
PCI
A25
A26
A27
A28
IDE_IORDY0
TFTD11
IN
V
V
V
V
TS1
IO
IO
IO
IO
C/BE3#
I/O
IN
O
,
PCI
PCI
O
O
O
O
O
I/O
O
O
O
O
O
1/4
1/4
1/4
1/4
1/4
(PU
)
)
)
)
)
22.5
IDE_ADDR0
TFTD3
D11
I/O
(PU
IN
O
,
PCI
PCI
22.5
22.5
22.5
22.5
IDE_CS0#
TFTD5
A9
SERR#
C/BE1#
D9
I/O
(PU
IN
,
V
V
---
PCI
IO
IO
OD
PCI
A10
I/O
(PU
IN
O
,
Cycle Multiplexed
PCI
PCI
GPIO18
IN
O
,
TS
8/8
(PU
)
)
22.5
I/O
(PU
IN
O
,
PCI
PCI
DTR1#/BOUT1
X27I
O
O
PMR[16] =1
8/8
(PU
22.5
A11
A12
A13
AD14
I/O
IN
O
,
V
V
V
Cycle Multiplexed
Cycle Multiplexed
Cycle Multiplexed
A29
A30
A31
B1
I
WIRE
---
V
---
PCI
PCI
IO
IO
IO
IO
V
V
V
V
PWR
GND
PWR
GND
I/O
---
---
IO
A14
O
O
PCI
---
---
---
---
---
SS
IO
AD12
I/O
IN
O
,
PCI
PCI
---
---
B2
---
---
SS
A12
O
O
PCI
B3
AD31
IN
O
,
V
Cycle Multiplexed
PCI
PCI
IO
IO
IO
C/BE0#
I/O
IN
O
,
PCI
PCI
(PU
)
)
22.5
D7
I/O
I/O
I/O
I/O
IN
O
,
PCI
PCI
D8
I/O
(PU
IN
O
,
PCI
PCI
22.5
B4
B5
AD27
D3
IN
O
,
V
V
Cycle Multiplexed
Cycle Multiplexed
PCI
PCI
A14
A15
A16
A17
A18
AD5
I/O
IN
O
,
V
V
V
V
V
Cycle Multiplexed
Cycle Multiplexed
Cycle Multiplexed
Cycle Multiplexed
Cycle Multiplexed
PCI
PCI
IO
IO
IO
IO
IO
IN
O
,
PCI
PCI
A5
O
O
PCI
AD3
I/O
IN
O
,
PCI
PCI
DEVSEL#
IN
O
,
PCI
PCI
(PU
)
22.5
A3
O
O
PCI
BHE#
O
O
PCI
AD4
I/O
IN
O
,
PCI
PCI
B6
B7
B8
V
V
PWR
GND
I/O
---
---
---
---
---
IO
---
SS
A4
O
O
PCI
TRDY#
IN
O
,
V
Cycle Multiplexed
PCI
IO
AD0
I/O
IN
O
,
PCI
PCI
(PU
)
)
)
22.5
PCI
D13
I/O
IN
O
,
PCI
PCI
A0
O
O
PCI
(PU
22.5
AD2
I/O
IN
O
,
PCI
PCI
B9
PERR#
I/O
IN
O
,
V
---
PCI
PCI
IO
(PU
22.5
A2
O
O
PCI
Revision 6.0
23
www.national.com
Signal Definitions (Continued)
Table 2-2. 432-EBGA Ball Assignment - Sorted by Ball Number (Continued)
1
1
Ball
No.
I/O
Buffer Power
Rail Configuration
Ball
No.
I/O
Buffer Power
Rail Configuration
Signal Name
(PU/PD) Type
Signal Name
(PU/PD) Type
B10
AD15
I/O
IN
O
,
V
Cycle Multiplexed
C4
AD28
I/O
I/O
I/O
I/O
I/O
IN
O
,
V
Cycle Multiplexed
PCI
IO
PCI
PCI
IO
PCI
A15
O
O
D4
IN
O
,
PCI
PCI
PCI
B11
B12
B13
V
V
PWR
GND
I/O
---
---
---
---
---
IO
C5
AD24
D0
IN
O
,
V
Cycle Multiplexed
PCI
PCI
IO
---
SS
AD9
IN
,
V
Cycle Multiplexed
PCI
IO
IN
O
,
PCI
PCI
O
PCI
A9
O
O
PCI
C6
C7
C8
AD21
IN
O
,
V
V
V
Cycle Multiplexed
Cycle Multiplexed
Cycle Multiplexed
PCI
PCI
IO
IO
IO
B14
AD7
I/O
IN
O
,
V
Cycle Multiplexed
PCI
PCI
IO
A21
O
O
PCI
A7
O
O
PCI
AD17
I/O
IN
O
,
PCI
PCI
B15
B16
B17
B18
V
GND
PWR
GND
I/O
---
---
---
---
---
SS
V
---
---
---
A17
O
O
IO
PCI
V
---
IRDY#
I/O
IN
O
,
SS
PCI
PCI
(PU
)
)
)
)
)
22.5
IDE_DATA15
IN
,
V
PMR[24] = 0
TS1
IO
TS
D14
I/O
(PU
IN
O
,
1/4
PCI
PCI
22.5
TFTD7
O
O
PMR[24] = 1
PMR[24] = 0
1/4
C9
LOCK#
PAR
I/O
(PU
IN
O
,
V
V
---
PCI
PCI
IO
IO
B19
IDE_DATA12
I/O
IN
,
V
TS1
IO
22.5
TS
1/4
C10
I/O
(PU
IN
O
,
Cycle Multiplexed
PCI
PCI
TFTD13
O
O
PMR[24] = 1
1/4
22.5
B20
B21
B22
V
V
PWR
GND
I/O
---
---
IN
---
---
---
IO
D12
I/O
(PU
IN
O
,
PCI
PCI
---
SS
22.5
IDE_DATA7
,
V
PMR[24] = 0
TS1
IO
IO
IO
C11
C12
C13
C14
C15
AD13
I/O
IN
O
,
V
V
V
V
V
Cycle Multiplexed
Cycle Multiplexed
Cycle Multiplexed
Cycle Multiplexed
Cycle Multiplexed
PCI
PCI
IO
IO
IO
IO
IO
TS
1/4
INTD#
I
IN
PMR[24] = 1
PMR[24] = 0
TS
A13
O
O
PCI
B23
B24
IDE_DATA4
I/O
IN
,
V
V
TS1
AD11
I/O
IN
O
,
PCI
PCI
TS
1/4
FP_VDD_ON
IDE_DATA0
O
O
PMR[24] = 1
PMR[24] = 0
1/4
A11
O
O
PCI
I/O
IN
,
TS1
AD10
I/O
IN
O
,
PCI
PCI
TS
1/4
TFTD6
O
PWR
GND
O
O
PMR[24] = 1
1/4
A10
AD8
O
O
PCI
B25
B26
B27
V
V
---
---
---
---
---
---
---
IO
I/O
IN
O
,
PCI
PCI
SS
A8
O
O
SOUT1
O
V
PCI
8/8
IO
AD6
I/O
IN
O
,
CLKSEL1
I
IN
Strap (See Table 2-
6 on page 54.)
PCI
PCI
STRP
(PD
)
100
A6
O
O
O
B28
B29
POWER_EN
PLL5B
O
O
V
V
---
PCI
1/4
IO
IO
I/O
IN ,
TS
PMR[29] = 0
C16
C17
C18
IDE_CS1#
TFTDE
O
O
O
O
V
V
V
PMR[24] = 0
PMR[24] = 1
PMR[24] = 0
PMR[24] = 1
PMR[24] = 0
T
1/4
1/4
1/4
1/4
IO
IO
IO
2/5
O
TEST2
O
GND
PWR
I
O
PMR[29] = 1
2/5
IDE_ADDR2
TFTD4
O
B30
B31
C1
V
V
---
---
---
---
---
---
SS
IO
O
---
IDE_DATA14
I/O
IN
,
TS1
REQ0#
INPCI
V
TS
1/4
IO
(PU
)
22.5
TFTD17
O
O
PMR[24] = 1
PMR[24] = 0
1/4
C2
AD30
I/O
IN
O
,
V
Cycle Multiplexed
PCI
PCI
IO
C19
IDE_DATA11
I/O
IN
,
V
TS1
IO
TS
1/4
D6
I/O
IN
O
,
PCI
PCI
GPIO41
I/O
IN
O
,
PMR[24] = 1
TS1
1/4
C3
V
PWR
---
---
---
IO
www.national.com
24
Revision 6.0
Signal Definitions (Continued)
Table 2-2. 432-EBGA Ball Assignment - Sorted by Ball Number (Continued)
1
1
Ball
No.
I/O
Buffer Power
Rail Configuration
Ball
No.
I/O
Buffer Power
Rail Configuration
Signal Name
(PU/PD) Type
Signal Name
(PU/PD) Type
2
IDE_DATA9
I/O
I/O
IN
TS
,
V
PMR[24] = 0
D9
STOP#
I/O
(PU
IN
O
,
V
IO
Cycle Multiplexed
C20
TS1
IO
PCI
PCI
)
)
22.5
1/4
DDC_SDA
IN ,
OD
PMR[24] = 1
D15
I/O
(PU
IN
O
,
T
PCI
PCI
22.5
4
1/4
1/4
C21
C22
IDE_IOR0#
TFTD10
O
O
O
O
V
V
PMR[24] = 0
PMR[24] = 1
PMR[24] = 0
D10
D11
D12
D13
D14
D15
D16
V
V
V
V
V
V
GND
PWR
GND
PWR
GND
PWR
I/O
---
---
---
---
---
---
---
---
IO
IO
SS
---
---
---
---
---
---
CORE
SS
IDE_DATA6
I/O
IN
TS
,
---
TS1
1/4
---
CORE
SS
IRQ9
I
IN
PMR[24] = 1
PMR[24] = 0
TS1
---
C23
IDE_DATA3
I/O
IN
TS
,
V
TS1
IO
---
CORE
1/4
AD1
IN
,
V
Cycle Multiplexed
PCI
IO
TFTD12
O
I
O
PMR[24] = 1
PMR[24] = 0
PMR[24] = 1
PMR[24] = 0
PMR[24] = 1
PMR[24] = 0
PMR[24] = 1
---
1/4
O
PCI
C24
C25
C26
IDE_DREQ0
TFTD8
IN
V
V
V
TS1
IO
IO
IO
A1
O
O
PCI
O
O
O
O
O
I
O
O
O
O
O
1/4
1/4
1/4
1/4
1/4
D17
D18
D19
D20
D21
D22
D23
V
V
V
V
V
V
PWR
GND
PWR
GND
PWR
GND
I/O
---
---
---
---
---
---
---
---
---
---
---
---
---
CORE
SS
IDE_DACK0#
TFTD0
---
---
CORE
SS
IDE_ADDR1
TFTD2
---
---
CORE
SS
C27
C28
OVER_CUR#
PLL6B
IN
V
V
TS
IO
IO
---
I/O
IN
TS
,
PMR[29] = 0
TS
IDE_DATA2
IN
,
V
PMR[24] = 0
TS1
IO
2/5
TS
1/4
TEST1
O
O
PMR[29] = 1
2/5
TFTD14
IDE_IOW0#
TFTD9
IRQ14
O
O
O
I
O
O
O
PMR[24] = 1
PMR[24] = 0
PMR[24] = 1
PMR[24] = 0
PMR[24] = 1
---
1/4
C29
C30
C31
D1
V
PWR
---
---
---
---
---
---
---
IO
D24
D25
V
V
1/4
IO
IO
X32I
I
PWR
O
WIRE
---
V
BAT
1/4
V
---
PLL3
IN
TS1
PCIRST#
GNT1#
DID1
O
O
V
PCI
PCI
IO
IO
TFTD1
SIN1
O
I
O
1/4
D2
O
V
V
V
V
D26
D27
D28
IN
V
V
V
TS
IO
IO
IO
I
IN
IN
IN
Strap (See Table 2-
6 on page 54.)
STRP
X27O
O
I/O
WIRE
IN ,
---
(PD
)
)
)
100
PLL2B
PMR[29] = 0
T
D3
D4
D5
PCICLK0
O
O
---
PCI
IO
IO
IO
TS
2/5
FPCI_MON
I
Strap (See Table 2-
6 on page 54.)
STRP
TEST0
X32O
O
O
O
PMR[29] = 1
2/5
(PD
100
D29
D30
D31
E1
WIRE
---
V
---
---
---
---
BAT
GNT0#
DID0
O
I
O
---
PCI
V
PWR
O
---
BAT
Strap (See Table 2-
6 on page 54.)
STRP
(PD
100
LED#
OD
V
SB
14
AD25
D1
I/O
I/O
I/O
IN
,
Cycle Multiplexed
PCI
FRAME#
I/O
IN
O
,
V
PCI
PCI
IO
O
(PU
)
)
PCI
22.5
IN
O
,
PCI
PCI
E2
E3
PCICLK
REQ1#
I
IN
V
V
---
---
T
IO
IO
I
IN
PCI
D6
D7
D8
AD20
IN
O
,
V
V
V
Cycle Multiplexed
Cycle Multiplexed
Cycle Multiplexed
(PU
PCI
PCI
IO
IO
IO
22.5
E4
PCICLK1
O
O
V
---
PCI
IO
A20
O
O
PCI
LPC_ROM
I
IN
Strap (See Table 2-
6 on page 54.)
STRP
AD18
I/O
IN
O
,
(PD
PCI
PCI
100)
E28
E29
AV
GND
---
---
---
---
SSPLL3
A18
O
O
PCI
PWRBTN#
I
IN
V
BTN
SB
(PU
C/BE2#
I/O
IN
O
,
100)
PCI
PCI
(PU
)
22.5
4, 5
ONCTL#
GPWIO0
O
OD
V
V
---
---
E30
E31
14
SB
SB
D10
I/O
(PU
IN
O
,
PCI
PCI
I/O
IN
TS
,
TS
)
22.5
(PU
)
100
2/14
Revision 6.0
25
www.national.com
Signal Definitions (Continued)
Table 2-2. 432-EBGA Ball Assignment - Sorted by Ball Number (Continued)
1
1
Ball
No.
I/O
Buffer Power
Rail Configuration
Ball
No.
I/O
Buffer Power
Signal Name
(PU/PD) Type
Signal Name
(PU/PD) Type
Rail Configuration
3
F1
IOR#
O
O
O
O
V
PMR[21] = 0 and
PMR[2] = 0
H3
GPIO20
I/O
(PU
IN ,
T
V
3/5
3/5
IO
IO
(PMR[23] = 0 and
PMR[7] = 0) or
)
)
O
22.5
3/5
3
(PMR[23] = 1 and
DOCR#
GPIO14
PMR[21] = 0 and
PMR[2] = 1
PMR[15] = 1 and
PMR[7] = 0)
I/O
IN
O
,
PMR[21] = 1 and
PMR[2] = 1
TS
3/5
3
DOCCS#
O
O
(PU
)
3/5
(PMR[23] = 0 and
22.5
(PU
22.5
PMR[7] = 1) or
F2
F3
V
GND
---
---
---
---
SS
3
(PMR[23] = 1 and
PMR[15] = 1 and
PMR[7] = 1)
RD#
O
I
O
V
3/5
IO
CLKSEL0
IN
Strap (See Table 2-
6 on page 54.)
STRP
3
TFTD0
O
O
(PD
)
1/4
PMR[23] = 1 and
100
(PU
)
)
22.5
PMR[15] = 0
F4
AD23
I/O
IN
,
V
Cycle Multiplexed
PCI
IO
H4
GPIO19
I/O
(PU
IN
O
,
V
PMR[9] = 0 and
PMR[4] = 0
TS
3/5
IO
O
PCI
22.5
A23
O
I
O
PCI
INTC#
I
IN
PMR[9] = 0 and
PMR[4] = 1
TS
F28
F29
F30
THRM#
IN
V
---
---
---
---
TS
SB
(PU
)
)
22.5
V
V
PWR
GND
O
---
---
OD
---
---
SB
SS
IOCHRDY
I
IN
PMR[9] = 1 and
PMR[4] = 1
TS1
(PU
22.5
H28
H29
H30
V
PWR
O
---
---
---
---
SBL
4, 5
PWRCNT1
WR#
V
SB
F31
G1
14
CLK32
O
V
SB
2/5
O
O
V
3/5
IO
IO
GPIO11
I/O
IN
O
,
V
PMR[18] = 0 and
PMR[8] = 0
TS
8/8
IO
G2
G3
V
PWR
O
---
---
---
IO
(PU
)
22.5
IOW#
O
V
PMR[21] = 0 and
PMR[2] = 0
3/5
RI2#
I
IN
PMR[18] = 1 and
PMR[8] = 0
TS
(PU
)
)
22.5
DOCW#
GPIO15
O
O
PMR[21] = 0 and
PMR[2] = 1
3/5
IRQ15
I
IN
PMR[18] = 0 and
PMR[8] = 1
TS1
(PU
22.5
I/O
IN
O
,
PMR[21] = 1 and
PMR[2] = 1
TS
3/5
H31
SDATA_IN2
I
IN
V
F3BAR0+Memory
Offset 08h[21] = 1
(PU
)
TS
SB
22.5
G4
ROMCS#
BOOT16
O
O
V
V
---
3/5
IO
IO
J1
J2
J3
HSYNC
VSYNC
IRTX
O
O
O
O
O
V
---
1/4
1/4
8/8
8/8
IO
IO
IO
I
IN
Strap (See Table 2-
6 on page 54.)
STRP
O
O
V
V
---
(PD
)
100
PMR[6] = 0
PMR[6] = 1
G28
G29
G30
GPWIO1
GPWIO2
I/O
(PU
IN
TS
,
V
V
---
Ts
SB
SB
)
100
SOUT3
GPIO17
O
2/14
I/O
(PU
IN
TS
,
---
3
J4
I/O
IN
O
,
V
TS
TS
3/5
IO
(PMR[23] = 0 and
)
(PU
)
)
)
100
22.5
PMR[5] = 0) or
2/14
3
(PMR[23] = 1 and
V
PWR
O
---
---
---
IO
PMR[15] = 1 and
PMR[5] = 0)
4, 5
14
PWRCNT2
TRDE#
V
---
G31
H1
OD
O
SB
3
IOCS0#
O
O
O
V
V
PMR[12] = 0
PMR[12] = 1
3/5
(PMR[23] = 0 and
3/5
IO
IO
(PU
22.5
PMR[5] = 1) or
GPIO0
I/O
IN
O
,
TS
3/5
3
(PMR[23] = 1 and
(PU
)
)
22.5
PMR[15] = 1 and
PMR[5] = 1)
3
H2
GPIO1
I/O
(PU
IN ,
T
O
V
V
V
IO
IO
IO
(PMR[23] = 0 and
22.5
22.5
22.5
PMR[13] = 0) or
3
3/5
TFTDCK
O
O
1/4
PMR[23] = 1 and
3
(PU
(PMR[23] = 1 and
22.5
PMR[15] = 0
PMR[15] = 1 and
PMR[13] = 0)
J28
J29
IRRX1
SIN3
I
IN
IN
IN
V
SB
PMR[6] = 0
TS
TS
TS
I
I
V
V
V
PMR[6] =1
3
IOCS1#
TFTD12
O
(PU
O
O
IO
IO
IO
3/5
1/4
(PMR[23] = 0 and
)
)
PMR[13] = 1) or
POR#
MD0
---
---
3
(PMR[23] = 1 and
4
I/O
IN ,
T
J30
PMR[15] = 1 and
PMR[13] = 1)
TS
2/5
4
3
MD1
I/O
IN ,
V
---
O
(PU
J31
T
IO
PMR[23] = 1 and
TS
PMR[15] = 0
2/5
www.national.com
26
Revision 6.0
Signal Definitions (Continued)
Table 2-2. 432-EBGA Ball Assignment - Sorted by Ball Number (Continued)
1
1
Ball
No.
I/O
Buffer Power
Rail Configuration
Ball
No.
I/O
Buffer Power
Rail Configuration
Signal Name
(PU/PD) Type
Signal Name
(PU/PD) Type
K1
RED
O
WIRE
AV
CCRT
---
P31
R1
BA1
O
PWR
GND
GND
PWR
PWR
O
O
V
IO
---
---
---
---
---
---
---
---
---
C-
2/5
V
V
---
---
PLL2
SS
K2
V
V
V
V
GND
PWR
GND
GND
I/O
---
---
---
---
---
---
---
---
---
---
SSCRT
CCCRT
SS
R2
---
---
---
---
---
---
---
---
K3
---
---
---
R3
AV
SSPLL2
K4
R4
V
V
CORE
CORE
K28
SS
R28
R29
R30
R31
4
MD2
MD3
MD4
IN ,
V
V
V
K29
K30
K31
T
IO
IO
IO
MA10
O
V
IO
2/5
TS
2/5
V
GND
O
---
---
4
4
SS
I/O
I/O
IN ,
---
---
T
TS
MA0
O
V
2/5
2/5
IO
IO
IN ,
4, 5
3
BUSY/WAIT#
I
IN
V
T
T1
T
PMR[23] = 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
TS
2/5
L1
AV
GND
GND
PWR
PWR
PWR
I/O
---
---
---
---
---
---
---
---
---
---
---
---
SSCRT
3
TFTD3
O
O
O
O
O
O
1/4
1/4
1/4
(PMR[23] = 1 and
L2
V
---
---
---
---
SS
PMR[15] = 0) and
(PMR[27] = 0 and
FPCI_MON = 0)
L3
AV
CCCRT
L4
V
CORE
CORE
3
VOPD2
(PMR[23] = 1 and
L28
V
PMR[15] = 1) and
(PMR[27] = 0 and
FPCI_MON = 0)
4
MD5
IN ,
V
IO
L29
T
TS
2/5
3
F_C/BE1#
PMR[23] = 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
L30
L31
V
GND
I/O
---
---
---
---
SS
4
MD6
IN ,
V
IO
T
TS
2/5
T2
T3
V
PWR
I
---
IN
---
V
---
IO
M1
M2
M3
AV
PWR
PWR
O
---
---
---
---
---
---
---
CCCRT
4, 5
3
PE
T
IO
PMR[23] = 0 and
(PU
22.5
(PMR[27] = 0 and
FPCI_MON = 0)
(PU/PD under soft-
ware control.)
V
IO
PD
)
22.5
GREEN
WIRE
AV
C-
CCRT
M4
V
GND
GND
I/O
---
---
---
---
---
---
3
SS
TFTD14
F_C/BE2#
SLCT
O
O
I
O
O
1/4
1/4
PMR[23] = 1 and
(PMR[27] = 0 and
FPCI_MON = 0)
M28
M29
V
---
SS
4
MD7
IN ,
V
T
IO
3
PMR[23] = 0 and
TS
2/5
(PMR[27] = 1 or
FPCI_MON = 1)
M30
M31
N1
V
PWR
O
---
---
---
---
---
---
IO
4, 5
3
IN
V
IO
DQM0
O
V
T4
T
PMR[23] = 0 and
2/5
IO
(PMR[27] = 0 and
FPCI_MON = 0)
AV
PWR
O
---
---
AV
CCCRT
N2
BLUE
WIRE
C-
3
TFTD15
F_C/BE3#
O
O
O
O
1/4
1/4
PMR[23] = 1 and
CCRT
(PMR[27] = 0 and
FPCI_MON = 0)
N3
AV
GND
PWR
PWR
O
---
---
---
---
---
---
---
---
---
---
---
SSCRT
3
N4
V
V
---
---
PMR[23] = 0 and
CORE
CORE
(PMR[27] = 1 or
FPCI_MON = 1)
N28
N29
N30
N31
P1
WEA#
CASA#
RASA#
VREF
O
O
O
V
V
V
2/5
2/5
2/5
IO
IO
IO
T28
T29
T30
T31
DQM4
MA2
O
O
O
O
V
V
---
---
---
---
2/5
2/5
IO
IO
O
O
V
PWR
O
---
---
CORE
I/O
WIRE
AV
C-
CCRT
MA1
PD7
O
V
V
2/5
IO
IO
4, 5
3
I/O
IN ,
T
U1
PMR[23] = 0 and
P2
SETRES
I
WIRE
AV
---
C-
O
(PMR[27] = 0 and
FPCI_MON = 0)
14/14
CCRT
P3
AV
GND
GND
GND
O
---
---
---
---
---
---
---
---
---
SSCRT
3
TFTD13
F_AD7
O
O
O
1/4
PMR[23] = 1 and
P4
V
---
---
SS
SS
(PMR[27] = 0 and
FPCI_MON = 0)
P28
P29
P30
V
3
O
14/14
PMR[23] = 0 and
CS0#
BA0
O
O
V
V
2/5
2/5
IO
IO
(PMR[27] = 1 or
FPCI_MON = 1)
O
Revision 6.0
27
www.national.com
Signal Definitions (Continued)
Table 2-2. 432-EBGA Ball Assignment - Sorted by Ball Number (Continued)
1
1
Ball
No.
I/O
Buffer Power
Rail Configuration
Ball
No.
I/O
Buffer Power
Rail Configuration
Signal Name
(PU/PD) Type
Signal Name
(PU/PD) Type
4
U2
V
GND
I
---
IN
--- ---
MD35
I/O
I/O
O
IN ,
V
V
V
---
SS
V30
V31
T
IO
IO
IO
TS
2/5
4, 5
3
ACK#
V
IO
U3
T
PMR[23] = 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
4
MD34
IN ,
T
---
TS
2/5
3
TFTDE
O
O
O
O
O
O
4, 5
4, 5
4, 5
3
1/4
1/4
1/4
(PMR[23] = 1 and
SLIN#/ASTRB#
O
14/14
W1
W2
W3
PMR[23] = 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[15] = 0) and
(PMR[27] = 0 and
FPCI_MON = 0)
3
TFTD16
F_IRDY#
PD3
O
O
O
1/4
PMR[23] = 1 and
(PMR[27] = 0 and
FPCI_MON = 0)
3
VOPCK
(PMR[23] = 1 and
PMR[15] = 1) and
(PMR[27] = 0 and
FPCI_MON = 0)
3
O
14/14
PMR[23] = 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
3
FPCICLK
PMR[23] = 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
3
I/O
O
IN ,
V
IO
T
PMR[23] = 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
O
14/14
U4
V
V
PWR
PWR
I/O
---
---
IN ,
---
---
---
---
---
CORE
U28
CORE
3
TFTD9
F_AD3
PD2
O
1/4
PMR[23] = 1 and
(PMR[27] = 0 and
FPCI_MON = 0)
4
4
MD33
V
IO
U29
T
TS
2/5
3
O
O
14/14
PMR[23] = 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
U30
U31
V
GND
I/O
---
---
---
---
SS
MD32
IN ,
T
V
IO
TS
2/5
3
I/O
O
IN ,
V
IO
T
PMR[23] = 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
4, 5
4, 5
4, 5
3
PD4
I/O
O
IN ,
V
V
V
O
14/14
V1
V2
V3
T
IO
PMR[23] = 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
O
14/14
3
TFTD8
O
1/4
1/4
(PMR[23] = 1 and
3
TFTD10
F_AD4
PD5
O
1/4
PMR[15] = 0) and
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23] = 1 and
(PMR[27] = 0 and
FPCI_MON = 0)
3
VOPD7
F_AD2
O
O
O
3
O
O
14/14
(PMR[23] = 1 and
PMR[23] = 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
PMR[15] = 1) and
(PMR[27] = 0 and
FPCI_MON = 0)
3
I/O
O
IN ,
T
IO
PMR[23] = 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
3
O
14/14
PMR[23] = 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
O
14/14
3
TFTD11
F_AD5
PD6
O
1/4
PMR[23] = 1 and
(PMR[27] = 0 and
FPCI_MON = 0)
W4
V
V
PWR
PWR
I/O
---
---
---
---
---
---
---
CORE
CORE
W28
W29
3
O
O
14/14
PMR[23] = 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
4
4
4
MD39
MD38
MD37
PD1
IN ,
V
T
IO
IO
IO
IO
TS
2/5
I/O
I/O
I/O
IN ,
V
V
V
---
---
W30
W31
T
3
I/O
O
IN ,
T
IO
PMR[23] = 0 and
TS
2/5
O
(PMR[27] = 0 and
FPCI_MON = 0)
14/14
IN ,
T
TS
3
2/5
TFTD1
O
1/4
1/4
(PMR[23] = 1 and
PMR[15] = 0) and
(PMR[27] = 0 and
FPCI_MON = 0
4, 5
3
IN ,
Y1
T
PMR[23] = 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
O
14/14
3
VOPD0
F_AD6
O
O
O
(PMR[23] = 1 and
3
TFTD7
VOPD6
F_AD1
O
O
O
1/4
1/4
(PMR[23] = 1 and
PMR[15] = 1) and
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[15] = 0) and
(PMR[27] = 0 and
FPCI_MON = 0)
3
O
14/14
PMR[23] = 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
3
O
(PMR[23] = 1 and
PMR[15] = 1) and
(PMR[27] = 0 and
FPCI_MON = 0)
V4
V
V
GND
GND
I/O
---
---
---
---
---
---
---
SS
3
O
O
14/14
---
PMR[23] = 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
V28
V29
SS
4
MD36
IN ,
V
IO
T
TS
2/5
Y2
V
PWR
---
---
IO
www.national.com
28
Revision 6.0
Signal Definitions (Continued)
Table 2-2. 432-EBGA Ball Assignment - Sorted by Ball Number (Continued)
1
1
Ball
No.
I/O
Buffer Power
Ball
No.
I/O
Buffer Power
Signal Name
(PU/PD) Type
Rail Configuration
Signal Name
(PU/PD) Type
Rail Configuration
4, 5
3
4, 5
3
INIT#
O
O
O
V
STB#/WRITE#
O
O
O
O
O
O
V
IO
Y3
14/14
IO
PMR[23] = 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
AB1
14/14
PMR[23] = 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
3
1/4
3
TFTD5
VOPD4
SMI_O
O
TFTD17
1/4
1/4
(PMR[23] = 1 and
O
PMR[23] = 1 and
PMR[15] = 0) and
(PMR[27] = 0 and
FPCI_MON = 0)
(PMR[27] = 0 and
FPCI_MON = 0)
3
F_FRAME#
AFD#/DSTRB#
TFTD2
O
O
14/14
14/14
PMR[23] = 0 and
3
O
O
O
(PMR[23] = 1 and
(PMR[27] = 1 or
FPCI_MON = 1)
PMR[15] = 1) and
(PMR[27] = 0 and
FPCI_MON = 0)
4, 5
3
V
AB2
IO
PMR[23] = 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
3
O
14/14
PMR[23] = 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
3
O
1/4
1/4
PMR[23] = 1 and
PMR[15] = 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
Y4
V
V
GND
GND
I/O
---
---
---
---
---
---
---
SS
Y28
SS
3
VOPD1
INTR_O
O
O
O
(PMR[23] = 1 and
4
4
MD46
IN ,
TS
V
IO
Y29
T
PMR[15] = 1) and
(PMR[27] = 0 and
FPCI_MON = 0)
2/5
Y30
Y31
V
PWR
I/O
---
---
---
IO
3
O
14/14
PMR[23] = 0 and
MD47
IN ,
TS
V
T
IO
(PMR[27] = 1 or
FPCI_MON = 1)
2/5
4, 5
3
PD0
I/O
O
IN ,
O
V
AA1
T
IO
PMR[23] = 0 and
AB3
AB4
CVBS
Y
O
O
O
WIRE AV
See F4BAR0+
Memory Offset
C08h[4:3] bit
description on
page 363.
CCTV
(PMR[27] = 0 and
FPCI_MON = 0)
14/14
TVG
3
TFTD6
VOPD5
F_AD0
O
1/4
1/4
(PMR[23] = 1 and
PMR[15] = 0) and
(PMR[27] = 0 and
FPCI_MON = 0)
V
V
GND
GND
I/O
---
---
---
---
---
---
---
SS
SS
AB28
AB29
3
O
O
O
(PMR[23] = 1 and
4
4
4
MD41
MD42
MD43
TVIOM
IN ,
TS
V
T
IO
IO
IO
PMR[15] = 1) and
(PMR[27] = 0 and
FPCI_MON = 0)
2/5
I/O
I/O
O
IN ,
TS
V
V
---
---
---
AB30
AB31
T
3
O
14/14
---
PMR[23] = 0 and
2/5
(PMR[27] = 1 or
FPCI_MON = 1)
IN ,
TS
T
2/5
AA2
AA3
V
GND
I
---
---
SS
AC1
AC2
WIRE AV
WIRE AV
CCTV
CCTV
4, 5
3
ERR#
IN ,
T
O
V
IO
PMR[23] = 0 and
SVC
Cr
O
O
See F4BAR0+
Memory Offset
C08h[4:3] bit
description on
page 363.
(PMR[27] = 0 and
FPCI_MON = 0)
1/4
3
TFTD4
O
O
O
O
Cb
O
1/4
(PMR[23] = 1 and
PMR[15] = 0) and
(PMR[27] = 0 and
FPCI_MON = 0)
TVB
TVR
O
O
3
AC3
AV
PWR
---
---
---
---
---
---
---
---
---
---
VOPD3
O
CCTV
1/4
(PMR[23] = 1 and
PMR[15] = 1) and
(PMR[27] = 0 and
FPCI_MON = 0)
AC4
AV
GND
O
SSTV
AC28
AC29
AC30
CKEA
O
O
O
V
2/5
2/5
2/5
IO
IO
IO
IO
3
F_C/BE0#
O
1/4
SDCLK0
DQM5
MD40
O
V
V
V
PMR[23] = 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
O
4
I/O
IN ,
T
TS
AA4
V
PWR
PWR
I/O
---
---
IN ,
---
---
---
---
---
AC31
AD1
CORE
2/5
AA28
AA29
V
CORE
SVY
O
O
WIRE AV
See F4BAR0+
Memory Offset
C08h[4:3] bit
description on
page 363.
CCTV
4
4
MD44
V
IO
T
TVR
TS
2/5
Cb
O
AA30
AA31
V
GND
I/O
---
---
---
---
SS
CVBS
TVREF
O
MD45
IN ,
TS
V
IO
T
AD2
I/O
WIRE AV
---
CCTV
2/5
Revision 6.0
29
www.national.com
Signal Definitions (Continued)
Table 2-2. 432-EBGA Ball Assignment - Sorted by Ball Number (Continued)
1
1
Ball
No.
I/O
Buffer Power
Rail Configuration
Ball
No.
I/O
Buffer Power
Rail Configuration
Signal Name
(PU/PD) Type
Signal Name
(PU/PD) Type
4
AD3
CVBS
Cr
O
O
O
WIRE AV
See F4BAR0+
Memory Offset
C08h[4:3] bit
description on
page 363.
DPOS_PORT1
I/O
I/O
IN
O
,
AV
C-
CUSB
---
CCTV
AH2
USB
USB
AH3
GPIO6
IN
O
,
V
PMR[18] = 0 and
PMR[8] = 0
TVB
TS
IO
(PU
)
22.5
1/4
AD4
TVCOMP
MA6
I
WIRE AV
---
---
---
---
---
---
---
---
DTR2#/BOUT2
IDE_IOR1#
SDTEST5
GPIO7
O
O
O
O
PMR[18] = 1 and
PMR[8] = 0
CCTV
1/4
(PU
)
)
)
)
22.5
AD28
AD29
AD30
AD31
AE1
O
O
O
O
O
V
2/5
2/5
2/5
2/5
IO
IO
IO
IO
O
PMR[18] = 0 and
PMR[8] = 1
1/4
2/5
MA7
O
V
V
V
(PU
22.5
MA8
O
O
PMR[18] = 1 and
PMR[8] = 1
(PU
MA9
O
22.5
AH4
I/O
(PU
IN
O
,
V
PMR[17] = 0 and
PMR[8] = 0
TVRSET
I
PWR
I
WIRE AV
---
TS
1/4
IO
CCTV
22.5
AE2
V
IO
---
RTS2#
O
O
O
O
PMR[17] = 1 and
PMR[8] = 0
1/4
1/4
2/5
AE3
INTA#
IN
V
IO
PCI
(PU
)
)
)
22.5
(PU
)
22.5
IDE_DACK1#
SDTEST0
O
PMR[17] = 0 and
PMR[8] = 1
4
DPOS_PORT3
I/O
IN
O
,
AV
C-
CUSB
---
AE4
USB
USB
(PU
22.5
O
PMR[17] = 1 and
PMR[8] = 1
AE28
AE29
AE30
AE31
AF1
MA3
MA4
O
O
O
V
---
---
---
---
---
(PU
2/5
2/5
IO
22.5
O
V
AH5
AH6
TDP
TDO
I/O
O
Diode
---
---
---
IO
V
PWR
O
---
---
O
V
V
V
V
IO
PCI
IO
IO
IO
IO
MA5
O
V
V
AH7
AH8
AH9
VPCKIN
VPD4
I
IN
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
2/5
IO
IO
T
T
T
INTB#
I
IN
I
IN
IN
PCI
(PU
)
22.5
VPD0
I
AF2
V
GND
---
---
AV
---
---
SS
AH10
AH11
AH12
AH13
AH14
AH15
AH16
AH17
AH18
AH19
AH20
AH21
AH22
V
V
V
V
V
V
GND
PWR
GND
PWR
GND
PWR
O
---
---
---
---
---
---
---
SS
4
DNEG_PORT3
I/O
IN
O
,
AF3
USB
USB
C-
---
---
---
---
---
CORE
SS
CUSB
AF4
AV
PWR
I/O
---
IN ,
---
---
---
CCUSB
CORE
SS
4
MD14
V
V
AF28
T
IO
IO
TS
2/5
4
MD15
I/O
IN ,
---
AF29
T
CORE
TS
2/5
SDCLK1
O
V
IO
2/5
AF30
AF31
AG1
V
GND
O
---
---
---
---
---
---
SS
V
V
V
V
V
V
PWR
GND
PWR
GND
PWR
GND
I/O
---
---
---
---
---
---
---
---
---
---
---
---
CORE
SS
DQM1
AV
O
V
2/5
IO
GND
I/O
---
---
AV
SSUSB
CORE
SS
4
DNEG_PORT2
DNEG_PORT1
GPIO9
IN
O
,
AG2
USB
USB
C-
CUSB
CORE
SS
4
I/O
I/O
IN
O
,
AV
C-
CUSB
---
AG3
AG4
USB
USB
4
4
4
4
4
MD28
MD55
MD51
MD48
MD23
IN ,
T
TS
2/5
V
IN
,
V
PMR[18] = 0 and
PMR[8] = 0
AH23
AH24
AH25
AH26
AH27
IO
IO
IO
IO
IO
TS
IO
(PU
)
O
22.5
1/4
I/O
I/O
I/O
I/O
IN ,
TS
2/5
V
V
V
V
---
---
---
---
DCD2#
I
IN
PMR[18] = 1 and
PMR[8] = 0
T
TS
1/4
2/5
2/5
(PU
)
)
)
22.5
IDE_IOW1#
SDTEST2
O
O
O
O
PMR[18] = 0 and
PMR[8] = 1
IN ,
T
TS
(PU
22.5
2/5
O
PMR[18] = 1 and
PMR[8] = 1
IN ,
TS
T
(PU
22.5
2/5
AG28
AG29
MA11
MD9
O
V
V
---
---
IO
IO
IN ,
TS
T
4
4
4
I/O
I/O
I/O
I/O
IN ,
T
2/5
TS
2/5
AH28
AH29
SDCLK_OUT
MA12
O
O
O
O
V
V
V
---
---
---
2/5
2/5
IO
IO
IO
MD8
IN ,
V
V
---
---
---
AG30
AG31
T
IO
IO
TS
2/5
4
4
MD11
I/O
IN ,
T
TS
AH30
AH31
MD13
IN ,
T
2/5
TS
2/5
MD10
I/O
IN ,
TS
V
---
T
IO
4
DPOS_PORT2
IN
O
,
AV
AH1
USB
USB
C-
CUSB
2/5
www.national.com
30
Revision 6.0
Signal Definitions (Continued)
Table 2-2. 432-EBGA Ball Assignment - Sorted by Ball Number (Continued)
1
1
Ball
No.
I/O
Buffer Power
Rail Configuration
Ball
No.
I/O
Buffer Power
Signal Name
(PU/PD) Type
Signal Name
(PU/PD) Type
Rail Configuration
3
AJ1
GPIO10
I/O
(PU
IN
O
,
V
PMR[18] = 0 and
PMR[8] = 0
AJ13
AB1C
I/O IN
,
V
TS
8/8
IO
AB
IO
PMR[23] = 0 or
(PMR[23] = 1 and
PMR[15] = 1)
)
(PU
)
OD
22.5
22.5
8
DSR2#
I
IN
PMR[18] = 1 and
PMR[8] = 0
TS
3
GPIO20
I/O
(PU
IN ,
T
O
(PU
)
)
)
)
PMR[23] = 1 and
22.5
)
22.5
PMR[15] = 0 and
PMR[7] = 0
3/5
IDE_IORDY1
SDTEST1
GPIO8
I
IN
PMR[18] = 0 and
PMR[8] = 1
TS1
(PU
22.5
3
DOCCS#
O
O3/5
PMR[23] = 1 and
O
O
PMR[18] = 1 and
PMR[8] = 1
2/5
PMR[15] = 0 and
PMR[7] = 1
(PU
22.5
22.5
AJ2
I/O
(PU
IN
O
,
V
PMR[17] = 0 and
PMR[8] = 0
TS
8/8
IO
AJ14
AJ15
AC97_CLK
AC97_RST#
F_STOP#
SDCLK3
O
O
O
O
O
O
V
V
PMR[25] = 1
FPCI_MON = 0
FPCI_MON = 1
---
2/5
2/5
2/5
2/5
IO
IO
CTS2#
I
IN
PMR[17] = 1 and
PMR[8] = 0
TS
O
(PU
)
)
)
22.5
AJ16
AJ17
O
V
V
IDE_DREQ1
SDTEST4
I
IN
PMR[17] = 0 and
PMR[8] = 1
IO
IO
TS1
(PU
22.5
4
4
4
MD56
I/O
IN ,
---
T
O
O
PMR[17] = 1 and
PMR[8] = 1
TS
2/5
2/5
(PU
22.5
MD58
MD61
I/O
I/O
IN ,
TS
2/5
V
V
---
---
AJ18
AJ19
T
IO
IO
AJ3
AJ4
V
PWR
---
---
---
IO
SIN2
I
O
I
IN
V
PMR[28] = 0
PMR[28] = 1
---
TS
2/5
PCI
IO
IN ,
T
TS
2/5
SDTEST3
TMS
O
AJ20
AJ21
DQM7
DQM3
MD25
O
O
O
O
V
V
V
---
---
---
2/5
2/5
IO
IO
IO
AJ5
IN
V
IO
(PU
)
22.5
AJ6
AJ7
AJ8
AJ9
VPD7
I
IN
V
V
V
V
---
---
---
T
T
T
IO
IO
IO
IO
4
4
4
4
I/O
IN ,
T
AJ22
AJ23
AJ24
AJ25
TS
VPD6
I
I
IN
IN
2/5
MD29
MD54
MD50
I/O
I/O
I/O
IN ,
TS
V
V
V
---
---
---
VPD2
T
IO
IO
IO
2/5
6
GPIO38/IRRX2
I/O
(PU
IN
O
,
PCI
PCI
PMR[14] = 0 and
)
IN ,
TS
6
22.5
T
PMR[22] = 0. The
2/5
IRRX2 input is con-
nected to the input
path of GPIO38.
There is no logic
required to enable
IRRX2, just a sim-
ple connection.
Hence, when
IN ,
T
TS
2/5
AJ26
AJ27
DQM6
MD22
O
O
V
V
---
---
2/5
IO
IO
4
4
I/O
IN ,
T
TS
2/5
GPIO38 is the
selected function,
IRRX2 is also
MD19
I/O
IN ,
V
---
AJ28
T
IO
TS
2/5
selected.
AJ29
AJ30
V
PWR
I
---
IN
---
---
---
---
IO
6
LPCPD#
GPIO35
LAD3
O
O
PCI
PMR[14] = 1 and
SDCLK_IN
MD12
V
V
T
IO
IO
6
PMR[22] = 1
4
I/O
IN ,
T
AJ31
6
AJ10
AJ11
AJ12
I/O
(PU
IN
O
,
V
V
V
PCI
PCI
IO
IO
IO
PMR[14] = 0 and
TS
2/5
)
)
)
)
6
22.5
PMR[22] = 0
AK1
AK2
AK3
V
V
PWR
GND
O
---
---
---
---
---
---
---
IO
6
I/O
(PU
IN
O
,
PCI
PCI
PMR[14] = 1 and
6
SS
22.5
PMR[22] = 1
SOUT2
O
V
8/8
IO
6
GPIO32
LAD0
I/O
(PU
IN
O
,
PCI
PCI
PMR[14] = 0 and
6
22.5
CLKSEL2
I
IN
Strap (See Table 2-
6 on page 54.)
PMR[22] = 0
STRP
(PD
)
100
6
I/O
(PU
IN
O
,
PCI
PCI
PMR[14] = 1 and
AK4
AK5
AK6
TRST#
TDI
I
IN
V
V
---
---
---
6
PCI
PCI
IO
IO
22.5
PMR[22] = 1
(PU
(PU
)
)
22.5
GPIO12
AB2C
I/O
(PU
IN
O
,
PMR[19] = 0
PMR[19] = 1
AB
8/8
I
IN
)
)
22.5
22.5
I/O
(PU
IN
OD
,
AB
V
PWR
---
---
IO
22.5
8
Revision 6.0
31
www.national.com
Signal Definitions (Continued)
Table 2-2. 432-EBGA Ball Assignment - Sorted by Ball Number (Continued)
1
1
Ball
No.
I/O
Buffer Power
Rail Configuration
Ball
No.
I/O
Buffer Power
Signal Name
(PU/PD) Type
Signal Name
(PU/PD) Type
Rail Configuration
6
AK7
AK8
AK9
V
GND
I
---
IN
---
---
---
AL8
GPIO39
I/O
(PU
IN
O
,
V
V
V
SS
PCI
PCI
IO
IO
IO
PMR[14] = 0 and
)
)
6
22.5
PMR[22] = 0
VPD1
V
T
IO
IO
6
SERIRQ
GPIO36
LDRQ#
GPIO33
LAD1
I/O
IN
O
,
6
PCI
PCI
PMR[14] = 1 and
GPIO37
I/O
IN
O
,
V
PCI
PMR[14] = 0 and
6
(PU
)
6
PMR[22] = 1
22.5
PCI
PMR[22] = 0
6
AL9
I/O
IN
O
,
PCI
PCI
PMR[14] = 0 and
6
LFRAME#
GPIO34
LAD2
O
O
PCI
PMR[14] = 1 and
(PU
6
22.5
6
PMR[22] = 0
PMR[22] = 1
6
I
IN
PCI
6
PMR[14] = 1 and
AK10
I/O
(PU
IN
O
,
V
PCI
PCI
IO
PMR[14] = 0 and
6
)
)
6
PMR[22] = 1
22.5
PMR[22] = 0
6
AL10
I/O
IN
O
,
PCI
PCI
PMR[14] = 0 and
6
I/O
(PU
IN
O
,
PCI
PCI
PMR[14] = 1 and
(PU
)
)
6
22.5
6
PMR[22] = 0
22.5
PMR[22] = 1
6
I/O
(PU
IN
O
,
PCI
PCI
PMR[14] = 1 and
AK11
AK12
AK13
V
V
PWR
GND
O
---
---
---
---
---
---
---
IO
6
22.5
PMR[22] = 1
SS
AL11
AL12
GPIO13
AB2D
I/O
(PU
IN
O
,
V
V
V
PMR[19] = 0
PMR[19] = 1
AB
8/8
IO
IO
IO
SDATA_OUT
TFT_PRSNT
O
V
AC97
STRP
IO
IO
)
)
)
22.5
I
IN
V
Strap (See Table 2-
6 on page 54.)
I/O
(PU
IN
OD
,
AB
(PD
)
100
22.5
8
AK14
SDATA_IN
F_GNT0#
I
IN
V
FPCI_MON = 0
T
IO
3
AB1D
I/O
(PU
IN
OD
,
AB
PMR[23] = 0 or
O
O
FPCI_MON = 1
22.5
(PMR[23] = 1 and
PMR[15] = 1)
2/5
8
AK15
AK16
AK17
V
V
V
GND
PWR
GND
I/O
---
---
---
---
---
---
SS
IO
3
GPIO1
I/O
(PU
IN ,
T
O
PMR[23] = 1 and
---
---
---
---
)
22.5
PMR[15] = 0 and
PMR[13] = 0
3/5
SS
3
IOCS1#
O
O
4
4
MD59
IN ,
V
3/5
PMR[23] = 1 and
AK18
AK19
T
IO
PMR[15] = 0 and
PMR[13] = 1
TS
2/5
MD62
I/O
IN ,
V
---
T
IO
AL13
SYNC
O
I
O
V
---
AC97
IO
TS
2/5
CLKSEL3
IN
Strap (See Table 2-
6 on page 54.)
STRP
AK20
AK21
V
V
PWR
GND
I/O
---
---
---
---
---
---
---
IO
(PD
)
100
SS
AL14
AL15
BIT_CLK
F_TRDY#
GPIO16
I
IN
V
V
FPCI_MON = 0
FPCI_MON = 1
T
IO
IO
4
4
4
MD26
MD30
MD53
IN ,
V
AK22
AK23
AK24
T
IO
IO
IO
O
O
1/4
TS
2/5
I/O
IN ,
T
O
PMR[0] = 0 and
FPCI_MON = 0
I/O
I/O
IN ,
V
V
---
---
T
(PU
)
22.5
2/5
TS
2/5
PC_BEEP
O
O
PMR[0] = 1 = 0 and
FPCI_MON = 0
2/5
IN ,
T
TS
2/5
F_DEVSEL#
GXCLK
O
O
O
O
FPCI_MON = 1
2/5
2/5
AK25
AK26
V
V
PWR
GND
I/O
---
---
---
---
---
---
---
IO
AL16
V
(PMR[29] = 0 and
IO
3
SS
PMR[23] = 0) or
3
(PMR[23] = 1 and
4
4
MD21
MD18
CS1#
IN ,
V
AK27
T
IO
IO
IO
PMR[15] = 1)
TS
2/5
3
FP_VDD_ON
TEST3
O
O
O
1/4
2/5
PMR[23] = 1 and
I/O
IN ,
V
---
AK28
T
PMR[15] = 0
TS
2/5
O
PMR[29] = 1 and
AK29
AK30
AK31
AL1
O
O
V
---
---
---
---
---
---
---
2/5
3
PMR[23] = 0
V
V
V
V
GND
PWR
GND
PWR
I/O
---
---
SS
IO
4
4
4
MD57
I/O
I/O
I/O
IN ,
TS
2/5
V
V
V
---
---
---
AL17
AL18
AL19
T
IO
IO
IO
---
---
---
---
---
MD60
IN ,
T
TS
SS
IO
2/5
AL2
---
MD63
IN ,
T
TS
AL3
TDN
TCK
WIRE
V
IO
IO
2/5
AL4
I
IN
V
PCI
AL20
AL21
SDCLK2
MD24
O
O
V
V
---
---
2/5
IO
IO
(PU
)
)
22.5
4
4
I/O
IN ,
T
TS
AL5
GTEST
I
IN
V
---
T
IO
(PD
2/5
22.5
MD27
I/O
IN ,
TS
V
---
AL6
AL7
VPD5
VPD3
I
I
IN
V
V
---
---
AL22
T
IO
T
T
IO
IO
2/5
IN
www.national.com
32
Revision 6.0
Signal Definitions (Continued)
Table 2-2. 432-EBGA Ball Assignment - Sorted by Ball Number (Continued)
1
Ball
No.
I/O
Buffer Power
Rail Configuration
Signal Name
(PU/PD) Type
4
4
4
MD31
I/O
I/O
I/O
IN ,
V
V
V
---
---
---
AL23
AL24
AL25
T
IO
IO
IO
TS
2/5
MD52
MD49
IN ,
T
TS
2/5
IN ,
T
TS
2/5
AL26
AL27
DQM2
MD20
O
O
V
V
---
---
2/5
IO
IO
4
4
4
I/O
IN ,
T
TS
2/5
MD17
MD16
I/O
I/O
IN ,
TS
V
V
---
---
AL28
AL29
T
IO
IO
2/5
IN ,
T
TS
2/5
AL30
AL31
V
V
PWR
GND
---
---
---
---
---
---
IO
SS
1.
2.
3.
4.
For Buffer Type definitions, refer to Table 8-9 "Buffer Types" on page
377.
May need 5V tolerant protection at system level (DDC_SCL,
DDC_SDA).
The TFT_PRSNT strap determines the power-on reset (POR) state of
PMR[23].
Is back-drive protected (MD[63:0], DPOS_PORT1, DNEG_PORT1,
DPOS_PORT2, DNEG_PORT2, DPOS_PORT3, DNEG_PORT3,
ACK#, AFD#/DSTRB#, BUSY/WAIT#, ERR#, INIT#, PD[7:0], PE,
SLCT, SLIN#/ASTRB#, STB#/WRITE#, ONCTL#, PWRCNT[2:1]).
Is 5V tolerant (ACK#, AFD#/DSTRB#, BUSY/WAIT#, ERR#, INIT#,
PD[7:0], PE, SLCT, SLIN#/ASTRB#, STB#/WRITE#, ONCTL#,
PWRCNT[2:1]).
5.
6.
The LPC_ROM strap determines the power-on reset (POR) state of
PMR[14] and PMR[22].
Revision 6.0
33
www.national.com
Signal Definitions (Continued)
Table 2-3. 432-EBGA Ball Assignment - Sorted Alphabetically by Signal Name
Signal Name
Ball No.
Signal Name
Ball No.
Signal Name
Ball No.
A0
A17
D16
A18
A15
A16
A14
C15
B14
C14
B13
C13
C12
A12
C11
A11
B10
A7
AD18
D7
A6
D0
C5
D5
A1
AD19
D1
A2
AD20
D6
D2
A4
A3
AD21
C6
D3
B4
A4
AD22
A5
D4
C4
A5
AD23
F4
D5
A3
A6
AD24
C5
D6
C2
A7
AD25
D5
D7
B3
A8
AD26
A4
D8
A13
A10
D8
A9
AD27
B4
D9
A10
AD28
C4
D10
A11
AD29
A3
D11
A8
A12
AD30
C2
D12
C10
B8
A13
AD31
B3
D13
A14
AFD#/DSTRB#
AVCCCRT
AB2
L3, M1, N1
D14
C8
A15
D15
D9
A16
DCD2#
DDC_SCL
DDC_SDA
DEVSEL#
DID0
AG4
A20
C20
B5
AVCCTV
AC3
AF4
A17
C7
AVCCUSB
AVSSCRT
AVSSPLL2
AVSSPLL3
AVSSTV
A18
D7
L1, N3, P3
R3
A19
A6
A20
D6
D4
E28
A21
C6
DID1
D2
AC4
A22
A5
DNEG_PORT1
DNEG_PORT2
DNEG_PORT3
DOCCS#
DOCR#
DOCW#
DPOS_PORT1
DPOS_PORT2
DPOS_PORT3
DQM0
AG3
AG2
AF3
H3, AJ13
F1
AVSSUSB
AG1
A23
F4
BA0
P30
P31
AB1C
AB1D
AB2C
AB2D
AC97_CLK
AC97_RST#
ACK#
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AJ13
AL12
AJ12
AL11
AJ14
AJ15
U3
BA1
BHE#
B5
BIT_CLK
BLUE
AL14
N2
G3
AH2
AH1
AE4
M31
AF31
AL26
AJ21
T28
AC30
AJ26
AJ20
AJ1
A28
AH3
AA3
AA1
Y1
BOOT16
BUSY/WAIT#
C/BE0#
C/BE1#
C/BE2#
C/BE3#
CASA#
Cb
G4
T1
A13
A17
D16
A18
A15
A16
A14
C15
B14
C14
B13
C13
C12
A12
C11
A11
B10
A7
A10
DQM1
D8
DQM2
A8
DQM3
N30
DQM4
AC2, AD1
AC28
A23
DQM5
CKEA
DQM6
CLK27M
CLK32
CLKSEL0
CLKSEL1
CLKSEL2
CLKSEL3
Cr
DQM7
H29
DSR2#
DTR1#/BOUT1
DTR2#/BOUT2
ERR#
F3
B27
AK3
AL13
AC2, AD3
P29
F_AD0
F_AD1
F_AD2
F_AD3
F_AD4
F_AD5
CS0#
W3
CS1#
AK29
AJ2
W2
CTS2#
CVBS
V1
AB3, AD1, AD3
C7
V2
www.national.com
34
Revision 6.0
Signal Definitions (Continued)
Table 2-3. 432-EBGA Ball Assignment - Sorted Alphabetically by Signal Name (Continued)
Signal Name
Ball No.
Signal Name
Ball No.
Signal Name
Ball No.
F_AD6
V3
U1
GREEN
M3
AL5
AL16
J1
IRQ14
IRQ15
IRRX1
IRTX
D25
H30
F_AD7
GTEST
F_C/BE0#
F_C/BE1#
F_C/BE2#
F_C/BE3#
F_DEVSEL#
F_FRAME#
F_GNT0#
F_IRDY#
F_STOP#
F_TRDY#
FP_VDD_ON
FPCI_MON
FPCICLK
FRAME#
GNT0#
AA3
T1
GXCLK
J28
HSYNC
J3
T3
IDE_ADDR0
IDE_ADDR1
IDE_ADDR2
IDE_CS0#
IDE_CS1#
IDE_DACK0#
IDE_DACK1#
IDE_DATA0
IDE_DATA1
IDE_DATA2
IDE_DATA3
IDE_DATA4
IDE_DATA5
IDE_DATA6
IDE_DATA7
IDE_DATA8
IDE_DATA9
IDE_DATA10
IDE_DATA11
IDE_DATA12
IDE_DATA13
IDE_DATA14
IDE_DATA15
IDE_DREQ0
IDE_DREQ1
IDE_IOR0#
IDE_IOR1#
IDE_IORDY0
IDE_IORDY1
IDE_IOW0#
IDE_IOW1#
IDE_RST#
INIT#
A26
C26
C17
A27
C16
C25
AH4
B24
A24
D23
C23
B23
A23
C22
B22
A21
C20
A20
C19
B19
A19
C18
B18
C24
AJ2
C21
AH3
A25
AJ1
D24
AG4
A22
Y3
LAD0
LAD1
LAD2
LAD3
LDRQ#
LED#
LFRAME#
LOCK#
LPC_ROM
LPCPD#
MA0
AJ11
AL10
AK10
AJ10
AL9
T4
AL15
AB1
AK14
W1
D31
AJ15
AL14
B23, AL16
D3
AK9
C9
E4
AJ9
U3
R31
E1
MA1
T31
D4
MA2
T29
GNT1#
D2
MA3
AE28
AE29
AE31
AD28
AD29
AD30
AD31
R29
GPIO0
H1
MA4
GPIO1
H2, AL12
AH3
AH4
AJ2
AG4
AJ1
H30
AJ12
AL11
F1
MA5
GPIO6
MA6
GPIO7
MA7
GPIO8
MA8
GPIO9
MA9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO20
GPIO32
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
GPIO38
GPIO39
GPIO40
GPIO41
GPWIO0
GPWIO1
GPWIO2
MA10
MA11
MA12
MD0
AG28
AH29
J30
MD1
J31
G3
MD2
K29
AL15
J4
MD3
K30
MD4
K31
A28
H4
MD5
L29
MD6
L31
H3
MD7
M29
AG30
AG29
AH31
AH30
AJ31
AG31
AF28
AF29
AL29
AL28
AK28
AJ28
AL27
AK27
AJ13
AJ11
AL10
AK10
AJ10
AL9
AK9
AJ9
AL8
A21
C19
E31
G28
G29
MD8
MD9
INTA#
AE3
AF1
H4
MD10
MD11
MD12
MD13
MD14
MD15
MD16
MD17
MD18
MD19
MD20
MD21
INTB#
INTC#
INTD#
B22
AB2
H4
INTR_O
IOCHRDY
IOCS0#
J4
IOCS1#
H2, AL12
F1
IOR#
IOW#
G3
IRDY#
C8
IRQ9
C22
Revision 6.0
35
www.national.com
Signal Definitions (Continued)
Table 2-3. 432-EBGA Ball Assignment - Sorted Alphabetically by Signal Name (Continued)
Signal Name
Ball No.
Signal Name
Ball No.
Signal Name
Ball No.
MD22
MD23
MD24
MD25
MD26
MD27
MD28
MD29
MD30
MD31
MD32
MD33
MD34
MD35
MD36
MD37
MD38
MD39
MD40
MD41
MD42
MD43
MD44
MD45
MD46
MD47
MD48
MD49
MD50
MD51
MD52
MD53
MD54
MD55
MD56
MD57
MD58
MD59
MD60
MD61
MD62
MD63
ONCTL#
OVER_CUR#
PAR
AJ27
AH27
AL21
AJ22
AK22
AL22
AH23
AJ23
AK23
AL23
U31
PCIRST#
PD0
D1
AA1
Y1
SLIN#/ASTRB#
SMI_O
SOUT1
SOUT2
SOUT3
STB#/WRITE#
STOP#
SVC
W1
Y3
PD1
B27
PD2
W3
AK3
PD3
W2
J3
PD4
V1
AB1
PD5
V2
D9
PD6
V3
AC2
PD7
U1
SVY
AD1
PE
T3
SYNC
AL13
PERR#
PLL2B
B9
TCK
AL4
U29
D28
B29
C28
J29
B28
E29
F31
G31
N31
F3
TDI
AK5
V31
PLL5B
TDN
AL3
V30
PLL6B
TDO
AH6
V29
POR#
TDP
AH5
W31
W30
W29
AC31
AB29
AB30
AB31
AA29
AA31
Y29
POWER_EN
PWRBTN#
PWRCNT1
PWRCNT2
RASA#
RD#
TEST0
TEST1
TEST2
TEST3
TFT_PRSNT
TFTD0
TFTD1
TFTD2
TFTD3
TFTD4
TFTD5
TFTD6
TFTD7
TFTD8
TFTD9
TFTD10
TFTD11
TFTD12
TFTD13
TFTD14
TFTD15
TFTD16
TFTD17
TFTDCK
TFTDE
THRM#
TMS
D28
C28
B29
AL16
AK13
C25, H3
D25, V3
C26, AB2
A26, T1
C17, AA3
A27, Y3
B24, AA1
B18, Y1
C24, W3
D24, W2
C21, V1
A25, V2
C23, H2
B19, U1
D23, T3
A19, T4
A24, W1
C18, AB1
A22, J4
C16, U3
F28
RED
K1
REQ0#
REQ1#
RI2#
C1
E3
H30
G4
Y31
ROMCS#
RTS2#
AH26
AL25
AJ25
AH25
AL24
AK24
AJ24
AH24
AJ17
AL17
AJ18
AK18
AL18
AJ19
AK19
AL19
E30
AH4
AK14
H31
AK13
AJ30
AH28
AC29
AH16
AL20
AJ16
AH4
AJ1
AG4
AJ4
AJ2
AH3
AL8
A9
SDATA_IN
SDATA_IN2
SDATA_OUT
SDCLK_IN
SDCLK_OUT
SDCLK0
SDCLK1
SDCLK2
SDCLK3
SDTEST0
SDTEST1
SDTEST2
SDTEST3
SDTEST4
SDTEST5
SERIRQ
SERR#
SETRES
SIN1
AJ5
TRDE#
TRDY#
TRST#
TVB
H1
C27
B8
C10
P2
AK4
PC_BEEP
PCICLK
PCICLK0
PCICLK1
AL15
E2
D26
AJ4
J28
T4
AC2, AD3
AD4
SIN2
TVCOMP
TVG
D3
SIN3
AB3
E4
SLCT
TVIOM
AC1
www.national.com
36
Revision 6.0
Signal Definitions (Continued)
Table 2-3. 432-EBGA Ball Assignment - Sorted Alphabetically by Signal Name (Continued)
Signal Name
Ball No.
Signal Name
Ball No.
Signal Name
Ball No.
TVR
AC2, AD1
AD2
VOPD3
VOPD4
VOPD5
VOPD6
VOPD7
VPCKIN
VPD0
AA3
Y3
VSS (Total of 56)
A1, A31, B2, B7,
B12, B15, B17,
B21, B26, B30,
D10, D12, D14,
D18, D20, D22,
F2, F30, K4, K28,
L2, L30, M4, M28,
P4, P28, R2, R30,
U2, U30, V4, V28,
Y4, Y28, AA2,
AA30, AB4,
AB28, AF2, AF30,
AH10, AH12,
AH14, AH18,
AH20, AH22,
AK2, AK7, AK12,
AK15, AK17,
TVREF
TVRSET
VBAT
AE1
AA1
Y1
D30
W3
VCCCRT
K3
AH7
AH9
AK8
AJ8
AL7
AH8
AL6
AJ7
AJ6
R1
V
CORE (Total of 25) D11, D13, D15,
D17, D19, D21,
L4, L28, N4, N28,
R4, R28, T30, U4,
U28, W4, W28,
AA4, AA28,
AH11, AH13,
AH15, AH17,
AH19, AH21
VPD1
VPD2
VPD3
VPD4
VPD5
VPD6
V
IO (Total of 31)
A2, A30, B1, B6,
B11, B16, B20,
B25, B31, C3,
C29, G2, G30,
M2, M30, T2, Y2,
Y30, AE2, AE30,
AJ3, AJ29, AK1,
AK6, AK11,
VPD7
AK21, AK26,
AK30, AL1, AL31
VPLL2
VSSCRT
K2
VPLL3
C31
VSYNC
WEA#
WR#
X27I
J2
VREF
VSB
P1
N29
G1
F29
VSBL
H28
AK16, AK20,
AK25, AK31, AL2,
AL30
A29
D27
C30
D29
AB3
X27O
X32I
VOPCK
VOPD0
VOPD1
VOPD2
U3
V3
X32O
Y
AB2
T1
Revision 6.0
37
www.national.com
Signal Definitions (Continued)
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
S
A
B
A
VSS
VSS
VIO AD30 PCK0 REQ1# PRST# PCICK IOW# GP20 GP17 HSNC AVCCCT VSS GREEN BLUE VSS VPLL2 PD7 VSS PD6 PD1 STB# CVBS SVY TVRST D+P3 D-P3 D+P1 D-P1 VIO
VSS
VIO
S
B
VIO AD29 AD28 REQ0# AD23 VSS RD# WR# VSS VSNC RED VIO AVSSCT STRES VIO BUSY ACK# VIO SLIN# INIT# VSS TVIOM AVSSTV VSS TVCMP D+P2 D-P2 GP10 VSS
S
S
S
C
C
AD26 AD24 VIO AD25 GNT0# GNT1# VIO RMCS# GP19 VIO IRTX VSSCT AVCCCT AVSSCTAVSSCT AVSSP2 SLCT PD4 PD5 PD3 PD0 VIO SVC TVREF VIO INTB# AVSSUSB GP9 VIO GP7 GP8
S
S
D
D
AD21 AD22 AD20 AD27 AD31 PCK1 VSS FRM# IOR# GP1 TRDE# VCCCT VSS
VIO AVCCCT VREF PE
VIO
VSS PD2 ERR# AFD# AVCCTV CVBS VSS INTA# AVCCUSB GP6 SOUT TDP TDN
E
E
AD16 AD19 AD18 DVSL#
TRDY# IRDY# CBE2# AD17
SIN2 TRST# TDO TCK
TMS TDI GTST VPCKI
F
F
G
G
VSS
VIO
VSS VPD7
STOP# VSS
VIO
VSS
H
H
VPD6 VPD5 VPD4 VPD3
VPD2 VPD1 VPD0 GP39
SRR# PRR# LOCK# CBE3#
AD13 CBE1# AD15 PAR
J
J
K
K
AD11 VIO
VSS AD14
GP38 VIO
GP36 GP35 GP34 GP33
GP32 GP13 VIO VSS
VSS GP12 AB1D AB1C
VSS GP37
Geode™
VCORE VCORE VSS VSS VSS VCORE VCORE
VCORE VCORE VSS VSS VSS VCORE VCORE
VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS
VCORE VCORE VSS VSS VSS VCORE VCORE
VCORE VCORE VSS VSS VSS VCORE VCORE
L
L
CBE0# AD9 AD10 AD12
VSS AD7 VIO AD8
AD3 AD6 AD5 VSS
AD4 ICS1# AD1 VCORE
VSS VSS VSS VSS
VCORE VCORE VCORE VCORE
AD0 IAD2 AD2 VCORE
IDAT15 IDAT14 IDAT13 VSS
M
M
N
N
S
S
P
P
VCORE SDO SYNC ACCK
VSS VSS VSS VSS
VCORE VCORE VCORE VCORE
VCORE ACRST# BITCK SDI
VSS SDCK3 GXCK GP16
R
R
T
T
U
U
V
V
W
Y
W
Y
VIO
VSS IDAT12 IDAT11
MD57 SDCK1 VSS
VIO
IDAT10 IDAT9 IDAT8 IIOR0#
IRST# IDAT7 IDAT6 IDAT5
MD58 MD59 MD60 MD56
SDCK2 MD61 MD62 MD63
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
SC1200/SC1201
Set-Top Box On a Chip
(Top View)
MD24 VIO
VSS DQM7
IDAT4 VSS
VIO IDAT3
IDAT1 IDAT2 IDAT0 IDRQ0
IIORY0 IIOW0# IAD0 IDACK0#
MD25 MD26 MD27 DQM3
MD52 MD29 MD30 MD31
VSS
VIO
VSS MD28
IAD1 VSS
VIO
S
VSS
MD50 MD49 MD54 MD53
MD21 DQM6 DQM2 MD55
IRQ14 ICS0# SOUT1 OVRCUR#
GP18 SIN1 X27I PLL6B
PWRE X27O PLL2B VIO PBTN# GPW0 VSS CK32 POR# MD3 MD5 WEA# VSS
VIO MA1 MD34 MD37 VIO
VSS MD41 MA9 MA8 DQM1 MD13 VSS MA11 CS1# MD18 MD48 MD20 MD51
PLL5B X32I X32O VPLL3 ONCT# GPW2 VIO GP11 MD0 VIO MD6 CASA# BA0 MA10 MD32 MD33 MD36 MD47 MD45 MD42 SDCK0 VIO MA6 MA3 VIO MD11 SDCKI MD19 VIO MD22 MD17
VIO
VSS
1
VSS AVSSP3 THRM#GPW1 PCNT1 VSS IRRX1 MD1 VSS MD7 RASA# VIO
BA1 MA2 VIO MD35 MD46 VIO MD43 DQM5 VSS MA5 MD15 VSS MD14 MD12 SDCKO MD16 VSS
VIO
VIO VBAT LED# VSB VSBL PCNT2 SDATI2 MD2 MD4 DQM0 CS0# VSS MA0 DQM4 VSS MD38 MD39 VSS MD44 MD40 CKEA MA7 MA4 MD8 MD10 MD9 MA12 MD23 VIO
VSS
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Note: Signal names have been abbreviated in this figure due to space constraints.
= GND Ball
= PWR Ball
= Strap Option Ball
S
= Multiplexed Ball
Figure 2-3. 481-TEPBGA Ball Assignment Diagram
www.national.com
38
Revision 6.0
Signal Definitions (Continued)
Table 2-4. 481-TEPBGA Ball Assignment - Sorted by Ball Number
1
1
Ball
No.
I/O
Buffer Power
Rail Configuration
Ball
No.
I/O
Buffer Power
Signal Name
(PU/PD) Type
Signal Name
(PU/PD) Type
Rail Configuration
6, 2
3
A1
A2
A3
V
V
GND
PWR
I/O
---
---
---
---
---
PD7
I/O
O
IN ,
V
IO
SS
A18
T
PMR[23] = 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
O
14/14
---
IO
AD30
IN
,
V
Cycle Multiplexed
PCI
IO
3
TFTD13
F_AD7
O
1/4
PMR[23] = 1 and
O
PCI
(PMR[27] = 0 and
FPCI_MON = 0)
D6
I/O
IN
O
,
PCI
PCI
3
O
O
14/14
---
PMR[23] = 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
A4
A5
PCICLK0
O
I
O
V
V
---
PCI
IO
IO
FPCI_MON
IN
Strap (See Table 2-
6 on page 54.)
STRP
A19
A20
V
GND
I/O
---
---
SS
(PD
)
100
6, 2
3
PD6
IN ,
V
V
V
T
IO
PMR[23] = 0 and
REQ1#
I
IN
---
PCI
O
(PMR[27] = 0 and
FPCI_MON = 0)
14/14
(PU
)
22.5
A6
A7
A8
PCIRST#
PCICLK
IOW#
O
O
V
V
V
---
---
PCI
IO
IO
IO
3
TFTD1
O
O
O
1/4
1/4
(PMR[23] = 1 and
PMR[15] = 0) and
(PMR[27] = 0 and
FPCI_MON = 0
I
IN
T
O
O
PMR[21] = 0 and
PMR[2] = 0
3/5
3
VOPD0
O
(PMR[23] = 1 and
DOCW#
GPIO15
O
O
PMR[21] = 0 and
PMR[2] = 1
3/5
PMR[15] = 1) and
(PMR[27] = 0 and
FPCI_MON = 0)
I/O
IN
O
,
PMR[21] = 1 and
PMR[2] = 1
TS
3/5
(PU
)
)
22.5
3
F_AD6
PD1
O
I/O
O
O
14/14
PMR[23] = 0 and
3
(PMR[27] = 1 or
FPCI_MON = 1)
A9
GPIO20
I/O
(PU
IN ,
T
V
V
V
IO
IO
IO
(PMR[23] = 0 and
PMR[7] = 0) or
O
22.5
3/5
3
6, 2
3
(PMR[23] = 1 and
PMR[15] = 1 and
PMR[7] = 0)
IN ,
T
A21
IO
PMR[23] = 0 and
O
(PMR[27] = 0 and
FPCI_MON = 0)
14/14
3
DOCCS#
O
O
3
3/5
(PMR[23] = 0 and
PMR[7] = 1) or
TFTD7
O
1/4
1/4
(PMR[23] = 1 and
(PU
)
22.5
PMR[15] = 0) and
(PMR[27] = 0 and
FPCI_MON = 0)
3
(PMR[23] = 1 and
PMR[15] = 1 and
PMR[7] = 1)
3
VOPD6
O
O
(PMR[23] = 1 and
3
TFTD0
O
O
1/4
PMR[23] = 1 and
PMR[15] = 0
PMR[15] = 1) and
(PMR[27] = 0 and
FPCI_MON = 0)
(PU
)
)
22.5
3
A10
GPIO17
I/O
(PU
IN
O
,
TS
3/5
(PMR[23] = 0 and
PMR[5] = 0) or
3
F_AD1
O
O
O
O
O
O
22.5
14/14
PMR[23] = 0 and
3
(PMR[27] = 1 or
FPCI_MON = 1)
(PMR[23] = 1 and
PMR[15] = 1 and
PMR[5] = 0)
6, 2
3
STB#/WRITE#
TFTD17
A22
14/14
1/4
IO
PMR[23] = 0 and
3
IOCS0#
O
O
(PMR[27] = 0 and
FPCI_MON = 0)
3/5
(PMR[23] = 0 and
PMR[5] = 1) or
(PU
)
22.5
3
3
(PMR[23] = 1 and
PMR[15] = 1 and
PMR[5] = 1)
O
PMR[23] = 1 and
(PMR[27] = 0 and
FPCI_MON = 0)
3
TFTDCK
HSYNC
O
O
O
3
1/4
1/4
PMR[23] = 1 and
PMR[15] = 0
F_FRAME#
O
14/14
PMR[23] = 0 and
(PU
)
22.5
(PMR[27] = 1 or
FPCI_MON = 1)
A11
A12
A13
A14
O
---
A23
A24
CVBS
Y
O
O
O
WIRE AV
WIRE AV
See F4BAR0+
Memory Offset
C08h[4:3] bit
description on
page 363.
CCTV
CCTV
AV
PWR
GND
O
---
---
---
AV
---
---
---
CCCRT
V
---
SS
TVG
GREEN
WIRE
C-
CCRT
SVY
TVR
Cb
O
O
O
O
See F4BAR0+
Memory Offset
C08h[4:3] bit
description on
page 363.
A15
BLUE
O
WIRE
AV
---
C-
CCRT
A16
A17
V
V
GND
PWR
---
---
---
---
---
SS
CVBS
---
PLL2
Revision 6.0
39
www.national.com
Signal Definitions (Continued)
Table 2-4. 481-TEPBGA Ball Assignment - Sorted by Ball Number (Continued)
1
1
Ball
No.
I/O
Buffer Power
Rail Configuration
Ball
No.
I/O
Buffer Power
Signal Name
TVRSET
(PU/PD) Type
Signal Name
(PU/PD) Type
Rail Configuration
6, 2
3
A25
I
WIRE AV
---
---
ACK#
I
IN
V
CCTV
B18
T
IO
PMR[23] = 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
6
DPOS_PORT3
I/O
IN
O
,
AV
C-
CUSB
A26
A27
A28
A29
USB
USB
3
TFTDE
O
O
O
O
1/4
1/4
1/4
(PMR[23] = 1 and
6
6
6
DNEG_PORT3
DPOS_PORT1
DNEG_PORT1
I/O
I/O
I/O
IN
O
,
AV
---
---
---
USB
USB
C-
CUSB
PMR[15] = 0) and
(PMR[27] = 0 and
FPCI_MON = 0)
IN
O
,
AV
USB
USB
C-
CUSB
3
VOPCK
FPCICLK
O
O
(PMR[23] = 1 and
PMR[15] = 1) and
(PMR[27] = 0 and
FPCI_MON = 0)
IN
O
,
AV
C-
CUSB
USB
USB
A30
A31
B1
V
PWR
GND
GND
PWR
I/O
---
---
---
---
---
---
3
IO
PMR[23] = 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
V
V
V
---
---
SS
SS
IO
---
---
B19
B20
V
PWR
O
---
---
V
---
IO
B2
---
---
6,2
3
SLIN#/ASTRB#
O
14/14
IO
PMR[23] = 0 and
B3
AD29
IN
O
,
V
V
Cycle Multiplexed
PCI
IO
(PMR[27] = 0 and
FPCI_MON = 0)
PCI
3
TFTD16
O
O
O
O
O
1/4
D5
I/O
I/O
I/O
I
IN
O
,
PMR[23] = 1 and
PCI
PCI
(PMR[27] = 0 and
FPCI_MON = 0)
B4
AD28
D4
IN
O
,
Cycle Multiplexed
PCI
PCI
IO
3
F_IRDY#
INIT#
O
O
14/14
14/14
PMR[23] = 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
IN
O
,
PCI
PCI
6,2
3
V
B21
IO
PMR[23] = 0 and
B5
B6
REQ0#
AD23
INPCI
V
V
---
(PMR[27] = 0 and
FPCI_MON = 0)
IO
IO
(PU
)
22.5
3
I/O
IN
O
,
Cycle Multiplexed
TFTD5
O
PCI
1/4
1/4
(PMR[23] = 1 and
PMR[15] = 0) and
(PMR[27] = 0 and
FPCI_MON = 0)
PCI
A23
O
GND
O
O
PCI
B7
B8
V
---
---
---
---
3
SS
VOPD4
SMI_O
O
O
O
(PMR[23] = 1 and
PMR[15] = 1) and
(PMR[27] = 0 and
FPCI_MON = 0)
RD#
O
V
3/5
IO
CLKSEL0
I
IN
Strap (See Table 2-
6 on page 54.)
STRP
(PD
)
100
3
O
14/14
---
PMR[23] = 0 and
B9
WR#
O
O
3/5
V
IO
IO
(PMR[27] = 1 or
FPCI_MON = 1)
B10
B11
B12
V
GND
O
---
---
---
---
---
SS
B22
B23
B24
B25
B26
V
GND
O
---
---
---
---
---
---
---
SS
VSYNC
RED
O
V
1/4
TVIOM
AV
WIRE AV
CCTV
O
WIRE
AV
C-
CCRT
GND
GND
I
---
---
SSTV
B13
B14
B15
V
PWR
GND
I
---
---
---
---
---
---
IO
V
---
---
SS
AV
---
SSCRT
TVCOMP
WIRE AV
CCTV
SETRES
WIRE
AV
C-
6
6
DPOS_PORT2
I/O
IN
O
,
AV
CUSB
B27
USB
USB
C-
CCRT
B16
B17
V
PWR
I
---
---
---
IO
DNEG_PORT2
GPIO10
I/O
IN
O
,
AV
---
B28
B29
USB
USB
C-
CUSB
6, 2
3
BUSY/WAIT#
IN
T
V
IO
PMR[23] = 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
I/O
IN
,
V
PMR[18] = 0 and
PMR[8] = 0
TS
IO
(PU
)
O
22.5
8/8
3
TFTD3
O
O
O
O
O
O
1/4
1/4
1/4
(PMR[23] = 1 and
DSR2#
I
IN
PMR[18] = 1 and
PMR[8] = 0
TS
PMR[15] = 0) and
(PMR[27] = 0 and
FPCI_MON = 0)
(PU
)
)
)
22.5
IDE_IORDY1
SDTEST1
I
IN
PMR[18] = 0 and
PMR[8] = 1
TS1
(PU
3
22.5
VOPD2
(PMR[23] = 1 and
PMR[15] = 1) and
(PMR[27] = 0 and
FPCI_MON = 0)
O
O
PMR[18] = 1 and
PMR[8] = 1
2/5
(PU
22.5
B30
B31
V
V
GND
PWR
---
---
---
---
---
---
SS
IO
3
F_C/BE1#
PMR[23] = 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
www.national.com
40
Revision 6.0
Signal Definitions (Continued)
Table 2-4. 481-TEPBGA Ball Assignment - Sorted by Ball Number (Continued)
1
1
Ball
No.
I/O
Buffer Power
Rail Configuration
Ball
No.
I/O
Buffer Power
Signal Name
(PU/PD) Type
Signal Name
(PU/PD) Type
Rail Configuration
6,2
6,2
6,2
3
C1
AD26
I/O
I/O
I/O
I/O
IN
O
,
V
Cycle Multiplexed
PD5
I/O
O
IN ,
V
V
V
PCI
PCI
IO
C19
C20
C21
T
IO
IO
IO
PMR[23] = 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
O
14/14
D2
IN
O
,
PCI
PCI
3
TFTD11
F_AD5
PD3
O
1/4
PMR[23] = 1 and
(PMR[27] = 0 and
FPCI_MON = 0)
C2
AD24
D0
IN
O
,
V
Cycle Multiplexed
PCI
PCI
IO
3
O
O
14/14
PMR[23] = 0 and
IN
O
,
PCI
PCI
(PMR[27] = 1 or
FPCI_MON = 1)
3
I/O
O
IN ,
T
C3
C4
V
PWR
I/O
---
---
---
PMR[23] = 0 and
IO
O
(PMR[27] = 0 and
FPCI_MON = 0)
14/14
AD25
IN
,
V
Cycle Multiplexed
PCI
IO
O
PCI
3
TFTD9
F_AD3
PD0
O
1/4
PMR[23] = 1 and
D1
I/O
IN
O
,
PCI
PCI
(PMR[27] = 0 and
FPCI_MON = 0)
3
C5
C6
GNT0#
DID0
O
I
O
V
V
---
O
O
14/14
PCI
IO
IO
PMR[23] = 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
IN
Strap (See Table 2-
6 on page 54.)
STRP
(PD
)
)
100
3
I/O
O
IN ,
T
PMR[23] = 0 and
GNT1#
DID1
O
O
---
PCI
O
(PMR[27] = 0 and
FPCI_MON = 0)
14/14
I
IN
Strap (See Table 2-
6 on page 54.)
STRP
(PD
100
3
TFTD6
O
1/4
1/4
(PMR[23] = 1 and
C7
C8
V
PWR
---
---
---
---
PMR[15] = 0) and
(PMR[27] = 0 and
FPCI_MON = 0)
IO
ROMCS#
BOOT16
O
I
O
V
V
3/5
IO
IO
IN
Strap (See Table 2-
6 on page 54.)
STRP
3
VOPD5
F_AD0
O
O
(PMR[23] = 1 and
(PD
)
100
PMR[15] = 1) and
(PMR[27] = 0 and
FPCI_MON = 0)
C9
GPIO19
I/O
IN
O
,
V
PMR[9] = 0 and
PMR[4] = 0
TS
IO
(PU
)
22.5
3/5
3
O
O
14/14
---
PMR[23] = 0 and
INTC#
I
IN
PMR[9] = 0 and
PMR[4] = 1
TS
(PMR[27] = 1 or
FPCI_MON = 1)
(PU
)
)
22.5
IOCHRDY
I
IN
PMR[9] = 1 and
PMR[4] = 1
TS1
C22
C23
V
PWR
---
---
IO
(PU
22.5
SVC
Cr
O
O
WIRE AV
See F4BAR0+
Memory Offset
C08h[4:3] bit
description on
page 363.
CCTV
C10
C11
V
PWR
O
---
---
---
IO
IRTX
O
O
V
PMR[6] = 0
8/8
8/8
IO
Cb
O
SOUT3
O
PMR[6] = 1
TVB
TVR
TVREF
O
C12
C13
C14
C15
C16
V
GND
PWR
GND
GND
GND
I
---
---
---
---
---
---
---
SSCRT
O
AV
AV
AV
AV
---
---
---
---
IN
---
---
---
---
CCCRT
SSCRT
SSCRT
SSPLL2
C24
C25
C26
I/O
WIRE AV
---
---
---
---
CCTV
V
PWR
---
IO
INTB#
I
IN
V
IO
PCI
(PU
)
)
22.5
C27
C28
AV
GND
---
---
---
6,2
3
SLCT
V
IO
SSUSB
C17
T
PMR[23] = 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
GPIO9
I/O
IN
O
,
V
PMR[18] = 0 and
PMR[8] = 0
TS
1/4
IO
(PU
22.5
3
TFTD15
F_C/BE3#
PD4
O
O
O
O
1/4
1/4
PMR[23] = 1 and
DCD2#
I
IN
PMR[18] = 1 and
PMR[8] = 0
TS
1/4
2/5
(PMR[27] = 0 and
FPCI_MON = 0)
(PU
)
)
)
22.5
IDE_IOW1#
SDTEST2
O
O
O
PMR[18] = 0 and
PMR[8] = 1
3
PMR[23] = 0 and
(PU
22.5
(PMR[27] = 1 or
FPCI_MON = 1)
O
PMR[18] = 1 and
PMR[8] = 1
(PU
22.5
3
C18
I/O
O
IN ,
V
IO
T
PMR[23] = 0 and
C29
C30
V
PWR
---
---
---
O
(PMR[27] = 0 and
FPCI_MON = 0)
IO
14/14
GPIO7
I/O
IN
O
,
V
PMR[17] = 0 and
PMR[8] = 0
TS
1/4
IO
3
TFTD10
F_AD4
O
1/4
(PU
)
PMR[23] = 1 and
22.5
(PMR[27] = 0 and
FPCI_MON = 0)
RTS2#
O
O
O
O
PMR[17] = 1 and
PMR[8] = 0
1/4
1/4
2/5
(PU
)
)
)
22.5
22.5
22.5
3
O
O
14/14
PMR[23] = 0 and
IDE_DACK1#
SDTEST0
O
(PU
PMR[17] = 0 and
PMR[8] = 1
(PMR[27] = 1 or
FPCI_MON = 1)
O
(PU
PMR[17] = 1 and
PMR[8] = 1
Revision 6.0
41
www.national.com
Signal Definitions (Continued)
Table 2-4. 481-TEPBGA Ball Assignment - Sorted by Ball Number (Continued)
1
1
Ball
No.
I/O
Buffer Power
Rail Configuration
Ball
No.
I/O
Buffer Power
Rail Configuration
Signal Name
(PU/PD) Type
Signal Name
(PU/PD) Type
C31
GPIO8
I/O
(PU
IN
O
,
V
PMR[17] = 0 and
PMR[8] = 0
D16
VREF
I/O
I
WIRE
IN
AV ---
TS
8/8
IO
C-
CCRT
)
22.5
6, 2
3
PE
V
IO
D17
T
PMR[23] = 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
(PU/PD under soft-
ware control.)
CTS2#
I
IN
PMR[17] = 1 and
PMR[8] = 0
TS
(PU
22.5
(PU
)
)
)
22.5
PD
)
22.5
IDE_DREQ1
SDTEST4
AD21
I
IN
PMR[17] = 0 and
PMR[8] = 1
TS1
(PU
22.5
3
O
O
PMR[17] = 1 and
PMR[8] = 1
TFTD14
O
O
O
O
2/5
1/4
1/4
PMR[23] = 1 and
(PMR[27] = 0 and
FPCI_MON = 0)
(PU
22.5
D1
D2
D3
D4
I/O
IN
O
,
V
V
V
V
Cycle Multiplexed
Cycle Multiplexed
Cycle Multiplexed
Cycle Multiplexed
PCI
IO
IO
IO
IO
3
F_C/BE2#
PCI
PMR[23] = 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
A21
O
O
PCI
AD22
I/O
IN
O
,
PCI
PCI
D18
D19
V
V
PWR
GND
I/O
---
---
IN ,
---
---
---
---
IO
SS
A22
O
O
PCI
6, 2
3
PD2
V
D20
D21
D22
T
IO
IO
IO
PMR[23] = 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
AD20
I/O
IN
O
,
PCI
PCI
O
14/14
A20
O
O
3
TFTD8
O
O
O
PCI
1/4
1/4
(PMR[23] = 1 and
PMR[15] = 0) and
(PMR[27] = 0 and
FPCI_MON = 0)
AD27
I/O
IN
O
,
PCI
PCI
D3
I/O
I/O
I/O
IN
O
,
PCI
PCI
3
VOPD7
O
(PMR[23] = 1 and
PMR[15] = 1) and
(PMR[27] = 0 and
FPCI_MON = 0)
D5
D6
AD31
D7
IN
O
,
V
V
Cycle Multiplexed
PCI
PCI
IO
IO
3
F_AD2
ERR#
O
I
O
14/14
PMR[23] = 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
IN
O
,
PCI
PCI
PCICLK1
O
I
O
---
PCI
6, 2
3
IN ,
T
V
PMR[23] = 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
O
LPC_ROM
IN
Strap (See Table 2-
6 on page 54.)
1/4
STRP
(PD
)
100
3
TFTD4
O
O
D7
D8
V
GND
---
---
---
---
1/4
(PMR[23] = 1 and
SS
PMR[15] = 0) and
(PMR[27] = 0 and
FPCI_MON = 0)
FRAME#
I/O
IN
,
V
PCI
IO
(PU
)
O
22.5
PCI
3
D9
IOR#
O
O
V
PMR[21] = 0 and
PMR[2] = 0
VOPD3
O
O
3/5
3/5
IO
1/4
(PMR[23] = 1 and
PMR[15] = 1) and
(PMR[27] = 0 and
FPCI_MON = 0)
DOCR#
GPIO14
O
O
PMR[21] = 0 and
PMR[2] = 1
3
F_C/BE0#
AFD#/DSTRB#
TFTD2
O
O
O
O
I/O
IN
O
,
PMR[21] = 1 and
PMR[2] = 1
1/4
PMR[23] = 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
TS
3/5
(PU
)
)
22.5
3
D10
GPIO1
I/O
(PU
IN ,
T
V
V
V
IO
IO
IO
(PMR[23] = 0 and
6, 2
3
O
V
14/14
PMR[23] = 0 and
O
22.5
PMR[13] = 0) or
3/5
(PMR[27] = 0 and
FPCI_MON = 0)
3
(PMR[23] = 1 and
PMR[15] = 1 and
PMR[13] = 0)
3
O
1/4
1/4
PMR[23] = 1 and
PMR[15] = 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
3
IOCS1#
O
O
3/5
(PMR[23] = 0 and
(PU
)
22.5
PMR[13] = 1) or
3
(PMR[23] = 1 and
3
VOPD1
INTR_O
O
O
PMR[15] = 1 and
PMR[13] = 1)
(PMR[23] = 1 and
PMR[15] = 1) and
(PMR[27] = 0 and
FPCI_MON = 0)
3
TFTD12
O
O
O
1/4
3/5
PMR[23] = 1 and
(PU
)
)
22.5
PMR[15] = 0
3
O
O
14/14
---
PMR[23] = 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
D11
TRDE#
GPIO0
O
V
V
PMR[12] = 0
IO
IO
I/O
IN
O
,
PMR[12] = 1
TS
3/5
(PU
22.5
D23
D24
AV
PWR
---
---
CCTV
D12
D13
D14
D15
V
PWR
GND
PWR
PWR
---
---
---
---
---
---
CVBS
Cr
O
O
O
WIRE AV
See F4BAR0+
Memory Offset
C08h[4:3] bit
description on
page 363.
CCCRT
CCTV
V
V
---
---
---
---
---
---
SS
IO
TVB
AV
CCCRT
www.national.com
42
Revision 6.0
Signal Definitions (Continued)
Table 2-4. 481-TEPBGA Ball Assignment - Sorted by Ball Number (Continued)
1
1
Ball
No.
I/O
Buffer Power
Rail Configuration
Ball
No.
I/O
Buffer Power
Rail Configuration
Signal Name
(PU/PD) Type
Signal Name
(PU/PD) Type
D25
D26
V
GND
I
---
IN
---
---
---
F29
TDI
I
IN
V
---
SS
PCI
IO
(PU
)
)
22.5
INTA#
V
IO
PCI
(PU
)
)
F30
GTEST
I
IN
V
---
22.5
T
IO
(PD
22.5
D27
D28
AV
PWR
---
IN
---
---
CCUSB
F31
G1
VPCKIN
STOP#
I
IN
V
V
---
T
IO
IO
GPIO6
I/O
,
V
PMR[18] = 0 and
PMR[8] = 0
TS
IO
(PU
I/O
IN
O
,
Cycle Multiplexed
O
22.5
PCI
1/4
(PU
)
)
22.5
PCI
DTR2#/BOUT2
IDE_IOR1#
SDTEST5
O
O
PMR[18] = 1 and
PMR[8] = 0
1/4
(PU
)
)
)
D15
I/O
IN
O
,
22.5
22.5
22.5
PCI
PCI
(PU
22.5
O
(PU
O
O
O
PMR[18] = 0 and
PMR[8] = 1
1/4
2/5
8/8
G2
V
GND
PWR
GND
GND
PWR
GND
I
---
---
---
---
---
---
IN
---
---
---
---
---
---
---
---
---
SS
O
(PU
PMR[18] = 1 and
PMR[8] = 1
G3
V
---
---
---
---
---
IO
G4
V
V
V
V
SS
SS
IO
D29
SOUT2
O
V
---
IO
G28
G29
G30
G31
H1
CLKSEL2
I
IN
Strap (See Table 2-
6 on page 54.)
STRP
(PD
)
100
D30
D31
TDP
TDN
I/O
Diode
WIRE
---
---
---
SS
VPD7
V
I/O
I/O
V
V
T
IO
IO
IO
IO
E1
E2
E3
E4
AD16
IN
O
,
Cycle Multiplexed
Cycle Multiplexed
Cycle Multiplexed
Cycle Multiplexed
SERR#
I/O
IN
,
V
V
V
V
PCI
PCI
(PU
)
)
)
)
)
OD
22.5
PCI
PCI
A16
O
O
H2
H3
H4
PERR#
LOCK#
C/BE3#
D11
I/O
IN
O
,
---
PCI
PCI
PCI
IO
IO
IO
(PU
22.5
22.5
22.5
AD19
I/O
IN
O
,
V
V
V
PCI
PCI
IO
IO
IO
I/O
(PU
IN
O
,
---
PCI
PCI
A19
O
O
PCI
I/O
(PU
IN
O
,
Cycle Multiplexed
PCI
PCI
AD18
I/O
IN
O
,
PCI
PCI
I/O
IN
O
,
PCI
PCI
A18
O
O
PCI
(PU
22.5
DEVSEL#
I/O
IN
O
,
PCI
PCI
H28
H29
H30
H31
J1
VPD6
VPD5
VPD4
VPD3
AD13
I
I
I
I
IN
V
V
V
V
V
---
T
T
T
T
IO
IO
IO
IO
IO
(PU
)
)
22.5
IN
---
BHE#
O
I
O
PCI
IN
IN
---
E28
E29
SIN2
IN
V
V
PMR[28] = 0
PMR[28] = 1
---
TS
2/5
PCI
IO
IO
---
SDTEST3
TRST#
O
I
O
I/O
IN
O
,
Cycle Multiplexed
PCI
IN
PCI
(PU
22.5
A13
O
O
PCI
E30
E31
TDO
TCK
O
I
O
V
V
---
---
PCI
IO
IO
J2
C/BE1#
I/O
IN
O
,
V
Cycle Multiplexed
PCI
PCI
IO
IN
PCI
(PU
)
)
22.5
(PU
)
)
22.5
D9
I/O
(PU
IN
O
,
F1
F2
F3
TRDY#
D13
I/O
(PU
IN
O
,
V
V
V
Cycle Multiplexed
Cycle Multiplexed
Cycle Multiplexed
PCI
PCI
PCI
PCI
IO
IO
IO
22.5
22.5
J3
J4
AD15
I/O
IN
O
,
V
V
Cycle Multiplexed
Cycle Multiplexed
I/O
(PU
IN
O
,
PCI
PCI
IO
IO
PCI
PCI
)
)
)
)
)
22.5
A15
PAR
O
O
IRDY#
D14
I/O
(PU
IN
O
,
PCI
PCI
PCI
22.5
I/O
IN
O
,
PCI
PCI
(PU
)
)
22.5
I/O
(PU
IN
O
,
PCI
PCI
22.5
D12
I/O
(PU
IN
O
,
PCI
PCI
22.5
C/BE2#
D10
I/O
(PU
IN
O
,
PCI
PCI
22.5
J28
J29
J30
J31
VPD2
VPD1
VPD0
GPIO39
I
I
IN
V
V
V
V
---
---
---
T
T
T
IO
IO
IO
IO
I/O
(PU
IN
O
,
PCI
PCI
IN
IN
22.5
I
F4
AD17
I/O
IN
O
,
V
V
Cycle Multiplexed
PCI
PCI
IO
IO
4
I/O
IN
O
,
PCI
PCI
PMR[14] = 0 and
(PU
)
4
22.5
PMR[22] = 0
A17
O
I
O
PCI
4
SERIRQ
I/O
IN
O
,
PCI
PCI
PMR[14] = 1 and
F28
TMS
IN
---
PCI
4
PMR[22] = 1
(PU
)
22.5
Revision 6.0
43
www.national.com
Signal Definitions (Continued)
Table 2-4. 481-TEPBGA Ball Assignment - Sorted by Ball Number (Continued)
1
1
Ball
No.
I/O
Buffer Power
Rail Configuration
Ball
No.
I/O
Buffer Power
Signal Name
(PU/PD) Type
Signal Name
(PU/PD) Type
Rail Configuration
4
K1
AD11
I/O
IN
O
,
V
Cycle Multiplexed
L31
GPIO33
I/O
(PU
IN
O
,
V
IO
PCI
IO
PCI
PCI
PMR[14] = 0 and
)
)
4
22.5
PCI
PMR[22] = 0
A11
O
O
4
LAD1
I/O
(PU
IN
O
,
PCI
PCI
PCI
PMR[14] = 1 and
4
22.5
PMR[22] = 1
K2
K3
K4
V
V
PWR
GND
I/O
---
---
---
---
---
IO
M1
M2
V
GND
I/O
---
IN
---
---
---
SS
SS
AD7
,
V
IO
Cycle Multiplexed
AD14
IN
,
V
Cycle Multiplexed
PCI
PCI
IO
O
O
PCI
PCI
A7
O
O
A14
O
O
PCI
PCI
M3
M4
V
PWR
I/O
---
IN
---
---
4
K28
GPIO38/IRRX2
I/O
IN
O
,
V
IO
PCI
PCI
IO
PMR[14] = 0 and
(PU
)
4
22.5
PMR[22] = 0. The
AD8
,
V
Cycle Multiplexed
PCI
IO
IRRX2 input is con-
nected to the input
path of GPIO38.
There is no logic
required to enable
IRRX2, just a sim-
ple connection.
Hence, when
O
PCI
A8
O
O
PCI
4
M28
M29
GPIO32
I/O
IN
O
,
V
PCI
PCI
IO
PMR[14] = 0 and
(PU
)
)
4
22.5
PMR[22] = 0
4
LAD0
I/O
IN
O
,
PCI
PCI
PMR[14] = 1 and
(PU
4
22.5
PMR[22] = 1
GPIO38 is the
selected function,
IRRX2 is also
GPIO13
AB2D
I/O
IN
O
,
V
V
PMR[19] = 0
PMR[19] = 1
AB
8/8
IO
IO
(PU
)
)
22.5
selected.
I/O
IN
OD
,
AB
4
LPCPD#
O
O
PCI
PMR[14] = 1 and
(PU
22.5
4
8
PMR[22] = 1
M30
M31
N1
V
V
PWR
GND
I/O
---
---
---
---
IO
K29
K30
K31
V
V
PWR
GND
I/O
---
---
---
---
---
---
IO
---
---
SS
SS
AD3
IN
O
,
V
Cycle Multiplexed
PCI
IO
IO
IO
4
GPIO37
IN
,
V
PCI
IO
PMR[14] = 0 and
PCI
(PU
)
4
O
22.5
PCI
PMR[22] = 0
A3
O
O
PCI
4
LFRAME#
O
O
PCI
PMR[14] = 1 and
N2
N3
AD6
I/O
IN
O
,
V
V
Cycle Multiplexed
Cycle Multiplexed
4
PCI
PCI
PMR[22] = 1
L1
C/BE0#
D8
I/O
(PU
IN
O
,
V
Cycle Multiplexed
PCI
PCI
IO
PCI
A6
O
)
)
O
22.5
AD5
I/O
IN
O
,
I/O
(PU
IN
O
,
PCI
PCI
PCI
PCI
22.5
A5
O
O
L2
AD9
I/O
IN
O
,
V
V
V
V
Cycle Multiplexed
Cycle Multiplexed
Cycle Multiplexed
PCI
PCI
PCI
IO
IO
IO
IO
N4
V
V
V
V
V
V
V
V
V
GND
PWR
PWR
GND
GND
GND
PWR
PWR
GND
I/O
---
---
---
---
---
---
---
---
---
---
---
SS
A9
O
O
PCI
N13
N14
N15
N16
N17
N18
N19
N28
N29
---
---
---
---
---
---
---
---
---
CORE
CORE
SS
L3
AD10
I/O
IN
O
,
PCI
PCI
---
---
A10
O
O
PCI
---
SS
L4
AD12
I/O
IN
O
,
PCI
PCI
---
SS
---
CORE
CORE
SS
A12
O
O
PCI
---
4
L28
GPIO36
I/O
IN
O
,
PCI
PCI
PMR[14] = 0 and
(PU
)
4
22.5
---
PMR[22] = 0
4
LDRQ#
GPIO35
LAD3
I
IN
GPIO12
IN
O
,
V
PMR[19] = 0
PCI
PMR[14] = 1 and
AB
IO
(PU
)
)
)
4
22.5
8/8
PMR[22] = 1
4
AB2C
I/O
IN
OD
,
PMR[19] = 1
L29
L30
I/O
IN
O
,
V
V
AB
PCI
PCI
IO
IO
PMR[14] = 0 and
(PU
(PU
)
)
)
)
4
22.5
22.5
22.5
8
PMR[22] = 0
3
N30
AB1D
I/O
(PU
IN
OD
,
V
4
AB
IO
PMR[23] = 0 or
I/O
(PU
IN
O
,
PCI
PCI
PMR[14] = 1 and
(PMR[23] = 1 and
PMR[15] = 1)
4
8
22.5
PMR[22] = 1
4
GPIO34
LAD2
I/O
(PU
IN
O
,
PCI
PCI
PMR[14] = 0 and
3
GPIO1
I/O
IN ,
O
T
PMR[23] = 1 and
4
22.5
PMR[22] = 0
(PU
)
22.5
PMR[15] = 0 and
PMR[13] = 0
3/5
4
I/O
(PU
IN
O
,
PCI
PCI
PMR[14] = 1 and
4
3
22.5
IOCS1#
O
O
PMR[22] = 1
3/5
PMR[23] = 1 and
PMR[15] = 0 and
PMR[13] = 1
www.national.com
44
Revision 6.0
Signal Definitions (Continued)
Table 2-4. 481-TEPBGA Ball Assignment - Sorted by Ball Number (Continued)
1
1
Ball
No.
I/O
Buffer Power
Ball
No.
I/O
Buffer Power
Rail Configuration
Signal Name
(PU/PD) Type
Rail Configuration
Signal Name
(PU/PD) Type
3
N31
AB1C
I/O IN
,
V
T4
V
V
V
V
V
V
V
V
V
V
V
V
PWR
GND
GND
GND
GND
GND
GND
GND
PWR
PWR
PWR
PWR
I/O
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
AB
IO
PMR[23] = 0 or
(PMR[23] = 1 and
PMR[15] = 1)
CORE
SS
(PU
)
OD
22.5
8
T13
T14
T15
T16
T17
T18
T19
T28
T29
T30
T31
U1
---
---
SS
3
GPIO20
DOCCS#
AD4
I/O
(PU
IN ,
T
O
PMR[23] = 1 and
)
22.5
PMR[15] = 0 and
PMR[7] = 0
---
3/5
SS
---
SS
3
O
O3/5
PMR[23] = 1 and
---
SS
PMR[15] = 0 and
PMR[7] = 1
---
SS
P1
I/O
IN
O
,
V
Cycle Multiplexed
PCI
IO
---
SS
PCI
---
CORE
CORE
CORE
CORE
A4
O
O
O
PCI
---
P2
P3
IDE_CS1#
TFTDE
AD1
O
O
V
V
PMR[24] = 0
1/4
1/4
IO
IO
---
O
PMR[24] = 1
---
I/O
IN
O
,
Cycle Multiplexed
PCI
AD0
IN
,
V
Cycle Multiplexed
PCI
IO
PCI
O
PCI
A1
O
O
PCI
A0
O
O
O
PCI
P4
V
V
V
V
V
V
V
V
V
PWR
PWR
PWR
GND
GND
GND
PWR
PWR
PWR
O
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
CORE
CORE
CORE
SS
U2
U3
IDE_ADDR2
TFTD4
AD2
O
O
V
V
PMR[24] = 0
1/4
1/4
IO
IO
P13
P14
P15
P16
P17
P18
P19
P28
P29
---
---
---
---
---
---
---
---
O
PMR[24] = 1
I/O
IN
O
,
Cycle Multiplexed
PCI
PCI
SS
A2
O
PWR
GND
GND
GND
GND
GND
GND
GND
PWR
O
O
PCI
SS
U4
V
V
V
V
V
V
V
V
V
---
---
---
---
---
---
---
---
---
---
---
CORE
SS
CORE
CORE
CORE
U13
U14
U15
U16
U17
U18
U19
U28
U29
---
---
---
---
---
---
---
---
---
---
SS
---
SS
SDATA_OUT
TFT_PRSNT
O
V
AC97
STRP
IO
IO
---
SS
I
IN
V
Strap (See Table 2-
6 on page 54.)
---
SS
(PD
)
100
---
SS
P30
SYNC
O
O
V
---
AC97
IO
---
SS
CLKSEL3
I
IN
Strap (See Table 2-
6 on page 54.)
STRP
(PD
)
---
100
CORE
P31
R1
AC97_CLK
O
O
V
PMR[25] = 1
AC97_RST#
F_STOP#
BIT_CLK
O
V
FPCI_MON = 0
FPCI_MON = 1
FPCI_MON = 0
FPCI_MON = 1
FPCI_MON = 0
FPCI_MON = 1
PMR[24] = 0
2/5
IO
2/5
2/5
IO
IO
IO
IO
V
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PWR
PWR
PWR
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
O
O
O
O
SS
R2
V
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
U30
U31
V1
I
IN
V
V
V
SS
T
R3
V
F_TRDY#
SDATA_IN
F_GNT0#
IDE_DATA15
O
SS
1/4
R4
V
I
IN
SS
T
R13
R14
R15
R16
R17
R18
R19
R28
R29
R30
R31
T1
V
O
SS
2/5
V
I/O
IN
,
TS1
SS
TS
1/4
V
V
V
V
V
V
V
V
V
V
V
V
SS
TFTD7
O
O
PMR[24] = 1
PMR[24] = 0
1/4
SS
V2
V3
IDE_DATA14
I/O
IN
,
V
V
TS1
IO
IO
SS
TS
1/4
SS
TFTD17
O
O
PMR[24] = 1
PMR[24] = 0
1/4
SS
IDE_DATA13
I/O
IN
,
TS1
SS
TS
1/4
SS
TFTD15
O
O
PMR[24] = 1
1/4
SS
V4
V
V
V
V
V
GND
PWR
PWR
GND
GND
---
---
---
---
---
---
---
SS
SS
V13
V14
V15
V16
---
---
---
---
---
---
---
---
CORE
CORE
SS
CORE
CORE
CORE
T2
T3
SS
Revision 6.0
45
www.national.com
Signal Definitions (Continued)
Table 2-4. 481-TEPBGA Ball Assignment - Sorted by Ball Number (Continued)
1
1
Ball
No.
I/O
Buffer Power
Rail Configuration
Ball
No.
I/O
Buffer Power
Rail Configuration
Signal Name
(PU/PD) Type
Signal Name
(PU/PD) Type
6
V17
V18
V19
V28
V29
V30
V
V
V
V
GND
PWR
PWR
GND
O
---
---
---
---
---
---
---
---
---
MD58
I/O
I/O
I/O
I/O
IN ,
V
V
V
V
V
---
---
---
---
SS
Y28
Y29
Y30
Y31
T
IO
IO
IO
IO
IO
TS
2/5
---
CORE
CORE
SS
6
6
6
MD59
MD60
MD56
IN ,
T
---
TS
2/5
---
IN ,
T
SDCLK3
GXCLK
O
V
---
TS
2/5
2/5
IO
IO
2/5
O
O
V
(PMR[29] = 0 and
IN ,
T
3
PMR[23] = 0) or
TS
2/5
3
(PMR[23] = 1 and
PMR[15] = 1)
AA1
AA2
IDE_RST#
TFTDCK
O
O
O
O
PMR[24] = 0
PMR[24] = 1
PMR[24] = 0
1/4
1/4
3
FP_VDD_ON
TEST3
O
O
O
O
1/4
2/5
PMR[23] = 1 and
PMR[15] = 0
IDE_DATA7
I/O
IN
,
V
V
V
TS1
IO
IO
IO
TS
PMR[29] = 1 and
1/4
3
PMR[23] = 0
INTD#
I
IN
PMR[24] = 1
PMR[24] = 0
TS
V31
GPIO16
I/O
IN ,
T
V
PMR[0] = 0 and
FPCI_MON = 0
IO
AA3
AA4
IDE_DATA6
I/O
IN
,
TS1
(PU
)
O
22.5
2/5
TS
1/4
PC_BEEP
O
O
PMR[0] = 1 = 0 and
FPCI_MON = 0
2/5
IRQ9
I
IN
PMR[24] = 1
PMR[24] = 0
TS1
IDE_DATA5
I/O
IN
,
TS1
F_DEVSEL#
O
O
FPCI_MON = 1
2/5
TS
1/4
1/4
2/5
W1
W2
W3
V
V
PWR
GND
I/O
---
---
IN
---
---
---
IO
CLK27M
SDCLK2
MD61
O
O
O
O
PMR[24] = 1
---
SS
AA28
AA29
V
V
---
---
IO
IO
IDE_DATA12
,
V
PMR[24] = 0
TS1
IO
6
6
6
I/O
IN ,
T
TS
1/4
TS
2/5
TFTD13
O
O
PMR[24] = 1
PMR[24] = 0
1/4
MD62
I/O
I/O
I/O
IN ,
V
V
V
---
AA30
T
IO
IO
IO
W4
IDE_DATA11
I/O
IN
,
V
TS
TS1
IO
2/5
TS
1/4
MD63
IN ,
---
AA31
AB1
T
GPIO41
I/O
IN
,
PMR[24] = 1
TS
TS1
2/5
O
1/4
IDE_DATA4
IN
,
PMR[24] = 0
TS1
W13
W14
W15
W16
W17
W18
W19
V
PWR
PWR
GND
GND
GND
PWR
PWR
I/O
---
---
---
---
---
---
---
---
---
---
TS
CORE
1/4
V
---
---
---
---
---
---
---
---
---
---
---
---
FP_VDD_ON
O
O
PMR[24] = 1
CORE
1/4
V
AB2
AB3
AB4
V
GND
PWR
I/O
---
---
IN
---
---
---
SS
SS
V
V
---
SS
IO
V
IDE_DATA3
,
V
PMR[24] = 0
SS
TS1
IO
TS
1/4
V
V
CORE
CORE
TFTD12
MD24
O
O
PMR[24] = 1
---
1/4
6
I/O
IN ,
TS
V
6
AB28
T
IO
MD57
IN ,
V
W28
T
IO
2/5
TS
2/5
AB29
AB30
AB31
AC1
V
V
PWR
GND
O
---
---
---
---
---
IO
W29
W30
W31
SDCLK1
O
O
V
---
2/5
IO
---
SS
V
V
GND
PWR
I/O
---
---
IN
---
---
---
SS
IO
DQM7
O
V
---
2/5
IO
IO
---
IDE_DATA1
I/O
IN
,
TS1
V
V
V
PMR[24] = 0
5
IDE_DATA10
,
V
PMR[24] = 0
Y1
TS1
IO
TS
1/4
TS
1/4
TFTD16
O
O
PMR[24] = 1
PMR[24] = 0
1/4
DDC_SCL
O
OD
PMR[24] = 1
PMR[24] = 0
4
AC2
AC3
IDE_DATA2
I/O
IN
,
TS1
5
IO
IO
IDE_DATA9
I/O
IN
,
V
V
V
Y2
TS1
IO
TS
1/4
TS
1/4
TFTD14
O
O
PMR[24] = 1
PMR[24] = 0
1/4
DDC_SDA
IDE_DATA8
GPIO40
I/O
I/O
I/O
IN ,
OD
PMR[24] = 1
PMR[24] = 0
PMR[24] = 1
T
IDE_DATA0
I/O
IN
,
TS1
4
TS
1/4
Y3
Y4
IN
,
TS1
IO
IO
TS
TFTD6
O
I
O
PMR[24] = 1
PMR[24] = 0
PMR[24] = 1
---
1/4
1/4
IN
,
AC4
IDE_DREQ0
TFTD8
IN
V
V
TS1
TS1
IO
IO
O
O
O
1/4
1/4
1/4
O
O
1/4
IDE_IOR0#
TFTD10
O
O
PMR[24] = 0
PMR[24] = 1
6
MD25
I/O
IN ,
T
AC28
TS
2/5
www.national.com
46
Revision 6.0
Signal Definitions (Continued)
Table 2-4. 481-TEPBGA Ball Assignment - Sorted by Ball Number (Continued)
1
1
Ball
No.
I/O
Buffer Power
Rail Configuration
Ball
No.
I/O
Buffer Power
Rail Configuration
Signal Name
(PU/PD) Type
Signal Name
X27I
(PU/PD) Type
6
6
MD26
I/O
I/O
IN ,
V
---
AG3
AG4
I
WIRE
V
V
---
AC29
T
IO
IO
IO
TS
2/5
PLL6B
I/O
IN
,
PMR[29] = 0
TS
MD27
IN ,
V
---
TS
2/5
AC30
T
IO
TS
2/5
TEST1
MD21
O
O
PMR[29] = 1
---
2/5
AC31
AD1
DQM3
O
I
O
V
V
---
2/5
IO
IO
6
6
I/O
IN ,
TS
2/5
V
AG28
T
IO
IDE_IORDY0
TFTD11
IN
PMR[24] = 0
PMR[24] = 1
PMR[24] = 0
PMR[24] = 1
PMR[24] = 0
PMR[24] = 1
PMR[24] = 0
PMR[24] = 1
---
TS1
O
O
O
O
O
O
O
I/O
O
O
O
O
O
O
O
AG29
AG30
DQM6
DQM2
MD55
O
O
O
O
V
V
V
---
---
---
1/4
1/4
1/4
1/4
1/4
1/4
1/4
2/5
2/5
IO
IO
IO
AD2
AD3
AD4
IDE_IOW0#
TFTD9
V
V
V
IO
IO
IO
I/O
IN ,
T
TS
AG31
2/5
IDE_ADDR0
TFTD3
AH1
AH2
AH3
POWER_EN
X27O
O
O
O
V
V
V
---
1/4
IO
IO
IO
WIRE
---
IDE_DACK0#
TFTD0
PLL2B
I/O
IN ,
TS
PMR[29] = 0
T
2/5
6
MD52
IN ,
TS
V
V
V
V
V
AD28
AD29
AD30
T
IO
IO
IO
IO
IO
TEST0
O
PWR
I
O
PMR[29] = 1
2/5
2/5
AH4
AH5
V
---
---
---
---
IO
6
6
6
MD29
MD30
MD31
I/O
I/O
I/O
IN ,
TS
---
---
---
T
PWRBTN#
IN
V
2/5
BTN
SB
(PU
)
)
100
IN ,
TS
T
AH6
GPWIO0
I/O
(PU
IN
TS
,
V
---
TS
SB
2/5
100
2/14
IN ,
TS
AD31
AE1
T
AH7
AH8
AH9
V
GND
O
---
---
---
---
---
---
SS
2/5
CLK32
POR#
MD3
O
V
SB
IDE_ADDR1
TFTD2
O
O
O
PMR[24] = 0
2/5
1/4
1/4
I
IN
V
V
O
PMR[24] = 1
TS
IO
IO
6
6
I/O
IN ,
T
TS
AE2
V
GND
PWR
GND
GND
PWR
GND
I/O
---
---
---
---
---
---
---
---
---
AH10
AH11
SS
2/5
AE3
V
V
V
V
V
---
---
---
---
---
---
---
---
---
---
IO
MD5
I/O
IN ,
TS
V
V
---
T
IO
IO
AE4
SS
SS
IO
2/5
AE28
AE29
AE30
AH12
AH13
AH14
AH15
WEA#
O
GND
PWR
O
O
---
---
---
---
---
2/5
V
V
---
---
---
---
SS
IO
SS
6
MD28
IN ,
TS
V
AE31
AF1
T
IO
MA1
O
V
2/5
IO
IO
2/5
6
6
MD34
I/O
IN ,
TS
V
AH16
T
IRQ14
I
IN
V
V
V
PMR[24] = 0
PMR[24] = 1
PMR[24] = 0
PMR[24] = 1
---
TS1
IO
2/5
TFTD1
O
O
O
O
I
O
O
O
O
1/4
1/4
1/4
8/8
MD37
I/O
IN ,
TS
2/5
V
---
AH17
T
IO
AF2
AF3
IDE_CS0#
TFTD5
IO
IO
AH18
AH19
V
V
PWR
GND
I/O
---
---
---
---
---
---
---
IO
SOUT1
CLKSEL1
SS
6
IN
Strap (See Table 2-
6 on page 54.)
MD41
IN ,
TS
V
STRP
AH20
T
IO
(PD
)
100
2/5
AF4
OVER_CUR#
MD50
I
IN
V
V
---
---
AH21
AH22
AH23
MA9
O
O
O
O
O
V
V
V
V
---
---
---
---
TS
IO
IO
2/5
2/5
2/5
IO
IO
IO
IO
6
6
6
6
I/O
I/O
I/O
I/O
I/O
IN ,
T
TS
MA8
AF28
AF29
AF30
2/5
DQM1
MD13
O
MD49
MD54
MD53
GPIO18
IN ,
TS
V
V
V
V
---
T
IO
IO
IO
IO
6
I/O
IN ,
T
TS
AH24
2/5
2/5
IN ,
TS
---
T
AH25
AH26
AH27
V
GND
O
---
---
---
---
---
---
SS
2/5
MA11
CS1#
MD18
O
V
V
V
2/5
2/5
IO
IO
IO
IN ,
TS
---
AF31
AG1
T
O
O
2/5
6
6
IN
O
,
PMR[16] = 0
I/O
IN ,
T
TS
TS
AH28
(PU
)
22.5
8/8
8/8
2/5
DTR1#/BOUT1
SIN1
O
O
PMR[16] =1
---
MD48
I/O
IN ,
TS
V
---
AH29
T
IO
(PU
)
22.5
2/5
AG2
I
IN
V
TS
IO
Revision 6.0
47
www.national.com
Signal Definitions (Continued)
Table 2-4. 481-TEPBGA Ball Assignment - Sorted by Ball Number (Continued)
1
1
Ball
No.
I/O
Buffer Power
Rail Configuration
Ball
No.
I/O
Buffer Power
Rail Configuration
Signal Name
(PU/PD) Type
Signal Name
(PU/PD) Type
6
6
6
MD20
I/O
I/O
I/O
IN ,
V
V
V
---
MD17
I/O
IN ,
TS
2/5
V
IO
---
AH30
T
IO
IO
IO
AJ31
T
TS
2/5
MD51
IN ,
---
AK1
AK2
AK3
AK4
AK5
V
V
PWR
GND
GND
I
---
---
---
---
---
---
---
---
---
AH31
AJ1
T
IO
TS
2/5
---
---
SS
PLL5B
IN ,
PMR[29] = 0
T
AV
SSPLL3
TS
2/5
THRM#
IN
V
TS
SB
SB
TEST2
X32I
O
I
O
PMR[29] = 1
2/5
GPWIO1
I/O
IN
,
V
Ts
AJ2
AJ3
AJ4
WIRE
WIRE
---
V
V
---
---
---
---
---
BAT
BAT
(PU
)
TS
100
2/14
X32O
O
6, 2
PWRCNT1
O
OD
V
---
AK6
AK7
14
SB
V
PWR
O
---
PLL3
V
GND
---
---
---
SS
6, 2
ONCTL#
GPWIO2
OD
V
AJ5
AJ6
14
SB
SB
AK8
IRRX1
SIN3
MD1
I
I
IN
V
PMR[6] = 0
PMR[6] =1
---
TS
TS
SB
I/O
IN
,
V
TS
IN
V
V
IO
IO
(PU
)
TS
100
PWR
I/O
2/14
6
I/O
IN ,
T
AK9
AJ7
AJ8
V
---
---
---
IO
TS
2/5
GPIO11
IN
O
,
V
V
PMR[18] = 0 and
PMR[8] = 0
TS
8/8
IO
AK10
AK11
V
GND
I/O
---
IN ,
---
---
---
SS
(PU
)
22.5
6
MD7
V
T
IO
RI2#
I
IN
PMR[18] = 1 and
PMR[8] = 0
TS
TS
2/5
(PU
)
)
22.5
AK12
AK13
AK14
AK15
AK16
RASA#
O
PWR
O
O
V
---
---
---
---
---
---
2/5
IO
IRQ15
MD0
I
IN
PMR[18] = 0 and
PMR[8] = 1
TS1
(PU
V
---
---
22.5
IO
6
I/O
IN ,
---
BA1
MA2
O
O
V
V
AJ9
T
IO
IO
2/5
2/5
IO
IO
TS
2/5
O
AJ10
AJ11
V
PWR
I/O
---
IN ,
---
---
---
IO
V
PWR
I/O
---
IO
6
MD6
V
T
6
6
MD35
IN ,
V
AK17
AK18
T
IO
TS
2/5
TS
2/5
AJ12
AJ13
AJ14
CASA#
BA0
O
O
O
O
O
V
V
V
V
---
---
---
---
2/5
2/5
2/5
IO
IO
IO
IO
MD46
I/O
IN ,
V
---
T
IO
TS
2/5
MA10
MD32
O
AK19
AK20
V
PWR
I/O
---
---
---
---
IO
6
6
6
6
6
6
I/O
IN ,
T
6
MD43
IN ,
T
V
AJ15
AJ16
AJ17
AJ18
AJ19
AJ20
IO
TS
TS
2/5
2/5
MD33
MD36
MD47
MD45
MD42
SDCLK0
I/O
I/O
I/O
I/O
I/O
IN ,
V
V
V
V
V
V
---
---
---
---
---
AK21
AK22
AK23
DQM5
O
GND
O
O
V
---
---
---
---
T
IO
IO
IO
IO
IO
IO
2/5
IO
TS
2/5
V
---
---
SS
IN ,
T
MA5
O
V
V
2/5
IO
IO
TS
2/5
6
MD15
I/O
IN ,
T
AK24
IN ,
T
TS
2/5
TS
2/5
AK25
AK26
V
GND
I/O
---
IN ,
---
---
---
SS
IN ,
T
6
6
TS
MD14
V
2/5
T
IO
TS
2/5
IN ,
T
TS
MD12
I/O
IN ,
V
---
2/5
AK27
T
IO
TS
2/5
AJ21
AJ22
AJ23
AJ24
AJ25
O
PWR
O
O
---
---
---
---
---
---
2/5
AK28
AK29
SDCLK_OUT
MD16
O
O
V
V
---
---
2/5
IO
IO
V
---
---
IO
6
I/O
IN ,
T
MA6
MA3
O
O
V
V
2/5
2/5
IO
IO
TS
2/5
O
AK30
AK31
AL1
AL2
AL3
AL4
AL5
AL6
V
V
V
V
V
GND
PWR
GND
PWR
PWR
O
---
---
---
---
---
---
---
---
---
---
---
---
---
---
SS
IO
V
PWR
I/O
---
---
IO
---
---
---
---
6
6
6
MD11
IN ,
V
AJ26
T
IO
SS
IO
TS
2/5
AJ27
AJ28
SDCLK_IN
MD19
I
IN
V
V
---
---
T
IO
IO
BAT
I/O
IN ,
T
TS
LED#
OD
V
SB
2/5
14
AJ29
AJ30
V
PWR
I/O
---
---
---
---
V
V
PWR
PWR
---
---
---
---
IO
SB
MD22
IN ,
V
T
IO
SBL
TS
2/5
www.national.com
48
Revision 6.0
Signal Definitions (Continued)
Table 2-4. 481-TEPBGA Ball Assignment - Sorted by Ball Number (Continued)
1
1
Ball
No.
I/O
Buffer Power
Ball
No.
I/O
Buffer Power
Rail Configuration
Signal Name
PWRCNT2
SDATA_IN2
(PU/PD) Type
Rail Configuration
Signal Name
MA7
(PU/PD) Type
6, 2
14
O
I
V
V
---
AL23
AL24
O
O
O
O
V
V
V
---
---
---
AL7
AL8
OD
IN
SB
SB
2/5
2/5
IO
IO
IO
MA4
F3BAR0+Memory
Offset 08h[21] = 1
TS
6
6
6
MD8
I/O
IN ,
T
AL25
AL26
AL27
6
MD2
MD4
I/O
I/O
IN ,
V
V
---
AL9
T
IO
IO
TS
2/5
TS
2/5
MD10
MD9
I/O
I/O
IN ,
TS
2/5
V
V
---
---
T
IO
IO
6
IN ,
---
AL10
T
TS
2/5
IN ,
T
AL11
AL12
AL13
AL14
AL15
AL16
DQM0
CS0#
O
O
O
O
V
V
---
---
---
---
---
---
---
2/5
2/5
IO
IO
TS
2/5
AL28
AL29
MA12
MD23
O
O
V
V
---
---
2/5
IO
IO
V
GND
O
---
---
6
SS
I/O
IN ,
T
TS
2/5
MA0
O
O
V
V
2/5
2/5
IO
IO
AL30
AL31
V
V
PWR
GND
---
---
---
---
---
---
IO
DQM4
O
SS
V
GND
I/O
---
---
SS
6
6
MD38
IN ,
V
1.
2.
For Buffer Type definitions, refer to Table 8-9 "Buffer Types" on page
377.
Is 5V tolerant (ACK#, AFD#/DSTRB#, BUSY/WAIT#, ERR#, INIT#,
PD[7:0], PE, SLCT, SLIN#/ASTRB#, STB#/WRITE#, ONCTL#,
PWRCNT[2:1]).
AL17
AL18
T
IO
TS
2/5
MD39
I/O
IN ,
V
---
T
IO
TS
2/5
3.
4.
5.
6.
The TFT_PRSNT strap determines the power-on reset (POR) state of
PMR[23].
The LPC_ROM strap determines the power-on reset (POR) state of
PMR[14] and PMR[22].
May need 5V tolerant protection at system level (DDC_SCL,
DDC_SDA).
Is back-drive protected (MD[63:0], DPOS_PORT1, DNEG_PORT1,
DPOS_PORT2, DNEG_PORT2, DPOS_PORT3, DNEG_PORT3,
ACK#, AFD#/DSTRB#, BUSY/WAIT#, ERR#, INIT#, PD[7:0], PE,
SLCT, SLIN#/ASTRB#, STB#/WRITE#, ONCTL#, PWRCNT[2:1]).
AL19
AL20
V
GND
I/O
---
---
---
---
SS
6
6
MD44
MD40
CKEA
IN ,
V
V
V
T
IO
IO
IO
TS
2/5
I/O
O
IN ,
---
---
AL21
AL22
T
TS
2/5
O
2/5
Revision 6.0
49
www.national.com
Signal Definitions (Continued)
Table 2-5. 481-TEPBGA Ball Assignment - Sorted Alphabetically by Signal Name
Signal Name
Ball No.
Signal Name
Ball No.
Signal Name
Ball No.
A0
U1
P3
U3
N1
P1
N3
N2
M2
M4
L2
AD18
E3
D0
C2
C4
A1
AD19
E2
D1
A2
AD20
D3
D2
C1
A3
AD21
D1
D3
D4
A4
AD22
D2
D4
B4
A5
AD23
B6
D5
B3
A6
AD24
C2
D6
A3
A7
AD25
C4
D7
D5
A8
AD26
C1
D8
L1
A9
AD27
D4
D9
J2
A10
L3
AD28
B4
D10
F3
A11
K1
L4
AD29
B3
D11
H4
A12
AD30
A3
D5
D12
J4
A13
J1
AD31
D13
F1
A14
K4
J3
AFD#/DSTRB#
AVCCCRT
D22
D14
F2
A15
A12, C13, D15
D15
G1
A16
E1
F4
DCD2#
DDC_SCL
DDC_SDA
DEVSEL#
DID0
C28
Y1
AVCCTV
D23
D27
A17
AVCCUSB
AVSSCRT
AVSSPLL2
AVSSPLL3
AVSSTV
A18
E3
E2
D3
D1
D2
B6
N31
N30
N29
M29
P31
U29
B18
U1
P3
U3
N1
P1
N3
N2
M2
M4
L2
Y2
B14, C14, C15
C16
A19
E4
A20
C5
AK3
A21
DID1
C6
B24
A22
DNEG_PORT1
DNEG_PORT2
DNEG_PORT3
DOCCS#
DOCR#
DOCW#
DPOS_PORT1
DPOS_PORT2
DPOS_PORT3
DQM0
A29
B28
A27
A9, N31
D9
AVSSUSB
C27
A23
BA0
AJ13
AK14
E4
AB1C
AB1D
AB2C
AB2D
AC97_CLK
AC97_RST#
ACK#
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
BA1
BHE#
BIT_CLK
BLUE
U30
A8
A15
A28
B27
A26
AL11
AH23
AG30
AC31
AL15
AK21
AG29
AB31
B29
AG1
D28
D21
C21
A21
D20
C20
C18
C19
BOOT16
BUSY/WAIT#
C/BE0#
C/BE1#
C/BE2#
C/BE3#
CASA#
Cb
C8
B17
L1
J2
DQM1
F3
DQM2
H4
DQM3
AJ12
A24, C23
AL22
AA4
DQM4
DQM5
CKEA
DQM6
CLK27M
CLK32
CLKSEL0
CLKSEL1
CLKSEL2
CLKSEL3
Cr
DQM7
AH8
DSR2#
DTR1#/BOUT1
DTR2#/BOUT2
ERR#
B8
AF3
L3
D29
K1
L4
P30
F_AD0
F_AD1
F_AD2
F_AD3
F_AD4
F_AD5
C23, D24
AL12
AH27
C31
J1
CS0#
K4
J3
CS1#
CTS2#
CVBS
E1
F4
A23, A24, D24
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50
Revision 6.0
Signal Definitions (Continued)
Table 2-5. 481-TEPBGA Ball Assignment - Sorted Alphabetically by Signal Name (Continued)
Signal Name
Ball No.
Signal Name
Ball No.
Signal Name
Ball No.
F_AD6
A20
A18
D21
B17
D17
C17
V31
A22
U31
B20
U29
U30
V30, AB1
A4
GTEST
F30
V30
A11
AD3
AE1
U2
IRQ15
IRRX1
IRTX
AJ8
AK8
F_AD7
GXCLK
F_C/BE0#
F_C/BE1#
F_C/BE2#
F_C/BE3#
F_DEVSEL#
F_FRAME#
F_GNT0#
F_IRDY#
F_STOP#
F_TRDY#
FP_VDD_ON
FPCI_MON
FPCICLK
FRAME#
GNT0#
HSYNC
C11
IDE_ADDR0
IDE_ADDR1
IDE_ADDR2
IDE_CS0#
IDE_CS1#
IDE_DACK0#
IDE_DACK1#
IDE_DATA0
IDE_DATA1
IDE_DATA2
IDE_DATA3
IDE_DATA4
IDE_DATA5
IDE_DATA6
IDE_DATA7
IDE_DATA8
IDE_DATA9
IDE_DATA10
IDE_DATA11
IDE_DATA12
IDE_DATA13
IDE_DATA14
IDE_DATA15
IDE_DREQ0
IDE_DREQ1
IDE_IOR0#
IDE_IOR1#
IDE_IORDY0
IDE_IORDY1
IDE_IOW0#
IDE_IOW1#
IDE_RST#
INIT#
LAD0
LAD1
LAD2
LAD3
LDRQ#
LED#
LFRAME#
LOCK#
LPC_ROM
LPCPD#
MA0
M28
L31
L30
AF2
P2
L29
L28
AD4
C30
AC3
AC1
AC2
AB4
AB1
AA4
AA3
AA2
Y3
AL4
K31
H3
D6
K28
AL14
AH15
AK15
AJ24
AL24
AK23
AJ23
AL23
AH22
AH21
AJ14
AH26
AL28
AJ9
B18
D8
MA1
MA2
C5
MA3
GNT1#
C6
MA4
GPIO0
D11
D10, N30
D28
C30
C31
C28
B29
AJ8
N29
M29
D9
MA5
GPIO1
Y2
MA6
GPIO6
Y1
MA7
GPIO7
W4
MA8
GPIO8
W3
MA9
GPIO9
V3
MA10
MA11
MA12
MD0
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO32
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
GPIO38/IRRX2
GPIO39
GPIO40
GPIO41
GPWIO0
GPWIO1
GPWIO2
GREEN
V2
V1
AC4
C31
Y4
MD1
AK9
MD2
AL9
A8
D28
AD1
B29
AD2
C28
AA1
B21
D26
C26
C9
MD3
AH10
AL10
AH11
AJ11
AK11
AL25
AL27
AL26
AJ26
AK27
AH24
AK26
AK24
AK29
AJ31
AH28
AJ28
AH30
AG28
AJ30
V31
A10
AG1
C9
MD4
MD5
MD6
MD7
A9, N31
M28
L31
MD8
MD9
INTA#
MD10
MD11
MD12
MD13
MD14
MD15
MD16
MD17
MD18
MD19
MD20
MD21
MD22
L30
INTB#
L29
INTC#
L28
INTD#
AA2
D22
C9
K31
K28
J31
INTR_O
IOCHRDY
IOCS0#
A10
D10, N30
D9
Y3
IOCS1#
W4
IOR#
AH6
AK5
AJ6
A14
IOW#
A8
IRDY#
F2
IRQ9
AA3
AF1
IRQ14
Revision 6.0
51
www.national.com
Signal Definitions (Continued)
Table 2-5. 481-TEPBGA Ball Assignment - Sorted Alphabetically by Signal Name (Continued)
Signal Name
Ball No.
Signal Name
Ball No.
Signal Name
Ball No.
MD23
MD24
MD25
MD26
MD27
MD28
MD29
MD30
MD31
MD32
MD33
MD34
MD35
MD36
MD37
MD38
MD39
MD40
MD41
MD42
MD43
MD44
MD45
MD46
MD47
MD48
MD49
MD50
MD51
MD52
MD53
MD54
MD55
MD56
MD57
MD58
MD59
MD60
MD61
MD62
MD63
ONCTL#
OVER_CUR#
PAR
AL29
AB28
AC28
AC29
AC30
AE31
AD29
AD30
AD31
AJ15
AJ16
AH16
AK17
AJ17
AH17
AL17
AL18
AL21
AH20
AJ20
AK20
AL20
AJ19
AK18
AJ18
AH29
AF29
AF28
AH31
AD28
AF31
AF30
AG31
Y31
PD0
C21
A21
D20
C20
C18
C19
A20
A18
D17
H2
SMI_O
SOUT1
SOUT2
SOUT3
STB#/WRITE#
STOP#
SVC
B21
AF3
PD1
PD2
D29
PD3
C11
PD4
A22
PD5
G1
PD6
C23
PD7
SVY
A24
PE
SYNC
P30
PERR#
PLL2B
TCK
E31
AH3
AJ1
AG4
AH9
AH1
AH5
AK6
AL7
AK12
B8
TDI
F29
PLL5B
TDN
D31
PLL6B
TDO
E30
POR#
TDP
D30
POWER_EN
PWRBTN#
PWRCNT1
PWRCNT2
RASA#
RD#
TEST0
TEST1
TEST2
TEST3
TFT_PRSNT
TFTD0
TFTD1
TFTD2
TFTD3
TFTD4
TFTD5
TFTD6
TFTD7
TFTD8
TFTD9
TFTD10
TFTD11
TFTD12
TFTD13
TFTD14
TFTD15
TFTD16
TFTD17
TFTDCK
TFTDE
THRM#
TMS
AH3
AG4
AJ1
V30
P29
A9, AD4
A20, AF1
D22, AE1
B17, AD3
D21, U2
B21, AF2
C21, AC3
A21, V1
D20, AC4
C20, AD2
C18, Y4
C19, AD1
D10, AB4
A18, W3
D17, AC2
C17, V3
B20, AC1
A22, V2
A10, AA1
B18, P2
AK4
RED
B12
B5
REQ0#
REQ1#
RI2#
A5
AJ8
C8
ROMCS#
RTS2#
C30
U31
AL8
P29
AJ27
AK28
AJ21
W29
AA28
V29
C30
B29
C28
E28
C31
D28
J31
SDATA_IN
SDATA_IN2
SDATA_OUT
SDCLK_IN
SDCLK_OUT
SDCLK0
SDCLK1
SDCLK2
SDCLK3
SDTEST0
SDTEST1
SDTEST2
SDTEST3
SDTEST4
SDTEST5
SERIRQ
SERR#
SETRES
SIN1
W28
Y28
Y29
Y30
AA29
AA30
AA31
AJ5
F28
TRDE#
TRDY#
TRST#
TVB
D11
AF4
H1
F1
J4
B15
AG2
E28
AK8
C17
B20
E29
PC_BEEP
PCICLK
PCICLK0
PCICLK1
PCIRST#
V31
C23
A7
SIN2
TVB
D24
A4
SIN3
TVCOMP
TVG
B26
D6
SLCT
A23
A6
SLIN#/ASTRB#
TVIOM
B23
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52
Revision 6.0
Signal Definitions (Continued)
Table 2-5. 481-TEPBGA Ball Assignment - Sorted Alphabetically by Signal Name (Continued)
Signal Name
Ball No.
Signal Name
Ball No.
Signal Name
Ball No.
TVR
A24, C23
C24
VPD2
VPD3
VPD4
VPD5
VPD6
VPD7
VPLL2
VPLL3
VREF
VSB
J28
H31
H30
H29
H28
G31
A17
AJ4
D16
AL5
VSYNC
WEA#
WR#
X27I
B11
AH12
B9
TVREF
TVRSET
VBAT
A25
AL3
AG3
AH2
AJ2
AJ3
A23
X27O
X32I
VCCCRT
D12
VCORE
N13, N14, N18,
N19, P4, P13,
P14, P18, P19,
P28, T1, T2, T3,
T4, T28, T29,
T30, T31, U4,
U28, V13, V14,
V18, V19, W13,
W14, W18, W19
X32O
Y
(Total of 28)
VSBL
AL6
VSS
A1, A13, A16,
A19, A31, B1, B7,
B10, B22, B25,
B30, D7, D13,
D19, D25, G2,
G4, G28, G30,
K3, K30, M1,
(Total of 91)
VIO
A2, A30, B2, B13,
B16, B19, B31,
C3, C7, C10,
(Total of 42)
C22, C25, C29,
D14, D18, G3,
G29, K2, K29,
M3, M30, W1,
W31, AB3, AB29,
AE3, AE29, AH4,
AH14, AH18, AJ7,
AJ10, AJ22,
AJ25, AJ29, AK1,
AK13, AK16,
AK19, AK31, AL2,
AL30,
M31, N4, N15,
N16, N17, N28,
P15, P16, P17,
R1, R2, R3, R4,
R13, R14, R15,
R16, R17, R18,
R19, R28, R29,
R30, R31, T13,
T14, T15, T16,
T17, T18, T19,
U13, U14, U15,
U16, U17, U18,
U19, V4, V15,
V16, V17, V28,
W2, W15, W16,
W17, W30, AB2,
AB30, AE2, AE4,
AE28, AE30,
VOPCK
VOPD0
VOPD1
VOPD2
VOPD3
VOPD4
VOPD5
VOPD6
VOPD7
VPCKIN
VPD0
B18
A20
D22
B17
D21
B21
C21
A21
D20
F31
J30
J29
AH7, AH13,
AH19, AH25,
AK2, AK7, AK10,
AK22, AK25,
AK30, AL1, AL13,
AL16, AL19, AL31
VPD1
VSSCRT
C12
Revision 6.0
53
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Signal Definitions (Continued)
2.2 STRAP OPTIONS
Several balls are read at power-up that set up the state of
the SC1200/SC1201. These balls are typically multiplexed
with other functions that are outputs after the power-up
sequence is complete. The SC1200/SC1201 must read the
state of the balls at power-up and the internal PU or PD
resistors do not guarantee the correct state will be read.
Therefore, it is required that an external PU or PD resistor
with a value of 1.5 KΩ be placed on the balls listed in Table
2-6. The value of the resistor is important to ensure that the
proper state is read during the power-up sequence. If the
ball is not read correctly at power-up, the SC1200/SC1201
may default to a state that causes it to function improperly,
possibly resulting in application failure.
Table 2-6. Strap Options
Ball No.
Nominal
Internal
External PU/PD Strap Settings
Strap
Option
Muxed With
RD#
EBGA TEPBGA PU or PD Strap = 0 (PD) Strap = 1 (PU) Register References
CLKSEL0
CLKSEL1
CLKSEL2
CLKSEL3
F3
B8
PD100
PD100
PD100
PD100
See Table 3-7 on page 99 for
CLKSEL strap options.
GCB+I/O Offset 1Eh[9:8] (aka
CCFC register bits [9:8]) (RO):
Value programmed at reset by
CLKSEL[1:0].
SOUT1
SOUT2
SYNC
B27
AK3
AL13
AF3
D29
P30
GCB+I/O Offset 10h[3:0] (aka
MCCM register bits [3:0]) (RO):
Value programmed at reset by
CLKSEL[3:0].
GCB+I/O Offset 1Eh[3:0] (aka
CCFC register bits [3:0]) (R/W,
but write not recommended):
Value programmed at reset by
CLKSEL[3:0].
Note: Values for GCB+I/O Offset
10h[3:0] and 1Eh[3:0] are not the
same.
BOOT16
ROMCS#
G4
C8
PD100
Enable boot
from 8-bit ROM from 16-bit
ROM
Enable boot
GCB+I/O Offset 34h[3] (aka MCR
register bit 3) (RO): Reads back
strap setting.
GCB+I/O Offset 34h[14] (R/W):
Used to allow the ROMCS# width
to be changed under program
control.
TFT_PRSNT SDATA_OUT
AK13
E4
P29
D6
PD100
PD100
TFT not muxed TFT muxed
GCB+I/O Offset 30h[23] (aka
PMR register bit 23) (R/W):
Reads back strap setting.
onto Parallel
Port
onto Parallel
Port
LPC_ROM
FPCI_MON
PCICLK1
PCICLK0
Disable boot
from ROM on
LPC bus
Enable boot
from ROM on
LPC bus
F0BAR1+I/O Offset 10h[15]
(R/W): Reads back strap setting
and allows LPC ROM to be
changed under program control.
D3
A4
PD100
Disable Fast-
PCI, INTR_O,
and SMI_O
Enable Fast-
PCI, INTR_O,
and SMI_O
GCB+I/O Offset 34h[30] (aka
MCR register bit 30) (RO): Reads
back strap setting.
monitoring sig- monitoring sig-
Note: For normal operation,
strap this signal low using
a 1.5 KΩ resistor.
nals.
nals. (Useful
during debug.)
DID0
DID1
GNT0#
GNT1#
D4
D2
C5
C6
PD100
PD100
Defines the system-level chip ID. GCB+I/O Offset 34h[31,29] (aka
MCR register bits 31 and 29)
(RO): Reads back strap setting.
Note: These signals should be
connected to a 1.5 KΩ PD
resistor to ensure a low
level at power-up.
Note: Accuracy of internal PU/PD resistors: 80K to 250K.
Location of the GCB (General Configuration Block) cannot be determined by software. See the SC1200/SC1201 Set-Top Box On
a Chip device errata document.
www.national.com
54
Revision 6.0
Signal Definitions (Continued)
2.3 MULTIPLEXING CONFIGURATION
The tables that follow list multiplexing options and their
configurations. Certain multiplexing options may be chosen
per signal; others are available only for a group of signals.
system reset, the pull-up is present. This pull-up resistor
can be disabled by writing Core Logic registers. The config-
uration is without regard to the selected ball function. The
above applies to all pins multiplexed with GPIO, except
GPIO12, GPIO13, and GPIO16.
Where ever a GPIO pin is multiplexed with another func-
tion, there is an optional pull-up resistor on this pin; after
Table 2-7. Two-Signal/Group Multiplexing
Default
Alternate
EBGA
TEPBGA
Signal
Configuration
Signal
Configuration
Ball No.
IDE
TFT, CRT, PCI, GPIO, System
A26
C26
C17
B24
A24
D23
C23
B23
A23
C22
B22
A21
C20
A20
C19
B19
A19
C18
B18
C21
A25
C24
D24
A27
C16
C25
A22
D25
AD3
AE1
U2
IDE_ADDR0
IDE_ADDR1
IDE_ADDR2
IDE_DATA0
IDE_DATA1
IDE_DATA2
IDE_DATA3
IDE_DATA4
IDE_DATA5
IDE_DATA6
IDE_DATA7
IDE_DATA8
IDE_DATA9
IDE_DATA10
IDE_DATA11
IDE_DATA12
IDE_DATA13
IDE_DATA14
IDE_DATA15
IDE_IOR0#
IDE_IORDY0
IDE_DREQ0
IDE_IOW0#
IDE_CS0#
PMR[24] = 0
TFTD3
TFTD2
TFTD4
TFTD6
TFTD16
TFTD14
TFTD12
PMR[24] = 1
AC3
AC1
AC2
AB4
AB1
AA4
AA3
AA2
Y3
FP_VDD_ON
CLK27M
IRQ9
INTD#
GPIO40
DDC_SDA
DDC_SCL
GPIO41
TFTD13
TFTD15
TFTD17
TFTD7
Y2
Y1
W4
W3
V3
V2
V1
Y4
TFTD10
TFTD11
TFTD8
AD1
AC4
AD2
AF2
P2
TFTD9
TFTD5
IDE_CS1#
TFTDE
AD4
AA1
AF1
IDE_DACK0#
IDE_RST#
TFTD0
TFTDCK
TFTD1
IRQ14
Ball No.
D11
Sub-ISA
GPIO
H1
TRDE#
PMR[12] = 0
GPIO0
PMR[12] = 1
Revision 6.0
55
www.national.com
Signal Definitions (Continued)
Table 2-7. Two-Signal/Group Multiplexing (Continued)
Default Alternate
EBGA
TEPBGA
Signal
Configuration
Signal
Configuration
Ball No.
GPIO
ACCESS.bus
PMR[19] = 1
AJ12
AL11
N29
M29
GPIO12
PMR[19] = 0
AB2C
AB2D
GPIO13
Ball No.
GPIO
UART
A28
AG1
GPIO18
PMR[16] = 0
Infrared
DTR1#/BOUT1
PMR[16] = 1
UART
Ball No.
J3
C11
AK8
IRTX
PMR[6] = 0
SOUT3
SIN3
PMR[6] = 1
J28
IRRX1
Ball No.
GPIO
LPC
AJ11
AL10
AK10
AJ10
AL9
M28
L31
L30
L29
L28
K31
K28
J31
GPIO32
PMR[14] = 0 and
PMR[22] = 0
LAD0
PMR[14] = 1 and
PMR[22] = 1
GPIO33
LAD1
GPIO34
LAD2
GPIO35
LAD3
GPIO36
LDRQ#
LFRAME#
LPCPD#
SERIRQ
AK9
AJ9
GPIO37
GPIO38/IRRX2
GPIO39
AL8
Ball No.
UART
Internal Test
AJ4
E28
SIN2
PMR[28] = 0
AC97
SDTEST3
PMR[28] = 1
FPCI Monitoring
FPCI_MON = 1
Ball No.
AJ15
AK14
AL14
U29
U31
U30
AC97_RST#
SDATA_IN
BIT_CLK
FPCI_MON = 0
F_STOP#
F_GNT0#
F_TRDY#
Ball No.
Internal Test
Internal Test
C28
B29
D28
AG4
AJ1
AH3
PLL6B
PLL5B
PLL2B
PMR[29] = 0
TEST1
TEST2
TEST0
PMR[29] = 1
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56
Revision 6.0
Signal Definitions (Continued)
Table 2-8. Three-Signal/Group Multiplexing
Default
Configuration
Alternate1
Alternate2
Signal Configuration
EBGA TEPBGA
Ball No.
Signal
Signal
Configuration
Sub-ISA1
PMR[21] = 0 and
Sub-ISA
PMR[21] = 0 and DOCR#
GPIO
PMR[21] = 1 and
F1
D9
A8
IOR#
GPIO14
GPIO15
PMR[2] = 0
PMR[2] = 1
PMR[2] = 1
G3
IOW#
DOCW#
Ball No.
GPIO
AC97
FPCI Monitoring
AL15
V31
GPIO16
PMR[0] = 0 and
FPCI_MON = 0
PC_BEEP
PMR[0] = 1 = 0 and F_DEVSEL
FPCI_MON = 0
FPCI_MON = 1
Ball No.
GPIO
PCI2
Sub-ISA
H4
C9
GPIO19
GPIO17
PMR[9] = 0 and
PMR[4] = 0
INTC#
PMR[9] = 0 and
PMR[4] = 1
IOCHRDY
TFTDCK
PMR[9] = 1 and
PMR[4] = 1
Ball No.
GPIO
Sub-ISA
TFT3
J4
H3
H2
A10
(PMR[23] = 0 and IOCS0#
PMR[5] = 0) or
(PMR[23] = 1 and
PMR[15] = 1 and
PMR[5] = 0)
(PMR[23] = 0 and
PMR[5] = 1) or
(PMR[23] = 1 and
PMR[15] = 1 and
PMR[5] = 1)
PMR[23] = 1 and
PMR[15] = 0
A9
GPIO20
GPIO1
(PMR[23] = 0 and DOCCS#
PMR[7] = 0) or
(PMR[23] = 1 and
PMR[15] = 1 and
PMR[7] = 0)
(PMR[23] = 0 and
PMR[7] = 1) or
(PMR[23] = 1 and
PMR[15] = 1 and
PMR[7] = 1)
TFTD0
PMR[23] = 1 and
PMR[15] = 0
D10
(PMR[23] = 0 and IOCS1#
PMR[13] = 0) or
(PMR[23] = 1 and
PMR[15] = 1 and
PMR[13] = 0)
(PMR[23] = 0 and
PMR[13] = 1) or
(PMR[23] = 1 and
PMR[15] = 1 and
PMR[13] = 1)
TFTD12
PMR[23] = 1 and
PMR[15] = 0
Ball No.
AB1
GPIO
Sub-ISA
AJ13
N31
AB1C
AB1D
PMR[23] = 0 or
(PMR[23] = 1 and
PMR[15] = 1)
GPIO20
GPIO1
PMR[23] = 1 and
PMR[15] = 0 and
PMR[7] = 0
DOCCS#
IOCS1#
PMR[23] = 1 and
PMR[15] = 0 and
PMR[7] = 1
AL12
N30
PMR[23] = 0 or
(PMR[23] = 1 and
PMR[15] = 1)
PMR[23] = 1 and
PMR[15] = 0 and
PMR[13] = 0
PMR[23] = 1 and
PMR[15] = 0 and
PMR[13] = 1
Ball No.
GPIO
UART2
IDE2
H30
AJ8
GPIO11
GXCLK
PMR[18] = 0 and RI2#
PMR[8] = 0
PMR[18] = 1 and
PMR[8] = 0
IRQ15
TEST3
PMR[18] = 0 and
PMR[8] = 1
Ball No.
Internal Test
TFT
Internal Test
AL16
V30
(PMR[29] = 0 and FP_VDD_ON
PMR[23] = 0) or
PMR[23] = 1 and
PMR[15] = 0
PMR[29] = 1 and
PMR[23] = 0
(PMR[23] = 1 and
PMR[15] = 1)
1. The combination of PMR[21] = 1 and PMR[2] = 0 is undefined and should not be used.
2. The combination of PMR[9] = 1 and PMR[4] = 0 is undefined and should not be used.
3. These TFT outputs are reset to 0 by POR# if the TFT_PRSNT strap is pulled high or PMR[10] = 0. This relates to signals TFTD[17:0],
TFTDE, TFTDCK.
Revision 6.0
57
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Signal Definitions (Continued)
Table 2-9. Four-Signal/Group Multiplexing
Default
Alternate1
Configuration
UART2
Alternate2
Configuration
IDE2
Alternate3
Signal Configuration
Signal
Configuration
GPIO
Signal
Signal
Ball No.
AH4 C30 GPIO7
Internal Test
PMR[17] = 1 and
PMR[17] = 0 and RTS2#
PMR[17] = 1 and IDE_DACK1#
PMR[17] = 0 and SDTEST0
PMR[8] = 0
PMR[8] = 0
PMR[8] = 1
PMR[8] = 1
AJ2
AH3
AG4
AJ1
C31 GPIO8
D28 GPIO6
C28 GPIO9
B29 GPIO10
CTS2#
IDE_DREQ1
SDTEST4
PMR[18] = 0 and DTR2#/BOUT2
PMR[8] = 0
PMR[18] = 1 and IDE_IOR1#
PMR[8] = 0
PMR[18] = 0 and SDTEST5
PMR[8] = 1
PMR[18] = 1 and
PMR[8] = 1
DCD2#
IDE_IOW1#
SDTEST2
DSR2#
IDE_IORDY1
SDTEST1
Ball No.
Parallel Port
PMR[23] = 0
TFT
(PMR[23] = 1
and
PMR[15] = 0)
and
VOP
FPCI Monitoring
U3
B18
D22
ACK#
TFTDE
TFTD2
VOPCK
VOPD1
(PMR[23] = 1
and
PMR[15] = 1)
and
(PMR[27] = 0
and
FPCI_CLK PMR[23] = 0
and
(PMR[27] = 0
and
and
AB2
AFD#/
DSTRB#
INTR_O
(PMR[27] = 1 or
FPCI_MON = 1)
F_C/BE1#
T1
B17
BUSY/
WAIT#
FPCI_MON = 0)
TFTD3
(PMR[27] = 0
and
VOPD2
FPCI_MON = 0)
FPCI_MON = 0)
AA3
Y3
D21
B21
C21
A21
D20
A20
ERR#
INIT#
PD0
TFTD4
TFTD5
TFTD6
TFTD7
TFTD8
TFTD1
VOPD3
VOPD4
VOPD5
VOPD6
VOPD7
VOPD0
F_C/BE0#
SMI_O
F_AD0
F_AD1
F_AD2
F_AD6
AA1
Y1
PD1
W3
V3
PD2
PD6
Three-Signal/Group Multiplexing (shown here for interface clarification)
W2
V1
V2
U1
T3
C20
C18
C19
A18
D17
C17
B20
PD3
PD4
PD5
PD7
PE
PMR[23] = 0
and
(PMR[27] = 0
and
TFTD9
TFTD10
TFTD11
TFTD13
TFTD14
TFTD15
TFTD16
PMR[23] = 1
and
(PMR[27] = 0
and
---
F_AD3
F_AD4
PMR[23] = 0
and
(PMR[27] = 1 or
FPCI_MON = 1)
F_AD5
FPCI_MON = 0)
FPCI_MON = 0)
F_AD7
F_C/BE2#
F_C/BE3#
F_IRDY
T4
SLCT
W1
SLIN#
/ASTRB#
AB1
A22
STB#/
TFTD17
F_FRAME#
WRITE#
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58
Revision 6.0
Signal Definitions (Continued)
2.4 SIGNAL DESCRIPTIONS
Information in the tables that follow may have duplicate information in multiple tables. Multiple references all contain identi-
cal information.
2.4.1 System Interface
Ball No.
Signal Name
EBGA
TEPBGA Type Description
Mux
CLKSEL1
CLKSEL0
B27
F3
AF3
B8
I
Fast-PCI Clock Selects. These strap signals
are used to set the internal Fast-PCI clock.
SOUT1
RD#
00 = 33.3 MHz
01 = 48 MHz
10 = 66.7 MHz
11 = 33.3 MHz
During system reset, an internal pull-down
resistor of 100 KΩ exists on these balls. An
external pull-up or pull-down resistor of 1.5
KΩ must be used.
CLKSEL3
CLKSEL2
AL13
AK3
P30
D29
I
I
I
Maximum Core Clock Multiplier. These
strap signals are used to set the maximum
allowed multiplier value for the core clock.
SYNC
SOUT2
During system reset, an internal pull-down
resistor of 100 KΩ exists on these balls. An
external pull-up or pull-down resistor of 1.5
KΩ must be used.
BOOT16
G4
E4
C8
D6
Boot ROM is 16 Bits Wide. This strap signal
enables the optional 16-bit wide Sub-ISA
bus.
ROMCS#
PCICLK1
During system reset, an internal pull-down
resistor of 100 KΩ exists on these balls. An
external pull-up or pull-down resistor of 1.5
KΩ must be used.
LPC_ROM
LPC_ROM. This strap signal forces selecting
of the LPC bus and sets bit F0BAR1+I/O Off-
set 10h[15], LPC ROM Addressing Enable. It
enables the SC1200/SC1201 to boot from a
ROM connected to the LPC bus.
During system reset, an internal pull-down
resistor of 100 KΩ exists on these balls. An
external pull-up or pull-down resistor of 1.5
KΩ must be used.
TFT_PRSNT
AK13
P29
I
TFT Present. A strap used to select multi-
plexing of TFT signals at power-up. Enables
using TFT instead of Parallel Port, ACB1,
and GPIO17.
SDATA_OUT
During system reset, an internal pull-down
resistor of 100 KΩ exists on these balls. An
external pull-up or pull-down resistor of 1.5
KΩ must be used.
FPCI_MON
D3
A4
I
Fast-PCI Monitoring. The strap on this ball
forces selection of Fast-PCI monitoring sig-
nals. For normal operation, strap this signal
low using a 1.5 KΩ resistor. The value of this
strap can be read on the MCR[30].
PCICLK0
Revision 6.0
59
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Signal Definitions (Continued)
2.4.1 System Interface (Continued)
Ball No.
Signal Name
EBGA
TEPBGA Type Description
Mux
DID1
DID0
D2
D4
C6
C5
I
I
Device ID. Together, the straps on these sig-
nals define the system-level chip ID.
GNT1#
GNT0#
The value of DID1 can be read in the
MCR[29]. The value of DID0 can be read in
the MCR[31].
DID1 and DID0 should be connected to a 1.5
KΩ pull-down resistor to ensure a low level at
power-up.
POR#
J29
AH9
I
Power On Reset. POR# is the system reset
signal generated from the power supply to
indicate that the system should be reset.
---
X32I
C30
D29
AJ2
AJ3
I/O
Crystal Connections. Connected directly to
a 32.768 KHz crystal. This clock input is
required even if the internal RTC is not being
used. Some of the internal clocks are derived
from this clock. If an external clock is used, it
should be connected to X32I, using a voltage
level of 0 volts to VCORE +10% maximum.
---
---
X32O
X32O should remain unconnected.
X27I
A29
D27
AG3
AH2
I/O
Crystal Connections. Connected directly to
a 27.000 MHz crystal. This clock input is
used for video circuits. Some of the internal
clocks are derived from this clock. If the inter-
nal TV encoder is used, a 25 ppm crystal is
recommended. If an external clock is used, it
should be connected to X27I, using a voltage
level of 0 volts to VIO and X27O should be
---
---
X27O
remain unconnected.
CLK27M
PCIRST#
A23
D1
AA4
A6
O
O
27 MHz Output Clock. Output of crystal
oscillator.
IDE_DATA5
---
PCI and System Reset. PCIRST# is the
reset signal for the PCI bus and system. It is
asserted for approximately 100 µs after
POR# is negated.
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60
Revision 6.0
Signal Definitions (Continued)
2.4.2 Memory Interface Signals
Ball No.
Signal Name
EBGA
TEPBGA Type Description
Mux
MD[63:0]
See
See
I/O
Memory Data Bus. The data bus lines
---
Table 2-3 Table 2-5
driven to/from system memory.
on page
34
on page
50
MA[12:0]
See
See
O
Memory Address Bus. The multiplexed
row/column address lines driven to the sys-
tem memory. Supports 256-Mbit SDRAM.
---
Table 2-3 Table 2-5
on page
34
on page
50
BA1
BA0
P31
P30
AK14
AJ13
O
O
Bank Address Bits. These bits are used to
select the component bank within the
SDRAM.
---
---
CS1#
CS0#
AK29
P29
AH27
AL12
Chip Selects. These bits are used to select
the module bank within system memory.
Each chip select corresponds to a specific
module bank. If CS# is high, the bank(s) do
not respond to RAS#, CAS#, and WE# until
the bank is selected again.
---
---
RASA#
CASA#
WEA#
N31
N30
N29
AK12
AJ12
AH12
O
O
Row Address Strobe. RAS#, CAS#, WE#
and CKE are encoded to support the different
SDRAM commands. RASA# is used with
CS[1:0]#.
---
---
---
Column Address Strobe. RAS#, CAS#,
WE# and CKE are encoded to support the
different SDRAM commands. CASA# is used
with CS[1:0]#.
O
O
Write Enable. RAS#, CAS#, WE# and CKE
are encoded to support the different SDRAM
commands. WEA# is used with CS[1:0]#.
DQM7
DQM6
DQM5
DQM4
DQM3
DQM2
DQM1
DQM0
CKEA
AJ20
AJ26
AC30
T28
AB31
AG29
AK21
AL15
AC31
AG30
AH23
AL11
AL22
Data Mask Control Bits. During memory
read cycles, these outputs control whether
SDRAM output buffers are driven on the MD
bus or not. All DQM signals are asserted dur-
ing read cycles.
---
---
---
---
---
---
---
---
---
During memory write cycles, these outputs
control whether or not MD data is written into
SDRAM.
AJ21
AL26
AF31
M31
DQM[7:0] connect directly to the [DQM7:0]
pins of each DIMM connector.
AC28
O
Clock Enable. These signals are used to
enter Suspend/power-down mode. CKEA is
used with CS[1:0]#.
If CKE goes low when no read or write cycle
is in progress, the SDRAM enters power-
down mode. To ensure that SDRAM data
remains valid, the self-refresh command is
executed. To exit this mode, and return to
normal operation, drive CKE high.
These signals should have an external pull-
down resistor of 33 KΩ.
Revision 6.0
61
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Signal Definitions (Continued)
2.4.2 Memory Interface Signals (Continued)
Ball No.
Signal Name
EBGA
TEPBGA Type Description
Mux
SDCLK3
SDCLK2
SDCLK1
SDCLK0
AJ16
AL20
AH16
AC29
V29
AA28
W29
AJ21
O
SDRAM Clocks. SDRAM uses these clocks
to sample all control, address, and data lines.
To ensure that the Suspend mode functions
correctly, SDCLK3 and SDCLK1 should be
used with CS1#. SDCLK2 and SDCLK0
should be used together with CS0#.
---
---
---
---
SDCLK_IN
AJ30
AJ27
I
SDRAM Clock Input. The SC1200/SC1201
samples the memory read data on this clock.
Works in conjunction with the SDCLK_OUT
signal.
---
SDCLK_OUT
AH28
AK28
O
SDRAM Clock Output. This output is routed
back to SDCLK_IN. The board designer
should vary the length of the board trace to
control skew between SDCLK_IN and
SDCLK.
---
2.4.3 Video Port Interface Signals
Ball No.
Mux
Signal Name
EBGA
TEPBGA Type Description
VPD7
VPD6
VPD5
VPD4
VPD3
VPD2
VPD1
VPD0
VPCKIN
AJ6
AJ7
AL6
AH8
AL7
AJ8
AK8
AH9
AH7
G31
H28
H29
H30
H31
J28
J29
J30
F31
I
Video Port Data. The data is input from the
CCIR-656 video decoder.
---
---
---
---
---
---
---
---
---
I
Video Port Clock Input. The clock input
from the video decoder.
www.national.com
62
Revision 6.0
Signal Definitions (Continued)
2.4.3 Video Port Interface Signals (Continued)
Ball No.
Mux
Signal Name
EBGA
TEPBGA Type Description
VOPD7
W3
D20
A21
C21
B21
D21
B17
D22
A20
B18
O
Video Output Port Data. The data is output
from the Video Processor in VESA Video
Interface Port Rev 1.1 Task B format.
PD2+TFTD8+
F_AD2
VOPD6
VOPD5
VOPD4
VOPD3
VOPD2
VOPD1
VOPD0
VOPCK
Y1
AA1
Y3
PD1+TFTD7+
F_AD1
PD0+TFTD6+
F_AD0
INIT#+TFTD5+
SMI_O
AA3
T1
ERR#+TFTD4+
F_CBE0#
BUSY/WAIT#+
TFTD3+F_C/BE1#
AB2
V3
AFD#/DSTRB#+
TFTD2+INTR_O
PD6+TFTD1+
F_AD6
U3
O
Video Output Port Clock. The clock output
from the Video Processor.
ACK#+TFTDE+
FPCICLK
Revision 6.0
63
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Signal Definitions (Continued)
2.4.4 CRT/TFT Interface Signals
Ball No.
Mux
Signal Name
EBGA
TEPBGA Type Description
DDC_SCL
A20
Y1
O
DDC Serial Clock. This is the serial clock for
the VESA Display Data Channel interface. It
is used for monitor communications. The
DDC2B standard is supported by this inter-
face.
IDE_DATA10
DDC_SDA
C20
Y2
I/O
DDC Serial Data. This is the bidirectional
serial data signal for the VESA Display Data
Channel interface. It is used for monitor com-
munications. The DDC2B standard is sup-
ported by this interface.
IDE_DATA9
HSYNC
VSYNC
VREF
J1
J2
P1
A11
B11
D16
O
O
Horizontal Sync
Vertical Sync
---
---
---
I/O
Voltage Reference. Reference voltage for
CRT PLL and DAC. This signal reflects the
internal voltage reference. If internal voltage
reference is used (recommended), leave this
ball disconnected. If an external voltage ref-
erence is used, this input is tied to a 1.235V
reference.
SETRES
P2
B15
I
Set Resistor. This signal sets the current
level for the RED/GREEN/BLUE analog out-
puts. Typically, a 464 Ω, 1% resistor is con-
---
nected between this ball and AVSSCRT
.
On-Chip RAMDAC
RED
K1
M3
N2
B12
A14
A15
O
Analog Red, Green and Blue
---
---
---
GREEN
BLUE
TFT (External DAC) Interface
TFTDCK
TFTDE
A22
J4
AA1
A10
P2
O
O
TFT Clock. Clock to external CRT DACs or
TFT.
IDE_RST#
GPIO17+ IOCS0#
IDE_CS1#
C16
U3
TFT Data Enable. Can be used as blank sig-
nal to external CRT DACs.
B18
ACK#+VOPCK+
FPCICLK
FP_VDD_ON
TFTD[17:0]
B23
AB1
V30
O
O
TFT Power Control. Used to enable power
to the Flat Panel display, with power
sequence timing.
IDE_DATA4
AL16
GXCLK+TEST3
See
See
Digital RGB Data to TFT.
TFTD[5:0] - Connect to BLUE TFT inputs.
The TFT interface is
muxed with the IDE
Table 2-3 Table 2-5
on page
34
on page
50
TFTD[11:6] - Connect to GREEN TFT inputs. interface or the Par-
TFTD[17:12] - Connect to RED TFT inputs.
allel Port/VOP inter-
face. See Table 2-7
on page 55 and
Table 2-9 on page
58 for details.
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64
Revision 6.0
Signal Definitions (Continued)
2.4.5 TV Interface Signals
Ball No.
Signal Name
EBGA
TEPBGA Type Description
Mux
CVBS
AD3,
AB3,
AD1
A23,
A24,
D24
O
Composite Video. Includes synchronization,
luminance and chrominance components of
video.
See F4BAR0+
Memory Offset
C08h[4:3] bit
description on
page 363 for config-
uration details.
SVY
SVC
TVR
TVG
TVB
AD1
A24
O
O
O
O
O
Super Video Luminance. S-Video lumi-
nance signal.
AC2
C23
Super Video Chrominance. S-Video
chrominance signal.
AC2,
AD1
A24,
C23
TV Red. TV Red component signal for
SCART.
AB3
A23
TV Green. TV Green component signal for
SCART.
AD3,
AC2
C23,
D24
TV Blue. TV Blue component signal for
SCART.
Y
AB3
A23
O
O
Intensity. Color intensity vector.
Cr
AD3,
AC2
C23,
D24
Chrominance Red. Red axis phase angle.
Cb
AD1,
AC2
A24,
C23
O
Chrominance Blue. Blue axis phase angle.
TVREF
AD2
C24
I/O
Voltage Reference. Reference voltage for
TV DAC. This signal reflects the internal volt-
age reference. If an external voltage refer-
ence is used, this input is tied to a 1.235V
reference.
---
TVCOMP
TVRSET
AD4
AE1
B26
A25
I
I
Current Compensation for TV DAC. A 0.1
µF to 1.2 µF capacitor is used to connect this
---
---
ball to AVCCTV
.
TV Set Resistor. This signal sets the cur-
rent-level for the TV DAC. Typically, an 1140
Ω, 1% resistor is connected between this ball
and AVSSTV. The full scale current output of
TV DACs is 32 * TVREF / TVRSET. An 1140
Ω, 1% resistor enables driving a double ter-
minated 75 Ω transmission line.
TVIOM
AC1
B23
O
TV Output Dump Current. Typically, a 9.3 Ω,
---
1% resistor is connected between this ball
and AVSSTV
.
Revision 6.0
65
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Signal Definitions (Continued)
2.4.6 ACCESS.bus Interface Signals
Ball No.
Type
Signal Name
EBGA
TEPBGA
Description
Mux
AB1C
AJ13
N31
I/O
ACCESS.bus 1 Serial Clock. This is the
GPIO20+DOCCS#
serial clock for the interface.
Note: If selected as AB1C function but not
used, tie AB1C high.
AB1D
AB2C
AB2D
AL12
AJ12
AL11
N30
N29
M29
I/O
I/O
I/O
ACCESS.bus 1 Serial Data. This is the bidi-
rectional serial data signal for the interface.
GPIO1+IOCS1#
GPIO12
Note: If AB1D function is selected but not
used, tie AB1D high.
ACCESS.bus 2 Serial Clock. This is the
serial clock for the interface.
Note: If AB2C function is selected but not
used, tie AB2C high.
ACCESS.bus 2 Serial Data. This is the bidi-
GPIO13
rectional serial data signal for the interface.
Note: If AB2D function is selected but not
used, tie AB2D high.
2.4.7 PCI Bus Interface Signals
BalL No.
Signal Name
EBGA
TEPBGA Type Description
Mux
PCICLK
E2
A7
I
PCI Clock. PCICLK provides timing for all
transactions on the PCI bus. All other PCI
signals are sampled on the rising edge of
PCICLK, and all timing parameters are
defined with respect to this edge.
---
PCICLK0
PCICLK1
D3
E4
A4
D6
O
O
PCI Clock Outputs. PCICLK0 and PCICLK1 FPCI_MON (Strap)
provide clock drives for the system at 33
LPC_ROM (Strap)
MHz. These clocks are asynchronous to PCI
signals. There is low skew between all out-
puts. One of these clock signals should be
connected to the PCICLK input. All PCI clock
users in the system (including PCICLK)
should receive the clock with as low a skew
as possible.
AD[31:24]
AD[23:0]
See
See
I/O
Multiplexed Address and Data. A bus
transaction consists of an address phase in
the cycle in which FRAME# is asserted fol-
lowed by one or more data phases. During
the address phase, AD[31:0] contain a physi-
cal 32-bit address. For I/O, this is a byte
address. For configuration and memory, it is
a DWORD address. During data phases,
AD[7:0] contain the least significant byte
(LSB) and AD[31:24] contain the most signifi-
cant byte (MSB).
D[7:0]
Table 2-3 Table 2-5
on page
34
A[23:0]
on page
50
www.national.com
66
Revision 6.0
Signal Definitions (Continued)
2.4.7 PCI Bus Interface Signals (Continued)
BalL No.
Signal Name
EBGA
TEPBGA Type Description
Mux
C/BE3#
C/BE2#
C/BE1#
C/BE0#
A8
D8
H4
F3
J2
L1
I/O
Multiplexed Command and Byte Enables.
During the address phase of a transaction
when FRAME# is active, C/BE[3:0]# define
the bus command. During the data phase,
C/BE[3:0]# are used as byte enables. The
byte enables are valid for the entire data
phase and determine which byte lanes carry
meaningful data. C/BE0# applies to byte 0
(LSB) and C/BE3# applies to byte 3 (MSB).
D11
D10
D9
A10
A13
D8
INTA#
INTB#
INTC#
INTD#
AE3
AF1
H4
D26
C26
C9
I
PCI Interrupts. The SC1200/SC1201 pro-
vides inputs for the optional “level-sensitive”
PCI interrupts (also known in industry terms
as PIRQx#). These interrupts can be
mapped to IRQs of the internal 8259A inter-
rupt controllers using PCI Interrupt Steering
Registers 1 and 2 (F0 Index 5Ch and 5Dh).
---
---
GPIO19+IOCHRDY
IDE_DATA7
B22
AA2
Note: If selected as INTC# or INTD# func-
tion(s) but not used, tie INTC# and
INTD# high.
PAR
C10
J4
I/O
Parity. Parity generation is required by all
PCI agents. The master drives PAR for
address- and write-data phases. The target
drives PAR for read-data phases. Parity is
even across AD[31:0] and C/BE[3:0]#.
D12
For address phases, PAR is stable and valid
one PCI clock after the address phase. It has
the same timing as AD[31:0] but is delayed
by one PCI clock.
For data phases, PAR is stable and valid one
PCI clock after either IRDY# is asserted on a
write transaction or after TRDY# is asserted
on a read transaction.
Once PAR is valid, it remains valid until one
PCI clock after the completion of the data
phase. (Also see PERR#.)
FRAME#
E1
D8
I/O
Frame Cycle. Frame is driven by the current
master to indicate the beginning and duration
of an access. FRAME# is asserted to indi-
cate the beginning of a bus transaction.
While FRAME# is asserted, data transfers
continue. FRAME# is de-asserted when the
transaction is in the final data phase.
---
This signal is internally connected to a pull-
up resistor.
Revision 6.0
67
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Signal Definitions (Continued)
2.4.7 PCI Bus Interface Signals (Continued)
BalL No.
Signal Name
EBGA
TEPBGA Type Description
Mux
IRDY#
C8
F2
F1
G1
I/O
I/O
I/O
Initiator Ready. IRDY# is asserted to indi-
cate that the bus master is able to complete
the current data phase of the transaction.
IRDY# is used in conjunction with TRDY#. A
data phase is completed on any PCI clock in
which both IRDY# and TRDY# are sampled
as asserted. During a write, IRDY# indicates
that valid data is present on AD[31:0]. During
a read, it indicates that the master is pre-
pared to accept data. Wait cycles are
inserted until both IRDY# and TRDY# are
asserted together.
D14
This signal is internally connected to a pull-
up resistor.
TRDY#
B8
Target Ready. TRDY# is asserted to indicate
that the target agent is able to complete the
current data phase of the transaction. TRDY#
is used in conjunction with IRDY#. A data
phase is complete on any PCI clock in which
both TRDY# and IRDY# are sampled as
asserted. During a read, TRDY# indicates
that valid data is present on AD[31:0]. During
a write, it indicates that the target is prepared
to accept data. Wait cycles are inserted until
both IRDY# and TRDY# are asserted
together.
D13
This signal is internally connected to a pull-
up resistor.
STOP#
D9
Target Stop. STOP# is asserted to indicate
that the current target is requesting that the
master stop the current transaction. This sig-
nal is used with DEVSEL# to indicate retry,
disconnect, or target abort. If STOP# is sam-
pled active by the master, FRAME# is de-
asserted and the cycle is stopped within
three PCI clock cycles. As an input, STOP#
can be asserted in the following cases:
D15
1) If a PCI master tries to access memory
that has been locked by another master.
This condition is detected if FRAME#
and LOCK# are asserted during an
address phase.
2) If the PCI write buffers are full or if a pre-
viously buffered cycle has not com-
pleted.
3) On read cycles that cross cache line
boundaries. This is conditional based
upon the programming of GX1 module’s
PCI Configuration Register, Index
41h[1].
This signal is internally connected to a pull-
up resistor.
www.national.com
68
Revision 6.0
Signal Definitions (Continued)
2.4.7 PCI Bus Interface Signals (Continued)
BalL No.
Signal Name
EBGA
TEPBGA Type Description
Mux
LOCK#
C9
H3
I/O
Lock Operation. LOCK# indicates an atomic
operation that may require multiple transac-
tions to complete. When LOCK# is asserted,
non-exclusive transactions may proceed to
an address that is not currently locked (at
least 16 bytes must be locked). A grant to
start a transaction on PCI does not guaran-
tee control of LOCK#. Control of LOCK# is
obtained under its own protocol in conjunc-
tion with GNT#.
---
It is possible for different agents to use PCI
while a single master retains ownership of
LOCK#. The arbiter can implement a com-
plete system lock. In this mode, if LOCK# is
active, no other master can gain access to
the system until the LOCK# is de-asserted.
This signal is internally connected to a pull-
up resistor.
DEVSEL#
B5
E4
I/O
Device Select. DEVSEL# indicates that the
driving device has decoded its address as
the target of the current access. As an input,
DEVSEL# indicates whether any device on
the bus has been selected. DEVSEL# is also
driven by any agent that has the ability to
accept cycles on a subtractive decode basis.
As a master, if no DEVSEL# is detected
within and up to the subtractive decode clock,
a master abort cycle is initiated (except for
special cycles which do not expect a
BHE#
DEVSEL# returned).
This signal is internally connected to a pull-
up resistor.
PERR#
B9
H2
I/O
Parity Error. PERR# is used for reporting
data parity errors during all PCI transactions
except a Special Cycle. The PERR# line is
driven two PCI clocks after the data in which
the error was detected. This is one PCI clock
after the PAR that is attached to the data.
The minimum duration of PERR# is one PCI
clock for each data phase in which a data
parity error is detected. PERR# must be
driven high for one PCI clock before being
placed in TRI-STATE. A target asserts
PERR# on write cycles if it has claimed the
cycle with DEVSEL#. The master asserts
PERR# on read cycles.
---
This signal is internally connected to a pull-
up resistor.
Revision 6.0
69
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Signal Definitions (Continued)
2.4.7 PCI Bus Interface Signals (Continued)
BalL No.
Signal Name
EBGA
TEPBGA Type Description
Mux
SERR#
A9
H1
I/O
System Error. SERR# can be asserted by
any agent for reporting errors other than PCI
parity, so that the PCI central agent notifies
the processor. When the Parity Enable bit is
set in the Memory Controller Configuration
register, SERR# is asserted upon detection
of a parity error in read operations from
DRAM.
---
This signal is internally connected to a pull-
up resistor.
REQ1#
REQ0#
E3
C1
A5
B5
I
Request Lines. REQ[1:0]# indicate to the
arbiter that an agent requires the bus. Each
master has its own REQ# line. REQ# priori-
ties (in order) are:
---
---
1) VIP
2) IDE Channel 0
3) IDE Channel 1
4) Audio
5) USB
6) External REQ0#
7) External REQ1#.
Each REQ# is internally connected to a pull-
up resistor.
GNT1#
GNT0#
D2
D4
C6
C5
O
Grant Lines. GNT[1:0]# indicate to the
requesting master that it has been granted
access to the bus. Each master has its own
GNT# line. GNT# can be retracted at any
time a higher REQ# is received or if the mas-
ter does not begin a cycle within a minimum
period of time (16 PCI clocks).
DID1 (Strap)
DID0 (Strap)
Each of these signals is internally connected
to a pull-up resistor.
GNT0# must have a pull-down resistor of 1.5
KΩ, GNT1# must have a pull-down resistor of
1.5 KΩ.
www.national.com
70
Revision 6.0
Signal Definitions (Continued)
2.4.8 Sub-ISA Interface Signals
Ball No.
Signal Name
EBGA
TEPBGA Type Description
Mux
A[23:0]
See
See
O
Address Lines
AD[23:0]
Table 2-3 Table 2-5
on page
34
on page
50
D15
D14
D13
D12
D11
D10
D9
See
See
I/O
Data Bus
STOP#
IRDY#
Table 2-3 Table 2-5
on page
34
on page
50
TRDY#
PAR
C/BE3#
C/BE2#
C/BE1#
C/BE0#
AD[31:24]
DEVSEL#
D8
D[7:0]
BHE#
B5
E4
O
O
Byte High Enable. With A0, defines byte
accessed for 16 bit wide bus cycles.
IOCS1#
H2
AL12
J4
D10
N30
A10
C8
I/O Chip Selects
GPIO1+TFTD12
AB1D+GPIO1
GPIO17+TFTDCK
BOOT16 (Strap)
GPIO20+TFTD0
AB1C+GPIO20
GPIO0
IOCS0#
ROMCS#
DOCCS#
G4
O
O
ROM or Flash ROM Chip Select
H3
A9
DiskOnChip or NAND Flash Chip Select
AJ13
H1
N31
D11
TRDE#
O
Transceiver Data Enable Control. Active
low for Sub-ISA data transfers. The signal
timing is as follows:
• In a read cycle, TRDE# has the same
timing as RD#.
• In a write cycle, TRDE# is asserted (to
active low) at the time WR# is asserted. It
continues being asserted for one PCI
clock cycle after WR# has been negated,
then it is negated.
RD#
F3
B8
B9
O
O
Memory or I/O Read. Active on any read
cycle.
CLKSEL0 (Strap)
---
WR#
G1
Memory or I/O Write. Active on any write
cycle.
IOR#
F1
G3
F1
D9
A8
D9
O
O
O
I/O Read. Active on any I/O read cycle.
I/O Write. Active on any I/O write cycle.
DOCR#+GPIO14
DOCW#+GPIO15
IOR#+GPIO14
IOW#
DOCR#
DiskOnChip or NAND Flash Read. Active
on any memory read cycle to DiskOnChip.
DOCW#
G3
A8
O
DiskOnChip or NAND Flash Write. Active
IOW#+GPIO15
on any memory write cycle to DiskOnChip.
Revision 6.0
71
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Signal Definitions (Continued)
2.4.8 Sub-ISA Interface Signals (Continued)
Ball No.
Signal Name
EBGA
TEPBGA Type Description
Mux
IRQ9
C22
AA3
C9
I
I
Interrupt 9 Request Input. Active high.
IDE_DATA6
Note: If IRQ9 function is selected but not
used, tie IRQ9 low.
IOCHRDY
H4
I/O Channel Ready
GPIO19+INTC#
Note: If IOCHRDY function is selected but
not used, tie IOCHRDY high.
2.4.9 Low Pin Count (LPC) Bus Interface Signals
Ball No.
Signal Name
EBGA
TEPBGA Type Description
Mux
LAD3
LAD2
LAD1
LAD0
LDRQ#
AJ10
AK10
AL10
AJ11
AL9
L29
L30
L31
M28
L28
I/O
LPC Address-Data. Multiplexed command,
address, bidirectional data, and cycle status.
GPIO35
GPIO34
GPIO33
GPIO32
GPIO36
I
LPC DMA Request. Encoded DMA request
for LPC interface.
Note: If LDRQ# function is selected but not
used, tie LDRQ# high.
LFRAME#
LPCPD#
SERIRQ
AK9
AJ9
AL8
K31
K28
J31
O
O
LPC Frame. A low pulse indicates the begin-
ning of a new LPC cycle or termination of a
broken cycle.
GPIO37
GPIO38/IRRX2
GPIO39
LPC Power-Down. Signals the LPC device
to prepare for power shut-down on the LPC
interface.
I/O
Serial IRQ. The interrupt requests are serial-
ized over a single signal, where each IRQ
level is delivered during a designated time
slot.
Note: If SERIRQ function is selected but
not used, tie SERIRQ high.
2.4.10 IDE Interface Signals
Ball No.
Signal Name
EBGA
TEPBGA Type Description
Mux
IDE_RST#
A22
AA1
O
IDE Reset. This signal resets all the devices
TFTDCK
that are attached to the IDE interface.
IDE_ADDR2
IDE_ADDR1
IDE_ADDR0
C17
C26
A26
U2
O
IDE Address Bits. These address bits are
used to access a register or data port in a
device on the IDE bus.
TFTD4
TFTD2
TFTD3
AE1
AD3
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72
Revision 6.0
Signal Definitions (Continued)
2.4.10 IDE Interface Signals (Continued)
Ball No.
Signal Name
EBGA
TEPBGA Type Description
Mux
IDE_DATA[15:0]
See
See
I/O
IDE Data Lines. IDE_DATA[15:0] transfers
data to/from the IDE devices.
The IDE interface is
muxed with the TFT
interface. See Table
2-7 on page 55 for
muxing details.
Table 2-3 Table 2-5
on page
34
on page
50
IDE_IOR0#
IDE_IOR1#
C21
AH3
Y4
O
O
IDE I/O Read Channels 0 and 1.
IDE_IOR0# is the read signal for Channel 0
and IDE_IOR1# is the read signal for Chan-
nel 1. Each signal is asserted at read
accesses to the corresponding IDE port
addresses.
TFTD10
D28
GPIO6+DTR2#/
BOUT2+SDTEST5#
IDE_IOW0#
IDE_IOW1#
D24
AG4
AD2
C28
O
O
IDE I/O Write Channels 0 and 1.
TFTD9
IDE_IOW0# is the write signal for Channel 0.
IDE_IOW1# is the write signal for Channel 1.
Each signal is asserted at write accesses to
corresponding IDE port addresses.
GPIO9+DCD2#+
SDTEST2
IDE_CS0#
IDE_CS1#
A27
C16
AF2
P2
O
O
IDE Chip Selects 0 and 1. These signals are
used to select the command block registers
in an IDE device.
TFTD5
TFTDE
IDE_IORDY0
IDE_IORDY1
A25
AJ1
AD1
B29
I
I
I/O Ready Channels 0 and 1. When de-
asserted, these signals extend the transfer
cycle of any host register access if the
required device is not ready to respond to the
data transfer request.
TFTD11
GPIO10+DSR2#+
SDTEST1
Note: If selected as IDE_IORDY0 or
IDE_IORDY1 function(s) but not
used, then signal(s) should be tied
high.
IDE_DREQ0
IDE_DREQ1
C24
AJ2
AC4
C31
I
I
DMA Request Channels 0 and 1. The
IDE_DREQ signals are used to request a
DMA transfer from the SC1200/SC1201. The
direction of transfer is determined by the
IDE_IOR/IOW signals.
TFTD8
GPIO8+CTS2#
+SDTEST5
Note: If
selected
as
IDE_DREQ0/
IDE_DREQ1 function but not used,
tie IDE_DREQ0/IDE_DREQ1 low.
IDE_DACK0#
IDE_DACK1#
C25
AH4
AD4
C30
O
O
DMA Acknowledge Channels 0 and 1. The
IDE_DACK# signals acknowledge the DREQ
request to initiate DMA transfers.
TFTD0
GPIO7+RTS2#
+SDTEST0
IRQ14
IRQ15
D25
H30
AF1
AJ8
I
I
Interrupt Request Channels 0 and 1.
These input signals are edge-sensitive inter-
rupts that indicate when the IDE device is
requesting a CPU interrupt service.
TFTD1
GPIO11+RI2#
Note: If selected as IRQ14/IRQ15 function
but not used, tie IRQ14/IRQ15 low.
Revision 6.0
73
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Signal Definitions (Continued)
2.4.11 Universal Serial Bus (USB) Interface Signals
Ball No.
Signal Name
EBGA
TEPBGA Type Description
Mux
POWER_EN
B28
AH1
O
Power Enable. This signal enables the
---
power to a self-powered USB hub.
OVER_CUR#
C27
AF4
I
Overcurrent. This signal indicates that the
USB hub has detected an overcurrent on the
USB.
---
DPOS_PORT1
DNEG_PORT1
DPOS_PORT2
DNEG_PORT2
DPOS_PORT3
DNEG_PORT3
AH2
AG3
AH1
AG2
AE4
AF3
A28
A29
B27
B28
A26
A27
I/O
I/O
I/O
I/O
I/O
I/O
USB Port 1 Data Positive for Port 1.
USB Port 1 Data Negative for port 1.
USB Port 2 Data Positive for Port 2.
USB Port 2 Data Negative for Port 2.
USB Port 3 Data Positive for Port 3.
USB Port 3 Data Negative for Port 3.
---
---
---
---
---
---
2.4.12 Serial Ports (UARTs) Interface Signals
Ball No.
Signal Name
EBGA
TEPBGA Type Description
Mux
SIN1
SIN2
SIN3
D26
AJ4
J28
AG2
E28
AK8
I
Serial Inputs. Receive composite serial data
from the communications link (peripheral
device, modem or other data transfer device).
---
SDTEST3
IRRX1
Note: If selected as SIN2 or SIN3 func-
tion(s) but not used, then signal(s)
should be tied high.
SOUT1
SOUT2
SOUT3
B27
AK3
J3
AF3
D29
C11
O
O
Serial Outputs. Send composite serial data
to the communications link (peripheral
device, modem or other data transfer device).
These signals are set active high after a sys-
tem reset.
CLKSEL1 (Strap)
CLKSEL2 (Strap)
IRTX
RTS2#
AH4
C30
Request to Send. When low, indicates to the
modem or other data transfer device that the
corresponding UART is ready to exchange
data. A system reset sets these signals to
inactive high, and loopback operation holds
them inactive.
GPIO7+
IDE_DACK1#
CTS2#
AJ2
C31
I
Clear to Send. When low, indicates that the
modem or other data transfer device is ready
to exchange data.
GPIO8+
IDE_DREQ1
Note: If selected as CTS2# function but not
used, tie CTS2# low.
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74
Revision 6.0
Signal Definitions (Continued)
2.4.12 Serial Ports (UARTs) Interface Signals (Continued)
Ball No.
Signal Name
EBGA
TEPBGA Type Description
Mux
DTR1#/BOUT1
DTR2#/BOUT2
A28
AH3
AG1
D28
O
Data Terminal Ready Outputs. When low,
indicate to the modem or other data transfer
device that the UART is ready to establish a
communications link. After a system reset,
these balls provide the DTR# function and
set these signals to inactive high. Loopback
operation drive them inactive.
GPIO18
GPIO6+IDE_IOR1#
Baud Outputs. Provide the associated serial
channel baud rate generator output signal if
test mode is selected (i.e., bit 7 of the EXCR1
Register is set).
RI2#
H30
AJ8
I
Ring Indicator. When low, indicates to the
modem that a telephone ring signal has been
received by the modem. They are monitored
during power-off for wakeup event detection.
GPIO11+IRQ15
Note: If selected as RI2# function but not
used, tie RI2# high.
DCD2#
DSR2#
AG4
AJ1
C28
B29
I
I
Data Carrier Detected. When low, indicates GPIO9+IDE_IOW1#
that the data transfer device (e.g., modem) is
ready to establish a communications link.
+SDTEST2
Note: If selected as DCD2# function but
not used, tie DCD2# high.
Data Set Ready. When low, indicates that
the data transfer device (e.g., modem) is
ready to establish a communications link.
GPIO10+
IDE_IORDY1
Note: If selected as DSR2# function but not
used, tie DSR2# low.
Revision 6.0
75
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Signal Definitions (Continued)
2.4.13 Parallel Port Interface Signals
Ball No.
Signal Name
EBGA
TEPBGA Type Description
Mux
ACK#
U3
B18
D22
I
Acknowledge. Pulsed low by the printer to
indicate that it has received data from the Par-
allel Port.
TFTDE+VOPCK+
FPCICLK
AFD#/DSTRB#
AB2
O
Automatic Feed. When low, instructs the
printer to automatically feed a line after print-
ing each line. This signal is in TRI-STATE
after a 0 is loaded into the corresponding
control register bit. An external 4.7 KΩ pull-
up resistor should be attached to this ball.
TFTD2+VOPD1+
INTR_O
Data Strobe (EPP). Active low, used in EPP
mode to denote a data cycle. When the cycle
is aborted, DSTRB# becomes inactive (high).
BUSY/WAIT#
T1
B17
I
Busy. Set high by the printer when it cannot
accept another character.
TFTD3+VOPD2+
F_C/BE1#
Wait. In EPP mode, the Parallel Port device
uses this active low signal to extend its
access cycle.
ERR#
INIT#
AA3
Y3
D21
B21
I
Error. Set active low by the printer when it
detects an error.
TFTD4+VOPD3+
F_C/BE0#
O
Initialize. When low, initializes the printer.
This signal is in TRI-STATE after a 1 is
loaded into the corresponding control register
bit. Use an external 4.7 KΩ pull-up resistor.
TFTD5+VOPD4+
SMI_O
PD7
PD6
U1
V3
A18
A20
I/O
Parallel Port Data. Transfer data to and from
the peripheral data bus and the appropriate
Parallel Port data register. These signals
have a high current drive capability.
TFTD13+F_AD7
TFTD1+VOPD0+
F_AD6
PD5
PD4
PD3
PD2
V2
V1
C19
C18
C20
D20
TFTD11+F_AD5
TFTD10+F_AD4
TFTD9+F_AD3
W2
W3
TFTD8+VOPD7+
F_AD2
PD1
PD0
PE
Y1
AA1
T3
A21
C21
D17
TFTD7+VOPD6+
F_AD1
TFTD6+VOPD5+
F_AD0
I
I
Paper End. Set high by the printer when it is TFTD14+F_C/BE2#
out of paper.
This ball has an internal weak pull-up or pull-
down resistor that is programmed by soft-
ware.
SLCT
T4
C17
Select. Set active high by the printer when
TFTD15+F_C/BE3#
the printer is selected.
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76
Revision 6.0
Signal Definitions (Continued)
2.4.13 Parallel Port Interface Signals (Continued)
Ball No.
Signal Name
EBGA
TEPBGA Type Description
Mux
SLIN#/ASTRB#
W1
B20
O
Select Input. When low, selects the printer.
This signal is in TRI-STATE after a 0 is
TFTD16+
F_IRDY#
loaded into the corresponding control register
bit. Uses an external 4.7 KΩ pull-up resistor.
Address Strobe (EPP). Active low, used in
EPP mode to denote an address or data
cycle. When the cycle is aborted, ASTRB#
becomes inactive (high).
STB#/WRITE#
AB1
A22
O
Data Strobe. When low, indicates to the
printer that valid data is available at the
printer port. This signal is in TRI-STATE after
a 0 is loaded into the corresponding control
register bit. An external 4.7 KΩ pull-up resis-
tor should be employed.
TFTD17+
F_FRAME#
Write Strobe. Active low, used in EPP mode
to denote an address or data cycle. When
the cycle is aborted, WRITE# becomes inac-
tive (high).
2.4.14 Fast Infrared (IR) Port Interface Signals
Ball No.
Signal Name
EBGA
TEPBGA Type Description
Mux
IRRX1
J28
AK8
I
IR Receive. Primary input to receive serial
data from the IR transceiver. Monitored dur-
ing power-off for wakeup event detection.
SIN3
Note: If selected as IRRX1 function but not
used, tie IRRX1 high.
IRRX2/GPIO38
AJ9
J3
K28
I
IR Receive 2. Auxiliary IR receiver input to
support a second transceiver. This input sig-
nal can be used when GPIO38 is selected
using PMR[14], and when AUX_IRRX bit in
register IRCR2 of the IR module in internal
SuperI/O is set.
LPCPD#
SOUT3
IRTX
C11
O
IR Transmit. IR serial output data.
2.4.15 AC97 Audio Interface Signals
Ball No.
Signal Name
EBGA
TEPBGA Type Description
Mux
BIT_CLK
AL14
U30
I
Audio Bit Clock. The serial bit clock from
F_TRDY#
the codec.
Note: If selected as BIT_CLK function but
not used, tie BIT_CLK low.
SDATA_OUT
AK13
P29
O
Serial Data Output. This output transmits
audio serial data to the codec.
TFT_PRSNT (Strap)
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Revision 6.0
77
Signal Definitions (Continued)
2.4.15 AC97 Audio Interface Signals (Continued)
Ball No.
Signal Name
EBGA
TEPBGA Type Description
Mux
SDATA_IN
AK14
U31
I
Serial Data Input. This input receives serial
F_GNT0#
data from the primary codec.
Note: If selected as SDATA_IN function but
not used, tie SDATA_IN low.
SDATA_IN2
SYNC
H31
AL8
P30
I
Serial Data Input 2. This input receives
serial data from the secondary codec. This
signal has wakeup capability.
---
AL13
O
Serial Bus Synchronization. This bit is
asserted to synchronize the transfer of data
between the SC1200/SC1201 and the AC97
codec.
CLKSEL3 (Strap)
AC97_CLK
AJ14
AJ15
P31
U29
O
O
Codec Clock. It is twice the frequency of the
Audio Bit Clock.
---
AC97_RST#
Codec Reset. S3 to S5 wakeup is not sup-
ported because AC97_RST# is powered by
VIO. If wakeup from states S3 to S5 are
F_STOP#
needed, a circuit in the system board should
be used to reset the AC97 codec.
PC_BEEP
AL15
V31
O
PC Beep. Legacy PC/AT speaker output.
GPIO16+
F_DEVSEL#
2.4.16 Power Management Interface Signals
Ball No.
Signal Name
EBGA
TEPBGA Type Description
Mux
CLK32
H29
E31
G28
G29
D31
AH8
AH6
AK5
AJ6
AL4
O
32.768 KHz Output Clock
---
---
---
---
---
GPWIO0
GPWIO1
GPWIO2
LED#
I/O
General Purpose Wakeup I/Os. These sig-
nals each have an internal pull-up of 100 KΩ.
O
O
LED Control. Drives an externally connected
LED (on, off or a 1 Hz blink). Sleeping /
Working indicator. This signal is an open-
drain output.
ONCTL#
E30
AJ5
On / Off Control. This signal indicates to the
main power supply that power should be
turned on. This signal is an open-drain out-
put.
---
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78
Revision 6.0
Signal Definitions (Continued)
2.4.16 Power Management Interface Signals (Continued)
Ball No.
Signal Name
EBGA
TEPBGA Type Description
Mux
PWRBTN#
E29
AH5
I
Power Button. Input used by the power
management logic to monitor external sys-
tem events, most typically a system on/off
button or switch.
---
The signal has an internal pull-up of 100 KΩ,
a Schmitt-trigger input buffer and debounce
protection of at least 16 ms.
ACPI is non-functional when the power-up
sequence does not include using the power
button. If ACPI functionality is desired, the
power button must be toggled. This can be
done externally or internally. GPIO63 is inter-
nally connected to PWRBTN#. To toggle the
power button with software, GPIO63 must be
programmed as an output using the normal
GPIO programming protocol (see Section
5.4.1.1 "GPIO Support Registers" on page
236). GPIO63 must be pulsed low for at least
16 ms and not more than 4 sec. Asserting
POR# has no effect on ACPI. If POR# is
asserted and ACPI was active prior to POR#,
then ACPI will remain active after POR#.
Therefore, BIOS must ensure that ACPI is
inactive before GPIO63 is pulsed low.
PWRCNT1
PWRCNT2
F31
G31
AK6
AL7
O
O
Suspend Power Plane Control 1 and 2.
Control signal asserted during power man-
agement Suspend states. These signals are
open-drain outputs.
---
---
THRM#
F28
AK4
I
Thermal Event. Active low signal generated
by external hardware indicating that the sys-
tem temperature is too high.
---
Revision 6.0
79
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Signal Definitions (Continued)
2.4.17 GPIO Interface Signals
Ball No.
Signal Name
EBGA
TEPBGA Type Description
Mux
GPIO0
GPIO1
H1
H2
D11
D10
N30
D28
I/O
GPIO Port 0. Each signal is configured inde-
pendently as an input or I/O, with or without
static pull-up, and with either open-drain or
totem-pole output type.
TRDE#
IOCS1#+TFTD12
AB1D+IOCS1#
AL12
AH3
GPIO6
A debouncer and an interrupt can be enabled
or masked for each of signals GPIO[00:01]
and [06:15] independently.
DTR2#/BOUT2+
IDE_IOR1#+
SDTEST5
Note: GPIO12, GPIO13, GPIO16 inputs: If
GPIOx function is selected but not
used, tie GPIOx low.
GPIO7
GPIO8
GPIO9
GPIO10
AH4
AJ2
AG4
AJ1
C30
C31
C28
B29
RTS2#+IDE_DACK1#
+SDTEST0
CTS2#+IDE_DREQ1
+SDTEST4
DCD2#+IDE_IOW1#+
SDTEST2
DSR2#+IDE_IORDY1
+SDTEST1
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
H30
AJ12
AL11
F1
AJ8
N29
M29
D9
RI2#+IRQ15
AB2C
AB2D
IOR#+DOCR#
IOW#+DOCW#
G3
A8
AL15
V31
PC_BEEP+
F_DEVSEL#
GPIO17
GPIO18
GPIO19
GPIO20
J4
A28
H4
A10
AG1
C9
IOCS0#+TFTDCK
DTR1#/BOUT1
INTC#+IOCHRDY
DOCCS#+TFTD0
AB1C+DOCCS#
LAD0
H3
A9
AJ13
AJ11
AL10
AK10
AJ10
AL9
AK9
AJ9
N31
M28
L31
L30
L29
L28
K31
K28
J31
Y3
GPIO32
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
GPIO38/IRRX2
GPIO39
GPIO40
GPIO41
I/O
GPIO Port 1. Each signal is configured inde-
pendently as an input or I/O, with or without
static pull-up, and with either open-drain or
totem-pole output type.
LAD1
LAD2
A debouncer and an interrupt can be enabled
or masked for each of signals GPIO[32:41]
independently.
LAD3
LDRQ#
LFRAME#
LPCPD#
AL8
A21
C19
SERIRQ
IDE_DATA8
IDE_DATA11
W4
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80
Revision 6.0
Signal Definitions (Continued)
2.4.18 Debug Monitoring Interface Signals
Ball No.
Signal Name
EBGA
TEPBGA Type Description
Mux
FPCICLK
U3
B18
O
Fast-PCI Bus Monitoring Signals. When
enabled, this group of signals provides for
monitoring of the internal Fast-PCI bus for
debug purposes. To enable, pull up
FPCI_MON (EBGA ball D3 / TEPBGA ball
A4).
ACK#+TFTDE+
VOPCK
F_AD7
F_AD6
U1
V3
A18
A20
O
O
PD7+TFTD13
PD6+TFTD1+
VOPD0
F_AD5
F_AD4
F_AD3
F_AD2
V2
V1
C19
C18
C20
D20
O
O
O
O
PD5+TFTD11
PD4+TFTD10
PD3+TFTD9
W2
W3
PD2+TFTD8+
VOPD7
F_AD1
F_AD0
Y1
A21
C21
O
O
PD1+TFTD7+
VOPD6
AA1
PD0+TFTD6+
VOPD5
F_C/BE3#
F_C/BE2#
F_C/BE1#
T4
T3
T1
C17
D17
B17
O
O
O
SLCT+TFTD15
PE+TFTD14
BUSY/WAIT#+
TFTD3+VOPD2
F_C/BE0#
F_FRAME#
F_IRDY#
AA3
AB1
W1
D21
A22
B20
O
O
O
ERR#+TFTD4+
VOPD3
STB#/WRITE#+
TFTD17
SLIN#/ASTRB#+
TFTD16
F_STOP#
AJ15
AL15
U29
V31
O
O
AC97_RST#
F_DEVSEL#
GPIO16+
PC_BEEP
F_GNT0#
F_TRDY#
INTR_O
AK14
AL14
AB2
U31
U30
D22
O
O
O
SDATA_IN
BIT_CLK
CPU Core Interrupt. When enabled, this sig-
nal provides for monitoring of the internal
GX1 core INTR signal for debug purposes.
To enable, pull up FPCI_MON (EBGA ball D3
/ TEPBGA ball A4).
AFD#/DSTRB#+
TFTD2+VOPD1
SMI_O
Y3
B21
O
System Management Interrupt. This is the
input to the GX1 core. When enabled, this
signal provides for monitoring of the internal
GX1 core SMI# signal for debug purposes.
To enable, pull up FPCI_MON (EBGA ball D3
/ TEPBGA ball A4).
INIT#+TFTD5+
VOPD4+
Revision 6.0
81
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Signal Definitions (Continued)
2.4.19 JTAG Interface Signals
Ball No.
Signal Name
EBGA
TEPBGA Type Description
Mux
TCK
AL4
E31
I
JTAG Test Clock. This signal has an internal
---
weak pull-up resistor.
TDI
AK5
F29
I
JTAG Test Data Input. This signal has an
---
internal weak pull-up resistor.
TDO
TMS
AH6
AJ5
E30
F28
O
I
JTAG Test Data Output
---
---
JTAG Test Mode Select. This signal has an
internal weak pull-up resistor.
TRST#
AK4
E29
I
JTAG Test Reset. This signal has an internal
---
weak pull-up resistor.
For normal JTAG operation, this signal
should be active at power-up.
If the JTAG interface is not being used, this
signal can be tied low.
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82
Revision 6.0
Signal Definitions (Continued)
2.4.20 Test and Measurement Interface Signals
Ball No.
Signal Name
EBGA
TEPBGA
Type
Description
Mux
PLL6B
PLL5B
PLL2B
GXCLK
C28
B29
AG4
AJ1
AH3
V30
I/O
I/O
I/O
O
PLL6, PLL5 and PLL2 Bypass. These sig-
nals are used for internal testing only. For
normal operation leave unconnected.
TEST1
TEST2
TEST0
D28
AL16
GX Clock. This signal is for internal testing
only. For normal operation either program as
FP_VDD_ON or leave unconnected.
FP_VDD_ON+
TEST3
TEST3
AL16
V30
O
Internal Test Signals. These signals are
used for internal testing only. For normal
operation, leave unconnected unless pro-
grammed as one of their muxed options.
FP_VDD_ON+
GXCLK
TEST2
TEST1
TEST0
GTEST
B29
C28
D28
AL5
AJ1
AG4
AH3
F30
O
O
O
I
PLL5B
PLL6B
PLL2B
---
Global Test. This signal is used for internal
testing only. For normal operation this signal
should be pulled down with 1.5 KΩ.
SDTEST5
SDTEST4
AH3
AJ2
D28
C31
O
O
Memory Internal Test Signals. These sig-
nals are used for internal testing only. For
normal operation, these signals should be
programmed as one of their muxed options.
GPIO6+
DTR2#/BOUT2+
IDE_IOR1#
GPIO8+CTS2#+
IDE_DREQ1
SDTEST3
SDTEST2
AJ4
E28
C28
O
O
SIN2
AG4
GPIO9+DCD2#+
IDE_IOW1#
SDTEST1
SDTEST0
AJ1
B29
C30
O
O
GPIO10+DSR2#
+IDE_IORDY1
AH4
GPIO7+RTS2#+
IDE_DACK1#
TDP
TDN
AH5
AL3
D30
D31
I/O
I/O
Thermal Diode Positive / Negative. These
signals are for internal testing only. For nor-
mal operation leave unconnected.
---
---
Revision 6.0
83
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Signal Definitions (Continued)
2.4.21 Power and Ground Connections1
Ball No.
Signal Name
AVSSPLL2
AVSSPLL3
VPLL2
EBGA
R3
TEPBGA
C16
Type Description
GND Analog PLL2 Ground Connection.
GND Analog PLL3 Ground Connection.
E28
R1
AK3
A17
PWR 3.3V PLL2 Analog Power Connection. Low noise
power for PLL2 and PLL5.
VPLL3
C31
AF4
AJ4
D27
PWR 3.3V PLL3 Analog Power Connection. Low noise
power for PLL3, PLL4, and PLL6.
AVCCUSB
PWR 3.3V Analog USB Power Connection. Low noise
power for USB.
AVSSUSB
AVCCCRT
AG1
C27
GND Analog USB Ground Connection.
L3, M1, N1
A12, C13, D15
PWR 3.3V Analog CRT DAC Power Connections. Low
noise power.
AVSSCRT
VCCCRT
L1, N3, P3
K3
B14, C14, C15
D12
GND Analog CRT DAC Ground Connections. Return
current.
PWR 1.8V CRT DAC Digital Power Connection. Can be
directly connected to VCORE on PCB (printed circuit
board).
VSSCRT
K2
C12
D23
GND CRT DAC Digital Ground Connection. Can be
directly connected to VSS on PCB.
AVCCTV
AC3
PWR 3.3V Analog TV DAC Power Connection. Low noise
power.
AVSSTV
VBAT
AC4
D30
B24
AL3
GND Analog TV DAC Ground Connection. Return current.
PWR Battery. Provides battery back-up to the RTC and
ACPI registers, when VSB is lower than the minimum
value (see Table 8-2 on page 372). The ball is con-
nected to the internal logic through a series resistor for
UL protection.
VSB
F29
H28
AL5
AL6
PWR 3.3V Standby Power Supply. Provides power to the
Real-Time Clock (RTC) and ACPI circuitry while the
main power supply is turned off.
VSBL
PWR 1.8V Standby Power Supply. Provides power to the
internal logic while the main power supply is turned off.
This signal requires a 0.1 µF bypass capacitor to VSS
.
This supply must be present when VSB is present.
VCORE
Refer to Table
2-3 on page 34
(Total of 25)
See Table 2-5
on page 50
(Total of 28)
PWR 1.8V Core Processor Power Connections.
VIO
Refer to Table
2-3 on page 34
(Total of 31)
See Table 2-5
on page 50
(Total of 42)
PWR 3.3V I/O Power Connections.
GND Ground Connections.
VSS
Refer to Table
2-3 on page 34
(Total of 56)
See Table 2-5
on page 50
(Total of 91)
1. All power sources must be connected, even if the function is not used
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84
Revision 6.0
3.0 General Configuration Block
The General Configuration block includes registers for:
After system reset, the Base Address register is located at
I/O address 02EAh. This address can be used only once.
Before accessing any PCI registers, the BOOT code must
program this 16-bit register to the I/O base address for the
General Configuration block registers. All subsequent
writes to this address, are ignored until system reset.
• Pin Multiplexing and Miscellaneous Configuration
• WATCHDOG Timer
• High-Resolution Timer
• Clock Generators
Note: Location of the General Configuration Block cannot
be
determined
by
software.
See
the
A selectable interrupt is shared by all these functions.
SC1200/SC1201 Set-Top Box On a Chip device
errata document.
3.1 CONFIGURATION BLOCK ADDRESSES
Registers of the General Configuration block are I/O
mapped in a 64-byte address range. These registers are
physically connected to the internal Fast-PCI bus, but do
not have a register block in PCI configuration space (i.e.,
they do not appear to software as PCI registers).
Reserved bits in the General Configuration block should
read as written unless otherwise specified.
Table 3-1. General Configuration Block Register Summary
Width
(Bits)
Offset
Type
Name
Reset Value
Reference
00h-01h
02h-03h
04h
16
16
8
R/W
R/W
R/WC
---
WDTO. WATCHDOG Timeout
WDCNFG. WATCHDOG Configuration
WDSTS. WATCHDOG Status
RSVD. Reserved
0000h
Page 94
Page 94
Page 95
---
0000h
00h
05h-07h
08h-0Bh
0Ch
---
32
8
---
RO
R/W
R/W
---
TMVALUE. TIMER Value
TMSTS. TIMER Status
xxxxxxxxh
Page 96
Page 96
Page 96
---
00h
0Dh
8
TMCNFG. TIMER Configuration
RSVD. Reserved
00h
0Eh-0Fh
10h
---
8
---
RO
---
MCCM. Maximum Core Clock Multiplier
RSVD. Reserved
Strapped Value
Page 101
---
11h
---
8
---
12h
R/W
---
PPCR. PLL Power Control
RSVD. Reserved
2Fh
Page 101
---
13h-17h
18h-1Bh
1Ch-1Dh
1Eh-1Fh
20h-2Fh
30h-33h
34h-37h
38h
---
32
---
16
---
32
32
8
---
E1040005h
---
R/W
---
PLL3C. PLL3 Configuration
RSVD. Reserved
Page 101
---
R/W
---
CCFC. Core Clock Frequency Control
RSVD. Reserved
Strapped Value
---
Page 102
---
R/W
R/W
R/W
---
PMR. Pin Multiplexing Register
MCR. Miscellaneous Configuration Register
INTSEL. Interrupt Selection
RSVD. Reserved
00000000h
00000001h
00h
Page 86
Page 90
Page 92
---
39h-3Bh
3Ch
---
8
---
RO
RO
RO
IID. IA On a Chip ID
xxh
Page 92
Page 92
Page 92
3Dh
8
REV. Revision
xxh
3Eh-3Fh
16
CBA. Configuration Base Address
xxxxh
Revision 6.0
85
www.national.com
General Configuration Block (Continued)
3.2 MULTIPLEXING, INTERRUPT SELECTION, AND BASE ADDRESS REGISTERS
The registers described inTable 3-2 are used to determine
general configuration for the SC1200/SC1201. These reg-
isters also indicate which multiplexed signals are issued via
balls from which more than one signal may be output. For
more information about multiplexed signals and the appro-
priate configurations, see Section 2.1 "Ball Assignments"
on page 21.
Table 3-2. Multiplexing, Interrupt Selection, and Base Address Registers
Bit
Description
Offset 30h-33h
Pin Multiplexing Register - PMR (R/W)
Reset Value: 00000000h
This register configures pins with multiple functions. See Section 2.1 on page 21 for more information about multiplexing information.
31:30
29
Reserved: Always write 0.
Test Signals. Selects ball functions.
Ball #
0: Internal Test Signals
1: Internal Test Signals
EBGA / TEPBGA Name
Add’l Dependencies
Name
Add’l Dependencies
D28 / AH3
C28 / AG4
B29 / AJ1
AL16 / V30
PLL2B
PLL6B
PLL5B
GXCLK
None
TEST0
TEST1
TEST2
TEST3
None
None
None
None
None
See PMR[23]
PMR[23] = 0
28
27
Test Signals. Selects ball function.
Ball # 0: AC97 Signal
EBGA / TEPBGA Name
AJ4 / E28 SIN2
1: Internal Test Signal
Add’l Dependencies
Name
Add’l Dependencies
None
SDTEST3
See Note.
Note: If this bit is set, PMR[8] and PMR[18] must be set by software.
FPCI_MON (Fast-PCI Monitoring). Selects Fast-PCI monitoring output signals instead of Parallel Port signals.
Fast-PCI monitoring output signals can be enabled in two ways: by setting this bit to 1 or by strapping FPCI_MON (EBGA
ball D3 / TEPBGA ball A4) high. (The strapped value can be read back at MCR[30].) Listed below is how these two options
work together and the signals that are enabled (enabling overrides add’l dependencies except FPCI_MON = 1). Note that
the FPCI monitoring signals that are muxed with Audio signals are not enabled via this bit. They are only enabled using the
strap option.
PMR[27] FPCI_MON
0
0
1
1
0
1
0
1
Disable all Fast-PCI monitoring signals
Enable all Fast-PCI monitoring signals
Enable Fast-PCI monitoring signals muxed with Parallel Port signals only
Enable all Fast-PCI monitoring signals
Ball #
EBGA / TEPBGA FPCI_MON Signal Other Signal
Add’l Dependencies
U3 / B18
U1 / A18
V3 / A20
V2 / C19
V1 / C18
W2 / C20
W3 / D20
Y1 / A21
AA1 / C21
T4 / C17
T3 / D17
T1 / B17
AA3 / D21
AB1 / A22
W1 / B20
AB2 / D22
Y3 / B21
FPCICLK
F_AD7
F_AD6
F_AD5
F_AD4
F_AD3
F_AD2
F_AD1
F_AD0
F_C/BE3#
F_C/BE2#
F_C/BE1#
F_C/BE0#
F_FRAME#
F_IRDY#
INTR_O
SMI_O
ACK#+TFTDE+VOPCK
PD7+TFTD13
PD6+TFTD1+VOPCK
PD5+TFT11
PD4+TFTD10
PD3+TFTD9
PD2+TFTD8+VOPD7
PD1+TFTD7+VOPD6
PD0_TFTD5+VOPD6
SLCT+TFTD15
See PMR[23]
See PMR[23]
See PMR[23]
See PMR[23]
See PMR[23]
See PMR[23]
See PMR[23]
See PMR[23]
See PMR[23]
See PMR[23]
See PMR[23]
See PMR[23]
See PMR[23]
See PMR[23]
See PMR[23]
See PMR[23]
See PMR[23]
PE+TFTD14
BUSY/WAIT#+TFTD3+VOPD2
ERR#+TFTD4+VOPD3
STB#/WRITE#+TFTD7
SLIN#/ASTRB#+TFTD16
AFD#/DSTRB#+TFTD2+VOPD1
INIT#+TFTD5+VOPD4
AL15 / V31
AJ15 / U29
AK14 / U31
AL14 / U30
F_DEVSEL#
F_STOP#
F_GNT0#
F_TRDY#
GPIO16+PC_BEEP
AC97_RST#
SDATA_IN
FPCI_MON = 1 and see PMR[0]
FPCI_MON = 1
FPCI_MON = 1
BIT_CLK
FPCI_MON = 1
26
Note: Reserved: Always write 0.
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86
Revision 6.0
General Configuration Block (Continued)
Table 3-2. Multiplexing, Interrupt Selection, and Base Address Registers (Continued)
Bit
Description
25
AC97CKEN (Enable AC97_CLK Output). This bit enables the output drive of AC97_CLK (EBGA ball AJ14 / TEPBGA ball
P31).
0: AC97_CLK output is HiZ.
1: AC97_CLK output is enabled.
24
TFTIDE (TFT/IDE). Determines whether certain balls are used for TFT signals or for IDE signals. Note that there are no
additional dependencies.
Ball #
0: IDE Signals
1: CRT, GPIO and TFT Signals
EBGA / TEPBGA Name
Name
A26 / AD3
C26 / AE1
C17 / U2
B24 / AC3
A24 / AC1
D23 / AC2
C23 / AB4
B23 / AB1
A23 / AA4
C22 / AA3
B22 / AA2
A21 / Y3
IDE_ADDR0
TFTD3
IDE_ADDR1
IDE_ADDR2
IDE_DATA0
IDE_DATA1
IDE_DATA2
IDE_DATA3
IDE_DATA4
IDE_DATA5
IDE_DATA6
IDE_DATA7
IDE_DATA8
IDE_DATA9
IDE_DATA10
IDE_DATA11
IDE_DATA12
IDE_DATA13
IDE_DATA14
IDE_DATA15
IDE_CS0#
TFTD2
TFTD4
TFTD6
TFTD16
TFTD14
TFTD12
FP_VDD_ON
CLK27M
IRQ9
INTD#
GPIO40
DDC_SDA
DDC_SCL
GPIO41
TFTD13
TFTD15
TFTD17
TFTD7
C20 / Y2
A20 / Y1
C19 / W4
B19 / W3
A19 / V3
C18 / V2
B18 / V1
A27 / AF2
C16 / P2
TFTD5
IDE_CS1#
TFTDE
C21 / Y4
IDE_IOR0#
IDE_IOW0#
IDE_DREQ0
IDE_DACK0#
IDE_RST#
TFTD10
TFTD9
D24 / AD2
C24 / AC4
C25 / AD4
A22 / AA1
A25 / AD1
D25 / AF1
TFTD8
TFTD0
TFTDCK
TFTD11
TFTD1
IDE_IORDY0
IRQ14
Revision 6.0
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General Configuration Block (Continued)
Table 3-2. Multiplexing, Interrupt Selection, and Base Address Registers (Continued)
Bit
Description
23
TFTPP (TFT/Parallel Port). Determines whether certain balls are used for TFT/VOP or PP/ACB1. This bit is set to 1 at
power-on if the TFT_PRSNT strap (EBGA ball AK13 / TEPBGA ball P29) is pulled high.
Ball #
0: PP/ACB1/FPCI
1: TFT/VOP
Name
EBGA / TEPBGA Name
Add’l Dependencies
Add’l Dependencies
H2 / D10
H3 / A9
J4 / A10
GPIO1
IOCS1#
PMR[13] = 0
PMR[13] = 1
TFTD12
GPIO1
IOCS1#
PMR[15] = 0
PMR[15] = 1 and PMR[13] = 0
PMR[15] = 1 and PMR[13] = 1
GPIO20
DOCCS#
PMR[7] = 0
PMR[7] = 1
TFTD0
GPIO20
DOCCS#
PMR[15] = 0
PMR[15] = 1 and PMR[7] = 0
PMR[15] = 1 and PMR[7] = 1
GPIO17
IOCS0#
PMR[5] = 0
PMR[5] = 1
TFTDCK
GPIO17
IOCS0#
PMR[15] = 0
PMR[15] = 1 and PMR[5] = 0
PMR[15] = 1 and PMR[5] = 1
T1 / B17
T3 / D17
T4 / C17
U1 / A18
U3 / B18
V1 / C18
V2 / C19
V3 / A20
W1 / B20
W2 / C20
W3 / D20
Y1 / A21
Y3 / B21
AA1 / C21
AA3 / D21
AB1 / A22
AB2 / D22
AJ13 / N31
BUSY/WAIT#
F_C/BE1#
Note 1
Note 2
TFTD3
VOPD2
PMR[15] = 0 and Note 1
PMR[15] = 1 and Note 1
PE
F_C/BE2#
Note 1
Note 2
TFTD14
TFTD15
TFTD13
Note 1
Note 1
Note 1
SLCT
F_C/BE3#
Note 1
Note 2
PD7
F_AD7
Note 1
Note 2
ACK#
FPCICLK
Note 1
Note 2
TFTDE
VOPCK
PMR[15] = 0 and Note 1
PMR[15] = 1 and Note 1
PD4
F_AD4
Note 1
Note 2
TFTD10
Note 1
PD5
F_AD5
Note 1
Note 2
TFTD11
Note 1
PD6
F_AD6
Note 1
Note 2
TFTD1
VOPD0
PMR[15] = 0 and Note 1
PMR[15] = 1 and Note 1
SLIN#/ASTRB#
F_IRDY#
Note 1
Note 2
TFTD16
Note 1
PD3
F_AD3
Note 1
Note 2
TFTD9
Note 1
PD2
F_AD2
Note 1
Note 2
TFTD8
VOPD7
PMR[15] = 0 and Note 1
PMR[15] = 1 and Note 1
PD1
F_AD1
Note 1
Note 2
TFTD7
VOPD6
PMR[15] = 0 and Note 1
PMR[15] = 1 and Note 1
INIT#
SMI_O
Note 1
Note 2
TFTD5
VOPD4
PMR[15] = 0 and Note 1
PMR[15] = 1 and Note 1
PD0
F_AD0
Note 1
Note 2
TFTD6
VOPD5
PMR[15] = 0 and Note 1
PMR[15] = 1 and Note 1
ERR#
F_C/BE0#
Note 1
Note 2
TFTD4
VOPD3
PMR[15] = 0 and Note 1
PMR[15] = 1 and Note 1
STB#/WRITE#
F_FRAME#
Note 1
Note 2
TFTD17
None
AFD#/DSTRB#
INTR_O
Note 1
Note 2
TFTD2
VOPD1
PMR[15] = 0 and Note 1
PMR[15] = 1 and Note 1
AB1C
None
GPIO20
DOCCS#
AB1C
PMR[15] = 0 and PMR[7] = 0
PMR[15] = 0 and PMR[7] = 1
PMR[15] = 1 (Note 3)
AL12 / N30
AL16 / V30
AB1D
None
GPIO1
IOCS1#
AB1D
PMR[15] = 0 and PMR[13] = 0
PMR[15] = 0 and PMR[13] = 1
PMR[15] = 1
GXCLK
TEST3
PMR[29] = 0
PMR[29] = 1
FP_VDD_ON
GXCLK
PMR[15] = 0
PMR[15] = 1
Note: 1. PMR[27] = 0 and FPCI_MON = 0
2. PMR[27] = 1 or FPCI_MON = 1
3. ACCESS.bus interface 1 is not available if PMR[23] = 1 and PMR[15] = 0.
4. If FPCI_MON strap is enabled, the TFT_PRSNT strap should be pulled low.
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Revision 6.0
General Configuration Block (Continued)
Table 3-2. Multiplexing, Interrupt Selection, and Base Address Registers (Continued)
Bit
Description
22
RSVD (Reserved). Must be set equal to PMR[14] (LPCSEL). The LPC_ROM strap (EBGA ball E4 / TEPBGA ball D6) deter-
mines the power-on reset (POR) state of PMR[14] and PMR[22].
21
IOCSEL (Select I/O Commands). Selects ball functions.
Ball #
0: I/O Command Signals
1: GPIO Signals
Name
EBGA / TEPBGA Name
Add’l Dependencies
Add’l Dependencies
F1 / D9
G3 / A8
IOR#
DOCR#
PMR[2] = 0
PMR[2] = 1
GPIO14
Undefined
PMR[2] = 1
PMR[2] = 0
IOW#
DOCW#
PMR[2] = 0
PMR[2] = 1
GPIO15
Undefined
PMR[2] = 1
PMR[2] = 0
20
19
Reserved. Must be set to 0.
AB2SEL (Select ACCESS.bus 2). Selects ball functions.
Ball # 0: GPIO Signals
EBGA / TEPBGA Name
1: ACCESS.bus 2 Signals
Add’l Dependencies
Name
AB2C
AB2D
Add’l Dependencies
AJ12 / N29
AL11 / M29
GPIO12
GPIO13
None
None
None
None
18
SP2SEL (Select SP2 Additional Pins). Selects ball functions.
Ball # 0: GPIO, IDE Signals
EBGA / TEPBGA Name
1: Serial Port Signals
Add’l Dependencies
Name
Add’l Dependencies
AH3 / D28
AG4 / C28
AJ1 / B29
H30 / AJ8
GPIO6
IDE_IOR1#
PMR[8] = 0
PMR[8] = 1
DTR2#/BOUT2
SDTEST5
PMR[8] = 0
PMR[8] = 1
GPIO9
IDE_IOW1#
PMR[8] = 0
PMR[8] = 1
DCD2#
SDTEST2
PMR[8] = 0
PMR[8] = 1
GPIO10
IDE_IORDY1
PMR[8] = 0
PMR[8] = 1
DSR2#
SDTEST1
PMR[8] = 0
PMR[8] = 1
GPIO11
IRQ15
PMR[8] = 0
PMR[8] = 1
RI2#
Undefined
PMR[8] = 0
PMR[8] = 1
17
SP2CRSEL (Select SP2 Flow Control). Selects ball functions.
Ball # 0: GPIO, IDE Signals
EBGA / TEPBGA Name
1: Serial Port Signals
Add’l Dependencies
Name
Add’l Dependencies
AH4 / C30
GPIO7
IDE_DACK1#
PMR[8] = 0
PMR[8] = 1
RTS2#
SDTEST0
PMR[8] = 0
PMR[8] = 1
AJ2 / C31
GPIO8
IDE_DREQ1
PMR[8] = 0
PMR[8] = 1
CTS2#
SDTEST4
PMR[8] = 0
PMR[8] = 1
16
SP1SEL (Select SP1 Additional Pin). Selects ball function.
Ball # 0: GPIO Signal
EBGA / TEPBGA Name
A28 / AG1 GPIO18
1: Serial Port Signal
Name
Add’l Dependencies
Add’l Dependencies
None
DTR1#/BOUT1
None
15
14
VOPS (Video Output Port Select). Select VOP signals instead of TFT signals. Works in conjunction with PMR[23], see
PMR[23] for definition.
LPCSEL (Select LPC Bus). Selects ball functions. The LPC_ROM strap (EBGA ball E4 / TEPBGA ball D6) determines the
power-on reset (POR) state of PMR[14] and PMR[22].
Ball #
0: GPIO Signals
1: LPC Signals
Name
EBGA / TEPBGA Name
Add’l Dependencies
PMR[22] = 0
PMR[22] = 0
PMR[22] = 0
PMR[22] = 0
PMR[22] = 0
PMR[22] = 0
PMR[22] = 0
PMR[22] = 0
Add’l Dependencies
PMR[22] = 1
PMR[22] = 1
PMR[22] = 1
PMR[22] = 1
PMR[22] = 1
PMR[22] = 1
PMR[22] = 1
PMR[22] = 1
AJ11 / M28
AL10 / L31
AK10 / L30
AJ10 / L29
AL9 / L28
AK9 / K31
AJ9 / K28
AL8 / J31
GPIO32
LAD0
GPIO33
LAD1
GPIO34
LAD2
GPIO35
LAD3
GPIO36
LDRQ#
LFRAME#
LPCPD#
SERIRQ
GPIO37
GPIO38/IRRX2
GPIO39
13
IOCS1SEL (Select IOCS1). Selects ball functions for IOCS1# or GPIO1. Works in conjunction with PMR[23], see PMR[23]
for definition.
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General Configuration Block (Continued)
Table 3-2. Multiplexing, Interrupt Selection, and Base Address Registers (Continued)
Bit
Description
12
TRDESEL (Select TRDE#). Selects ball function.
Ball #
EBGA / TEPBGA Name
H1 / D11 TRDE#
0: Sub-ISA Signal
1: GPIO Signal
Name
Add’l Dependencies
Add’l Dependencies
None
GPIO0
None
11
10
EIDE (Enable IDE Outputs). This bit enables IDE output signals.
0: IDE signals are HiZ. Other signals multiplexed on the same balls are HiZ until this bit is set. (without regard to bit 24 of
this register). This bit does not control IDE channel 1 control signals selected by bit 8 of this register.
1: Signals are enabled.
ETFT (Enable TFT Outputs). This bit enables TFT output signals, that are multiplexed with the Parallel Port and controlled
by PMR[23].
0: Signals TFTD[17:0], TFTDE and TFTDCK are set to 0.
1: Signals TFTD[17:0], TFTDE and TFTDCK are enabled.
Note: TFTDCK that is multiplexed on IDE_RST# (EBGA ball A22 / TEPBGA ball AA1) is also enabled by this bit.
IOCHRDY (Select IOCHRDY). Selects ball function.
9
Ball #
0: PCI, GPIO Signal
1: Sub-ISA Signal
Name
EBGA / TEPBGA Name
Add’l Dependencies
Add’l Dependencies
H4 / C9
GPIO19
INTC#
PMR[4] = 0
PMR[4] = 1
IOCHRDY
Undefined
PMR[4] = 1
PMR[4] = 0
8
7
6
IDE1SEL (Select IDE Channel 1). Selects IDE Channel 1 or GPIO ball functions. Works in conjunction with PMR[18] and
PMR[17], see PMR[18] and PMR[17] for definitions.
DOCCSSEL (Select DOCCS#). Selects DOCCS# or GPIO20 ball functions. Works in conjunction with PMR[23], see
PMR[23] for definition.
SP3SEL (Select UART3). Selects ball functions.
Ball #
0: IR Signals
1: Serial Port Signals
EBGA / TEPBGA Name
Add’l Dependencies
Name
Add’l Dependencies
J28 / AK8
J3 / C11
IRRX1
IRTX
None
None
SIN3
None
None
SOUT3
5
4
3
2
IOCS0SEL (Select IOCS0#). Selects ball function. Works in conjunction with PMR[23], see PMR[23] for definition.
INTCSEL (Select INTC#). Selects ball function. Works in conjunction with PMR[9], see PMR[9] for definition.
Reserved. Write as read.
DOCWRSEL (Select DiskOnChip and NAND Flash Command Lines). Selects ball functions. Works in conjunction with
PMR[21], see PMR[21] for definition.
1
0
Reserved. Write as read.
PCBEEPSEL (Select PC_BEEP). Selects ball function.
Ball #
0: GPIO Signal
1: Audio Signal
Name
EBGA / TEPBGA Name
Add’l Dependencies
Add’l Dependencies
AL15 / V31
GPIO16
F_DEVSEL#
FPCI_MON = 0
FPCI_MON = 1
PC_BEEP
F_DEVSEL#
FPCI_MON] = 0
FPCI_MON = 1
Offset 34h-37h
Miscellaneous Configuration Register - MCR (R/W)
Reset Value: 0000001h
Power-on reset value: The BOOT16 strap pin selects "Enable 16-Bit Wide Boot Memory".
31
30
DID0 (EBGA Ball D4 / TEPBGA Ball C5) Strap Status. (Read Only) Represents the value of the strap that is latched after
power-on reset. Read in conjunction with bit 29.
FPCI_MON (EBGA Ball D3 / TEPBGA Ball A4) Strap Status. (Read Only) Represents the value of the strap that is
latched after power-on reset. Indicates if Fast-PCI monitoring output signals (instead of Parallel Port and some audio sig-
nals) are enabled. The state of this bit along with PMR[27] control the Fast-PCI monitoring function. See PMR[27] definition.
29
DID1 (EBGA Ball D2 / TEPBGA Ball C6) Strap Status. (Read Only) Represents the value of the strap that is latched after
power-on reset. Read in conjunction with bit 31.
28:20
19:18
Reserved
PLL1 and TV Encoder Clock Frequency. PLL1 supplies the clock for the TV Encoder.
00: TV Encoder clock is 27 MHz from crystal oscillator. PLL1 is powered down.
01: TV Encoder clock is PLL1 output. PLL1 output is 27 MHz.
10: TV Encoder clock is PLL1 output. PLL1 output is 24.545454 MHz.
11: TV Encoder clock is PLL1 output. PLL1 output is 29.5 MHz.
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Revision 6.0
General Configuration Block (Continued)
Table 3-2. Multiplexing, Interrupt Selection, and Base Address Registers (Continued)
Bit
Description
17
HSYNC Timing. HSYNC timing control for TFT.
0: HSYNC timing suited for CRT.
1: HSYNC timing suited for TFT.
16
Delay HSYNC. HSYNC delay by two TFT clock cycles.
0: There is no delay on HSYNC.
1: HYSNC is delayed twice by rising edge of TFT clock. Enables delay between VSYNC and HSYNC suited for TFT dis-
play.
15
14
Reserved. Write as read.
IBUS16 (Invert BUS16). This bit inverts the meaning of MCR[3] (bit 3 of this register).
0: BUS16 is as described for MCR[3].
1: BUS16 meaning is inverted: if MCR[3] = 0, ROMCS# access is 16 bits wide; if MCR[3] = 1, ROMCS# access is 8 bits
wide.
13
12
Reserved. Must be set to 0.
IO1ZWS (Enable ZWS# for IOCS1# Access). This bit enables internal activation of ZWS# (Zero Wait States) control for
IOCS1# access.
0: ZWS# is not active for IOCS1# access.
1: ZWS# is active for IOCS1# access.
11
10
9
IO0ZWS (Enable ZWS# for IOCS0# Access). This bit enables internal activation of ZWS# (Zero Wait States) control for
IOCS0# access.
0: ZWS# is not active for IOCS0# access.
1: ZWS# is active for IOCS0# access.
DOCZWS (Enable ZWS# for DOCCS# Access). This bit enables internal activation of ZWS# (Zero Wait States) control for
DOCCS# access.
0: ZWS# is not active for DOCCS# access.
1: ZWS# is active for DOCCS# access.
ROMZWS (Enable ZWS# for ROMCS# Access). This bit enables internal activation of ZWS# (Zero Wait States) control for
ROMCS# access.
0: ZWS# is not active for ROMCS# access.
1: ZWS# is active for ROMCS# access.
8
7
6
IO1_16 (Enable 16-Bit Wide IOCS1# Access). This bit enables the16-line access to IOCS1# in the Sub-ISA interface.
0: 8-bit wide IOCS1# access is used.
1: 16-bit wide IOCS1# access is used.
IO0_16 (Enable 16-Bit Wide IOCS0# Access). This bit enables the 16-line access to IOCS0# in the Sub-ISA interface.
0: 8-bit wide IOCS0# access is used.
1: 16-bit wide IOCS0# access is used.
DOC16 (Enable 16-Bit Wide DOCCS# Access). This bit enables the 16-line access to DOCCS# in the Sub-ISA interface.
0: 8-bit wide DOCCS# access is used.
1: 16-bit wide DOCCS# access is used.
5
4
Reserved. Write as read.
IRTXEN (Infrared Transmitter Enable). This bit enables drive of Infrared transmitter output.
0: IRTX+SOUT3 line (EBGA ball J3 / TEPBGA ball C11) is HiZ.
1: IRTX+SOUT3 line (EBGA ball J3 / TEPBGA ball C11) is enabled.
3
BUS16 (16-Bit Wide Boot Memory). (Read Only) This bit reports the status of the BOOT16 strap (EBGA ball G4 / TEP-
BGA ball C8). If the BOOT16 strap is pulled high, at reset 16-bit access to ROM in the Sub-ISA interface is enabled.
MCR[14] = 1 inverts the meaning of this register.
0: 8-bit wide ROM.
1: 16-bit wide ROM.
Reserved. Write as read.
2:1
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General Configuration Block (Continued)
Table 3-2. Multiplexing, Interrupt Selection, and Base Address Registers (Continued)
Bit
Description
0
SDBE0 (Slave Disconnect Boundary Enable). Works in conjunction with the GX1 module’s PCI Control Function 2 Regis-
ter (Index 41h), bit 1 (SDBE1). Sets boundaries for when the GX1 module is a PCI slave.
SDBE[1:0]
00: Read and Write disconnect on boundaries set by bits [3:2] of the GX1 module’s PCI Control Function 2 register (Index
41h).
01: Write disconnects on boundaries set by bits [3:2] of the GX1 module’s PCI Control Function 2 register. Read discon-
nects on cache line boundary of 16 bytes.
1x: Read and Write disconnect on cache line boundary of 16 bytes.
This bit is reset to 1.
All PCI bus masters (including SC1200/SC1201’s on-chip PCI bus masters, e.g., the USB Controller) must be disabled while
modifying this bit. When accessing this register while any PCI bus master is enabled, use read-modify-write to ensure these
bit contents are unchanged.
Offset 38h
Interrupt Selection Register - INTSEL (R/W)
Reset Value: 00h
This register selects the IRQ signal of the combined WATCHDOG and High-Resolution timer interrupt. This interrupt is shareable with
other interrupt sources.
7:4
3:0
Reserved. Write as read.
CBIRQ. Configuration Block Interrupt.
0000: Disable
0001: IRQ1
0100: IRQ4
1000: IRQ8#
1001: IRQ9
1010: IRQ10
1011: IRQ11
1100: IRQ12
1101: Reserved
1110: IRQ14
1111: IRQ15
0101: IRQ5
0110: IRQ6
0111: IRQ7
0010: Reserved
0011: IRQ3
Offset 39h-3Bh
Reserved - RSVD
Offset 3Ch
IA On a Chip Identification Number Register - IID (RO)
Reset Value: xxh
This register identifies the IA On a Chip device. SC1200 = 04h. SC1201 = 05h.
Offset 3Dh
Revision Register - REV (RO)
Reset Value: xxh
Reset Value: xxh
This register identifies the device revision. See device errata for value.
Offset 3Eh-3Fh
Configuration Base Address Register - CBA (RO)
This register sets the base address of the Configuration block.
15:6
5:0
Configuration Base Address. These bits are the high bits of the Configuration Base Address.
Configuration Base Address. These bits are the low bits of the Configuration Base Address. These bits are set to 0.
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Revision 6.0
General Configuration Block (Continued)
3.3 WATCHDOG
The SC1200/SC1201 includes a WATCHDOG function to
serve as a fail-safe mechanism in case the system
becomes hung. When triggered, the WATCHDOG mecha-
nism returns the system to a known state by generating an
interrupt, an SMI, or a system reset (depending on configu-
ration).
• The GX1 module’s internal SUSPA# signal is 1.
or
• The GX1 module’s internal SUSPA# signal is 0 and the
WD32KPD bit (Offset 02h[8]) is 0.
The 32 KHz input clock is disabled, when:
3.3.1 Functional Description
• The GX1 module’s internal SUSPA# signal is 0 and the
WATCHDOG is enabled when the WATCHDOG Timeout
(WDTO) register (Offset 00h) is set to a non-zero value.
The WATCHDOG timer starts with this value and counts
down until either the count reaches 0, or a trigger event
restarts the count (with the WDTO register value).
WD32KPD bit is 1.
For more information about signal SUSPA#, refer to the
GX1 Processor Series Datasheet.
When the WATCHDOG timer reaches 0:
The WATCHDOG timer is restarted in any of the following
cases:
• If the WDOVF bit in the WDSTS register (Offset 04h[0])
is 0, an interrupt, an SMI or a system reset is generated,
depending on the value of the WDTYPE1 field in the
WDCNFG register (Offset 02h[5:4]).
• The WDTO register is set with a non-zero value.
• The WATCHDOG timer reaches 0 and the WATCHDOG
Overflow bit, WDOVF (Offset 04h[0]), is 0.
• If the WDOVF bit in the WDSTS register is already 1
when the WATCHDOG timer reaches 0, an interrupt, an
SMI or a system reset is generated according to the
WDTYPE2 field (Offset 02h[7:6]), and the timer is
disabled. The WATCHDOG timer is re-enabled when a
non-zero value is written to the WDTO register (Offset
00h).
The WATCHDOG function is disabled in any of the follow-
ing cases:
• System reset occurs.
• The WDTO register is set to 0.
• The WDOVF bit is already 1 when the timer reaches 0.
The interrupt or SMI is de-asserted when the WDOVF bit is
set to 0. The reset generated by the WATCHDOG function
is used to trigger a system reset via the Core Logic mod-
ule. The value of the WDOVF bit, the WDTYPE1 field, and
the WDTYPE2 field are not affected by a system reset
(except when generated by power-on reset).
3.3.1.1 WATCHDOG Timer
The WATCHDOG timer is a 16-bit down counter. Its input
clock is a 32 KHz clock divided by a predefined value (see
WDPRES field, Offset 02h[3:0]). The 32 KHz input clock is
enabled when either:
The SC1200/SC1201 also allows no action to be taken
when the timer reaches 0 (according to WDTYPE1 field
and WDTYPE2 field). In this case only the WDOVF bit is
set to 1.
Internal Fast-PCI Bus
WATCHDOG
WDTO
SUSPA#
32 KHz
POR#
WDPRES
Timer
WDOVF
WDTYPE1 or
WDTYPE2
Reset IRQ SMI
Figure 3-1. WATCHDOG Block Diagram
Revision 6.0
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General Configuration Block (Continued)
WATCHDOG Interrupt
3.3.2 WATCHDOG Registers
The WATCHDOG interrupt (if configured and enabled) is
routed to an IRQ signal. The IRQ signal is programmable
via the INTSEL register (Offset 38h, described in Table 3-2
"Multiplexing, Interrupt Selection, and Base Address Regis-
ters" on page 86). The WATCHDOG interrupt is a share-
able, active low, level interrupt.
Table 3-3 describes the WATCHDOG registers.
3.3.2.1 Usage Hints
• SMM code should set bit 8 of the WDCNFG register to 1
when entering ACPI C3 state, if the WATCHDOG timer
is to be suspended. If this is not done, the WATCHDOG
timer is functional during C3 state.
WATCHDOG SMI
The WATCHDOG SMI is recognized by the Core Logic
module as internal input signal EXT_SMI0#. To use the
WATCHDOG SMI, Core Logic registers must be configured
appropriately.
• SMM code should set bit 8 of the WDCNFG register to
1, when entering ACPI S1 and S2 states if the
WATCHDOG timer is to be suspended. If this is not
done, the WATCHDOG timer is functional during S1 and
S2 states.
Table 3-3. WATCHDOG Registers
Bit
Description
Offset 00h-01h
WATCHDOG Timeout Register - WDTO (R/W)
Reset Value: 0000h
Reset Value: 0000h
This register specifies the programmed WATCHDOG timeout period.
15:0 Programmed timeout period.
Offset 02h-03h WATCHDOG Configuration Register - WDCNFG (R/W)
This register selects the signal to be generated when the timer reaches 0, whether or not to disable the 32 KHz input clock during low
power states, and the prescaler value of the clock input.
15:9
8
Reserved. Write as read.
WD32KPD (WATCHDOG 32 KHz Power Down).
0: 32 KHz clock is enabled.
1: 32 KHz clock is disabled, when the GX1 module asserts its internal SUSPA# signal.
This bit is cleared to 0, when POR# is asserted or when the GX1 module de-asserts its internal SUSPA# signal (i.e., on
SUSPA# rising edge). See Section 3.3.2.1 "Usage Hints" on page 94.
7:6
5:4
3:0
WDTYPE2 (WATCHDOG Event Type 2).
00: No action
01: Interrupt
10: SMI
11: System reset
This field is reset to 0 when POR# is asserted. Other system resets do not affect this field.
WDTYPE1 (WATCHDOG Event Type 1).
00: No action
01: Interrupt
10: SMI
11: System reset
This field is reset to 0 when POR# is asserted. Other system resets do not affect this field.
WDPRES (WATCHDOG Timer Prescaler). Divide 32 KHz by:
0000: 1
0001: 2
0010: 4
0011: 8
0100: 16
0101: 32
0110: 64
0111: 128
1000: 256
1001: 512
1010: 1024
1011: 2048
1100: 4096
1101: 8192
1110: Reserved
1111: Reserved
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Revision 6.0
General Configuration Block (Continued)
Table 3-3. WATCHDOG Registers (Continued)
Bit
Description
Offset 04h
WATCHDOG Status Register - WDSTS (R/WC)
Reset Value: 00h
This register contains WATCHDOG status information.
7:4
3
Reserved. Write as read.
WDRST (WATCHDOG Reset Asserted) (Read Only) This bit is set to 1 when WATCHDOG Reset is asserted. It is set to 0
when POR# is asserted, or when the WDOVF bit is set to 0.
2
1
0
WDSMI (WATCHDOG SMI Asserted.) (Read Only) This bit is set to 1 when WATCHDOG SMI is asserted. It is set to 0
when POR# is asserted, or when the WDOVF bit is set to 0.
WDINT (WATCHDOG Interrupt Asserted, Read Only). This bit is set to 1 when the WATCHDOG Interrupt is asserted. It is
set to 0 when POR# is asserted, or when the WDOVF bit is set to 0.
WDOVF (WATCHDOG Overflow). This bit is set to 1 when the WATCHDOG Timer reaches 0. It is set to 0 when POR# is
asserted, or when a 1 is written to this bit by software. Other system reset sources do not affect this bit.
Offset 05h-07h
Reserved - RSVD
The input clock (derived from the 27 MHz crystal oscillator)
is enabled when:
3.4 HIGH-RESOLUTION TIMER
The SC1200/SC1201 provides an accurate time value that
can be used as a time stamp by system software. This time
is called the High-Resolution Timer. The length of the timer
value can be extended via software. It is normally enabled
while the system is in the C0 and C1 states. Optionally,
software can be programmed to enable use of the High-
Resolution Timer during C3 state and/or S1 state as well.
In all other power states the High-Resolution Timer is dis-
abled.
• The GX1 module’s internal SUSPA# signal is 1.
or
• The GX1 module’s internal SUSPA# signal is 0 and bit
TM27MPD (Offset 0Dh[2]) is 0.
The input clock is disabled, when the GX1 module’s inter-
nal SUSPA# signal is 0 and the TM27MPD bit is 1.
For more information about signal SUSPA# see Section
3.4.2.1 "Usage Hints" on page 95 and the GX1 Processor
Series Datasheet.
3.4.1 Functional Description
The High-Resolution Timer is a 32-bit free-running count-
up timer that uses the oscillator clock or the oscillator clock
divided by 27. Bit TMCLKSEL of the TMCNFG register
(Offset 0Dh[1]) can be set via software to determine which
clock should be used for the High-Resolution Timer.
The High-Resolution Timer function resides on the internal
Fast-PCI bus and its registers are in General Configuration
Block address space. Only one complete register should
be accessed at-a-time (e.g., DWORD access should be
used for DWORD wide registers and byte access should be
used for byte-wide registers).
When the most significant bit (bit 31) of the timer changes
from 1 to 0, bit TMSTS of the TMSTS register (Offset
0Ch[0]) is set to 1. When both bit TMSTS and bit TMEN
(Offset 0Dh[0]) are 1, an interrupt is asserted. Otherwise,
the interrupt is de-asserted. This interrupt enables software
emulation of a larger timer.
3.4.2 High-Resolution Timer Registers
Table 3-4 on page 96 describes the registers for the High-
Resolution Timer (TIMER).
The High-Resolution Timer interrupt is routed to an IRQ
signal. The IRQ signal is programmable via the INTSEL
register (Offset 38h). For more information about this regis-
ter, see section Section 3.2 "Multiplexing, Interrupt Selec-
tion, and Base Address Registers" on page 86.
3.4.2.1 Usage Hints
• SMM code should set bit 2 of the TMCNFG register to 1
when entering ACPI C3 state if the High-Resolution
Timer should be disabled. If this is not done, the High-
Resolution Timer is functional during C3 state.
System software uses the read-only TMVALUE register
(Offset 08h[31:0]) to read the current value of the timer.
The TMVALUE register has no default value.
• SMM code should set bit 2 of the TMCNFG register to 1
when entering ACPI S1 state if the High-Resolution
Timer should be disabled. If this is not done, the High-
Resolution Timer is functional during S1 state.
Revision 6.0
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General Configuration Block (Continued)
Table 3-4. High-Resolution Timer Registers
Bit
Description
Offset 08h-0Bh
TIMER Value Register - TMVALUE (RO)
Reset Value: xxxxxxxxh
Reset Value: 00h
This register contains the current value of the High-Resolution Timer.
31:0
Current Timer Value.
Offset 0Ch
TIMER Status Register - TMSTS (R/W)
This register supplies the High-Resolution Timer status information.
7:1
0
Reserved
TMSTS (TIMER Status). This bit is set to 1 when the most significant bit (bit 31) of the timer changes from 1 to 0. It is
cleared to 0 upon system reset or when 1 is written by software to this bit.
Offset 0Dh
TIMER Configuration Register - TMCNFG (R/W)
Reset Value: 00h
This register enables the High-Resolution Timer interrupt; selects the Timer clock; and disables the 27 MHz internal clock during low
power states.
7:3
2
Reserved.
TM27MPD (TIMER 27 MHz Power Down). This bit is cleared to 0 when POR# is asserted or when the GX1 module de-
asserts its internal SUSPA# signal (i.e., on SUSPA# rising edge). See Section 3.4.2.1 "Usage Hints" on page 95.
0: 27 MHz input clock is enabled.
1: 27 MHz input clock is disabled when the GX1 module asserts its internal SUSPA# signal.
TMCLKSEL (TIMER Clock Select).
1
0
0: Count-up timer uses the oscillator clock divided by 27.
1: Count-up timer uses the oscillator clock, 27 MHz clock.
TMEN (TIMER Interrupt Enable).
0: High-Resolution Timer interrupt is disabled.
1: High-Resolution Timer interrupt is enabled.
Offset 0Eh-0Fh
Reserved - RSVD
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Revision 6.0
General Configuration Block (Continued)
3.5 CLOCK GENERATORS AND PLLS
This section describes the registers for the clocks required
by the GX1 module, Core Logic module, and the Video
Processor, and how these clocks are generated. See Fig-
ure 3-2 for a clock generation diagram.
The clock generators are based on 32.768 KHz and 27.000
MHz crystal oscillators. The 32.768 KHz crystal oscillator is
described in Section 4.5.2 "RTC Clock Generation" on
page 119 (functional description of the RTC).
Real-Time Clock (RTC)
32.768 KHz
32.768 KHz
USB Clock (48 MHz)
and I/O Block Clock
Crystal
Oscillator
PLL4
48 MHz
Shutdown
DISABLE
AC97_CLK
(24.576 MHz)
To PAD
PLL3
24.576 MHz
Shutdown
Shutdown
27 MHz
Crystal
High-Resolution Timer Clock
Oscillator
ACPI Clock (14.318 MHz)
Divide
PLL6
57.273 MHz
by 4
CLK27M Ball
Shutdown
Dot Clock
CLK
PLL2
Shutdown
DISABLE
25-135 MHz
48 MHz
Internal Fast-PCI Clock
66 MHz
PLL5
66.67 MHz
Shutdown
(ACPI)
33 MHz
External PCI Clock
(33.3 MHz)
Divide
by 2
DISABLE
Core Clock
ADL
100-333 MHz
Shutdown
(ACPI)
SDRAM Clock
Divider
Note: VPLL2 powers PLL2 and PLL5. VPLL3 powers PLL3, PLL4, and PLL6.
Figure 3-2. Clock Generation Block Diagram
Revision 6.0
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General Configuration Block (Continued)
3.5.1 27 MHz Crystal Oscillator
The internal oscillator employs an external crystal con-
nected to the on-chip amplifier. The on-chip amplifier is
accessible on the X27I input and X27O output signals. See
Figure 3-3 for the recommended external circuit and Table
3-5 for a list of the circuit components.
To other
modules
Internal
External
X27O
X27I
Choose C1 and C2 capacitors to match the crystal’s load
capacitance. The load capacitance CL “seen” by crystal Y
is comprised of C1 in series with C2 and in parallel with the
parasitic capacitance of the circuit. The parasitic capaci-
tance is caused by the chip package, board layout and
socket (if any), and can vary from 0 to 10 pF. The rule of
thumb in choosing these capacitors is:
R1
Y
R2
C1
C2
Figure 3-3. Recommended Oscillator External
Circuitry
CL = (C1 * C2) / (C1 + C2) + CPARASITIC
Example 1:
Crystal CL = 10 pF, CPARASITIC = 8.2 pF
C1 = 3.6 pF, C2 = 3.6 pF
Example 2:
Crystal CL = 20 pF, CPARASITIC = 8 pF
C1 = 24 pF, C2 = 24 pF
Table 3-5. Crystal Oscillator Circuit Components
Component
Parameters
Values
Tolerance
Crystal
Resonance Frequency
Type
27.00 MHz Parallel mode
50 PPM or better
AT-cut or BT-cut
40 Ω
Serial Resistance
Shunt Capacitance
Load Capacitance, CL
Max
Max
7 pF
10-20 pF
Temperature Coefficient
Resistance
User-defined
Resistor R1
20 MΩ
5%
5%
1
Resistance
Capacitance
Capacitance
100 Ω
Resistor R2
1
1
3-24 pF
3-24 pF
5%
5%
Capacitor C1
Capacitor C2
1. The value of these components is recommended. It should be tuned according to crystal and board parameters.
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Revision 6.0
General Configuration Block (Continued)
3.5.2 GX1 Module Core Clock
Table 3-6. Core Clock Frequency
Internal Fast-PCI Clock Freq. (MHz)
The core clock is generated by an Analog Delay Loop
(ADL) clock generator from the internal Fast-PCI clock. The
clock can be any whole number multiple of the input clock
between 4 and 10. Possible values are listed in Table 3-6.
ADL
Multiplier
Value
33.33
48
66.67
At power-on reset, the core clock multiplier value is set
according to the value of four strapped balls - CLKSEL[3:0]
(EBGA balls AL13, AK3, B27, F3 / TEPBGA balls P30,
D29, AF3, B8). These balls also select the clock which is
used as input to the multiplier, as shown in Table 3-7.
4
5
133.3
166.7
200
192
240
288
---
266.7
---
6
---
7
233.3
266.7
---
---
3.5.3 Internal Fast-PCI Clock
8
---
---
The internal Fast-PCI clock can be configured to 33, 48, or
66 MHz via strap options on the CLKSEL1 and CLKSEL0
balls. These can be read in the internal Fast-PCI Clock field
in the CCFC register (GCB+I/O Offset 1Eh[9:8]). (See
Table 3-8 on page 101 details on the CCFC register.)
9
---
---
10
---
---
---
Table 3-7. Strapped Core Clock Frequency
Default ADL Multiplier
Internal Fast-PCI Clock
CLKSEL[3:0]
Straps
Freq. (MHz)
(GCB+I/O Offset 1Eh[9:8])
Multiplier Value
(GCB+I/O Offset 1Eh[3:0])
Maximum Core
Clock Freq. (MHz)
Multiply By
0111
1011
1111
0000
0100
1000
1100
0001
0101
1001
1101
0110
1010
33.33
4
5
0100
0101
0110
0111
1000
1001
1010
0100
0101
0110
0111
0100
0101
133
167
6
200
7
233
8
266
9
Reserved
Reserved
192
10
4
48
5
240
6
288
7
Reserved
266
66.67
4
5
Reserved
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General Configuration Block (Continued)
3.5.4 SuperI/O Clocks
AC97
The SuperI/O module requires a 48 MHz input for Fast
infrared (FIR), UART, and other functions. This clock is sup-
plied by PLL4 using a multiplier value of 576/(108x3) to
generate 48 MHz.
The SC1200/SC1201 generates the 24.576 MHz clock
required by the audio codec. Therefore, no crystal need be
included for the audio codec on the system board.
PLL3 uses the crystal oscillator clock, to generate a 24.576
MHz clock. This clock is driven on the AC97_CLK ball. The
accuracy of the clock supplied by the SC1200/SC1201 is
50 PPM.
3.5.5 Core Logic Module Clocks
The Core Logic module requires the following clock
sources:
3.5.6 Video Processor Clocks
The Video processor requires the following clock sources:
Real-Time Clock (RTC)
RTC requires a 32.768 KHz clock which is supplied directly
from an internal low-power crystal oscillator. This oscillator
uses battery power and has very low current consumption.
Dot
The Dot clock is generated by PLL2. It is supplied to the
Display Controller in the GX1 module (DCLK) that creates
the pixel information, and is returned to the Graphics block
(PCLK) with this information. PLL2 uses the 27 MHz clock
to generate the Dot clock.
USB
The USB requires a 48 MHz input which is supplied by
PLL4. The required total frequency accuracy and slow jitter
for USB is 500 PPM; edge to edge jitter is ±1.2%.
Video
ACPI
The Video clock source depends on the source of the video
data.
The ACPI logic block uses a 14.32 MHz clock supplied by
PLL6. PLL6 creates this clock from the 32.768 KHz clock,
with a multiplier value of 6992/4 to output a 57.278 MHz
clock that is divided by 4.
• If the video data is coming from the GX1 module
(Capture Video mode), the video clock is generated by
the Display Controller.
External PCI
• If the video data is coming directly from the VIP block
(Direct Video mode), the Video Clock is generated by
the VIP block.
The PCI Interface uses a 33.3 MHz clock that is created by
PLL5 and divided by 2. PLL5 uses the 27 MHz clock, to
output a 66.67 MHz clock. PLL5 has a frequency accuracy
of ± 0.1%.
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Revision 6.0
General Configuration Block (Continued)
3.5.7 Clock Registers
The clock generator and PLL registers are described in Table 3-8.
Table 3-8. Clock Generator Configuration
Bit
Description
Offset 10h
Maximum Core Clock Multiplier Register - MCCM (RO)
Reset Value: Strapped Value
This register holds the maximum core clock multiplier value. The maximum clock frequency allowed by the core, is the Fast-PCI clock
multiplied by this value.
7:4
3:0
Reserved.
MCM (Maximum Clock Multiplier). This 4-bit value is the maximum multiplier value allowed for the core clock generator. It
is derived from strap pins CLKSEL[3:0] based on the multiplier value in Table 3-7 on page 99.
Offset 11h
Reserved - RSVD
Offset 12h
PLL Power Control Register - PPCR (R/W)
Reset Value: 2Fh
This register controls operation of the PLLs.
7
6
Reserved.
EXPCID (Disable External PCI Clock).
0: External PCI clock is enabled.
1: External PCI clock is disabled.
GPD (Disable Graphic Pixel Reference Clock).
0: PLL2 input clock is enabled.
5
1: PLL2 input clock is disabled.
Reserved.
4
3
PLL3SD (Shut Down PLL3). AC97 codec clock.
0: PLL3 is enabled.
1: PLL3 is shutdown.
2
1
0
FM1SD (Shut Down PLL4).
0: PLL4 is enabled.
1: PLL4 is shutdown, unless internal Fast-PCI clock is strapped to 48 MHz.
C48MD (Disable SuperI/O and USB Clock).
0: USB and SuperI/O clock is enabled.
1: USB and SuperI/O clock is disabled.
Reserved. Write as read.
Offset 13h-17h
Offset 18h-1Bh
Reserved - RSVD
PLL3 Configuration Register - PLL3C (R/W)
Reset Value: E1040005h
31:24
MFFC (MFF Counter Value).
Fvco = OSCCLK * MFBC / (MFFC * MOC)
OSCCLK = 27 MHz
23:19
18:8
Reserved. Write as read.
MFBC (MFB Counter Value).
Fvco
= OSCCLK * MFBC / (MFFC * MOC)
OSCCLK = 27 MHz
Note: Bits 18, 9, and 8 cannot be changed. Bit 18 is always a 1; bits 9 and 8 are always 0.
7
6
Reserved. Write as read.
Reserved. Must be set to 0.
MOC (MO Counter Value).
5:0
Fvco
= OSCCLK * MFBC / (MFFC * MOC)
OSCCLK = 27 MHz
Revision 6.0
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General Configuration Block (Continued)
Table 3-8. Clock Generator Configuration (Continued)
Bit
Description
Offset 1Eh-1Fh
Core Clock Frequency Control Register - CCFC (R/W)
Reset Value: Strapped Value
This register controls the configuration of the core clock multiplier and the reference clocks.
15:14
13
Reserved.
Reserved. Must be set to 0.
Reserved. Must be set to 0.
Reserved.
12
11:10
9:8
FPCICK (Internal Fast-PCI Clock). (Read Only) Reflects the internal Fast-PCI clock and is the input to the GX1 module
that is used to generate the core clock. These bits reflect the value of strap pins CLKSEL[1:0].
00: 33.3 MHz
01: 48 MHz
10: 66.7 MHz
11: 33.3 MHz
Reserved.
7:4
3:0
MVAL (Multiplier Value). This 4-bit value controls the multiplier in ADL. The value is set according to the Maximum Clock
Multiplier bits of the MCCM register (Offset 10h). The multiplier value should never be written with a multiplier which is differ-
ent from the multiplier indicated in the MCCM register.
0100: Multiply by 4
0101: Multiply by 5
0110: Multiply by 6
0111: Multiply by 7
1000: Multiply by 8
1001: Multiply by 9
1010: Multiply by 10
Other: Reserved
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Revision 6.0
4.0 SuperI/O Module
The SuperI/O (SIO) module is a member of National Semi-
conductor’s SuperI/O family of integrated PC peripherals. It
is a PC98 and ACPI compliant SIO that offers a single-cell
solution to the most commonly used ISA peripherals.
Outstanding Features
• Full compatibility with ACPI Revision 1.0 requirements.
• System Wakeup Control powered by VSB, generates
power-up request and a PME (power management
event) in response to SDATA_IN2 (an audio codec),
IRRX1 (a pre-programmed CEIR), or a RI2# (serial port
ring indicate) event.
The SIO module incorporates: two Serial Ports, an Infrared
Communication Port that supports FIR, MIR, HP-SIR,
Sharp-IR, and Consumer Electronics-IR, a full IEEE 1284
Parallel Port, two ACCESS.bus Interface (ACB) ports, Sys-
tem Wakeup Control (SWC), and a Real-Time Clock (RTC)
that provides RTC timekeeping.
• Advanced RTC, Y2K compliant.
Serial
Interface
Serial
Interface
Infrared/Serial
ISA
Interface
VBAT
VSB
Interface
IR Comunication
Port/Serial Port 3
Serial Port 1
Serial Port 2
Real-Time Clock
Host Interface
System Wakeup
IEEE 1284
Parallel Port
ACCESS.bus 1
ACCESS.bus 2
Control
Wakeup PWUREQ
Events
AB1C
AB1D
AB2C
AB2D
Parallel Port
Interface
Figure 4-1. SIO Block Diagram
Revision 6.0
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SuperI/O Module (Continued)
4.1 FEATURES
PC98 and ACPI Compliant
System Wakeup Control (SWC)
• PnP Configuration Register structure
• Power-up request upon detection of RI2#, CEIR, or
SDATA_IN2 activity:
• Flexible resource allocation for all logical devices:
— Relocatable base address
— Optional routing of power-up request on IRQ line
— 9 Parallel IRQ routing options
• Pre-programmed CEIR address in a pre-selected
— 3 optional 8-bit DMA channels (where applicable)
standard (any NEC, RCA or RC-5)
• Powered by VSB
Parallel Port
• Battery-backed wakeup setup
• Power-fail recovery support
• Software or hardware control
• Enhanced Parallel Port (EPP) compatible with version
EPP 1.9 and IEEE 1284 compliant
Real-Time Clock
• EPP support for version EPP 1.7 of the Xircom specifi-
• A modifiable address that is referenced by a 16-bit
cation
programmable register
• EPP support as mode 4 of the Extended Capabilities
• DS1287, MC146818 and PC87911 compatibility
Port (ECP)
• 242 bytes of battery backed up CMOS RAM in two
• IEEE 1284 compliant ECP, including level 2
banks
• Selection of internal pull-up or pull-down resistor for
• Selective lock mechanisms for the CMOS RAM
Paper End (PE) pin
• Battery backed up century calendar in days, day of the
week, date of month, months, years and century, with
automatic leap-year adjustment
• PCI bus utilization reduction by supporting a demand
DMA mode mechanism and a DMA fairness mechanism
• Protection circuit that prevents damage to the parallel
port when a printer connected to it powers up or is oper-
ated at high voltages, even if the device is in power-
down
• Battery backed-up time of day in seconds, minutes and
hours that allows a 12 or 24 hour format and adjust-
ments for daylight savings time
• BCD or binary format for time keeping
• Output buffers that can sink and source 14 mA
• Three different maskable interrupt flags:
— Periodic interrupts - At intervals from 122 msec to
500 msec
Serial Port 1
• 16550A compatible (SIN1, SOUT1, DTR1#/BOUT1
— Time-of-Month alarm - At intervals from once per
second to once per month
signals only)
— Update Ended Interrupt - Once per second upon
completion of update
Serial Port 2
• 16550A compatible
• Separate battery pin, 3.0V operation that includes an
internal UL protection resistor
Serial Port 3 / Infrared (IR) Communication Port
• 7 µA typical power consumption during power down
• Double-buffer time registers
• Serial Port 3
— SIN and SOUT signals only
— Data rate of up to 1.5 Mbps
• Y2K Compliant
— Software compatible with the 16550A and the 16450
— Shadow register support for write-only bit monitoring
— DMA support
Clock Sources
• 48 MHz clock input
• IR Communication Port
— IrDA 1.1 and 1.0 compatible
• On-chip low frequency clock generator for wakeup
— Data rate of up to 115.2 Kbps (HP-SIR)
— Data rate of 1.152 Mbps (MIR)
— Data rate of 4.0 Mbps (FIR)
• 32.768 KHz crystal with an internal frequency multiplier
to generate all required internal frequencies
— Selectable internal or external modulation/demodula-
tion (ASK-IR and DASK-IR options of SHARP-IR)
— Consumer-IR (TV-Remote) mode
— Consumer Remote Control supports RC-5, RC-6,
NEC, RCA and RECS 80
— DMA support
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Revision 6.0
SuperI/O Module (Continued)
4.2 MODULE ARCHITECTURE
The SIO module comprises a collection of generic func-
tional blocks. Each functional block is described in detail
later in this chapter. The beginning of this chapter
describes the SIO structure and provides all device specific
information, including special implementation of generic
blocks, system interface and device configuration.
The central configuration register set supports ACPI com-
pliant PnP configuration. The configuration registers are
structured as a subset of the Plug and Play Standard Reg-
isters, defined in Appendix A of the Plug and Play ISA
Specification Version 1.0a by Intel and Microsoft. All sys-
tem resources assigned to the functional blocks (I/O
address space, DMA channels and IRQ lines) are config-
ured in, and managed by, the central configuration register
set. In addition, some function-specific parameters are con-
figurable through this unit and distributed to the functional
blocks through special control signals.
The SIO module is based on eight logical devices, the host
interface, and a central configuration register set, all built
around a central, internal 8-bit bus.
The host interface serves as a bridge between the external
ISA interface and the internal bus. It supports 8-bit I/O
read, 8-bit I/O write and 8-bit DMA transactions, as defined
in Personal Computer Bus Standard P996.
The source of the device internal clocks is the 48 MHz
clock signal or through the 32.768 KHz crystal with an
internal frequency multiplier. RTC operates on a 32 KHz
clock.
ACK#
AFD#/DSTRB#
BUSY/WAIT#
ERR#
SIN1
Infrared
Communication
Port/Serial Port 3
Serial
Port 1
SOUT1
Parallel
Port
INIT#
PD[7:0]
DTR#/BOUT1
PE
SLCT
SLIN#/ASTRB#
STB#/WRITE#
SIN2
SOUT2
RTS2#
DTR2#/BOUT2
CTS2
RI2#
DCD2#
DSR2#
Serial
Port 2
Configuration
and Control
Registers
AB1C
AB1D
ACCESS.
bus 1
TC
AB2C
AB2D
DACK0-3
DRQ0-3
IRQ1-12,14-15
IOCHRDY
ZWS#
ACCESS.
bus 2
Internal
Host
Interface
Internal
Signals
IOWR#
IORD#
AEN
System
Wakeup
Real-Time Clock (RTC)
Internal
Signal
Internal Signals
Figure 4-2. Detailed SIO Block Diagram
Revision 6.0
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SuperI/O Module (Continued)
4.3 CONFIGURATION STRUCTURE / ACCESS
This section describes the structure of the configuration
register file, and the method of accessing the configuration
registers.
Table 4-2. LDN Assignments
LDN Functional Block
Reference
00h
01h
02h
Real-Time Clock (RTC)
Page 112
Page 114
Page 115
4.3.1 Index-Data Register Pair
System Wakeup Control (SWC)
The SIO configuration access is performed via an Index-
Data register pair, using only two system I/O byte locations.
The base address of this register pair is determined
according to the state of the IO_SIOCFG_IN bit field of the
Core Logic module (F5BAR0+I/O Offset 00h[26:25]). Table
4-1 shows the selected base addresses as a function of the
IO_SIOCFG_IN bit field.
Infrared Communication Port
(IRCP) or Serial Port 3 (SP3)
03h
05h
06h
07h
08h
Serial Port 1 (SP1)
ACCESS.bus 1 (ACB1)
ACCESS.bus 2 (ACB2)
Parallel Port (PP)
Page 116
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Table 4-1. SIO Configuration Options
I/O Address
Serial Port 2 (SP2)
IO_SIOCFG_IN
Settings
Index
Register Register
Data
Figure 4-3 shows the structure of the standard PnP config-
uration register file. The SIO Control And Configuration
registers are not banked and are accessed by the Index-
Data register pair only (as described above). However, the
Logical Device Control and Configuration registers are
duplicated over eight banks for eight logical devices. There-
fore, accessing a specific register in a specific bank is per-
formed by two-dimensional indexing, where the LDN
register selects the bank (or logical device), and the Index
register selects the register within the bank. Accessing the
Data register while the Index register holds a value of 30h
or higher results in a physical access to the Logical Device
Configuration registers currently pointed to by the Index
register, within the logical device bank currently selected by
the LDN register.
Description
00
01
-
-
-
-
SIO disabled
Configuration
access disabled
10
11
002Eh
015Ch
002Fh
Base address 1
selected
015Dh Base address 2
selected
The Index Register is an 8-bit R/W register located at the
selected base address (Base+0). It is used as a pointer to
the configuration register file, and holds the index of the
configuration register that is currently accessible via the
Data Register. Reading the Index Register returns the last
value written to it (or the default of 00h after reset).
07h
Logical Device Number Register
The Data Register is an 8-bit virtual register, used as a
data path to any configuration register. Accessing the data
register results with physically accessing the configuration
register that is currently pointed by the Index Register.
20h
2Fh
SIO Configuration Registers
Logical Device Control Register
30h
60h
4.3.2 Banked Logical Device Registers
63h
Each functional block is associated with a Logical Device
Number (LDN). The configuration registers are grouped
into banks, where each bank holds the standard configura-
tion registers of the corresponding logical device. Table 4-2
shows the LDNs of the device functional blocks.
Standard Logical Device
70h
71h
74h
75h
Standard Registers
Bank
Select
Special (Vendor-defined)
Logical Device
Configuration Registers
F0h
FEh
Banks
(One per Logical Device)
Figure 4-3. Structure of the Standard
Configuration Register File
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SuperI/O Module (Continued)
Write accesses to unimplemented registers (i.e., accessing
the Data register while the Index register points to a non-
existing register or the LDN is 07h or higher than 08h), are
ignored and a read returns 00h on all addresses except for
74h and 75h (DMA configuration registers) which returns
04h (indicating no DMA channel is active). The configura-
tion registers are accessible immediately after reset.
The SIO module wakes up with the default setup, as fol-
lows:
• When a hardware reset occurs:
— The configuration base address is 2Eh, 15Ch or
None, according to the IO_SIOCFG_IN bit values, as
shown in Table 4-1 on page 106.
— All Logical devices are disabled, with the exception of
the RTC and the SWC, which remains functional but
whose registers cannot be accessed.
4.3.3 Default Configuration Setup
The device has four reset types:
• When either a hardware or a software reset occurs:
— The legacy devices are assigned with their legacy
system resource allocation.
Software Reset
This reset is generated by bit 1 of the SIOCF1 register,
which resets all logical devices. A software reset also
resets most bits in the SIO Configuration and Control regis-
ters (see Section 4.4.1 on page 111 for the bits not
affected). This reset does not affect register bits that are
locked for write access.
— The National proprietary functions are not assigned
with any default resources and the default values of
their base addresses are all 00h.
4.3.4 Address Decoding
Hardware Reset
A full 16-bit address decoding is applied when accessing
the configuration I/O space, as well as the registers of the
functional blocks. However, the number of configurable bits in
the base address registers vary for each device.
This reset is activated by the system reset signal. This
resets all logical devices, with the exception of the RTC and
the SWC, and all SIO Configuration and Control registers,
with the exception of the SIOCF2 register. It also resets all
SuperI/O control and configuration registers, except for
those that are battery-backed.
The lower 1, 2, 3 or 4 address bits are decoded within the
functional block to determine the offset of the accessed
register, within the device’s I/O range of 2, 4, 8 or 16 bytes,
respectively. The rest of the bits are matched with the base
address register to decode the entire I/O range allocated to
the device. Therefore the lower bits of the base address
register are forced to 0 (RO), and the base address is
forced to be 2, 4, 8 or 16 byte aligned, according to the size
of the I/O range.
VPP Power-Up Reset
This reset is activated when either VSB or VBAT is powered
on after both have been off. VPP is an internal voltage
which is a combination of VSB and VBAT. VPP is taken from
VSB if VSB is greater than the minimum (Min) value defined
in Section 8.1.3 "Operating Conditions" on page 371; oth-
erwise, VBAT is used as the VPP source. This reset resets
all registers whose values are retained by VPP.
The base address of the RTC, Serial Port 1, Serial Port 2,
and the Infrared Communication Port are limited to the I/O
address range of 00h to 7Fxh only (bits [15:11] are forced
to 0). The Parallel Port base address is limited to the I/O
address range of 00h to 3F8h. The addresses of the non-
legacy devices are configurable within the full 16-bit
address range (up to FFFxh).
VSB Power-Up Reset
This is an internally generated reset that resets the SWC,
excluding those SWC registers whose values are retained
by VPP. This reset is activated after VSB is powered up.
In some special cases, other address bits are used for
internal decoding (such as 10 in the Parallel Port). For
more details, please see the detailed description of the
base address register for each specific logical device.
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SuperI/O Module (Continued)
4.4 STANDARD CONFIGURATION REGISTERS
As illustrated in Figure 4-4, the Standard Configuration reg-
isters are broadly divided into two categories: SIO Control
and Configuration registers and Logical Device Control and
Configuration registers (one per logical device, some are
optional).
(except for the RTC and the SWC). Activation of the block
enables access to the block’s registers, and attaches its
system resources, which are unused as long as the block is
not activated. Activation of the block may also result in
other effects (e.g., clock enable and active signaling), for
certain functions.
SIO Control and Configuration Registers
Standard Logical Device Configuration Registers
(Index 60h-75h): These registers are used to manage the
resource allocation to the functional blocks. The I/O port
base address descriptor 0 is a pair of registers at Index
60h-61h, holding the (first or only) 16-bit base address for
the register set of the functional block. An optional second
base-address (descriptor 1) at Index 62h-63h is used for
devices with more than one continuous register set. Inter-
rupt Number Select (Index 70h) and Interrupt Type Select
(Index 71h) allocate an IRQ line to the block and control its
type. DMA Channel Select 0 (Index 74h) allocates a DMA
channel to the block, where applicable. DMA Channel
Select 1 (Index 75h) allocates a second DMA channel,
where applicable.
The only PnP control register in the SIO module is the Log-
ical Device Number register at Index 07h. All other stan-
dard PnP control registers are associated with PnP
protocol for ISA add-in cards, and are not supported by the
SIO module.
The SIO Configuration registers at Index 20h-27h are
mainly used for part identification. (See Section 4.4.1 "SIO
Control and Configuration Registers" on page 111 for fur-
ther details.)
Logical Device Control and Configuration Registers
A subset of these registers is implemented for each logical
device. (See Table 4-2 on page 106 for LDN assignment
and Section 4.4.2 "Logical Device Control and Configura-
tion" on page 112 for register details.)
Special Logical Device Configuration Registers (F0h-
F3h): The vendor-defined registers, starting at Index F0h
are used to control function-specific parameters such as
operation modes, power saving modes, pin TRI-STATE,
clock rate selection, and non-standard extensions to
generic functions.
Logical Device Control Register (Index 30h): The only
implemented Logical Device Control register is the Activate
register at Index 30. Bit 0 of the Activate register and bit 0
of the SIO Configuration 1 register (Global Device Enable
bit) control the activation of the associated function block
Index
Register Name
Logical Device Number
07h
20h
21h
22h
27h
2Eh
30h
60h
61h
62h
63h
70h
71h
74h
75h
F0h
F1h
F2h
F3h
SIO ID
SIO Configuration 1
SIO Control and
Configuration Registers
SIO Configuration 2
SIO Revision ID
Reserved exclusively for National use
Logical Device Control (Activate)
I/O Port Base Address Descriptor 0 Bits [15:8]
I/O Port Base Address Descriptor 0 Bits [7:0]
I/O Port Base Address Descriptor 1 Bits [15:8]
I/O Port Base Address Descriptor 1 Bits [7:0]
Interrupt Number Select
Logical Device Control and
Configuration Registers -
one per logical device
(some are optional)
Interrupt Type Select
DMA Channel Select 0
DMA Channel Select 1
Device Specific Logical Device Configuration 1
Device Specific Logical Device Configuration 2
Device Specific Logical Device Configuration 3
Device Specific Logical Device Configuration 4
Figure 4-4. Standard Configuration Registers Map
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Table 4-3 provides the bit definitions for the Standard Con-
figuration registers.
write to prevent the values of reserved bits from being
changed during write.
• All reserved bits return 0 on reads, except where noted
otherwise. They must not be modified as such modifica-
tion may cause unpredictable results. Use read-modify-
• Write only registers should not use read-modify-write
during updates.
Table 4-3. Standard Configuration Registers
Bit
Description
Index 07h
Logical Device Number (R/W)
This register selects the current logical device. See Table 4-2 for valid numbers. All other values are reserved.
7:0 Logical Device number.
Index 20h-2Fh
SIO configuration and ID registers. See Section 4.4.1 "SIO Control and Configuration Registers" on page 111 for register/bit details.
SIO Configuration (R/W)
Index 30h
Activate (R/W)
7:1
0
Reserved.
Logical Device Activation Control.
0: Disable
1: Enable
Index 60h
7:0
I/O Port Base Address Bits [15:8] Descriptor 0 (R/W)
Descriptor 0 A[15:8]. Selects I/O lower limit address bits [15:8] for I/O Descriptor 0.
I/O Port Base Address Bits [7:0] Descriptor 0 (R/W)
Index 61h
7:0
Descriptor 0 A[7:0]. Selects I/O lower limit address bits [7:0] for I/O Descriptor 0.
I/O Port Base Address Bits [15:8] Descriptor 1 (R/W)
Descriptor 1 A[15:8]. Selects I/O lower limit address bits [15:8] for I/O Descriptor 1.
I/O Port Base Address Bits [7:0] Descriptor 1 (R/W)
Index 62h
7:0
Index 63h
7:0
Descriptor 1 A[7:0]. Selects I/O lower limit address bits [7:0] for I/O Descriptor 1.
Interrupt Number (R/W)
Index 70h
7:4
3:0
Reserved.
Interrupt Number. These bits select the interrupt number. A value of 1 selects IRQ1, a value of 2 selects IRQ2, etc. (up to
IRQ12).
Note: IRQ0 is not a valid interrupt selection.
Index 71h
Interrupt Request Type Select (R/W)
Selects the type and level of the interrupt request number selected in the previous register.
7:2
1
Reserved.
Interrupt Level Requested. Level of interrupt request selected in previous register.
0: Low polarity.
1: High polarity.
This bit must be set to 1 (high polarity), except for IRQ8#, that must be low polarity.
0
Interrupt Type Requested. Type of interrupt request selected in previous register.
0: Edge.
1: Level.
Index 74h
DMA Channel Select 0 (R/W)
Selects selected DMA channel for DMA 0 of the logical device (0 - the first DMA channel in case of using more than one DMA channel).
7:3
2:0
Reserved.
DMA 0 Channel Select. This bit field selects the DMA channel for DMA 0.
The valid choices are 0-3, where a value of 0 selects DMA channel 0, 1 selects channel 1, etc.
A value of 4 indicates that no DMA channel is active.
Values 5-7 are reserved.
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SuperI/O Module (Continued)
Table 4-3. Standard Configuration Registers
Bit
Description
Index 75h
DMA Channel Select 1 (R/W)
Indicates selected DMA channel for DMA 1 of the logical device (1 - the second DMA channel in case of using more than one DMA
channel).
7:3
2:0
Reserved.
DMA 1 Channel Select: This bit field selects the DMA channel for DMA 1.
The valid choices are 0-3, where a value of 0 selects DMA channel 0, 1 selects channel 1, etc.
A value of 4 indicates that no DMA channel is active.
Values 5-7 are reserved.
Index F0h-FEh
Logical Device Configuration (R/W)
Special (vendor-defined) configuration options.
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4.4.1 SIO Control and Configuration Registers
Table 4-4 lists the SIO Control and Configuration registers and Table 4-5 provides their bit formats.
Table 4-4. SIO Control and Configuration Register Map
Index
20h
Type
RO
Name
Power Rail
VCORE
VCORE
VPP
Reset Value
SID. SIO ID
F5h
01h
02h
01h
---
21h
R/W
R/W
RO
SIOCF1. SIO Configuration 1
SIOCF2. SIO Configuration 2
SRID. SIO Revision ID
RSVD. Reserved exclusively for National use.
22h
27h
VCORE
---
2Eh
---
Table 4-5. SIO Control and Configuration Registers
Bit
Description
Index 20h
7:0
SIO ID Register - SID (RO)
Reset Value: F5h
Reset Value: 01h
Chip ID. Contains the identity number of the module. The SIO module is identified by the value F5h.
Index 21h
7:6
SIO Configuration 1 Register - SIOCF1 (RW)
General Purpose Scratch. When bit 5 is set to 1, these bits are RO. After reset, these bits can be read or write. Once
changed to RO, the bits can be changed back to R/W only by a hardware reset.
5
Lock Scratch. This bit controls bits 7 and 6 of this register. Once this bit is set to 1 by software, it can be cleared to 0 only
by a hardware reset.
0: Bits 7 and 6 of this register are R/W bits. (Default)
1: Bits 7 and 6 of this register are RO bits.
4:2
1
Reserved.
SW Reset. Read always returns 0.
0: Ignored. (Default)
1: Resets all devices that are reset by MR (with the exception of the lock bits) and the registers of the SWC.
0
Global Device Enable. This bit controls the function enable of all the logical devices in the SIO module, except the SWC
and the RTC. It allows them to be disabled simultaneously by writing to a single bit.
0: All logical devices in the SIO module are disabled, except the SWC and the RTC.
1: Each logical device is enabled according to its Activate register at Index 30h. (Default)
Index 22h
SIO Configuration 2 Register - SIOCF2 (R/W)
Reset Value: 02h
Note: This register is reset only when VPP is first applied.
7
6:4
3:2
1
Reserved.
General Purpose Scratch. Battery-backed.
Reserved.
Reserved.
0
Reserved. (RO)
Index 27h
SIO Revision ID Register - SRID (RO)
Reset Value: 01h
7:0
SIO Revision ID. (RO) This RO register contains the identity number of the chip revision. SRID is incremented on each revi-
sion.
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4.4.2 Logical Device Control and Configuration
As described in Section 4.3.2 "Banked Logical Device Reg-
isters" on page 106, each functional block is associated
with a Logical Device Number (LDN). This section provides
the register descriptions for each LDN.
4.4.2.1 LDN 00h - Real-Time Clock
Table 4-6 lists the registers which are relevant to configura-
tion of the Real-Time Clock (RTC). Only the last registers
(F0h-F3h) are described here (Table 4-7). See Table 4-3
"Standard Configuration Registers" on page 109 for
descriptions of the other registers.
The register descriptions in this subsection use the follow-
ing abbreviations for Type:
• R/W
• R
= Read/Write
= Read from a specific address returns the
value of a specific register. Write to the
same address is to a different register.
= Write
• W
• RO
= Read Only
• R/W1C = Read/Write 1 to Clear. Writing 1 to a bit
clears it to 0. Writing 0 has no effect.
Table 4-6. Relevant RTC Configuration Registers
Reset
Value
Index
Type
Configuration Register or Action
Activate. When bit 0 is cleared, the registers of this logical device are not accessible.1
Standard Base Address MSB register. Bits [7:3] (for A[15:11]) are RO, 00000b.
Standard Base Address LSB register. Bit 0 (for A0) is RO, 0b.
Extended Base Address MSB register. Bits [7:3] (for A[15:11]) are RO, 00000b.
Extended Base Address LSB register. Bit 0 (for A0) is RO, 0b.
Interrupt Number.
30h
R/W
00h
60h
61h
62h
63h
70h
71h
74h
75h
F0h
F1h
R/W
R/W
R/W
R/W
R/W
R/W
RO
00h
70h
00h
72h
08h
00h
04h
04h
00h
00h
Interrupt Type. Bit 1 is R/W; other bits are RO.
Report no DMA assignment.
RO
Report no DMA assignment.
R/W
R/W
RAM Lock register (RLR).
Date of Month Alarm Offset register (DOMAO). Sets index of Date of Month Alarm
register in the standard base address.
F2h
F3h
R/W
R/W
Month Alarm Offset register (MONAO). Sets index of Month Alarm register in the
standard base address.
00h
00h
Century Offset register (CENO). Sets index of Century register in the standard base
address.
1. The logical device registers are maintained, and all RTC mechanisms are functional.
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Table 4-7. RTC Configuration Registers
Bit
Description
Index F0h
RAM Lock Register - RLR (R/W)
When any non-reserved bit in this register is set to 1, it can be cleared only by hardware reset.
7
6
5
4
3
Block Standard RAM.
0: No effect on Standard RAM access. (Default)
1: Read and write to locations 38h-3Fh of the Standard RAM are blocked, writes ignored, and reads return FFh.
Block RAM Write.
0: No effect on RAM access. (Default)
1: Writes to RAM (Standard and Extended) are ignored.
Block Extended RAM Write. This bit controls writes to bytes 00h-1Fh of the Extended RAM.
0: No effect on the Extended RAM access. (Default)
1: Writes to bytes 00h-1Fh of the Extended RAM are ignored.
Block Extended RAM Read. This bit controls read from bytes 00h-1Fh of the Extended RAM.
0: No effect on Extended RAM access. (Default)
1: Reads to bytes 00h-1Fh of the Extended RAM are ignored.
Block Extended RAM. This bit controls access to the Extended RAM 128 bytes.
0: No effect on Extended RAM access. (Default)
1: Read and write to the Extended RAM are blocked: writes are ignored and reads return FFh.
Reserved.
2:0
Index F1h
Date Of Month Alarm Register Offset Register - DOMAO (R/W)
7
Reserved.
6:0
Date of Month Alarm Register Offset Value.
Index F2h
Month Alarm Register Offset Register - MANAO (R/W)
7
Reserved.
6:0
Month Alarm Register Offset Value.
Index F3h
Century Register Offset Register - CENO (R/W)
7
Reserved.
6:0
Century Register Offset Value.
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4.4.2.2 LDN 01h - System Wakeup Control
Table 4-8 lists registers that are relevant to the configura-
tion of System Wakeup Control (SWC). These registers are
described earlier in Table 4-3 "Standard Configuration Reg-
isters" on page 109.
Table 4-8. Relevant SWC Registers
Reset
Value
Index
Type
Configuration Register or Action
Activate. When bit 0 is cleared, the registers of this logical device are not accessible.1
Base Address MSB register.
30h
R/W
00h
60h
61h
70h
71h
74h
75h
R/W
R/W
R/W
R/W
RO
00h
00h
00h
03h
04h
04h
Base Address LSB register. Bits [3:0] (for A[3:0]) are RO, 0000b.
Interrupt Number. (For routing the internal PWUREQ signal.)
Interrupt Type. Bit 1 is R/W. Other bits are RO.
Report no DMA assignment.
RO
Report no DMA assignment.
1. The logical device registers are maintained, and all wakeup detection mechanisms are functional.
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4.4.2.3 LDN 02h - Infrared Communication Port or
Serial Port 3
Table 4-9 lists the configuration registers which affect the
Infrared Communication Port or Serial Port 3 (IRCP/SP3).
Only the last register (F0h) is described here (Table 4-10).
See Table 4-3 "Standard Configuration Registers" on page
109 for descriptions of the other registers listed.
Table 4-9. Relevant IRCP/SP3 Registers
Reset
Value
Index
Type
Configuration Register or Action
30h
60h
61h
70h
71h
74h
75h
F0h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Activate. See also bit 0 of the SIOCF1 register.
Base Address MSB register. Bits [7:3] (for A[15:11]) are RO, 00000b.
Base Address LSB register. Bit [2:0] (for A[2:0]) are RO, 000b.
Interrupt Number.
00h
03h
E8h
00h
03h
04h
04h
02h
Interrupt Type. Bit 1 is R/W; other bits are RO.
DMA Channel Select 0 (RX_DMA).
DMA Channel Select 1 (TX_DMA).
Infrared Communication Port/Serial Port 3 Configuration register.
Table 4-10. IRCP/SP3 Configuration Register
Bit
Description
Index F0h
Infrared Communication Port/Serial Port 3 Configuration Register (R/W)
Reset Value: 02h
7
Bank Select Enable. Enables bank switching.
0: All attempts to access the extended registers are ignored. (Default)
1: Enables bank switching.
6:3
2
Reserved.
Busy Indicator. (RO) This bit can be used by power management software to decide when to power-down the device.
0: No transfer in progress. (Default)
1: Transfer in progress.
1
0
Power Mode Control. When the logical device is active in:
0: Low power mode - Clock disabled. The output signals are set to their default states. Registers are maintained. (Unlike
Active bit in Index 30h that also prevents access to device registers.)
1: Normal power mode - Clock enabled. The device is functional when the logical device is active. (Default)
TRI-STATE Control. When enabled and the device is inactive, the logical device output pins are in TRI-STATE. One excep-
tion is the IRTX/SOUT3 pin, which is driven to 0 when the Infrared Communication Port or Serial Port 3 is inactive and is not
affected by this bit.
0: Disabled. (Default)
1: Enabled (when the device is inactive).
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4.4.2.4 LDN 03h and 08h - Serial Ports 1 and 2
Serial Ports 1 and 2 are identical, except for their reset val-
ues.
affect Serial Ports 1 and 2. Only the last register (F0h) is
described here (Table 4-12). See Table 4-3 "Standard Con-
figuration Registers" on page 109 for descriptions of the
others.
Serial Port 1 is designated as LDN 03h and Serial Port 2 as
LDN 08h. Table 4-11 lists the configuration registers which
Table 4-11. Relevant Serial Ports 1 and 2 Registers
Reset Value
Index
Type
Configuration Register or Action
Port 1
Port 2
30h
60h
61h
70h
71h
74h
75h
F0h
R/W
R/W
R/W
R/W
R/W
RO
Activate. See also bit 0 of the SIOCF1 register.
Base Address MSB register. Bits [7:3] (for A[15:11]) are RO, 00000b.
Base Address LSB register. Bit [2:0] (for A[2:0]) are RO, 000b.
Interrupt Number.
00h
03h
F8h
04h
03h
04h
04h
02h
00h
02h
F8h
03h
03h
04h
04h
02h
Interrupt Type. Bit 1 is R/W; other bits are RO.
Report no DMA assignment.
RO
Report no DMA assignment.
R/W
Serial Ports 1 and 2 Configuration register.
Table 4-12. Serial Ports 1 and 2 Configuration Register
Bit
Description
Index F0h
Serial Ports 1 and 2 Configuration Register (R/W)
Reset Value: 02h
7
Bank Select Enable. Enables bank switching for Serial Ports 1 and 2.
0: Disabled. (Default)
1: Enabled.
6:3
2
Reserved.
Busy Indicator. (RO) This bit can be used by power management software to decide when to power-down Serial Ports 1
and 2 logical devices.
0: No transfer in progress. (Default)
1: Transfer in progress.
1
0
Power Mode Control. When the logical device is active in:
0: Low power mode - Serial Ports 1 and 2 Clock disabled. The output signals are set to their default states. Registers are
maintained. (Unlike Active bit in Index 30h that also prevents access to Serial Ports 1 or 2 registers.)
1: Normal power mode - Serial Ports 1 and 2 clock enabled. Serial Ports 1 and 2 are functional when the respective logical
devices are active. (Default)
TRI-STATE Control. This bit controls the TRI-STATE status of the device output pins when it is inactive (disabled).
0: Disabled. (Default)
1: Enabled when device inactive.
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4.4.2.5 LDN 05h and 06h - ACCESS.bus Ports 1 and 2
ACCESS.bus ports 1 and 2 (ACB1 and ACB2) are identi-
cal. Each ACB is a two-wire synchronous serial interface
compatible with the ACCESS.bus physical layer. ACB1 and
ACB2 use a 24 MHz internal clock. Six runtime registers for
each ACCESS.bus are described in Section 4.7
"ACCESS.bus Interface" on page 135.
ACB1 is designated as LDN 05h and ACB2 as LDN 06h.
Table 4-13 lists the configuration registers which affect the
ACCESS.bus ports. Only the last register (F0h) is
described here (Table 4-14). See Table 4-3 "Standard Con-
figuration Registers" on page 109 for descriptions of the
others.
Table 4-13. Relevant ACB1 and ACB2 Registers
Reset
Value
Index
Type
Configuration Register or Action
30h
60h
61h
70h
71h
74h
75h
F0h
R/W
R/W
R/W
R/W
R/W
RO
Activate. See also bit 0 of the SIOCF1 register
Base Address MSB register.
00h
00h
00h
00h
03h
04h
04h
00h
Base Address LSB register. Bits [2:0] (for A[2:0]) are RO, 000b.
Interrupt Number.
Interrupt Type. Bit 1 is R/W. Other bits are RO.
Report no DMA assignment.
RO
Report no DMA assignment.
R/W
ACB1 and ACB2 Configuration register.
Table 4-14. ACB1 and ACB2 Configuration Register
Bit
Description
Index F0h
ACB1 and ACB2 Configuration Register (R/W)
This register is reset by hardware to 00h.
7:3
2
Reserved.
Internal Pull-Up Enable.
0: No internal pull-up resistors on AB1C/AB2C and AB1D/AB2D. (Default)
1: Internal pull-up resistors on AB1C/AB2C and AB1D/AB2D.
Reserved.
1:0
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SuperI/O Module (Continued)
4.4.2.6 LDN 07h - Parallel Port
• A group of four registers, used only in the Extended ECP
mode, accessed by a second level offset.
The Parallel Port supports all IEEE 1284 standard commu-
nication modes: Compatibility (known also as Standard or
SPP), Bidirectional (known also as PS/2), FIFO, EPP
(known also as Mode 4) and ECP (with an optional
Extended ECP mode).
The desired mode is selected by the ECR runtime register
(Offset 402h). The selected mode determines which runt-
ime registers are used and which address bits are used for
the base address. (See Section 4.8.1 on page 143 for fur-
ther details regarding the runtime registers.)
The Parallel Port includes two groups of runtime registers,
as follows:
Table 4-15 lists the configuration registers which affect the
Parallel Port. Only the last register (F0h) is described here
(Table 4-16). See Table 4-3 "Standard Configuration Regis-
ters" on page 109 for descriptions of the others.
• A group of 21 registers at first level offset, sharing 14
entries. Three of these registers (at Offset 403h, 404h,
and 405h) are used only in the Extended ECP mode.
Table 4-15. Relevant Parallel Port Registers
Reset
Value
Index Type Configuration Register or Action
30h
60h
R/W
R/W
Activate. See also bit 0 of the SIOCF1 register.
00h
02h
Base Address MSB register. Bits [7:3] (for A[15:11]) are RO, 00000b. Bit 2 (for A10) should
be 0b.
61h
R/W
Base Address LSB register. Bits 1 and 0 (A1 and A0) are RO, 00b. For ECP Mode 4 (EPP)
78h
or when using the Extended registers, bit 2 (A2) should also be 0b.
70h
71h
R/W
R/W
Interrupt Number.
Interrupt Type.
Bits [7:2] are RO.
Bit 1 is R/W.
07h
02h
Bit 0 is RO. It reflects the interrupt type dictated by the Parallel Port operation mode. This bit
is set to 1 (level interrupt) in Extended Mode and cleared (edge interrupt) in all other modes.
74h
75h
F0h
R/W
RO
DMA Channel Select.
04h
04h
F2h
Report no second DMA assignment.
Parallel Port Configuration register. (See Table 4-16.)
R/W
Table 4-16. Parallel Port Configuration Register
Bit
Description
Index F0h
Parallel Port Configuration Register (R/W)
Reset Value: F2h
This register is reset by hardware to F2h.
7:5
4
Reserved. Must be 11.
Extended Register Access.
0: Registers at base (address)+403h, base+404h and base+405h are not accessible (reads and writes are ignored).
1: Registers at base (address)+403h, base+404h and base+405h are accessible. This option supports run-time configura-
tion within the Parallel Port address space.
3:2
1
Reserved.
Power Mode Control. When the logical device is active:
0: Parallel port clock disabled. ECP modes and EPP timeout are not functional when the logical device is active. Registers
are maintained.
1: Parallel port clock enabled. All operation modes are functional when the logical device is active. (Default)
0
TRI-STATE Control. When enabled and the device is inactive, the logical device output pins are in TRI-STATE.
0: Disable. (Default)
1: Enable.
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Revision 6.0
SuperI/O Module (Continued)
4.5 REAL-TIME CLOCK (RTC)
The RTC provides timekeeping and calendar management
capabilities. The RTC uses a 32.768 KHz signal as the
basic clock for timekeeping. It also includes 242 bytes of
battery-backed RAM for general-purpose use.
4.5.2 RTC Clock Generation
The RTC uses a 32.768 KHz clock signal as the basic
clock for timekeeping. The 32.768 KHz clock can be sup-
plied by the internal oscillator circuit, or by an external
oscillator (see Section 4.5.2.2 "External Oscillator" on page
120).
The RTC provides the following functions:
• Accurate timekeeping and calendar management
• Alarm at a predetermined time and/or date
• Three programmable interrupt sources
4.5.2.1 Internal Oscillator
The internal oscillator employs an external crystal con-
nected to the on-chip amplifier. The on-chip amplifier is
accessible on the X32I input and X32O output. See Figure
4-5 for the recommended external circuit and Table 4-17 for
a listing of the circuit components. The oscillator may be
disabled in certain conditions. See Section 4.5.2.8 "Oscilla-
tor Activity" on page 123 for more details.
• Valid timekeeping during power-down, by utilizing
external battery backup
• 242 bytes of battery-backed RAM
• RAM lock schemes to protect its content
• Internal oscillator circuit (the crystal itself is off-chip), or
external clock supply for the 32.768 KHz clock
To other
modules
VBAT
CF
• A century counter
Internal
• PnP support:
External
— Relocatable Index and Data registers
— Module access enable/disable option
— Host interrupt enable/disable option
X32I
X32O
C2
R1
Y
R2
• Additional low-power features such as:
— Automatic switching from battery to VSB
— Internal power monitoring on the VRT bit
— Oscillator disabling to save battery during storage
B1
C1
Battery
CF = 0.1 µF
• Software compatible with the DS1287 and MC146818
Figure 4-5. Recommended Oscillator External
Circuitry
4.5.1 Bus Interface
The RTC function is initially mapped to the default SuperI/O
locations at Indexes 70h to 73h (two Index/Data pairs).
These locations may be reassigned, in compliance with
Plug and Play requirements.
Table 4-17. Crystal Oscillator Circuit Components
Component
Parameters
Values
Tolerance
Crystal
Resonance Frequency
Type
32.768 KHz Parallel mode
User-defined
N-cut or XY-bar
40 KΩ
Serial Resistance
Quality Factor, Q
Shunt Capacitance
Load Capacitance, CL
Max
Min
35000
2 pF
Max
9-13 pF
Temperature Coefficient
Resistance
User-defined
Resistor R1
Resistor R2
Capacitor C1
Capacitor C2
20 MΩ
5%
5%
5%
5%
Resistance
Capacitance
Capacitance
120 KΩ
3 to 10 pF
3 to 10 pF
Revision 6.0
119
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SuperI/O Module (Continued)
External Elements
The divider chain can be activated by setting normal opera-
tional mode (bits [6:4] of CRA = 01x or 100). The first
update occurs 500 msec after divider chain activation.
Choose C1 and C2 capacitors (see Figure 4-5 on page
119) to match the crystal’s load capacitance. The load
capacitance CL “seen” by crystal Y is comprised of C1 in
series with C2 and in parallel with the parasitic capacitance
of the circuit. The parasitic capacitance is caused by the
chip package, board layout and socket (if any), and can
vary from 0 to 10 pF. The rule of thumb in choosing these
capacitors is:
Bits [3:0] of CRA select one the of fifteen taps from the
divider chain to be used as a periodic interrupt. The peri-
odic flag becomes active after half of the programmed
period has elapsed, following divider chain activation.
See Table 4-20 on page 126 for more details.
CL = (C1 * C2) / (C1 + C2) + CPARASITIC
Example:
VBAT
To other
Crystal CL = 10 pF, CPARASITIC = 8.2 pF
C1 = 3.6 pF, C2 = 3.6 pF
modules
Internal
CF
External
Oscillator Startup
X32O
NC
CLKIN
(X32I)
The oscillator starts to generate 32.768 KHz pulses to the
RTC after about 100 msec from when VBAT is higher than
VBATMIN (2.4V) or VSB is higher than VSBMIN (3.0V). The
oscillation amplitude on the X32O pin stabilizes to its final
value (approximately 0.4V peak-to-peak around 0.7V DC)
in about 1 s.
R2
R1
3.3V square wave
OUT
POWER
R1 = 30 KΩ
32.768 KHz
Clock Generator
C1 can be trimmed to achieve precisely 32.768 KHz. To
achieve a high time accuracy, use crystal and capacitors
with low tolerance and temperature coefficients.
CF
B1
R2 = 30 KΩ
CF = 0.1 µF
Battery
4.5.2.2 External Oscillator
32.768 KHz can be applied from an external clock source,
as shown in Figure 4-6.
Figure 4-6. External Oscillator Connections
Connections
Connect the clock to the X32I ball, leaving the oscillator
output, X32O, unconnected.
Divider Chain
1
2
2
2
3
13 14 15
1 Hz
2
2
2
2
Signal Parameters
The signal levels should conform to the voltage level
requirements for X32I, of square or sine wave of 0.0V to
VCORE amplitude. The signal should have a duty cycle of
approximately 50%. It should be sourced from a battery-
backed source in order to oscillate during power-down.
This assures that the RTC delivers updated time/calendar
information.
Reset
DV2 DV1 DV0
4
6
5
CRA Register
32.768 KHz
Oscillator
Enable
To other
modules
4.5.2.3 Timing Generation
The timing generation function divides the 32.768 KHz
clock by 215 to derive a 1 Hz signal, which serves as the
input for the seconds counter. This is performed by a
divider chain composed of 15 divide-by-two latches, as
shown in Figure 4-7.
X32I
X32O
Figure 4-7. Divider Chain Control
Bits [6:4] (DV[2:0]) of the CRA Register control the follow-
ing functions:
• Normal operation of the divider chain (counting).
• Divider chain reset to 0.
• Oscillator activity when only VBAT power is present
(backup state).
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Revision 6.0
SuperI/O Module (Continued)
4.5.2.4 Timekeeping
Method 2
1) Access the RTC registers after detection of an Update
Ended interrupt. This implies that an update has just
been completed and 999 msec remain until the next
update.
Data Format
Time is kept in BCD or binary format, as determined by bit
2 (DM) of Control Register B (CRB), and in either 12 or 24-
hour format, as determined by bit 1 of this register.
2) To detect an Update Ended interrupt, you may either:
Note: When changing the above formats, re-initialize all
— Poll bit 4 of CRC.
— Use the following interrupt routine:
– Set bit 4 of CRB.
the time registers.
Daylight Saving
– Wait for an interrupt from interrupt pin.
– Clear the IRQF flag of CRC before exiting the
interrupt routine.
Daylight saving time exceptions are handled automatically,
as described in Table 4-20 on page 126.
Leap Years
Method 3
Leap year exceptions are handled automatically by the
internal calendar function. Every four years, February is
extended to 29 days.
Poll bit 7 of CRA. The update occurs 244 µs after this bit
goes high. Therefore, if a 0 is read, the time registers
remain stable for at least 244 µs.
Updating
Method 4
The time and calendar registers are updated once per sec-
ond regardless of bit 7 (SET) of CRB. Since the time and
calendar registers are updated serially, unpredictable
results may occur if they are accessed during the update.
Therefore, you must ensure that reading or writing to the
time storage locations does not coincide with a system
update of these locations. There are several methods to
avoid this contention.
Use a periodic interrupt routine to determine if an update
cycle is in progress, as follows:
1) Set the periodic interrupt to the desired period.
2) Set bit 6 of CRB to enable the interrupt from periodic
interrupt.
3) Wait for the periodic interrupt appearance. This indi-
cates that the period represented by the following
expression remains until another update occurs:
[(Period of periodic interrupt / 2) + 244 µs]
Method 1
1) Set bit 7 of CRB to 1. This takes a “snapshot” of the
internal time registers and loads them into the user
copy registers. The user copy registers are seen when
accessing the RTC from outside, and are part of the
double buffering mechanism. You may keep this bit set
for up to 1 second, since the time/calendar chain con-
tinue to be updated once per second.
4.5.2.5 Alarms
The timekeeping function can be set to generate an alarm
when the current time reaches a stored alarm time. After
each RTC time update (every 1 second), the seconds, min-
utes, hours, date of month and month counters are com-
pared with their corresponding registers in the alarm
settings. If equal, bit 5 of CRC is set. If the Alarm Interrupt
Enable bit was previously set (CRB bit 5), interrupt request
pin is also active.
2) Read or write the required registers (since bit 1 is set,
you are accessing the user copy registers). If you per-
form a read operation, the information you read is cor-
rect from the time when bit 1 was set. If you perform a
write operation, you write only to the user copy regis-
ters.
Any alarm register may be set to “Unconditional Match” by
setting bits [7:6] to 11. This combination, not used by any
BCD or binary time codes, results in a periodic alarm. The
rate of this periodic alarm is determined by the registers
that were set to “Unconditional Match”.
3) Reset bit 1 to 0. During the transition, the user copy
registers update the internal registers, using the dou-
ble buffering mechanism to ensure that the update is
performed between two time updates. This mecha-
nism enables new time parameters to be loaded in the
RTC.
For example, if all but the seconds and minutes alarm reg-
isters are set to “Unconditional Match”, an interrupt is gen-
erated every hour at the specified minute and second. If all
but the seconds, minutes and hours alarm registers are set
to “Unconditional Match”, an interrupt is generated every
day at the specified hour, minute and second.
Revision 6.0
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SuperI/O Module (Continued)
4.5.2.6 Power Supply
The device is supplied from two supply voltages, as shown
in Figure 4-8:
The RTC is supplied from one of two power supplies, VSB
or VBAT, according to their levels. An internal voltage com-
parator delivers the control signals to a pair of switches.
Battery backup voltage VBAT maintains the correct time and
saves the CMOS memory when the VSB voltage is absent,
due to power failure or disconnection of the external AC/DC
input power supply or VSB main battery.
• System standby power supply voltage, VSB
• Backup voltage, from low capacity Lithium battery
A standby voltage, VSB, from the external AC/DC power
supply powers the RTC under normal conditions.
To assure that the module uses power from VSB and not
from VBAT, the VSB voltage should be maintained above its
minimum, as detailed in Section 8.0 "Electrical Specifica-
tions" on page 371.
Figure 4-9 represents a typical battery configuration. No
external diode is required to meet the UL standard, due to
the internal switch and internal serial resistor RUL
.
The actual voltage point where the module switches from
VBAT to VSB is lower than the minimum workable battery
voltage, but high enough to guarantee the correct function-
ality of the oscillator and the CMOS RAM.
External AC Power
ACPI Controller
Power
Supply
Figure 4-10 shows typical battery current consumption dur-
ing battery-backed operation, and Figure 4-11 during nor-
mal operation.
VDIGITAL
VDIGITAL Sense
VDIGITAL
ONCTL#
VSB
ONCTL#
VSB
PC0
VSB
IBAT (µA)
VSB
RTC
10.0
7.5
VBAT
5.0
VBAT
VBAT
Backup
Battery
2.5
VBAT (V)
2.4 3.0 3.6
Figure 4-8. Power Supply Connections
Figure 4-10. Typical Battery Current: Battery
Backed Power Mode @ T = 25°C
C
VSB
VSB
0.1 µF
RTC
CF
CF
VSBL
VSBL
IBAT (µA)
VPP
VREF
0.1 µF
VBAT
RUL
BT1
0.75
0.50
CF
0.1 µF
0.25
VSB
Note: Place a 0.1 µF capacitor on each VSB, VSBL
(V)
3.0 3.3 3.6
power supply pin as close as possible to the
Note: Battery voltage in this test is 3.0V.
pin, and also on VBAT
.
Figure 4-11. Typical Battery Current: Normal
Operation Mode
Figure 4-9. Typical Battery Configuration
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Revision 6.0
SuperI/O Module (Continued)
4.5.2.7 System Power States
Power-Up Detection
The system power state may be No Power, Power On,
Power Off or Power Failure. Table 4-18 indicates the power-
source combinations for each state. No other power-source
combinations are valid.
When system power is restored after a power failure or
power off state (VSB = 0), the lockout condition continues
for a delay of 62 msec (minimum) to 125 msec (maximum)
after the RTC switches from battery to system power.
In addition, the power sources and distribution for the entire
system are illustrated in Figure 4-8 on page 122.
The lockout condition is switched off immediately in the fol-
lowing situations:
• If the Divider Chain Control bits, DV[2:0], (CRA bits [6:4])
specify a normal operation mode (01x or 100), all input
signals are enabled immediately upon detection of
Table 4-18. System Power States
VDIGITAL
VSB
VBAT
Power State
system voltage above VSBON
.
• When battery voltage is below VBATDCT and HMR is 1,
all input signals are enabled immediately upon detection
of system voltage above VSBON. This also initializes
registers at offsets 00h through 0Dh.
−
−
−
+
−
−
+
+
−
No Power
+
Power Failure
Power Off
Power On
+ or -
+ or -
• If bit 7 (VRT) of CRD is 0, all input signals are enabled
immediately upon detection of system voltage above
VSBON
.
No Power
4.5.2.8 Oscillator Activity
The RTC oscillator is active if:
This state exists when no external or battery power is con-
nected to the device. This condition does not occur once a
backup battery has been connected, except in the case of
a malfunction.
• VSB power supply is higher than VSBON, independent of
the battery voltage, VBAT
Power On
-or-
This is the normal state when the system is active. This
state may be initiated by various events in addition to the
normal physical switching on of the system. In this state,
the system power supply is powered by external AC power
and produces VDIGITAL and VSB. The system and the part
are powered by VDIGITAL, with the exception of the RTC log-
ical device, which is powered by VSB.
• VBAT power supply is higher than VBATMIN, regardless if
VSB is present or not.
The RTC oscillator is disabled if:
• During power-down (VBAT only), the battery voltage
drops below VBATMIN. When this occurs, the oscillator
may be disabled and its functionality cannot be guaran-
teed.
Power Off (Suspended)
This is the normal state when the system has been
switched off and is not required to be active, but is still con-
nected to a live external AC input power source. This state
may be initiated directly or by software. The system is pow-
ered down. The RTC logical device remains active, pow-
-or-
• Software wrote 00x to DV[2:0] bits of the CRA Register
and VSB is removed. This disables the oscillator and
decreases the power consumption from the battery
connected to VBAT. When disabling the oscillator, the
CMOS RAM is not affected as long as the battery is
present at a correct voltage level.
ered by VSB
.
Power Failure
This state occurs when the external power source to the
system stops supplying power, due to disconnection or
power failure on the external AC input power source. The
RTC continues to maintain timekeeping and RAM data
under battery power (VBAT), unless the oscillator stop bit
was set in the RTC. In this case, the oscillator stops func-
tioning if the system goes to battery power, and timekeep-
ing data becomes invalid.
If the RTC oscillator becomes inactive, the following fea-
tures are dysfunctional/disabled:
• Timekeeping.
• Periodic interrupt.
• Alarm.
System Bus Lockout
During power on or power off, spurious bus transactions
from the host may occur. To protect the RTC internal regis-
ters from corruption, all inputs are automatically locked out.
The lockout condition is asserted when VSB is lower than
VSBON
.
Revision 6.0
123
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SuperI/O Module (Continued)
4.5.2.9 Interrupt Handling
4.5.2.10 Battery-Backed RAMs and Registers
The RTC has a single Interrupt Request line which handles
the following three interrupt conditions:
The RTC has two battery-backed RAMs and 17 registers,
used by the logical units themselves. Battery-backup power
enables information retention during system power down.
• Periodic interrupt.
• Alarm interrupt.
The RAMs are:
• Standard RAM
• Extended RAM
• Update end interrupt.
The interrupts are generated if the respective enable bits in
the CRB register are set prior to an interrupt event occur-
rence. Reading the CRC register clears all interrupt flags.
Thus, when multiple interrupts are enabled, the interrupt
service routine should first read and store the CRC regis-
ter, and then deal with all pending interrupts by referring to
this stored status.
The memory maps and register content of the RAMs is
provided in Section 4.5.4 "RTC General-Purpose RAM
Map" on page 129.
The first 14 bytes and 3 programmable bytes of the Stan-
dard RAM are overlaid by time, alarm data and control reg-
isters. The remaining 111 bytes are general-purpose
memory.
If an interrupt is not serviced before a second occurrence
of the same interrupt condition, the second interrupt event
is lost. Figure 4-12 illustrates the interrupt timing in the
RTC.
Registers with reserved bits should be written using the
read-modify-write method.
All register locations within the device are accessed by the
RTC Index and Data registers (at base address and base
address+1). The Index register points to the register loca-
tion being accessed, and the Data register contains the
data to be transferred to or from the location. An additional
128 bytes of battery-backed RAM (also called Extended
RAM) may be accessed via a second pair of Index and
Data registers.
Bit 7
of CRA
A
244 µs
Bit 4
of CRC
P
P/2
P/2
Bit 6
of CRC
Access to the two RAMs may be locked. For details see
Table 4-7 on page 113.
B
C
30.5 µs
Bit 5
of CRC
Flags (and IRQ) are reset at the conclusion of CRC read or by
reset.
A = Update In Progress bit high before update occurs = 244 µs
B = Periodic interrupt to update = Period (periodic int) / 2 +
244 µs
C =Update to Alarm Interrupt = 30.5 µs
P = Period is programmed by RS[3:0] of CRA
Figure 4-12. Interrupt/Status Timing
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Revision 6.0
SuperI/O Module (Continued)
4.5.3 RTC Registers
these registers is also disabled if bit 7 of the CRD Register
is 0.
The RTC registers can be accessed (see Section 4.4.2.1
"LDN 00h - Real-Time Clock" on page 112) at any time dur-
ing normal operation mode (i.e.,when VSB is within the rec-
ommended operation range). This access is disabled
during battery-backed operation. The write operation to
Note: Before attempting to perform any start-up proce-
dures, read about bit 7 (VRT) of the CRD Register.
This section describes the RTC Timing and Control Regis-
ters that control basic RTC functionality.
Table 4-19. RTC Register Map
Reset
Type
Index
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Name
SEC. Seconds Register
SECA. Seconds Alarm Register
MIN. Minutes Register
MINA. Minutes Alarm Register
HOR. Hours Register
VPP PUR
VPP PUR
VPP PUR
VPP PUR
V
PP PUR
PP PUR
HORA. Hours Alarm Register
DOW. Day Of Week Register
DOM. Date Of Month Register
MON. Month Register
V
VPP PUR
VPP PUR
VPP PUR
VPP PUR
YER. Year Register
0Ah
0Bh
0Ch
0Dh
R/W
R/W
RO
CRA. RTC Control Register A
CRB. RTC Control Register B
CRC. RTC Control Register C
CRD. RTC Control Register D
Bit specific
Bit specific
Bit specific
RO
VPP PUR
Programmable1
Programmable1
Programmable1
R/W
R/W
R/W
DOMA. Date of Month Alarm Register
MONA. Month Alarm Register
CEN. Century Register
VPP PUR
VPP PUR
VPP PUR
1. Overlaid on RAM bytes in range 0Eh-7Fh. See Section 4.4.2.1 "LDN 00h - Real-Time Clock" on page 112.
Revision 6.0
125
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SuperI/O Module (Continued)
Table 4-20. RTC Registers
Bit
Description
Index 00h
Seconds Register - SEC (R/W)
Reset Type: VPP PUR
Reset Type: VPP PUR
7:0
Seconds Data. Values may be 00 to 59 in BCD format or 00 to 3B in binary format.
Index 01h
Seconds Alarm Register - SECA (R/W)
7:0
Seconds Alarm Data. Values may be 00 to 59 in BCD format or 00 to 3B in binary format.
When bits 7 and 6 are both set to one (“11”), unconditional match is selected.
Index 02h
Minutes Register - MIN (R/W)
Reset Type: VPP PUR
Reset Type: VPP PUR
7:0
Minutes Data. Values can be 00 to 59 in BCD format, or 00 to 3B in binary format.
Index 03h
Minutes Alarm Register - MINA (R/W)
7:0
Minutes Alarm Data. Values can be 00 to 59 in BCD format, or 00 to 3B in binary format.
When bits 7 and 6 are both set to 1, unconditional match is selected. See Section 4.5.2.5 "Alarms" on page 121 for more
information about "unconditional" matches.
Index 04h
Hours Register - HOR (R/W)
Reset Type: VPP PUR
7:0
Hours Data. For 12-hour mode, values can be 01 to 12 (AM) and 81 to 92 (PM) in BCD format, or 01 to 0C (AM) and 81 to
8C (PM) in binary format. For 24-hour mode, values can be 0- to 23 in BCD format or 00 to 17 in binary format.
Index 05h
Hours Alarm Register - HORA (R/W)
Reset Type: VPP PUR
7:0
Hours Alarm Data. For 12-hour mode, values may be 01 to 12 (AM) and 81 to 92 (PM) in BCD format or 01 to 0C (AM) and
81 to 8C (PM) in Binary format. For 24-hour mode, values may be 0- to 23 in BCD format or 00 to 17 in Binary format.
When bits 7 and 6 are both set to one (“11”), unconditional match is selected.
Index 06h
Day of Week Register - DOW (R/W)
Reset Type: VPP PUR
Reset Type: VPP PUR
Reset Type: VPP PUR
7:0
Day Of Week Data. Values may be 01 to 07 in BCD format or 01 to 07 in binary format.
Index 07h
Date of Month Register - DOM (R/W)
7:0
Date Of Month Data. Values may be 01 to 31 in BCD format or 01 to 1F in binary format.
Index 08h
Month Register - MON (R/W)
Width: Byte
7-0
Month Data. Values may be 01 to 12 in BCD format or 01 to 0C in binary format.
Index 09h
Year Register - YER (R/W)
Reset Type: VPP PUR
7:0
Year Data. Values may be 00 to 99 in BCD format or 00 to 63 in binary format.
Index 0Ah
RTC Control Register A - CRA (R/W)
Reset Type: Bit Specific
This register controls test selection, among other functions. This register cannot be written before reading bit 7 of CRD.
7
Update in Progress. (RO) This bit is not affected by reset. This bit reads 0 when bit 7 of the CRB Register is 1.
0: Timing registers not updated within 244 µs.
1: Timing registers updated within 244 µs.
6:4
3:0
Divider Chain Control. These bits control the configuration of the divider chain for timing generation and register bank
selection. See Table 4-21 on page 128. They are cleared to 000 as long as bit 7 of CRD is 0.
Periodic Interrupt Rate Select. These bits select one of fifteen output taps from the clock divider chain to control the rate of
the periodic interrupt. See Table 4-22 on page 128 and Figure 4-7 on page 120. They are cleared to 000 as long as bit 7 of
CRD is 0.
Index 0Bh
RTC Control Register B - CRB (R/W)
Set Mode. This bit is reset at VPP power-up reset only.
0: Timing updates occur normally.
Reset Type: Bit Specific
7
1: User copy of time is “frozen”, allowing the time registers to be accessed whether or not an update occurs.
6
Periodic Interrupt. Bits [3:0] of the CRA Register determine the rate at which this interrupt is generated. It is cleared to 0 on
RTC reset (i.e., hardware or software reset) or when RTC is disable.
0: Disable.
1: Enable.
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SuperI/O Module (Continued)
Table 4-20. RTC Registers (Continued)
Bit
Description
5
Alarm Interrupt. This interrupt is generated immediately after a time update in which the seconds, minutes, hours, date and
month time equal their respective alarm counterparts. It is cleared to 0 as long as bit 7 of the CRD Register is reads 0.
0: Disable.
1: Enable.
4
Update Ended Interrupt. This interrupt is generated when an update occurs. It is cleared to 0 on RTC reset (i.e., hardware
or software reset) or when the RTC is disable.
0: Disable.
1: Enable.
3
2
Reserved. This bit is defined as “Square Wave Enable” by the MC146818 and is not supported by the RTC. This bit is
always read as 0.
Data Mode. This bit is reset at VPP power-up reset only.
0: Enable BCD format.
1: Enable Binary format.
1
0
Hour Mode. This bit is reset at VPP power-up reset only.
0: Enable 12-hour format.
1: Enable 24-hour format.
Daylight Saving. This bit is reset at VPP power-up reset only.
0: Disable.
1: Enable:
- In the spring, time advances from1:59:59 AM to 3:00:00 AM on the first Sunday in April.
- In the fall, time returns from 1:59:59 AM to 1:00:00 AM on the last Sunday in October.
Index 0Ch
RTC Control Register C - CRC (RO)
Reset Type: Bit Specific
7
IRQ Flag. Mirrors the value on the interrupt output signal. When interrupt is active, IRQF is 1. To clear this bit (and deacti-
vate the interrupt pin), read the CRC Register as the flag bits UF, AF and PF are cleared after reading this register.
0: IRQ inactive.
1: Logic equation is true: ((UIE and UF) or (AIE and AF) or (PIE and PF)).
6
5
4
Periodic Interrupt Flag. Cleared to 0 on RTC reset (i.e., hardware or software reset) or the RTC disabled. In addition, this
bit is cleared to 0 when this register is read.
0: No transition occurred on the selected tap since the last read.
1: Transition occurred on the selected tap of the divider chain.
Alarm Interrupt Flag. Cleared to 0 as long as bit 7 of the CRD Register is reads 0. In addition, this bit is cleared to 0 when
this register is read.
0: No alarm detected since the last read.
1: Alarm condition detected.
Update Ended Interrupt Flag. Cleared to 0 on RTC reset (i.e., hardware or software reset) or the RTC disabled. In addition,
this bit is cleared to 0 when this register is read.
0: No update occurred since the last read.
1: Time registers updated.
Reserved.
3:0
Index 0Dh
RTC Control Register D - CRD (RO)
Reset Type: VPP PUR
7
Valid RAM and Time. This bit senses the voltage that feeds the RTC (VSB or VBAT) and indicates whether or not it was too
low since the last time this bit was read. If it was too low, the RTC contents (time/calendar registers and CMOS RAM) is not
valid.
0: The voltage that feeds the RTC was too low.
1: RTC contents (time/calendar registers and CMOS RAM) are valid.
Reserved.
6:0
Index Programmable
Date of Month Alarm Register - DOMA (R/W)
Reset Type: VPP PUR
7:0
Date of Month Alarm Data. Values may be 01 to 31 in BCD format or 01 to 1F in Binary format.
When bits 7 and 6 are both set to one (“11”), unconditional match is selected. (Default)
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SuperI/O Module (Continued)
Table 4-20. RTC Registers (Continued)
Bit
Description
Index Programmable
Month Alarm Register - MONA (R/W)
Reset Type: VPP PUR
Reset Type: VPP PUR
7:0
Month Alarm Data. Values may be 01 to 12 in BCD format or 01 to 0C in Binary format.
When bits 7 and 6 are both set to one (“11”), unconditional match is selected. (Default)
Index Programmable
Century Register - CEN (R/W)
7:0
Century Data. Values may be 00 to 99 in BCD format or 00 to 63 in Binary format.
Table 4-21. Divider Chain Control / Test Selection
Table 4-22. Periodic Interrupt Rate Encoding
DV2
DV1
DV0
Rate Select
3 2 1 0
Periodic Interrupt
Rate (msec)
Divider
Chain Output
CRA6
CRA5 CRA4 Configuration
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
No interrupts
3.906250
7.812500
0.122070
0.244141
0.488281
0.976562
1.953125
3.906250
7.812500
15.625000
31.250000
62.500000
125.000000
250.000000
500.000000
0
0
0
1
1
0
1
1
0
1
X
0
Oscillator Disabled
Normal Operation
Test
7
8
1
2
X
X
3
Divider Chain Reset
4
5
6
7
8
9
10
11
12
13
14
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SuperI/O Module (Continued)
Parameter
Table 4-23. BCD and Binary Formats
BCD Format
Binary Format
Seconds
Minutes
Hours
00 to 59
00 to 3B
00 to 3B
00 to 59
12-hour mode:
01 to 12 (AM)
81 to 92 (PM)
00 to 23
12-hour mode:
01 to 0C (AM)
81 to 8C (PM)
00 to 17
24-hour mode:
24-hour mode:
01 to 07
Day
01 to 07 (Sunday = 01)
01 to 31
Date
01 to 1F
Month
Year
01 to 12 (January = 01)
00 to 99
01 to 0C
00 to 63
Century
00 to 99
00 to 63
4.5.3.1 Usage Hints
4.5.4 RTC General-Purpose RAM Map
Table 4-24. Standard RAM Map
1) Read bit 7 of CRD at each system power-up to vali-
date the contents of the RTC registers and the CMOS
RAM. When this bit is 0, the contents of these regis-
ters and the CMOS RAM are questionable. This bit is
reset when the backup battery voltage is too low. The
voltage level at which this bit is reset is below the mini-
mum recommended battery voltage, 2.4V. Although
the RTC oscillator may function properly and the regis-
ter contents may be correct at lower than 2.4V, this bit
is reset since correct functionality cannot be guaran-
teed. System BIOS may use a checksum method to
revalidate the contents of the CMOS-RAM. The check-
sum byte should be stored in the same CMOS RAM.
Index
Description
0Eh - 7Fh
Battery-backed general-purpose 111-
byte RAM.
Table 4-25. Extended RAM Map
Description
Index
00h - 7Fh
Battery-backed general-purpose 128-
byte RAM.
2) Change the backup battery while normal operating
power is present, and not in backup mode, to maintain
valid time and register information. If a low leakage
capacitor is connected to VBAT, the battery may be
changed in backup mode.
3) A rechargeable NiCd battery may be used instead of a
non-rechargeable Lithium battery. This is a preferred
solution for portable systems, where small size com-
ponents is essential.
4) A supercap capacitor may be used instead of the nor-
mal Lithium battery. In a portable system usually the
VSB voltage is always present since the power man-
agement stops the system before its voltage falls to
low. The supercap capacitor in the range of 0.047-
0.47 F should supply the power during the battery
replacement.
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SuperI/O Module (Continued)
4.6 SYSTEM WAKEUP CONTROL (SWC)
The SWC wakes up the system by sending a power-up
request to the ACPI controller in response to the following
maskable system events:
4.6.1.2 CEIR Address
A CEIR transmission received on IRRX1 in a pre-selected
standard (NEC, RCA or RC-5) is matched against a pro-
grammable CEIR address. Detection of matching can be
used as a wakeup event. The CEIR address detection
operates independently of the serial port with the IR (which
is powered down with the rest of the system).
• Modem ring (RI2#)
• Audio Codec event (SDATA_IN2)
• Programmable Consumer Electronics IR (CEIR)
address
Whenever an IR signal is detected, the receiver immedi-
ately enters the Active state. When this happens, the
receiver keeps sampling the IR input signal and generates
a bit string where a logic 1 indicates an idle condition and a
logic 0 indicates the presence of IR energy. The received
bit string is de-serialized and assembled into 8-bit charac-
ters.
Each system event that is monitored by the SWC is fed into
a dedicated detector that decides when the event is active,
according to predetermined (either fixed or programmable)
criteria. A set of dedicated registers is used to determine
the wakeup criteria, including the CEIR address.
A Wakeup Events Status Register (WKSR) and a Wakeup
Events Control Register (WKCR) hold a Status bit and
Enable bit, respectively, for each possible wakeup event.
The expected CEIR protocol of the received signal should
be configured through bits [5:4] of the CEIR Wakeup Con-
trol register (IRWCR) (see Table 4-30 on page 133).
Upon detection of an active event, the corresponding Sta-
tus bit is set to 1. If the event is enabled (the corresponding
Enable bit is set to 1), a power-up request is issued to the
ACPI controller. In addition, detection of an active wakeup
event may be also routed to an arbitrary IRQ.
The CEIR Wakeup Address register (IRWAD) holds the
unique address to be compared with the address contained
in the incoming CEIR message. If CEIR is enabled
(IRWCR[0] = 1) and an address match occurs, then the
CEIR Event Status bit of WKSR is set to 1.
Disabling an event prevents it from issuing power-up
requests, but does not affect the Status bits. A power-up
reset is issued to the ACPI controller when both the Status
and Enable bits are set to 1 for at least one event type.
The CEIR Address Shift register (ADSR) holds the
received address which is compared with the address con-
tained in the IRWAD. The comparison is affected also by
the CEIR Wakeup Address Mask register (IRWAM) in
which each bit determines whether to ignore the corre-
sponding bit in the IRWAD.
SWC logic is powered by VSB. The SWC control and con-
figuration registers are battery backed, powered by VPP
The setup of the wakeup events, including programmable
sequences, is retained throughout power failures (no VSB
.
If CEIR routing to interrupt request is enabled, the assigned
SWC interrupt request can be used to indicate that a com-
plete address has been received. To get this interrupt when
the address is completely received, IRWAM should be writ-
ten with FFh. Once the interrupt is received, the value of
the address can be read from ADSR.
)
as long as the battery is connected. VPP is taken from VSB
if VSB > 2.0; otherwise, VBAT is used as the VPP source.
Hardware reset does not affect the SWC registers. They
are reset only by a SIO software reset or power-up of VPP
.
Another parameter that is used to determine whether a
CEIR signal is to be considered valid is the bit cell time
width. There are four time ranges for the different protocols
and carrier frequencies. Four pairs of registers (IRWTRxL
and IRWTRxH) define the low and high limits of each time
range. Table 4-26 lists the recommended time ranges limits
for the different protocols and their applicable ranges. The
values are represented in hexadecimal code where the
units are of 0.1 ms.
4.6.1 Event Detection
4.6.1.1 Audio Codec Event
A low-to-high transition on SDATA_IN2 indicates the detec-
tion of an Audio Codec event and can be used as a wakeup
event.
Table 4-26. Time Range Limits for CEIR Protocols
RC-5 NEC
RCA
Time
Range
Low Limit
High Limit
Low Limit
High Limit
Low Limit
High Limit
0
1
2
3
10h
14h
09h
14h
50h
28h
0Dh
19h
64h
32h
0Ch
16h
B4h
23h
12h
1Ch
DCh
2Dh
07h
0Bh
-
-
-
-
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SuperI/O Module (Continued)
4.6.2 SWC Registers
• Bank 0 holds reserved registers.
The SWC registers are organized in two banks. The offsets
are related to a base address that is determined by the
SWC Base Address Register in the logical device configu-
ration. The lower three registers are common to the two
banks while the upper registers (03h-0Fh) are divided as
follows:
• Bank 1 holds the CEIR Control Registers.
The active bank is selected through the Configuration Bank
Select field (bits [1:0]) in the Wakeup Configuration Regis-
ter (WKCFG). See Table 4-29 on page 132.
The tables that follow provide register maps and bit defini-
tions for Banks 0 and 1.
Table 4-27. Banks 0 and 1 - Common Control and Status Register Map
Reset
Value
Offset
Type
Name
00h
01h
02h
R/W1C
R/W
WKSR. Wakeup Events Status Register
WKCR. Wakeup Events Control Register
WKCFG. Wakeup Configuration Register
00h
03h
00h
R/W
Table 4-28. Bank 1 - CEIR Wakeup Configuration and Control Register Map
Reset
Value
Offset
Type
Name
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
R/W
---
IRWCR. CEIR Wakeup Control Register
00h
---
RSVD. Reserved
R/W
R/W
RO
IRWAD. CEIR Wakeup Address Register
00h
E0h
00h
10h
14h
07h
0Bh
50h
64h
28h
32h
IRWAM. CEIR Wakeup Address Mask Register
ADSR. CEIR Address Shift Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IRWTR0L. CEIR Wakeup, Range 0, Low Limit Register
IRWTR0H. CEIR Wakeup, Range 0, High Limit Register
IRWTR1L. CEIR Wakeup, Range 1, Low Limit Register
IRWTR1H. CEIR Wakeup, Range 1, High Limit Register
IRWTR2L. CEIR Wakeup, Range 2, Low Limit Register
IRWTR2H. CEIR Wakeup, Range 2, High Limit Register
IRWTR3L. CEIR Wakeup, Range 3, Low Limit Register
IRWTR3H. CEIR Wakeup, Range 3, High Limit Register
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SuperI/O Module (Continued)
Table 4-29. Banks 0 and 1 - Common Control and Status Registers
Bit
Description
Offset 00h
Wakeup Events Status Register - WKSR (R/W1C)
Reset Value: 00h
This register is set to 00h on power-up of VPP or software reset. It indicates which wakeup event and/or PME occurred. (See
.)
7
6
5
Reserved.
Reserved. Must be set to 0.
IRRX1 (CEIR) Event Status. This sticky bit shows the status of the CEIR event detection.
0: Event not detected. (Default)
1: Event detected.
4:2
1
Reserved.
RI2# Event Status. This sticky bit shows the status of RI2# event detection.
0: Event not detected. (Default)
1: Event detected.
0
SDATA_IN2 Event Status. This sticky bit shows the status of Audio Codec event detection.
0: Event not detected. (Default)
1: Event detected.
Offset 01h
Wakeup Events Control Register - WKCR (R/W)
Reset Value: 03h
This register is set to 03h on power-up of VPP or software reset. Detected wakeup events that are enabled issue a power-up request the
ACPI controller and/or a PME to the Core Logic module. (See Section 5.2.9.4 "Power Management Events" on page 174.)
7
6
5
Reserved.
Reserved. Must be set to 0.
IRRX1 (CEIR) Event Enable.
0: Disable. (Default)
1: Enable.
4:2
1
Reserved.
RI2# Event Enable.
0: Disable.
1: Enable. (Default)
SDATA_IN2 Event Enable.
0: Disable.
0
1: Enable. (Default)
Offset 02h
Wakeup Configuration Register - WKCFG (R/W)
Reset Value: 00h
This register is set to 00h on power-up of VPP or software reset. It enables access to CEIR registers.
7:5
4
Reserved.
Reserved. Must be set to 0.
Reserved. Must be set to 0.
Reserved.
3
2
1:0
Configuration Bank Select Bits.
00: Only shared registers are accessible.
01: Shared registers and Bank 1 (CEIR) registers are accessible.
10: Bank selected.
11: Reserved.
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Table 4-30. Bank 1 - CEIR Wakeup Configuration and Control Registers
Bit
Description
Bank 1, Offset 03h
CEIR Wakeup Control Register - IRWCR (R/W)
Reset Value: 00h
This register is set to 00h on power-up of VPP or software reset.
7:6
5:4
Reserved.
CEIR Protocol Select.
00: RC5
01: NEC/RCA
1x: Reserved
Reserved.
3
2
Invert IRRX Input.
0: Not inverted. (Default)
1: Inverted.
1
0
Reserved.
CEIR Enable.
0: Disable. (Default)
1: Enable.
Bank 1, Offset 04h
Reserved
Bank 1, Offset 05h
CEIR Wakeup Address Register - IRWAD (R/W)
Reset Value: 00h
This register defines the station address to be compared with the address contained in the incoming CEIR message. If CEIR is enabled
(bit 0 of the IRWCR register is 1) and an address match occurs, then bit 5 of the WKSR register is set to 1.
This register is set to 00h on power-up of VPP or software reset.
7:0
CEIR Wakeup Address
Bank 1, Offset 06h
CEIR Wakeup Mask Register - IRWAM (R/W)
Reset Value: E0h
Each bit in this register determines whether the corresponding bit in the IRWAD register takes part in the address comparison. Bits 5, 6,
and 7 must be set to 1 if the RC-5 protocol is selected.
This register is set to E0h on power-up of VPP or software reset.
7:0
CEIR Wakeup Address Mask.
•
•
If the corresponding bit is 0, the address bit is not masked (enabled for compare).
If the corresponding bit is 1, the address bit is masked (ignored during compare).
Bank 1, Offset 07h
CEIR Address Shift Register - ADSR (RO)
Reset Value: 00h
This register holds the received address to be compared with the address contained in the IRWAD register.
This register is set to 00h on power-up of VPP or software reset.
7:0
CEIR Address.
CEIR Wakeup Range 0 Registers
These two registers (IRWTR0L and IRWTR0H) define the low and high limits of time range 0 (see Table 4-26 on page 130). The values
are represented in units of 0.1 ms.
•
RC-5 protocol: The bit cell width must fall within this range for the cell to be considered valid. The nominal cell width is 1.778 msec for
a 36 KHz carrier. IRWTR0L and IRWTR0H should be set to 10h and 14h, respectively. (Default)
•
NEC protocol: The time distance between two consecutive CEIR pulses that encodes a bit value of 0 must fall within this range. The
nominal distance for a 0 is 1.125 msec for a 38 KHz carrier. IRWTR0L and IRWTR0H should be set to 09h and 0Dh, respectively.
Bank 1, Offset 08h
IRWTR0L Register (R/W)
Reset Value: 10h
This register is set to 10h on power-up of VPP or software reset.
7:5
4:0
Reserved.
CEIR Pulse Change, Range 0, Low Limit.
Bank 1, Offset 09h
IRWTR0H Register (R/W)
Reset Value: 14h
This register is set to 14h on power-up of VPP or software reset.
7:5
4:0
Reserved.
CEIR Pulse Change, Range 0, High Limit.
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SuperI/O Module (Continued)
Table 4-30. Bank 1 - CEIR Wakeup Configuration and Control Registers (Continued)
Bit
Description
CEIR Wakeup Range 1 Registers
These two registers (IRWTR1L and IRWTR1H) define the low and high limits of time range 1 (see Table 4-26 on page 130). The values
are represented in units of 0.1 ms.
•
RC-5 protocol: The pulse width defining a half-bit cell must fall within this range in order for the cell to be considered valid. The
nominal pulse width is 0.889 for a 38 KHz carrier. IRWTR1L and IRWTR1H should be set to 07h and 0Bh, respectively. (Default)
•
NEC protocol: The time between two consecutive CEIR pulses that encodes a bit value of 1 must fall within this range. The nominal
time for a 1 is 2.25 msec for a 36 KHz carrier. IRWTR1L and IRWTR1H should be set to 14h and 19h, respectively.
Bank 1, Offset 0Ah
IRWTR1L Register (R/W)
Reset Value: 07h
This register is set to 07h on power-up of VPP or software reset.
7:5
4:0
Reserved.
CEIR Pulse Change, Range 1, Low Limit.
Bank 1, Offset 0Bh
IRWTR1H Register (R/W)
Reset Value: 0Bh
This register is set to 0Bh on power-up of VPP or software reset.
7:5
4:0
Reserved.
CEIR Pulse Change, Range 1, High Limit.
CEIR Wakeup Range 2 Registers
These two registers (IRWTR2L and IRWTR2H) define the low and high limits of time range 2 (see Table 4-26 on page 130). The values
are represented in units of 0.1 ms.
•
•
RC-5 protocol: These registers are not used when the RC-5 protocol is selected.
NEC protocol: The header pulse width must fall within this range in order for the header to be considered valid. The nominal value is
9 msec for a 38 KHz carrier. IRWTR2L and IRWTR2H should be set to 50h and 64h, respectively. (Default)
Bank 1, Offset 0Ch
IRWTR2L Register (R/W)
Reset Value: 50h
This register is set to 50h on power-up of VPP or software reset.
7:0 CEIR Pulse Change, Range 2, Low Limit.
Bank 1, Offset 0Dh IRWTR2H Register (R/W)
This register is set to 64h on power-up of VPP or software reset.
7:0 CEIR Pulse Change, Range 2, High Limit.
CEIR Wakeup Range 3 Registers
Reset Value: 64h
These two registers (IRWTR3L and IRWTR3H) define the low and high limits of time range 3 (see Table 4-26 on page 130). The values
are represented in units of 0.1 ms.
•
RC-5 protocol: These registers are not used when the RC-5 protocol is selected.
•
NEC protocol: The post header gap width must fall within this range in order for the gap to be considered valid. The nominal value is
4.5 msec for a 36 KHz carrier. IRWTR3L and IRWTR3H should be set to 28h and 32h, respectively. (Default)
Bank 1, Offset 0Eh
IRWTR3L Register (R/W)
Reset Value: 28h
This register is set to 28h on power-up of VPP or software reset.
7:0 CEIR Pulse Change, Range 3, Low Limit.
Bank 1, Offset 0Fh IRWTR3H Register (R/W)
This register is set to 32h on power-up of VPP or software reset.
7:0 CEIR Pulse Change, Range 3, High Limit.
Reset Value: 32h
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SuperI/O Module (Continued)
4.7 ACCESS.BUS INTERFACE
The SC1200/SC1201 has two ACCESS.bus (ACB) control-
lers. ACB is a two-wire synchronous serial interface com-
patible with the ACCESS.bus physical layer, Intel's SMBus,
and Philips’ I2C. The ACB can be configured as a bus mas-
ter or slave, and can maintain bidirectional communication
with both multiple master and slave devices. As a slave
device, the ACB may issue a request to become the bus
master.
During each clock cycle, the slave can stall the master
while it handles the previous data or prepares new data.
This can be done for each bit transferred, or on a byte
boundary, by the slave holding ABC low to extend the
clock-low period. Typically, slaves extend the first clock
cycle of a transfer if a byte read has not yet been stored, or
if the next byte to be transmitted is not yet ready. Some
microcontrollers, with limited hardware support for
ACCESS.bus, extend the access after each bit, thus allow-
ing the software to handle this bit.
The ACB allows easy interfacing to a wide range of low-
cost memories and I/O devices, including: EEPROMs,
SRAMs, timers, ADC, DAC, clock chips and peripheral driv-
ers.
The ACCESS.bus protocol uses a two-wire interface for
bidirectional communication between the ICs connected to
the bus. The two interface lines are the Serial Data Line
(AB1D and AB2D) and the Serial Clock Line (AB1C and
AB2C). (Here after referred to as ABD and ABC unless oth-
erwise specified.) These lines should be connected to a
positive supply via an internal or external pull-up resistor,
and remain high even when the bus is idle.
ABD
ABC
Data Line
Stable:
Data Valid Allowed
Change
of Data
Figure 4-13. Bit Transfer
Each IC has a unique address and can operate as a trans-
mitter or a receiver (though some peripherals are only
receivers).
4.7.2 Start and Stop Conditions
The ACCESS.bus master generates Start and Stop Condi-
tions (control codes). After a Start Condition is generated,
the bus is considered busy and retains this status for a cer-
tain time after a Stop Condition is generated. A high-to-low
transition of the data line (ABD) while the clock (ABC) is
high indicates a Start Condition. A low-to-high transition of
the ABD line while the ABC is high indicates a Stop Condi-
tion (Figure 4-14).
During data transactions, the master device initiates the
transaction, generates the clock signal and terminates the
transaction. For example, when the ACB initiates a data
transaction with an attached ACCESS.bus compliant
peripheral, the ACB becomes the master. When the periph-
eral responds and transmits data to the ACB, their mas-
ter/slave (data transaction initiator and clock generator)
relationship is unchanged, even though their transmit-
ter/receiver functions are reversed.
In addition to the first Start Condition, a repeated Start
Condition can be generated in the middle of a transaction.
This allows another device to be accessed, or a change in
the direction of data transfer.
This section describes the general ACB functional block. A
device may include a different implementation. For device
specific implementation, see Section 4.4.2.5 "LDN 05h and
06h - ACCESS.bus Ports 1 and 2" on page 117.
4.7.1 Data Transactions
One data bit is transferred during each clock pulse. Data is
sampled during the high state of the serial clock (ABC).
Consequently, throughout the clock’s high period, the data
should remain stable (see Figure 4-13). Any changes on
the ABD line during the high state of the ABC and in the
middle of a transaction aborts the current transaction. New
data should be sent during the low ABC state. This protocol
permits a single data line to transfer both command/control
information and data, using the synchronous serial clock.
ABD
ABC
S
P
Start
Condition
Stop
Condition
Figure 4-14. Start and Stop Conditions
Each data transaction is composed of a Start Condition, a
number of byte transfers (set by the software) and a Stop
Condition to terminate the transaction. Each byte is trans-
ferred with the most significant bit first, and after each byte
(8 bits), an Acknowledge signal must follow. The following
sections provide further details of this process.
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4.7.3 Acknowledge (ACK) Cycle
the ABD line (permits it to go high) to allow the receiver to
send the ACK signal. The receiver must pull down the ABD
line during the ACK clock pulse, signalling that it has cor-
rectly received the last data byte and is ready to receive the
next byte. Figure 4-16 illustrates the ACK cycle.
The ACK cycle consists of two signals: the ACK clock pulse
sent by the master with each byte transferred, and the ACK
signal sent by the receiving device (see Figure 4-15).
The master generates the ACK clock pulse on the ninth
clock pulse of the byte transfer. The transmitter releases
Acknowledge
Signal From Receiver
ABD
MSB
ABC
3 - 6
9
ACK
8
1
2
7
9
ACK
1
2
3 - 8
P
S
Start
Condition
Stop
Condition
Clock Line Held
Low by Receiver
While Interrupt
is Serviced
Byte Complete
Interrupt Within
Receiver
Figure 4-15. ACCESS.bus Data Transaction
Data Output
by Transmitter
Transmitter Stays Off Bus
During Acknowledge Clock
Data Output
by Receiver
Acknowledge
Signal From Receiver
ABC
3 - 6
8
1
2
7
9
S
Start
Condition
Figure 4-16. ACCESS.bus Acknowledge Cycle
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4.7.4 Acknowledge After Every Byte Rule
4.7.6 Arbitration on the Bus
According to this rule, the master generates an acknowl-
edge clock pulse after each byte transfer, and the receiver
sends an acknowledge signal after every byte received.
There are two exceptions to this rule:
Multiple master devices on the bus require arbitration
between their conflicting bus access demands. Control of
the bus is initially determined according to address bits and
clock cycle. If the masters are trying to address the same
slave, data comparisons determine the outcome of this
arbitration. In master mode, the device immediately aborts
a transaction if the value sampled on the ABD line differs
from the value driven by the device. (An exception to this
rule is ABD while receiving data. The lines may be driven
low by the slave without causing an abort.)
• When the master is the receiver, it must indicate to the
transmitter the end of data by not acknowledging (nega-
tive acknowledge) the last byte clocked out of the slave.
This negative acknowledge still includes the acknowl-
edge clock pulse (generated by the master), but the
ABD line is not pulled down.
The ABC signal is monitored for clock synchronization and
to allow the slave to stall the bus. The actual clock period is
set by the master with the longest clock period, or by the
slave stall period. The clock high period is determined by
the master with the shortest clock high period.
• When the receiver is full, otherwise occupied, or a
problem has occurred, it sends a negative acknowledge
to indicate that it cannot accept additional data bytes.
4.7.5 Addressing Transfer Formats
Each device on the bus has a unique address. Before any
data is transmitted, the master transmits the address of the
slave being addressed. The slave device should send an
acknowledge signal on the ABD line, once it recognizes its
address.
When an abort occurs during the address transmission, a
master that identifies the conflict should give up the bus,
switch to slave mode and continue to sample ABD to check
if it is being addressed by the winning master on the bus.
4.7.7 Master Mode
The address consists of the first 7 bits after a Start Condi-
tion. The direction of the data transfer (R/W#) depends on
the bit sent after the address, the eighth bit. A low-to-high
transition during a ABC high period indicates the Stop Con-
dition, and ends the transaction of ABD (see Figure 4-17).
Requesting Bus Mastership
An ACCESS.bus transaction starts with a master device
requesting bus mastership. It asserts a Start Condition, fol-
lowed by the address of the device it wants to access. If
this transaction is successfully completed, the software
may assume that the device has become the bus master.
When the address is sent, each device in the system com-
pares this address with its own. If there is a match, the
device considers itself addressed and sends an acknowl-
edge signal. Depending on the state of the R/W# bit (1 =
Read, 0 = Write), the device acts either as a transmitter or
a receiver.
For the device to become the bus master, the software
should perform the following steps:
1) Configure ACBCTL1[2] to the desired operation mode.
(Polling or Interrupt) and set the ACBCTL1[0]. This
causes the ACB to issue a Start Condition on the
ACCESS.bus when the ACCESS.bus becomes free
(ACBCST[1] is cleared, or other conditions that can
delay start). It then stalls the bus by holding ABC low.
The I2C bus protocol allows a general call address to be
sent to all slaves connected to the bus. The first byte sent
specifies the general call address (00h) and the second
byte specifies the meaning of the general call (for example,
write slave address by software only). Those slaves that
require data acknowledge the call, and become slave
receivers; other slaves ignore the call.
2) If a bus conflict is detected (i.e., another device pulls
down the ABC signal), the ACBST[5] is set.
3) If there is no bus conflict, ACBST[1] and ACBST[6] are
set.
4) If the ACBCTL1[2] is set and either ACBST[5] or
ACBST[6] is set, an interrupt is issued.
ABD
ABC
9
9
9
8
8
8
1 - 7
1 - 7
Data
1 - 7
Data
P
S
Start
Condition
Stop
Condition
Address
ACK
ACK
R/W
ACK
Figure 4-17. A Complete ACCESS.bus Data Transaction
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Sending the Address Byte
Master Receive
When the device is the active master of the ACCESS.bus
(ACBST[1] is set), it can send the address on the bus.
After becoming the bus master, the device can start receiv-
ing data on the ACCESS.bus.
The address sent should not be the device’s own address,
as defined by ACBADDR[6:0] if ACBADDR[7] is set, nor
should it be the global call address if ACBST[3] is set.
To receive a byte in an interrupt or polling operation, the
software should:
1) Check that ACBST[6] is set and that ACBST[5] is
cleared. If ACBCTL1[7] is set, also check that the
ACBST[3] is cleared (and clear it if required).
To send the address byte, use the following sequence:
1) For a receive transaction where the software wants
only one byte of data, it should set ACBCTL1[4]. If only
an address needs to be sent or if the device requires
stall for some other reason, set ACBCTL1[7].
2) Set ACBCTL1[4] to 1, if the next byte is the last byte
that should be read. This causes a negative acknowl-
edge to be sent.
2) Write the address byte (7-bit target device address)
and the direction bit to the ACBSDA register. This
causes the ACB to generate a transaction. At the end
of this transaction, the acknowledge bit received is
copied to ACBST[4]. During the transaction, the ABD
and ABC lines are continuously checked for conflict
with other devices. If a conflict is detected, the transac-
tion is aborted, ACBST[5] is set and ACBST[1] is
cleared.
3) Read the data byte from the ACBSDA.
Before receiving the last byte of data, set ACBCTL1[4].
4.7.7.1 Master Stop
To end a transaction, set the ACBCTL1[1] before clearing
the current stall flag (i.e., ACBST[6], ACBST[4], or
ACBST[3]). This causes the ACB to send a Stop Condition
immediately, and to clear ACBCTL1[1]. A Stop Condition
may be issued only when the device is the active bus mas-
ter (i.e., ACBST[1] is set).
3) If ACBCTL1[7] is set and the transaction was success-
fully completed (i.e., both ACBST[5] and ACBST[4] are
cleared), ACBST[3] is set. In this case, the ACB stalls
any further ACCESS.bus operations (i.e., holds ABC
low). If ACBCTL1[2] is set, it also sends an interrupt
request to the host.
Master Bus Stall
The ACB can stall the ACCESS.bus between transfers
while waiting for the host response. The ACCESS.bus is
stalled by holding the AB1C signal low after the acknowl-
edge cycle. Note that this is interpreted as the beginning of
the following bus operation. The user must make sure that
the next operation is prepared before the flag that causes
the bus stall is cleared.
4) If the requested direction is transmit and the start
transaction was completed successfully (i.e., neither
ACBST[5] nor ACBST[4] is set, and no other master
has accessed the device), ACBST[6] is set to indicate
that the ACB awaits attention.
The flags that can cause a bus stall in master mode are:
5) If the requested direction is receive, the start transac-
tion was completed successfully and ACBCTL1[7] is
cleared, the ACB starts receiving the first byte auto-
matically.
• Negative acknowledge after sending a byte (ACBST[4] =
1).
• ACBST[6] bit is set.
• ACBCTL1[7] = 1, after a successful start (ACBST[3] =
6) Check that both ACBST[5] and ACBST[4] are cleared.
If ACBCTL1[2] is set, an interrupt is generated when
ACBST[5] or ACBST[4] is set.
1).
Repeated Start
A repeated start is performed when the device is already
the bus master (ACBST[1] is set). In this case, the
ACCESS.bus is stalled and the ACB awaits host handling
due to: negative acknowledge (ACBST[4] = 1), empty
buffer (ACBST[6] = 1) and/or a stall after start (ACBST[3]
1).
Master Transmit
After becoming the bus master, the device can start trans-
mitting data on the ACCESS.bus.
To transmit a byte in an interrupt or polling controlled oper-
ation, the software should:
1) Check that both ACBST[5] and ACBST[4] are cleared,
and that ACBST[6] is set. If ACBCTL1[7] is set, also
check that ACBST[3] is cleared (and clear it if
required).
For a repeated start:
1) Set \ACBCTL1[0] to 1.
2) In master receive mode, read the last data item from
ACBSDA.
2) Write the data byte to be transmitted to the ACBSDA.
3) Follow the address send sequence, as described pre-
viously in "Sending the Address Byte". If the ACB was
awaiting handling due to ACBST[3] = 1, clear it only
after writing the requested address and direction to
ACBSDA.
When either ACBST[5] or ACBST[4] is set, an interrupt is
generated. When the slave responds with a negative
acknowledge, ACBST[4] Register is set and ACBST[6]
remains cleared. In this case, if ACBCTL1[2] Register is
set, an interrupt is issued.
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Master Error Detection
3) If ACBCTL1[2] is set, an interrupt is generated if both
ACBCTL1[2] and ACBCTL16 are set.
The ACB detects illegal Start or Stop Conditions (i.e., a
Start or Stop Condition within the data transfer, or the
acknowledge cycle) and a conflict on the data lines of the
ACCESS.bus. If an illegal condition is detected, ACBST[5]
is set, and master mode is exited (ACBST[1] is cleared).
4) The software then reads ACBST[0] to identify the
direction requested by the master device. It clears
ACBST[2] so future byte transfers are identified as
data bytes.
Bus Idle Error Recovery
Slave Receive and Transmit
When a request to become the active bus master or a
restart operation fails, ACBST[5] is set to indicate the error.
In some cases, both the device and the other device may
identify the failure and leave the bus idle. In this case, the
start sequence may be incomplete and the ACCESS.bus
may remain deadlocked.
Slave receive and transmit are performed after a match is
detected and the data transfer direction is identified. After a
byte transfer, the ACB extends the acknowledge clock until
the software reads or writes ACBSDA. The receive and
transmit sequences are identical to those used in the mas-
ter routine.
To recover from deadlock, use the following sequence:
1) Clear ACBST[5] and ACBCST[1].
Slave Bus Stall
When operating as
a slave, the device stalls the
ACCESS.bus by extending the first clock cycle of a trans-
action in the following cases:
2) Wait for a timeout period to check that there is no other
active master on the bus (i.e., ACBCST[1] remains
cleared).
• ACBST[6] is set.
3) Disable, and re-enable the ACB to put it in the non-
addressed slave mode. This completely resets the
functional block.
• ACBST[2] and ACBCTL1[6] are set.
Slave Error Detection
The ACB detects illegal Start and Stop Conditions on the
ACCESS.bus (i.e., a Start or Stop Condition within the data
transfer or the acknowledge cycle). When this occurs,
ACBST[5] is set and ACBCST[3:2] are cleared, setting the
ACB as an unaddressed slave.
At this point, some of the slaves may not identify the bus
error. To recover, the ACB becomes the bus master: it
asserts a Start Condition, sends an address byte, then
asserts a Stop Condition which synchronizes all the slaves.
4.7.8 Slave Mode
4.7.9 Configuration
A slave device waits in idle mode for a master to initiate a
bus transaction. Whenever the ACB is enabled and it is not
acting as a master (i.e., ACBST[1] is cleared), it acts as a
slave device.
ABD and ABC Signals
The ABD and ABC are open-drain signals. The device per-
mits the user to define whether to enable or disable the
internal pull-up of each of these signals.
Once a Start Condition on the bus is detected, the device
checks whether the address sent by the current master
matches either:
ACB Clock Frequency
The ACB permits the user to set the clock frequency for the
ACCESS.bus clock. The clock is set by the ACBCTL2[7:1],
which determines the ABC clock period used by the device.
This clock low period may be extended by stall periods initi-
ated by the ACB or by another ACCESS.bus device. In
case of a conflict with another bus master, a shorter clock
high period may be forced by the other bus master until the
conflict is resolved.
• The ACBADDR[6:0] value if ACBADDR[7] = 1.
or
• The general call address if ACBCTL1[5] 1.
This match is checked even when ACBST[1] is set. If a bus
conflict (on ABD or ABC) is detected, ACBST[5] is set,
ACBST[1] is cleared and the device continues to search
the received message for a match.
If an address match or a global match is detected:
1) The device asserts its ABD pin during the acknowl-
edge cycle.
2) ACBCST[2] and ACBST[2] are set. If ACBST[0] = 1
(i.e., slave transmit mode) ACBST[6] is set to indicate
that the buffer is empty.
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4.7.10 ACB Registers
as LDN 05h and ACCESS.bus Port 2 as LDN 06h. In addi-
tion to the registers listed here, there are additional config-
uration registers listed in Section 4.4.2.5 "LDN 05h and 06h
- ACCESS.bus Ports 1 and 2" on page 117.
Each functional block is associated with a Logical Device
Number (LDN) (see Section 4.3.2 "Banked Logical Device
Registers" on page 106). ACCESS.Bus Port 1 is assigned
Table 4-31. ACB Register Map
Reset
Value
Offset
Type
Name
00h
01h
02h
03h
04h
05h
R/W
R/W
R/W
R/W
R/W
R/W
ACBSDA. ACB Serial Data
ACBST. ACB Status
xxh
00h
00h
00h
xxh
00h
ACBCST. ACB Control Status
ACBCTL1. ACB Control 1
ACBADDR. ACB Own Address
ACBCTL2. ACB Control 2
Table 4-32. ACB Registers
Bit
Description
Offset 00h
ACB Serial Data Register - ACBSDA (R/W)
Reset Value: xxh
7:0
ACB Serial Data. This shift register is used to transmit and receive data. The most significant bit is transmitted (received)
first, and the least significant bit is transmitted last. Reading or writing to ACBSDA is allowed only when ACBST[6] is set, or
for repeated starts after setting the ACBCTL1[0]. An attempt to access the register in other cases may produce unpredict-
able results.
Offset 01h
ACB Status Register - ACBST (R/W)
Reset Value: 00h
This is a read register with a special clear. Some of its bits may be cleared by software, as described below. This register maintains the
current ACB status. On reset, and when the ACB is disabled, ACBST is cleared (00h).
7
6
SLVSTP (Slave Stop). (R/W1C) Writing 0 to SLVSTP is ignored.
0: Writing 1 or ACB disabled.
1: Stop Condition detected after a slave transfer in which ACBCST[2] or ACBCST[3] was set.
SDAST (SDA Status). (RO)
0: Reading from ACBSDA during a receive, or when writing to it during a transmit. When ACBCTL1[0] is set, reading ACB-
SDA does not clear SDAST. This enables ACB to send a repeated start in master receive mode.
1: SDA Data Register awaiting data (transmit - master or slave) or holds data that should be read (receive - master or
slave).
5
BER (Bus Error). (R/W1C) Writing 0 to this bit is ignored.
0: Writing 1 or ACB disabled.
1: Start or Stop Condition detected during data transfer (i.e., Start or Stop Condition during the transfer of bits [8:2] and
acknowledge cycle), or when an arbitration problem detected.
4
3
NEGACK (Negative Acknowledge). (R/W1C) Writing 0 to this bit is ignored.
0: Writing 1 or ACB disabled.
1: Transmission not acknowledged on the ninth clock (In this case, SDAST (bit 6) is not set).
STASTR (Stall After Start). (R/W1C) Writing 0 to this bit is ignored.
0: Writing 1 or ACB disabled.
1: Address sent successfully (i.e., a Start Condition sent without a bus error, or Negative Acknowledge), if ACBCTL1[7] is
set. This bit is ignored in slave mode. When STASTR is set, it stalls the ACCESS.bus by pulling down the ABC line, and
suspends any further action on the bus (e.g., receive of first byte in master receive mode). In addition, if ACBCTL1[1] is
set, it also causes the ACB to send an interrupt.
2
NMATCH (New Match). (R/W1C) Writing 0 to this bit is ignored. If ACBCTL1[2] is set, an interrupt is sent when this bit is
set.
0: Software writes 1 to this bit.
1: Address byte follows a Start Condition or a repeated start, causing a match or a global-call match.
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Table 4-32. ACB Registers (Continued)
Bit
Description
1
MASTER. (RO)
0: Arbitration loss (BER, bit 5, is set) or recognition of a Stop Condition.
1: Bus master request succeeded and master mode active.
XMIT (Transmit). (RO) Direction bit.
0
0: Master/slave transmit mode not active.
1: Master/slave transmit mode active.
Offset 02h
ACB Control Status Register - ACBCST (R/W)
Reset Value: 00h
This register configures and controls the ACB functional block. It maintains the current ACB status and controls several ACB functions.
On reset and when the ACB is disabled, the non-reserved bits of ACBCST are cleared.
7:6
5
Reserved.
TGABC (Toggle ABC Line). (R/W) Enables toggling the ABC line during error recovery.
0: Clock toggle completed.
1: When the ABD line is low, writing 1 to this bit toggles the ABC line for one cycle. Writing 1 to TGABC while ABD is high
is ignored.
4
3
TSDA (Test ABD Line). (RO) Reads the current value of the ABD line. It can be used while recovering from an error condi-
tion in which the ABD line is constantly pulled low by an out-of-sync slave. Data written to this bit is ignored.
GCMTCH (Global Call Match). (RO)
0: Start Condition or repeated Start and a Stop Condition (including illegal Start or Stop Condition).
1: In slave mode, ACBCTL1.GCMEN is set and the address byte (the first byte transferred after a Start Condition) is 00h.
MATCH (Address Match). (RO)
2
0: Start Condition or repeated Start and a Stop Condition (including illegal Start or Stop Condition).
1: ACBADDR[7] is set and the first 7 bits of the address byte (the first byte transferred after a Start Condition) match the 7-
bit address in ACBADDR.
1
0
BB (Bus Busy). (R/W1C)
0: Writing 1, ACB disabled, or Stop Condition detected.
1: Bus active (a low level on either ABD or ABC), or Start Condition.
BUSY. (RO) This bit should always be written 0. This bit indicates the period between detecting a Start Condition and com-
pleting receipt of the address byte. After this, the ACB is either free or enters slave mode.
0: Completion of any state below or ACB disabled.
1: ACB is in one of the following states:
-Generating a Start Condition
-Master mode (ACBST[1] is set)
-Slave mode (ACBCST[2] or ACBCST[3] set).
Offset 03h
ACB Control Register 1 - ACBCTL1 (R/W)
STASTRE (Stall After Start Enable).
Reset Value: 00h
7
0: When cleared, ACBST[3] can not be set. However, if ACBST[3] is set, clearing STASTRE does not clear ACBST[3].
1: Stall after start mechanism enabled, and ACB stalls the bus after the address byte.
NMINTE (New Match Interrupt Enable).
6
5
4
0: No interrupt issued on a new match.
1: Interrupt issued on a new match only if ACBCTL1[2] set.
GCMEN (Global Call Match Enable).
0: Global call match disabled.
1: Global call match enabled.
ACK (Acknowledge). This bit is ignored in transmit mode. When the device acts as a receiver (slave or master), this bit
holds the stop transmitting instruction that is transmitted during the next acknowledge cycle.
0: Cleared after acknowledge cycle.
1: Negative acknowledge issued on next received byte.
Reserved.
3
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SuperI/O Module (Continued)
Table 4-32. ACB Registers (Continued)
Bit
Description
2
INTEN (Interrupt Enable).
0: ACB interrupt disabled.
1: ACB interrupt enabled. An interrupt is generated in response to one of the following events:
-Detection of an address match (ACBST[2] = 1) and ACBCTL1[6] = 1.
-Receipt of Bus Error (ACBST[5] = 1).
-Receipt of Negative Acknowledge after sending a byte (ACBST[4] = 1).
-Acknowledge of each transaction (same as the hardware set of the ACBST[6]).
-In master mode if ACBCTL1[7] = 1, after a successful start (ACBST[3] = 1).
-Detection of a Stop Condition while in slave mode (ACBST[7] = 1).
1
0
STOP (Stop).
0: Automatically cleared after Stop issued.
1: Setting this bit in master mode generates a Stop Condition to complete or abort current message transfer.
START (Start). Set this bit only when in master mode or when requesting master mode.
0: Cleared after Start Condition sent or Bus Error (ACBST[5] = 1) detected.
1: Single or repeated Start Condition generated on the ACCESS.bus. If the device is not the active master of the bus
(ACBST[1] = 0), setting START generates a Start Condition when the ACCESS.bus becomes free (ACBCST[1] = 0). An
address transmission sequence should then be performed.
If the device is the active master of the bus (ACBST[1] = 1), setting START and then writing to ACBSDA generates a
Start Condition. If a transmission is already in progress, a repeated Start Condition is generated. This condition can be
used to switch the direction of the data flow between the master and the slave, or to choose another slave device without
separating them with a Stop Condition.
Offset 04h
ACB Own Address Register - ACBADDR (R/W)
SAEN (Slave Address Enable).
Reset Value: xxh
7
0: ACB does not check for an address match with ACBADDR[6:0].
1: ACBADDR[6:0] holds a valid address and enables the match of ADDR to an incoming address byte.
6:0
ADDR (Address). These bits hold the 7-bit device address of the SC1200/SC1201. When in slave mode, the first 7 bits
received after a Start Condition are compared with this field (first bit received is compared with bit 6, and the last bit with bit
0). If the address field matches the received data and ACBADDR[7] is 1, a match is declared.
Offset 05h
ACB Control Register 2 - ACBCTL2 (R/W)
Reset Value: 00h
This register enables/disables the functional block and determines the ACB clock rate.
7:1
ABCFRQ (ABC Frequency). This field defines the ABC period (low and high time) when the device serves as a bus master.
The clock low and high times are defined as follows:
tABCl = tABCh = 2*ABCFRQ*tCLK
where tCLK is the module input clock cycle, as defined in the Section 4.2 "Module Architecture" on page 105.
ABCFRQ can be programmed to values in the range of 0001000b through 1111111b. Using any other value has unpredict-
able results.
0
EN (Enable).
0: ACB is disabled, ACBCTL1, ACBST and ACBCST registers are cleared, and clocks are halted.
1: ACB is enabled.
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4.8 LEGACY FUNCTIONAL BLOCKS
This section briefly describes the following blocks that pro-
vide legacy device functions:
The description of each Legacy block includes a general
description, register maps, and bit maps. For more informa-
tion about legacy blocks, contact your National Semicon-
ductor representative.
• Parallel Port.
• Serial Port 1 and Serial Port 2 (SP1 and SP2), UART
4.8.1 Parallel Port
functionality for both SP1 and SP2.
The Parallel Port supports all IEEE1284 standard commu-
nication modes: Compatibility (known also as Standard or
SPP), Bidirectional (known also as PS/2), FIFO, EPP
(known also as Mode 4) and ECP (with an optional
Extended ECP mode).
• Infrared Communications Port / Serial Port 3 function-
ality.
Notes
• SP1 and SP2 are similar to SCC1 in the National
4.8.1.1 Parallel Port Register and Bit Maps
PC87338 device.
The Parallel Port register maps (Table 4-33 and Table 4-34)
are grouped according to first and second level offsets.
EPP and second level offset registers are available only
when the base address is 8-byte aligned.
• The Parallel Port is similar to Parallel Port in the National
PC87338 device.
• The IR Communications Port is similar to SCC2 in the
National PC87338 device.
Parallel Port functional block bit maps are shown in Table 4-
35 and Table 4-36.
Table 4-33. Parallel Port Register Map for First Level Offset
First Level Offset
Type
Name
Modes (ECR Bits) 7 6 5
000h
000h
001h
002h
003h
004h
005h
006h
007h
400h
400h
400h
400h
401h
402h
403h
404h
405h
R/W
W
DATAR. PP Data
000 or 001
011
AFIFO. ECP Address FIFO
DSR. Status
RO
All Modes
All Modes
100
R/W
R/W
R/W
R/W
R/W
R/W
W
DCR. Control
ADDR. EPP Address
DATA0. EPP Data Port 0
DATA1. EPP Data Port 1
DATA2. EPP Data Port 2
DATA3. EPP Data Port 3
CFIFO. PP Data FIFO
DFIFO. ECP Data FIFO
TFIFO. Test FIFO
100
100
100
100
010
R/W
R/W
RO
011
110
CNFGA. Configuration A
CNFGB. Configuration B
ECR. Extended Control
EIR. Extended Index
EDR. Extended Data
EAR. Extended Auxiliary Status
111
RO
111
R/W
R/W
R/W
R/W
All Modes
All Modes
All Modes
All Modes
Table 4-34. Parallel Port Register Map for Second Level Offset
Second Level Offset
Type
Name
00h
02h
04h
05h
R/W
R/W
R/W
R/W
Control0. Control Register 0
Control2. Control Register 2
Control4. Control Register 4
PP Confg0. Parallel Port Configuration Register 0
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SuperI/O Module (Continued)
Table 4-35. Parallel Port Bit Map for First Level Offset
Bits
Offset
Name
7
6
5
4
3
2
1
0
000h
DATAR
AFIFO
DSR
Data Bits
Address Bits
001h
002h
Printer
Status
ACK#
Status
PE
Status
SLCT
Status
ERR#
Status
RSVD
EPP
Timeout
Status
DCR
RSVD
Direction
Control
Interrupt
Enable
PP Input
Control
Printer Ini- Automatic
Data
tialization
Control
Line Feed
Control
Strobe
Control
003h
004h
005h
006h
007h
400h
400h
400h
400h
ADDR
DATA0
DATA1
DATA2
DATA3
CFIFO
DFIFO
TFIFO
CNFGA
EPP Device or Register Selection Address Bits
EPP Device or R/W Data
EPP Device or R/W Data
EPP Device or R/W Data
EPP Device or R/W Data
Data Bits
Data Bits
Data Bits
RSVD
Bit 7 of PP
Confg0
RSVD
401h
402h
CNFGB
ECR
RSVD
Interrupt
Request
Value
Interrupt Select
RSVD
DMA Channel Select
ECP Mode Control
ECP Inter- ECP DMA ECP Inter-
rupt Mask
FIFO
Full
FIFO
Empty
Enable
rupt Ser-
vice
403h
404h
405h
EIR
EDR
EAR
RSVD
Second Level Offset
Data Bits
RSVD
FIFO Tag
Table 4-36. Parallel Port Bit Map for Second Level Offset
Bits
Offset
Name
7
6
5
4
3
2
1
0
00h
Control0
RSVD
DCR Reg- Freeze Bit
ister Live
RSVD
EPP Time-
out Inter-
rupt Mask
02h
Control2
SPP Com-
patibility
Channel
Address
Enable
RSVD
Revision
1.7 or 1.9
Select
RSVD
04h
05h
Control4
RSVD
PP DMA Request Inactive Time
RSVD
PP DMA Request Active Time
PP Confg0
Bit 3 of
CNFGA
Demand
DMA
ECP IRQ Channel Number
PE Inter-
ECP DMA Channel
Number
nal PU or
PD
Enable
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Revision 6.0
SuperI/O Module (Continued)
4.8.2 UART Functionality (SP1 and SP2)
Both SP1 and SP2 provide UART functionality. The generic
SP1 and SP2 support serial data communication with
remote peripheral device or modem using a wired inter-
face. The functional blocks can function as a standard
16450, 16550, or as an Extended UART.
Bank 3
Bank 2
Bank 1
Common
Register
Throughout
All Banks
Bank 0
4.8.2.1 UART Mode Register Bank Overview
Four register banks, each containing eight registers, control
UART operation. All registers use the same 8-byte address
space to indicate offsets 00h through 07h. The BSR regis-
ter selects the active bank and is common to all banks. See
Figure 4-18.
Offset 07h
Offset 06h
Offset 05h
Offset 04h
4.8.2.2 SP1 and SP2 Register and Bit Maps for UART
Functionality
The tables in this subsection provide register and bit maps
for Banks 0 through 3.
LCR/BSR
Offset 02h
Offset 01h
Offset 00h
16550 Banks
Figure 4-18. UART Mode Register Bank
Architecture
Table 4-37. Bank 0 Register Map
Name
Offset
Type
00h
RO
W
RXD. Receiver Data Port
TXD. Transmitter Data Port
IER. Interrupt Enable
01h
02h
R/W
RO
R/W
W
EIR. Event Identification (Read Cycles)
FCR. FIFO Control (Write Cycles)
LCR1. Line Control
03h
BSR1.Bank Select
R/W
04h
05h
06h
07h
R/W
R/W
R/W
R/W
R/W
MCR. Modem/Mode Control
LSR. Link Status
MSR. Modem Status
SPR. Scratchpad
ASCR. Auxiliary Status and Control
1. When bit 7 of this register is set to 1, bits [6:0] of BSR select the bank, as shown in Table 4-38.
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SuperI/O Module (Continued)
Table 4-38. Bank Selection Encoding
BSR Bits
7
6
5
4
3
2
1
0
Bank Selected
0
1
1
1
1
1
x
0
1
1
1
1
x
x
x
x
1
1
x
x
x
x
0
0
x
x
x
x
0
0
x
x
x
x
0
1
x
x
1
x
0
0
x
x
x
1
0
0
0
1
1
1
2
3
Table 4-39. Bank 1 Register Map
Name
Offset
Type
00h
01h
02h
03h
R/W
R/W
---
LBGD(L). Legacy Baud Generator Divisor Port (Low Byte)
LBGD(H). Legacy Baud Generator Divisor Port (High Byte)
RSVD. Reserved
LCR1. Line Control
W
BSR1. Bank Select
RSVD. Reserved
R/W
---
04h-07h
1. When bit 7 of this register is set to 1, bits [6:0] of BSR select the bank, as shown in Table 4-38 on page 146.
Table 4-40. Bank 2 Register Map
Offset
Type
Name
00h
01h
02h
03h
04h
05h
06h
07h
R/W
R/W
R/W
R/W
R/W
---
BGD(L). Baud Generator Divisor Port (Low Byte)
BGD(H). Baud Generator Divisor Port (High Byte)
EXCR1. Extended Control1
BSR. Bank Select
EXCR2. Extended Control 2
RSVD. Reserved
RO
RXFLV. RX_FIFO Level
RO
TXFLV. TX_FIFO Level
Table 4-41. Bank 3 Register Map
Name
Offset
Type
00h
01h
RO
RO
RO
R/W
---
MRID. Module and Revision ID
SH_LCR. Shadow of LCR
SH_FCR. Shadow of FIFO Control
BSR. Bank Select
02h
03h
04h-07h
RSVD. Reserved
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Revision 6.0
SuperI/O Module (Continued)
Table 4-42. Bank 0 Bit Map
Register
Bits
Offset
Name
7
6
5
4
3
2
1
0
00h
RXD
TXD
RXD[7:0] (Receiver Data Bits)
TXD[7:0] (Transmitter Data Bits)
MS_IE
IER1
IER2
01h
02h
RSVD
TXEMP_IE
LS_IE
LS_IE
TXLDL_IE RXHDL_IE
TXLDL_IE RXHDL_IE
RSVD3/
RSVD
MS_IE
DMA_IE4
EIR1
EIR2
FEN[1:0]
RSVD
RSVD
RXFT
IPR1
IPR0
IPF
RSVD 3/
TXEMP_EV
MS_EV
LS_EV or
TXLDL_EV RXHDL_EV
TXHLT_EV
DMA_EV 4
FCR
LCR5
BSR5
MCR1
RXFTH[1:0]
TXFTH[1:0]
RSVD
PEN
TXSR
STB
RXSR
FIFO_EN
03h
04h
BKSE
BKSE
SBRK
STKP
EPS
WLS[1:0]
BSR[6:0] (Bank Select)
RSVD
LOOP
ISEN or
DCDLP
RILP
RTS
RTS
DTR
DTR
MCR2
LSR
RSVD
TX_DFR
RSVD
05h
06h
07h
ER_INF
DCD
TXEMP
RI
TXRDY
DSR
BRK
CTS
FE
PE
OE
RXDA
DCTS
MSR
DDCD
TERI
DDSR
SPR1
Scratch Data
ASCR2
TXUR4
RXACT4
RXWDG4
S_OET4
RSVD
RSVD
RSVD
RXF_TOUT
1. Non-Extended Mode.
2. Extended Mode.
3. In SP1 only.
4. In SP2 only.
5. When bit 7 of this register is set to 1, bits [6:0] of BSR select the bank, as shown in Table 4-38 on page 146.
Table 4-43. Bank 1 Bit Map
Register
Name
Bits
Offset
7
6
5
4
3
2
1
0
00h
01h
02h
03h
LBGD(L)
LBGD(H)
RSVD
LBGD[7:0] (Low Byte)
LBGD[15:8] (High Byte)
Reserved
LCR1
BKSE
BKSE
SBRK
STKP
EPS
PEN
STB
WLS[1:0]
BSR1
BSR[6:0] (Bank Select)
Reserved
04h-07h
RSVD
1. When bit 7 of this register is set to 1, bits [6:0] of BSR select the bank, as shown in Table 4-38 on page 146.
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SuperI/O Module (Continued)
Table 4-44. Bank 2 Bit Map
Register
Bits
Offset
Name
7
6
5
4
3
2
1
0
00h
01h
02h
03h
04h
05h
06h
07h
BGD(L)
BGD(H)
EXCR1
BSR
BGD[7:0] (Low Byte)
BGD [15:8] (High Byte)
LOOP
BTEST
BKSE
LOCK
RSVD
RSVD
ETDLBK
RSVD
EXT_SL
BSR[6:0] (Bank Select)
EXCR2
RSVD
PRESL[1:0]
RSVD
Reserved
RXFLV
TXFLV
RSVD
RSVD
RFL[4:0]
TFL[4:0]
Table 4-45. Bank 3 Bit Map
Register
Bits
Offset
Name
7
6
5
4
3
2
1
0
00h
01h
MRID
SH_LCR
SH_FCR
BSR
MID[3:0]
RID[3:0]
BKSE
SBRK
STKP
EPS
PEN
STB
WLS[1:0]
02h
RXFTH[1:0]
BKSE
TXFHT[1:0]
RSVD
TXSR
RXSR
FIFO_EN
03h
BSR[6:0] (Bank Select)
RSVD
04h-07h
RSVD
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Revision 6.0
SuperI/O Module (Continued)
4.8.3 IR Communications Port (IRCP) / Serial Port 3
(SP3) Functionality
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
Bank 0
This section describes the IRCP/SP3 support registers.
The IRCP/SP3 functional block provides advanced, versa-
tile serial communications features with IR capabilities.
The IRCP/SP3 also supports two DMA channels; the func-
tional block can use either one or both of them. One chan-
nel is required for IR-based applications, since IR
communication works in half duplex fashion. Two channels
would normally be needed to handle high-speed full duplex
IR based applications.
The IRCP or Serial Port 3 is chosen via bit 6 of the PMR
Register (see Section 3.2 "Multiplexing, Interrupt Selection,
and Base Address Registers" on page 86).
Offset 07h
Offset 06h
Offset 05h
Offset 04h
4.8.3.1 IR/SP3 Mode Register Bank Overview
Eight register banks, each containing eight registers, con-
trol IR/SP3 operation. All registers use the same 8-byte
address space to indicate offsets 00h through 07h. The
BSR register selects the active bank and is common to all
banks. See Figure 4-19.
LCR/BSR
Offset 02h
Common
Register
Throughout
All Banks
4.8.3.2 IRCP/SP3 Register and Bit Maps
The tables in this subsection provide register and bit maps
for Banks 0 through 7.
Offset 01h
Offset 00h
Figure 4-19. IRCP/SP3 Register Bank
Architecture
Table 4-46. Bank 0 Register Map
Name
Offset
Type
00h
RO
W
RXD. Receive Data Port
TXD. Transmit Data Port
IER. Interrupt Enable
EIR. Event Identification
FCR. FIFO Control
01h
02h
R/W
RO
R/W
W
LCR1. Link Control
03h
BSR1. Bank Select
R/W
04h
05h
06h
07h
R/W
R/W
R/W
R/W
R/W
MCR. Modem/Mode Control
LSR. Link Status
MSR. Modem Status
SPR. Scratchpad
ASCR. Auxiliary Status and Control
1. When bit 7 of this register is set to 1, bits [6:0] of BSR select the bank, as shown in Table 4-47.
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SuperI/O Module (Continued)
Table 4-47. Bank Selection Encoding
BSR Bits
7
6
5
4
3
2
1
0
Bank Selected
Functionality
0
1
1
1
1
1
1
1
1
1
x
0
1
1
1
1
1
1
1
1
x
x
x
x
1
1
1
1
1
1
x
x
x
x
0
0
0
0
1
1
x
x
x
x
0
0
1
1
0
0
x
x
x
x
0
1
0
1
0
1
x
x
1
x
0
0
0
0
0
0
x
x
x
1
0
0
0
0
0
0
0
1
1
1
2
3
4
5
6
7
UART + IR
IR Only
Table 4-48. Bank 1 Register Map
Name
Offset
Type
00h
01h
02h
03h
R/W
R/W
---
LBGD(L). Legacy Baud Generator Divisor Port (Low Byte)
LBGD(H). Legacy Baud Generator Divisor Port (High Byte)
RSVD. Reserved
LCR1. Link Control
W
BSR1. Bank Select
RSVD. Reserved
R/W
---
04h-07h
1. When bit 7 of this register is set to 1, bits [6:0] of BSR select the bank, as shown in Table 4-47.
Table 4-49. Bank 2 Register Map
Offset
Type
Name
00h
01h
02h
03h
04h
05h
06h
07h
R/W
R/W
R/W
R/W
R/W
---
BGD(L). Baud Generator Divisor Port (Low Byte)
BGD(H). Baud Generator Divisor Port (High Byte)
EXCR1. Extended Control 1
BSR. Bank Select
EXCR2. Extended Control 2
RSVD. Reserved
RO
TXFLV. TX FIFO Level
RO
RXFLV. RX FIFO Level
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Revision 6.0
SuperI/O Module (Continued)
Table 4-50. Bank 3 Register Map
Name
Offset
Type
00h
01h
RO
RO
RO
R/W
---
MID. Module and Revision Identification
SH_LCR. Link Control Shadow
SH_FCR. FIFO Control Shadow
BSR. Bank Select
02h
03h
04h-07h
RSVD. Reserved
Table 4-51. Bank 4 Register Map
Name
Offset
Type
00h
01h
02h
03h
04h
RO
RO
TMR(L). TImer (Low Byte)
TMR(H). Timer (High Byte)
R/W
R/W
R/W
RO
IRCR1. IR Control 1
BSR. Bank Select
TFRL(L). Transmission Frame Length (Low Byte)
TFRCC(L). Transmission Current Count (Low Byte)
TFRL(H). Transmission Frame Length (High Byte)
TFRCC(H). Transmission Current Count (High Byte)
RFRML(L). Reception Frame Maximum Length (Low Byte)
RFRCC(L). Reception Frame Current Count (Low Byte)
RFRML(H). Reception Frame Maximum Length (High Byte)
RFRCC(H). Reception Frame Current Count (High Byte)
05h
06h
07h
R/W
RO
R/W
RO
R/W
RO
Table 4-52. Bank 5 Register Map
Name
Offset
Type
00h
01h
02h
03h
04h
05h
06h
R/W
R/W
R/W
R/W
R/W
RO
SPR3. Scratchpad 2
SPR3. Scratchpad 3
RSVD. Reserved
BSR. Bank Select
IRCR2. IR Control 2
FRM_ST. Frame Status
RO
RFRL(L). Received Frame Length (Low Byte)
LSTFRC. Lost Frame Count
RFRL(H). Received Frame Length (High Byte)
RO
07h
RO
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SuperI/O Module (Continued)
Table 4-53. Bank 6 Register Map
Name
Offset
Type
00h
01h
R/W
R/W
R/W
R/W
R/W
---
IRCR3. IR Control 3
MIR_PW. MIR Pulse Width
SIR_PW. SIR Pulse Width
BSR. Bank Select
02h
03h
04h
BFPL. Beginning Flags/Preamble Length
RSVD. Reserved
05h-07h
Table 4-54. Bank 7 Register Map
Name
Offset
Type
00h
01h
R/W
R/W
R/W
R/W
R/W
---
IRRXDC. IR Receiver Demodulator Control
IRTXMC. IR Transmitter Modulator Control
RCCFG. Consumer IR (CEIR) Configuration
BSR. Bank Select
02h
03h
04h
IRCFG1. IR Interface Configuration 1
RSVD. Reserved
05h-06h
07h
R/W
IRCFG4. IR Interface Configuration 4
Table 4-55. Bank 0 Bit Map
Register
Bits
Offset
Name
7
6
5
4
3
2
1
0
00h
RXD
TXD
RXD[7:0] (Receive Data)
TXD[7:0] (Transmit Data)
MS_IE
IER1
IER2
01h
RSVD
LS_IE
LS_IE
TXLDL_IE RXHDL_IE
TXLDL_IE RXHDL_IE
TMR_IE
SFIF_IE
TXEMP_
DMA_IE
MS_IE
IE/PLD_IE
EIR1
EIR2
02h
FEN[1:0]
RSVD
RXFT
IPR[1:0]
IPF
TMR_EV
SFIF_EV TXEMP_EV/ DMA_EV
PLD_EV
MS_EV
LS_EV/
TXLDL_EV RXHDL_EV
TXHLT_EV
FCR
LCR
BSR
RXFTH[1:0]
TXFTH[1:0]
RSVD
PEN
TXSR
STB
RXSR
FIFO_EN
DTR
03h
04h
BKSE
BKSE
SBRK
RSVD
STKP
EPS
WLS[1:0]
BSR[6:0] (Bank Select)
MCR1
LOOP
ISEN/
DCDLP
RILP
RTS
MCR2
LSR
MDSL[2:0]
TXEMP
IR_PLS
TX_DFR
DMA_EN
PE/
RTS
OE
DTR
05h
ER_INF/
FR_END
TXRDY
DSR
BRK/
MAX_LEN
FE/
RXDA
PHY_ERR BAD_CRC
06h
07h
MSR
SPR1
DCD
RI
CTS
DDCD
TERI
DDSR
DCTS
Scratch Data
ASCR2
CTE/PLD
TXUR
RXACT/
RXBSY
RXWDG/
LOST_FR
TXHFE
S_EOT
FEND_INF RXF_TOUT
1. Non-extended mode.
2. Extended mode.
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Revision 6.0
SuperI/O Module (Continued)
Table 4-56. Bank 1 Bit Map
Register
Bits
Offset
Name
7
6
5
4
3
2
1
0
00h
01h
02h
03h
LBGD(L)
LBGD(H)
RSVD
LCR
LBGD[7:0] (Low Byte Data)
LBGD[15:8] (High Byte Data)
RSVD
BKSE
BKSE
SBRK
STKP
EPS
PEN
BSR[6:0] (Bank Select)
RSVD
STB
WLS[1:0]
BSR
04h-07h
RSVD
Table 4-57. Bank 2 Bit Map
Register
Bits
Offset
Name
7
6
5
4
3
2
1
0
00h
01h
02h
03h
04h
05h
06h
07h
BGD(L)
BGD(H)
EXCR1
BSR
BGD[7:0] (Low Byte Data)
BGD[15:8] (High Byte Data)
BTEST
BKSE
LOCK
RSVD
RSVD
ETDLBK
LOOP
DMASWP
DMATH
DMANF
EXT_SL
BSR[6:0] (Bank Select)
RF_SIZ[1:0]
RSVD
EXCR2
RSVD
PRESL[1:0]
TF_SIZ[1:0]
TXFLV
RXFLV
RSVD
RSVD
TFL[5:0]
RFL[5:0]
Table 4-58. Bank 3 Bit Map
Register
Bits
Offset
Name
MID
7
6
5
4
3
2
1
0
00h
01h
MID[3:0]
SBRK
RID[3:0]
SH_LCR1
RSVD
STKP
EPS
PEN
STB
WLS[1:0]
SH_FCR2
BSR
02h
RXFTH[1:0]
BKSE
TXFTH[1:0]
RSVD
TXSR
RXSR
FIFO_EN
03h
BSR[6:0] (Bank Select)
Reserved
04h-07h
RSVD
1. LCR Register Value
2. FCR Register Value
Table 4-59. Bank 4 Bit Map
Register
Bits
Offset
Name
7
6
5
4
3
2
1
0
00h
01h
02h
03h
04h
TMR(L)
TMR(H)
IRCR1
BSR
TMR[7:0] (Low Byte Data)
RSVD
RSVD
TMR[11:8] (High Byte Data)
IR_SL[1:0] CTEST
TMR_EN
BKSE
BSR[6:0] (Bank Select)
TFRL(L)/
TFRL[7:0] / TFRCC[7:0] (Low Byte Data)
TFRCC(L)
05h
TFRL(H)/
RSVD
TFRL[12:8] / TFRCC[12:8] (High Byte Data)
TFRCC(H)
Revision 6.0
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SuperI/O Module (Continued)
Table 4-59. Bank 4 Bit Map (Continued)
Register
Bits
Offset
Name
7
6
5
4
3
2
1
0
06h
RFRML(L)/
RFRCC(L)
RFRML[7:0] / RFRCC[7:0] (Low Byte Data)
07h
RFRML(H)/
RFRCC(H)
RSVD
RFRML[12:8] / RFRCC[12:8] (High Byte Data)
Table 4-60. Bank 5 Bit Map
Register
Bits
Offset
Name
7
6
5
4
3
2
1
0
00h
01h
02h
03h
04h
05h
06h
SPR2
SPR3
Scratchpad 2
Scratchpad 2
RSVD
RSVD
BSR
BKSE
RSVD
VLD
BSR[6:0] (Bank Select)
IRCR2
FRM_ST
SFTSL
FEND_MD AUX_IRRX
RSVD MAX_LEN
TX_MS
MDRS
IRMSSL
OVR1
IR_FDPLX
OVR2
LOST_FR
PHY_ERR BAD_CRC
RFRL(L)/
LSTFRC
RFRL[7:0] (Low Byte Data) / LSTFRC[7:0]
07h
RFRL(H)
RFRL[15:8] (High Byte Data)
Table 4-61. Bank 6 Bit Map
Register
Bits
Offset
Name
7
6
5
4
3
2
1
0
00h
01h
IRCR3
MIR_PW
SIR_PW
BSR
SHDM_DS SHMD_DS
FIR_CRC
MIR_CRC
RSVD
TXCRC_INV TXCRC_DS
MPW[3:0]
RSVD
RSVD
02h
RSVD
SPW[3:0]
03h
BKSE
BSR[6:0] (Bank Select)
RSVD
04h
BFPL
MBF[3:0]
FPL[3:0]
05h-07h
RSVD
Table 4-62. Bank 7 Bit Map
Register
Bits
Offset
Name
7
6
5
4
3
2
1
0
00h
01h
IRRXDC
IRTXMC
RCCFG
BSR
DBW[2:0]
MCPW[2:0]
T_OV
DFR[4:0]
MCFR[4:0]
TXHSC
02h
R_LEN
BKSE
RXHSC
SIRC[2:0]
IRSL0_DS
RCDM_DS
RSVD
RC_MMD[1:0]
03h
BSR[6:0] (Bank Select)
04h
IRCFG1
RSVD
STRV_MS
IRID3
RSVD
IRIC[2:0]
RSVD
05h-06h
07h
IRCFG4
RSVD
IRRX_MD
RXINV
IRSL21_DS
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Revision 6.0
5.0 Core Logic Module
The Core Logic module is an enhanced PCI-to-Sub-ISA
bridge (South Bridge), this module is ACPI-compliant, and
provides AT/Sub-ISA functionality. The Core Logic module
also contains state-of-the-art power management. Two bus
mastering IDE controllers are included for support of up to
four ATA-compliant devices. A three-port Universal Serial
Bus (USB) provides high speed, and Plug & Play expan-
sion for a variety of new consumer peripheral devices.
AT Compatibility
• 8259A-equivalent interrupt controllers
• 8254-equivalent timer
• 8237-equivalent DMA controllers
• Port A, B, and NMI logic
• Positive decode for AT I/O space
5.1 FEATURE LIST
Sub-ISA Interface
• Boot ROM chip select
Internal Fast-PCI Interface
The internal Fast-PCI bus interface is used to connect the
Core Logic and GX1 modules of the SC1200/SC1201. This
interface includes the following features:
• Extended ROM to 16 MB
• Two general-purpose chip selects
• NAND Flash support
• PCI protocol for transfers on Fast-PCI bus
• Up to 66 MHz operation
• M-Systems DiskOnChip support
• Is not the subtractive decode agent
• Subtractive decode handled internally in conjunction
with external PCI bus
Power Management
Bus Mastering IDE Controllers
• Automated CPU 0V Suspend modulation
• Two controllers with support for up to four IDE devices
• I/O Traps and Idle Timers for peripheral power manage-
ment
• Independent timing for master and slave devices for both
channels
• Software SMI and Stop Clock for APM support
• ACPI-compliant timer and register set
• PCI bus master burst reads and writes
• Multiword DMA support
• Up to 22 GPIOs of which all can generate Power
Management Interrupts (PMEs)
• Programmed I/O (PIO) Modes 0-4 support
• Three Dedicated GPWIOs powered by VSBL and VSB
Universal Serial Bus
• Shadow register support for legacy controllers for 0V
• Three independent USB interfaces
Suspend
• Open Host Controller Interface (OpenHCI) specification
Integrated Audio
compliant
• AC97 Version 2.0 compliant interface to audio codecs
• Secondary codec support
PCI Interface
• PCI 2.1 compliant
• AMC97 codec support
• PCI master for AC97 and IDE controllers
• Subtractive agent for unclaimed transactions
• Supports PCI initiator-to-Sub-ISA cycle translations
• PCI-to-Sub-ISA interrupt mapper/translator
Video Processor Interface
• Synchronous serial interface to the Video Processor
• Translates video and clock control register accesses
from PCI to serial interface
• External PCI bus
• Supports both reads and writes of Video Processor
— Devices internal to the Core Logic module (IDE,
Audio, USB, Sub-ISA, etc.) cannot master to memory
through the external PCI bus.
— Legacy DMA is not supported to memory located on
external PCI bus.
registers
• Retries Fast-PCI bus accesses until Core Logic
completes the transfer over the serial interface
— The Core Logic module does not transfer subtrac-
tively decoded I/O cycles originating from the
external PCI bus.
Low Pin Count (LPC) Interface
• Based on Intel LPC Interface Specification Revision 1.0
• Serial IRQ support
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Core Logic Module (Continued)
5.2 MODULE ARCHITECTURE
The Core Logic architecture provides the internal functional
blocks shown in Figure 5-1.
• AT compatibility logic (legacy)
• ACPI compliant power management (includes GPIO
• Fast-PCI interface to external PCI bus
• IDE controllers (UDMA-33)
• USB controllers
interfaces, such as joystick)
• Integrated audio controller
• Low Pin Count (LPC) Interface
• Sub-ISA bus interface
Fast-PCI
UDMA33
IDE
33-66 MHz
PCI
Fast X-Bus
PCI Interface
33 MHz
USB
Config.
Reg.
USB
AC97
Audio
Controller
X-Bus
Legacy
ISA/PIC/PIT/DMA
PW
ACPI/PM
GPIOs
LPC
GPIOs
LPC
Sub-ISA
Figure 5-1. Core Logic Module Block Diagram
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Revision 6.0
Core Logic Module (Continued)
5.2.1 Fast-PCI Interface to External PCI Bus
1) VIP
The Core Logic module provides a PCI bus interface that is
both a slave for PCI cycles initiated by the GX1 module or
other PCI master devices, and a non-preemptive master for
DMA transfer cycles. It is also a standard PCI master for
the IDE controllers and audio I/O logic. The Core Logic
supports positive decode for configurable memory and I/O
regions, and implements a subtractive decode option for
unclaimed PCI accesses. It also generates address and
data parity, and performs parity checking. The arbiter for
the Fast-PCI interface is located in the GX1 module.
2) IDE Channel 0
3) IDE Channel 1
4) Audio
5) USB
6) External REQ0#
7) External REQ1#
5.2.2 PSERIAL Interface
Configuration registers are accessed through the PCI inter-
face using the PCI Bus Type 1 configuration mechanism as
described in the PCI Specification.
The majority of the system power management logic is
implemented in the Core Logic module, but a minimal
amount of logic is contained within the GX1 module to pro-
vide information that is not externally visible (e.g., graphics
controller).
5.2.1.1 Processor Mastered Cycles
The Core Logic module acts on all processor initiated
cycles according to PCI rules for active/subtractive decode
using DEVSEL#. Memory writes are automatically posted.
Reads are retried if they are not destined for actively
decoded (i.e., positive decode) devices on the high speed
X-Bus or the 33 MHz X-Bus. This means that reads to
external PCI, LPC, or Sub-ISA devices are automatically
treated as delayed transactions through the PCI retry
mechanism. This allows the high bandwidth devices
access to the Fast-PCI interface while the response from a
slow device is accumulated.
The GX1 module implements a simple serial communica-
tions mechanism to transmit the CPU status to the Core
Logic module via internal signal PSERIAL. The GX1 mod-
ule accumulates CPU events in an 8-bit register which it
transmits serially every 1 to 10 µs.
The packet transmitter holds the serial output internal sig-
nal (PSERIAL) low until the transmission interval counter
has elapsed. Once the counter has elapsed, the PSERIAL
signal is held high for two clocks to indicate the start of
packet transmission. The contents of the Serial Packet reg-
ister are then shifted out starting from bit 7 down to bit 0.
The PSERIAL signal is held high for one clock to indicate
the end of packet transmission and then remains low until
the next transmission interval. After the packet transmis-
sion is complete, the GX1 module’s Serial Packet register’s
contents are cleared.
Bursting from the host is not supported.
All types of configuration cycles are supported and handled
appropriately according to the PCI specification.
5.2.1.2 External PCI Mastered Cycles
Memory cycles mastered by external PCI devices on the
external PCI bus are actively taken if they are to the system
memory address range. Memory cycles to system memory
are forwarded to the Fast-PCI interface. Burst transfers are
stopped on every cache line boundary to allow efficient
buffering in the Fast-PCI interface block.
The GX1 module’s input clock is used as the clock refer-
ence for the serial packet transmitter.
Once a bit in the register is set, it remains set until the com-
pletion of the next packet transmission. Successive events
of the same type that occur between packet transmissions
are ignored. Multiple unique events between packet trans-
missions accumulate in this register. The GX1 module
transmits the contents of the serial packet only when a bit
in the Serial Packet register is set and the interval counter
has elapsed.
I/O and configuration cycles mastered by external PCI
devices which are subtractively decoded by the Core Logic
module, are not handled.
5.2.1.3 Core Logic Internal or Sub-ISA Mastered
Cycles
The Core Logic module decodes the serial packet after
each transmission and performs the power management
tasks related to video retrace.
Only memory cycles (not I/O cycles) are supported by the
internal Sub-ISA or legacy DMA masters. These memory
cycles are always forwarded to the Fast-PCI interface.
For more information on the Serial Packet register refer to
the GX1 Processor Series Datasheet.
5.2.1.4 External PCI Bus
The external PCI bus is a fully-compliant PCI bus. PCI slots
are connected to this bus. Support for up to two bus mas-
ters is provided. The arbiter is in the Core Logic module.
5.2.2.1 Video Retrace Interrupt
Bit 7 of the “Serial Packet” can be used to generate an SMI
whenever a video retrace occurs within the GX1 module.
This function is normally not used for power management
but for SoftVGA routines. Setting F0 Index 83h[2] = 1
enables this function. A read only status register located at
F1BAR0+I/O Offset 00h[5] can be read to see if the SMI
was caused by a video retrace event.
5.2.1.5
Bus Master Request Priority
The Fast-PCI bus supports seven bus masters. The
requests (REQs) are fixed in priority. The seven bus mas-
ters in order of priority are:
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Core Logic Module (Continued)
5.2.3 IDE Controller
Recovery latency occurs after the IDE data port transac-
tions have completed. It provides hold time on the
IDE_ADDR[2:0] and IDE_CS# lines with respect to the
read and write strobes (IDE_IOR# and IDE_IOW#).
The Core Logic module integrates a PCI bus mastering,
ATA-4 compatible IDE controller. This controller supports
UltraDMA, Multiword DMA and Programmed I/O (PIO)
modes. Two devices are supported on the IDE controller.
The data-transfer speed for each device can be indepen-
dently programmed. This allows high-speed IDE peripher-
als to coexist on the same channel as lower speed devices.
The PIO portion of the IDE registers is enabled through:
• Channel 0 Drive 0 Programmed I/O Register
(F2 Index 40h)
The Core Logic module supports two IDE channels, a pri-
mary channel and a secondary channel.
• Channel 0 Drive 1 Programmed I/O Register
(F2 Index 48h)
The IDE interface provides a variety of features to optimize
system performance, including 32-bit disk access, post
write buffers, bus master, Multiword DMA, look-ahead read
buffer, and prefetch mechanism for each channel respec-
tively.
• Channel 1 Drive 0 Programmed I/O Register
(F2 Index 50h)
• Channel 1 Drive 1 Programmed I/O Register
(F2 Index 58h)
The IDE channels and devices can be individually pro-
grammed to select the proper address setup time, asserted
time, and recovery time.
The IDE interface timing is completely programmable. Tim-
ing control covers the command active and recover pulse
widths, and command block register accesses. The IDE
data-transfer speed for each device on each channel can
be independently programmed allowing high-speed IDE
peripherals to coexist on the same channel as older, com-
patible devices.
The bit formats for these registers are shown inTable 5-35
on page 266. Note that there are different bit formats for
each of the PIO programming registers depending on the
operating format selected: Format 0 or Format 1:
The Core Logic module also provides a software accessi-
ble buffered reset signal to the IDE drive, F0 Index
44h[3:2]. The IDE_RST# signal is driven low during reset to
the Core Logic module and can be driven low or high as
needed for device-power-off conditions.
• F2 Index 44h[31] (Channel 0 Drive 0 — DMA Control
Register) sets the format of the PIO register.
— If bit 31 = 0, Format 0 is used and it selects the
slowest PIO mode (bits [19:16]) per channel for
commands.
5.2.3.1 IDE Configuration Registers
— If bit 31 = 1, Format 1 is used and it allows indepen-
dent control of command and data.
Registers for configuring Channels 0 and 1 are located in
the PCI register space designated as Function 2 (F2 Index
40h-5Ch). Table 5-35 on page 266 provides the bit formats
for these registers. The IDE bus master configuration regis-
ters are accessed via F2 Index 20h which is Base Address
Register 4 in Function 2 (F2BAR4). See Table 5-36 on
page 270 for register/bit formats.
Also listed in the bit formats are recommended values for
the different PIO modes. Note that these are only recom-
mended settings and are not 100% tested.
When using independent control of command and data
cycles the following algorithm should be used when two
IDE devices are sharing the same channel:
The following subsections discuss Core Logic opera-
tional/programming details concerning PIO, Bus Master,
and UltraDMA/33 modes.
1) The PIO data cycle timing for a particular device can
be the timing value for the maximum PIO mode which
that device reports it supports.
5.2.3.2 PIO Mode
2) The PIO command cycle timing for a particular device
must be the timing value for the lowest PIO mode for
both devices on the channel.
The IDE data port transaction latency consists of address
latency, asserted latency and recovery latency. Address
latency occurs when a PCI master cycle targeting the IDE
data port is decoded, and the IDE_ADDR[2:0] and
IDE_CS# lines are not set up. Address latency provides the
setup time for the IDE_ADDR[2:0] and IDE_CS# lines prior
to IDE_IOR# and IDE_IOW#.
For example, if a channel had one Mode 4 device and one
Mode 0 device, then the Mode 4 device would have com-
mand timings for Mode 0 and data timing for Mode 4. The
Mode 0 device would have both command and data timings
for Mode 0. Note that for the Mode 0 case, the 32-bit timing
value is listed because both data and command timings are
the same mode. However, the actual timing value for the
Mode 4 device would be constructed out of the Mode 4
data timing 16-bit value and the Mode 0 16-bit command
timing value. Both 16-bit values are shown in the register
description but not assembled together as they are mixed
modes.
Asserted latency consists of the I/O command strobe
assertion length and recovery time. Recovery time is pro-
vided so that transactions may occur back-to-back on the
IDE interface without violating minimum cycle periods for
the IDE interface.
If IDE_IORDY is asserted when the initial sample point is
reached, no wait states are added to the command strobe
assertion length. If IDE_IORDY is negated when the initial
sample point is reached, additional wait states are added.
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Core Logic Module (Continued)
5.2.3.3 Bus Master Mode
The PRD table consists of two DWORDs. The first DWORD
contains a 32-bit pointer to a buffer to be transferred. The
second DWORD contains the size (16 bits) of the buffer
and the EOT flag. The EOT bit (bit 31) must be set to indi-
cate the last PRD in the PRD table.
Two IDE bus masters are provided to perform the data
transfers for the primary and secondary channels. The IDE
controller of the Core Logic module off-loads the CPU and
improves system performance in multitasking environ-
ments.
Programming Model
The bus master mode programming interface is an exten-
sion of the standard IDE programming model. This means
that devices can always be dealt with using the standard
IDE programming model, with the master mode functional-
ity used when the appropriate driver and devices are
present. Master operation is designed to work with any IDE
device that supports DMA transfers on the IDE bus.
Devices that work in PIO mode can only use the standard
IDE programming model.
The following steps explain how to initiate and maintain a
bus master transfer between memory and an IDE device.
1) Software creates a PRD table in system memory.
Each PRD entry is 8 bytes long, consisting of a base
address pointer and buffer size. The maximum data
that can be transferred from a PRD entry is 64 KB. A
PRD table must be aligned on a 4-byte boundary. The
last PRD in a PRD table must have the EOT bit set.
2) Software loads the starting address of the PRD table
by programming the PRD Table Address register.
The IDE bus masters use a simple scatter/gather mecha-
nism allowing large transfer blocks to be scattered to or
gathered from memory. This cuts down on the number of
interrupts to and interactions with the CPU.
3) Software must fill the buffers pointed to by the PRDs
with IDE data.
Physical Region Descriptor Table Address
4) Write 1 to the Bus Master Interrupt bit and Bus Master
Error (Status register bits 2 and 1) to clear the bits.
Before the controller starts a master transfer it is given a
pointer to a Physical Region Descriptor Table. This pointer
sets the starting memory location of the Physical Region
Descriptors (PRDs). The PRDs describe the areas of mem-
ory that are used in the data transfer. The PRDs must be
aligned on a 4-byte boundary and the table cannot cross a
64 KB boundary in memory.
5) Set the correct direction to the Read or Write Control
bit (Command register bit 3).
Engage the bus master by writing a “1” to the Bus
Master Control bit (Command register bit 0).
The bus master reads the PRD entry pointed to by the
PRD Table Address register and increments the
address by 08h to point to the next PRD. The transfer
begins.
Primary and Secondary IDE Bus Master Registers
The IDE Bus Master Registers for each channel (primary
and secondary) have an IDE Bus Master Command regis-
ter and Bus Master Status register. These registers and bit
formats are described in Table 5-36 on page 270.
6) The bus master transfers data to/from memory
responding to bus master requests from the IDE
device. At the completion of each PRD, the bus mas-
ter’s next response depends on the settings of the
EOT flag in the PRD. If the EOT bit is set, then the IDE
bus master clears the Bus Master Active bit (Status
register bit 0) and stop. If any errors occurred during
the transfer, the bus master sets the Bus Master Error
bit Status register bit 1).
Physical Region Descriptor Format
Each physical memory region to be transferred is
described by a Physical Region Descriptor (PRD) as illus-
trated in Table 5-1. When the bus master is enabled (Com-
mand register bit 0 = 1), data transfer proceeds until each
PRD in the PRD table has been transferred. The bus mas-
ter does not cache PRDs.
Table 5-1. Physical Region Descriptor Format
Byte 2 Byte 1
Byte 3
Byte 0
DWORD 31 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
0
1
Memory Region Physical Base Address [31:1] (IDE Data Buffer)
Reserved Size [15:1]
0
0
E
O
T
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Core Logic Module (Continued)
5.2.3.4 UltraDMA/33 Mode
The data transfer phase continues the burst transfers with
the Core Logic and the IDE via providing data, toggling
STROBE and DMARDY#. The IDE_DATA[15:0] is latched
by receiver on each rising and falling edge of STROBE.
The transmitter can pause the burst cycle by holding
STROBE high or low, and resume the burst cycle by again
toggling STROBE. The receiver can pause the burst cycle
by negating DMARDY# and resumes the burst cycle by
asserting DMARDY#.
The IDE controller of the Core Logic module supports
UltraDMA/33. It utilizes the standard IDE Bus Master func-
tionality to interface, initiate and control the transfer.
UltraDMA/33 definition also incorporates a Cyclic Redun-
dancy Checking (CRC) error checking protocol to detect
errors.
The UltraDMA/33 protocol requires no extra signal pins on
the IDE connector. The IDE controller redefines three stan-
dard IDE control signals when in UltraDMA/33 mode.
These definitions are shown in Table 5-2.
The current burst cycle can be terminated by either the
transmitter or the receiver. A burst cycle must first be
paused as described above before it can be terminated.
The IDE controller can then stop the burst cycle by assert-
ing STOP, with the IDE device acknowledging by negating
IDE_DREQ. The IDE device then stops the burst cycle by
negating IDE_DREQ and the IDE controller acknowledges
by asserting STOP. The transmitter then drives the
STROBE signal to a high level. The IDE controller then
puts the result of the CRC calculation onto the
IDE_DATA[15:0] while de-asserting IDE_DACK#. The IDE
device latches the CRC value on the rising edge of
IDE_DACK#.
Table 5-2. UltraDMA/33 Signal Definitions
IDE Controller
Channel Signal
UltraDMA/33
Read Cycle
UltraDMA/33
Write Cycle
IDE_IOW#
IDE_IOR#
IDE_IORDY
STOP
STOP
DMARDY#
STROBE
STROBE
DMARDY#
The CRC value is used for error checking on UltraDMA/33
transfers. The CRC value is calculated for all data by both
the IDE controller and the IDE device during the
UltraDMA/33 burst transfer cycles. This result of the CRC
calculation is defined as all data transferred with a valid
STROBE edge while IDE_DACK# is asserted. At the end
of the burst transfer, the IDE controller drives the result of
the CRC calculation onto IDE_DATA[15:0] which is then
strobed by the de-assertion of IDE_DACK#. The IDE
device compares the CRC result of the IDE controller to its
own and reports an error if there is a mismatch.
All other signals on the IDE connector retain their func-
tional definitions during the UltraDMA/33 operation.
IDE_IOW# is defined as STOP for both read and write
transfers to request to stop a transaction.
IDE_IOR# is redefined as DMARDY# for transferring data
from the IDE device to the IDE controller. It is used by the
IDE controller to signal when it is ready to transfer data and
to add wait states to the current transaction. IDE_IOR# sig-
nal is defined as STROBE for transferring data from the
IDE controller to the IDE device. It is the data strobe signal
driven by the IDE controller on which data is transferred
during each rising and falling edge transition.
The timings for UltraDMA/33 are programmed into the
DMA control registers:
IDE_IORDY is redefined as STROBE for transferring data
from the IDE device to the IDE controller during a read
cycle. It is the data strobe signal driven by the IDE device
on which data is transferred during each rising and falling
edge transition. IDE_IORDY is defined as DMARDY# dur-
ing a write cycle for transferring data from the IDE control-
ler to the IDE device. It is used by the IDE device to signal
when it is ready to transfer data and to add wait states to
the current transaction.
• Channel 0 Drive 0 DMA Control Register (F2 Index 44h)
• Channel 0 Drive 1 DMA Control Register (F2 Index 4Ch)
• Channel 1 Drive 0 DMA Control Register (F2 Index 54h)
• Channel 1 Drive 1 DMA Control Register (F2 Index 5Ch)
The bit formats for these registers are described in Table 5-
35 on page 266. Note that F2 Index 44h[20] is used to
select either Multiword or UltraDMA mode. Bit 20 = 0
selects Multiword DMA mode. If bit 20 = 1, then
UltraDMA/33 mode is selected. Once mode selection is
made using this bit, the remaining DMA Control registers
also operate in the selected mode.
UltraDMA/33 data transfer consists of three phases, a star-
tup phase, a data transfer phase and a burst termination
phase.
The IDE device begins the startup phase by asserting
IDE_DREQ. When ready to begin the transfer, the IDE con-
troller asserts IDE_DACK#. When IDE_DACK# is asserted,
the IDE controller drives IDE_CS0# and IDE_CS1#
asserted, and IDE_ADDR[2:0] low. For write cycles, the
IDE controller negates STOP, waits for the IDE device to
assert DMARDY#, and then drives the first data WORD
and STROBE signal. For read cycles, the IDE controller
negates STOP, and asserts DMARDY#. The IDE device
then sends the first data WORD and asserts STROBE.
Also listed in the bit formats are recommended values for
both Multiword DMA Modes 0-2 and UltraDMA/33 Modes
0-2. Note that these are only recommended settings and
are not 100% tested.
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Core Logic Module (Continued)
5.2.4 Universal Serial Bus
• DOCW
— DOCW# is asserted on memory write transactions to
The Core Logic module provides three complete, indepen-
dent USB ports. Each port has a Data "Negative" and a
Data "Positive" signal.
DOCCS# window (i.e., when both DOCCS# and
MEMW# are active, DOCW# is active; otherwise, it is
inactive).
The USB ports are Open Host Controller Interface (Open-
HCI) compliant. The OpenHCI specification provides a reg-
ister-level description for a host controller, as well as
common industry hardware/software interface and drivers.
• RD#, WR#
— The signals IOR#, IOW#, MEMR#, and MEMW# are
combined into two signals: RD# is asserted on I/O
read or memory read; WR# is asserted on I/O write
or memory write.
5.2.5 Sub-ISA Bus Interface
The Sub-ISA interface of the Core Logic module is an ISA-
like bus interface that is used by SC1200/SC1201 to inter-
face with Boot Flash, M-Systems DiskOnChip or NAND
EEPROM and other I/O devices. The Core Logic module is
the default subtractive decoding agent and forwards all
unclaimed memory and I/O cycles to the ISA bus. However,
the Core Logic module can be configured to ignore either
I/O, memory, or all unclaimed cycles (subtractive decode
disabled).
Memory devices that use ROMCS# or DOCCS# as their
chip select signal can be configured to support an 8-bit or
16-bit data bus via bits 3 and 6 of the MCR register. Such
devices can also be configured as zero wait states devices
(regardless of the data bus width) via bits 9 and 10 of the
MCR register. For MCR register bit descriptions, see Table
3-2 on page 86.
I/O peripherals that use IOCS0# or IOCS1# as their chip
select signal can be configured to support an 8-bit or 16-bit
data bus via bits 7 and 8 of the MCR register. Such devices
can also be configured as zero wait state devices (for 8-bit
peripherals) via bits 11 and 12 of the MCR register. For
MCR register bit descriptions, see Table 3-2 on page 86.
Note: The external Sub-ISA bus is a positive decode bus.
Unclaimed memory and I/O cycles will not appear
on the Sub-ISA interface.
The Core Logic module does not support Sub-ISA refresh
cycles. The refresh toggle bit in Port B still exists for soft-
ware compatibility reasons.
Other memory devices and I/O peripherals must be 8-bit
devices; their transactions can not be with zero wait states
The Sub-ISA interface includes the followings signals in
addition to the signals used for an ISA interface:
The Boot Flash supported by the SC1200/SC1201 can be
up to 16 MB. It is supported with the ROMCS# signal.
• IOCS0#/IOCS1#
All unclaimed memory and I/O cycles are forwarded to the
Internal ISA bus if subtractive decode is enabled.
— Asserted on I/O read/write transactions from/to a
programmable address range.
The DiskOnChip chip select signal (DOCCS#) is asserted
on any memory read or memory write transaction from/to a
programmable address range. The address range is pro-
grammable via the DOCCS# Base Address and Control
registers (F0 Index 78h and 7Ch). The base address must
be on an address boundary, the size of the range.
• DOCCS#
— Asserted on memory read/write transactions from/to
a programmable window.
• ROMCS#
— Asserted on memory read/write to upper 16 MB of
address space. Configurable via the ROM Mask
register (F0 Index 6Eh).
Signal DOCCS# can also be used to interface to NAND
Flash devices together with signals DOCW# and DOCR#.
See application note Geode™ SC1200/SC2200/SC3200
IAOC Devices: External NAND Flash Memory Circuit for
details.
• DOCR#
— DOCR# is asserted on memory read transactions
from DOCCS# window (i.e., when both DOCCS# and
MEMR# are active, DOCR# is active; otherwise, it is
inactive).
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Core Logic Module (Continued)
5.2.5.1 Sub-ISA Bus Cycles
Note: Not all signals described in Figure 5-2 are available
externally. See Section 2.4.8 "Sub-ISA Interface
Signals" on page 71 for more information about
which Sub-ISA signals are externally available on
the SC1200/SC1201.
The ISA bus controller issues multiple ISA cycles to satisfy
PCI transactions that are larger than 16 bits. A full 32-bit
read or write results in two 16-bit ISA transactions or four 8-
bit ISA transactions. The ISA controller gathers the data
from multiple ISA read cycles and returns TRDY# to the
PCI bus.
5.2.5.2 Sub-ISA Support of Delayed PCI Transactions
Multiple PCI cycles occur for every slower ISA cycle. This
prevents slow PCI cycles from occupying too much band-
width and allows access to other PCI traffic. Figure 5-3 on
page 163 shows the relationship of PCI cycles to an ISA
cycle with PCI delayed transactions enabled.
SA[23:0] are a concatenation of ISA LA[23:17] and
SA[19:0] and perform equivalent functionality at a reduced
pin count.
Figure 5-2 shows the relationship between a PCI cycle and
the corresponding ISA cycle generated.
Fast-PCI_CLK
ISACLK
FRAME#
IRDY#
TRDY#
STOP#
AD[31:0] (Read)
AD[31:0] (Write)
BALE
RD#,WR#,IOR#,IOW#
MEMR#,MEMW#
Figure 5-2. Non-Posted Fast-PCI to ISA Access
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REQ#
GNT#
FRAME#
Fast-PCI
1
1
2
IRDY#
1
1
TRDY#
STOP#
BALE
ISA
RD#, IOR#
3
1 - GX1 transaction
2 - IDE bus master - starts and completes
3 - End of ISA cycle
Figure 5-3. PCI to ISA Cycles with Delayed Transaction Enabled
5.2.5.3 Sub-ISA Bus Data Steering 5.2.5.4 I/O Recovery Delays
The Core Logic module performs all of the required data
steering from SD[7:0] to SD[15:0] during normal 8-bit ISA
cycles, as well as during DMA and ISA master cycles. It
handles data transfers between the 32-bit PCI data bus
and the ISA bus. 8/16-bit devices can reside on the ISA
bus. Various PC-compatible I/O registers, DMA controller
registers, interrupt controller registers, and counter/timer
registers lie on the on-chip I/O data bus. Either the PCI bus
master or the DMA controllers can become the bus owner.
In normal operation, the Core Logic module inserts a delay
between back-to-back ISA I/O cycles that originate on the
PCI bus. The default delay is four ISACLK cycles. Thus, the
second of consecutive I/O cycles is held in the ISA bus
controller until this delay count has expired. The delay is
measured between the rising edge of IOR#/IOW# and the
falling edge of BALE. This delay can be adjusted to a
greater delay through the ISA I/O Recovery Control register
(F0 Index 51h).
When the PCI bus master is the bus owner, the Core Logic
module data steering logic provides data conversion nec-
essary for 8/16/32-bit transfers to and from 8/16-bit devices
on either the Sub-ISA bus or the 8-bit registers on the on-
chip I/O data bus. When PCI data bus drivers of the Core
Logic module are in TRI-STATE, data transfers between
the PCI bus master and PCI bus devices are handled
directly via the PCI data bus.
Note: This delay is not inserted for a 16-bit Sub-ISA I/O
access that is split into two 8-bit I/O accesses.
When the DMA requestor is the bus owner, the Core Logic
module allows 8/16-bit data transfer between the Sub-ISA
bus and the PCI data bus.
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Core Logic Module (Continued)
5.2.5.5 ISA DMA
to the PCI arbiter. After the PCI bus has been granted, the
respective DACK# is driven active.
DMA transfers occur between ISA I/O peripherals and sys-
tem memory (i.e., not available externally). The data width
can be either 8 or 16 bits. Out of the seven DMA channels
available, four are used for 8-bit transfers while the remain-
ing three are used for 16-bit transfers. One byte or WORD
is transferred in each DMA cycle.
The Core Logic module generates PCI memory read or
write cycles in response to a DMA cycle. Figure 5-4 and
Figure 5-5 are examples of DMA memory read and mem-
ory write cycles. Upon detection of the DMA controller’s
MEMR# or MEMW# active, the Core Logic module starts
the PCI cycle, asserts FRAME#, and negates an internal
IOCHRDY. This assures the DMA cycle does not complete
before the PCI cycle has provided or accepted the data.
IOCHRDY is internally asserted when IRDY# and TRDY#
are sampled active.
Note: The Core Logic module does not support DMA
transfers to ISA memory.
The ISA DMA device initiates a DMA request by asserting
one of the DRQ[7:5, 3:0] signals. When the Core Logic
module receives this request, it sends a bus grant request
PCICLK
ISACLK
MEMR#
IOW#
SD[15:0]
IOCHRDY
FRAME#
AD[31:0]
IRDY#
TRDY#
Figure 5-4. ISA DMA Read from PCI Memory
PCICLK
ISACLK
MEMW#
IOR#
SD[15:0]
IOCHRDY
FRAME#
AD[31:0]
IRDY#
TRDY#
Figure 5-5. ISA DMA Write to PCI Memory
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5.2.5.6 ROM Interface
Table 5-3. Cycle Multiplexed PCI / Sub-ISA Balls
The Core Logic module positively decodes memory
addresses 000F0000h-000FFFFFh (64 KB) and
FFFC0000h-FFFFFFFFh (256 KB) at reset. These memory
cycles cause the Core Logic module to claim the cycle, and
generate an ISA bus memory cycle with ROMCS#
asserted. The Core Logic module can also be configured to
respond to memory addresses FF000000h-FFFFFFFFh
(16 MB) and 000E0000h-000FFFFFh (128 KB).
Ball No.
PCI
Sub-ISA
EBGA
TEPBGA
AD0
AD1
A0
A1
A17
D16
A18
A15
A16
A14
C15
B14
C14
B13
C13
C12
A12
C11
A11
B10
A7
U1
P3
U3
N1
P1
N3
N2
M2
M4
L2
AD2
A2
AD3
A3
8- or 16-bit wide ROM is supported. BOOT16 strap deter-
mines the width after reset. MCR[14,3] (Offset 34h) in the
General Configuration Block (see Table 3-2 on page 86 for
bit details) allows program control of the width.
AD4
A4
AD5
A5
AD6
A6
AD7
A7
Flash ROM is supported in the Core Logic module by
enabling the ROMCS# signal on write accesses to the
ROM region. Normally only read cycles are passed to the
ISA bus, and the ROMCS# signal is suppressed for write
cycles. When the ROM Write Enable bit (F0 Index 52h[1])
is set, a write access to the ROM address region causes a
write cycle to occur with MEMW#, WR# and ROMCS#
asserted.
AD8
A8
AD9
A9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
C/BE0#
C/BE1#
C/BE2#
C/BE3#
PAR
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
D0
L3
K1
L4
J1
K4
J3
5.2.5.7 PCI and Sub-ISA Signal Cycle Multiplexing
The SC1200/SC1201 multiplexes most PCI and Sub-ISA
signals on the balls listed in Table 5-3, in order to reduce
the number of balls on the device. Cycle multiplexing is on
a bus-cycle by bus-cycle basis (see Figure 5-6 on page
166), where the internal Core Logic PCI bridge arbitrates
between PCI cycles and Sub-ISA cycles. Other PCI and
Sub-ISA signals remain non-shared, however, some Sub-
ISA signals may be muxed with GPIO.
E1
F4
E3
E2
D3
D1
D2
B6
C2
C4
C1
D4
B4
B3
A3
D5
L1
C7
D7
A6
D6
C6
A5
F4
Sub-ISA cycles are only generated as a result of GX1 mod-
ule accesses to the following addresses or conditions:
C5
D1
D5
• ROMCS# address range.
• DOCCS# address range.
• IOCS0# address range.
D2
A4
D3
B4
D4
C4
D5
A3
• IOCS1# address range.
D6
C2
• An I/O write to address 80h or to 84h.
D7
B3
• Internal ISA is programmed to be the subtractive decode
D8
A13
A10
D8
agent and no other agents claim the cycle.
D9
J2
D10
D11
D12
D13
D14
D15
BHE#
F3
H4
J4
If the Sub-ISA and PCI bus have more than four compo-
nents, the Sub-ISA components can be buffered using
74HCT245 or 74FCT245 type transceivers. The RD# (an
AND of IOR#, MEMR#) signal can be used as DIR control
while TRDE# is used as enable control.
A8
C10
B8
TRDY#
IRDY#
STOP#
DEVSEL#
F1
F2
G1
E4
C8
D9
B5
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Core Logic Module (Continued)
PCI
TCS
Sub-ISA
PCI
TCP
pull-up
FRAME#
TRDY#, IRDY#
GNT[x]
ROMCS#, DOCCS#,
IOCS0#, IOCS1#
PAR,
DEVSEL#,STOP#
AD[31:0],
C/BE[3:0]#
Figure 5-6. PCI Change to Sub-ISA and Back
5.2.6 AT Compatibility Logic
Note: DMA interface signals are not available externally.
The Core Logic module integrates:
DMA Controllers
• Two 8237-equivalent DMA controllers with full 32-bit
The Core Logic module supports seven DMA channels
using two standard 8237-equivalent controllers. DMA Con-
troller 1 contains Channels 0 through 3 and supports 8-bit
I/O adapters. These channels are used to transfer data
between 8-bit peripherals and PCI memory or 8/16-bit ISA
memory. Using the high and low page address registers, a
full 32-bit PCI address is output for each channel so they
can all transfer data throughout the entire 4 GB system
address space. Each channel can transfer data in 64 KB
pages.
addressing
• Two 8259A-equivalent interrupt controllers providing 13
individually programmable external interrupts
• An 8254-equivalent timer for refresh, timer, and speaker
logic
• NMI control and generation for PCI system errors and all
parity errors
• Support for standard AT keyboard controllers
• Positive decode for the AT I/O register space
• Reset control
DMA Controller 2 contains Channels 4 through 7. Channel
4 is used to cascade DMA Controller 1, so it is not available
externally. Channels 5 through 7 support 16-bit I/O adapt-
ers to transfer data between 16-bit I/O adapters and 16-bit
system memory. Using the high and low page address reg-
isters, a full 32-bit PCI address is output for each channel
so they can all transfer data throughout the entire 4 GB
system address space. Each channel can transfer data in
128 KB pages. Channels 5, 6, and 7 transfer 16-bit
WORDs on even byte boundaries only.
5.2.6.1 DMA Controller
The Core Logic module supports industry standard DMA
architecture using two 8237-compatible DMA controllers in
cascaded configuration. The DMA functions supported by
the Core Logic module include:
• Standard seven-channel DMA support
DMA Transfer Modes
• 32-bit address range support via high page registers
Each DMA channel can be programmed for single, block,
demand or cascade transfer modes. In the most commonly
used mode, single transfer mode, one DMA cycle occurs
per DRQ and the PCI bus is released after every cycle.
This allows the Core Logic module to timeshare the PCI
bus with the GX1 module. This is imperative, especially in
cases involving large data transfers, because the GX1
module gets locked out for too long.
• IOCHRDY extended cycles for compatible timing trans-
fers
• Internal Sub-ISA bus master device support using
cascade mode
• NMI control and generation for PCI system errors and all
parity errors.
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In block transfer mode, the DMA controller executes all of
DMA Priority
its transfers consecutively without releasing the PCI bus.
The DMA controller may be programmed for two types of
priority schemes: fixed and rotate (I/O Ports 008h[4] and
0D0h[4] - see Table 5-43 on page 305).
In demand transfer mode, DMA transfer cycles continue to
occur as long as DRQ is high or terminal count is not
reached. In this mode, the DMA controller continues to exe-
cute transfer cycles until the I/O device drops DRQ to indi-
cate its inability to continue providing data. For this case,
the PCI bus is held by the Core Logic module until a break
in the transfers occurs.
In fixed priority, the channels are fixed in priority order
based on the descending values of their numbers. Thus,
Channel 0 has the highest priority. In rotate priority, the last
channel to get service becomes the lowest-priority channel
with the priority of the others rotating accordingly. This pre-
vents a channel from dominating the system.
In cascade mode, the channel is connected to another
DMA controller or to an ISA bus master, rather than to an
I/O device. In the Core Logic module, one of the 8237 con-
trollers is designated as the master and the other as the
slave. The HOLD output of the slave is tied to the DRQ0
input of the master (Channel 4), and the master’s DACK0#
output is tied to the slave’s HLDA input.
The address and WORD Count registers for each channel
are 16-bit registers. The value on the data bus is written
into the upper byte or lower byte, depending on the state of
the internal addressing byte pointer. This pointer can be
cleared by the Clear Byte Pointer command. After this com-
mand, the first read/write to an address or WORD-count
register reads or writes to the low byte of the 16-bit register
and the byte pointer points to the high byte. The next
read/write to an address or WORD-count register reads or
writes to the high byte of the 16-bit register and the byte
pointer points back to the low byte.
In each of these modes, the DMA controller can be pro-
grammed for read, write, or verify transfers.
Both DMA controllers are reset at power-on reset (POR) to
fixed priority. Since master Channel 0 is actually connected
to the slave DMA controller, the slave’s four DMA channels
have the highest priority, with Channel 0 as highest and
Channel 3 as the lowest. Immediately following slave
Channel 3, master Channel 1 (Channel 5) is the next high-
est, followed by Channels 6 and 7.
When programming the 16-bit channels (Channels 5, 6,
and 7), the address which is written to the base address
register must be the real address divided by two. Also, the
base WORD Count for the 16-bit channels is the number of
16-bit WORDs to be transferred, not the number of bytes
as is the case for the 8-bit channels.
DMA Controller Registers
The DMA controller can be programmed with standard I/O
cycles to the standard register space for DMA. The I/O
addresses for the DMA controller registers are listed Table
5-43 on page 305.
The DMA controller allows the user to program the active
level (low or high) of the DRQ and DACK# signals. Since
the two controllers are cascaded together internally on the
chip, these signals should always be programmed with the
DRQ signal active high and the DACK# signal active low.
When writing to a channel's address or WORD Count reg-
ister, the data is written into both the base register and the
current register simultaneously. When reading a channel
address or WORD Count register, only the current address
or WORD Count can be read. The base address and base
WORD Count are not accessible for reading.
DMA Shadow Registers
The Core Logic module contains a shadow register located
at F0 Index B8h (Table 5-29 on page 204) for reading the
configuration of the DMA controllers. This read only regis-
ter can sequence to read through all of the DMA registers.
DMA Transfer Types
DMA Addressing Capability
Each of the seven DMA channels may be programmed to
perform one of three types of transfers: read, write, or ver-
ify. The transfer type selected defines the method used to
transfer a byte or WORD during one DMA bus cycle.
DMA transfers occur over the entire 32-bit address range of
the PCI bus. This is accomplished by using the DMA con-
troller’s 16-bit memory address registers in conjunction
with an 8-bit DMA Low Page register and an 8-bit DMA
High Page register. These registers, associated with each
channel, provide the 32-bit memory address capability. A
write to the Low Page register clears the High Page regis-
ter, for backward compatibility with the PC/AT standard.
The starting address for the DMA transfer must be pro-
grammed into the DMA controller registers and the chan-
nel’s respective Low and High Page registers prior to
beginning the DMA transfer.
For read transfer types, the Core Logic module reads data
from memory and write it to the I/O device associated with
the DMA channel.
For write transfer types, the Core Logic module reads data
from the I/O device associated with the DMA channel and
write to the memory.
The verify transfer type causes the Core Logic module to
execute DMA transfer bus cycles, including generation of
memory addresses, but neither the READ nor WRITE com-
mand lines are activated. This transfer type was used by
DMA Channel 0 to implement DRAM refresh in the original
IBM PC and XT.
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Core Logic Module (Continued)
DMA Page Registers and Extended Addressing
The DMA Page registers provide the upper address bits
during DMA cycles. DMA addresses do not increment or
decrement across page boundaries. Page boundaries for
the 8-bit channels (Channels 0 through 3) are every 64 KB
and page boundaries for the 16-bit channels (Channels 5,
6, and 7) are every 128 KB.
5.2.6.2 Programmable Interval Timer
The Core Logic module contains an 8254-equivalent Pro-
grammable Interval Timer (PIT) configured as shown in
Figure 5-7. The PIT has three timers/counters, each with
an input frequency of 1.19318 MHz (OSC divided by 12),
and individually programmable to different modes.
The gates of Counter 0 and 1 are usually enabled, how-
ever, they can be controlled via F0 Index 50h. The gate of
Counter 2 is connected to I/O Port 061h[0]. The output of
Counter 0 is connected internally to IRQ0. This timer is typ-
ically configured in Mode 3 (square wave output), and used
to generate IRQ0 at a periodic rate to be used as a system
timer function. The output of Counter 1 is connected to I/O
Port 061h[4]. The reset state of I/O Port 061h[4] is 0 and
every falling edge of Counter 1 output causes I/O Port
061h[4] to flip states. The output of Counter 2 is brought
out to the PC_BEEP output. This output is gated with I/O
Port 061h[1].
Before any DMA operations are performed, the Page regis-
ters must be written at the I/O Port addresses in the DMA
controller registers to select the correct page for each DMA
channel. The other address locations between 080h and
08Fh and 480h and 48Fh are not used by the DMA chan-
nels, but can be read or written by a PCI bus master. These
registers are reset to zero at POR. A write to the Low Page
register clears the High Page register, for backward com-
patibility with the PC/AT standard.
For most DMA transfers, the High Page register is set to
zeros and is driven onto PCI address bits AD[31:24] during
DMA cycles. This mode is backward compatible with the
PC/AT standard. For DMA extended transfers, the High
Page register is programmed and the values are driven
onto the PCI addresses AD[31:24] during DMA cycles to
allow access to the full 4 GB PCI address space.
CLK0
CLK1
CLK2
OUT0
OUT1
IRQ0
1.19318 MHz
F0 Index 50h[4]
I/O Port
061h[4]
DMA Address Generation
F0 Index 50h[3]
F0 Index 50h[5]
I/O Port 061h[0]
GATE0
GATE1
GATE2
The DMA addresses are formed such that there is an
upper address, a middle address, and a lower address por-
tion.
F0 Index 50h[6]
PC_BEEP
I/O Port 061h[1]
OUT2
A[1:0]
XD[7:0]
IOW#
The upper address portion, which selects a specific page,
is generated by the Page registers. The Page registers for
each channel must be set up by the system before a DMA
operation. The DMA Page register values are driven on
PCI address bits AD[31:16] for 8-bit channels and
AD[31:17] for 16-bit channels.
WR#
RD#
IOR#
Figure 5-7. PIT Timer
PIT Shadow Register
The PIT registers are shadowed to allow for 0V Suspend to
save/restore the PIT state by reading the PIT’s counter and
write only registers. The read sequence for the shadow
register is listed in F0 Index BAh (see Table 5-29 on page
204).
The middle address portion, which selects a block within
the page, is generated by the DMA controller at the begin-
ning of a DMA operation and any time the DMA address
increments or decrements through a block boundary. Block
sizes are 256 bytes for 8-bit channels (Channels 0 through
3) and 512 bytes for 16-bit channels (Channels 5, 6, and
7). The middle address bits are is driven on PCI address
bits AD[15:8] for 8-bit channels and AD[16:9] for 16-bit
channels.
The lower address portion is generated directly by the DMA
controller during DMA operations. The lower address bits
are output on PCI address bits AD[7:0] for 8-bit channels
and AD[8:1] for 16-bit channels.
BHE# is configured as an output during all DMA opera-
tions. It is driven as the inversion of AD0 during 8-bit DMA
cycles and forced low for all 16-bit DMA cycles.
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5.2.6.3 Programmable Interrupt Controller
Table 5-4. PIC Interrupt Mapping
Mapping
The Core Logic module contains two 8259A-equivalent
programmable interrupt controllers, with eight interrupt
request lines each, for a total of 16 interrupts. The two con-
trollers are cascaded internally, and two of the interrupt
request inputs are connected to the internal circuitry. This
allows a total of 13 externally available interrupt requests.
See Figure 5-9.
Master
IRQ
IRQ0
Connected to the OUT0 (system timer) of
the internal 8254 PIT.
IRQ2
Connected to the slave’s INTR for a cas-
caded configuration.
Each Core Logic IRQ signal can be individually selected to
as edge- or level-sensitive. The four PCI interrupt signals
may be routed internally to any PIC IRQ.
IRQ8#
IRQ13
Connected to internal RTC.
Connected to the FPU interface of the
GX1 module.
.
IRQ15
IRQ14
IRQ12
IRQ11
IRQ10
IRQ9
Interrupts available to other functions
IRQ0
8254 Timer 0
IR0
IR1
IR2
IR3
IR4
IR5
IR6
IR7
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
Internal
INTR
IRQ7
IRQ8#
IRQ9
RTC_IRQ#
IR0
IR1
IR2
IR3
IR4
IR5
IR6
IR7
IRQ6
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
IRQ5
IRQ4
FPU
IRQ3
IRQ1
Figure 5-8. PIC Interrupt Controllers
The Core Logic module allows PCI interrupt signals INTA#,
INTB#, INTC# (muxed with GPIO19+IOCHRDY) and
INTD# (muxed with IDE_DATA7) to be routed internally to
any IRQ signal. The routing can be modified through Core
Logic module’s configuration registers. If this is done, the
IRQ input must be configured to be level- rather than edge-
sensitive. IRQ inputs may be individually programmed to be
active low, level-sensitive with the Interrupt Sensitivity con-
figuration registers at I/O address space 4D0h and 4D1h.
PCI interrupt configuration is discussed in further detail in
“PCI Compatible Interrupts” on page 170.
Three interrupts are available externally depending upon
selected ball multiplexing:
1) IRQ15 (muxed with GPIO11+RI2#),
2) IRQ14 (muxed with TFTD1), and
3) IRQ9 (muxed with IDE_DATA6)
More of the IRQs are available through the use of SERIRQ
(muxed with GPIO39) function. See Table 5-4.
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Core Logic Module (Continued)
PIC Interrupt Sequence
Interrupt Edge/Level Sensitivity registers in I/O Port 4D0h
and 4D1h. However, if the controllers are programmed to
be level-sensitive via ICW1, all interrupts must be level-
sensitive. Figure 5-9 shows the PCI interrupt mapping for
the master/slave 8259A interrupt controller.
A typical AT-compatible interrupt sequence is as follows.
Any unmasked interrupt generates the internal INTR signal
to the CPU. The interrupt controller then responds to the
interrupt acknowledge (INTA) cycles from the CPU. On the
first INTA cycle the cascading priority is resolved to deter-
mine which of the two 8259A controllers output the inter-
rupt vector onto the data bus. On the second INTA cycle
the appropriate 8259A controller drives the data bus with
the correct interrupt vector for the highest priority interrupt.
IRQ[15:14,12:9,7:3,1]
PCI INTA#-INTD#
Steering Registers
F0 Index 5Ch,5Dh
By default, the Core Logic module responds to PCI INTA
cycles because the system interrupt controller is located
within the Core Logic module. This may be disabled with
F0 Index 40h[0]. When the Core Logic module responds to
a PCI INTA cycle, it holds the PCI bus and internally gener-
ates the two INTA cycles to obtain the correct interrupt vec-
tor. It then asserts TRDY# and returns the interrupt vector.
12
4
Level/Edge
Sensitivity
IRQ[13,8#,0]
3
12
PIC I/O Registers
4D0h/4D1h
Each PIC contains registers located in the standard I/O
address locations, as shown in Table 5-46 "Programmable
Interrupt Controller Registers" on page 313.
ICW1
16
IRQ3
IRQ4
An initialization sequence must be followed to program the
interrupt controllers. The sequence is started by writing Ini-
tialization Command Word 1 (ICW1). After ICW1 has been
written, the controller expects the next writes to follow in
the sequence ICW2, ICW3, and ICW4 if it is needed. The
Operation Control Words (OCW) can be written after initial-
ization. The PIC must be programmed before operation
begins.
Master/Slave
8259A PIC
1
IRQ15
INTR
Since the controllers are operating in cascade mode, ICW3
of the master controller should be programmed with a
value indicating that the IRQ2 input of the master interrupt
controller is connected to the slave interrupt controller
rather than an I/O device as part of the system initialization
code. In addition, ICW3 of the slave interrupt controller
should be programmed with the value 02h (slave ID) and
corresponds to the input on the master controller.
Figure 5-9. PCI and IRQ Interrupt Mapping
5.2.7 I/O Ports 092h and 061h System Control
The Core Logic module supports control functions of I/O
Ports 092h (Port A) and 061h (Port B) for PS/2 compatibil-
ity. I/O Port 092h allows a fast assertion of the A20M# or
CPU_RST. (CPU_RST is an internal signal that resets the
CPU. It is asserted for 100 µs after the negation of POR#.)
I/O Port 061h controls NMI generation and reports system
status.The Core Logic module generates an SMI for every
internal change of the A20M# state and the SMI handler
sets the A20M# state inside the GX1 module. This method
is used for both the Port 092h (PS/2) and Port 061h (key-
board) methods of controlling A20M#.
PIC Shadow Register
The PIC registers are shadowed to allow for 0V Suspend to
save/restore the PIC state by reading the PICs write only
registers. A write to this register resets the read sequence
to the first register. The read sequence for the shadow reg-
ister is listed in F0 Index B9h.
PCI Compatible Interrupts
5.2.7.1 I/O Port 092h System Control
The Core Logic module allows the PCI interrupt signals
INTA#, INTB#, INTC#, and INTD# (also known in industry
terms as PIRQx#) to be mapped internally to any IRQ sig-
nal with the PCI Interrupt Steering registers 1 and 2, F0
Index 5Ch and 5Dh.
I/O Port 092h allows for a fast keyboard assertion of an
A20# SMI and a fast keyboard CPU reset. Decoding for this
register may be disabled via F0 Index 52h[3].
The assertion of a fast keyboard A20# SMI is controlled by
either I/O Port 092h or by monitoring for the keyboard com-
mand sequence (see Section 5.2.8.1 "Fast Keyboard Gate
Address 20 and CPU Reset" on page 171). If bit 1 of I/O
Port 092h is cleared, the Core Logic module internally
asserts an A20M#, which in turn causes an SMI to the
GX1 module. If bit 1 is set, A20M# is internally de-
asserted, again causing an SMI.
PCI interrupts are low-level sensitive, whereas PC/AT inter-
rupts are positive-edge sensitive; therefore, the PCI inter-
rupts are inverted before being connected to the 8259A.
Although the controllers default to the PC/AT-compatible
mode (positive-edge sensitive), each IRQ may be individu-
ally programmed to be edge or level sensitive using the
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Core Logic Module (Continued)
The assertion of a fast keyboard reset (WM_RST SMI) is
controlled by bit 0 in I/O Port 092h or by monitoring for the
keyboard command sequence (write data = FEh to I/O port
64h). If bit 0 is changed from 0 to 1, the Core Logic module
generates a reset to the GX1 module by generating a
WM_RST SMI. When the WM_RST SMI occurs, the BIOS
jumps to the Warm Reset vector. Note that Warm Reset is
not a pin, it is under SMI control.
disabled if F0 Index 5Ah[1] is cleared (i.e., subtractive
decoding enabled).
5.2.8.1 Fast Keyboard Gate Address 20 and CPU
Reset
The Core Logic module monitors the keyboard I/O Ports
064h and 060h for the fast keyboard A20M# and CPU reset
control sequences. If a write to I/O Port 060h[1] = 1 after a
write takes place to I/O Port 064h with data of D1h, then
the Core Logic module asserts the A20M# signal. A20M#
remains asserted until cleared by any one of the following:
5.2.7.2 I/O Port 061h System Control
Through I/O Port 061h, the speaker output can be enabled,
the status of IOCHK# and SERR# can be read, and the
state of the speaker data (Timer2 output) and refresh tog-
gle (Timer1 output) can be read back. Note that NMI is
under SMI control. Even though the hardware is present,
the IOCHK# ball does not exist. Therefore, an NMI from
IOCHK# can not happen.
• A write to bit 1 of I/O Port 092h.
• A CPU reset of some kind.
• A write to I/O Port 060h[1] = 0 following a write to I/O
Port 064h with data of D1h.
The fast keyboard A20M# and CPU reset can be disabled
through F0 Index 52h[7]. By default, bit 7 is set, and the
fast keyboard A20M# and CPU reset monitor logic is
active. If bit 7 is clear, the Core Logic module forwards the
commands to the keyboard controller.
5.2.7.3 SMI Generation for NMI
Figure 5-10 shows how the Core Logic module can gener-
ate an SMI for an NMI. Note that NMI is not a pin.
5.2.8 Keyboard Support
By default, the Core Logic module forces the de-assertion
of A20M# during a warm reset. This action may be dis-
abled if F0 Index 52h[4] is cleared.
The Core Logic module can actively decode the keyboard
controller I/O Ports 060h, 062h, 064h and 066h, and gener-
ate an LPC bus cycle. Keyboard positive decoding can be
IOCHK#
(No External Connection)
Parity Errors
AND
System Errors
AND
F0 Index 04h[6]
F0 Index 40h[1]
AND
F0 Index 04h[8]
I/O Port 061h[3]
AND
NMI
SERR#
OR
PERR#
I/O Port 061h[2]
NMI
F0 Index 04h: PCI Command Register
Bit 6 = PE (PERR# Enable)
Bit 8 = SE (SERR# Enable)
AND
F0 Index 40h: PCI Function Control Register 1
Bit 1 = PES (PERR# Signals SERR#)
OR
I/O Port 070h[7]
I/O Port 061h: Port B
Bit 2 = ERR_EN (PERR#/SERR# Enable)
Bit 3 = IOCHK_EN (IOCHK Enable)
AND
SMI
I/O Port 070h: RTC Index Register (WO)
Bit 72 = NMI (NMI Enable)
Figure 5-10. SMI Generation for NMI
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Core Logic Module (Continued)
5.2.9 Power Management Logic
C0 Power State - On
The Core Logic module integrates advanced power man-
agement features including idle timers for common system
peripherals, address trap registers for programmable
address ranges for I/O or memory accesses, four program-
mable general purpose external inputs, clock throttling with
automatic speedup for the GX1 clock, software GX1 stop
clock, 0V Suspend/Resume with peripheral shadow regis-
ters, and a dedicated serial bus to/from the GX1 module
providing power management status.
In this state the GX1 module executes code. This state has
two sub-states: Full Speed or Throttling; selected via the
THT_EN bit (F1BAR1+I/O Offset 00h[4]).
C1 Power State - Active Idle
The SC1200/SC1201 enters the C1 state, when the Halt
Instruction (HLT) is executed. It exits this state back to the
C0 state upon an NMI, an unmasked interrupt, or an SMI.
The Halt instruction stops program execution and gener-
ates a special Halt bus cycle. (See “Usage Hints” on page
175.)
The Core Logic module is ACPI (Advanced Configuration
Power Interface) compliant. An ACPI-compliant system is
one whose underlying BIOS, device drivers, chipset and
peripherals conform to revision 1.0 of the ACPI specifica-
tion. The Core Logic also supports Advanced Power Man-
agement (APM).
Bus masters are supported in the C1 state and the
SC1200/SC1201 will temporarily exit C1 to perform a bus
master transaction.
C2 Power State
The SC1200/SC1201 provides the following support of
ACPI states:
The SC1200/SC1201 does not support the C2 power state.
All relevant registers and bit fields in the Core Logic are
reserved.
• CPU States: C0, C1, and C3.
• Sleep States:
C3 Power State
— SL1/SL2 - ACPI S1 equivalent.
— SL3 - ACPI S3 equivalent.
— SL4 - ACPI S4 equivalent.
— SL5 - ACPI S5 equivalent.
The SC1200/SC1201 enters the C3 state, when the
P_LVL3 register (F1BAR1+I/O Offset 05h) is read. It exits
this state back to the C0 state (Full Speed or Throttling,
depending on the THT_EN bit) upon:
• General Purpose Events: Fully programmable GPE0
• An NMI, an unmasked interrupt, or an SMI.
Event Block registers.
• A bus master request, if enabled via the BM_RLD bit
• Wakeup Events: Supported through GPWIO[2:0] which
are powered by standby voltage and generate SMIs.
See registers at F1BAR1+I/O Offset 0Ah and
(F1BAR1+I/O Offset 0Ch[1]).
In this state, the GX1 module is in Suspend Refresh mode
(for details, see the Power Management section of the GX1
Processor Series Datasheet, and Section 5.2.9.5 "Usage
Hints" on page 175).
F1BAR1+I/O Offset 12h. Also see Section 4.6 "System
Wakeup Control (SWC)" on page 130 and Table 5-5
"Wakeup Events Capability" on page 173.
PCI arbitration should be disabled prior entering the C3
state via the ARB_DIS bit in the PM2_CNT register
(F1BAR1+I/O Offset 20h[0]) because a PCI arbitration
event could start after P_LVL3 has been read. After
wakeup ARB_DIS needs to be cleared.
SC1200/SC1201 device power management is highly
tuned for low power systems. It allows the system designer
to implement a wide range of power saving modes using a
wide range of capabilities and configuration options.
SC1200/SC1201 controls the following functions directly:
• The system clocks.
5.2.9.2 Sleep States
The SC1200/SC1201 supports four Sleep states (SL1-
SL3) and the Soft Off state (G2/S5). These states are fully
compliant with the ACPI specification, revision 1.0.
• Core processor power states.
• Wakeup/resume event detection, including general
purpose events.
When the SLP_EN bit (F1BAR1+I/O Offset 0Ch[13]) is set
to 1, the SC1200/SC1201 enters an SLx state according to
the SLP_TYPx field (F1BAR1+I/O Offset 0Ch[12:10]). It
exits the Sleep state back to the S0 state (C0 state - Full
Speed or Throttling, depending on the THT_EN bit) upon
an enabled power management event. Table 5-5 on page
173 lists wakeup events from the various Sleep states.
• Power supply and power planes.
It also supports systems with an external micro controller
that is used as a power management controller.
5.2.9.1 CPU States
The SC1200/SC1201 supports three CPU states: C0, C1
and C3 (the Core Logic C2 CPU state is not supported).
These states are fully compliant with the ACPI specifica-
tion, revision 1.0. These states occur in the Working state
only (S0/G0). They have no meaning when the system
transitions into a Sleep state. For details on the various
Sleep states, see Section 5.2.9.2 "Sleep States" on page
172.
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Core Logic Module (Continued)
SL1 Sleep State (ACPI S1)
SL3 Sleep State (ACPI S3)
In this state the core processor is in 3V Suspend mode (all
its clocks are stopped, including the memory controller and
the display controller). The SDRAM is placed in self-refresh
mode. All other SC1200/SC1201 system clocks and PLLs
are running. All devices are powered up (PWRCNT[2:1]
and ONCTL# are all asserted). See Section 5.2.9.5 "Usage
Hints" on page 175.
In this state, the SDRAM is placed in self-refresh mode,
and PWRCNT[2:1] are de-asserted. PWRCNT[2:1] should
be used to power off most of the system (except for the
SDRAM). If the Save-to-RAM feature is used, external cir-
cuitry in the SDRAM interface is required to guarantee data
integrity. All SC1200/SC1201 signals powered by VSB
,
VSBL or VBAT are still functional to allow wakeup and to
keep the RTC.
No reset is performed, when exiting this state. The
SC1200/SC1201 keeps all context in this state. This state
corresponds to ACPI Sleep state S1.
The power-up sequence is performed, when exiting this
state. This state corresponds to ACPI Sleep state S3.
SL2 Sleep State (ACPI S1)
SL4 and SL5 Sleep States (ACPI S4 and S5)
In this state, all of the SC1200/SC1201 clocks are stopped
including the PLLs. Selected clocks from the PLLs can be
kept running under program control (F0 Index 60h). An
exception to this is the CLK32 output signal which keeps
toggling and the 32 KHz oscillator itself. The SDRAM is
placed in self-refresh mode. The PWRCNT1 pin is de-
asserted. The SC1200/SC1201 itself is powered up. The
system designer can decide which other system devices to
power off with the PWRCNT1 pin.
The SL4 and SL5 states are similar from the hardware per-
spective. In these states, the SC1200/SC1201 de-asserts
PWRCNT[2:1] and ONCTL#. PWRCNT[2:1] and ONCTL#
should be used to power off the system. All signals pow-
ered by VSB, VSBL or VBAT are still functional to allow
wakeup and to keep the RTC.
While in this state, LED# can be toggled to give visual noti-
fication of this state. ACPI Function Control register
(F1BAR1+I/O Offset 07h[7:6]) is used to control LED#.
No reset is performed, when exiting this state. The
SC1200/SC1201 keeps all context in this state. This state
corresponds to ACPI sleep state S1, with lower power and
longer wake time than in SL1.
The power-up sequence is performed when exiting this
state. This state corresponds to ACPI Sleep states S4 and
S5.
Table 5-5. Wakeup Events Capability
S0/C1 S0/C3 SL1 SL2
Yes Yes
Event
SL3
SL4, SL5
Enabled Interrupts
Yes
Yes
Yes
Yes
Yes
Yes
-
-
-
SMI according to Table 5-8
SCI according to Table 5-8
GPIO[47:32], GPIO[15:0]
Power Button
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
-
-
-
-
-
-
-
-
Yes
Yes
-
Yes
Yes
-
Yes
Yes
-
Power Button Override
Bus Master Request
Yes1
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Thermal Monitoring
USB
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
-
SDATA_IN2 (AC97)
IRRX1 (Infrared)
GPWIO[2:0]
-
-
-
-
Yes
-
Yes
-
RI2# (UART2)
RTC
Yes
Yes
1. Temporarily exits state.
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Core Logic Module (Continued)
5.2.9.3 Power Planes Control
5.2.9.4 Power Management Events
The SC1200/SC1201 supports power management events
that can manage:
The SC1200/SC1201 supports up to three power planes.
Three signals are used to control these power planes.
Table 5-6 describes the signals and when each is asserted.
• Transition of the system from a Sleep state to a Work
state. This is done by the hardware. These events are
defined as wakeup events.
Table 5-6. Power Planes Control Signals vs.
Sleep States
• Enabled wakeup events to set the WAK_STS bit
(F1BAR1+I/O Offset 08h[15]) to 1, when transitioning
the system back to the working state.
SL4
and
Signal
S0
SL1
SL2
SL3
SL5
• Generation of an interrupt. This invokes the relevant
software driver. The interrupt can either be an SMI or
SCI (selected by the SCI_EN bit, F1BAR1+I/O Offset
0Ch[0]). These events are defined as interrupt events.
PWRCNT1
PWRCNT2
ONCTL#
1
1
0
1
1
0
0
1
0
0
0
0
0
0
1
Table 5-8 lists the power management events that can gen-
erate an SCI or SMI.
These signals allow control of the power of system devices
and the SC1200/SC1201 itself. Table 5-7 describes the
SC1200/SC1201 power planes with respect to the different
Sleep and Global states.
Table 5-8. Power Management Events
Event
SCI
SMI
Power Button
Power Button Override
Bus Master Request
Thermal Monitoring
USB
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
Table 5-7. Power Planes vs. Sleep/Global States
-
VCORE
,
VCCCRT, VI/O
,
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
Sleep/
Global
State
AVCCTV, VPLL
,
AVCCCRT
VSB, VSBL
VBAT
RTC
S0, SL1 and
SL2
On
Off
On
On or Off
ACPI Timer
GPIO
SL3, SL4
and SL5
On
On or Off
SDATA_IN2 (AC97)
IRRX1
G3
Off
Off
On
Off
Off
Off
On
Off
RI2#
No Power
Illegal
GPWIO
On or Off
Internal SMI signal
The SC1200/SC1201 power planes are controlled exter-
nally by the three signals (i.e., the system designer should
make sure the system design is such that Table 5-7 is met)
for all supported Sleep states.
Power Button
The power button (PWRBTN#) input provides two events: a
wake request, and a sleep request. For both these events,
the PWRBTN# signal is debounced (i.e., the signal state is
transferred only after 14 to 16 ms without transitions, to
ensure that the signal is no longer bouncing).
VSB and VBAT are not controlled by any control signal. VSB
exists as long as the AC power is plugged in (for desktop
systems) or the main battery is charged (for mobile sys-
tems). VBAT exists as long as the RTC battery is charged.
ACPI is non-functional when the power-up sequence does
not include using the power button. If ACPI functionality is
desired, the power button must be toggled. This can be
done externally or internally. GPIO63 is internally con-
nected to PWRBTN#. To toggle the power button with soft-
ware, GPIO63 must be programmed as an output using the
normal GPIO programming protocol (see Section 5.4.1.1
"GPIO Support Registers" on page 236). GPIO63 must be
pulsed low for at least 16 ms and not more than 4 sec.
Asserting POR# has no effect on ACPI. If POR# is
asserted and ACPI was active prior to POR#, then ACPI
The case in which VSB does not exist is called Mechanical
Off (G3).
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Core Logic Module (Continued)
will remain active after POR#. Therefore, BIOS must
ensure that ACPI is inactive before GPIO63 is pulsed low.
• SMM code should correctly set the CLK_STP bit in the
PM Clock Stop Control register (GX_BASE+Memory
Offset 8500h[0]) when entering the SL1, SL2, and SL3
states.
Power Button Wake Event - Detection of a high-to-low
transition on the debounced PWRBTN# input signal when
in SL1 to SL5 Sleep states. The system is considered in
the Sleep state, only after it actually transitioned into the
state and not only according to the SLP_TYP field.
5.2.10 Power Management Programming
The power management resources provided by a com-
bined GX1 module and Core Logic module based system
supports a high efficiency power management implementa-
tion. The following explanations pertain to a full-featured
“notebook” power management system. The extent to
which these resources are employed depends on the appli-
cation and on the discretion of the system designer.
In reaction to this event, the PWRBTN_STS bit
(F1BAR1+I/O Offset 08h[8]) is set to 1 and a wakeup event
or an interrupt is generated (note that this is regardless of
the PWRBTN_EN bit, F1BAR1+I/O Offset 0Ah[8]).
Power Button Sleep Event - Detection of a high-to-low
transition on the debounced PWRBTN# input signal, when
in the Working state (S0).
Power management resources can be grouped according
to the function they enable or support. The major functions
are as follows:
In reaction to this event, the PWRBTN_STS bit is set to 1.
• APM Support
• When both the PWRBTN_STS bit and the
PWRBTN_EN bit are set to 1, an SCI interrupt is gener-
ated.
• CPU Power Management
— Suspend Modulation
— 3V Suspend
• When SCI_EN bit is 0, ONCTL# and PWRCNT[2:1] are
de-asserted immediately regardless of the
PWRBTN_EN bit.
— Save-to-Disk
• Peripheral Power Management
— Device Idle Timers and Traps
— General Purpose Timers
Power Button Override
— ACPI Timer Register
— Power Management SMI Status Reporting Registers
When PWRBTN# is 0 for more than four seconds, ONCTL#
and PWRCNT[2:1] are de-asserted (i.e., the system transi-
tions to the SL5 state, "Soft Off"). This power management
event is called the power button override event.
Included in the following subsections are details regarding
the registers used for configuring power management fea-
tures. The majority of these registers are directly accessed
through the PCI configuration register space designated as
Function 0 (F0). However, included in the discussions are
references to F1BARx+I/O Offset xxh. This refers to regis-
ters accessed through base address registers in Function 1
(F1) at Index 10h (F1BAR0) and Index 40h (F1BAR1).
In reaction to this event, the PWRBTN_STS bit is cleared
to 0 and the PWRBTNOR_STS bit (F1BAR1+I/O Offset
08h[11]) is set to 1.
Thermal Monitoring
The thermal monitoring event (THRM#) enables control of
ACPI-OS Control.
5.2.10.1 APM Support
When the THRM# signal transitions from high-to-low, the
THRM_STS bit (F1BAR1+I/O Offset 10h[5]) is set to 1. If
the THRM_EN bit (F1BAR1+I/O Offset 12h[5]) is also set
to 1, an interrupt is generated.
Many notebook computers rely solely on an Advanced
Power Management (APM) driver for enabling the operat-
ing system to power-manage the CPU. APM provides sev-
eral services which enhance the system power
management; but in its current form, APM is imperfect for
the following reasons:
SDATA_IN2, IRRX1, RI2#
Section 4.4.1 "SIO Control and Configuration Registers" on
page 111 for control and operation.
• APM is an OS-specific driver, and may not be available
for some operating systems.
5.2.9.5 Usage Hints
• Application support is inconsistent. Some applications in
• During initialization, the BIOS should:
— Clear the SUSP_HLT bit in CCR2 (GX1 module,
Index C2h[3]) to 0. This is needed for compliance
with C0 definition of ACPI, when the Halt Instruction
(HLT) is executed.
foreground may prevent Idle calls.
• APM does not help with Suspend determination or
peripheral power management.
The Core Logic module provides two entry points for APM
support:
— Disable the SUSP_3V option in C3 power state (F0
Index 60h[2]).
— Disable the SUSP_3V option in SL1 sleep state (F0
Index 60h[1]).
• Software CPU Suspend control via the CPU Suspend
Command register (F0 Index AEh).
• Software SMI entry via the Software SMI register (F0
Index D0h). This allows the APM BIOS to be part of the
SMI handler.
• SMM code should clear the CLK_STP bit in the PM
Clock Stop Control register (GX_BASE+Memory Offset
8500h[0]) to 0 when entering C3 state.
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Core Logic Module (Continued)
5.2.10.2 CPU Power Management
major I/O events occur, Suspend Modulation should be
temporarily disabled using the procedures described in the
Power Management registers in the following subsections.
The three greatest power consumers in a system are the
display, the hard drive, and the CPU. The power manage-
ment of the first two is relatively straightforward and is dis-
If a bus master (UltraDMA/33, Audio, USB) request occurs,
the GX1 module automatically de-asserts SUSPA# and
grants the bus to the requesting bus master. When the bus
master de-asserts REQ#, SUSPA# reasserts. This does
not directly affect the Suspend Modulation programming.
cussed
in Section
5.2.10.3 "Peripheral
Power
Management" on page 177.
APM, if available, is used primarily by CPU power manage-
ment since the operating system is most capable of report-
ing the Idle condition. Additional resources provided by the
Core Logic module supplement APM by monitoring exter-
nal activity and power managing the CPU based on the
system demands. The two processes for power managing
the CPU are Suspend Modulation and 3V Suspend.
Configuring Suspend Modulation: Control of the Sus-
pend Modulation feature is accomplished using the Sus-
pend Modulation and Suspend Configuration registers (F0
Index 94h and 96h, respectively).
The Suspend Configuration register contains the global
power management enable bit, as well as the enables for
the individual activity speedup timers. The global power
management bit must be enabled for Suspend Modulation
and all other power management resources to function.
Suspend Modulation
Suspend Modulation works by asserting and de-asserting
the internal SUSP# signal to the GX1 module for config-
urable durations. When SUSP# is asserted to the GX1
module, it enters an Idle state during which time the power
consumption is significantly reduced. Even though the PCI
clock is still running, the GX1 module stops the clocks to its
core when SUSP# is asserted. By modulating SUSP# a
reduced frequency of operation is achieved.
Bit 0 of the Suspend Configuration register enables Sus-
pend Modulation. Bit 1 controls how SMI events affect Sus-
pend Modulation. In general this bit should be set to 1,
which causes SMIs to disable Suspend Modulation until it
is re-enabled by the SMI handler.
The Suspend Modulation feature works by assuming that
the GX1 module is Idle unless external activity indicates
otherwise. This approach effectively slows down the GX1
module until external activity indicates a need to run at full
speed, thereby reducing power consumption. This
approach is the opposite of that taken by most power man-
agement schemes in the industry, which run the system at
full speed until a period of inactivity is detected, and then
slows down. Suspend Modulation, the more aggressive
approach, yields lower power consumption.
The Suspend Modulation register controls two 8-bit
counters that represent the number of 32 µs intervals that
the internal SUSP# signal is asserted and then de-
asserted to the GX1 module. These counters define a ratio
which is the effective frequency of operation of the system
while Suspend Modulation is enabled.
Asserted Count
Feff = FGX1
x
Asserted Count + de-asserted Count
Suspend Modulation serves as the primary CPU power
management mechanism when APM is not present. It also
acts as a backup for situations where APM does not cor-
rectly detect an Idle condition in the system.
The IRQ and Video Speedup Timer Count registers (F0
Index 8Ch and 8Dh) configure the amount of time which
Suspend Modulation is disabled when the respective
events occur.
To provide high-speed performance when needed, SUSP#
modulation is temporarily disabled any time system activity
is detected. When this happens, the GX1 module is
“instantly” converted to full speed for a programmed dura-
tion. System activities in the Core Logic module are
asserted as: any unmasked IRQ, accessing Port 061h, any
asserted SMI, and/or accessing the Video Processor mod-
ule interface.
SMI Speedup Disable: If the Suspend Modulation feature
is being used for CPU power management, the occurrence
of an SMI disables Suspend Modulation so that the system
operates at full speed while in SMM. There are two meth-
ods used to invoke this via bit 1 of the Suspend Configura-
tion register.
1) If F0 Index 96h[1] = 0: Use the IRQ Speedup Timer
(F0 Index 8Ch) to temporarily disable Suspend Modu-
lation when an SMI occurs.
The graphics controller is integrated in the GX1 module.
Therefore, the indication of video activity is sent to the Core
Logic module via the serial link (see Section 5.2.2 "PSE-
RIAL Interface" on page 157 for more information on serial
link) and is automatically decoded. Video activity is defined
as any access to the VGA register space, the VGA frame
buffer, the graphics accelerator control registers and the
configured graphics frame buffer.
2) If F0 Index 96h[1] = 1: Disable Suspend Modulation
when an SMI occurs until a read to the SMI Speedup
Disable register (F1BAR0+I/O Offset 08h).
The SMI Speedup Disable register prevents VSA software
from entering Suspend Modulation while operating in
SMM. The data read from this register can be ignored. If
the Suspend Modulation feature is disabled, reading this
I/O location has no effect.
The automatic speedup events (video and IRQ) for Sus-
pend Modulation should be used together with software-
controlled speedup registers for major I/O events such as
any access to the FDC, HDD, or parallel/serial ports, since
these are indications of major system activities. When
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3 Volt Suspend
5.2.10.3 Peripheral Power Management
The Core Logic module supports the stopping of the CPU
and system clocks for a 3V Suspend state. If appropriately
configured, via the Clock Stop Control register (F0 Index
BCh), the Core Logic module asserts internal SUSP_3V
after it has gone through the SUSP#/SUSPA# handshake.
SUSP_3V is a state indicator, indicating that the system is
in a low-activity state and Suspend Modulation is active.
This indicator can be used to put the system into a low-
power state (the system clock can be turned off).
The Core Logic module provides peripheral power man-
agement using a combination of device idle timers, address
traps, and general purpose I/O pins. Idle timers are used in
conjunction with traps to support powering down peripheral
devices.
Device Idle Timers and Traps
Idle timers are used to power manage a peripheral by
determining when the peripheral has been inactive for a
specified period of time, and removing power from the
peripheral at the end of that time period.
Internal SUSP_3V is connected to the enable control of the
clock generators, so that the clocks to the CPU and the
Core Logic module (and most other system devices) are
stopped. The Core Logic module continues to decrement
all of its device timers and respond to external SMI inter-
rupts after the input clock has been stopped, as long as the
32 KHz clock continues to oscillate. Any SMI event or
unmasked interrupt causes the Core Logic module to de-
assert SUSP_3V, restarting the system clocks. As the CPU
or other device might include a PLL, the Core Logic module
holds SUSP# active for a pre-programmed period of delay
(the PLL re-sync delay) that varies from 0 to 15 ms. After
this period has expired, the Core Logic module de-asserts
SUSP#, stopping Suspend. SMI# is held active for the
entire period, so that the CPU reenters SMM when the
clocks are restarted.
Idle timers are provided for the commonly-used peripherals
(FDC, IDE, Parallel/Serial Ports, and Mouse/Keyboard). In
addition, there are three user-defined timers that can be
configured for either I/O or memory ranges.
The idle timers are 16-bit countdown timers with a one sec-
ond time base, providing a timeout range of 1 to 65536
seconds (1092 minutes) (18 hours).
When the idle timer count registers are loaded with a non-
zero value and enabled, the timers decrement until one of
two possibilities happens: a bus cycle occurs at that I/O or
memory range, or the timer decrements to zero.
If a bus cycle occurs, the timer is reloaded and begins dec-
rementing again. If the timer decrements to zero, and
power management is enabled (F0 Index 80h[0] = 1), the
timer generates an SMI.
Save-to-Disk
Save-to-Disk is supported by the Core Logic module. In
this state, the power is typically removed from the Core
Logic module and from the entire SC1200/SC1201, caus-
ing the state of the legacy peripheral devices to be lost.
Shadow registers are provided for devices which allow their
state to be saved prior to removing power. This is neces-
sary because the legacy AT peripheral devices used sev-
eral write only registers. To restore the exact state of these
devices on resume, the write only register values are
“shadowed” so that the values can be saved by the power
management software.
When an idle timer generates an SMI, the SMI handler
manages the peripheral power, disables the timer, and
enables the trap. The next time an event occurs, the trap
generates an SMI. This time, the SMI handler applies
power to the peripheral, resets the timer, and disables the
trap.
Relevant registers for controlling Device Idle Timers are: F0
Index 80h, 81h, 82h, 93h, 98h-9Eh, and ACh.
Relevant registers for controlling User Defined Device Idle
Timers are: F0 Index 81h, 82h, A0h, A2h, A4h, C0h, C4h,
C8h, CCh, CDh, and CEh.
The PC/AT compatible keyboard controller (KBC) and
floppy port (FDC) do not exist in the SC1200/SC1201.
However, it is possible that one is attached on the ISA bus
or the LPC bus (e.g., in a SuperI/O device). Some of the
KBC and FDC registers are shadowed because they can-
not be safely read. Additional shadow registers for other
functions are described in Table 5-29 "F0: PCI Header and
Bridge Configuration Registers for GPIO and LPC Support"
on page 204.
Although not considered as device idle timers, two addi-
tional timers are provided by the Core Logic module. The
Video Idle Timer used for Suspend-determination and the
VGA Timer used for SoftVGA.
The programming bits for these timers are:
• F0 Index 81h[7], Video Access Idle Timer Enable
• F0 Index 82h[7], Video Access Trap Enable
• F0 Index A6h[15:0], Video Timer Count
• F0 Index 83h[3], VGA Timer Enable
• F0 Index 8Bh[6], VGA Timer Base
• F0 Index 8Eh[7:0], VGA Timer Count
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Core Logic Module (Continued)
General Purpose Timers
Power Management SMI Status Reporting Registers
The Core Logic module updates status registers to reflect
the SMI sources. Power management SMI sources are the
device idle timers, address traps, and general purpose I/O
pins.
The Core Logic module contains two general purpose idle
timers, General Purpose Timer 1 (F0 Index 88h) and Gen-
eral Purpose Timer 2 (F0 Index 8Ah). These two timers are
similar to the Device Idle Timers in that they count down to
zero unless re-triggered, and generate an SMI when they
reach zero. However, these are 8-bit timers instead of 16
bits, they have a programmable timebase, and the events
which reload these timers are configurable. These timers
are typically used for an indication of system inactivity for
Suspend determination.
Power management events are reported to the GX1 mod-
ule through the active low SMI# signal. When an SMI is ini-
tiated, the SMI# signal is asserted low and is held low until
all SMI sources are cleared. At that time, SMI# is de-
asserted.
All SMI sources report to the Top Level SMI Status register
(F1BAR0+I/O Offset 02h) and the Top Level SMI Status
Mirror register (F1BAR0+I/O Offset 00h). The Top SMI Sta-
tus and Status Mirror registers are the top level of hierarchy
for the SMI Handler in determining the source of an SMI.
These two registers are identical except that reading the
register at F1BAR0+I/O Offset 02h clears the status.
General Purpose Timer 1 can be re-triggered by activity to
any of the configured User Defined Devices, Keyboard and
Mouse, Parallel and Serial, Floppy disk, or Hard disk.
General Purpose Timer 2 can be re-triggered by a transi-
tion on the GPIO7 signal (if GPIO7 is properly configured).
When a General Purpose Timer is enabled or when an
event reloads the timer, the timer is loaded with the config-
ured count value. Upon expiration of the timer an SMI is
generated and a status flag is set. Once expired, this
counter must be re-initialized by disabling and enabling it.
Since all SMI sources report to the Top Level SMI Status
register, many of its bits combine a large number of events
requiring a second level of SMI status reporting. The sec-
ond level of SMI status reporting is set up very much like
the top level. There are two status reporting registers, one
“read only” (mirror) and one “read to clear”. The data
returned by reading either offset is the same, the difference
between the two being that the SMI can not be cleared by
reading the mirror register.
The timebase for both General Purpose Timers can be
configured as either 1 second (default) or 1 millisecond.
The registers at F0 Index 89h and 8Bh are the control reg-
isters for the General Purpose Timers.
ACPI Timer Register
Figure 5-11 on page 179 shows an example SMI tree for
checking and clearing the source of General Purpose Tim-
ers and the User Defined Trap generated SMI.
The ACPI Timer register (F1BAR0+I/O Offset 1Ch or at
F1BAR1+I/O Offset 1Ch) provides the ACPI counter. The
counter counts at 14.31818/4 MHz (3.579545 MHz). If SMI
generation is enabled (F0 Index 83h[5] = 1), an SMI or SCI
is generated when bit 23 toggles.
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SMI# Asserted
SMM software reads SMI Header
If Bit X = 1
(External SMI)
If Bit X = 0
(Internal SMI)
Call internal SMI handler
to take appropriate action
GX1
Module
Core Logic
Module
F1BAR0+I/O
Offset 02h
Read to Clear
to determine
top-level source
of SMI
SMI de-asserted after all SMI Sources are Cleared
(i.e., Top and Second Levels - note some sources may have a Third Level)
F1BAR0+I/O
Offset 06h
Read to Clear
to determine
second-level
source of SMI
Bits [15:10]
Other_SMI
If bit 9 = 1,
Source of SMI
Bits [15:6]
RSVD
is GP Timer or UDEF Trap
Bit 9
GTMR_TRP_SMI
Bit 5
PCI_TRP_SMI
Bit 4
UDEF3_TRP_SMI
Bit 3
Take
UDEF2_TRP_SMI
Appropriate
Action
Bits [8:0]
Other_SMI
Bit 2
UDEF1_TRP_SMI
Bit 1
GPT2_SMI
Bit 0
GPT1_SMI
Top Level
Second Level
Figure 5-11. General Purpose Timer and UDEF Trap SMI Tree Example
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Core Logic Module (Continued)
5.2.10.4 Power Management Programming Summary
Table 5-9 provides a programming register summary for the
power management timers, traps, and functions. For com-
plete bit information regarding the registers listed in Table
5-9, refer to Section 5.4.1 "Bridge, GPIO, and LPC Regis-
ters - Function 0" on page 204.
Table 5-9. Device Power Management Programming Summary
Located at F0 Index xxh Unless Otherwise Noted
Device Power
Management Resource
Second Level
SMI Status/No Clear
Second Level SMI
Status/With Clear
Enable
Configuration
Global Timer Enable
80h[0]
81h[3]
81h[2]
81h[1]
81h[7]
N/A
N/A
N/A
Keyboard / Mouse Idle Timer
Parallel / Serial Idle Timer
Floppy Disk Idle Timer
93h[1:0]
85h[3]
85h[2]
85h[1]
85h[7]
F5h[3]
F5h[2]
F5h[1]
F5h[7]
93h[1:0]
9Ah[15:0], 93h[7]
A6h[15:0]
Video Idle Timer1
VGA Timer2
83h[3]
8Eh[7:0]
F1BAR0+I/O
Offset 00h[6]
F1BAR0+I/O
Offset 02h[6]
Primary Hard Disk Idle Timer
81h[0]
98h[15:0], 93h[5]
ACh[15:0], 93h[4]
85h[0]
86h[4]
85h[4]
F5h[0]
F6h[4]
F5h[4]
Secondary Hard Disk Idle Timer 83h[7]
User Defined Device 1 Idle
Timer
81h[4]
81h[5]
81h[6]
A0h[15:0], C0h[31:0],
CCh[7:0]
User Defined Device 2 Idle
Timer
A2h[15:0], C4h[31:0],
CDh[7:0]
85h[5]
85h[6]
F5h[5]
F5h[6]
User Defined Device 3 Idle
Timer
A4h[15:0], C8h[31:0],
CEh[7:0]
Global Trap Enable
80h[2]
82h[3]
82h[2]
82h[1]
82h[7]
82h[0]
83h[6]
82h[4]
N/A
N/A
N/A
Keyboard / Mouse Trap
Parallel / Serial Trap
Floppy Disk Trap
9Eh[15:0] 93h[1:0]
9Ch[15:0], 93h[1:0]
93h[7]
86h[3]
86h[2]
86h[1]
86h[7]
86h[0]
86h[5]
F6h[3]
F6h[2]
F6h[1]
F6h[7]
F6h[0]
F6h[5]
Video Access Trap
N/A
Primary Hard Disk Trap
Secondary Hard Disk Trap
User Defined Device 1 Trap
93h[5]
93h[4]
C0h[31:0], CCh[7:0]
F1BAR0+I/O
Offset 04h[2]
F1BAR0+I/O
Offset 06h[2]
User Defined Device 2 Trap
User Defined Device 3 Trap
General Purpose Timer 1
General Purpose Timer 2
82h[5]
82h[6]
83h[0]
83h[1]
C4h[31:0], CDh[7:0]
C8h[31:0], CEh[7:0]
F1BAR0+I/O
Offset 04h[3]
F1BAR0+I/O
Offset 06h[3]
F1BAR0+I/O
Offset 04h[4]
F1BAR0+I/O
Offset 06h[4]
88h[7:0], 89h[7:0], 8Bh[4] F1BAR0+I/O
Offset 04h[0]
F1BAR0+I/O
Offset 06h[0]
8Ah[7:0], 8Bh[5,3,2]
F1BAR0+I/O
Offset 04h[1]
F1BAR0+I/O
Offset 06h[1]
Suspend Modulation
Video Speedup
IRQ Speedup
96h[0]
80h[4]
80h[3]
94h[15:0], 96h[2:0]
8Dh[7:0], A8h[15:0]
8Ch[7:0]
N/A
N/A
N/A
N/A
N/A
N/A
1. This function is used for Suspend determination.
2. This function is used for SoftVGA.
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5.2.11 GPIO Interface
• Trap accesses for MIDI UART interface at I/O Port 300h-
301h or 330h-331h.
Up to 64 GPIOs in the in the Core Logic module are pro-
vided for system control. For further information, see Sec-
tion 3.2 "Multiplexing, Interrupt Selection, and Base
Address Registers" on page 86 and Table 5-30
"F0BAR0+I/O Offset: GPIO Configuration Registers" on
page 236.
• Trap accesses for serial input and output at COM2 (I/O
Port 2F8h-2FFh) or COM4 (I/O Port 2E8h-2EFh).
• Support trapping for low (I/O Port 00h-0Fh) and/or high
(I/O Port C0h-DFh) DMA accesses.
Note: Not all GPIOs are available on SC1200/SC1201
balls. GPIOs [63:42], [31:21], and [5:2] are
reserved.
• Support hardware status register reads in Core Logic
module, minimizing SMI overhead.
• Support is provided for software-generated IRQs on IRQ
2, 3, 5, 7, 10, 11, 12, 13, 14, and 15.
5.2.12 Integrated Audio
The Core Logic module provides hardware support for the
Virtual (soft) Audio subsystem as part of the Virtual System
Architecture (VSA) technology for capture and playback
of audio using an external codec. This eliminates much of
the hardware traditionally associated with audio functions.
The following subsections include details of the registers
used for configuring the audio interface. The registers are
accessed through F3 Index 10h, the Base Address Regis-
ter (F3BAR0) in Function 3. F3BAR0 sets the base
address for the audio support registers as shown in Table
5-37 "F3: PCI Header Registers for Audio Configuration"
on page 272.
This hardware support includes:
• Six-channel buffered PCI bus mastering interface.
5.2.12.1 Data Transport Hardware
The data transport hardware can be broadly divided into
two sections: bus mastering and the codec interface.
• AC97 version 2.0 compatible interface to the codec. Any
codec, which supports an independent input and output
sample rate conversion interface, can be used with the
Core Logic module.
Audio Bus Masters
The Core Logic module audio hardware includes six PCI
bus masters (three for input and three for output) for trans-
ferring digitized audio between memory and the external
codec. With these bus master engines, the Core Logic
module off-loads the CPU and improves system perfor-
mance.
Additional hardware provides the necessary functionality
for VSA. This hardware includes the ability to:
• Generate an SMI to alert software to update required
data. An SMI is generated when either audio buffer is
half empty or full. If the buffers become completely
empty or full, the Empty bit is asserted.
The programming interface defines a simple scatter/gather
mechanism allowing large transfer blocks to be scattered to
or gathered from memory. This cuts down on the number of
interrupts to and interactions with the CPU.
• Generate an SMI on I/O traps.
• Trap accesses for sound card compatibility at either I/O
Port 220h-22Fh, 240h-24Fh, 260h-26Fh, or 280h-28Fh.
The six bus masters that directly drive specific slots on the
AC97 interface are described in Table 5-10.
• Trap accesses for FM compatibility at I/O Port 388h-
38Bh.
Table 5-10. Bus Masters That Drive Specific Slots of the AC97 Interface
Audio Bus
Master #
Slots
Description
0
1
2
3
4
5
3 and 4
3 and 4
5
32-Bit output to codec. Left and right channels.
32-Bit input from codec. Left and right channels.
16-Bit output to codec.
5
16-Bit input from codec.
6 or 11
6 or 11
16-Bit output to codec. Slot in use is determined by F3BAR0+Memory Offset 08h[19].
16-Bit input from codec. Slot in use is determined by F3BAR0+Memory Offset 08h[20].
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Core Logic Module (Continued)
Physical Region Descriptor Table Address
looping mechanism. If a PRD table is created with the
JMP bit set in the last PRD, the PRD table does not
need a PRD with the EOT bit set. A PRD can not have
both the JMP and EOT bits set.
Before the bus master starts a master transfer it must be pro-
grammed with a pointer (PRD Table Address register) to a
Physical Region Descriptor Table. This pointer sets the start-
ing memory location of the Physical Region Descriptors
(PRDs). The PRDs describe the areas of memory that are
used in the data transfer. The descriptor table entries must be
aligned on a 32-byte boundary and the table cannot cross a
64 KB boundary in memory.
Programming Model
The following discussion explains, in steps, how to initiate
and maintain a bus master transfer between memory and
an audio slave device.
In the steps listed below, the reference to “Example” refers
to Figure 5-12 "PRD Table Example" on page 183.
Physical Region Descriptor Format
Each physical memory region to be transferred is
described by a Physical Region Descriptor (PRD) as illus-
trated in Table 5-11. When the bus master is enabled
(Command register bit 0 = 1), data transfer proceeds until
each PRD in the PRD table has been transferred. The bus
master does not cache PRDs.
1) Software creates a PRD table in system memory.
Each PRD entry is 8 bytes long; consisting of a base
address pointer and buffer size. The maximum data
that can be transferred from a PRD entry is 64 KB. A
PRD table must be aligned on a 32-byte boundary.
The last PRD in a PRD table must have the EOT or
JMP bit set.
The PRD table consists of two DWORDs. The first DWORD
contains a 32-bit pointer to a buffer to be transferred. The
second DWORD contains the size (16 bits) of the buffer
and flags (EOT, EOP, JMP). The description of the flags are
as follows:
Example - Assume the data is outbound. There are
three PRDs in the example PRD table. The first two
PRDs (PRD_1, PRD_2) have only the EOP bit set.
The last PRD (PRD_3) has only the JMP bit set. This
example creates a PRD loop.
• EOT bit - If set in a PRD, this bit indicates the last entry
in the PRD table (bit 31). The last entry in a PRD table
must have either the EOT bit or the JMP bit set. A PRD
can not have both the JMP and EOT bits set.
2) Software loads the starting address of the PRD table by
programming the PRD Table Address register.
• EOP bit - If set in a PRD and the bus master has
completed the PRD’s transfer, the End of Page bit is set
(Status register bit 0 = 1) and an SMI is generated. If a
second EOP is reached due to the completion of
Example - Program the PRD Table Address register
with Address_3.
3) Software must fill the buffers pointed to by the PRDs
with audio data. It is not absolutely necessary to fill the
buffers; however, the buffer filling process must stay
ahead of the buffer emptying. The simplest way to do
this is by using the EOP flags to generate an SMI
when a PRD is empty.
another PRD before the End of Page bit is cleared, the
Bus Master Error bit is set (Status register bit 1 = 1) and
the bus master pauses. In this paused condition, reading
the Status register clears both the Bus Master Error and
the End of Page bits and the bus master continues.
Example - Fill Audio Buffer_1 and Audio Buffer_2. The
SMI generated by the EOP from the first PRD allows
the software to refill Audio Buffer_1. The second SMI
refills Audio Buffer_2. The third SMI refills Audio
Buffer_1 and so on.
• JMP bit - This PRD is special. If set, the Memory Region
Physical Base Address is now the target address of the
JMP. The target address must be on a 32-byte boundary
so bits[4:0] must be written to 0. There is no data
transfer with this PRD. This PRD allows the creation of a
Table 5-11. Physical Region Descriptor Format
Byte 2 Byte 1
Byte 3
Byte 0
DWORD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
0
1
Memory Region Base Address [31:1] (Audio Data Buffer)
Reserved Size [15:1]
0
0
E E
J
O O M
T
P P
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4) Read the SMI Status register to clear the Bus Master
Error and End of Page bits (bits 1 and 0).
Table Address register is incremented by 08h and is
now pointing to PRD_3. The SMI Status register is
read to clear the End of Page status flag. Since Audio
Buffer_1 is now empty, the software can refill it.
Set the correct direction to the Read or Write Control
bit (Command register bit 3). Note that the direction of
the data transfer of a particular bus master is fixed and
therefore the direction bit must be programmed
accordingly. It is assumed that the codec has been
properly programmed to receive the audio data.
At the completion of PRD_2 an SMI is generated
because the EOP bit is set. The bus master then con-
tinues on to PRD_3. The address in the PRD Table
Address register is incremented by 08h. The DMA SMI
Status register is read to clear the End of Page status
flag. Since Audio Buffer_2 is now empty, the software
can refill it. Audio Buffer_1 has been refilled from the
previous SMI.
Engage the bus master by writing a “1” to the Bus
Master Control bit (Command register bit 0).
The bus master reads the PRD entry pointed to by the
PRD Table Address register and increments the
address by 08h to point to the next PRD. The transfer
begins.
PRD_3 has the JMP bit set. This means the bus mas-
ter uses the address stored in PRD_3 (Address_3) to
locate the next PRD. It does not use the address in the
PRD Table Address register to get the next PRD. Since
Address_3 is the location of PRD_1, the bus master
has looped the PRD table.
Example - The bus master is now properly pro-
grammed to transfer Audio Buffer_1 to a specific
slot(s) in the AC97 interface.
Stopping the bus master can be accomplished by not read-
ing the SMI Status register End of Page status flag. This
leads to a second EOP which causes a Bus Master Error
and pauses the bus master. In effect, once a bus master
has been enabled it never has to be disabled, just paused.
The bus master cannot be disabled unless the bus master
has been paused or has reached an EOT.
5) The bus master transfers data to/from memory
responding to bus master requests from the AC97
interface. At the completion of each PRD, the bus mas-
ter’s next response depends on the settings of the
flags in the PRD.
Example - At the completion of PRD_1 an SMI is gen-
erated because the EOP bit is set while the bus mas-
ter continues on to PRD_2. The address in the PRD
Address_3
32-byte
boundary
Address_1
Address_1
Address_2
Address_3
Audio
Buffer_1
Size_1
PRD_1
PRD_2
PRD_3
EOT = 0
EOP = 1
JMP = 0
Size_1
Size_2
EOT = 0
EOP = 1
JMP = 0
Address_2
Audio
Buffer_2
Size_2
EOT = 0
EOP = 0
JMP = 1
Don’t Care
Figure 5-12. PRD Table Example
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Core Logic Module (Continued)
5.2.12.2 AC97 Codec Interface
Codec Configuration/Control Registers
The AC97 codec (e.g., LM4548) is the master of the serial
interface and generates the clocks to Core Logic module.
Figure 5-13 shows the signal connections between two
codecs and the SC1200/SC1201:
The codec 32-bit related registers:
• GPIO Status and Control Registers
— Codec GPIO Status Register (F3BAR0+Memory
Offset 00h)
• Codec1 can be AC97 Rev. 1.3 or higher compliant.
— Codec GPIO Control Register (F3BAR0+Memory
Offset 04h)
• Codec2 is optional, but must be compliant with AC97 2.0
or higher. (For specifics on the serial interface, refer to
the appropriate codec manufacturer’s datasheet.)
— SDATA_IN2 has wakeup capability. (See Section 4.6
"System Wakeup Control (SWC)" on page 130.)
• Codec Status Register (F3BAR0+Memory Offset 08h)
• Codec Command Register (F3BAR0+Memory Offset
0Ch)
— If SDATA_IN2 is not used it must be connected to
Codec GPIO Status and Control Registers:
The Codec GPIO Status and Control registers are used for
codec GPIO related tasks such as enabling a codec GPIO
interrupt to cause an SMI.
VSS
.
— If an AMC97 codec is used (as Codec2), it should be
connected to SDATA_IN2 and SDATA_IN should be
connected to VSS
.
Codec Status Register:
• For PC speaker synthesis, the Core Logic module
outputs the PC speaker signal on the PC_BEEP pin
which is connected to the PC_BEEP input of the AC97
codec. Note that PC_BEEP is muxed with GPIO16 and
must be programmed via PMR[0] (see Table 3-2 on
page 86.)
The Codec Status register stores the codec status WORD.
It is updated every valid Status Word slot.
Codec Command Register:
The Codec Command register writes the control WORD to
the codec. By writing the appropriate control WORDs to
this port, the features of the codec can be controlled. The
contents of this register are written to the codec during the
Control Word slot.
The bit formats for these registers are given in Table 5-38
"F3BAR0+Memory Offset: Audio Configuration Registers"
on page 273.
BIT_CLK
BIT_CLK
XTAL_I
SYNC
SYNC
Codec1
PC_BEEP
PC_BEEP
SDATA_OUT
SDATA_IN
SDATA_OUT
SDATA_IN
BIT_CLK
XTAL_I
AC97_CLK
Codec2
(Optional)
SYNC
Geode™
SC1200/SC1201
PC_BEEP
SDATA_OUT
SDATA_IN2
SDATA_IN2
Figure 5-13. AC97 V2.0 Codec Signal Connections
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Core Logic Module (Continued)
5.2.12.3 VSA Technology Support Hardware
The Core Logic module incorporates the required hard-
ware in order to support the Virtual System Architecture
(VSA™) technology for capture and playback of audio
using an external codec. This eliminates much of the hard-
ware traditionally associated with industry standard audio
functions.
Audio SMI Status Reporting Registers:
The Top SMI Status Mirror and Status registers are the top
level of hierarchy for the SMI Handler in determining the
source of an SMI. These two registers are at
F1BAR0+Memory Offset 00h (Status Mirror) and 02h (Sta-
tus). The registers are identical except that reading the reg-
ister at F1BAR0+Memory Offset 02h clears the status.
The second level of audio SMI status reporting is set up
very much like the top level. There are two status reporting
registers, one “read only” (mirror) and one “read to clear”.
The data returned by reading either offset is the same (i.e.,
SMI was caused by an audio related event). The difference
between F3BAR0+Memory Offset 10h (Status Mirror) and
12h (Status) is in the ability to clear the SMI source at 12h.
VSA Technology
VSA technology provides a framework to enable software
implementation of traditionally hardware-only components.
VSA software executes in System Management Mode
(SMM), enabling it to execute transparently to the operating
system, drivers and applications.
The VSA design is based upon a simple model for replac-
ing hardware components with software. Hardware to be
virtualized is merely replaced with simple access detection
circuitry which asserts the SMI# (System Management
Interrupt) internal signal when hardware accesses are
detected. The current execution stream is immediately pre-
empted, and the processor enters SMM. The SMM system
software then saves the processor state, initializes the VSA
execution environment, decodes the SMI source and dis-
patches handler routines which have registered requests to
service the decoded SMI source. Once all handler routines
have completed, the processor state is restored and nor-
mal execution resumes. In this manner, hardware accesses
are transparently replaced with the execution of SMM han-
dler software.
Figure 5-14 on page 186 shows an SMI tree for checking
and clearing the source of an audio SMI. Only the audio
SMI bit is detailed here. For details regarding the remaining
bits in the Top SMI Status Mirror and Status registers refer
toTable 5-33 "F1BAR0+I/O Offset: SMI Status Registers"
on page 248.
I/O Trap SMI and Fast Write Status Register:
This 32-bit read-only register (F3BAR0+Memory Offset
14h) not only indicates if the enabled I/O trap generated an
SMI, but also contains Fast Path Write related bits.
I/O Trap SMI Enable Register:
The I/O Trap SMI Enable register (F3BAR0+Memory Offset
18h) allows traps for specified I/O addresses and config-
ures generation for I/O events. It also contains the enabling
bit for Fast Path Read/Write features.
Historically, SMM software was used primarily for the single
purpose of facilitating active power management for note-
book designs. That software’s only function was to manage
the power up and down of devices to save power. With high
performance processors now available, it is feasible to
implement, primarily in SMM software, PC capabilities tra-
ditionally provided by hardware. In contrast to power man-
agement code, this virtualization software generally has
strict performance requirements to prevent application per-
formance from being significantly impacted.
Status Fast Path Read/Write
Status Fast Path Read – If enabled, the Core Logic module
intercepts and responds to reads to several status regis-
ters. This speeds up operations, and prevents SMI genera-
tion for reads to these registers. This process is called
Status Fast Path Read. Status Fast Path Read is enabled
via F3BAR0+Memory Offset 18h[4].
In Status Fast Path Read the Core Logic module responds
to reads of the following addresses:
Audio SMI Related Registers
The SMI related registers consist of:
388h-38Bh, 2x0h, 2x1h, 2x2h, 2x3h, 2x8h and 2x9h
Note that if neither sound card or FM I/O mapping is
enabled, then status read trapping is not possible.
• Audio SMI Status Reporting Registers:
— Top Level SMI Mirror and Status Registers
(F1BAR0+Memory Offset 00h/02h)
Fast Path Write – If enabled, the Core Logic module cap-
tures certain writes to several I/O locations. This feature
prevents two SMIs from being asserted for write operations
that are known to take two accesses (the first access is an
index and the second is data). This process is called Fast
Path Write. Fast Path Write is enabled in via
F3BAR0+Memory Offset 18h[11].
— Second Level SMI Status Registers
(F3BAR0+Memory Offset 10h/12h)
• I/O Trap SMI and Fast Write Status Register
(F3BAR0+Memory Offset 14h)
• I/O Trap SMI Enable Register (F3BAR0+Memory Offset
18h)
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Core Logic Module (Continued)
Fast Path Write captures the data and address bit 1 (A1) of
the first access, but does not generate an SMI. A1 is stored
in F3BAR0+Memory Offset 14h[15]. The second access
causes an SMI, and the data and address are captured as
in a normal trapped I/O.
In Fast Path Write, the Core Logic module responds to
writes to the following addresses:
388h, 38Ah, 38Bh, 2x0h, 2x2h, and 2x8h
Table 5-38 on page 273 shows the bit formats of the sec-
ond level SMI status reporting registers and the Fast Path
Read/Write programming bits.
SMI# Asserted
SMM software reads SMI Header
If Bit X = 1
If Bit X = 0
(Internal SMI)
(External SMI)
Call internal SMI handler
GX1
to take appropriate action
Module
Core Logic Module
F1BAR0+Memory
Offset 02h
Read to Clear
to determine
top-level source
of SMI
SMI de-asserted after all SMI Sources are Cleared
(i.e., Top, Second, and Third Levels)
F3BAR0+Memory
Offset 10h
Read to Clear
to determine
second-level
source of SMI
Bits [15:8]
RSVD
Bit 7
ABM5_SMI
Bits [15:2]
Other_SMI
F3BAR0+Memory
Offset 14h
Read to Clear
to determine
third-level
Bit 6
ABM4_SMI
Bit 5
ABM3_SMI
source of SMI
Take
Appropriate
Action
Bit 4
Bits [31:14]
Other_RO
ABM2_SMI
If bit 1 = 1,
Source of
SMI is
Bit 3
ABM1_SMI
Bit 13
SMI_SC/FM_TRAP
Audio Event
Bit 1
AUDIO_SMI
Bit 2
Bit 12
ABM0_SMI
Take
Appropriate
Action
SMI_DMA_TRAP
If bit 0 = 1,
Source of
SMI is
Bit 0
Other_SMI
Bit 1
SER_INTR_SMI
Bit 11
SMI_MPU_TRAP
I/O Trap
Top Level
Bit 0
I/O_TRAP_SMI
Bit 10
SMI_SC/FM_TRAP
Second Level
Bits [9:0]
Other_RO
Third Level
Figure 5-14. Audio SMI Tree Example
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Core Logic Module (Continued)
5.2.12.4 IRQ Configuration Registers
• Enable support of a variable number of wait states.
• Enable I/O memory cycle retries in SMM handler.
The Core Logic module provides the ability to set and clear
IRQs internally through software control. If the IRQs are
configured for software control, they do not respond to
external hardware. There are two registers provided for this
feature:
• Enable support of wakeup and other power state transi-
tions.
Assumptions and functionality requirements of the LPC
interface are:
• Internal IRQ Enable Register (F3BAR0+Memory Offset
1Ah)
• Only the following class of devices may be connected to
the LPC interface:
• Internal IRQ Control Register (F3BAR0+Memory Offset
1Ch)
— SuperI/O (FDC, SP, PP, IR, KBC) - I/O slave, DMA,
bus master (for IR, PP).
Internal IRQ Enable Register
— Audio, including AC97 style design - I/O slave, DMA,
bus master.
— Generic Memory, including BIOS - Memory slave.
— System Management Controller - I/O slave, bus
master.
The Internal IRQ Enable register configures the IRQs as
internal (software) interrupts or external (hardware) inter-
rupts. Any IRQ used as an internal software driven source
must be configured as internal.
• Interrupts are communicated with the serial interrupt
Internal IRQ Control Register
(SERIRQ) protocol.
The Internal IRQ Control register allows individual software
assertion/de-assertion of the IRQs that are enabled as
internal. These bits are used as masks when attempting to
write a particular IRQ bit. If the mask bit is set, it can then
be asserted/de-asserted according to the value in the low-
order 16 bits. Otherwise the assertion/de-assertion values
of the particular IRQ can not be changed.
• The LPC interface does not need to support high-speed
buses (such as CardBus, 1394, etc.) downstream, nor
does it need to support low-latency buses such as USB.
Figure 5-15 shows a typical setup. In this setup, the LPC is
connected through the Core Logic module to a PCI or host
bus.
5.2.12.5 LPC Interface
The LPC interface of the Core Logic module is based on
the Intel Low Pin Count (LPC) Interface specification, revi-
sion 1.0. In addition to the requirement pins that are speci-
fied in the Intel LPC Interface specification, the Core Logic
module also supports three optional pins: LDRQ#, SER-
IRQ, and LPCPD#.
ISA (Optional)
PCI/Host Bus
Core Logic
Module
The following subsections briefly describe some sections of
the specification. However, for full details refer to the LPC
specification directly.
The goals of the LPC interface are to:
• Enable a system without an ISA bus.
• Reduce the cost of traditional ISA bus devices.
• Use on a motherboard only.
LPC
SuperI/O Module
• Perform the same cycle types as the ISA bus: memory,
I/O, DMA, and Bus Master.
KBC
SP
• Increase the memory space from 16 MB to 4 GB to allow
BIOS sizes much greater.
PP
FDC
• Provide synchronous design. Much of the challenge of
an ISA design is meeting the different, and in some
cases conflicting, ISA timings. Make the timings
synchronous to a reference well known to component
designers, such as PCI.
Figure 5-15. Typical Setup
• Support software transparency: do not require special
drivers or configuration for this interface. The mother-
board BIOS should be able to configure all devices at
boot.
• Support desktop and mobile implementations.
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Core Logic Module (Continued)
5.2.12.6 LPC Interface Signal Definitions
5.2.12.7 Cycle Types
The LPC specification lists seven required and six optional
signals for supporting the LPC interface. Many of the sig-
nals are the same signals found on the PCI interface and
do not require any new pins on the host. Required signals
must be implemented by both hosts and peripherals.
Optional signals may or may not be present on particular
hosts or peripherals.
Table 5-12 shows the various types of cycles that are sup-
ported by the Core Logic module.
Table 5-12. Cycle Types
Supported Sizes
Cycle Type
(Bytes)
The Core Logic module incorporates all the required LPC
interface signals and two of the optional signals:
Memory Read
Memory Write
I/O Read
1
1
• Required LPC signals:
1
— LAD[3:0] - Multiplexed Command, Address and Data.
— LFRAME# - Frame: Indicates start of a new cycle,
termination of broken cycle.
— LRESET# - Reset: This signal is not available. Use
PCI Reset signal PCIRST# instead.
I/O Write
1
DMA Read
1 or 2
1 or 2
1, 2, or 4
1, 2, or 4
DMA Write
— LCLK - Clock: This signal is not available. Use PCI 33
MHz clock signal PCICLK instead.
Bus Master Memory Read
Bus Master Memory Write
• Core Logic module optional LPC signals:
— LDRQ# - Encoded DMA/Bus Master Request: Only
needed by peripheral that need DMA or bus
mastering. Peripherals may not share the LDRQ#
signal.
5.2.12.8 LPC Interface Support
The LPC interface supports all the features described in
the LPC Bus Interface specification, revision 1.0, with the
following exceptions:
— SERIRQ - Serialized IRQ: Only needed by periph-
erals that need interrupt support.
— LPCPD# - Power Down: Indicates that the peripheral
should prepare for power to the LPC interface to be
shut down. Optional for the host.
• Only 8- or 16-bit DMA, depending on channel number.
Does not support the optional larger transfer sizes.
• Only one external DRQ pin.
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Core Logic Module (Continued)
5.3 REGISTER DESCRIPTIONS
The Core Logic module is a multi-function module. Its reg-
ister space can be broadly divided into three categories in
which specific types of registers are located:
5.3.1 PCI Configuration Space and Access Methods
Configuration cycles are generated in the processor. All
configuration registers in the Core Logic module are
accessed through the PCI interface using the PCI Type
One Configuration Mechanism. This mechanism uses two
DWORD I/O locations at 0CF8h and 0CFCh. The first loca-
tion (0CF8h) references the Configuration Address register.
The second location (0CFCh) references the Configuration
Data Register (CDR).
1) Chipset Register Space (F0-F5) (Note that F4 is for
Video Processor support, see Section 6.3.1 on page
341 for register descriptions): Comprised of six sepa-
rate functions, each with its own register space, con-
sisting of PCI header registers and configuration
registers.
To access PCI configuration space, write the Configuration
Address (0CF8h) Register with data that specifies the Core
Logic module as the device on PCI being accessed, along
with the configuration register offset. On the following
cycle, a read or write to the Configuration Data Register
(CDR) causes a PCI configuration cycle to the Core Logic
module. Byte, WORD, or DWORD accesses are allowed to
CDR at 0CFCh, 0CFDh, 0CFEh, or 0CFFh.
The PCI header is a 256-byte region used for configur-
ing a PCI device or function. The first 64 bytes are the
same for all PCI devices and are predefined by the
PCI specification. These registers are used to config-
ure the PCI for the device. The rest of the 256-byte
region is used to configure the device or function itself.
2) USB Controller Register Space (PCIUSB): Consists of
the standard PCI header registers. The USB controller
supports three ports and is OpenHCI compliant.
The Core Logic module has seven PCI configuration regis-
ter sets, one for each function (F0-F5) and USB (PCIUSB).
Base Address Registers (BARx) in F0-F5 and PCIUSB set
the base addresses for additional I/O or memory mapped
configuration registers for each function.
3) ISA Legacy Register Space (I/O Ports): Contains all
the legacy compatibility I/O ports that are internal,
trapped, shadowed, or snooped.
The following subsections provide:
Table 5-13 shows the PCI Configuration Address Register
(0CF8h) and how to access the PCI header registers.
• A brief discussion on how to access the registers
located in PCI Configuration Space.
• Core Logic module register summaries.
• Bit formats for Core Logic module registers.
Table 5-13. PCI Configuration Address Register (0CF8h)
31
30
24 23
16 15
11 10
8
7
2
1
0
Configuration
Space Mapping
DWORD
00
Reserved
Bus Number
0000 0000
Device Number
xxxx x (Note)
Function
Index
1 (Enable)
000 000
xxx
xxxx xx
00 (Always)
Function 0 (F0): Bridge Configuration, GPIO and LPC Configuration Register Space
80h 0000 0000 1001 0 or 1000 0
Function 1 (F1): SMI Status and ACPI Timer Configuration Register Space
80h 0000 0000 1001 0 or 1000 0
Function 2 (F2): IDE Controller Configuration Register Space
000
001
010
011
100
101
000
Index
Index
Index
Index
Index
Index
Index
80h
Function 3 (F3): Audio Configuration Register Space
80h 0000 0000
0000 0000
1001 0 or 1000 0
1001 0 or 1000 0
Function 4 (F4): Video Processor Configuration Register Space
80h 0000 0000 1001 0 or 1000 0
Function 5 (F5): X-Bus Expansion Configuration Register Space
80h
PCIUSB: USB Controller Configuration Register Space
80h 0000 0000
0000 0000
1001 0 or 1000 0
1001 1 or 1000 1
Note: The device number depends upon the IDSEL Strap Override bit (F5BAR0+I/O Offset 04h[0]). This bit allows selection of the
address lines to be used as the IDSEL. By Default: IDSEL = AD28 (1001 0) for F0-F5, AD29 (1001 1) for PCIUSB.
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Core Logic Module (Continued)
5.3.2 Register Summary
The tables in this subsection summarize the registers of
the Core Logic module. Included in the tables are the regis-
ter’s reset values and page references where the bit for-
mats are found.
Note: Function 4 (F4) is for Video Processor support
(although accessed through the Core Logic PCI
configuration registers). Refer to Section 6.3 "Reg-
ister Descriptions" on page 341 for details.
Table 5-14. F0: PCI Header and Bridge Configuration Registers
for GPIO and LPC Support Summary
Width
(Bits)
Reset
Value
Reference
(Table 5-29)
F0 Index
Type
Name
00h-01h
02h-03h
04h-05h
06h-07h
08h
16
16
16
16
8
RO
RO
Vendor Identification Register
Device Identification Register
PCI Command Register
PCI Status Register
100Bh
0500h
000Fh
0280h
00h
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R/W
R/W
RO
Device Revision ID Register
PCI Class Code Register
PCI Cache Line Size Register
PCI Latency Timer Register
PCI Header Type Register
PCI BIST Register
09h-0Bh
0Ch
24
8
RO
060100h
00h
R/W
R/W
RO
0Dh
8
00h
0Eh
8
80h
0Fh
8
RO
00h
10h-13h
32
R/W
Base Address Register 0 (F0BAR0) — Sets the base address for
the I/O mapped GPIO Runtime and Configuration Registers (sum-
marized in Table 5-15).
00000001h
14h-17h
32
R/W
Base Address Register 1 (F0BAR1) — Sets the base address for
the I/O mapped LPC Configuration Registers (summarized in
Table 5-16)
00000001h
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18h-2Bh
2Ch-2Dh
2Eh-2Fh
30h-3Fh
40h
---
16
16
---
8
---
Reserved
00h
100Bh
0500h
00h
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RO
Subsystem Vendor ID
Subsystem ID
RO
---
Reserved
R/W
R/W
---
PCI Function Control Register 1
PCI Function Control Register 2
Reserved
39h
41h
8
00h
42h
---
8
00h
43h
R/W
R/W
---
PIT Delayed Transactions Register
Reset Control Register
Reserved
02h
44h
8
01h
45h
---
8
00h
46h
R/W
R/W
---
PCI Functions Enable Register
Miscellaneous Enable Register
Reserved
FEh
47h
8
00h
48h-4Bh
4Ch-4Fh
50h
---
32
8
00h
R/W
R/W
R/W
R/W
R/W
---
Top of System Memory
PIT Control/ISA CLK Divider
ISA I/O Recovery Control Register
ROM/AT Logic Control Register
Alternate CPU Support Register
Reserved
FFFFFFFFh
7Bh
51h
8
40h
52h
8
98h
53h
8
00h
54h-59h
5Ah
---
8
00h
R/W
R/W
R/W
R/W
---
Decode Control Register 1
Decode Control Register 2
PCI Interrupt Steering Register 1
PCI Interrupt Steering Register 2
Reserved
01h
5Bh
8
20h
5Ch
8
00h
5Dh
8
00h
5Eh-5Fh
60h-63h
64h-6Dh
6Eh-6Fh
---
32
---
16
00h
R/W
---
ACPI Control Register
Reserved
00000000h
00h
R/W
ROM Mask Register
FFF0h
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Core Logic Module (Continued)
Table 5-14. F0: PCI Header and Bridge Configuration Registers
for GPIO and LPC Support Summary (Continued)
Width
(Bits)
Reset
Value
Reference
(Table 5-29)
F0 Index
Type
Name
70h-71h
72h
16
8
R/W
R/W
---
IOCS1# Base Address Register
IOCS1# Control Register
0000h
00h
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73h
8
Reserved
00h
74h-75h
76h
16
8
R/W
R/W
---
IOCS0 Base Address Register
0000h
00h
IOCS0 Control Register
77h
---
32
32
8
Reserved
00h
78h-7Bh
7Ch-7Fh
80h
R/W
R/W
R/W
R/W
R/W
R/W
RO
DOCCS Base Address Register
DOCCS Control Register
00000000h
00000000h
00h
Power Management Enable Register 1
Power Management Enable Register 2
Power Management Enable Register 3
Power Management Enable Register 4
Second Level PME/SMI Status Mirror Register 1
Second Level PME/SMI Status Mirror Register 2
Second Level PME/SMI Status Mirror Register 3
Second Level PME/SMI Status Mirror Register 4
General Purpose Timer 1 Count Register
General Purpose Timer 1 Control Register
General Purpose Timer 2 Count Register
General Purpose Timer 2 Control Register
IRQ Speedup Timer Count Register
Video Speedup Timer Count Register
VGA Timer Count Register
81h
8
00h
82h
8
00h
83h
8
00h
84h
8
00h
85h
8
RO
00h
86h
8
RO
00h
87h
8
RO
00h
88h
8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
---
00h
89h
8
00h
8Ah
8
00h
8Bh
8
00h
8Ch
8
00h
8Dh
8
00h
8Eh
8
00h
8Fh-92h
93h
---
8
Reserved
00h
R/W
R/W
R/W
---
Miscellaneous Device Control Register
Suspend Modulation Register
00h
94h-95h
96h
16
8
0000h
00h
Suspend Configuration Register
Reserved
97h
---
16
16
16
16
16
16
16
16
16
---
16
8
00h
98h-99h
9Ah-9Bh
9Ch-9Dh
9Eh-9Fh
A0h-A1h
A2h-A3h
A4h-A5h
A6h-A7h
A8h-A9h
AAh-ABh
ACh-ADh
AEh
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
---
Hard Disk Idle Timer Count Register — Primary Channel
Floppy Disk Idle Timer Count Register
Parallel / Serial Idle Timer Count Register
Keyboard / Mouse Idle Timer Count Register
User Defined Device 1 Idle Timer Count Register
User Defined Device 2 Idle Timer Count Register
User Defined Device 3 Idle Timer Count Register
Video Idle Timer Count Register
Video Overflow Count Register
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
00h
Reserved
R/W
WO
WO
---
Hard Disk Idle Timer Count Register — Secondary Channel
CPU Suspend Command Register
Suspend Notebook Command Register
Reserved
0000h
00h
AFh
8
00h
B0h-B3h
B4h
---
8
00h
RO
Floppy Port 3F2h Shadow Register
Floppy Port 3F7h Shadow Register
Floppy Port 1F2h Shadow Register
Floppy Port 1F7h Shadow Register
DMA Shadow Register
xxh
B5h
8
RO
xxh
B6h
8
RO
xxh
B7h
8
RO
xxh
B8h
8
RO
xxh
B9h
8
RO
PIC Shadow Register
xxh
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Core Logic Module (Continued)
Table 5-14. F0: PCI Header and Bridge Configuration Registers
for GPIO and LPC Support Summary (Continued)
Width
(Bits)
Reset
Value
Reference
(Table 5-29)
F0 Index
Type
Name
BAh
8
8
RO
RO
R/W
---
PIT Shadow Register
xxh
xxh
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BBh
RTC Index Shadow Register
Clock Stop Control Register
Reserved
BCh
8
00h
BDh-BFh
C0h-C3h
C4h-C7h
C8h-CBh
CCh
---
32
32
32
8
00h
R/W
R/W
R/W
R/W
R/W
R/W
---
User Defined Device 1 Base Address Register
User Defined Device 2 Base Address Register
User Defined Device 3 Base Address Register
User Defined Device 1 Control Register
User Defined Device 2 Control Register
User Defined Device 3 Control Register
Reserved
00000000h
00000000h
00000000h
00h
CDh
8
00h
CEh
8
00h
CFh
---
8
00h
D0h
WO
---
Software SMI Register
00h
D1h-EBh
ECh
16
8
Reserved
00h
R/W
---
Timer Test Register
00h
EDh-F3h
F4h
---
8
Reserved
00h
RC
RC
RC
RC
---
Second Level PME/SMI Status Register 1
Second Level PME/SMI Status Register 2
Second Level PME/SMI Status Register 3
Second Level PME/SMI Status Register 4
Reserved
00h
F5h
8
00h
F6h
8
00h
F7h
8
00h
F8h-FFh
---
00h
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192
Revision 6.0
Core Logic Module (Continued)
Table 5-15. F0BAR0: GPIO Support Registers Summary
F0BAR0+
I/O Offset
Width
(Bits)
Reset
Value
Reference
(Table 5-30)
Type
Name
00h-03h
04h-07h
08h-0Bh
0Ch-0Fh
10h-13h
14h-17h
18h-1Bh
1Ch-1Fh
20h-23h
24h-27h
28h-2Bh
32
32
32
32
32
32
32
32
32
32
32
R/W
RO
GPDO0 — GPIO Data Out 0 Register
GPDI0 — GPIO Data In 0 Register
GPIEN0 — GPIO Interrupt Enable 0 Register
GPST0 — GPIO Status 0 Register
FFFFFFFFh
FFFFFFFFh
00000000h
00000000h
FFFFFFFFh
FFFFFFFFh
00000000h
00000000h
00000000h
00000044h
00000000h
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R/W
R/W1C
R/W
GPDO1 — GPIO Data Out 1 Register
GPDI1 — GPIO Data In 1 Register
GPIEN1 — GPIO Interrupt Enable 1 Register
GPST1 — GPIO Status 1 Register
RO
R/W
R/W1C
R/W
GPIO Signal Configuration Select Register
GPIO Signal Configuration Access Register
GPIO Reset Control Register
R/W
R/W
Table 5-16. F0BAR1: LPC Support Registers Summary
F0BAR1+
I/O Offset
Width
(Bits)
Reset
Value
Reference
(Table 5-31)
Type
Name
00h-03h
04h-07h
08h-0Bh
0Ch-0Fh
10h-13h
14h-17h
18h-1Bh
1Ch-1Fh
20h-23h
32
32
32
32
32
32
32
32
32
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
SERIRQ_SRC — Serial IRQ Source Register
SERIRQ_LVL — Serial IRQ Level Control Register
SERIRQ_CNT — Serial IRQ Control Register
DRQ_SRC — DRQ Source Register
00000000h
00000000h
00000000h
00000000h
00000000h
00080020h
00000000h
00000080h
00000000h
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LAD_EN — LPC Address Enable Register
LAD_D0 — LPC Address Decode 0 Register
LAD_D1 — LPC Address Decode 1 Register
LPC_ERR_SMI — LPC Error SMI Register
LPC_ERR_ADD — LPC Error Address Register
Revision 6.0
193
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Core Logic Module (Continued)
Table 5-17. F1: PCI Header Registers for SMI Status and ACPI Support Summary
Width
(Bits)
Reset
Value
Reference
(Table 5-32)
F1 Index
Type
Name
00h-01h
02h-03h
04h-05h
06h-07h
08h
16
16
16
16
8
RO
RO
R/W
RO
RO
RO
RO
RO
RO
RO
R/W
Vendor Identification Register
Device Identification Register
PCI Command Register
PCI Status Register
100Bh
0501h
0000h
0280h
00h
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Device Revision ID Register
PCI Class Code Register
PCI Cache Line Size Register
PCI Latency Timer Register
PCI Header Type Register
PCI BIST Register
09h-0Bh
0Ch
24
8
068000h
00h
0Dh
8
00h
0Eh
8
00h
0Fh
8
00h
10h-13h
32
Base Address Register 0 (F1BAR0) — Sets the base address for
the I/O mapped SMI Status Registers (summarized in Table 5-18).
00000001h
14h-2Bh
2Ch-2Dh
2Eh-2Fh
30h-3Fh
40h-43h
---
16
16
---
32
---
RO
RO
---
Reserved
00h
100Bh
0501h
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Subsystem Vendor ID
Subsystem ID
Reserved
00h
R/W
Base Address Register 1 (F1BAR1) — Sets the base address for
00000001h
the I/O mapped ACPI Support Registers (summarized in Table 5-
19)
44h-FFh
---
---
Reserved
00h
Page 247
Table 5-18. F1BAR0: SMI Status Registers Summary
F1BAR0+
I/O Offset
Width
(Bits)
Reset
Value
Reference
(Table 5-33)
Type
Name
00h-01h
02h-03h
04h-05h
16
16
16
RO
RO/RC
RO
Top Level PME/SMI Status Mirror Register
Top Level PME/SMI Status Register
0000h
0000h
0000h
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Second Level General Traps & Timers PME/SMI Status Mirror
Register
06h-07h
08h-09h
16
16
RC
Second Level General Traps & Timers PME/SMI Status Register
SMI Speedup Disable Register
0000h
0000h
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Read to
Enable
0Ah-1Bh
1Ch-1Fh
20h-21h
22h-23h
24h-27h
28h-4Fh
50h-FFh
---
32
16
16
32
---
---
---
RO
RO
RC
R/W
---
Reserved
00h
xxxxxxxxh
0000h
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ACPI Timer Register
Second Level ACPI PME/SMI Status Mirror Register
Second Level ACPI PME/SMI Status Register
External SMI Register
0000h
00000000h
00h
Not Used
---
The I/O mapped registers located here (F1BAR0+I/O Offset 50h-FFh) are also accessible at F0
Index 50h-FFh. The preferred method is to program these registers through the F0 register space.
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Revision 6.0
Core Logic Module (Continued)
Table 5-19. F1BAR1: ACPI Support Registers Summary
F1BAR1+
I/O Offset
Width
(Bits)
Reset
Value
Reference
(Table 5-34)
Type
Name
00h-03h
04h
32
8
R/W
RO
P_CNT — Processor Control Register
Reserved, do not read
00000000h
00h
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05h
8
RO
P_LVL3 — Enter C3 Power State Register
SMI_CMD — OS/BIOS Requests Register
ACPI_FUN_CNT — ACPI Function Control Register
PM1A_STS — PM1A Status Register
PM1A_EN — PM1A Enable Register
PM1A_CNT — PM1A Control Register
ACPI_BIOS_STS Register
xxh
06h
8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
---
00h
07h
8
00h
08h-09h
0Ah-0Bh
0Ch-0Dh
0Eh
16
16
16
8
0000h
0000h
0000h
00h
0Fh
8
ACPI_BIOS_EN Register
00h
10h-11h
12h-13h
14h
16
16
8
GPE0_STS — General Purpose Event 0 Status Register
GPE0_EN — General Purpose Event 0 Enable Register
GPWIO Control Register 1
xxxxh
0000h
00h
15h
8
GPWIO Control Register 2
00h
16h
8
GPWIO Data Register
00h
17h
---
32
32
8
Reserved
00h
18h-1Bh
1Ch-1Fh
20h
R/W
RO
ACPI SCI_ROUTING Register
00000F00h
xxxxxxxxh
00h
PM_TMR — ACPI Timer Register
PM2_CNT — PM2 Control Register
Not Used
R/W
---
21h-FFh
---
00h
Revision 6.0
195
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Core Logic Module (Continued)
Table 5-20. F2: PCI Header Registers for IDE Controller Support Summary
Width
(Bits)
Reset
Value
Reference
(Table 5-35)
F2 Index
Type
Name
00h-01h
02h-03h
04h-05h
06h-07h
08h
16
16
16
16
8
RO
RO
R/W
RO
RO
RO
RO
RO
RO
RO
RO
Vendor Identification Register
Device Identification Register
PCI Command Register
PCI Status Register
100Bh
0502h
0000h
0280h
01h
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Device Revision ID Register
PCI Class Code Register
PCI Cache Line Size Register
PCI Latency Timer Register
PCI Header Type Register
PCI BIST Register
09h-0Bh
0Ch
24
8
010180h
00h
0Dh
8
00h
0Eh
8
00h
0Fh
8
00h
10h-13h
32
Base Address Register 0 (F2BAR0) — Reserved for possible
future use by the Core Logic module.
00000000h
14h-17h
18h-1Bh
1Ch-1Fh
20h-23h
32
32
32
32
RO
RO
Base Address Register 1 (F2BAR1) — Reserved for possible
future use by the Core Logic module.
00000000h
00000000h
00000000h
00000001h
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Base Address Register 2 (F2BAR2) — Reserved for possible
future use by the Core Logic module.
RO
Base Address Register 3 (F2BAR3) — Reserved for possible
future use by the Core Logic module.
R/W
Base Address Register 4 (F2BAR4) — Sets the base address for
the I/O mapped Bus Master IDE Registers (summarized in Table
5-21)
24h-2Bh
2Ch-2Dh
2Eh-2Fh
30h-3Fh
40h-43h
44h-47h
48h-4Bh
4Ch-4Fh
50h-53h
54h-57h
58h-5Bh
5Ch-5Fh
60h-FFh
---
16
16
---
32
32
32
32
32
32
32
32
---
---
Reserved
00h
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RO
Subsystem Vendor ID
100Bh
RO
Subsystem ID
0502h
---
Reserved
00h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
---
Channel 0 Drive 0 PIO Register
Channel 0 Drive 0 DMA Control Register
Channel 0 Drive 1 PIO Register
Channel 0 Drive 1 DMA Control Register
Channel 1 Drive 0 PIO Register
Channel 1 Drive 0 DMA Control Register
Channel 1 Drive 1 PIO Register
Channel 1 Drive 1 DMA Control Register
Reserved
00009172h
00077771h
00009172h
00077771h
00009172h
00077771h
00009172h
00077771h
00h
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Revision 6.0
Core Logic Module (Continued)
Table 5-21. F2BAR4: IDE Controller Support Registers Summary
F2BAR4+
I/O Offset
Width
(Bits)
Reset
Value
Reference
(Table 5-36)
Type
Name
00h
8
---
8
R/W
---
IDE Bus Master 0 Command Register — Primary
Not Used
00h
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01h
---
02h
R/W
---
IDE Bus Master 0 Status Register — Primary
Not Used
00h
03h
---
32
8
---
00000000h
00h
04h-07h
08h
R/W
R/W
---
IDE Bus Master 0 PRD Table Address — Primary
IDE Bus Master 1 Command Register — Secondary
Not Used
09h
---
8
---
0Ah
R/W
---
IDE Bus Master 1 Status Register — Secondary
Not Used
00h
0Bh
---
32
---
0Ch-0Fh
R/W
IDE Bus Master 1 PRD Table Address — Secondary
00000000h
Table 5-22. F3: PCI Header Registers for Audio Support Summary
Width
(Bits)
Reset
Value
Reference
(Table 5-37)
F3 Index
Type
Name
00h-01h
02h-03h
04h-05h
06h-07h
08h
16
16
16
16
8
RO
RO
R/W
RO
RO
RO
RO
RO
RO
RO
R/W
Vendor Identification Register
Device Identification Register
PCI Command Register
PCI Status Register
100Bh
0503h
0000h
0280h
00h
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Device Revision ID Register
PCI Class Code Register
PCI Cache Line Size Register
PCI Latency Timer Register
PCI Header Type Register
PCI BIST Register
09h-0Bh
0Ch
24
8
040100h
00h
0Dh
8
00h
0Eh
8
00h
0Fh
8
00h
10h-13h
32
Base Address Register 0 (F3BAR0) — Sets the base address for
the memory mapped VSA audio interface control register block
(summarized in Table 5-23).
00000000h
14h-2Bh
2Ch-2Dh
2Eh-2Fh
30h-FFh
---
16
16
---
---
RO
RO
---
Reserved
00h
100Bh
0503h
00h
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Subsystem Vendor ID
Subsystem ID
Reserved
Revision 6.0
197
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Core Logic Module (Continued)
Table 5-23. F3BAR0: Audio Support Registers Summary
F3BAR0+
Memory
Offset
Width
(Bits)
Reset
Value
Reference
(Table 5-38)
Type
Name
00h-03h
04h-07h
08h-0Bh
0Ch-0Fh
10h-11h
12h-13h
14h-17h
18h-19h
1Ah-1Bh
1Ch-1Fh
20h
32
32
32
32
16
16
32
16
16
32
8
R/W
R/W
R/W
R/W
RC
Codec GPIO Status Register
00000000h
00000000h
00000000h
00000000h
0000h
0000h
00000000h
0000h
0000h
00000000h
00h
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Codec GPIO Control Register
Codec Status Register
Codec Command Register
Second Level Audio SMI Status Register
Second Level Audio SMI Status Mirror Register
I/O Trap SMI and Fast Write Status Register
I/O Trap SMI Enable Register
RO
RO
R/W
R/W
R/W
R/W
RC
Internal IRQ Enable Register
Internal IRQ Control Register
Audio Bus Master 0 Command Register
Audio Bus Master 0 SMI Status Register
Not Used
21h
8
00h
22h-23h
24h-27h
28h
---
32
8
---
---
R/W
R/W
RC
Audio Bus Master 0 PRD Table Address
Audio Bus Master 1 Command Register
Audio Bus Master 1 SMI Status Register
Not Used
00000000h
00h
29h
8
00h
2Ah-2Bh
2Ch-2Fh
30h
---
32
8
---
---
R/W
R/W
RC
Audio Bus Master 1 PRD Table Address
Audio Bus Master 2 Command Register
Audio Bus Master 2 SMI Status Register
Not Used
00000000h
00h
31h
8
00h
32h-33h
34h-37h
38h
---
32
8
---
00h
R/W
R/W
RC
Audio Bus Master 2 PRD Table Address
Audio Bus Master 3 Command Register
Audio Bus Master 3 SMI Status Register
Not Used
00000000h
00h
39h
8
00h
3Ah-3Bh
3Ch-3Fh
40h
---
32
8
---
---
R/W
R/W
RC
Audio Bus Master 3 PRD Table Address
Audio Bus Master 4 Command Register
Audio Bus Master 4 SMI Status Register
Not Used
00000000h
00h
41h
8
00h
42h-43h
44h-47h
48h
---
32
8
---
---
R/W
R/W
RC
Audio Bus Master 4 PRD Table Address
Audio Bus Master 5 Command Register
Audio Bus Master 5 SMI Status Register
Not Used
00000000h
00h
49h
8
00h
4Ah-4Bh
4Ch-4Fh
---
32
---
---
R/W
Audio Bus Master 5 PRD Table Address
00000000h
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198
Revision 6.0
Core Logic Module (Continued)
Table 5-24. F5: PCI Header Registers for X-Bus Expansion Support Summary
Width
(Bits)
Reset
Value
Reference
(Table 5-39)
F5 Index
Type
Name
00h-01h
02h-03h
04h-05h
06h-07h
08h
16
16
16
16
8
RO
RO
R/W
RO
RO
RO
RO
RO
RO
RO
R/W
Vendor Identification Register
Device Identification Register
PCI Command Register
PCI Status Register
100Bh
0505h
0000h
0280h
00h
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Device Revision ID Register
PCI Class Code Register
PCI Cache Line Size Register
PCI Latency Timer Register
PCI Header Type Register
PCI BIST Register
09h-0Bh
0Ch
24
8
068000h
00h
0Dh
8
00h
0Eh
8
00h
0Fh
8
00h
10h-13h
32
Base Address Register 0 (F5BAR0) — Sets the base address for
the X-Bus Expansion support registers (summarized in
Table 5-25.)
00000000h
14h-17h
18h-1Bh
1Ch-1Fh
20h-23h
24h-27h
32
32
32
32
32
R/W
R/W
R/W
R/W
R/W
Base Address Register 1 (F5BAR1) — Reserved for possible
future use by the Core Logic module.
00000000h
00000000h
00000000h
00000000h
00000000h
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Base Address Register 2 (F5BAR2) — Reserved for possible
future use by the Core Logic module.
Base Address Register 3 (F5BAR3) — Reserved for possible
future use by the Core Logic module.
Base Address Register 4 (F5BAR4) — Reserved for possible
future use by the Core Logic module.
Base Address Register 5 (F5BAR5) — Reserved for possible
future use by the Core Logic module.
28h-2Bh
2Ch-2Dh
2Eh-2Fh
30h-3Fh
40h-43h
44h-47h
48h-4Bh
4Ch-4Fh
50h-53h
54h-57h
58h
---
16
16
---
32
32
32
32
32
32
8
---
Reserved
00h
100Bh
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RO
Subsystem Vendor ID
RO
Subsystem ID
0505h
---
Reserved
00h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
---
F5BAR0 Base Address Register Mask
F5BAR1 Base Address Register Mask
F5BAR2 Base Address Register Mask
F5BAR3 Base Address Register Mask
F5BAR4 Base Address Register Mask
F5BAR5 Base Address Register Mask
F5BARx Initialized Register
Reserved
FFFFFFC1h
00000000h
00000000h
00000000h
00000000h
00000000h
00h
59h-FFh
60h-63h
64h-67h
68h-FFh
---
32
32
---
xxh
R/W
R/W
---
Scratchpad for Chip Number
Scratchpad for Configuration Block Address
Reserved
00000000h
00000000h
Table 5-25. F5BAR0: I/O Control Support Registers Summary
F5BAR0+
I/O Offset
Width
(Bits)
Reset
Value
Reference
(Table 5-40)
Type
Name
00h-03h
04h-07h
08h-0Bh
32
32
32
R/W
R/W
R/W
I/O Control Register 1
I/O Control Register 2
I/O Control Register 3
010C0007h
00000002h
00009000h
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Core Logic Module (Continued)
Table 5-26. PCIUSB: USB PCI Configuration Register Summary
PCIUSB
Index
Width
(Bits)
Reference
(Table 5-41)
Type
Name
Reset Value
00h-01h
16
16
16
16
8
RO
RO
R/W
R/W
RO
RO
R/W
R/W
RO
RO
R/W
---
Vendor Identification
Device Identification
Command Register
Status Register
0E11h
A0F8h
00h
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02h-03h
04h-05h
06h-07h
08h
0280h
08h
Device Revision ID
Class Code
09h-0Bh
0Ch
24
8
0C0310h
00h
Cache Line Size
Latency Timer
0Dh
8
00h
0Eh
8
Header Type
00h
0Fh
8
BIST Register
00h
10h-13h
14h-2Bh
2Ch-2Dh
2Eh-2Fh
30h-3Bh
3Ch
32
---
16
16
---
8
Base Address 0
00000000h
00h
Reserved
RO
RO
---
Subsystem Vendor ID
Subsystem ID
0E11h
A0F8h
00h
Reserved
R/W
R/W
RO
RO
R/W
R/W
---
Interrupt Line Register
Interrupt Pin Register
Min. Grant Register
Max. Latency Register
ASIC Test Mode Enable Register
ASIC Operational Mode Enable
Reserved
00h
3Dh
8
01h
3Eh
8
00h
3Fh
8
50h
40h-43h
44h
32
8
000F0000h
00h
45h-FFh
---
00h
Table 5-27. USB_BAR: USB Controller Registers Summary
USB_BAR0
+Memory
Offset
Width
(Bits)
Reference
(Table 5-42)
Type
Name
Reset Value
00h-03h
04h-07h
08h-0Bh
0Ch-0Fh
10h-13h
14h-17h
18h-1Bh
1Ch-1Fh
20h-23h
24h-27h
28h-2Bh
2Ch-2Fh
30h-33h
34h-37h
38h-3Bh
3Ch-3Fh
40h-43h
44h-47h
48h-4Bh
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
HcRevision
00000110h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00002EDFh
00000000h
00000000h
00000000h
00000628h
01000003h
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HcControl
HcCommandStatus
HcInterruptStatus
HcInterruptEnable
HcInterruptDisable
HcHCCA
HcPeriodCurrentED
HcControlHeadED
HcControlCurrentED
HcBulkHeadED
HcBulkCurrentED
HcDoneHead
HcFmInterval
HcFrameRemaining
HcFmNumber
RO
R/W
R/W
R/W
HcPeriodicStart
HcLSThreshold
HcRhDescriptorA
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Core Logic Module (Continued)
Table 5-27. USB_BAR: USB Controller Registers Summary (Continued)
USB_BAR0
+Memory
Offset
Width
(Bits)
Reference
(Table 5-42)
Type
Name
Reset Value
4Ch-4Fh
50h-53h
32
32
32
32
32
---
32
32
32
32
R/W
R/W
R/W
R/W
R/W
---
HcRhDescriptorB
HcRhStatus
00000000h
00000000h
00000000h
00000000h
00000000h
xxxxxxxxh
00000000h
000000xxh
000000xxh
00000000h
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54h-57h
HcRhPortStatus[1]
HcRhPortStatus[2]
HcRhPortStatus[3]
Reserved
58h-5Bh
5Ch-5Fh
60h-9Fh
100h-103h
104h-107h
108h-10Dh
10Ch-10Fh
R/W
R/W
R/W
R/W
HceControl
HceInput
HceOutput
HceStatus
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Core Logic Module (Continued)
Table 5-28. ISA Legacy I/O Register Summary
I/O Port
Type
Name
Reference
DMA Channel Control Registers (Table 5-43)
000h
001h
002h
003h
004h
005h
006h
007h
008h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read
Write
WO
W
DMA Channel 0 Address Register
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DMA Channel 0 Transfer Count Register
DMA Channel 1 Address Register
DMA Channel 1 Transfer Count Register
DMA Channel 2 Address Register
DMA Channel 2 Transfer Count Register
DMA Channel 3 Address Register
DMA Channel 3 Transfer Count Register
DMA Status Register, Channels 3:0
DMA Command Register, Channels 3:0
Software DMA Request Register, Channels 3:0
DMA Channel Mask Register, Channels 3:0
DMA Channel Mode Register, Channels 3:0
DMA Clear Byte Pointer Command, Channels 3:0
DMA Master Clear Command, Channels 3:0
DMA Clear Mask Register Command, Channels 3:0
DMA Write Mask Register Command, Channels 3:0
DMA Channel 4 Address Register (Not used)
DMA Channel 4 Transfer Count Register (Not Used)
DMA Channel 5 Address Register
009h
00Ah
00Bh
00Ch
00Dh
00Eh
00Fh
0C0h
0C2h
0C4h
0C6h
0C8h
0CAh
0CCh
0CEh
0D0h
WO
WO
WO
WO
WO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read
Write
WO
W
DMA Channel 5 Transfer Count Register
DMA Channel 6 Address Register
DMA Channel 6 Transfer Count Register
DMA Channel 7 Address Register
DMA Channel 7 Transfer Count Register
DMA Status Register, Channels 7:4
DMA Command Register, Channels 7:4
Software DMA Request Register, Channels 7:4
DMA Channel Mask Register, Channels 7:4
DMA Channel Mode Register, Channels 7:4
DMA Clear Byte Pointer Command, Channels 7:4
DMA Master Clear Command, Channels 7:4
DMA Clear Mask Register Command, Channels 7:4
DMA Write Mask Register Command, Channels 7:4
0D2h
0D4h
0D6h
0D8h
0DAh
0DCh
0DEh
WO
WO
WO
WO
WO
DMA Page Registers (Table 5-44)
081h
082h
083h
087h
089h
08Ah
08Bh
08Fh
481h
482h
483h
487h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DMA Channel 2 Low Page Register
DMA Channel 3 Low Page Register
DMA Channel 1 Low Page Register
DMA Channel 0 Low Page Register
DMA Channel 6 Low Page Register
DMA Channel 7 Low Page Register
DMA Channel 5 Low Page Register
Sub-ISA Refresh Low Page Register
DMA Channel 2 High Page Register
DMA Channel 3 High Page Register
DMA Channel 1 High Page Register
DMA Channel 0 High Page Register
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Page 310
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Revision 6.0
Core Logic Module (Continued)
Table 5-28. ISA Legacy I/O Register Summary (Continued)
I/O Port
Type
Name
Reference
489h
48Ah
48Bh
R/W
R/W
R/W
DMA Channel 6 High Page Register
DMA Channel 7 High Page Register
DMA Channel 5 High Page Register
Page 310
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Page 310
Programmable Interval Timer Registers (Table 5-45)
040h
041h
042h
043h
W
R
PIT Timer 0 Counter
Page 311
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PIT Timer 0 Status
W
PIT Timer 1 Counter (Refresh)
PIT Timer 1 Status (Refresh)
PIT Timer 2 Counter (Speaker)
PIT Timer 2 Status (Speaker)
PIT Mode Control Word Register
Read Status Command
R
W
R
R/W
Counter Latch Command
Programmable Interrupt Controller Registers (Table 5-46)
020h / 0A0h
021h / 0A1h
021h / 0A1h
021h / 0A1h
021h / 0A1h
020h / 0A0h
020h / 0A0h
020h / 0A0h
WO
WO
WO
WO
R/W
WO
WO
RO
Master / Slave PCI ICW1
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Master / Slave PIC ICW2
Master / Slave PIC ICW3
Master / Slave PIC ICW4
Master / Slave PIC OCW1
Master / Slave PIC OCW2
Master / Slave PIC OCW3
Master / Slave PIC Interrupt Request and Service Registers for OCW3 Commands
Keyboard Controller Registers (Table 5-47)
060h
061h
062h
064h
066h
092h
R/W
R/W
R/W
R/W
R/W
R/W
External Keyboard Controller Data Register
Port B Control Register
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External Keyboard Controller Mailbox Register
External Keyboard Controller Command Register
External Keyboard Controller Mailbox Register
Port A Control Register
Real-Time Clock Registers (Table 5-48)
070h
071h
072h
073h
WO
R/W
WO
R/W
RTC Address Register
Page 317
Page 317
Page 317
Page 317
RTC Data Register
RTC Extended Address Register
RTC Extended Data Register
Miscellaneous Registers (Table 5-49)
0F0h, 0F1h
WO
Coprocessor Error Register
Secondary IDE Registers
Page 317
Page 317
170h-177h/
376h-377h
R/W
1F0-1F7h/
3F6h-3F7h
R/W
Primary IDE Registers
Page 317
4D0h
4D1h
R/W
R/W
Interrupt Edge/Level Select Register 1
Interrupt Edge/Level Select Register 2
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Core Logic Module (Continued)
5.4 CHIPSET REGISTER SPACE
The Chipset Register Space of the Core Logic module is
comprised of six separate functions (F0-F5), each with its
own register space. Base Address Registers (BARs) in
each PCI header register space set the base address for
the configuration registers for each respective function. The
configuration registers accessed through BARs are I/O or
memory mapped. The PCI header registers in all functions
are very similar.
General Remarks:
• Reserved bits that are defined as "must be set to 0 or 1"
should be written with that value.
• Reserved bits that are not defined as "must be set to 0
or 1" should be written with a value that is read from
them.
• "Read to Clear" registers that are wider than one byte
should be read in one read operation. If they are read a
byte at a time, status bits may be lost, or not cleared.
1) Function 0 (F0): PCI Header/Bridge Configuration
Registers for GPIO, and LPC Support (see Section
5.4.1).
5.4.1 Bridge, GPIO, and LPC Registers - Function 0
The register space designated as Function 0 (F0) is used
to configure Bridge features and functionality unique to the
Core Logic module. In addition, it configures the PCI por-
tion of support hardware for the GPIO and LPC support
registers. The bit formats for the PCI Header and Bridge
Configuration registers are given in Table 5-29.
2) Function 1 (F1): PCI Header Registers for SMI Status
and ACPI Support (see Section 5.4.3 on page 266).
3) Function 2 (F2): PCI Header/Channel 0 and 1 Configu-
ration Registers for IDE Controller Support (see Sec-
tion 5.4.3 on page 266).
4) Function 3 (F3): PCI Header Registers for Audio Sup-
port (see Section 5.4.4 on page 272).
Note: The registers at F0 Index 50h-FFh can also be
accessed at F1BAR0+I/O Offset 50h-FFh. How-
ever, the preferred method is to program these reg-
isters through the F0 register space.
5) Function 4 (F4): PCI Header Registers Video Proces-
sor Support (see Section 6.3 on page 341).
6) Function 5 (F5): PCI Header Registers for X-Bus
Expansion Support (see Section 5.4.5 on page 287).
Located in the PCI Header registers of F0, are two Base
Address Registers (F0BARx) used for pointing to the regis-
ter spaces designated for GPIO and LPC configuration
(described in Section 5.4.1.1 "GPIO Support Registers" on
page 236 and Section 5.4.1.2 "LPC Support Registers" on
page 240).
Function 5 contain six BARs in their standard PCI
header locations (i.e., Index 10h, 14h, 18h, 1Ch, 20h,
and 24h). In addition there are six mask registers that
allow the six BARs to be fully programmable from 4
GB to 16 bytes for memory and from 4 GB to 4 bytes
for I/O
Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support
Bit
Description
Index 00h-01h
Index 02h-03h
Index 04h-05h
Vendor Identification Register (RO)
Device Identification Register (RO)
PCI Command Register (R/W)
Reset Value: 100Bh
Reset Value: 0500h
Reset Value: 000Fh
15:10
9
Reserved. Must be set to 0.
Fast Back-to-Back Enable. This function is not supported when the Core Logic module is a master. It must always be dis-
abled (i.e., must be set to 0).
8
SERR#. Allow SERR# assertion on detection of special errors.
0: Disable. (Default)
1: Enable.
7
6
Wait Cycle Control (Read Only). This function is not supported in the Core Logic module. It is always disabled (always
reads 0, hardwired).
Parity Error. Allow the Core Logic module to check for parity errors on PCI cycles for which it is a target and to assert
PERR# when a parity error is detected.
0: Disable. (Default)
1: Enable.
5
VGA Palette Snoop Enable. (Read Only) This function is not supported in the Core Logic module. It is always disabled
(always reads 0, hardwired).
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Core Logic Module (Continued)
Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)
Bit
Description
4
Memory Write and Invalidate. Allow the Core Logic module to do memory write and invalidate cycles, if the PCI Cache
Line register (F0 Index 0Ch) is set to 32 bytes (08h).
0: Disable. (Default)
1: Enable.
3
2
Special Cycles. Allow the Core Logic module to respond to special cycles.
0: Disable.
1: Enable. (Default)
This bit must be enabled to allow the internal CPU Warm Reset signal to be triggered from a CPU Shutdown cycle.
Bus Master. Allow the Core Logic module bus mastering capabilities.
0: Disable.
1: Enable. (Default)
This bit must be set to 1.
1
0
Memory Space. Allow the Core Logic module to respond to memory cycles from the PCI bus.
0: Disable.
1: Enable. (Default)
I/O Space. Allow the Core Logic module to respond to I/O cycles from the PCI bus:
0: Disable.
1: Enable. (Default)
This bit must be set to 1 to access I/O offsets through F0BAR0 and F0BAR1 (see F0 Index 10h and 14h).
Index 06h-07h
PCI Status Register (R/W)
Reset Value: 0280h
15
14
13
Detected Parity Error. This bit is set whenever a parity error is detected.
Write 1 to clear.
Signaled System Error. This bit is set whenever the Core Logic module asserts SERR# active.
Write 1 to clear.
Received Master Abort. This bit is set whenever a master abort cycle occurs. A master abort occurs when a PCI cycle is
not claimed, except for special cycles.
Write 1 to clear.
12
11
Received Target Abort. This bit is set whenever a target abort is received while the Core Logic module is the master for the
PCI cycle.
Write 1 to clear.
Signaled Target Abort. This bit is set whenever the Core Logic module signals a target abort. This occurs when an address
parity error occurs for an address that hits in the active address decode space of the Core Logic module.
Write 1 to clear.
10:9
DEVSEL# Timing. (Read Only) These bits are always 01, as the Core Logic module always responds to cycles for which it
is an active target with medium DEVSEL# timing.
00: Fast
01: Medium
10: Slow
11: Reserved.
8
7
Data Parity Detected. This bit is set when:
1) The Core Logic module asserts PERR# or observed PERR# asserted.
2) The Core Logic module is the master for the cycle in which the PERR# occurred, and PE is set (F0 Index 04h[6] = 1).
Write 1 to clear.
Fast Back-to-Back Capable. (Read Only) Enables the Core Logic module, as a target, to accept fast back-to-back trans-
actions.
0: Disable.
1: Enable.
This bit is always set to 1.
6:0
Reserved. (Read Only) Must be set to 0 for future use.
Index 08h
Device Revision ID Register (RO)
Reset Value: 00h
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Core Logic Module (Continued)
Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)
Bit
Description
Index 09h-0Bh
Index 0Ch
PCI Class Code Register (RO)
Reset Value: 060100h
Reset Value: 00h
PCI Cache Line Size Register (R/W)
7:0
PCI Cache Line Size Register. This register sets the size of the PCI cache line, in increments of four bytes. For memory
write and invalidate cycles, the PCI cache line size must be set to 32 bytes (08h) and the Memory Write and Invalidate bit
(F0 Index 04h[4]) must be set to 1.
Index 0Dh
PCI Latency Timer Register (R/W)
Reset Value: 00h
7:4
3:0
Reserved. Must be set to 0.
PCI Latency Timer Value. The PCI Latency Timer register prevents system lockup when a slave does not respond to a
cycle that the Core Logic module masters.
If the value is set to 00h (default), the timer is disabled.
If the timer is written with any other value, bits [3:0] become the four most significant bits in a timer that counts PCI clocks for
slave response.
The timer is reset on each valid data transfer. If the counter expires before the next assertion of TRDY# is received, the
Core Logic module stops the transaction with a master abort and asserts SERR#, if enabled to do so (via F0 Index 04h[8]).
Index 0Eh
PCI Header Type (RO)
Reset Value: 80h
7:0
PCI Header Type Register. This register defines the format of this header. This header has a format of type 0. (For more
information about this format, see the PCI Local Bus specification, revision 2.2.)
Additionally, bit 7 of this register defines whether this PCI device is a multifunction device (bit 7 = 1) or not (bit 7 = 0).
Index 0Fh
PCI BIST Register (RO)
Reset Value: 00h
This register indicates various information about the PCI Built-In Self-Test (BIST) mechanism.
Note: This mechanism is not supported in the Core Logic module in the SC1200/SC1201.
7
BIST Capable. Indicates if the device can run a Built-In Self-Test (BIST).
0: The device has no BIST functionality.
1: The device can run a BIST.
6
Start BIST. Setting this bit to 1 starts up a BIST on the device. The device resets this bit when the BIST is completed. (Not
supported.)
5:4
3:0
Reserved.
BIST Completion Code. Upon completion of the BIST, the completion code is stored in these bits. A completion code of
0000 indicates that the BIST was successfully completed. Any other value indicates a BIST failure.
Index 10h-13h
Base Address Register 0 - F0BAR0 (R/W)
Reset Value: 00000001h
This register allows access to I/O mapped GPIO runtime and configuration Registers. Bits [5:0] are read only (000001), indicating a 64-
byte aligned I/O address space. Refer to Table 5-30 on page 236 for the GPIO register bit formats and reset values.
31:6
5:0
GPIO Base Address.
Address Range. (Read Only)
Index 14h-17h
Base Address Register 1 - F0BAR1 (R/W)
Reset Value: 00000001h
This register allows access to I/O mapped LPC configuration registers. Bits [5:0] are read only (000001), indicating a 64-byte aligned I/O
address space. Refer to Table 5-31 on page 240 for the bit formats and reset values of the LPC registers.
31:6
5:0
LPC Base Address.
Address Range. (Read Only)
Index 18h-2Bh
Index 2Ch-2Dh
Index 2Eh-2Fh
Index 30h-3Fh
Index 40h
Reserved
Subsystem Vendor ID (RO)
Subsystem ID (RO)
Reset Value: 00h
Reset Value: 100Bh
Reset Value: 0500h
Reset Value: 00h
Reset Value: 39h
Reserved
PCI Function Control Register 1 (R/W)
7:6
5
Reserved. Must be set to 0.
Reserved. Must be set to 0.
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Core Logic Module (Continued)
Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)
Bit
Description
4
PCI Subtractive Decode.
0: Disable transfer of subtractive decode address to external PCI bus. External PCI bus is not usable.
1: Enable transfer of subtractive decode address to external PCI bus. Recommended setting.
Reserved. Must be set to 1.
3
2
1
Reserved. Must be set to 0.
PERR# Signals SERR#. Assert SERR# when PERR# is asserted or detected as active by the Core Logic module (allows
PERR# assertion to be cascaded to NMI (SMI) generation in the system).
0: Disable.
1: Enable.
0
PCI Interrupt Acknowledge Cycle Response. The Core Logic module responds to PCI interrupt acknowledge cycles.
0: Disable.
1: Enable.
Index 41h
PCI Function Control Register 2 (R/W)
Reset Value: 00h
7:6
5
Reserved. Must be set to 0.
X-Bus Configuration Trap. If this bit is set to 1 and an access occurs to one of the configuration registers in PCI Function 5
(F5) register space, an SMI is generated. Writes are trapped; access to the register is denied. Reads are snooped; access
to the register is allowed.
0: Disable.
1: Enable.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[9].
Second level SMI status is reported at F1BAR0+I/O Offset 04h/06h[5].
4
3
2
1
Video Configuration Trap. If this bit is set to 1 and an access occurs to one of the configuration registers in PCI Function 4
(F4) register space, an SMI is generated. Writes are trapped; access to the register is denied. Reads are snooped; access
to the register is allowed.
0: Disable.
1: Enable.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[9].
Second level SMI status is reported at F1BAR0+I/O Offset 04h/06h[5].
Audio Configuration Trap. If this bit is set to 1 and an access occurs to one of the configuration registers in PCI Function
3 (F3) register space, an SMI is generated. Writes are trapped; access to the register is denied. Reads are snooped; access
to the register is allowed.
0: Disable.
1: Enable.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[9].
Second level SMI status is reported at F1BAR0+I/O Offset 04h/06h[5].
IDE Configuration Trap. If this bit is set to 1 and an access occurs to one of the configuration registers in PCI Function 2
(F2) register space, an SMI is generated. Writes are trapped; access to the register is denied. Reads are snooped; access
to the register is allowed.
0: Disable.
1: Enable.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[9].
Second level SMI status is reported at F1BAR0+I/O Offset 04h/06h[5].
Power Management Configuration Trap. If this bit is set to 1 and an access occurs to one of the configuration registers in
PCI Function 1 (F1) register space, an SMI is generated. Writes are trapped; access to the register is denied. Reads are
snooped; access to the register is allowed.
0: Disable.
1: Enable.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[9].
Second level SMI status is reported at F1BAR0+I/O Offset 04h/06h[5].
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Core Logic Module (Continued)
Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)
Bit
Description
0
Legacy Configuration Trap. If this bit is set to 1 and an access occurs to one of the configuration registers in PCI Function
0 (F0), an SMI is generated. Reads and writes are snooped; access to the register is allowed.
0: Disable.
1: Enable.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[9].
Second level SMI status is reported at F1BAR0+I/O Offset 04h/06h[5].
Index 42h
Index 43h
Reserved
Reset Value: 00h
Reset Value: 02h
Delayed Transactions Register (R/W)
7:6
5
Reserved. Must be set to 0.
Reserved. Must be set to 1.
4
Enable PCI Delayed Transactions for Access to I/O Address 170h-177h (Secondary IDE Channel). PIO mode uses
repeated I/O transactions that are faster when non-delayed transactions are used.
0: I/O addresses complete as fast as possible on PCI. (Default)
1: Accesses to Secondary IDE channel I/O addresses are delayed transactions on PCI.
For best performance of VIP, this bit should be set to 1 unless PIO mode 3 or 4 are used.
3
2
1
Enable PCI Delayed Transactions for Access to I/O Address 1F0h-1F7h (Primary IDE Channel). PIO mode uses
repeated I/O transactions that are faster when non-delayed transactions are used.
0: I/O addresses complete as fast as possible on PCI. (Default)
1: Accesses to Primary IDE channel I/O addresses are delayed transactions on PCI.
For best performance of VIP, this bit should be set to 1 unless PIO mode 3 or 4 are used.
Enable PCI Delayed Transactions for AT Legacy PIC I/O Addresses. Some PIC status reads are long. Enabling delayed
transactions help reduce DMA latency for high bandwidth devices like VIP.
0: PIC I/O addresses complete as fast as possible on PCI. (Default)
1: Accesses to PIC I/O addresses are delayed transactions on PCI.
For best performance of VIP, this bit should be set to 1.
Enable PCI Delayed Transactions for AT Legacy PIT I/O Addresses. Some x86 programs (certain benchmarks/diagnos-
tics) assume a particular latency for PIT accesses; this bit allows that code to work.
0: PIT I/O addresses complete as fast as possible on PCI.
1: Accesses to PIT I/O addresses are delayed transactions on PCI. (Default)
For best performance (e.g., when running Microsoft Windows), this bit should be set to 0.
Reserved. Must be set to 0.
0
Index 44h
7
Reset Control Register (R/W)
Reset Value: 01h
AC97 Soft Reset. Active low reset for the AC97 codec interface.
0: AC97_RST# is driven high. (Default)
1: AC97_RST# is driven low.
6:4
3
Reserved. Must be set to 0.
IDE Controller Reset. Reset the IDE controller.
0: Disable.
1: Enable.
Write 0 to clear. This bit is level-sensitive and must be cleared after the reset is enabled.
2
1
IDE Reset. Reset IDE bus.
0: Disable.
1: Enable (drives outputs to zero).
Write 0 to clear. This bit is level-sensitive and must be cleared after the reset is enabled.
PCI Reset. Reset PCI bus.
0: Disable.
1: Enable.
When this bit is set to 1, the Core Logic module output signal PCIRST# is asserted and all devices on the PCI bus (including
PCIUSB) are reset. No other function within the Core Logic module is affected by this bit.
Write 0 to clear this bit. This bit is level-sensitive and must be cleared after the reset is enabled.
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Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)
Bit
Description
0
X-Bus Warm Start. Writing and reading this bit each have different meanings.
When reading this bit, it indicates whether or not a warm start occurred since power-up:
0: A warm start occurred.
1: No warm start has occurred.
When writing this bit, it can be used to trigger a system-wide reset:
0: No effect.
1: Execute system-wide reset (used only for clock configuration at power-up).
Index 45h
Index 46h
Reserved
Reset Value: 00h
Reset Value: FEh
PCI Functions Enable Register (R/W)
7:6
5
Reserved. Resets to 11.
F5 (PCI Function 5). When asserted (set to 1), enables the register space designated as F5.
This bit must always be set to 1. (Default)
4
3
2
1
F4 (PCI Function 4). When asserted (set to 1), enables the register space designated as F4.
This bit must always be set to 1. (Default)
F3 (PCI Function 3). When asserted (set to 1), enables the register space designated as F3.
This bit must always be set to 1. (Default)
F2 (PCI Function 2). When asserted (set to 1), enables the register space designated as F2.
This bit must always be set to 1. (Default)
F1 (PCI Function 1). When asserted (set to 1), enables the register space designated as F1.
This bit must always be set to 1. (Default)
0
Reserved. Must be set to 0.
Index 47h
Miscellaneous Enable Register (R/W)
Reset Value: 00h
7:3
2
Reserved. Must be set to 0.
F0BAR1 (PCI Function 0, Base Address Register 1). F0BAR1, pointer to I/O mapped LPC configuration registers.
0: Disable.
1: Enable.
1
0
F0BAR0 (PCI Function 0, Base Address Register 0). F0BAR0, pointer to I/O mapped GPIO configuration registers.
0: Disable.
1: Enable.
Reserved. Must be set to 0.
Index 48h-4Bh
Index 4Ch-4Fh
Reserved
Reset Value: 00h
Top of System Memory (R/W)
Reset Value: FFFFFFFFh
31:0
Top of System Memory. Highest address in system used to determine active decode for external PCI mastered memory
cycles.
If an external PCI master requests a memory address below the value programmed in this register, the cycle is transferred
from the external PCI bus interface to the Fast-PCI interface for servicing by the GX1 module.
Note: The four least significant bits must be set to 1100.
Index 50h
PIT Control/ISA CLK Divider (R/W)
Reset Value: 7Bh
7
PIT Software Reset.
0: Disable.
1: Enable.
6
5
PIT Counter 1.
0: Forces Counter 1 output (OUT1) to zero.
1: Allows Counter 1 output (OUT1) to pass to the Port 061h[4].
PIT Counter 1 Enable.
0: Sets GATE1 input low.
1: Sets GATE1 input high.
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Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)
Bit
Description
4
PIT Counter 0.
0: Forces Counter 0 output (OUT0) to zero.
1: Allows Counter 0 output (OUT0) to pass to IRQ0.
PIT Counter 0 Enable.
3
0: Sets GATE0 input low.
1: Sets GATE0 input high.
2:0
ISA Clock Divisor. Determines the divisor of the PCI clock used to make the ISA clock, which is typically programmed for
approximately 8 MHz:
000: Divide by 1
001: Divide by 2
010: Divide by 3
011: Divide by 4
100: Divide by 5
101: Divide by 6
110: Divide by 7
111: Divide by 8
If PCI clock = 25 MHz, use setting of 010 (divide by 3).
If PCI clock = 30 or 33 MHz, use a setting of 011 (divide by 4).
Index 51h
ISA I/O Recovery Control Register (R/W)
Reset Value: 40h
7:4
8-Bit I/O Recovery. These bits determine the number of ISA bus clocks between back-to-back 8-bit I/O read cycles. This
count is in addition to a preset one-clock delay built into the controller.
0000: 1 PCI clock
0001: 2 PCI clocks
:::
:::
:::
1111: 16 PCI clocks
3:0
16-Bit I/O Recovery. These bits determine the number of ISA bus clocks between back-to-back 16-bit I/O cycles. This
count is in addition to a preset one-clock delay built into the controller.
0000: 1 PCI clock
0001: 2 PCI clocks
:::
:::
:::
1111: 16 PCI clocks
Index 52h
ROM/AT Logic Control Register (R/W)
Reset Value: 98h
7
Snoop Fast Keyboard Gate A20 and Fast Reset. Enables the snoop logic associated with keyboard commands for A20
Mask and Reset.
0: Disable snooping. The keyboard controller handles the commands.
1: Enable snooping.
6:5
4
Reserved. Must be set to 0.
Enable A20M# De-assertion on Warm Reset. Force A20M# high during a Warm Reset (guarantees that A20M# is de-
asserted regardless of the state of A20).
0: Disable.
1: Enable.
3
2
Enable Port 092h (Port A). Port 092h decode and the logical functions.
0: Disable.
1: Enable.
Upper ROM Size. Selects upper ROM addressing size.
0: 256K (FFFC0000h-FFFFFFFFh).
1: Use ROM Mask register (F0 Index 6Eh).
ROMCS# goes active for the above ranges whether strapped for ISA or LPC. (Refer to F0BAR1+I/O Offset 10h[15] for fur-
ther strapping/programming details.)
The selected range can then be either positively or subtractively decoded through F0 Index 5Bh[5].
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Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)
Bit
Description
1
ROM Write Enable. When asserted, enables writes to ROM space, allowing Flash programming.
If strapped for ISA and this bit is set to 1, writes to the configured ROM space asserts ROMCS#, enabling the write cycle to
the Flash device on the ISA bus. Otherwise, ROMCS# is inhibited for writes.
If strapped for LPC and this bit is set to 1, the cycle runs on the LPC bus. Otherwise, the LPC bus cycle is inhibited for
writes.
Refer to F0BAR1+I/O Offset 10h[15] for further strapping/programming details.
Lower ROM Size. Selects lower ROM addressing size in which ROMCS# goes active.
0: Lower ROM access are 000F0000h-000FFFFFh (64 KB). (Default)
1: Lower ROM accesses are 000E0000h-000FFFFFh (128 KB).
0
ROMCS# goes active for the above ranges whether strapped for ISA or LPC. (Refer to F0BAR1+I/O Offset 10h[15] for fur-
ther strapping/programming details.)
The selected range can then be either positively or subtractively decoded through F0 Index 5Bh[5].
Index 53h
Alternate CPU Support Register (R/W)
Reset Value: 00h
7:6
5
Reserved. Must be set to 0.
Bidirectional SMI Enable.
0: Disable.
1: Enable.
This bit must be set to 0.
Reserved. Must be set to 0.
Reserved. Must be set to 0.
4:3
2
1
IRQ13 Function Selection. Selects function of the internal IRQ13/FERR# signal.
0: FERR#.
1: IRQ13.
This bit must be set to 1.
Generate SMI on A20M# Toggle.
0: Disable.
0
1: Enable.
This bit must be set to 1.
SMI status is reported at F1BAR0+I/O Offset 00h/02h[7].
Index 54h-59h
Reserved
Reset Value: 00h
Reset Value: 01h
Index 5Ah
Decode Control Register 1 (R/W)
Indicates PCI positive or negative decoding for various I/O ports on the ISA bus.
Note: Positive decoding by the Core Logic module speeds up I/O cycle time. The I/O ports mentioned in the bit descriptions below, do
not exist in the Core Logic module. It is assumed that if positive decode is enabled for a port, the port exists on the ISA bus.
7
6
Secondary Floppy Positive Decode. Selects PCI positive or subtractive decoding for accesses to I/O ports 372h-375h
and 377h.
0: Subtractive.
1: Positive.
Primary Floppy Positive Decode. Selects PCI positive or subtractive decoding for accesses to I/O ports 3F2h-3F5h and
3F7h.
0: Subtractive.
1: Positive.
5
4
COM4 Positive Decode. Selects PCI positive or subtractive decoding for accesses to I/O ports 2E8h-2EFh.
0: Subtractive.
1: Positive.
COM3 Positive Decode. Selects PCI positive or subtractive decoding for accesses to I/O ports 3E8h-3EFh.
0: Subtractive.
1: Positive.
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Core Logic Module (Continued)
Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)
Bit
Description
3
COM2 Positive Decode. Selects PCI positive or subtractive decoding for accesses to I/O ports 2F8h-2FFh.
0: Subtractive.
1: Positive.
2
1
COM1 Positive Decode. Selects PCI positive or subtractive decoding for accesses to I/O ports 3F8h-3FFh.
0: Subtractive.
1: Positive.
Keyboard Controller Positive Decode. Selects PCI positive or subtractive decoding for accesses to I/O Ports 060h and
064h (as well as 062h and 066h, if enabled - F4 Index 5Bh[7] = 1).
0: Subtractive.
1: Positive.
Note: If F0BAR1+I/O Offset 10h bits 10 = 0 and 16 = 1, then this bit must be written 0.
0
Real-Time Clock Positive Decode. Selects PCI positive or subtractive decoding for accesses to I/O Ports 070h-073h.
0: Subtractive.
1: Positive.
Index 5Bh
Decode Control Register 2 (R/W)
Reset Value: 20h
Note: Positive decoding by the Core Logic module speeds up the I/O cycle time. The Keyboard, LPT3, LPT2, and LPT1 I/O ports do
not exist in the Core Logic module. It is assumed that if positive decoding is enabled for any of these ports, the port exists on
the ISA bus.
7
Keyboard I/O Port 062h/066h Positive Decode. This alternate port to the keyboard controller is provided in support of
power management features.
0: Disable.
1: Enable.
6
5
Reserved. Must be set to 0.
BIOS ROM Positive Decode. Selects PCI positive or subtractive decoding for accesses to the configured ROM space.
0: Subtractive.
1: Positive.
ROM configuration is at F0 Index 52h[2:0].
4
3
Secondary IDE Controller Positive Decode. Selects PCI positive or subtractive decoding for accesses to I/O ports 170h-
177h and 376h-377h (excluding writes to 377h).
0: Subtractive. Subtractively decoded IDE addresses are forwarded to the PCI slot bus. If a master abort occurs, they are
then forwarded to ISA.
1: Positive. Positively decoded IDE addresses are forwarded to the internal IDE controller and then to the IDE bus.
Primary IDE Controller Positive Decode. Selects PCI positive or subtractive decoding for accesses to I/O ports 1F0h-
1F7h and 3F6h-3F7h (excluding writes to 3F7h).
0: Subtractive. Subtractively decoded IDE addresses are forwarded to the PCI slot bus. If a master abort occurs, they are
then forwarded to ISA.
1: Positive. Positively decoded IDE addresses are forwarded to the internal IDE controller and then to the IDE bus.
2
1
0
LPT3 Positive Decode. Selects PCI positive or subtractive decoding for accesses to I/O ports 278h-27Fh.
0: Subtractive.
1: Positive.
LPT2 Positive Decode. Selects PCI positive or subtractive decoding for accesses to I/O ports 378h-37Fh.
0: Subtractive.
1: Positive.
LPT1 Positive Decode. Selects PCI positive or subtractive decoding for accesses to I/O ports 3BCh-3BFh
0: Subtractive.
1: Positive.
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Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)
Bit
Description
Index 5Ch
PCI Interrupt Steering Register 1 (R/W)
Reset Value: 00h
Indicates target interrupts for signals INTB# and INTA#.
Note: The target interrupt must first be configured as level sensitive via I/O Ports 4D0h and 4D1h in order to maintain PCI interrupt
compatibility.
7:4
3:0
INTB# (EBGA Ball AF1 / TEPBGA Ball C26) Target Interrupt.
0000: Disable
0001: IRQ1
0010: Reserved
0011: IRQ3
0100: IRQ4
0101: IRQ5
0110: IRQ6
0111: IRQ7
1000: Reserved
1001: IRQ9
1010: IRQ10
1011: IRQ11
1100: IRQ12
1101: Reserved
1110: IRQ14
1111: IRQ15
INTA# (EBGA Ball AE3 / TEPBGA Ball D26) Target Interrupt.
0000: Disable
0001: IRQ1
0010: Reserved
0011: IRQ3
0100: IRQ4
0101: IRQ5
0110: IRQ6
0111: IRQ7
1000: Reserved
1001: IRQ9
1010: IRQ10
1011: IRQ11
1100: IRQ12
1101: Reserved
1110: IRQ14
1111: IRQ15
Index 5Dh
PCI Interrupt Steering Register 2 (R/W)
Reset Value: 00h
Indicates target interrupts for signals INTD# and INTC#. Note that INTD# is muxed with IDE_DATA7 (selection made via PMR[24]) and
INTC# is muxed with GPIO19+IOCHRDY (selection made via PMR[9,4]). See Table 3-2 on page 86 for PMR bit descriptions.
Note: The target interrupt must first be configured as level sensitive via I/O Ports 4D0h and 4D1h in order to maintain PCI interrupt
compatibility.
7:4
INTD# (EBGA Ball B22 / TEPBGA Ball AA2) Target Interrupt.
0000: Disable
0001: IRQ1
0010: Reserved
0011: IRQ3
0100: IRQ4
0101: IRQ5
0110: IRQ6
0111: IRQ7
1000: Reserved
1001: IRQ9
1010: IRQ10
1011: IRQ11
1100: IRQ12
1101: Reserved
1110: IRQ14
1111: IRQ15
3:0
INTC# (EBGA Ball H4 / TEPBGA Ball C9) Target Interrupt.
0000: Disable
0001: IRQ1
0010: Reserved
0011: IRQ3
0100: IRQ4
0101: IRQ5
0110: IRQ6
0111: IRQ7
1000: Reserved
1001: IRQ9
1010: IRQ10
1011: IRQ11
1100: IRQ12
1101: Reserved
1110: IRQ14
1111: IRQ15
Index 5Eh-5Fh
Index 60h-63h
Reserved
Reset Value: 00h
Reset Value: 00000000h
ACPI Control Register (R/W)
31:8
7
Reserved. Must be set to 0.
SUSP_3V Shut Down PLL5. Allow internal SUSP_3V to shut down PLL5.
0: Clock generator is stopped when internal SUSP_3V is active.
1: Clock generator continues working when internal SUSP_3V is active.
SUSP_3V Shut Down PLL4. Allow internal SUSP_3V to shut down PLL4
0: Clock generator is stopped when internal SUSP_3V is active.
1: Clock generator continues working when internal SUSP_3V is active.
SUSP_3V Shut Down PLL3. Allow internal SUSP_3V to shut down PLL3.
0: Clock generator is stopped when internal SUSP_3V is active.
1: Clock generator continues working when internal SUSP_3V is active.
SUSP_3V Shut Down PLL2. Allow internal SUSP_3V to shut down PLL2.
0: Clock generator is stopped when internal SUSP_3V is active.
1: Clock generator continues working when internal SUSP_3V is active.
SUSP_3V Shut Down PLL6. Allow internal SUSP_3V to shut down PLL6.
0: Clock generator is stopped when internal SUSP_3V is active.
1: Clock generator continues working when internal SUSP_3V is active.
ACPI C3 SUSP_3V Enable. Allow internal SUSP_3V to be active during C3 state.
0: Disable.
6
5
4
3
2
1: Enable.
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Core Logic Module (Continued)
Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)
Bit
Description
1
ACPI SL1 SUSP_3V Enable. Allow internal SUSP_3V to be active during SL1 sleep state.
0: Disable.
1: Enable.
0
ACPI C3 Support Enable. Allow support of C3 states.
0: Disable.
1: Enable.
Index 64h-6Dh
Index 6Eh-6Fh
Reserved
Reset Value: 00h
ROM Mask Register (R/W)
Reset Value: FFF0h
15:8
7:4
Reserved. Must be set to FFh.
ROM Size. If F0 Index 52h[2] = 1:
0000: 16 MB = FF000000h-FFFFFFFFh
1000: 8 MB = FF800000h-FFFFFFFFh
1100: 4 MB = FFC00000h-FFFFFFFFh
1110: 2 MB = FFE00000h-FFFFFFFFh
1111: 1 MB = FFF00000h-FFFFFFFFh
All other settings for these bits are reserved.
3:0
Reserved. Must be set to 0.
Index 70h-71h
IOCS1# Base Address Register (R/W)
Reset Value: 0000h
15:0
I/O Chip Select 1 Base Address. This 16-bit value represents the I/O base address used to enable assertion of IOCS1#
(EBGA ball H2 or AL12 / TEPBGA ball D10 or N30 - see PMR[23] in Table 3-2 on page 86).
This register is used in conjunction with F0 Index 72h (IOCS1# Control register).
Index 72h
IOCS1# Control Register (R/W)
Reset Value: 00h
This register is used in conjunction with F0 Index 70h (IOCS1# Base Address register).
7
I/O Chip Select 1 Positive Decode (IOCS1#).
0: Disable.
1: Enable.
6
Writes Result in Chip Select. When this bit is set to 1, writes to configured I/O address (base address configured in F0
Index 70h; range configured in bits [4:0]) cause IOCS1# to be asserted.
0: Disable.
1: Enable.
5
Reads Result in Chip Select. When this bit is set to 1, reads from configured I/O address (base address configured in F0
Index 70h; range configured in bits [4:0]) cause IOCS1# to be asserted.
0: Disable.
1: Enable.
4:0
IOCS1# I/O Address Range. This 5-bit field is used to select the range of IOCS1#.
00000: 1 Byte
00001: 2 Bytes
00011: 4 Bytes
00111: 8 Bytes
01111: 16 Bytes
11111: 32 Bytes
All other combinations are reserved.
Index 73h
Reserved
Reset Value: 00h
Index 74h-75h
IOCS0# Base Address Register (R/W)
Reset Value: 0000h
15:0
I/O Chip Select 0 Base Address. This 16-bit value represents the I/O base address used to enable the assertion of
IOCS0# (EBGA ball J4 / TEPBGA ball A10 - see PMR[23] in Table 3-2 on page 86).
This register is used in conjunction with F0 Index 76h (IOCS0# Control register).
Index 76h
IOCS0# Control Register (R/W)
Reset Value: 00h
This register is used in conjunction with F0 Index 74h (IOCS0# Base Address register).
7
I/O Chip Select 0 Positive Decode (IOCS0#).
0: Disable.
1: Enable.
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Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)
Bit
Description
6
Writes Result in Chip Select. When this bit is set to 1, writes to configured I/O address (base address configured in F0
Index 74h; range configured in bits [4:0]) cause IOCS0# to be asserted.
0: Disable.
1: Enable.
5
Reads Result in Chip Select. When this bit is set to 1, reads from configured I/O address (base address configured in F0
Index 74h; range configured in bits [4:0]) cause IOCS0# to be asserted.
0: Disable.
1: Enable.
4:0
IOCS0# I/O Address Range. This 5-bit field is used to select the range of IOCS0#.
00000: 1 Byte
00001: 2 Bytes
00011: 4 Bytes
00111: 8 Bytes
01111: 16 Bytes
11111: 32 Bytes
All other combinations are reserved.
Index 77h
Reserved
Reset Value: 00h
Index 78h-7Bh
31:0
DOCCS# Base Address Register (R/W)
Reset Value: 00000000h
DiskOnChip Chip Select Base Address. This 32-bit value represents the memory base address used to enable assertion
of DOCCS# (EBGA ball H3 or AJ13 / TEPBGA ball A9 or N31, see PMR[23] in Table 3-2 on page 86).
This register is used in conjunction with F0 Index 7Ch (DOCCS# Control register).
Index 7Ch-7Fh
DOCCS# Control Register (R/W)
Reset Value: 00000000h
This register is used in conjunction with F0 Index 78h (DOCCS# Base Address register).
31:27
26
Reserved. Must be set to 0.
DiskOnChip Chip Select Positive Decode (DOCCS#).
0: Disable.
1: Enable.
25
24
Writes Result in Chip Select. When this bit is set to 1, writes to configured memory address (base address configured in
F0 Index 78h; range configured in bits [18:0]) cause DOCCS# to be asserted.
0: Disable.
1: Enable.
Reads Result in Chip Select. When this bit is set to 1, reads from configured memory address (base address configured in
F0 Index 78h; range configured in bits [18:0]) cause DOCCS# to be asserted.
0: Disable.
1: Enable.
23:19
18:0
Reserved. Must be set to 0.
DOCCS# Memory Address Range. This 19-bit mask is used to qualify accesses on which DOCCS# is asserted by mask-
ing the upper 19 bits of the incoming PCI address (AD[31:13]).
Index 80h
Power Management Enable Register 1 (R/W)
Reset Value: 00h
7:6
5
Reserved. Must be set to 0.
Codec SDATA_IN SMI. When set to 1, this bit allows an SMI to be generated in response to an AC97 codec producing a
positive edge on SDATA_IN.
0: Disable.
1: Enable.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 87h/F7h[2].
4
Video Speedup. Any video activity, as decoded from the serial connection (PSERIAL) from the GX1 module disables clock
throttling (via internal SUSP#/SUSPA# handshake) for a configurable duration when system is power-managed using CPU
Suspend modulation.
0: Disable.
1: Enable.
The duration of the speedup is configured in the Video Speedup Timer Count Register (F0 Index 8Dh). Detection of an
external VGA access (3Bx, 3Cx, 3Dx and A000h-B7FFh) on the PCI bus is also supported. This configuration is non-stan-
dard, but it does allow the power management routines to support an external VGA chip.
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Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)
Bit
Description
3
IRQ Speedup. Any unmasked IRQ (per I/O Ports 021h/0A1h) or SMI disables clock throttling (via internal SUSP#/SUSPA#
handshake) for a configurable duration when system is power-managed using CPU Suspend modulation.
0: Disable.
1: Enable.
The duration of the speedup is configured in the IRQ Speedup Timer Count Register (F0 Index 8Ch).
2
1
Traps. Globally enable all power management I/O traps.
0: Disable.
1: Enable.
This excludes the audio I/O traps, which are enabled via F3BAR0+Memory Offset 18h.
Idle Timers. Device idle timers.
0: Disable.
1: Enable.
Note: Disable at this level does not reload the timers on the enable. The timers are disabled at their current counts.
This bit has no affect on the Suspend Modulation register (F0 Index 94h).
Only applicable when in APM mode (F1BAR1+I/O Offset 0Ch[0] = 0) and not ACPI mode.
0
Power Management. Global power management.
0: Disable.
1: Enable.
This bit must be set to 1 immediately after POST for power management resources to function.
Index 81h
Power Management Enable Register 2 (R/W)
Reset Value: 00h
7
Video Access Idle Timer Enable. Turn on Video Idle Timer Count Register (F0 Index A6h) and generate an SMI when the
timer expires.
0: Disable.
1: Enable.
If an access occurs in the video address range (sets bit 0 of the GX1 module’s PSERIAL register) the timer is reloaded with
the programmed count.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 85h/F5h[7].
6
5
4
User Defined Device 3 (UDEF3) Idle Timer Enable. Turn on UDEF3 Idle Timer Count Register (F0 Index A4h) and gener-
ate an SMI when the timer expires.
0: Disable.
1: Enable.
If an access occurs in the programmed address range, the timer is reloaded with the programmed count.
UDEF3 address programming is at F0 Index C8h (base address register) and CEh (control register).
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 85h/F5h[6].
User Defined Device 2 (UDEF2) Idle Timer Enable. Turn on UDEF2 Idle Timer Count Register (F0 Index A2h) and gener-
ate an SMI when the timer expires.
0: Disable.
1: Enable.
If an access occurs in the programmed address range, the timer is reloaded with the programmed count.
UDEF2 address programming is at F0 Index C4h (base address register) and CDh (control register).
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 85h/F5h[5].
User Defined Device 1 (UDEF1) Idle Timer Enable. Turn on UDEF1 Idle Timer Count Register (F0 Index A0h) and gener-
ate an SMI when the timer expires.
0: Disable.
1: Enable.
If an access occurs in the programmed address range, the timer is reloaded with the programmed count.
UDEF1 address programming is at F0 Index C0h (base address register) and CCh (control register).
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 85h/F5h[4].
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Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)
Bit
Description
3
Keyboard/Mouse Idle Timer Enable. Turn on Keyboard/Mouse Idle Timer Count Register (F0 Index 9Eh) and generate an
SMI when the timer expires.
0: Disable.
1: Enable.
If an access occurs in the address ranges listed below, the timer is reloaded with the programmed count:
— Keyboard Controller: I/O Ports 060h/064h.
— COM1: I/O Port 3F8h-3FFh (if F0 Index 93h[1:0] = 10 this range is included).
— COM2: I/O Port 2F8h-2FFh (if F0 Index 93h[1:0] = 11 this range is included).
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 85h/F5h[3].
2
Parallel/Serial Idle Timer Enable. Turn on Parallel/Serial Port Idle Timer Count Register (F0 Index 9Ch) and generate an
SMI when the timer expires.
0: Disable.
1: Enable.
If an access occurs in the address ranges listed below, the timer is reloaded with the programmed count.
— LPT1: I/O Port 3BCh-3BEh.
— LPT2: I/O Port 378h-37Fh.
— COM1: I/O Port 3F8h-3FFh (if F0 Index 93h[1:0] = 10 this range is excluded).
— COM2: I/O Port 2F8h-2FFh (if F0 Index 93h[1:0] = 11 this range is excluded).
— COM3: I/O Port 3E8h-3EFh.
— COM4: I/O Port 2E8h-2EFh.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 85h/F5h[2].
1
Floppy Disk Idle Timer Enable. Turn on Floppy Disk Idle Timer Count Register (F0 Index 9Ah) and generate an SMI when
the timer expires.
0: Disable.
1: Enable.
If an access occurs in the address ranges (listed below, the timer is reloaded with the programmed count.
— Primary floppy disk: I/O Port 3F2h-3F5h, 3F7h.
— Secondary floppy disk: I/O Port 372h-375h, 377h.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 85h/F5h[1].
0
Primary Hard Disk Idle Timer Enable. Turn on Primary Hard Disk Idle Timer Count Register (F0 Index 98h) and generate
an SMI when the timer expires.
0: Disable.
1: Enable.
If an access occurs in the address ranges selected in F0 Index 93h[5], the timer is reloaded with the programmed count.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 85h/F5h[0].
Index 82h
Power Management Enable Register 3 (R/W)
Reset Value: 00h
7
Video Access Trap. If this bit is enabled and an access occurs in the video address range (sets bit 0 of the GX1 module’s
PSERIAL register), an SMI is generated.
0: Disable.
1: Enable.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 86h/F6h[7].
6
User Defined Device 3 (UDEF3) Access Trap. If this bit is enabled and an access occurs in the programmed address
range, an SMI is generated. UDEF3 address programming is at F0 Index C8h (Base Address register) and CEh (Control
register).
0: Disable.
1: Enable.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[9].
Second level SMI status is reported at F1BAR0+I/O Offset 04h/06h[4].
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Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)
Bit
Description
5
User Defined Device 2 (UDEF2) Access Trap. If this bit is enabled and an access occurs in the programmed address
range, an SMI is generated. UDEF2 address programming is at F0 Index C4h (Base Address register) and CDh (Control
register).
0: Disable.
1: Enable.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[9].
Second level SMI status is reported at F1BAR0+I/O Offset 04h/06h[3].
4
User Defined Device 1 (UDEF1) Access Trap. If this bit is enabled and an access occurs in the programmed address
range, an SMI is generated. UDEF1 address programming is at F0 Index C0h (base address register), and CCh (control
register).
0: Disable.
1: Enable.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[9].
Second level SMI status is reported at F1BAR0+I/O Offset 04h/06h[2].
3
Keyboard/Mouse Access Trap.
0: Disable.
1: Enable.
If this bit is enabled and an access occurs in the address ranges listed below, an SMI is generated.
— Keyboard Controller: I/O Ports 060h/064h.
— COM1: I/O Port 3F8h-3FFh (if F0 Index 93h[1:0] = 10 this range is included).
— COM2: I/O Port 2F8h-2FFh (if F0 Index 93h[1:0] = 11 this range is included).
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 86h/F6h[3].
2
Parallel/Serial Access Trap.
0: Disable.
1: Enable.
If this bit is enabled and an access occurs in the address ranges listed below, an SMI is generated.
— LPT1: I/O Port 3BCh-3BEh.
— LPT2: I/O Port 378h-37Fh.
— COM1: I/O Port 3F8h-3FFh (if F0 Index 93h[1:0] = 10 this range is excluded).
— COM2: I/O Port 2F8h-2FFh (if F0 Index 93h[1:0] = 11 this range is excluded).
— COM3: I/O Port 3E8h-3EFh.
— COM4: I/O Port 2E8h-2EFh.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 86h/F6h[2].
1
Floppy Disk Access Trap.
0: Disable.
1: Enable.
If this bit is enabled and an access occurs in the address ranges listed below, an SMI is generated.
— Primary floppy disk: I/O Port 3F2h-3F5h, 3F7h.
— Secondary floppy disk: I/O Port 372h-375h, 377h.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 86h/F6h[1].
0
Primary Hard Disk Access Trap.
0: Disable.
1: Enable.
If this bit is enabled and an access occurs in the address ranges selected in F0 Index 93h[5], an SMI is generated.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 86h/F6h[0].
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Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)
Bit
Description
Index 83h
Power Management Enable Register 4 (R/W)
Reset Value: 00h
7
Secondary Hard Disk Idle Timer Enable. Turn on Secondary Hard Disk Idle Timer Count Register (F0 Index ACh) and
generate an SMI when the timer expires.
0: Disable.
1: Enable.
If an access occurs in the address ranges selected in F0 Index 93h[4], the timer is reloaded with the programmed count.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 86h/F6h[4].
6
5
Secondary Hard Disk Access Trap. If this bit is enabled and an access occurs in the address ranges selected in F0 Index
93h[4], an SMI is generated.
0: Disable.
1: Enable.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 86h/F6h[5].
ACPI Timer SMI. Allow SMI generation for MSB toggles on the ACPI Timer (F1BAR0+I/O Offset 1Ch or
F1BAR1+I/O Offset 1Ch).
0: Disable.
1: Enable.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 87h/F7h[0].
4
3
THRM# SMI. Allow SMI generation on assertion of THRM#.
0: Disable.
1: Enable.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 87h/F7h[6].
VGA Timer Enable. Turn on VGA Timer Count Register (F0 Index 8Eh) and generate an SMI when the timer reaches 0.
0: Disable.
1: Enable.
If an access occurs in the programmed address range, the timer is reloaded with the programmed count. F0 Index 8Bh[6]
selects the timebase for the VGA Timer.
SMI status is reported at F1BAR0+I/O Offset 00h/02h[6] (top level only).
2
1
Video Retrace Interrupt SMI. Allow SMI generation whenever video retrace occurs.
0: Disable.
1: Enable.
This information is decoded from the serial connection (PSERIAL register, bit 7) from the GX1 module. This function is nor-
mally not used for power management but for soft (VSA) VGA routines.
SMI status reporting is at F1BAR0+I/O Offset 00h/02h[5] (top level only).
General Purpose Timer 2 Enable. Turn on GP Timer 2 Count Register (F0 Index 8Ah) and generate an SMI when the
timer expires.
0: Disable.
1: Enable.
This idle timer is reloaded from the assertion of GPIO7 (if programmed to do so). GP Timer 2 programming is at F0 Index
8Bh[5,3,2].
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[9].
Second level SMI status is reported at F1BAR0+I/O Offset 04h/06h[1].
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Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)
Bit
Description
0
General Purpose Timer 1 Enable. Turn on GP Timer 1 Count Register (F0 Index 88h) and generate an SMI when the timer
expires.
0: Disable.
1: Enable.
This idle timer’s load is multi-sourced and gets reloaded any time an enabled event (F0 Index 89h[6:0]) occurs.
GP Timer 1 programming is at F0 Index 8Bh[4].
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[9].
Second level SMI status is reported at F1BAR0+I/O Offset 04h/06h[0].
Index 84h
Second Level PME/SMI Status Mirror Register 1 (RO)
Reset Value: 00h
The bits in this register are used for the second level of status reporting. The top level is reported at F1BAR0+I/O Offset 00h/02h[0].
This register is called a "mirror" register since an identical register exists at F0 Index F4h. Reading this register does not clear the status,
while reading its counterpart at F0 Index F4h clears the status at both the second and the top levels.
7:3
2
Reserved. Reads as 0.
GPWIO2 SMI Status. Indicates whether or not an SMI was caused by a transition on the GPWIO2 pin.
0: No.
1: Yes.
To enable SMI generation:
1) Ensure that GPWIO2 is enabled as an input: F1BAR1+I/O Offset 15h[2] = 0.
2) Set F1BAR1+I/O Offset 15h[6] to 1.
1
0
GPWIO1 SMI Status. Indicates whether or not an SMI was caused by a transition on the GPWIO1 pin.
0: No.
1: Yes.
To enable SMI generation:
1) Ensure that GPWIO1 is enabled as an input: F1BAR1+I/O Offset 15h[1] = 0.
2) Set F1BAR1+I/O Offset 15h[5] to 1.
GPWIO0 SMI Status. Indicates whether or not an SMI was caused by a transition on the GPWIO0 pin.
0: No.
1: Yes.
To enable SMI generation:
1) Ensure that GPWIO0 is enabled as an input: F1BAR1+I/O Offset 15h[0] = 0.
2) Set F1BAR1+I/O Offset 15h[4] to 1.
Index 85h
Second Level PME/SMI Status Mirror Register 2 (RO)
Reset Value: 00h
The bits in this register contain second level status reporting. Top level status is reported in F1BAR0+I/O Offset 00h/02h[0].
This register is called a “Mirror” register since an identical register exists at F0 Index F5h. Reading this register does not clear the status,
while reading its counterpart at F0 Index F5h clears the status at both the second and top levels.
7
6
5
Video Idle Timer Timeout. Indicates whether or not an SMI was caused by expiration of Video Idle Timer Count Register
(F0 Index A6h).
0: No.
1: Yes.
To enable SMI generation, set F0 Index 81h[7] to 1.
User Defined Device Idle Timer 3 Timeout. Indicates whether or not an SMI was caused by expiration of User Defined
Device 3 Idle Timer Count Register (F0 Index A4h).
0: No
1: Yes
To enable SMI generation, set F0 Index 81h[6] to 1.
User Defined Device Idle Timer 2 Timeout. Indicates whether or not an SMI was caused by expiration of User Defined
Device 2 Idle Timer Count Register (F0 Index A2h).
0: No.
1: Yes.
To enable SMI generation, set F0 Index 81h[5] to 1.
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Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)
Bit
Description
4
User Defined Device Idle Timer 1 Timeout. Indicates whether or not an SMI was caused by expiration of User Defined
Device 1 Idle Timer Count Register (F0 Index A0h).
0: No.
1: Yes.
To enable SMI generation, set F0 Index 81h[4] to 1.
3
2
1
0
Keyboard/Mouse Idle Timer Timeout. Indicates whether or not an SMI was caused by expiration of Keyboard/Mouse Idle
Timer Count Register (F0 Index 9Eh).
0: No.
1: Yes.
To enable SMI generation, set F0 Index 81h[3] to 1.
Parallel/Serial Idle Timer Timeout. Indicates whether or not an SMI was caused by expiration of Parallel/Serial Port Idle
Timer Count Register (F0 Index 9Ch).
0: No.
1: Yes.
To enable SMI generation, set F0 Index 81h[2] to 1.
Floppy Disk Idle Timer Timeout. Indicates whether or not an SMI was caused by expiration of Floppy Disk Idle Timer
Count Register (F0 Index 9Ah).
0: No.
1: Yes.
To enable SMI generation, set F0 Index 81h[1] to 1.
Primary Hard Disk Idle Timer Timeout. Indicates whether or not an SMI was caused by expiration of Primary Hard Disk
Idle Timer Count Register (F0 Index 98h).
0: No.
1: Yes.
To enable SMI generation, set F0 Index 81h[0] to 1.
Index 86h
Second Level PME/SMI Status Mirror Register 3 (RO)
Reset Value: 00h
The bits in this register contain second level status reporting. Top level status is reported in F1BAR0+I/O Offset 00h/02h[0].
This register is called a “Mirror” register since an identical register exists at F0 Index F6h. Reading this register does not clear the status,
while reading its counterpart at F0 Index F6h clears the status at both the second and top levels.
7
Video Access Trap SMI Status. Indicates whether or not an SMI was caused by a trapped I/O access to the Video I/O
Trap.
0: No.
1: Yes.
To enable SMI generation, set F0 Index 82h[7] to 1.
6
5
Reserved
Secondary Hard Disk Access Trap SMI Status. Indicates whether or not an SMI was caused by a trapped I/O access to
the secondary hard disk.
0: No.
1: Yes.
To enable SMI generation, set F0 Index 83h[6] to 1.
4
3
Secondary Hard Disk Idle Timer SMI Status. Indicates whether or not an SMI was caused by expiration of Secondary
Hard Disk Idle Timer Count register (F0 Index ACh).
0: No.
1: Yes.
To enable SMI generation, set F0 Index 83h[7] to 1.
Keyboard/Mouse Access Trap SMI Status. Indicates whether or not an SMI was caused by an trapped I/O access to the
keyboard or mouse.
0: No.
1: Yes.
To enable SMI generation, set F0 Index 82h[3] to 1.
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Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)
Bit
Description
2
Parallel/Serial Access Trap SMI Status. Indicates whether or not an SMI was caused by a trapped I/O access to either the
serial or parallel ports.
0: No.
1: Yes.
To enable SMI generation, set F0 Index 82h[2] to 1.
1
0
Floppy Disk Access Trap SMI Status. Indicates whether or not an SMI was caused by a trapped I/O access to the floppy
disk.
0: No.
1: Yes.
To enable SMI generation, set F0 Index 82h[1] to 1.
Primary Hard Disk Access Trap SMI Status. Indicates whether or not an SMI was caused by a trapped I/O access to the
primary hard disk.
0: No.
1: Yes.
To enable SMI generation, set F0 Index 82h[0] to 1.
Index 87h
Second Level PME/SMI Status Mirror Register 4 (RO)
Reset Value: 00h
The bits in this register contain second level status reporting. Top level status is reported at F1BAR0+I/O Offset 00h/02h[0].
This register is called a “Mirror” register since an identical register exists at F0 Index F7h. Reading this register does not clear the status,
while reading its counterpart at F0 Index F7h clears the status at both the second and top levels except for bit 7 which has a third level
of SMI status reporting at F0BAR0+I/O 0Ch/1Ch.
7
GPIO Event SMI Status. Indicates whether or not an SMI was caused by a transition of any of the GPIOs (GPIO47-GPIO32
and GPIO15-GPIO0).
0: No.
1: Yes.
To enable SMI generation, set F1BAR1+I/O Offset 0Ch[0] to 0.
F0BAR0+I/O Offset 08h/18h selects which GPIOs are enabled to generate a PME and setting F1BAR1+I/O Offset 0Ch[0] =
0 enables the PME to generate an SMI. In addition, the selected GPIO must be enabled as an input (F0BAR0+I/O Offset
20h and 24h).
The next level (third level) of SMI status is at F0BAR0+I/O 0Ch/1Ch[15:0].
6
Thermal Override SMI Status. Indicates whether or not an SMI was caused by the assertion of THRM#.
0: No.
1: Yes.
To enable SMI generation, set F0 Index 83h[4] to 1.
5:4
3
Reserved. Always reads 0.
SIO PWUREQ SMI Status. Indicates whether or not an SMI was caused by a power-up event from the SIO.
0: No.
1: Yes.
A power-up event is defined as any of the following events/activities:
— RI2#
— SDATA_IN2
— IRRX1 (CEIR)
To enable SMI generation, set F1BAR1+I/O Offset 0Ch[0] to 0.
2
1
Codec SDATA_IN SMI Status. Indicates whether or not an SMI was caused by AC97 Codec producing a positive edge on
SDATA_IN.
0: No.
1: Yes.
To enable SMI generation, set F0 Index 80h[5] to 1.
RTC Alarm (IRQ8#) SMI Status. Indicates whether or not an SMI was caused by an RTC interrupt.
0: No.
1: Yes.
This SMI event can only occur while in 3V Suspend and an RTC interrupt occurs with F1BAR1+I/O Offset 0Ch[0] = 0.
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Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)
Bit
Description
0
ACPI Timer SMI Status. Indicates whether or not an SMI was caused by an ACPI Timer (F1BAR0+I/O Offset 1Ch or
F1BAR1+I/O Offset 1Ch) MSB toggle.
0: No.
1: Yes.
To enable SMI generation, set F0 Index 83h[5] to 1.
Index 88h
General Purpose Timer 1 Count Register (R/W)
Reset Value: 00h
7:0
GPT1_COUNT. This field represents the load value for General Purpose Timer 1. This value can represent either an 8-bit
counter or a 16-bit counter (selected in F0 Index 8Bh[4]). It is loaded into the counter when the timer is enabled (F0 Index
83h[0] = 1). Once enabled, an enabled event (configured in F0 Index 89h[6:0]) reloads the timer.
The counter is decremented with each clock of the configured timebase (1 msec or 1 sec selected at F0 Index 89h[7]). Upon
expiration of the counter, an SMI is generated, and the top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[9].
The second level SMI status is reported at F1BAR0+I/O Offset 04h/06h[0]. Once expired, this counter must be re-initialized
by either disabling and enabling it, or writing a new count value in this register.
Index 89h
General Purpose Timer 1 Control Register (R/W)
Reset Value: 00h
7
General Purpose Timer 1 TImebase. Selects timebase for General Purpose Timer 1 (F0 Index 88h).
0: 1 second.
1: 1 millisecond.
6
5
4
3
Re-trigger General Purpose Timer 1 on User Defined Device 3 (UDEF3) Activity.
0: Disable.
1: Enable.
Any access to the configured (memory or I/O) address range for UDEF3 (configured in F0 Index C8h and CEh) reloads
General Purpose Timer 1.
Re-trigger General Purpose Timer 1 on User Defined Device 2 (UDEF2) Activity.
0: Disable.
1: Enable.
Any access to the configured (memory or I/O) address range for UDEF2 (configured in F0 Index C4h and CDh) reloads
General Purpose Timer 1.
Re-trigger General Purpose Timer 1 on User Defined Device 1 (UDEF1) Activity.
0: Disable.
1: Enable.
Any access to the configured (memory or I/O) address range for UDEF1 (configured in F0 Index C0h and CCh) reloads
General Purpose Timer 1.
Re-trigger General Purpose Timer 1 on Keyboard or Mouse Activity.
0: Disable.
1: Enable.
Any access to the keyboard or mouse I/O address range listed below reloads General Purpose Timer 1:
— Keyboard Controller: I/O Ports 060h/064h.
— COM1: I/O Port 3F8h-3FFh (if F0 Index 93h[1:0] = 10 this range is included).
— COM2: I/O Port 2F8h-2FFh (if F0 Index 93h[1:0] = 11 this range is included).
2
Re-trigger General Purpose Timer 1 on Parallel/Serial Port Activity.
0: Disable.
1: Enable.
Any access to the parallel or serial port I/O address range listed below reloads the General Purpose Timer 1:
— LPT1: I/O Port 3BCh-3BEh.
— LPT2: I/O Port 378h-37Fh.
— COM1: I/O Port 3F8h-3FFh (if F0 Index 93h[1:0] = 10 this range is excluded).
— COM2: I/O Port 2F8h-2FFh (if F0 Index 93h[1:0] = 11 this range is excluded).
— COM3: I/O Port 3E8h-3EFh.
— COM4: I/O Port 2E8h-2EFh.
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Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)
Bit
Description
1
Re-trigger General Purpose Timer 1 on Floppy Disk Activity.
0: Disable.
1: Enable.
Any access to the floppy disk drive address ranges listed below reloads General Purpose Timer 1:
— Primary floppy disk: I/O Port 3F2h-3F5h, 3F7h
— Secondary floppy disk: I/O Port 372h-375h, 377h
The active floppy disk drive is configured via F0 Index 93h[7].
0
Re-trigger General Purpose Timer 1 on Primary Hard Disk Activity.
0: Disable.
1: Enable.
Any access to the primary hard disk address range selected in F0 Index 93h[5], reloads General Purpose Timer 1.
Index 8Ah
General Purpose Timer 2 Count Register (R/W)
Reset Value: 00h
7:0
GPT2_COUNT. This field represents the load value for General Purpose Timer 2. This value can represent either an 8-bit or
16-bit counter (configured in F0 Index 8Bh[5]). It is loaded into the counter when the timer is enabled (F0 Index 83h[1] = 1).
Once the timer is enabled and a transition occurs on GPIO7, the timer is re-loaded.
The counter is decremented with each clock of the configured timebase (1 msec or 1 sec selected at F0 Index 8Bh[3]).
Upon expiration of the counter, an SMI is generated and the top level of status is F1BAR0+I/O Offset 00h/02h[9]. The sec-
ond level of status is reported at F1BAR0+I/O Offset 04h/06h[1]). Once expired, this counter must be re-initialized by either
disabling and enabling it, or by writing a new count value in this register.
For GPIO7 to act as the reload for this counter, it must be enabled as such (F0 Index 8Bh[2]) and be configured as an input.
(GPIO pin programming is at F0BAR0+I/O Offset 20h and 24h.)
Index 8Bh
General Purpose Timer 2 Control Register (R/W)
Reset Value: 00h
7
Re-trigger General Purpose Timer 1 (GP Timer 1) on Secondary Hard Disk Activity.
0: Disable.
1: Enable.
Any access to the secondary hard disk address range selected in F0 Index 93h[4] reloads GP Timer 1.
VGA Timer Base. Selects timebase for VGA Timer Register (F0 Index 8Eh).
0: 1 millisecond.
6
5
1: 32 microseconds.
General Purpose Timer 2 (GP Timer 2) Shift. GP Timer 2 is treated as an 8-bit or 16-bit timer.
0: 8-bit. The count value is loaded into GP Timer 2 Count Register (F0 Index 8Ah).
1: 16-bit. The value loaded into GP Timer 2 Count Register is shifted left by eight bits, the lower eight bits become zero,
and this 16-bit value is used as the count for GP Timer 2.
4
General Purpose Timer 1 (GP Timer 1) Shift. GP Timer 1 is treated as an 8-bit or 16-bit timer.
0: 8-bit. The count value is that loaded into GP Timer 1 Count Register (F0 Index 88h).
1: 16-bit. The value loaded into GP Timer 1 Count Register is shifted left by eight bit, the lower eight bits become zero, and
this 16-bit value is used as the count for GP Timer 1.
3
2
General Purpose Timer 2 (GP Timer 2) Timebase. Selects timebase for GP Timer 2 (F0 Index 8Ah).
0: 1 second.
1: 1 millisecond.
Re-trigger Timer on GPIO7 Pin Transition. A rising-edge transition on the GPIO7 pin reloads GP Timer 2 (F0 Index 8Ah).
0: Disable.
1: Enable.
For GPIO7 to work here, it must first be configured as an input. (GPIO pin programming is at F0BAR0+I/O Offset 20h and
24h.)
1:0
Reserved. Set to 0.
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Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)
Bit
Description
Index 8Ch
IRQ Speedup Timer Count Register (R/W)
Reset Value: 00h
7:0
IRQ Speedup Timer Load Value. This field represents the load value for the IRQ speedup timer. It is loaded into the
counter when Suspend Modulation is enabled (F0 Index 96h[0] = 1) and an INTR or an access to I/O Port 061h occurs.
When the event occurs, the Suspend Modulation logic is inhibited, permitting full performance operation of the GX1 module.
Upon expiration, no SMI is generated; the Suspend Modulation begins again. The IRQ speedup timer’s timebase is 1 msec.
This speedup mechanism allows instantaneous response to system interrupts for full-speed interrupt processing. A typical
value here would be 2 to 4 msec.
Index 8Dh
Video Speedup Timer Count Register (R/W)
Reset Value: 00h
7:0
Video Speedup Timer Load Value. This field represents the load value for the Video speedup timer. It is loaded into the
counter when Suspend Modulation is enabled (F0 Index 96[0] = 1) and any access to the graphics controller occurs. When
a video access occurs, the Suspend Modulation logic is inhibited, permitting full-performance operation of the GX1 module.
Upon expiration, no SMI is generated, and Suspend Modulation begins again. The video speedup timer’s timebase is 1
msec.
This speedup mechanism allows instantaneous response to video activity for full speed during video processing calcula-
tions. A typical value here would be 50 msec to 100 msec.
Index 8Eh
VGA Timer Count Register (R/W)
Reset Value: 00h
7:0
VGA Timer Load Value. This field represents the load value for VGA Timer. It is loaded into the counter when the timer is
enabled (F0 Index 83h[3] = 1). The counter is decremented with each clock of the configured timebase (F0 Index 8Bh[6]).
Upon expiration of the counter, an SMI is generated and the status is reported at F1BAR0+I/O Offset 00h/02h[6] (only).
Once expired, this counter must be re-initialized by either disabling and enabling it, or by writing a new count value in this
register.
Note:
Although grouped with the power management Idle Timers, the VGA Timer is not a power management function.
It is not affected by the Global Power Management Enable setting at F0 Index 80h[0].
Index 8Fh-92h
Index 93h
Reserved
Reset Value: 00h
Reset Value: 00h
Miscellaneous Device Control Register (R/W)
7
Floppy Drive Port Select. Indicates whether all system resources used to power manage the floppy drive use the primary,
or secondary FDC addresses for decode.
0: Secondary.
1: Primary.
6
5
Reserved. Must be set to 1.
Partial Primary Hard Disk Decode. This bit is used to restrict the addresses which are decoded as primary hard disk
accesses.
0: Power management monitors all reads and writes to I/O Port 1F0h-1F7h, 3F6h-3F7h (excludes writes to 3F7h), and
170h-177h, 376h-377h (excludes writes to 377h).
1: Power management monitors only writes to I/O Port 1F6h and 1F7h.
4
Partial Secondary Hard Disk Decode. This bit is used to restrict the addresses which are decoded as secondary hard disk
accesses.
0: Power management monitors all reads and writes to I/O Port 170h-177h, 376h-377h (excludes writes to 377h).
1: Power management monitors only writes to I/O Port 176h and 177h.
3:2
1
Reserved. Must be set to 0.
Mouse on Serial Enable. Mouse is present on a Serial Port.
0: No.
1: Yes.
If a mouse is attached to a serial port (i.e., this bit is set to 1), that port is removed from the serial device list being used to
monitor serial port access for power management purposes and added to the keyboard/mouse decode. This is done
because a mouse, along with the keyboard, is considered an input device and is used only to determine when to blank the
screen.
This bit and bit 0 of this register determine the decode used for the Keyboard/Mouse Idle Timer Count Register (F0 Index
9Eh) as well as the Parallel/Serial Port Idle Timer Count Register (F0 Index 9Ch).
0
Mouse Port Select. Selects which serial port the mouse is attached to.
0: COM1
1: COM2.
For more information see the description of bit 1 in this register (above).
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Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)
Bit
Description
Index 94h-95h
Suspend Modulation Register (R/W)
Reset Value: 0000h
15:8
7:0
Suspend Signal Asserted Counter. This 8-bit counter represents the number of 32 µs intervals that the internal SUSP#
signal is asserted to the GX1 module. Together with bits [7:0], perform the Suspend Modulation function for CPU power
management. The ratio of SUSP# asserted-to-de-asserted sets up an effective (emulated) clock frequency, allowing the
power manager to reduce GX1 module power consumption.
This counter is prematurely reset if an enabled speedup event occurs (i.e., IRQ and video speedups).
Suspend Signal De-asserted Counter. This 8-bit counter represents the number of 32 µs intervals that the internal SUSP#
signal is de-asserted to the GX1 module. Together with bits [15:8], perform the Suspend Modulation function for CPU power
management. The ratio of SUSP# asserted-to-de-asserted sets up an effective (emulated) clock frequency, allowing the
power manager to reduce GX1 module power consumption.
This counter is prematurely reset if an enabled speedup event occurs (i.e., IRQ and video speedups).
Index 96h
Suspend Configuration Register (R/W)
Reset Value: 00h
7:3
2
Reserved. Must be set to 0.
Suspend Mode Configuration. Special 3V Suspend mode to support powering down the GX1 module during Suspend.
0: Disable.
1: Enable.
1
SMI Speedup Configuration. Selects how the Suspend Modulation function should react when an SMI occurs.
0: Use the IRQ Speedup Timer Count Register (F0 Index 8Ch) to temporarily disable Suspend Modulation when an SMI
occurs.
1: Disable Suspend Modulation when an SMI occurs until a read to the SMI Speedup Disable Register (F1BAR0+I/O Offset
08h).
The purpose of this bit is to disable Suspend Modulation while the GX1 module is in the System Management Mode so that
VSA and Power Management operations occur at full speed. Two methods for accomplishing this are:
Map the SMI into the IRQ Speedup Timer Count Register (F0 Index 8Ch).
- or -
Have the SMI disable Suspend Modulation until the SMI handler reads the SMI Speedup Disable Register (F1BAR0+I/O
Offset 08h). This the preferred method.
This bit has no affect if the Suspend Modulation feature is disabled (bit 0 = 0).
0
Suspend Modulation Feature Enable. This bit is used to enable/disable the Suspend Modulation feature.
0: Disable.
1: Enable.
When enabled, the internal SUSP# signal is asserted and de-asserted for the durations programmed in the Suspend Modu-
lation register (F0 Index 94h).
The setting of this bit is mirrored in the Top Level PME/SMI Status register (F1BAR0+I/O Offset 00h/02h[15]. It is used by
the SMI handler to determine if the SMI Speedup Disable register (F1BAR0+I/O Offset 08h) must be cleared on exit.
Index 97h
Reserved
Reset Value: 00h
Index 98h-99h
Primary Hard Disk Idle Timer Count Register (Primary Channel) (R/W)
Reset Value: 0000h
15:0
Primary Hard Disk Idle Timer Count. This idle timer is used to determine when the primary hard disk is not in use so that
it can be powered down. The 16-bit value programmed here represents the period of hard disk inactivity after which the sys-
tem is alerted via an SMI. The timer is automatically reloaded with the count value whenever an access occurs to the config-
ured hard disk’s data port (I/O port 1F0h or 3F6h).
This counter uses a 1 second timebase. To enable this timer, set F0 Index 81h[0] = 1.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 85h/F5h[0].
Index 9Ah-9Bh
15:0
Floppy Disk Idle Timer Count Register (R/W)
Reset Value: 0000h
Floppy Disk Idle Timer Count. This idle timer is used to determine when the floppy disk drive is not in use so that it can be
powered down. The 16-bit value programmed here represents the period of floppy disk drive inactivity after which the sys-
tem is alerted via an SMI. The timer is automatically reloaded with the count value whenever an access occurs to the config-
ured floppy drive’s data port (I/O port 3F5h or 375h).
This counter uses a 1 second time base. To enable this timer, set F0 Index 81h[1] = 1.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 85h/F5h[1].
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Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)
Bit
Description
Index 9Ch-9Dh
15:0
Parallel / Serial Idle Timer Count Register (R/W)
Reset Value: 0000h
Parallel / Serial Idle Timer Count. This idle timer is used to determine when the parallel and serial ports are not in use so
that the ports can be power managed. The 16-bit value programmed in this register represents the period of inactivity for
these ports after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever
an access occurs to the parallel (LPT) or serial (COM) I/O address spaces. If the mouse is enabled on a serial port, that port
is not considered here.
This counter uses a 1 second timebase. To enable this timer, set F0 Index 81h[2] = 1.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 85h/F5h[2].
Index 9Eh-9Fh
15:0
Keyboard / Mouse Idle Timer Count Register (R/W)
Reset Value: 0000h
Keyboard / Mouse Idle Timer Count. This idle timer determines when the keyboard and mouse are not in use so that the
LCD screen can be blanked. The 16-bit value programmed in this register represents the period of inactivity for these ports
after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever an access
occurs to either the keyboard or mouse I/O address spaces (including the mouse serial port address space when a mouse
is enabled on a serial port.)
This counter uses a 1 second time base. To enable this timer, set F0 Index 81h[3] = 1.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 85h/F5h[3].
Index A0h-A1h
15:0
User Defined Device 1 Idle Timer Count Register (R/W)
Reset Value: 0000h
User Defined Device 1 (UDEF1) Idle Timer Count. This idle timer determines when the device configured as User Defined
Device 1 (UDEF1) is not in use so that it can be power managed. The 16-bit value programmed in this register represents
the period of inactivity for this device after which the system is alerted via an SMI. The timer is automatically reloaded with
the count value whenever an access occurs to memory or I/O address space configured in the F0 Index C0h (Base Address
register) and F0 Index CCh (Control register).
This counter uses a 1 second time base. To enable this timer, set F0 Index 81h[4] = 1.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 85h/F5h[4].
Index A2h-A3h
15:0
User Defined Device 2 Idle Timer Count Register (R/W)
Reset Value: 0000h
User Defined Device 2 (UDEF2) Idle Timer Count. This idle timer determines when the device configured as UDEF2 is not
in use so that it can be power managed. The 16-bit value programmed in this register represents the period of inactivity for
this device after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever
an access occurs to memory or I/O address space configured in the F0 Index C4h (Base Address register) and F0 Index
CDh (Control register).
This counter uses a 1 second timebase. To enable this timer, set F0 Index 81h[5] = 1.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 85h/F5h[5].
Index A4h-A5h
User Defined Device 3 Idle Timer Count Register (R/W)
Reset Value: 0000h
15:0
User Defined Device 3 (UDEF3) Idle Timer Count. This idle timer determines when the device configured as UDEF3 is not
in use so that it can be power managed. The 16-bit value programmed in this register represents the period of inactivity for
this device after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever
an access occurs to memory or I/O address space configured in the UDEF3 Base Address Register (F0 Index C8h) and
UDEF3 Control Register (F0 Index CEh).
This counter uses a 1 second timebase. To enable this timer, set F0 Index 81h[6] = 1.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 85h/F5h[6].
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Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)
Bit
Description
Index A6h-A7h
15:0
Video Idle Timer Count Register (R/W)
Reset Value: 0000h
Video Idle Timer Count. This idle timer determines when the graphics subsystem has been idle as part of the Suspend-
determination algorithm. The 16-bit value programmed in this register represents the period of video inactivity after which
the system is alerted via an SMI. The count in this timer is automatically reset at any access to the graphics controller
space.
This counter uses a 1 second timebase. To enable this timer, set F0 Index 81h[7] = 1.
Since the graphics controller is embedded in the GX1 module, video activity is communicated to the Core Logic module via
the serial connection (PSERIAL register, bit 0). The Core Logic module also detects accesses to standard VGA space on
PCI (3Bxh, 3Cxh, 3Dxh and A000h-B7FFh) if an external VGA controller is being used.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 85h/F5h[7].
Index A8h-A9h
15:0
Video Overflow Count Register (R/W)
Reset Value: 0000h
Video Overflow Count. Each time the video speedup counter is triggered, a 100 msec timer is started. If the 100 msec
timer expires before the video speedup counter lapses, the Video Overflow Count register increments and the 100 msec
timer retriggers. Software clears the overflow register when new evaluations are to begin. The count contained in this regis-
ter can be combined with other data to determine the type of video accesses present in the system.
Index AAh-ABh
Index ACh-ADh
Reserved
Reset Value: 00h
Secondary Hard Disk Idle Timer Count Register (R/W)
Reset Value: 0000h
15:0
Secondary Hard Disk Idle Timer Count. This idle timer is used to determine when the secondary hard disk is not in use so
that it can be powered down. The 16-bit value programmed in this register represents the period of hard disk inactivity after
which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever an access occurs
to the configured hard disk’s data port (I/O port 1F0h or 170h).
This counter uses a 1 second timebase. To enable this timer, set F0 Index 83h[7] = 1.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 86h/F6h[4].
Index AEh
CPU Suspend Command Register (WO)
Reset Value: 00h
7:0
Software CPU Suspend Command. If bit 0 in the Clock Stop Control register is set low (F0 Index BCh[0] = 0), a write to
this register causes an internal SUSP#/SUSPA# handshake with the GX1 module, placing the GX1 module in a low-power
state. The actual data written is irrelevant. Once in this state, any unmasked IRQ or SMI releases the GX1 module halt con-
dition.
If F0 Index BCh[0] = 1, writing to this register invokes a full system Suspend. In this case, the internal SUSP_3V signal is
asserted after the SUSP#/SUSPA# halt. Upon a Resume event, the PLL delay programmed in the F0 Index BCh[7:4] is
invoked, allowing the clock chip and GX1 module PLL to stabilize before de-asserting SUSP#.
Index AFh
Suspend Notebook Command Register (WO)
Reset Value: 00h
7:0
Software CPU Stop Clock Suspend. A write to this register causes a SUSP#/SUSPA# handshake with the CPU, placing
the GX1 module in a low-power state. Following this handshake, the SUSP_3V signal is asserted. The SUSP_3V signal is
intended to be used to stop all system clocks.
Upon a Resume event, the internal SUSP_3V signal is de-asserted. After a slight delay, the Core Logic module de-asserts
the SUSP# signal. Once the clocks are stable, the GX1 module de-asserts SUSPA# and system operation resumes.
Index B0h-B3h
Index B4h
Reserved
Reset Value: 00h
Reset Value: xxh
Floppy Port 3F2h Shadow Register (RO)
7:0
Floppy Port 3F2h Shadow. Last written value of I/O Port 3F2h. Required for support of FDC power On/Off and 0V Sus-
pend/Resume coherency.
This register is a copy of an I/O register which cannot safely be directly read. The value in this register is not deterministic of
when the register is being read. It is provided here to assist in a Suspend-to-Disk operation.
Index B5h
Floppy Port 3F7h Shadow Register (RO)
Reset Value: xxh
7:0
Floppy Port 3F7h Shadow. Last written value of I/O Port 3F7h. Required for support of FDC power On/Off and 0V Sus-
pend/Resume coherency.
This register is a copy of an I/O register which cannot safely be directly read. The value in this register is not deterministic of
when the register is being read. It is provided here to assist in a Suspend-to-Disk operation.
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Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)
Bit
Description
Index B6h
Floppy Port 372h Shadow Register (RO)
Reset Value: xxh
7:0
Floppy Port 372h Shadow. Last written value of I/O Port 372h. Required for support of FDC power On/Off and 0V Sus-
pend/Resume coherency.
This register is a copy of an I/O register which cannot safely be directly read. The value in this register is not deterministic of
when the register is being read. It is provided here to assist in a Suspend-to-Disk operation.
Index B7h
Floppy Port 377h Shadow Register (RO)
Reset Value: xxh
7:0
Floppy Port 377h Shadow. Last written value of I/O Port 377h. Required for support of FDC power On/Off and 0V Sus-
pend/Resume coherency.
This register is a copy of an I/O register which cannot safely be directly read. The value in this register is not deterministic of
when the register is being read. It is provided here to assist in a Suspend-to-Disk operation.
Index B8h
DMA Shadow Register (RO)
Reset Value: xxh
7:0
DMA Shadow. This 8-bit port sequences through the following list of shadowed DMA Controller registers. At power on, a
pointer starts at the first register in the list and continuing through the other registers in subsequent reads according to the
read sequence. A write to this register resets the read sequence to the first register. Each shadow register in the sequence
contains the last data written to that location.
The read sequence for this register is:
1. DMA Channel 0 Mode Register
2. DMA Channel 1 Mode Register
3. DMA Channel 2 Mode Register
4. DMA Channel 3 Mode Register
5. DMA Channel 4 Mode Register
6. DMA Channel 5 Mode Register
7. DMA Channel 6 Mode Register
8. DMA Channel 7 Mode Register
9. DMA Channel Mask Register (bit 0 is channel 0 mask, etc.)
10. DMA Busy Register (bit 0 or 1 means a DMA occurred within last 1 msec, all other bits are 0)
Index B9h
PIC Shadow Register (RO)
Reset Value: xxh
7:0
PIC Shadow. This 8-bit port sequences through the following list of shadowed Interrupt Controller registers. At power on, a
pointer starts at the first register in the list and continuing through the other registers in subsequent reads according to the
read sequence. A write to this register resets the read sequence to the first register. Each shadow register in the sequence
contains the last data written to that location.
The read sequence for this register is:
1. PIC1 ICW1
2. PIC1 ICW2
3. PIC1 ICW3
4. PIC1 ICW4 - Bits [7:5] of ICW4 are always 0.
5. PIC1 OCW2 - Bits [6:3] of OCW2 are always 0 (See Note).
6. PIC1 OCW3 - Bits [7:4] are 0 and bits [6:3] are 1.
7. PIC2 ICW1
8. PIC2 ICW2
9. PIC2 ICW3
10. PIC2 ICW4 - Bits [7:5] of ICW4 are always 0.
11. PIC2 OCW2 - Bits [6:3] of OCW2 are always 0 (See Note).
12. PIC2 OCW3 - Bits [7:4] are 0 and bits [6:3] are 1.
Note: To restore OCW2 to the shadow register value, write the appropriate address twice. First with the shadow register
value, then with the shadow register value ORed with C0h.
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Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)
Bit
Description
Index BAh
PIT Shadow Register (RO)
Reset Value: xxh
7:0
PIT Shadow. This 8-bit port sequences through the following list of shadowed Programmable Interval Timer registers. At
power on, a pointer starts at the first register in the list and continuing through the other registers in subsequent reads
according to the read sequence. A write to this register resets the read sequence to the first register. Each shadow register
in the sequence contains the last data written to that location.
The read sequence for this register is:
1. Counter 0 LSB (least significant byte)
2. Counter 0 MSB
3. Counter 1 LSB
4. Counter 1 MSB
5. Counter 2 LSB
6. Counter 2 MSB
7. Counter 0 Command Word
8. Counter 1 Command Word
9. Counter 2 Command Word
Note: The LSB/MSB of the count is the Counter base value, not the current value.
Bits [7:6] of the command words are not used.
Index BBh
7:0
RTC Index Shadow Register (RO)
RTC Index Shadow. The RTC Shadow register contains the last written value of the RTC Index register (I/O Port 070h).
Clock Stop Control Register (R/W) Reset Value: 00h
Reset Value: xxh
Index BCh
7:4
PLL Delay. The programmed value in this field sets the delay (in milliseconds) after a break event occurs before the internal
SUSP# signal is de-asserted to the GX1 module. This delay is designed to allow the clock chip and CPU PLL to stabilize
before starting execution. This delay is only invoked if the STP_CLK bit was set.
The 4-bit field allows values from 0 to 15 msec.
0000: 0 msec
0001: 1 msec
0010: 2 msec
0011: 3 msec
0100: 4 msec
0101: 5 msec
0110: 6 msec
0111: 7 msec
1000: 8 msec
1001: 9 msec
1010: 10 msec
1011: 11 msec
1100: 12 msec
1101: 13 msec
1110: 14 msec
1111: 15 msec
3:1
0
Reserved. Set to 0.
CPU Clock Stop.
0: Normal internal SUSP#/SUSPA# handshake.
1: Full system Suspend.
Note: This register configures the Core Logic module to support a 3V Suspend mode. Setting bit 0 causes the SUSP_3V signal to
assert after the appropriate conditions, stopping the system clocks. A delay of 0-15 msec is programmable (bits [7:4]) to allow
for a delay for the clock chip and CPU PLL to stabilize when an event Resumes the system.
A write to the CPU Suspend Command register (F0 Index AEh) with bit 0 written as:
0: Internal SUSP#/SUSPA# handshake occurs. The GX1 module is put into a low-power state, and the system clocks are not
stopped. When a break/resume event occurs, it releases the CPU halt condition.
1: Internal SUSP#/SUSPA# handshake occurs and the SUSP_3V signal is asserted, thus invoking a full system Suspend (both
GX1 module and system clocks are stopped). When a break event occurs, the SUSP_3V signal is de-asserted, the PLL delay
programmed in bits [7:4] are invoked which allows the clock chip and GX1 module PLL to stabilize before de-asserting the
internal SUSP# signal.
Index BDh-BFh
Index C0h-C3h
Reserved
Reset Value: 00h
User Defined Device 1 Base Address Register (R/W)
Reset Value: 00000000h
31:0
User Defined Device 1 Base Address. This 32-bit register supports power management (Trap and Idle timer resources)
for a PCMCIA slot or some other device in the system. The value in this register is used as the address comparator for the
device trap/timer logic. The device can be memory or I/O mapped (configured in F0 Index CCh).
The Core Logic module cannot snoop addresses on the Fast-PCI bus unless it actually claims the cycle. Therefore, Traps
and Idle timers cannot support power management of devices on the Fast-PCI bus.
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Core Logic Module (Continued)
Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)
Bit
Description
Index C4h-C7h
31:0
User Defined Device 2 Base Address Register (R/W)
Reset Value: 00000000h
User Defined Device 2 Base Address. This 32-bit register supports power management (Trap and Idle timer resources)
for a PCMCIA slot or some other device in the system. The value in this register is used as the address comparator for the
device trap/timer logic. The device can be memory or I/O mapped (configured in F0 Index CDh).
The Core Logic module cannot snoop addresses on the Fast-PCI bus unless it actually claims the cycle. Therefore, Traps
and Idle timers cannot support power management of devices on the Fast-PCI bus.
Index C8h-CBh
User Defined Device 3 Base Address Register (R/W)
Reset Value: 00000000h
31:0
User Defined Device 3 Base Address. This 32-bit register supports power management (Trap and Idle timer resources)
for a PCMCIA slot or some other device in the system. The value in this register is used as the address comparator for the
device trap/timer logic. The device can be memory or I/O mapped (configured in F0 Index CEh).
The Core Logic module cannot snoop addresses on the Fast-PCI bus unless the it actually claims the cycle. Therefore,
Traps and Idle timers cannot support power management of devices on the Fast-PCI bus.
Index CCh
User Defined Device 1 Control Register (R/W)
Reset Value: 00h
7
Memory or I/O Mapped. Determines how User Defined Device 1 is mapped.
0: I/O.
1: Memory.
Mask.
6:0
If bit 7 = 0 (I/O):
Bit 6
0: Disable write cycle tracking
1: Enable write cycle tracking
Bit 5
0: Disable read cycle tracking
1: Enable read cycle tracking
Bits [4:0] Mask for address bits A[4:0]
If bit 7 = 1 (Memory):
Bits [6:0] Mask for address memory bits A[15:9] (512 bytes min. and 64 KB max.) A[8:0] are ignored.
Note: A "1" in a mask bit means that the address bit is ignored for comparison.
Index CDh
User Defined Device 2 Control Register (R/W)
Reset Value: 00h
7
Memory or I/O Mapped. determines how User Defined Device 2 is mapped.
0: I/O
1: Memory
Mask.
6:0
If bit 7 = 0 (I/O):
Bit 6
0: Disable write cycle tracking
1: Enable write cycle tracking
Bit 5
0: Disable read cycle tracking
1: Enable read cycle tracking
Bits [4:0] Mask for address bits A[4:0]
If bit 7 = 1 (Memory):
Bits [6:0] Mask for address memory bits A[15:9] (512 bytes min. and 64 KB max.) A[8:0] are ignored.
Note: A "1" in a mask bit means that the address bit is ignored for comparison.
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Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)
Bit
Description
Index CEh
User Defined Device 3 Control Register (R/W)
Reset Value: 00h
7
Memory or I/O Mapped. Determines how User Defined Device 3 is mapped.
0: I/O.
1: Memory.
Mask.
6:0
If bit 7 = 0 (I/O):
Bit 6
0: Disable write cycle tracking
1: Enable write cycle tracking
Bit 5
0: Disable read cycle tracking
1: Enable read cycle tracking
Bits [4:0] Mask for address bits A[4:0]
If bit 7 = 1 (Memory):
Bits [6:0] Mask for address memory bits A[15:9] (512 bytes min. and 64 KB max.) A[8:0] are ignored.
Note: A "1" in a mask bit means that the address bit is ignored for comparison.
Index CFh
Reserved
Reset Value: 00h
Reset Value: 00h
Index D0h
Software SMI Register (WO)
7:0
Software SMI. A write to this location generates an SMI. The data written is irrelevant. This register allows software entry
into SMM via normal bus access instructions.
Index D1h-EBh
Index ECh
Reserved
Reset Value: 00h
Reset Value: 00h
Timer Test Register (R/W)
7:0
Timer Test Value. The Timer Test register is intended only for test and debug purposes. It is not intended for setting opera-
tional timebases. For normal operation, never write to this register.
Index EDh-F3h
Reserved
Reset Value: 00h
Reset Value: 00h
Index F4h
Second Level PME/SMI Status Register 1 (RC)
The bits in this register contain second level status reporting. Top level status is reported in F1BAR0+I/O Offset 00h/02h[0].
Reading this register clears the status at both the second and top levels.
A read-only “Mirror” version of this register exists at F0 Index 84h. If the value of the register must be read without clearing the SMI
source (and consequently de-asserting SMI), F0 Index 84h can be read instead.
7:3
2
Reserved. Reads as 0.
GPWIO2 SMI Status. Indicates whether or not an SMI was caused by a transition on the GPWIO2 pin.
0: No.
1: Yes.
To enable SMI generation:
1) Ensure that GPWIO2 is enabled as an input: F1BAR1+I/O Offset 15h[2] = 0.
2) Set F1BAR1+I/O Offset 15h[6] = 1 to allow SMI generation.
1
0
GPWIO1 SMI Status. Indicates whether or not an SMI was caused by a transition on the GPWIO1 pin.
0: No.
1: Yes.
To enable SMI generation:
1) Ensure that GPWIO1 is enabled as an input: F1BAR1+I/O Offset 15h[1] = 0.
2) Set F1BAR1+I/O Offset 15h[5] to 1 to allow SMI generation.
GPWIO0 SMI Status. Indicates whether or not an SMI was caused by a transition on the GPWIO0 pin.
0: No
1: Yes
To enable SMI generation:
1) Ensure that GPWIO0 is enabled as an input: F1BAR1+I/O Offset 15h[0] = 0.
2) Set F1BAR1+I/O Offset 15h[4] to 1 to allow SMI generation.
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Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)
Bit
Description
Index F5h
Second Level PME/SMI Status Register 2 (RC)
Reset Value: 00h
The bits in this register contain second level status reporting. Top level status is reported in F1BAR0+I/O Offset 00h/02h[0].
Reading this register clears the status at both the second and top levels.
A read-only “Mirror” version of this register exists at F0 Index 85h. If the value of the register must be read without clearing the SMI
source (and consequently de-asserting SMI), F0 Index 85h can be read instead.
7
6
5
4
3
2
1
0
Video Idle Timer SMI Status. Indicates whether or not an SMI was caused by expiration of Video Idle Timer Count Regis-
ter, (F0 Index A6h).
0: No.
1: Yes.
To enable SMI generation, set F0 Index 81h[7] = 1.
User Defined Device Idle Timer 3 (UDEF3) SMI Status. Indicates whether or not an SMI was caused by expiration of User
Defined Device 3 (UDEF3) Idle Timer Count Register (F0 Index A4h).
0: No.
1: Yes.
To enable SMI generation, set F0 Index 81h[6] = 1.
User Defined Device Idle Timer 2 (UDEF2) SMI Status. Indicates whether or not an SMI was caused by expiration of User
Defined Device 2 (UDEF2) Idle Timer Count Register (F0 Index A2h).
0: No.
1: Yes.
To enable SMI generation, set F0 Index 81h[5] = 1.
User Defined Device Idle Timer 1 (UDEF1) SMI Status. Indicates whether or not an SMI was caused by expiration of User
Defined Device 1 (UDEF1) Idle Timer Count Register (F0 Index A0h).
0: No.
1: Yes.
To enable SMI generation, set F0 Index 81h[4] = 1.
Keyboard/Mouse Idle Timer SMI Status. Indicates whether or not an SMI was caused by expiration of Keyboard/ Mouse
Idle Timer Count Register (F0 Index 9Eh).
0: No.
1: Yes.
To enable SMI generation, set F0 Index 81h[3] = 1.
Parallel/Serial Idle Timer SMI Status. Indicates whether or not an SMI was caused by expiration of Parallel/Serial Port Idle
Timer Count Register (F0 Index 9Ch).
0: No.
1: Yes.
To enable SMI generation, set F0 Index 81h[2] = 1.
Floppy Disk Idle Timer SMI Status. Indicates whether or not an SMI was caused by expiration of Floppy Disk Idle Timer
Count Register (F0 Index 9Ah).
0: No.
1: Yes.
To enable SMI generation, set F0 Index 81h[1] = 1.
Hard Disk Idle Timer SMI Status. Indicates whether or not an SMI was caused by expiration of Hard Disk Idle Timer Count
Register (F0 Index 98h).
0: No.
1: Yes.
To enable SMI generation, set F0 Index 81h[0] = 1.
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Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)
Bit
Description
Index F6h
Second Level PME/SMI Status Register 3 (RC)
Reset Value: 00h
The bits in this register contain second level status reporting. Top level status is reported in F1BAR0+I/O Offset 00h/02h[0].
Reading this register clears the status at both the second and top levels.
A read-only “Mirror” version of this register exists at F0 Index 86h. If the value of the register must be read without clearing the SMI
source (and consequently de-asserting SMI), F0 Index 86h can be read instead.
7
Video Access Trap SMI Status. Indicates whether or not an SMI was caused by a trapped I/O access to the Video I/O
Trap.
0: No.
1: Yes.
To enable SMI generation, set F0 Index 82h[7] = 1.
Reserved. Reads as 0.
6
5
Secondary Hard Disk Access Trap SMI Status. Indicates whether or not an SMI was caused by a trapped I/O access to
the secondary hard disk.
0: No.
1: Yes.
To enable SMI generation, set F0 Index 83h[6] = 1.
4
3
2
1
0
Secondary Hard Disk Idle Timer SMI Status. Indicates whether or not an SMI was caused by expiration of Secondary
Hard Disk Idle Timer Count register (F0 Index ACh).
0: No.
1: Yes.
To enable SMI generation, set F0 Index 83h[7] = 1.
Keyboard/Mouse Access Trap SMI Status. Indicates whether or not an SMI was caused by a trapped I/O access to the
keyboard or mouse.
0: No.
1: Yes.
To enable SMI generation, set F0 Index 82h[3] = 1.
Parallel/Serial Access Trap SMI Status. Indicates whether or not an SMI was caused by a trapped I/O access to either the
serial or parallel ports.
0: No.
1: Yes.
To enable SMI generation, set F0 Index 82h[2] =1.
Floppy Disk Access Trap SMI Status. Indicates whether or not an SMI was caused by a trapped I/O access to the floppy
disk.
0: No.
1: Yes.
To enable SMI generation, set F0 Index 82h[1] = 1.
Primary Hard Disk Access Trap SMI Status. Indicates whether or not an SMI was caused by a trapped I/O access to the
primary hard disk.
0: No.
1: Yes.
To enable SMI generation, set F0 Index 82h[0] = 1.
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Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)
Bit
Description
Index F7h
Second Level PME/SMI Status Register 4 (RC)
Reset Value: 00h
The bits in this register contain second level status reporting. Top level status is reported in F1BAR0+I/O Offset 00h/02h[0].
Reading this register clears the status at both the second and top levels except for bit 7 which has a third level of status reporting at
F0BAR0+I/O 0Ch/1Ch.
A read-only “Mirror” version of this register exists at F0 Index 87h. If the value of the register must be read without clearing the SMI
source (and consequently de-asserting SMI), F0 Index 87h can be read instead.
7
GPIO Event SMI Status (Read Only, Read does not Clear). Indicates whether or not an SMI was caused by a transition of
any of the GPIOs (GPIO47-GPIO32 and GPIO15-GPIO0).
0: No.
1: Yes.
To enable SMI generation, set F1BAR1+I/O Offset 0Ch[0] = 0.
F0BAR0+I/O Offset 08h/18h selects which GPIOs are enabled to generate a PME and setting F1BAR1+I/O Offset 0Ch[0] =
0 enables the PME to generate an SMI. In addition, the selected GPIO must be enabled as an input (F0BAR0+I/O Offset
20h and 24h).
The next level (third level) of SMI status is at F0BAR0+I/O 0Ch/1Ch.
6
Thermal Override SMI Status. Indicates whether or not an SMI was caused by an assertion of the THRM#.
0: No.
1: Yes.
To enable SMI generation set F0 Index 83h[4] = 1.
5:4
3
Reserved. Read as 0.
SIO PWUREQ SMI Status. Indicates whether or not an SMI was caused by a power-up event from the SIO.
0: No.
1: Yes.
A power-up event is defined as any of the following events/activities:
— RI2#
— SDATA_IN2
— IRRX1 (CEIR)
To enable SMI generation, set F1BAR1+I/O Offset 0Ch[0] = 0.
2
Codec SDATA_IN SMI Status. Indicates whether or not an SMI was caused by AC97 Codec producing a positive edge on
SDATA_IN.
0: No.
1: Yes.
To enable SMI generation, set F0 Index 80h[5] = 1.
1
0
RTC Alarm (IRQ8#) SMI Status. Indicates whether or not an SMI was caused by an RTC interrupt.
0: No.
1: Yes.
This SMI event can only occur while in 3V Suspend and an RTC interrupt occurs and F1BAR1+I/O Offset 0Ch[0] = 0.
ACPI Timer SMI Status. Indicates whether or not an SMI was caused by an ACPI Timer (F1BAR0+I/O Offset 1Ch or
F1BAR1+I/O Offset 1Ch) MSB toggle.
0: No.
1: Yes.
To enable SMI generation, set F0 Index 83h[5] = 1.
Index F8h-FFh
Reserved
Reset Value: 00h
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5.4.1.1 GPIO Support Registers
F0 Index 10h, Base Address Register 0 (F0BAR0) points to
the base address of where the GPIO runtime and configu-
ration registers are located. Table 5-29 gives the bit formats
of I/O mapped registers accessed through F0BAR0.
Table 5-30. F0BAR0+I/O Offset: GPIO Configuration Registers
Bit
Description
Offset 00h-03h
31:0
GPDO0 — GPIO Data Out 0 Register (R/W)
Reset Value: FFFFFFFFh
GPIO Data Out. Bits [31:0] of this register correspond to GPIO31-GPIO0 signals, respectively. The value of each bit deter-
mines the value driven on the corresponding GPIO signal when its output buffer is enabled. Writing to the bit latches the
written data unless the bit is locked by the GPIO Configuration register Lock bit (F0BAR0+I/O Offset 24h[3]). Reading the
bit returns the value, regardless of the signal value and configuration.
0: Corresponding GPIO signal is driven to low when output enabled.
1: Corresponding GPIO signal is driven or released to high (according to buffer type and static pull-up selection) when out-
put is enabled.
Offset 04h-07h
31:0
GPDI0 — GPIO Data In 0 Register (RO)
Reset Value: FFFFFFFFh
GPIO Data In. Bits [31:0] of this register correspond to GPIO31-GPIO0 signals, respectively. Reading each bit returns the
value of the corresponding GPIO signal, regardless of the signal configuration and the GPDO0 register (F0BAR0+I/O Offset
00h) value.
Writes to this register are ignored.
0: Corresponding GPIO signal level is low.
1: Corresponding GPIO signal level is high.
Offset 08h-0Bh
GPIEN0 — GPIO Interrupt Enable 0 Register (R/W)
Reset Value: 00000000h
31:16
15:0
Reserved. Must be set to 0.
GPIO Power Management Event (PME) Enable. Bits [15:0] correspond to GPIO15-GPIO0 signals, respectively. Each bit
allows PME generation by the corresponding GPIO signal.
0: Disable PME generation.
1: Enable PME generation.
Notes: 1) All of the enabled GPIO PMEs are always reported at F1BAR1+I/O Offset 10h[3].
2) Any enabled GPIO PME can be selected to generate an SCI or SMI at F1BAR1+I/O Offset 0Ch[0].
If SCI is selected, then the individually selected GPIO PMEs are globally enabled for SCI generation at
F1BAR1+I/O Offset 12h[3] and the status is reported at F1BAR1+I/O Offset 10h[3].
If SMI is selected, the individually selected GPIO PMEs generate an SMI and the status is reported at
F1BAR0+I/O Offset 00h/02h[0].
Offset 0Ch-0Fh
GPST0 — GPIO Status 0 Register (R/W1C)
Reset Value: 00000000h
31:16
15:0
Reserved. Must be set to 0.
GPIO Status. Bits [15:0] correspond to GPIO15-GPIO0 signals, respectively. Each bit reports a 1 when hardware detects
the edge (rising/falling on the GPIO signal) that is programmed in F0BAR0+I/O Offset 24h[5]. If the corresponding bit in
F0BAR0+I/O Offset 08h is set, this edge generates a PME.
0: No active edge detected since the bit was last cleared.
1: Active edge detected.
Writing 1 to the a Status bit clears it to 0.
This is the third level of SMI status reporting to the second level at F0 Index 87h/F7h[7] and the top level at F1BAR0+I/O
Offset 00h/02h[0]. Clearing the third level also clears the second and top levels.
This is the second level of SCI status reporting to the top level at F1BAR1+Offset 10h[3]. The status must be cleared at
both the this level and the top level (i.e., the top level is not automatically cleared when a bit in this register is cleared).
Offset 10h-13h
31:0
GPDO1 — GPIO Data Out 1 Register (R/W)
Reset Value: FFFFFFFFh
GPIO Data Out. Bits [31:0] of this register correspond to GPIO63-GPIO32 signals, respectively. The value of each bit deter-
mines the value driven on the corresponding GPIO signal when its output buffer is enabled. Writing to the bit latches the
written data unless the bit is locked by the GPIO Configuration register Lock bit (F0BAR0+I/O Offset 24h[3]). Reading the
bit returns the value, regardless of the signal value and configuration.
0: Corresponding GPIO signal driven to low when output enabled.
1: Corresponding GPIO signal driven or released to high (according to buffer type and static pull-up selection) when output
enabled.
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Table 5-30. F0BAR0+I/O Offset: GPIO Configuration Registers (Continued)
Bit
Description
Offset 14h-17h
GPDI1 — GPIO Data In 1 Register (RO)
Reset Value: FFFFFFFFh
31:0
GPIO Data In. Bits [31:0] of this register correspond to GPIO63-GPIO32 signals, respectively. Reading each bit returns the
value of the corresponding GPIO signal, regardless of the signal configuration and the GPDO1 register (F0BAR0+I/O Offset
10h) value. Writes to this register are ignored.
0: Corresponding GPIO signal level low.
1: Corresponding GPIO signal level high.
Offset 18h-1Bh
GPIEN1 — GPIO Interrupt Enable 1 Register (R/W)
Reset Value: 00000000h
31:16
15:0
Reserved. Must be set to 0.
GPIO Power Management Event (PME) Enable. Bits [15:0] of this register correspond to GPIO47-GPIO32 signals,
respectively. Each bit allows PME generation by the corresponding GPIO signal.
0: Disable PME generation.
1: Enable PME generation.
Notes: 1) All of the enabled GPIO PMEs are always reported at F1BAR1+I/O Offset 10h[3].
2) Any enabled GPIO PME can be selected to generate an SCI or SMI at F1BAR1+I/O Offset 0Ch[0].
If SCI is selected, the individually selected GPIO PMEs are globally enabled for SCI generation at
F1BAR1+I/O Offset 12h[3] and the status is reported at F1BAR1+I/O Offset 10h[3].
If SMI is selected, the individually selected GPIO PMEs generate an SMI and the status is reported at
F1BAR0+I/O Offset 00h/02h[0].
Offset 1Ch-1Fh
GPST1 — GPIO Status 1 Register (R/W1C)
Reset Value: 00000000h
31:16
15:0
Reserved. Must be set to 0.
GPIO Status. Bits [15:0] correspond to GPIO47-GPIO32 signals, respectively. Each bit reports a 1 when hardware detects
the edge (rising/falling on the GPIO signal) that is programmed in F0BAR0+I/O Offset 24h[5]. If the corresponding bit in
F0BAR0+I/O Offset 18h is set, this edge generates a PME.
0: No active edge detected since the bit was last cleared.
1: Active edge detected.
Writing 1 to the a Status bit clears it to 0.
This is the third level of SMI status reporting to the second level at F0 Index 87h/F7h[7] and the top level at F1BAR0+I/O
Offset 00h/02h[0]. Clearing the third level also clears the second and top levels.
This is the second level of SCI status reporting to the top level at F1BAR1+Offset 10h[3]. The status must be cleared at
both the this level and the top level (i.e., the top level is not automatically cleared when a bit in this register is cleared).
Offset 20h-23h
GPIO Signal Configuration Select Register (R/W)
Reset Value: 00000000h
31:6
Reserved. Must be set to 0.
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Table 5-30. F0BAR0+I/O Offset: GPIO Configuration Registers (Continued)
Bit
Description
5:0
Signal Select. Selects the GPIO signal to be configured in the Bank selected via bit 5 setting (i.e., Bank 0 or Bank 1). See
Table 3-2 "Multiplexing, Interrupt Selection, and Base Address Registers" on page 86 for GPIO ball muxing options. GPIOs
without an associated ball number are not available externally.
Bank 0
000000 = GPIO0 (EBGA: H1 / TEPBGA: D11)
010000 = GPIO16 (EBGA: AL15 / TEPBGA: V31)
000001 = GPIO1 (EBGA: H2, AL12 / TEPBGA: D10, N30) 010001 = GPIO17 (EBGA: J4 / TEPBGA: A10)
000010 = GPIO2
000011 = GPIO3
000100 = GPIO4
000101 = GPIO5
010010 = GPIO18 (EBGA: A28 / TEPBGA: AG1)
010011 = GPIO19 (EBGA: H4 / TEPBGA: C9)
010100 = GPIO20 (EBGA: H3, AJ13 / TEPBGA: A9, N31)
010101 = GPIO21
000110 = GPIO6 (EBGA: AH3 / TEPBGA: D28)
000111 = GPIO7 (EBGA: AH4 / TEPBGA: C30)
001000 = GPIO8 (EBGA: AJ2 / TEPBGA: C31)
001001 = GPIO9 (EBGA: AG4 / TEPBGA: C28)
001010 = GPIO10 (EBGA: AJ1 / TEPBGA: B29)
001011 = GPIO11 (EBGA: H30 / TEPBGA: AJ8)
001100 = GPIO12 (EBGA: AJ12 / TEPBGA: N29)
001101 = GPIO13 (EBGA: AL11 / TEPBGA: M29)
001110 = GPIO14 (EBGA: F1 / TEPBGA: D9)
001111 = GPIO15 (EBGA: G3 / TEPBGA: A8)
010110 = GPIO22
010111 = GPIO23
011000 = GPIO24
011001 = GPIO25
011010 = GPIO26
011011 = GPIO27
011100 = GPIO28
011101 = GPIO29
011110 = GPIO30
011111 = GPIO31
Bank 1
100000 = GPIO32 (EBGA: AJ11 / TEPBGA: M28)
100001 = GPIO33 (EBGA: AL10 / TEPBGA: L31)
100010 = GPIO34 (EBGA: AK10 / TEPBGA: L30)
100011 = GPIO35 (EBGA: AJ10 / TEPBGA: L29)
100100 = GPIO36 (EBGA: AL9 / TEPBGA: L28)
100101 = GPIO37 (EBGA: AK9 / TEPBGA: K31)
100110 = GPIO38 (EBGA: AJ9 / TEPBGA: K28)
100111 = GPIO39 (EBGA: AL8 / TEPBGA: J31)
101000 = GPIO40 (EBGA: A21 / TEPBGA: Y3)
101001 = GPIO41 (EBGA: C19 / TEPBGA: W4)
101010 = GPIO42
110000 = GPIO48
110001 = GPIO49
110010 = GPIO50
110011 = GPIO51
110100 = GPIO52
110101 = GPIO53
110110 = GPIO54
110111 = GPIO55
111000 = GPIO56
111001 = GPIO57
111010 = GPIO58
111011 = GPIO59
111100 = GPIO60
111101 = GPIO61
111110 = GPIO62
111111 = GPIO63 (Note)
101011 = GPIO43
101100 = GPIO44
101101 = GPIO45
101110 = GPIO46
101111 = GPIO47
Note:
GPIO63 can be used to generate the PWRBTN# input signal. See PWRBTN# signal description in Section 2.4.16
"Power Management Interface Signals" on page 78.
Offset 24h-27h
GPIO Signal Configuration Access Register (R/W)
Reset Value: 00000044h
This register is used to indicate configuration for the GPIO signal that is selected in the GPIO Signal Configuration Select Register
(above).
Note: PME debouncing, polarity, and edge/level configuration is only applicable on GPIO0-GPIO15 signals (Bank 0 = 00000 to
01111) and on GPIO32-GPIO47 signals (Bank 1 settings of 00000 to 01111). The remaining GPIOs (GPIO16-GPIO31 and
GPIO48-GPIO63) can not generate PMEs, therefore these bits have no function and read 0.
31:7
6
Reserved. Must be set to 0.
PME Debounce Enable. Enables/disables IRQ debounce (debounce period = 16 ms).
0: Disable.
1: Enable. (Default).
See the note in the description of this register for more information about the default value of this bit.
PME Polarity. Selects the polarity of the signal that issues a PME from the selected GPIO signal (falling/low or rising/high).
0: Falling edge or low level input. (Default)
5
1: Rising edge or high level input.
See the note in the description of this register for more information about the default value of this bit.
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Table 5-30. F0BAR0+I/O Offset: GPIO Configuration Registers (Continued)
Bit
Description
4
PME Edge/Level Select. Selects the type (edge or level) of the signal that issues a PME from the selected GPIO signal.
0: Edge input. (Default)
1: Level input.
For normal operation, always set this bit to 0 (edge input). Erratic system behavior results if this bit is set to 1.
See the note in the description of this register for more information about the default value of this bit.
3
2
Lock. This bit locks the selected GPIO signal. Once this bit is set to 1 by software, it can only be cleared to 0 by power on
reset or by WATCHDOG reset.
0: No effect. (Default)
1: Direction, output type, pull-up and output value locked.
Pull-Up Control. Enables/disables the internal pull-up capability of the selected GPIO signal. It supports open-drain output
signals with internal pull-ups and TTL input signals.
0: Disable.
1: Enable. (Default)
Bits [1:0] of this register must = 01 for this bit to have effect.
Output Type. Controls the output buffer type (open-drain or push-pull) of the selected GPIO signal.
0: Open-drain. (Default)
1
0
1: Push-pull.
Bit 0 of this register must be set to 1 for this bit to have effect.
Output Enable. Indicates the GPIO signal output state. It has no effect on input.
0: TRI-STATE - Setting for GPIO to function as an input only. (Default)
1: Output enabled.
Offset 28h-2Bh
GPIO Reset Control Register (R/W)
Reset Value: 00000000h
31:1
0
Reserved. Must be set to 0.
GPIO Reset. Reset the GPIO logic.
0: Disable.
1: Enable.
Write 0 to clear.
This bit is level-sensitive and must be cleared after the reset is enabled (normal operation requires this bit to be 0).
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5.4.1.2 LPC Support Registers
The LPC Interface supports all features described in the
LPC bus specification 1.0, with the following exceptions:
F0 Index 14h, Base Address Register 1 (F0BAR1) points to
the base address of the register space that contains the
configuration registers for LPC support. Table 5-31 gives
the bit formats of the I/O mapped registers accessed
through F0BAR1.
• Only 8- or 16-bit DMA, depending on channel number.
Does not support the optional larger transfer sizes.
• Only one external DRQ pin.
Table 5-31. F0BAR1+I/O Offset: LPC Interface Configuration Registers
Bit
Description
Offset 00h-03h
SERIRQ_SRC — Serial IRQ Source Register (R/W)
Reset Value: 00000000h
31:21
20
Reserved.
INTD Source. Selects the interface source of the INTD# signal.
0: PCI - INTD#. (Program PMR[24] = 1 to enable INTD# function on ball.)
1: LPC - SERIRQ. (Program PMR[14] = 1 and PMR[22] = 1 or LPC_ROM strap = 1 to enable SERIRQ function on ball.)
INTC Source. Selects the interface source of the INTC# signal.
19
18
17
0: PCI - INTC#. (Program PMR[4] =1 and PMR[9] = 0 to enable INTD# function on ball.
1: LPC - SERIRQ. (Program PMR[14] = 1 and PMR[22] = 1 or LPC_ROM strap = 1 to enable SERIRQ function on ball.)
INTB Source. Selects the interface source of the INTB# signal.
0: PCI - INTB#.
1: LPC - SERIRQ. (Program PMR[14] = 1 and PMR[22] = 1 or LPC_ROM strap = 1 to enable SERIRQ function on ball.)
INTA Source. Selects the interface source of the INTA# signal.
0: PCI - INTA#.
1: LPC - SERIRQ. (Program PMR[14] = 1 and PMR[22] = 1 or LPC_ROM strap = 1 to enable SERIRQ function on ball.)
Reserved. Set to 0.
16
15
IRQ15 Source. Selects the interface source of the IRQ15 signal.
0: ISA - IRQ15. (Program PMR[18] = 0 and PMR[8] = 1 to enable IRQ15 function on ball.)
1: LPC - SERIRQ. (Program PMR[14] = 1 and PMR[22] = 1 or LPC_ROM strap = 1 to enable SERIRQ function on ball.)
IRQ14 Source. Selects the interface source of the IRQ14 signal.
14
13
0: ISA - IRQ14. (Program PMR[24] = 0 to enable IRQ14 function on ball.)
1: LPC - SERIRQ. (Program PMR[14] = 1 and PMR[22] = 1 or LPC_ROM strap = 1 to enable SERIRQ function on ball.)
IRQ13 Source. Selects the interface source of the internal IRQ13 signal.
0: ISA - IRQ13. (Internal signal - An input from the CPU indicating that a floating point error has been detected and that
internal INTR should be asserted.)
1: LPC - SERIRQ. (Program PMR[14] = 1 and PMR[22] = 1 or LPC_ROM strap = 1 to enable SERIRQ function on ball.)
IRQ12 Source. Selects the interface source of the IRQ12 signal.
12
11
10
9
0: ISA - IRQ12. (Unavailable externally.)
1: LPC - SERIRQ (Program PMR[14] = 1 and PMR[22] = 1 or LPC_ROM strap = 1 to enable SERIRQ function on ball.)
IRQ11 Source. Selects the interface source of the IRQ11 signal.
0: ISA - IRQ11 (Unavailable externally.)
1: LPC - SERIRQ (Program PMR[14] = 1 and PMR[22] = 1 or LPC_ROM strap = 1 to enable SERIRQ function on ball.)
IRQ10 Source. Selects the interface source of the IRQ10 signal.
0: ISA - IRQ10. (Unavailable externally.)
1: LPC - SERIRQ. (Program PMR[14] = 1 and PMR[22] = 1 or LPC_ROM strap = 1 to enable SERIRQ function on ball.)
IRQ9 Source. Selects the interface source of the IRQ9 signal.
0: ISA - IRQ9. (Program PMR[24] = 1.)
1: LPC - SERIRQ. (Program PMR[14] = 1 and PMR[22] = 1 or LPC_ROM strap = 1 to enable SERIRQ function on ball.)
IRQ8# Source. Selects the interface source of the IRQ8# signal.
8
0: ISA - IRQ8# (Internal signal - Connected to internal RTC.)
1: LPC - SERIRQ (Program PMR[14] = 1 and PMR[22] = 1 or LPC_ROM strap = 1 to enable SERIRQ function on ball.)
IRQ7 Source. Selects the interface source of the IRQ7 signal.
7
0: ISA - IRQ7. (Unavailable externally.)
1: LPC - SERIRQ. (Program PMR[14] = 1 and PMR[22] = 1 or LPC_ROM strap = 1 to enable SERIRQ function on ball.)
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Table 5-31. F0BAR1+I/O Offset: LPC Interface Configuration Registers (Continued)
Bit
Description
6
IRQ6 Source. Selects the interface source of the IRQ6 signal.
0: ISA - IRQ6. (Unavailable externally.)
1: LPC - SERIRQ. (Program PMR[14] = 1 and PMR[22] = 1 or LPC_ROM strap = 1 to enable SERIRQ function on ball.)
IRQ5 Source. Selects the interface source of the IRQ5 signal.
5
4
3
0: ISA - IRQ5. (Unavailable externally.)
1: LPC - SERIRQ. (Program PMR[14] = 1 and PMR[22] = 1 or LPC_ROM strap = 1 to enable SERIRQ function on ball.)
IRQ4 Source. Selects the interface source of the IRQ4 signal.
0: ISA - IRQ4. (Unavailable externally.)
1: LPC - SERIRQ. (Program PMR[14] = 1 and PMR[22] = 1 or LPC_ROM strap = 1 to enable SERIRQ function on ball.)
IRQ3 Source. Selects the interface source of the IRQ3 signal.
0: ISA - IRQ3. (Unavailable externally.)
1: LPC - SERIRQ. (Program PMR[14] = 1 and PMR[22] = 1 or LPC_ROM strap = 1 to enable SERIRQ function on ball.)
Reserved. Must be set to 0.
2
1
IRQ1 Source. Selects the interface source of the IRQ1 signal.
0: ISA - IRQ1. (Unavailable externally.)
1: LPC - SERIRQ. (Program PMR[14] = 1 and PMR[22] = 1 or LPC_ROM strap = 1 to enable SERIRQ function on ball.)
IRQ0 Source. Selects the interface source of the IRQ0 signal.
0
0: ISA - IRQ0 (Internal signal - Connected to OUT0, System Timer, of the internal 8254 PIT.)
1: LPC - SERIRQ. (Program PMR[14] = 1 and PMR[22] = 1 or LPC_ROM strap = 1 to enable SERIRQ function on ball.)
Offset 04h-07h
SERIRQ_LVL — Serial IRQ Level Control Register (R/W)
Reset Value: 00000000h
31:21
20
Reserved
INTD# Polarity. If LPC is selected as the interface source for INTD# (F0BAR1+I/O Offset 00h[20] = 1), this bit allows signal
polarity selection.
0: Active high.
1: Active low.
19
INTC# Polarity. If LPC is selected as the interface source for INTC# (F0BAR1+I/O Offset 00h[19] = 1), this bit allows signal
polarity selection.
0: Active high.
1: Active low.
18
17
INTB# Polarity. If LPC is selected as the interface source for INTB# (F0BAR1+I/O Offset 00h[18] = 1), this bit allows signal
polarity selection.
0: Active high.
1: Active low.
INTA# Polarity. If LPC is selected as the interface source for INTA# (F0BAR1+I/O Offset 00h[17] = 1), this bit allows signal
polarity selection.
0: Active high.
1: Active low.
16
15
Reserved. Must be set to 0.
IRQ15 Polarity. If LPC is selected as the interface source for IRQ15 (F0BAR1+I/O Offset 00h[15] = 1), this bit allows signal
polarity selection.
0: Active high.
1: Active low.
14
13
IRQ14 Polarity. If LPC is selected as the interface source for IRQ14 (F0BAR1+I/O Offset 00h[14] = 1), this bit allows signal
polarity selection.
0: Active high.
1: Active low.
IRQ13 Polarity. If LPC is selected as the interface source for IRQ13 (F0BAR1+I/O Offset 00h[13] = 1), this bit allows signal
polarity selection.
0: Active high.
1: Active low.
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Core Logic Module (Continued)
Table 5-31. F0BAR1+I/O Offset: LPC Interface Configuration Registers (Continued)
Bit
Description
12
IRQ12 Polarity. If LPC is selected as the interface source for IRQ12 (F0BAR1+I/O Offset 00h[12] = 1), this bit allows signal
polarity selection.
0: Active high.
1: Active low.
11
10
9
IRQ11 Polarity. If LPC is selected as the interface source for IRQ11 (F0BAR1+I/O Offset 00h[11] = 1), this bit allows signal
polarity selection.
0: Active high.
1: Active low.
IRQ10 Polarity. If LPC is selected as the interface source for IRQ10 (F0BAR1+I/O Offset 00h[10] = 1), this bit allows signal
polarity selection.
0: Active high.
1: Active low.
IRQ9 Polarity. If LPC is selected as the interface source for IRQ9 (F0BAR1+I/O Offset 00h[9] = 1), this bit allows signal
polarity selection.
0: Active high.
1: Active low.
8
IRQ8# Polarity. If LPC is selected as the interface source for IRQ8# (F0BAR1+I/O Offset 00h[8] = 1), this bit allows signal
polarity selection.
0: Active high.
1: Active low.
7
IRQ7 Polarity. If LPC is selected as the interface source for IRQ7 (F0BAR1+I/O Offset 00h[7] = 1), this bit allows signal
polarity selection.
0: Active high.
1: Active low.
6
IRQ6 Polarity. If LPC is selected as the interface source for IRQ6 (F0BAR1+I/O Offset 00h[6] = 1), this bit allows signal
polarity selection.
0: Active high.
1: Active low.
5
IRQ5 Polarity. If LPC is selected as the interface source for IRQ5 (F0BAR1+I/O Offset 00h[5] = 1), this bit allows signal
polarity selection.
0: Active high.
1: Active low.
4
IRQ4 Polarity. If LPC is selected as the interface source for IRQ4 (F0BAR1+I/O Offset 00h[4] = 1), this bit allows signal
polarity selection.
0: Active high.
1: Active low.
3
IRQ3 Polarity. If LPC is selected as the interface source for IRQ3 (F0BAR1+I/O Offset 00h[3] = 1), this bit allows signal
polarity selection.
0: Active high.
1: Active low.
2
1
SMI# Polarity. This bit allows signal polarity selection of the SMI# generated from LPC.
0: Active high.
1: Active low.
IRQ1 Polarity. If LPC is selected as the interface source for IRQ1 (F0BAR1+I/O Offset 00h[1] = 1), this bit allows signal
polarity selection.
0: Active high.
1: Active low.
0
IRQ0 Polarity. If LPC is selected as the interface source for IRQ0 (F0BAR1+I/O Offset 00h[0] = 1), this bit allows signal
polarity selection.
0: Active high.
1: Active low.
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Table 5-31. F0BAR1+I/O Offset: LPC Interface Configuration Registers (Continued)
Bit
Description
Offset 08h-0Bh
SERIRQ_CNT — Serial IRQ Control Register (R/W)
Reset Value: 00000000h
31:8
7
Reserved.
Serial IRQ Enable.
0: Disable.
1: Enable.
6
Serial IRQ Interface Mode.
0: Continuous.
1: Quiet.
5:2
Number of IRQ Data Frames.
0000: 17 frames
0001: 18 frames
0010: 19 frames
0011: 20 frames
0100: 21 frames
0101: 22 frames
0110: 23 frames
0111: 24 frames
1000: 25 frames
1001: 26 frames
1010: 27 frames
1011: 28 frames
1100: 29 frames
1101: 30 frames
1110: 31 frames
1111: 32 frames
1:0
Start Frame Pulse Width.
00: 4 Clocks
01: 6 Clocks
10: 8 Clocks
11: Reserved
Offset 0Ch-0Fh
DRQ_SRC — DRQ Source Register (R/W)
Reset Value: 00000000h
DRQx are internal signals between the Core Logic and SuperI/O modules.
31:8
7
Reserved.
DRQ7 Source. Selects the interface source of the DRQ7 signal.
0: ISA - DRQ7 (Unavailable externally.)
1: LPC - LDRQ# (Program PMR[14] = 1 and PMR[22] = 1 or LPC_ROM strap = 1 to enable LDRQ# function on ball.)
DRQ6 Source. Selects the interface source of the DRQ6 signal.
0: ISA - DRQ6 (Unavailable externally.)
6
5
4
3
2
1
0
1: LPC - LDRQ# (Program PMR[14] = 1 and PMR[22] = 1 or LPC_ROM strap = 1 to enable LDRQ# function on ball.)
DRQ5 Source. Selects the interface source of the DRQ5 signal.
0: ISA - DRQ5 (Unavailable externally.)
1: LPC - LDRQ# (Program PMR[14] = 1 and PMR[22] = 1 or LPC_ROM strap = 1 to enable LDRQ# function on ball.)
LPC BM0 Cycles. Allow LPC Bus Master 0 Cycles.
0: Enable.
1: Disable.
DRQ3 Source. Selects the interface source of the DRQ3 signal.
0: ISA - DRQ3 (Unavailable externally.)
1: LPC - LDRQ# (Program PMR[14] = 1 and PMR[22] = 1 or LPC_ROM strap = 1 to enable LDRQ# function on ball.)
DRQ2 Source. Selects the interface source of the DRQ2 signal.
0: ISA - DRQ2 (Unavailable externally.)
1: LPC - LDRQ# (Program PMR[14] = 1 and PMR[22] = 1 or LPC_ROM strap = 1 to enable LDRQ# function on ball.)
DRQ1 Source. Selects the interface source of the DRQ1 signal.
0: ISA - DRQ1 (Unavailable externally.)
1: LPC - LDRQ# (Program PMR[14] = 1 and PMR[22] = 1 or LPC_ROM strap = 1 to enable LDRQ# function on ball.)
DRQ0 Source. Selects the interface source of the DRQ0 signal.
0: ISA - DRQ0 (Unavailable externally.)
1: LPC - LDRQ# (Program PMR[14] = 1 and PMR[22] = 1 or LPC_ROM strap = 1 to enable LDRQ# function on ball.)
Offset 10h-13h
LAD_EN — LPC Address Enable Register (R/W)
Reset Value: 00000000h
31:18
17
Reserved.
LPC RTC. RTC addresses I/O Ports 070h-073h. See bit 16 for decode.
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Table 5-31. F0BAR1+I/O Offset: LPC Interface Configuration Registers (Continued)
Bit
Description
16
LPC/ISA Default Mapping. Works in conjunction with bits 17 and [14:0] of this register to enable mapping of specific
peripherals to LPC or internal ISA interfaces.
If bit [x] = 0 and bit 16 = 0 then: Transaction routed to internal ISA bus.
If bit [x] = 0 and bit 16 = 1 then: Transaction routed to LPC interface.
If bit [x] = 1 and bit 16 = 0 then: Transaction routed to LPC interface.
If bit [x] = 1 and bit 16 = 1 then: Transaction routed to internal ISA bus.
Bit [x] is defined as bits 17 and [14:0].
15
LPC ROM Addressing. Depends upon F0 Index 52h[2,0].
0: Disable.
1: Enable.
14
13
LPC Alternate SuperI/O Addressing. Alternate SuperI/O control addresses 4Eh-4Fh. See bit 16 for decode.
LPC SuperI/O Addressing. SuperI/O control addresses I/O Ports 2Eh-2Fh. See bit 16 for decode.
Note: This bit should not be enabled when using the internal SuperI/O module and if IO_SIOCFG_IN (F5BAR0+I/O
Offset 00h[26:25]) = 11.
12
11
10
LPC Ad-Lib Addressing. Ad-Lib addresses I/O Ports 388h-389h. See bit 16 for decode.
LPC ACPI Addressing. ACPI microcontroller addresses I/O Ports 62h and 66h. See bit 16 for decode.
LPC Keyboard Controller Addressing. KBC addresses I/O Ports 60h and 64h.
Note: If this bit = 0 and bit 16 = 1, then F0 Index 5Ah[1] must be written 0.
LPC Wide Generic Addressing. Wide generic addresses. See bit 16 for decode.
Address selection made via F0BAR1+I/O Offset 18h[15:9]
9
Note: The selected range must not overlap any address range that is positively decoded by F0BAR1+I/O Offset 10h bits
[17], [14:10], and [8:0].
8
7
6
5
4
3
2
1
0
LPC Game Port 1 Addressing. Game Port 1 addresses. See bit 16 for decode.
Address selection made via F0BAR1+I/O Offset 14h[22:19]
LPC Game Port 0 Addressing. Game Port 0 addresses. See bit 16 for decode.
Address selection made via F0BAR1+I/O Offset 14h[18:15].
LPC Floppy Disk Controller Addressing. FDC addresses. See bit 16 for decode.
Address selection made via F0BAR1+I/O Offset 14h[14]
LPC Microsoft Sound System (MSS) Addressing. MSS addresses. See bit 16 for decode.
Address selection made via F0BAR1+I/O Offset 14h[13:12].
LPC MIDI Addressing. MIDI addresses. See bit 16 for decode.
Address selection made via F0BAR1+I/O Offset 14h[11:10].
LPC Audio Addressing. Audio addresses. See bit 16 for decode.
Address selection made via F0BAR1+I/O Offset 14h[9:8].
LPC Serial Port 1 Addressing. Serial Port 1 addresses. See bit 16 for decode.
Address selection made via F0BAR1+I/O Offset 14h[7:5].
LPC Serial Port 0 Addressing. Serial Port 0 addresses. See bit 16 for decode.
Address selection made via F0BAR1+I/O Offset 14h[4:2].
LPC Parallel Port Addressing. Parallel Port addresses. See bit 16 for decode.
Address selection made via F0BAR1+I/O Offset 14h[1:0].
Offset 14h-17h
LAD_D0 — LPC Address Decode 0 Register (R/W)
Reset Value: 00080020h
31:23
22:19
Reserved.
LPC Game Port 1 Address Select. Selects I/O Port:
0000: 200h
0001: 201h
0010: 202h
0011: 203h
0100: 204h
0101: 205h
0110: 206h
0111: 207h
1000: 208h
1001: 209h
1010: 20Ah
1011: 20Bh
1100: 20Ch
1101: 20Dh
1110: 20Eh
1111: 20Fh
Selected address range is enabled via F0BAR1+I/O Offset 10h[8].
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Table 5-31. F0BAR1+I/O Offset: LPC Interface Configuration Registers (Continued)
Bit
Description
LPC Game Port 0 Address Select. Selects I/O Port:
18:15
0000: 200h
0001: 201h
0010: 202h
0011: 203h
0100: 204h
0101: 205h
0110: 206h
0111: 207h
1000: 208h
1001: 209h
1010: 20Ah
1011: 20Bh
1100: 20Ch
1101: 20Dh
1110: 20Eh
1111: 20Fh
Selected address range is enabled via F0BAR1+I/O Offset 10h[7].
LPC Floppy Disk Controller Address Select. Selects I/O Port:
0: 3F0h-3F7h.
14
1: 370h-377h.
Selected address range is enabled via F0BAR1+I/O Offset 10h[6].
LPC Microsoft Sound System (MSS) Address Select. Selects I/O Port:
13:12
11:10
9:8
00: 530h-537h
01: 604h-60Bh
10: E80h-E87h
11: F40h-F47h
Selected address range is enabled via F0BAR1+I/O Offset 10h[5].
LPC MIDI Address Select. Selects I/O Port:
00: 300h-301h
01: 310h-311h
10: 320h-321h
11: 330h-331h
Selected address range is enabled via F0BAR1+I/O Offset 10h[4].
LPC Audio Address Select. Selects I/O Port:
00: 220h-233h
01: 240h-253h
10: 260h-273h
11: 280h-293h
Selected address range is enabled via F0BAR1+I/O Offset 10h[3].
7:5
LPC Serial Port 1 Address Select. Selects I/O Port:
000: 3F8h-3FFh
001: 2F8h-2FFh
010: 220h-227h
011: 228h-22Fh
100: 238h-23Fh
101: 2E8h-2EFh
110: 338h-33Fh
111: 3E8h-3EFh
Selected address range is enabled via F0BAR1+I/O Offset 10h[2].
4:2
LPC Serial Port 0 Address Select. Selects I/O Port:
000: 3F8h-3FFh
001: 2F8h-2FFh
010: 220h-227h
011: 228h-22Fh
100: 238h-23Fh
101: 2E8h-2EFh
110: 338h-33Fh
111: 3E8h-3EFh
Selected address range is enabled via F0BAR1+I/O Offset 10h[1].
1:0
LPC Parallel Port Address Select. Selects I/O Port:
00: 378h-37Fh (+778h-77Fh for ECP)
10: 3BCh-3BFh (+7BCh-7BFh for ECP)
01: 278h-27Fh (+678h-67Fh for ECP) (Note)
11: Reserved
Selected address range is enabled via F0BAR1+I/O Offset 10h[0].
Note: 279h is read only, writes are forwarded to ISA for PnP.
Offset 18h-1Bh
LAD_D1 — LPC Address Decode 1 Register (R/W)
Reset Value: 00000000h
31:16
15:9
Reserved. Must be set to 0.
Wide Generic Base Address Select. Defines a 512 byte space. Can be mapped anywhere in the 64 KB I/O space. AC97
and other configuration registers are expected to be mapped to this range. It is wide enough to allow many unforeseen
devices to be supported. Enabled at F0BAR1+I/O Offset 10h[9].
Note: The selected range must not overlap any address range that is positively decoded by F0BAR1+I/O Offset 10h bits
[17], [14:10], and [8:0].
8:0
Reserved. Must be set to 0.
Offset 1Ch-1Fh
LPC_ERR_SMI — LPC Error SMI Register (R/W)
Reset Value: 00000080h
31:12
11
Reserved. Must be set to 0.
LPCPD# Override Enable. Determines how LPCPD# output is controlled.
0: ACPI logic.
1: LPCPD# Override Value bit (bit 10 of this register).
LPCPD# Override Value. Selects value of LPCPD# output if bit 11 of this register is set to 1.
0: Power down sequence.
10
1: Normal power.
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Core Logic Module (Continued)
Table 5-31. F0BAR1+I/O Offset: LPC Interface Configuration Registers (Continued)
Bit
Description
9
SMI Serial IRQ Enable. Allows serial IRQ to generate an SMI.
0: Disable.
1: Enable.
Top Level SMI status is reported at F1BAR0+I/O Offset 02h[3].
Second level status is reported at bit 6 of this register.
8
SMI Configuration for LPC Error Enable. Allows LPC errors to generate an SMI.
0: Disable.
1: Enable.
Top Level SMI status is reported at F1BAR0+I/O Offset 02h[3].
Second level status is reported at bit 5 of this register.
7
6
LPCPD# Pin Status. (Read Only) Reflects the current value of the LPCPD# output signal.
SMI Source is Serial IRQ. Indicates whether or not an SMI was generated by an SERIRQ.
0: No.
1: Yes.
Write 1 to clear.
To enable SMI generation, set bit 9 of this register to 1.
This is the second level of status reporting. The top level status is reported in F1BAR0+I/O Offset 02h[3].
Writing a 1 to this bit also clears the top level status bit as long as bit 5 of this register is cleared.
5
LPC Error Status. Indicates whether or not an SMI was generated by an error that occurred on LPC.
0: No.
1: Yes.
Write 1 to clear.
To enable SMI generation, set bit 8 of this register to 1.
This is the second level of status reporting. The top level status is reported in F1BAR0+I/O Offset 02h[3].
Writing a 1 to this bit also clears the top level status bit as long as bit 6 of this register is cleared.
4
3
2
1
0
LPC Multiple Errors Status. Indicates whether or not multiple errors have occurred on LPC.
0: No.
1: Yes.
Write 1 to clear.
LPC Timeout Error Status. Indicates whether or not an error was generated by a timeout on LPC.
0: No.
1: Yes.
Write 1 to clear.
LPC Error Write Status. Indicates whether or not an error was generated during a write operation on LPC.
0: No.
1: Yes.
Write 1 to clear.
LPC Error DMA Status. Indicates whether or not an error was generated during a DMA operation on LPC.
0: No.
1: Yes.
Write 1 to clear.
LPC Error Memory Status. Indicates whether or not an error was generated during a memory operation on LPC.
0: No.
1: Yes.
Write 1 to clear.
Offset 20h-23h
LPC_ERR_ADD — LPC Error Address Register (RO)
Reset Value: 00000000h
31:0
LPC Error Address.
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5.4.2 SMI Status and ACPI Registers - Function 1
The register space designated as Function 1 (F1) is used
to configure the PCI portion of support hardware for the
SMI Status and ACPI Support registers. The bit formats for
the PCI Header registers are given in Table 5-32.
Located in the PCI Header registers of F1 are two Base
Address Registers (F1BARx) used for pointing to the regis-
ter spaces designated for SMI status and ACPI support,
described later in this section.
Table 5-32. F1: PCI Header Registers for SMI Status and ACPI Support
Bit
Description
Index 00h-01h
Index 02h-03h
Index 04h-05h
Vendor Identification Register (RO)
Device Identification Register (RO)
PCI Command Register (R/W)
Reset Value: 100Bh
Reset Value: 0501h
Reset Value: 0000h
15:1
0
Reserved. (Read Only)
I/O Space. Allow the Core Logic module to respond to I/O cycles from the PCI bus.
0: Disable.
1: Enable.
This bit must be enabled to access I/O offsets through F1BAR0 and F1BAR1 (see F1 Index 10h and 40h).
Index 06h-07h
Index 08h
PCI Status Register (RO)
Device Revision ID Register (RO)
PCI Class Code Register (RO)
PCI Cache Line Size Register (RO)
PCI Latency Timer Register (RO)
PCI Header Type (RO)
Reset Value: 0280h
Reset Value: 00h
Index 09h-0Bh
Index 0Ch
Reset Value: 068000h
Reset Value: 00h
Index 0Dh
Reset Value: 00h
Index 0Eh
Reset Value: 00h
Index 0Fh
PCI BIST Register (RO)
Reset Value: 00h
Index 10h-13h
Base Address Register 0 - F1BAR0 (R/W)
Reset Value: 00000001h
This register allows access to I/O mapped SMI status related registers. Bits [7:0] are read only (0000 0001), indicating a 256-byte I/O
address range. Refer to Table 5-33 on page 248 for bit formats and reset values of the SMI status registers.
31:8
7:0
SMI Status Base Address.
Address Range. (Read Only)
Index 14h-2Bh
Index 2Ch-2Dh
Index 2Eh-2Fh
Index 30h-3Fh
Index 40h-43h
Reserved
Subsystem Vendor ID (RO)
Subsystem ID (RO)
Reset Value: 00h
Reset Value: 100Bh
Reset Value: 0501h
Reset Value: 00h
Reserved
Base Address Register 1 - F1BAR1 (R/W)
Reset Value: 00000001h
This register allows access to I/O mapped ACPI related registers. Bits [7:0] are read only (0000 0001), indicating a 256 byte address
range. Refer to Table 5-34 on page 257 for bit formats and reset values of the ACPI registers.
Note: This Base Address register moved from its normal PCI Header Space (F1 Index 14h) to prevent plug and play software from
relocating it after an FACP table is built.
31:8
7:1
0
ACPI Base Address.
Address Range. (Read Only)
Enable. (Write Only) This bit must be set to 1 to enable access to ACPI Support Registers.
Index 44h-FFh
Reserved
Reset Value: 00h
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Core Logic Module (Continued)
5.4.2.1 SMI Status Support Registers
The registers at F1BAR0+I/O Offset 50h-FFh can also be
accessed F0 Index 50h-FFh. The preferred method is to
program these registers through the F0 register space.
F1 Index 10h, Base Address Register 0 (F1BAR0), points
to the base address for SMI Status register locations. Table
5-33 gives the bit formats of I/O mapped SMI Status regis-
ters accessed through F1BAR0.
Table 5-33. F1BAR0+I/O Offset: SMI Status Registers
Bit
Description
Offset 00h-01h
Top Level PME/SMI Status Mirror Register (RO)
Reset Value: 0000h
Note: Reading this register does not clear the status bits. For more information, see F1BAR0+I/O Offset 02h.
15
14
Suspend Modulation Enable Mirror. This bit mirrors the Suspend Mode Configuration bit (F0 Index 96h[0]). It is used by
the SMI handler to determine if the SMI Speedup Disable Register (F1BAR0+I/O Offset 08h) must be cleared on exit.
SMI Source is USB. Indicates whether or not an SMI was caused by USB activity
0: No.
1: Yes.
To enable SMI generation, set F5BAR0+I/O Offset 00h[20:19] to 11.
13
12
11
SMI Source is Warm Reset Command. Indicates whether or not an SMI was caused by a Warm Reset command.
0: No.
1: Yes.
SMI Source is NMI. Indicates whether or not an SMI was caused by NMI activity.
0: No.
1: Yes.
SMI Source is SuperI/O. Indicates whether or not an SMI was caused by SuperI/O.
0: No.
1: Yes.
The next level (second level) of SMI status is reported in the SuperI/O module. For more information, see Table 4-29 "Banks
0 and 1 - Common Control and Status Registers" on page 132, Offset 00h.
10
9
SMI Source is EXT_SMI[7:0]. Indicates whether or not an SMI was caused by a negative-edge event on EXT_SMI[7:0].
0: No.
1: Yes.
The next level (second level) of SMI status is at F1BAR0+I/O Offset 24h[23:8].
SMI Source is GP Timers/UDEF/PCI/ISA Function Trap. Indicates if an SMI was caused by:
— Expiration of GP Timer 1 or 2.
— Trapped access to UDEF1, 2, or 3.
— Trapped access to F1-F5 or ISA Legacy register space.
0: No.
1: Yes.
The next level (second level) of SMI status is at F1BAR0+I/O Offset 04h/06h.
8
7
SMI Source is Software Generated. Indicates whether or not an SMI was caused by software.
0: No.
1: Yes.
SMI on an A20M# Toggle. Indicates whether or not an SMI was caused by a write access to either Port 92h or the keyboard
command which initiates an A20M# SMI.
0: No.
1: Yes.
This method of controlling the internal A20M# in the GX1 module is used instead of a pin.
To enable SMI generation, set F0 Index 53h[0] to 1.
6
SMI Source is a VGA Timer Event. Indicates whether or not an SMI was caused by the expiration of the VGA Timer (F0
Index 8Eh).
0: No.
1: Yes.
To enable SMI generation, set F0 Index 83h[3] to 1.
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Core Logic Module (Continued)
Table 5-33. F1BAR0+I/O Offset: SMI Status Registers (Continued)
Bit
Description
5
SMI Source is Video Retrace. Indicates whether or not an SMI was caused by a video retrace event as decoded from the
internal serial connection (PSERIAL register, bit 7) from the GX1 module.
0: No.
1: Yes.
To enable SMI generation, set F0 Index 83h[2] to 1.
4
3
Reserved. Reads as 0.
SMI Source is LPC. Indicates whether or not an SMI was caused by the LPC interface.
0: No.
1: Yes.
The next level (second level) of SMI status is at F0BAR1+I/O Offset 1Ch[6:5].
2
SMI Source is ACPI. Indicates whether or not an SMI was caused by an access (read or write) to one of the ACPI registers
(F1BAR1).
0: No.
1: Yes.
The next level (second level) of SMI status is at F1BAR0+I/O Offset 20h.
1
0
SMI Source is Audio Subsystem. Indicates whether or not an SMI was caused by the audio subsystem.
0: No.
1: Yes.
The next level (second level) of SMI status is at F3BAR0+Memory Offset 10h/12h.
SMI Source is Power Management Event. Indicates whether or not an SMI was caused by one of the power management
resources (except for GP timers, UDEFx and PCI/ISA function traps that are reported in bit 9).
0: No.
1: Yes.
The next level (second level) of SMI status is at F0 Index 84h-F4h/87h-F7h.
Offset 02h-03h
Top Level PME/SMI Status Register (RO/RC)
Reset Value: 0000h
Note: Reading this register clears all the SMI status bits except for the "read only" bits, because they have a second level of status
reporting. Clearing the second level status bits also clears the top level (except for GPIOs).
GPIO SMIs have third level of SMI status reporting at F0BAR0+I/O Offset 0Ch/1Ch. Clearing the third level GPIO status bits
also clears the second and top levels.
A read-only “Mirror” version of this register exists at F1BAR0+I/O Offset 00h. If the value of the register must be read without
clearing the SMI source (and consequently de-asserting SMI), F1BAR0+I/O Offset 00h can be read instead.
15
14
Suspend Modulation Enable Mirror. (Read to Clear)
This bit mirrors the Suspend Mode Configuration bit (F0 Index 96h[0]). It is used by the SMI handler to determine if the SMI
Speedup Disable Register (F1BAR0+I/O Offset 08h) must be cleared on exit.
SMI Source is USB. (Read to Clear) Indicates whether or not an SMI was caused by USB activity.
0: No.
1: Yes.
To enable SMI generation, set F5BAR0+I/O Offset 00h[20:19] to 11.
13
SMI Source is Warm Reset Command. (Read to Clear) Indicates whether or not an SMI was caused by Warm Reset
command
0: No.
1: Yes.
12
11
SMI Source is NMI. (Read to Clear) Indicates whether or not an SMI was caused by NMI activity.
0: No.
1: Yes.
SMI Source is SuperI/O. (Read to Clear) Indicates whether or not an SMI was caused by SuperI/O.
0: No.
1: Yes.
The next level (second level) of SMI status is reported in the SuperI/O module. See Table 4-29 "Banks 0 and 1 - Common
Control and Status Registers" on page 132 for details.
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Core Logic Module (Continued)
Table 5-33. F1BAR0+I/O Offset: SMI Status Registers (Continued)
Bit
Description
10
SMI Source is EXT_SMI[7:0]. (Read Only. Read Does Not Clear) Indicates whether or not an SMI was caused by a neg-
ative-edge event on EXT_SMI[7:0].
0: No.
1: Yes.
The next level (second level) of SMI status is at F1BAR0+I/O Offset 24h[23:8].
9
SMI Source is General Timers/Traps. (Read Only, Read Does Not Clear) Indicates whether or not an SMI was caused by
the expiration of one of the General Purpose Timers or one of the User Defined Traps.
0: No.
1: Yes.
The next level (second level) of SMI status is at F1BAR0+I/O Offset 04h/06h.
8
7
SMI Source is Software Generated. (Read to Clear) Indicates whether or not an SMI was caused by software.
0: No.
1: Yes.
SMI on an A20M# Toggle. (Read to Clear) Indicates whether or not an SMI was caused by an access to either Port 92h or
the keyboard command which initiates an A20M# SMI
0: No.
1: Yes.
This method of controlling the internal A20M# in the GX1 module is used instead of a pin.
To enable SMI generation, set F0 Index 53h[0] to 1.
6
5
SMI Source is a VGA Timer Event. (Read to Clear) Indicates whether or not an SMI was caused by expiration of the VGA
Timer (F0 Index 8Eh).
0: No.
1: Yes.
To enable SMI generation, set F0 Index 83h[3] to 1.
SMI Source is Video Retrace. (Read to Clear) Indicates whether or not an SMI was caused by a video retrace event as
decoded from the internal serial connection (PSERIAL register, bit 7) from the GX1 module.
0: No.
1: Yes.
To enable SMI generation, set F0 Index 83h[2] to 1.
4
3
Reserved. Reads as 0.
SMI Source is LPC. (Read Only, Read Does Not Clear) Indicates whether or not an SMI was caused by the LPC interface.
0: No.
1: Yes.
The next level (second level) of SMI status is at F0BAR1+I/O Offset 1Ch[6:5].
2
1
0
SMI Source is ACPI. (Read Only, Read Does Not Clear) Indicates whether or not an SMI was caused by an access (read
or write) to one of the ACPI registers (F1BAR1).
0: No.
1: Yes.
The next level (second level) of SMI status is at F1BAR0+I/O Offset 20h.
SMI Source is Audio Subsystem. (Read Only, Read Does Not Clear) Indicates whether or not an SMI was caused by the
audio subsystem.
0: No.
1: Yes.
The second level of status is found in F3BAR0+Memory Offset 10h/12h.
SMI Source is Power Management Event. (Read Only, Read Does Not Clear) Indicates whether or not an SMI was
caused by one of the power management resources (except for GP timers, UDEFx and PCI/ISA function traps which are
reported in bit 9).
0: No.
1: Yes.
The next level (second level) of SMI status is at F0 Index 84h/F4h-87h/F7h.
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Table 5-33. F1BAR0+I/O Offset: SMI Status Registers (Continued)
Bit
Description
Offset 04h-05h
Second Level General Traps & Timers
PME/SMI Status Mirror Register (RO)
Reset Value: 0000h
The bits in this register contain second level status reporting. Top level status is reported at F1BAR0+I/O Offset 00h/02h[9].
Reading this register does not clear the SMI. For more information, see F1BAR0+I/O Offset 06h.
15:6
5
Reserved.
PCI/ISA Function Trap. Indicates whether or not an SMI was caused by a trapped PCI/ISA configuration cycle.
0: No.
1: Yes.
To enable SMI generation for:
— Trapped access to ISA Legacy I/O register space set F0 Index 41h[0] = 1.
— Trapped access to F1 register space set F0 Index 41h[1] = 1.
— Trapped access to F2 register space set F0 Index 41h[2] = 1.
— Trapped access to F3 register space set F0 Index 41h[3] = 1.
— Trapped access to F4 register space set F0 Index 41h[4] = 1.
— Trapped access to F5 register space set F0 Index 41h[5] = 1.
4
3
2
1
0
SMI Source is Trapped Access to User Defined Device 3. Indicates whether or not an SMI was caused by a trapped I/O
or memory access to the User Defined Device 3 (F0 Index C8h).
0: No.
1: Yes.
To enable SMI generation, set F0 Index 82h[6] = 1.
SMI Source is Trapped Access to User Defined Device 2. Indicates whether or not an SMI was caused by a trapped I/O
or memory access to the User Defined Device 2 (F0 Index C4h).
0: No.
1: Yes.
To enable SMI generation, set F0 Index 82h[5] = 1.
SMI Source is Trapped Access to User Defined Device 1. Indicates whether or not an SMI was caused by a trapped I/O
or memory access to the User Defined Device 1 (F0 Index C0h).
0: No.
1: Yes.
To enable SMI generation, set F0 Index 82h[4] = 1.
SMI Source is Expired General Purpose Timer 2. Indicates whether or not an SMI was caused by the expiration of Gen-
eral Purpose Timer 2 (F0 Index 8Ah).
0: No.
1: Yes.
To enable SMI generation, set F0 Index 83h[1] = 1.
SMI Source is Expired General Purpose Timer 1. Indicates whether or not an SMI was caused by the expiration of Gen-
eral Purpose Timer 1 (F0 Index 88h).
0: No.
1: Yes.
To enable SMI generation, set F0 Index 83h[0] = 1.
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Core Logic Module (Continued)
Table 5-33. F1BAR0+I/O Offset: SMI Status Registers (Continued)
Bit
Description
Offset 06h-07h
Second Level General Traps & Timers Status Register (RC)
Reset Value: 0000h
The bits in this register contain second level of status reporting. Top level status is reported in F1BAR0+I/O Offset 00h/02h[9]. Reading
this register clears the status at both the second and top levels.
A read-only “Mirror” version of this register exists at F1BAR0+I/O Offset 04h. If the value of this register must be read without clearing
the SMI source (and consequently de-asserting SMI), F1BAR0+I/O Offset 04h can be read instead.
15:6
5
Reserved.
PCI/ISA Function Trap. Indicates whether or not an SMI was caused by a trapped PCI/ISA configuration cycle
0: No.
1: Yes.
To enable SMI generation for:
— Trapped access to ISA Legacy I/O register space set F0 Index 41h[0] = 1.
— Trapped access to F1 register space set F0 Index 41h[1] = 1.
— Trapped access to F2 register space set F0 Index 41h[2] = 1.
— Trapped access to F3 register space set F0 Index 41h[3] = 1.
— Trapped access to F4 register space set F0 Index 41h[4] = 1.
— Trapped access to F5 register space set F0 Index 41h[5] = 1.
4
3
2
1
0
SMI Source is Trapped Access to User Defined Device 3 (UDEF3). Indicates whether or not an SMI was caused by a
trapped I/O or memory access to User Defined Device 3 (F0 Index C8h).
0: No.
1: Yes.
To enable SMI generation, set F0 Index 82h[6] = 1.
SMI Source is Trapped Access to User Defined Device 2 (UDEF2). Indicates whether or not an SMI was caused by a
trapped I/O or memory access to User Defined Device 2 (F0 Index C4h).
0: No.
1: Yes.
To enable SMI generation, set F0 Index 82h[5] = 1.
SMI Source is Trapped Access to User Defined Device 1 (UDEF1). Indicates whether or not an SMI was caused by a
trapped I/O or memory access to User Defined Device 1 (F0 Index C0h).
0: No.
1: Yes.
To enable SMI generation, set F0 Index 82h[4] = 1.
SMI Source is Expired General Purpose Timer 2. Indicates whether or not an SMI was caused by the expiration of Gen-
eral Purpose Timer 2 (F0 Index 8Ah).
0: No.
1: Yes.
To enable SMI generation, set F0 Index 83h[1] = 1.
SMI Source is Expired General Purpose Timer 1. Indicates whether or not an SMI was caused by the expiration of Gen-
eral Purpose Timer 1 (F0 Index 88h).
0: No.
1: Yes.
To enable SMI generation, set F0 Index 83h[0] = 1.
Offset 08h-09h
SMI Speedup Disable Register (Read to Enable)
Reset Value: 0000h
15:0
SMI Speedup Disable. If bit 1 in the Suspend Configuration Register is set (F0 Index 96h[1] = 1), a read of this register
invokes the SMI handler to re-enable Suspend Modulation.
The data read from this register can be ignored. If the Suspend Modulation feature is disabled, reading this I/O location has
no effect.
Offset 0Ah-1Bh
Reserved
Reset Value: 00h
These addresses should not be written.
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Table 5-33. F1BAR0+I/O Offset: SMI Status Registers (Continued)
Bit
Description
Offset 1Ch-1Fh
ACPI Timer Register (RO)
Reset Value: xxxxxxxxh
Note: This register can also be read at F1BAR1+I/O Offset 1Ch.
31:24
23:0
Reserved.
TMR_VAL. This field returns the running count of the power management timer.
Offset 20h-21h
Second Level ACPI PME/SMI
Status Mirror Register (RO)
Reset Value: 0000h
The bits in this register contain second level SMI status reporting. Top level status is reported in F1BAR0+I/O Offset 00h/02h[2].
Reading this register does not clear the SMI. For more information, see F1BAR0+I/O Offset 22h.
15:6
5
Reserved. Always reads 0.
ACPI BIOS SMI Status. Indicates whether or not an SMI was caused by ACPI software raising an event to BIOS software.
0: No.
1: Yes.
To enable SMI generation, set F1BAR1+I/O Offset 0Ch[2] to 1, and F1BAR1+I/O Offset 0Fh[0] to 1.
4
PLVL3 SMI Status. Indicates whether or not an SMI was caused by a read of the ACPI PLVL3 register (F1BAR1+I/O Offset
05h).
0: No.
1: Yes.
To enable SMI generation, set F1BAR1+I/O Offset 18h[11] to 1 (default).
3
2
Reserved.
SLP_EN SMI Status. Indicates whether or not an SMI was caused by a write of 1 to the ACPI SLP_EN bit (F1BAR1+I/O
Offset 0Ch[13]).
0: No.
1: Yes.
To enable SMI generation, set F1BAR1+I/O Offset 18h[9] to 1 (default).
1
0
THT_EN SMI Status. Indicates whether or not an SMI was caused by a write of 1 to the ACPI THT_EN bit (F1BAR1+I/O
Offset 00h[4]).
0: No.
1: Yes.
To enable SMI generation, set F1BAR1+I/O Offset 18h[8] to 1 (default).
SMI_CMD SMI Status. Indicates whether or not an SMI was caused by a write to the ACPI SMI_CMD register
(F1BAR1+I/O Offset 06h).
0: No.
1: Yes.
A write to the ACPI SMI_CMD register always generates an SMI.
Offset 22h-23h
Second Level ACPI PME/SMI Status Register (RC)
Reset Value: 0000h
The bits in this register contain second level of SMI status reporting. Top level is reported in F1BAR0+I/O Offset 00h/02h[2].
Reading this register clears the status at both the second and top levels.
A read-only “Mirror” version of this register exists at F1BAR0+I/O Offset 20h. If the value of the register must be read without clearing the
SMI source (and consequently de-asserting SMI), F1BAR0+I/O Offset 20h can be read instead.
15:6
5
Reserved. Always reads 0.
ACPI BIOS SMI Status. Indicates whether or not an SMI was caused by ACPI software raising an event to BIOS software.
0: No.
1: Yes.
To enable SMI generation, set F1BAR1+I/O Offset 0Ch[2] to 1, and F1BAR1+I/O Offset 0Fh[0] to 1.
4
PLVL3 SMI Status. Indicates whether or not an SMI was caused by a read of the ACPI PLVL3 register (F1BAR1+I/O Offset
05h).
0: No.
1: Yes.
To enable SMI generation, set F1BAR1+I/O Offset 18h[11] to 1 (default).
3
Reserved.
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Core Logic Module (Continued)
Table 5-33. F1BAR0+I/O Offset: SMI Status Registers (Continued)
Bit
Description
2
SLP_EN SMI Status. Indicates whether or not an SMI was caused by a write of 1 to the ACPI SLP_EN bit (F1BAR1+I/O
Offset 0Ch[13]).
0: No.
1: Yes.
To enable SMI generation, set F1BAR1+I/O Offset 18h[9] to 1 (default).
1
0
THT_EN SMI Status. Indicates whether or not an SMI was caused by a write of 1 to the ACPI THT_EN bit (F1BAR1+I/O
Offset 00h[4])
0: No.
1: Yes.
To enable SMI generation, set F1BAR1+I/O Offset 18h[8] to 1 (default).
SMI_CMD SMI Status. Indicates whether or not an SMI was caused by a write to the ACPI SMI_CMD register
(F1BAR1+I/O Offset 06h).
0: No.
1: Yes.
A write to the ACPI SMI_CMD register always generates an SMI.
Offset 24h-27h
External SMI Register (R/W)
Reset Value: 00000000h
Note: EXT_SMI[7:0] are external SMIs, meaning external to the Core Logic module.
Bits [23:8] of this register contain second level of SMI status reporting. Top level status is reported in F1BAR0+I/O Offset
00h/02h[10]. Reading bits [23:16] clears the second and top levels. If the value of the status bits must be read without clearing
the SMI source (and consequently de-asserting SMI), bits [15:8] can be read instead.
31:24
23
Reserved. Must be set to 0.
EXT_SMI7 SMI Status. (Read to Clear) Indicates whether or not an SMI was caused by assertion of EXT_SMI7.
0: No.
1: Yes.
To enable SMI generation, set bit 7 to 1.
22
21
20
19
18
17
EXT_SMI6 SMI Status. (Read to Clear) Indicates whether or not an SMI was caused by an assertion of EXT_SMI6
0: No.
1: Yes.
To enable SMI generation, set bit 6 to 1.
EXT_SMI5 SMI Status. (Read to Clear) Indicates whether or not an SMI was caused by an assertion of EXT_SMI5.
0: No.
1: Yes.
To enable SMI generation, set bit 5 to 1.
EXT_SMI4 SMI Status. (Read to Clear) Indicates whether or not an SMI was caused by an assertion of EXT_SMI4.
0: No.
1: Yes.
To enable SMI generation, set bit 4 to 1.
EXT_SMI3 SMI Status. (Read to Clear) Indicates whether or not an SMI was caused by an assertion of EXT_SMI3.
0: No.
1: Yes.
To enable SMI generation, set bit 3 to 1.
EXT_SMI2 SMI Status. (Read to Clear) Indicates whether or not an SMI was caused by an assertion of EXT_SMI2.
0: No.
1: Yes.
To enable SMI generation, set bit 2 to 1.
EXT_SMI1 SMI Status. (Read to Clear) Indicates whether or not an SMI was caused by an assertion of EXT_SMI1.
0: No.
1: Yes.
To enable SMI generation, set bit 1 to 1.
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Table 5-33. F1BAR0+I/O Offset: SMI Status Registers (Continued)
Bit
Description
16
EXT_SMI0 SMI Status. (Read to Clear) Indicates whether or not an SMI was caused by an assertion of EXT_SMI0.
0: No.
1: Yes.
To enable SMI generation, set bit 0 to 1.
15
14
13
12
11
10
9
EXT_SMI7 SMI Status. (Read Only) Indicates whether or not an SMI was caused by an assertion of EXT_SMI7.
0: No.
1: Yes.
To enable SMI generation, set bit 7 to 1.
EXT_SMI6 SMI Status. (Read Only) Indicates whether or not an SMI was caused by an assertion of EXT_SMI6.
0: No.
1: Yes.
To enable SMI generation, set bit 6 to 1.
EXT_SMI5 SMI Status. (Read Only) Indicates whether or not an SMI was caused by an assertion of EXT_SMI5.
0: No.
1: Yes.
To enable SMI generation, set bit 5 to 1.
EXT_SMI4 SMI Status. (Read Only) Indicates whether or not an SMI was caused by an assertion of EXT_SMI4.
0: No.
1: Yes.
To enable SMI generation, set bit 4 to 1.
EXT_SMI3 SMI Status. (Read Only) Indicates whether or not an SMI was caused by an assertion of EXT_SMI3.
0: No.
1: Yes.
To enable SMI generation, set bit 3 to 1.
EXT_SMI2 SMI Status. (Read Only) Indicates whether or not an SMI was caused by an assertion of EXT_SMI2.
0: No.
1: Yes.
To enable SMI generation, set bit 2 to 1.
EXT_SMI1 SMI Status. (Read Only) Indicates whether or not an SMI was caused by an assertion of EXT_SMI1.
0: No.
1: Yes.
To enable SMI generation, set bit 1 to 1.
8
EXT_SMI0 SMI Status. (Read Only) Indicates whether or not an SMI was caused by an assertion of EXT_SMI0.
0: No.
1: Yes.
To enable SMI generation, set bit 0 to 1.
7
EXT_SMI7 SMI Enable. When this bit is asserted, allow EXT_SMI7 to generate an SMI on negative-edge events.
0: Disable.
1: Enable.
Top level SMI status is reported at F1BAR0+00h/02h[10].
Second level SMI status is reported at bits 23 (RC) and 15 (RO).
6
EXT_SMI6 SMI Enable. When this bit is asserted, allow EXT_SMI6 to generate an SMI on negative-edge events.
0: Disable.
1: Enable.
Top level SMI status is reported at F1BAR0+00h/02h[10].
Second level SMI status is reported at bits 22 (RC) and 14 (RO).
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Core Logic Module (Continued)
Table 5-33. F1BAR0+I/O Offset: SMI Status Registers (Continued)
Bit
Description
5
EXT_SMI5 SMI Enable. When this bit is asserted, allow EXT_SMI5 to generate an SMI on negative-edge events.
0: Disable.
1: Enable.
Top level SMI status is reported at F1BAR0+00h/02h[10].
Second level SMI status is reported at bits 21 (RC) and 13 (RO).
4
3
2
1
0
EXT_SMI4 SMI Enable. When this bit is asserted, allows EXT_SMI4 to generate an SMI on negative-edge events.
0: Disable.
1: Enable.
Top level SMI status is reported at F1BAR0+00h/02h[10].
Second level SMI status is reported at bits 20 (RC) and 12 (RO).
EXT_SMI3 SMI Enable. When this bit is asserted, allow EXT_SMI3 to generate an SMI on negative-edge events.
0: Disable.
1: Enable.
Top level SMI status is reported at F1BAR0+00h/02h[10].
Second level SMI status is reported at bits 19 (RC) and 11 (RO).
EXT_SMI2 SMI Enable. When this bit is asserted, allow EXT_SMI2 to generate an SMI on negative-edge events.
0: Disable.
1: Enable.
Top level SMI status is reported at F1BAR0+00h/02h[10].
Second level SMI status is reported at bits 18 (RC) and 10 (RO).
EXT_SMI1 SMI Enable. When this bit is asserted, allow EXT_SMI1 to generate an SMI on negative-edge events.
0: Disable.
1: Enable.
Top level SMI status is reported at F1BAR0+00h/02h[10].
Second level SMI status is reported at bits 17 (RC) and 9 (RO).
EXT_SMI0 SMI Enable. When this bit is asserted, allow EXT_SMI0 to generate an SMI on negative-edge events.
0: Disable.
1: Enable.
Top level SMI status is reported at F1BAR0+00h/02h[10].
Second level SMI status is reported at bits 16 (RC) and 8 (RO).
Offset 28h-4Fh
Not Used
Reset Value: 00h
The I/O mapped registers located here (F1BAR0+I/O Offset 50h-FFh) can also be accessed at F0 Index 50h-FFh. The pre-
ferred method is to program these registers through the F0 register space. Refer to Table 5-29 "F0: PCI Header and Bridge
Configuration Registers for GPIO and LPC Support" on page 204 for more information about these registers.
Offset
50h-FFh
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Core Logic Module (Continued)
5.4.2.2 ACPI Support Registers
F1 Index 40h, Base Address Register 1 (F1BAR1), points
to the base address of where the ACPI Support registers
are located. Table 5-34 shows the I/O mapped ACPI Sup-
port registers accessed through F1BAR1.
Table 5-34. F1BAR1+I/O Offset: ACPI Support Registers
Bit
Description
Offset 00h-03h
P_CNT — Processor Control Register (R/W)
Reset Value: 00000000h
31:5
4
Reserved. Always reads 0.
THT_EN (Throttle Enable). When this bit is asserted, it enables throttling of the clock based on the CLK_VAL field (bits
[2:0] of this register).
0:
1:
Disable.
Enable.
If F1BAR1+I/O Offset 18h[8] =1, an SMI is generated when this bit is set.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[2].
Second level SMI status is reported at F1BAR0+I/O Offset 20h/22h[1].
3
Reserved. Always reads 0.
2:0
CLK_VAL (Clock Throttling Value). CPU duty cycle:
000: Reserved
001: 12.5%
010: 25%
011: 37.5%
100: 50%
101: 62.5%
110: 75%
111: 87.5%
Offset 04h
Reserved
Reset Value: 00h
Note: This register should not be read. It controls a reserved function of power management logic.
Offset 05h
P_LVL3 — Enter C3 Power State Register (RO)
Reset Value: xxh
7:0
P_LVL3 (Power Level 3). Reading this 8-bit read only register causes the processor to enter the C3 power state. Reads of
P_LVL3 return 0. Writes have no effect.
The ACPI state machine always waits for an SMI (any SMI) to be generated and serviced before transfer into C3 power
state.
A read of this register causes an SMI if enabled: F1BAR1+I/O Offset 18h[11] = 1 (default).
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[2].
Second level SMI status is reported at F1BAR0+I/O Offset 20h/22h[4].
Offset 06h
SMI_CMD — OS/BIOS Requests Register (R/W)
Reset Value: 00h
7:0
SMI_CMD (SMI Command and OS / BIOS Requests). A write to this register stores data and a read returns the last data
written. In addition, a write to this register always generates an SMI. A read of this register does not generate an SMI.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[2].
Second level SMI status is reported at F1BAR0+I/O Offset 20h/22h[0].
Offset 07h
ACPI_FUN_CNT — ACPI Function Control Register (R/W)
Reset Value: 00h
7:6
LED_CNT (LED Output Control). Controls the blinking of an LED when in the SL4 or SL5 sleep state
00: Disable (LED# signal, is HiZ).
01: Zero (LED# signal is HiZ).
10: Blink @ 1 Hz rate, when in SL4 and SL5 sleep states. Duty cycle: LED# is 10% pulled low, 90% HiZ.
11: One (LED# is pulled low, when in SL4 and SL5 sleep states)
Reserved. Must be set to 0.
5
4
INTR_WU_SL1. Enables wakeup on enabled interrupts in sleep state SL1.
0: Disable wakeup from SL1, when an enabled interrupt is active.
1: Enable wakeup from SL1, when an enabled interrupt is active.
3
GPWIO_DBNC_DIS (GPWIO0 and GPWIO1 Debouncers). Debounce settings for GPWIO0 and GPWIO1. Selects the
time that a high-to-low or low-to-high transition (debounce period) must be for GPWIO0 to be recognized.
0: Debounce period is 15.8 msec. (Default)
1: Debounce period is 31 µs.
GPWIO2 pin is fixed at 31 µs.
2:1
Reserved. Must be set to 0.
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Table 5-34. F1BAR1+I/O Offset: ACPI Support Registers (Continued)
Bit
Description
0
PWRBTN_DBNC_DIS (Power Button Debouncer). Allow a high-to-low or low-to-high transition of greater than 15.8 ms
(debounce period) on PWRBTN# before it is recognized.
0: Enable. (Default)
1: Disable.
Offset 08h-09h
PM1A_STS — PM1A Top Level PME/SCI Status Register (R/W)
Reset Value: 0000h
Notes: 1. This is the top level of PME/SCI status reporting for these events. There is no second level.
2. If SCI generation is not desired, the status bits are still set by the described conditions and can be used for monitoring pur-
poses.
15
WAK_STS (Wakeup Status). Indicates whether or not an SCI was caused by the occurrence of an enabled wakeup event.
0: No.
1: Yes.
This bit is set when the system is in any Sleep state and an enabled wakeup event occurs (wakeup events are configured at
F1BAR1+I/O Offset 0Ah and 12h). After this bit is set, the system transitions to a Working state.
SCI generation is always enabled.
Write 1 to clear.
14:12
11
Reserved. Must be set to 0.
PWRBTNOR_STS (Power Button Override Status). Indicates whether or not an SCI was caused by the power button
being active for greater than 4 seconds.
0: No.
1: Yes.
SCI generation is always enabled.
Write 1 to clear.
10
RTC_STS (Real-Time Clock Status). Indicates if a Power Management Event (PME) was caused by the RTC generating
an alarm (RTC IRQ signal is asserted).
0: No.
1: Yes.
For the PME to generate an SCI, set F1BAR1+I/O Offset 0Ah[10] to 1 and F1BAR1+I/O Offset 0Ch[0] to 1. (See Note 2 in
the general description of this register.)
Write 1 to clear.
9
8
Reserved. Must be set to 0.
PWRBTN_STS (Power Button Status). Indicates if PME was caused by the PWRBTN# going low while the system is in a
Working state.
0: No.
1: Yes.
For the PME to generate an SCI, set F1BAR1+I/O Offset 0Ah[8] = 1 and F1BAR1+I/O Offset 0Ch[0] = 1. (See Note 2 in the
general description of this register.)
In a Sleep state or the Soft-Off state, a wakeup event is generated when the power button is pressed (regardless of the
PWRBTN_EN bit, F1BAR1+I/O Offset 0Ah[8], setting).
Write 1 to clear.
7:6
5
Reserved. Must be set to 0.
GBL_STS (Global Lock Status). Indicates if PME was caused by the BIOS releasing control of the global lock.
0: No.
1: Yes.
This bit is used by the BIOS to generate an SCI. BIOS writes the BIOS_RLS bit (F1BAR1+I/O Offset 0Fh[1]) which in turns
sets the GBL_STS bit and raises a PME.
For the PME to generate an SCI, set F1BAR1+I/O Offset 0Ah[5] to 1 and F1BAR1+I/O Offset 0Ch[0] to 1. (See Note 2 in the
general description of this register.)
Write 1 to clear.
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Table 5-34. F1BAR1+I/O Offset: ACPI Support Registers (Continued)
Bit
Description
4
BM_STS (Bus Master Status). Indicates if PME was caused by a system bus master requesting the system bus.
0: No.
1: Yes.
For the PME to generate an SCI, set F1BAR1+I/O Offset 0Ch[1] = 1 and F1BAR1+I/O Offset 0Ch[0] = 1. (See Note 2 in the
general description of this register.)
Write 1 to clear.
3:1
0
Reserved. Must be set to 0.
TMR_STS (Timer Carry Status). Indicates if SCI was caused by an MSB toggle (MSB changes from low-to-high or high-to-
low) on the ACPI Timer (F1BAR0+I/O Offset 1Ch or F1BAR1+I/O Offset 1Ch).
0: No.
1: Yes.
For the PME to generate an SCI, set F1BAR1+I/O Offset 0Ah[0] = 1 and F1BAR1+I/O Offset 0Ch[0] = 1. (See Note 2 in the
general description of this register.)
Write 1 to clear.
Offset 0Ah-0Bh
PM1A_EN — PM1A PME/SCI Enable Register (R/W)
Reset Value: 0000h
In order for the ACPI events described below to generate an SCI, the SCI_EN bit must also be set (F1BAR1+I/O Offset 0Ch[0] = 1).
The SCIs enabled via this register are globally enabled by setting F1BAR1+I/O Offset 08h. There is no second level of SCI status report-
ing for these bits.
15:11
10
Reserved. Must be set to 0.
RTC_EN (Real-Time Clock Enable). Allow SCI generation when the RTC generates an alarm (RTC IRQ signal is
asserted).
0: Disable.
1: Enable
9
8
Reserved. Must be set to 0.
PWRBTN_EN (Power Button Enable). Allow SCI generation when PWRBTN# goes low while the system is in a Working
state.
0: Disable.
1: Enable
7:6
5
Reserved. Must be set to 0.
GBL_EN (Global Lock Enable). Allow SCI generation when the BIOS releases control of the global lock via the BIOS_RLS
(F1BAR1+I/O Offset 0Fh[1] and GBL_STS (F1BAR1+I/O Offset 08h[5]) bits.
0: Disable.
1: Enable
4:1
0
Reserved. Must be set to 0.
TMR_EN (ACPI Timer Enable). Allow SCI generation for MSB toggles (MSB changes from low-to-high or high-to-low) on
the ACPI Timer (F1BAR0+I/O Offset 1Ch or F1BAR1+I/O Offset 1Ch).
0: Disable.
1: Enable
Offset 0Ch-0Dh
PM1A_CNT — PM1A Control Register (R/W)
Reset Value: 0000h
15:14
13
Reserved. Must be set to 0.
SLP_EN (Sleep Enable). (Write Only) Allow the system to sequence into the sleeping state associated with the SLP_TYPx
(bits [12:10]).
0: Disable.
1: Enable.
This is a write only bit and reads of this bit always return a 0.
The ACPI state machine always waits for an SMI (any SMI) to be generated and serviced before transitioning into a Sleep
state.
If F1BAR1+I/O Offset 18h[9] = 1, an SMI is generated when SLP_EN is set.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[2].
Second level SMI status is reported at F1BAR0+I/O Offset 20h/22h[2].
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Table 5-34. F1BAR1+I/O Offset: ACPI Support Registers (Continued)
Bit
Description
SLP_TYPx (Sleep Type). Defines the type of Sleep state the system enters when SLP_EN (bit 13) is set.
12:10
000: Sleep State S0 (Full on)
001: Sleep State SL1
010: Sleep State SL2
011: Sleep State SL3
100: Sleep State SL4
101: Sleep State SL5 (Soft off)
110: Reserved
111: Reserved
9:3
2
Reserved. Set to 0.
GBL_RLS (Global Release). (Write Only) This write only bit is used by ACPI software to raise an event to the BIOS soft-
ware (i.e., it generates an SMI to pass execution control to the BIOS).
0: Disable.
1: Enable.
This is a write only bit and reads of this bit always return a 0.
To generate an SMI, ACPI software writes the GBL_RLS bit which in turn sets the BIOS_STS bit (F1BAR1+I/O Offset
0Eh[0]) and raises a PME. For the PME to generate an SMI, set BIOS_EN (F1BAR1+I/O Offset 0Fh[0] to 1).
The top level SMI status is reported at F1BAR0+I/O offset 00h/02h.
Second level status is at F1BAR0+I/O Offset 22h[5].
1
0
BM_RLD (Bus Master RLD). If the processor is in the C3 state and a bus master request is generated, force the processor
to transition to the C0 state.
0: Disable.
1: Enable
SCI_EN (System Control Interrupt Enable). Globally selects power management events (PMEs) reported in PM1A_STS
and GPE0_STS (F1BAR1+I/O Offset 08h and 10h) to be either an SCI or SMI type of interrupt.
0: APM Mode, generates an SMI and status is reported at F1BAR0+I/O Offset 00h/02h[0].
1: ACPI Mode, generates an SCI if the corresponding PME enable bit is set and status is reported at F1BAR1+I/O Offset
08h and 10h.
Note: This bit enables the ACPI state machine.
Offset 0Eh
ACPI_BIOS_STS Register (R/W)
Reset Value: 00h
7:1
0
Reserved. Must be set to 0.
BIOS_STS (BIOS Status Release). When 1 is written to the GLB_RLS bit (F1BAR1+I/O Offset 0Ch[2]), this bit is also set
to 1.
Write 1 to clear.
Offset 0Fh
ACPI_BIOS_EN Register (R/W)
Reset Value: 00h
7:2
1
Reserved. Must be set to 0.
BIOS_RLS (BIOS Release). (Write Only) When this bit is asserted, allow the BIOS to release control of the global lock.
0: Disable.
1: Enable.
This is a write only bit and reads of this bit always return a 0.
To generate an SCI, the BIOS writes the BIOS_RLS bit which in turn sets the GBL_STS bit (F1BAR1+I/O Offset 08h[5]) and
raises a PME. For the PME to generate an SCI, set GBL_EN (F1BAR1+I/O Offset 0Ah[5] to 1).
0
BIOS_EN (BIOS Enable). When this bit is asserted, allow SMI generation by ACPI software via writes to GBL_RLS
(F1BAR1+I/O Offset 0Ch[2]).
0: Disable.
1: Enable
Offset 10h-11h
GPE0_STS — General Purpose Event 0 PME/SCI Status Register (R/W)
Reset Value: xxxxh
Notes: 1) This is the top level of PME/SCI status reporting. There is no second level except for bit 3 (GPIOs) where the next level of
status is reported at F0BAR0+I/O Offset 0Ch/1Ch.
2) If SCI generation is not desired, the status bits are still set by the described conditions and can be used for monitoring pur-
poses.
15:12
11
Reserved. Must be set to 0.
Reserved.
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Table 5-34. F1BAR1+I/O Offset: ACPI Support Registers (Continued)
Bit
Description
10
GPWIO2_STS. Indicates if PME was caused by activity on GPWIO2.
0: No.
1: Yes.
Write 1 to clear.
For the PME to generate an SCI:
1) Ensure that GPWIO2 is enabled as an input (F1BAR1+I/O Offset 15h[2] = 0)
2) Set F1BAR1+I/O Offset 12h[10] = 1 and F1BAR1+I/O Offset 0Ch[0] = 1. (See Note 2 in the general description of this
register above.)
If F1BAR1+I/O Offset 15h[6] = 1 it overrides these settings and GPWIO2 generates an SMI and the status is reported in
F1BAR0+00h/02h[0].
9
GPWIO1_STS. Indicates if PME was caused by activity on GPWIO1.
0: No.
1: Yes.
Write 1 to clear.
For the PME to generate an SCI:
1) Ensure that GPWIO1 is enabled as an input (F1BAR1+I/O Offset 15h[1] = 0)
2) Set F1BAR1+I/O Offset 12h[9] = 1 and F1BAR1+I/O Offset 0Ch[0] = 1. (See Note 2 in the general description of this
register above.)
If F1BAR1+I/O Offset 15h[5] = 1 it overrides these settings and GPWIO1 generates an SMI and the status is reported in
F1BAR0+00h/02h[0].
8
GPWIO0_STS. Indicates if PME was caused by activity on GPWIO0.
0: No.
1: Yes.
Write 1 to clear.
For the PME to generate an SCI:
1) Ensure that GPWIO0 is enabled as an input (F1BAR1+I/O Offset 15h[0] = 0)
2) Set F1BAR1+I/O Offset 12h[8] = 1 and F1BAR1+I/O Offset 0Ch[0] = 1. (See Note 2 in the general description of this
register above).
If F1BAR1+I/O Offset 15h[4] = 1 it overrides these settings and GPWIO0 generates an SMI and the status is reported in
F1BAR0+00h/02h[0].
7
6
Reserved. Must be set to 0.
USB_STS. Indicates if PME was caused by a USB interrupt event.
0: No.
1: Yes.
Write 1 to clear.
For the PME to generate an SCI, set F1BAR1+I/O Offset 12h[6] = 1 and F1BAR1+I/O Offset 0Ch[0] = 1. (See Note 2 in the
general description of this register above.)
5
4
THRM_STS. Indicates if PME was caused by activity on THRM#.
0: No.
1: Yes.
Write 1 to clear.
For the PME to generate an SCI, set F1BAR1+I/O Offset 12h[5] = 1 and F1BAR1+I/O Offset 0Ch[0] = 1, (See Note 2 in the
general description of this register above,)
SMI_STS. Indicates if PME was caused by activity on the internal SMI# signal.
0: No.
1: Yes.
Write 1 to clear.
For the PME to generate an SCI, set F1BAR1+I/O Offset 12h[4] = 1 and F1BAR1+I/O Offset 0Ch[0] = 1. (See Note 2 in the
general description of this register above.)
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Table 5-34. F1BAR1+I/O Offset: ACPI Support Registers (Continued)
Bit
Description
3
GPIO_STS. Indicates if PME was caused by activity on any of the GPIOs (GPIO47-GPIO32 and GPIO15-GPIO0).
0: No.
1: Yes.
Write 1 to clear.
For the PME to generate an SCI, set F1BAR1+I/O Offset 12h[3] = 1 and F1BAR1+I/O Offset 0Ch[0] = 1. (See Note 2 in the
general description of this register above).
F0BAR0+I/O Offset 08h/18h selects which GPIOs are enabled to generate a PME. In addition, the selected GPIO must be
enabled as an input (F0BAR0+I/O Offset 20h and 24h).
2:1
0
Reserved. Reads as 0.
PWR_U_REQ_STS. Indicates if PME was caused by a power-up request event from the SuperI/O module.
0: No.
1: Yes.
Write 1 to clear.
For the PME to generate an SCI, set F1BAR1+I/O Offset 12h[0] = 1 and F1BAR1+I/O Offset 0Ch[0] = 1. (See Note 2 in the
general description of this register above.)
Offset 12h-13h
GPE0_EN — General Purpose Event 0 Enable Register (R/W)
Reset Value: 0000h
In order for the ACPI events described below to generate an SCI, the SCI_EN bit must also be set (F1BAR1+I/O Offset 0Ch[0] = 1).
The SCIs enabled in this register are globally enabled by setting F1BAR1+I/O Offset 0Ch[0] to 1. The status of the SCIs is reported in
F1BAR1+I/O Offset 10h.
15:12
11
Reserved.
Reserved.
10
GPWIO2_EN. Allow GPWIO2 to generate an SCI.
0: Disable.
1: Enable.
A fixed high-to-low or low-to-high transition (debounce period) of 31 µs exists in order for GPWIO2 to be recognized.
The setting of this bit can be overridden via F1BAR1+I/O Offset 15h[6] to force an SMI.
9
8
GPWIO1_EN. Allow GPWIO1 to generate an SCI.
0: Disable.
1: Enable.
See F1BAR1+I/O Offset 07h[3] for debounce information.
The setting of this bit can be overridden via F1BAR1+I/O Offset 15h[5] to force an SMI.
GPWIO0_EN. Allow GPWIO0 to generate an SCI.
0: Disable.
1: Enable.
See F1BAR1+I/O Offset 07h[3] for debounce information.
The setting of this bit can be overridden via F1BAR1+I/O Offset 15h[4] to force an SMI.
7
6
Reserved. Must be set to 0
USB_EN. Allow USB events to generate a SCI.
0: Disable.
1: Enable
5
4
THRM_EN. Allow THRM# to generate an SCI.
0: Disable.
1: Enable
SMI_EN. Allow SMI events to generate an SCI.
0: Disable.
1: Enable
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Table 5-34. F1BAR1+I/O Offset: ACPI Support Registers (Continued)
Bit
Description
3
GPIO_EN. Allow GPIOs (GPIO47-GPIO32 and GPIO15-GPIO0) to generate an SCI.
0: Disable.
1: Enable.
F0BAR0+I/O Offset 08h/18h selects which GPIOs are enabled for PME generation. This bit (GPIO_EN) globally enables
those selected GPIOs for generation of an SCI.
2:1
0
Reserved. Must be set to 0.
PWR_U_REQ_EN. Allow power-up request events from the SuperI/O module to generate an SCI.
0: Disable.
1: Enable.
A power-up request event is defined as any of the following events/activities: Modem, Telephone, Keyboard, Mouse, CEIR
(Consumer Electronic Infrared)
Offset 14h
GPWIO Control Register 1 (R/W)
Reset Value: 00h
7:4
3
Reserved. Must be set to 0.
Reserved.
2
GPWIO2_POL. Select GPWIO2 polarity.
0: Active high
1: Active low
1
0
GPWIO1_POL. Select GPWIO1 polarity.
0: Active high
1: Active low
GPWIO0_POL. Select GPWIO0 polarity.
0: Active high
1: Active low
Offset 15h
GPWIO Control Register 2 (R/W)
Reset Value: 00h
7
6
Reserved.
GPWIO_SMIEN2. Allow GPWIO2 to generate an SMI.
0: Disable. (Default)
1: Enable.
A fixed high-to-low or low-to-high transition (debounce period) of 31 µs exists in order for GPWIO2 to be recognized.
Bit 2 of this register must be set to 0 (input) for GPWIO2 to be able to generate an SMI.
If asserted, this bit overrides the setting of F1BAR1+I/O Offset 12h[10] and its status is reported in F1BAR0+I/O Offset
00h/02h[0].
5
GPWIO_SMIEN1. Allow GPWIO1 to generate an SMI.
0: Disable. (Default)
1: Enable.
See F1BAR1+I/O Offset 07h[3] for debounce information.
Bit 1 of this register must be set to 0 (input) for GPWIO1 to be able to generate an SMI.
If asserted, this bit overrides the setting of F1BAR1+I/O Offset 12h[9] and its status is reported in F1BAR0+I/O Offset
00h/02h[0].
4
GPWIO_SMIEN0. Allow GPWIO0 to generate an SMI.
0: Disable. (Default)
1: Enable.
See F1BAR1+I/O Offset 07h[3] for debounce information.
Bit 0 of this register must be set to 0 (input) for GPWIO0 to be able to generate an SMI.
If enabled, this bit overrides the setting of F1BAR1+I/O Offset 12h[8] and its status is reported in F1BAR0+I/O Offset
00h/02h[0].
3
2
Reserved.
GPWIO2_DIR. Selects the direction of GPWIO2.
0: Input.
1: Output.
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Table 5-34. F1BAR1+I/O Offset: ACPI Support Registers (Continued)
Bit
Description
1
GPWIO1_DIR. Selects the direction of GPWIO1.
0: Input.
1: Output.
0
GPWIO0_DIR. Selects the direction of the GPWIO0.
0: Input.
1: Output.
Offset 16h
GPWIO Data Register (R/W)
Reset Value: 00h
This register contains the direct values of the GPWIO2-GPWIO0 pins. Write operations are valid only for bits defined as outputs. Reads
from this register read the last written value if the pin is an output. The pins are configured as inputs or outputs in F1BAR1+I/O Offset
15h.
7:4
3
Reserved. Must be set to 0.
Reserved.
2
GPWIO2_DATA. Reflects the level of GPWIO2.
0: Low.
1: High.
A fixed high-to-low or low-to-high transition (debounce period) of 31 µs exists in order for GPWIO2 to be recognized.
1
0
GPWIO1_DATA. Reflects the level of GPWIO1.
0: Low.
1: High.
See F1BAR1+I/O Offset 07h[3] for debounce information.
GPWIO0_DATA. Reflects the level of GPWIO0.
0: Low.
1: High.
See F1BAR1+I/O Offset 07h[3] for debounce information.
Offset 17h
Reserved
Reset Value: 00h
Reset Value: 00000F00h
Offset 18h-1Bh
ACPI SCI_ROUTING Register (R/W)
31:17
16
Reserved.
PCTL_DELAYEN. Allow staggered delays on the activation and deactivation of the power control pins PWRCNT1,
PWRCNT2, and ONCTL# by 2 msec each.
0: Disable. (Default)
1: Enable.
15:12
11
Reserved. Must be set to 0.
PLVL3_SMIEN. Allow SMI generation when the PLVL3 Register (F1BAR1+I/O Offset 05h) is read.
0: Disable.
1: Enable. (Default)
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[2].
Second level SMI status is reported at F1BAR0+I/O Offset 20h/22h[4].
10
9
Reserved. Must be set to 0.
SLP_SMIEN. Allow SMI generation when the SLP_EN bit (F1BAR1+I/O Offset 0Ch[13]) is set.
0: Disable.
1: Enable. (Default)
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[2].
Second level SMI status is reported at F1BAR0+I/O Offset 20h/22h[2].
8
THT_SMIEN. Allow SMI generation when the THT_EN bit (F1BAR1+I/O Offset 00h[4]) is set.
0: Disable.
1: Enable. (Default)
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[2].
Second level SMI status is reported at F1BAR0+I/O Offset 20h/22h[1].
7:4
Reserved. Must be set to 0.
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Table 5-34. F1BAR1+I/O Offset: ACPI Support Registers (Continued)
Bit
Description
SCI_IRQ_ROUTE. SCI is routed to:
3:0
0000: Disable
0001: IRQ1
0010: Reserved
0011: IRQ3
0100: IRQ4
1000: IRQ8
1001: IRQ9
1010: IRQ10
1011: IRQ11
1100: IRQ12
1101: IRQ13
1110: IRQ14
1111: IRQ15
0101: IRQ5
0010: IRQ6
0011: IRQ7
For more details see Section 5.2.6.3 "Programmable Interrupt Controller" on page 169.
Offset 1Ch-1Fh PM_TMR — ACPI Timer Register (RO)
Note: This register can also be read at F1BAR0+I/O Offset 1Ch.
Reset Value: xxxxxxxxh
31:24
23:0
Reserved.
TMR_VAL. (Read Only) This bit field contains the running count of the power management timer.
Offset 20h
PM2_CNT — PM2 Control Register (R/W)
Reset Value: 00h
Reset Value: 00h
7:1
0
Reserved.
Arbiter Disable. Disables the PCI arbiter when set by the OS. Used during C3 transition.
0: Arbiter not disabled. (Default)
1: Disable arbiter.
Offset 21h-FFh
Reserved
The read value for these registers is undefined.
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5.4.3 IDE Controller Registers - Function 2
The register space designated as Function 2 (F2) is used
to configure Channels 0 and 1 and the PCI portion of sup-
port hardware for the IDE controllers. The bit formats for
the PCI Header/Channels 0 and 1 Registers are given in
Table 5-35.
Located in the PCI Header Registers of F2 is a Base
Address Register (F2BAR4) used for pointing to the regis-
ter space designated for support of the IDE controllers,
described later in this section.
Table 5-35. F2: PCI Header/Channels 0 and 1 Registers for IDE Controller Configuration
Bit
Description
Index 00h-01h
Index 02h-03h
Index 04h-05h
Vendor Identification Register (RO)
Device Identification Register (RO)
PCI Command Register (R/W)
Reset Value: 100Bh
Reset Value: 0502h
Reset Value: 0000h
15:3
2
Reserved. (Read Only)
Bus Master. Allow the Core Logic module bus mastering capabilities.
0: Disable.
1: Enable. (Default)
This bit must be set to 1.
1
0
Reserved. (Read Only)
I/O Space. Allow the Core Logic module to respond to I/O cycles from the PCI bus.
0: Disable.
1: Enable.
This bit must be enabled, in order to access I/O offsets through F2BAR4 (for more information see F2 Index 20h).
Index 06h-07h
Index 08h
PCI Status Register (RO)
Device Revision ID Register (RO)
PCI Class Code Register (RO)
PCI Cache Line Size Register (RO)
PCI Latency Timer Register (RO)
PCI Header Type (RO)
Reset Value: 0280h
Reset Value: 01h
Index 09h-0Bh
Index 0Ch
Reset Value: 010180h
Reset Value: 00h
Index 0Dh
Reset Value: 00h
Index 0Eh
Reset Value: 00h
Index 0Fh
PCI BIST Register (RO)
Reset Value: 00h
Index 10h-13h
Base Address Register 0 - F2BAR0 (RO)
Reset Value: 00000000h
Reserved. Reserved for possible future use by the Core Logic module.
Index 14h-17h
Base Address Register 1 - F2BAR1 (RO)
Reset Value: 00000000h
Reset Value: 00000000h
Reset Value: 00000000h
Reset Value: 00000001h
Reserved. Reserved for possible future use by the Core Logic module.
Index 18h-1Bh
Base Address Register 2 - F2BAR2 (RO)
Reserved. Reserved for possible future use by the Core Logic module.
Index 1Ch-1Fh
Base Address Register 3 - F2BAR3 (RO)
Reserved. Reserved for possible future use by the Core Logic module.
Index 20h-23h
Base Address Register 4 - F2BAR4 (R/W)
Base Address 0 Register. This register allows access to I/O mapped Bus Mastering IDE registers. Bits [3:0] are read only (0001), indi-
cating a 16-byte I/O address range. Refer to Table 5-36 on page 270 for the IDE controller register bit formats and reset values.
31:4
3:0
Bus Mastering IDE Base Address.
Address Range. (Read Only)
Index 24h-2Bh
Index 2Ch-2Dh
Index 2Eh-2Fh
Index 30h-3Fh
Reserved
Subsystem Vendor ID (RO)
Subsystem ID (RO)
Reserved
Reset Value: 00h
Reset Value: 100Bh
Reset Value: 0502h
Reset Value: 00h
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Table 5-35. F2: PCI Header/Channels 0 and 1 Registers for IDE Controller Configuration (Continued)
Bit
Description
Index 40h-43h
Channel 0 Drive 0 PIO Register (R/W)
Reset Value: 00009172h
If Index 44h[31] = 0, Format 0. The bits in this register select the slowest PIO mode per channel for commands.
Format 0 settings for a Fast-PCI clock frequency of 33.3 MHz:
— PIO Mode 0 = 00009172h
— PIO Mode 1 = 00012171h
— PIO Mode 2 = 00020080h
— PIO Mode 3 = 00032010h
— PIO Mode 4 = 00040010h
Format 0 settings for a Fast-PCI clock frequency of 48 MHz:
— PIO Mode 0 = 0000FAA3h
— PIO Mode 1 = 0001C232h
— PIO Mode 2 = 00025131h
— PIO Mode 3 = 00033121h
— PIO Mode 4 = 00041021h
Format 0 settings for a Fast-PCI clock frequency of 66.7 MHz:
— PIO Mode 0 = 0000FFF4h
— PIO Mode 1 = 0001F353h
— PIO Mode 2 = 00028141h
— PIO Mode 3 = 00034231h
— PIO Mode 4 = 00041131h
Note: All references to "cycle" in the following bit descriptions are to a Fast-PCI clock cycle.
31:20
19:16
15:12
11:8
7:4
Reserved. Must be set to 0.
PIOMODE. PIO mode.
t2I. Recovery time (value + 1 cycle).
t3. IDE_IOW# data setup time (value + 1 cycle).
t2W. IDE_IOW# width minus t3 (value + 1 cycle).
t1. Address Setup Time (value + 1 cycle).
3:0
If Index 44h[31] = 1, Format 1. The bits in this register allow independent control of command and data.
Format 1 settings for a Fast-PCI clock frequency of 33.3 MHz:
— PIO Mode 0 = 9172D132h
— PIO Mode 1 = 21717121h
— PIO Mode 2 = 00803020h
— PIO Mode 3 = 20102010h
— PIO Mode 4 = 00100010h
Format 1 settings for a Fast-PCI clock frequency of 48 MHz:
— PIO Mode 0 = E2A3F383h
— PIO Mode 1 = 42A2B232h
— PIO Mode 2 = 11B16121h
— PIO Mode 3 = 31213121h
— PIO Mode 4 = 10211021h
Format 1 settings for a Fast-PCI clock frequency of 66.7 MHz:
— PIO Mode 0 = F8E4F8E4h
— PIO Mode 1 = 53F3F353h
— PIO Mode 2 = 13F18141h
— PIO Mode 3 = 42314231h
— PIO Mode 4 = 11311131h
Note: All references to "cycle" in the following bit descriptions are to a Fast-PCI clock cycle.
31:28
27:24
23:20
19:16
15:12
11:8
t2IC. Command cycle recovery time (value + 1 cycle).
t3C. Command cycle IDE_IOW# data setup (value + 1 cycle).
t2WC. Command cycle IDE_IOW# pulse width minus t3 (value + 1 cycle).
t1C. Command cycle address setup time (value + 1 cycle).
t2ID. Data cycle recovery time (value + 1 cycle).
t3D. Data cycle IDE_IOW# data setup (value + 1 cycle).
t2WD. Data cycle IDE_IOW# pulse width minus t3 (value + 1 cycle).
t1D. Data cycle address Setup Time (value + 1 cycle).
7:4
3:0
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Core Logic Module (Continued)
Table 5-35. F2: PCI Header/Channels 0 and 1 Registers for IDE Controller Configuration (Continued)
Bit
Description
Index 44h-47h
Channel 0 Drive 0 DMA Control Register (R/W)
Reset Value: 00077771h
The structure of this register depends on the value of bit 20.
If bit 20 = 0, Multiword DMA
Settings for a Fast-PCI clock frequency of 33.3 MHz:
— Multiword DMA Mode 0 = 00077771h
— Multiword DMA Mode 1 = 00012121h
— Multiword DMA Mode 2 = 00002020h
Settings for a Fast-PCI clock frequency of 48 MHz:
— Multiword DMA Mode 0 = 000BBBB2h
— Multiword DMA Mode 1 = 00024241h
— Multiword DMA Mode 2 = 00013131h
Settings for a Fast-PCI clock frequency of 66.7 MHz:
— Multiword DMA Mode 0 = 000FFFF3h
— Multiword DMA Mode 1 = 00035352h
— Multiword DMA Mode 2 = 00015151h
Note: All references to "cycle" in the following bit descriptions are to a Fast-PCI clock cycle.
31
PIO Mode Format. This bit sets the PIO mode format for all channels and drives. Bit 31 of Offsets 2Ch, 34h, and 3Ch are
R/W, but have no function so are defined as reserved.
0: Format 0.
1
Format 1.
30:21
20
Reserved. Must be set to 0.
DMA Select. Selects type of DMA operation. 0: Multiword DMA
tKR. IDE_IOR# recovery time (4-bit) (value + 1 cycle).
tDR. IDE_IOR# pulse width (value + 1 cycle).
19:16
15:12
11:8
7:4
tKW. IDE_IOW# recovery time (4-bit) (value + 1 cycle).
tDW. IDE_IOW# pulse width (value + 1 cycle).
3:0
tM. IDE_CS[1:0]# to IDE_IOR#/IOW# setup; IDE_CS[1:0]# setup to IDE_DACK0#/DACK1#.
If bit 20 = 1, UltraDMA
Settings for a Fast-PCI clock frequency of 33.3 MHz:
— UltraDMA Mode 0 = 00921250h
— UltraDMA Mode 1 = 00911140h
— UltraDMA Mode 2 = 00911030h
Settings for a Fast-PCI clock frequency of 48 MHz:
— UltraDMA Mode 0 = 00932470h
— UltraDMA Mode 1 = 00922260h
— UltraDMA Mode 2 = 00922140h
Settings for a Fast-PCI clock frequency of 66.7 MHz:
— UltraDMA Mode 0 = 009436A1h
— UltraDMA Mode 1 = 00933481h
— UltraDMA Mode 2 = 00923261h
Note: All references to "cycle" in the following bit descriptions are to a Fast-PCI clock cycle.
31
PIO Mode Format. This bit sets the PIO mode format for all channels and drives. Bit 31 of Offsets 2Ch, 34h, and 3Ch are
R/W, but have no function so are defined as reserved.
0: Format 0
1: Format 1
30:24
23:21
20
Reserved. Must be set to 0.
BSIZE. Input buffer threshold.
DMA Select. Selects type of DMA operation. 1: UltraDMA.
tCRC. CRC setup UDMA in IDE_DACK# (value + 1 cycle) (for host terminate CRC setup = tMLI + tSS).
tSS. UDMA out (value + 1 cycle).
19:16
15:12
11:8
7:4
tCYC. Data setup and cycle time UDMA out (value + 2 cycles).
tRP. Ready to pause time (value + 1 cycle). Note: tRFS + 1 tRP on next clock.
tACK. IDE_CS[1:0]# setup to IDE_DACK0#/DACK1# (value + 1 cycle).
3:0
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Table 5-35. F2: PCI Header/Channels 0 and 1 Registers for IDE Controller Configuration (Continued)
Bit
Description
Index 48h-4Bh
Channel 0 Drive 1 PIO Register (R/W)
Reset Value: 00009172h
Reset Value: 00077771h
Channel 0 Drive 1 Programmed I/O Control Register. See F2 Index 40h for bit descriptions.
Index 4Ch-4Fh
Channel 0 Drive 1 DMA Control Register (R/W)
Channel 0 Drive 1 MDMA/UDMA Control Register. See F2 Index 44h for bit descriptions.
Note: The PIO Mode format is selected in F2 Index 44h[31], bit 31 of this register is defined as reserved.
Index 50h-53h
Channel 1 Drive 0 PIO Register (R/W)
Reset Value: 00009172h
Reset Value: 00077771h
Channel 1 Drive 0 Programmed I/O Control Register. See F2 Index 40h for bit descriptions.
Index 54h-57h
Channel 1 Drive 0 DMA Control Register (R/W)
Channel 1 Drive 0 MDMA/UDMA Control Register. See F2 Index 44h for bit descriptions.
Note: The PIO Mode format is selected in F2 Index 44h[31], bit 31 of this register is defined as reserved.
Index 58h-5Bh
Channel 1 Drive 1 PIO Register (R/W)
Reset Value: 00009172h
Reset Value: 00077771h
Channel 1 Drive 1 Programmed I/O Control Register. See F2 Index 40h for bit descriptions.
Index 5Ch-5Fh
Channel 1 Drive 1 DMA Control Register (R/W)
Channel 1 Drive 1 MDMA/UDMA Control Register. See F2 Index 44h for bit descriptions.
Note: The PIO Mode format is selected in F2 Index 44h[31], bit 31 of this register is defined as reserved.
Index 60h-FFh
Reserved
Reset Value: 00h
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Core Logic Module (Continued)
5.4.3.1 IDE Controller Support Registers
F2 Index 20h, Base Address Register 4 (F2BAR4), points
to the base address of where the registers for IDE control-
ler configuration are located. Table 5-36 gives the bit for-
mats of the I/O mapped IDE Controller Configuration
registers that are accessed through F2BAR4.
Table 5-36. F2BAR4+I/O Offset: IDE Controller Configuration Registers
Bit
Description
Offset 00h
IDE Bus Master 0 Command Register — Primary (R/W)
Reset Value: 00h
7:4
3
Reserved. Must be set to 0. Must return 0 on reads.
Read or Write Control. Sets the direction of bus master transfers.
0: PCI reads performed.
1: PCI writes performed.
This bit should not be changed when the bus master is active.
Reserved. Must be set to 0. Must return 0 on reads.
Bus Master Control. Controls the state of the bus master.
0: Disable master.
2:1
0
1: Enable master.
Bus master operations can be halted by setting this bit to 0. Once an operation has been halted, it cannot be resumed. If this
bit is set to 0 while a bus master operation is active, the command is aborted and the data transferred from the drive is dis-
carded. This bit should be reset after completion of data transfer.
Offset 01h
Not Used
Offset 02h
IDE Bus Master 0 Status Register — Primary (R/W)
Reset Value: 00h
7
Simplex Mode. (Read Only) Indicates if both the primary and secondary channel operate independently.
0: Yes.
1: No (simplex mode).
6
5
Drive 1 DMA Enable. When asserted, allows Drive 1 to perform DMA transfers.
0: Disable.
1: Enable.
Drive 0 DMA Enable. When asserted, allows Drive 0 to perform DMA transfers.
0: Disable.
1: Enable.
4:3
2
Reserved. Must be set to 0. Must return 0 on reads.
Bus Master Interrupt. Indicates if the bus master detected an interrupt.
0: No.
1: Yes. Write 1 to clear.
1
0
Bus Master Error. Indicates if the bus master detected an error during data transfer.
0: No.
1: Yes. Write 1 to clear.
Bus Master Active. Indicates if the bus master is active.
0: No.
1: Yes.
Offset 03h
Not Used
Offset 04h-07h
IDE Bus Master 0 PRD Table Address — Primary (R/W)
Reset Value: 00000000h
31:2
Pointer to the Physical Region Descriptor Table. This bit field contains a PRD table pointer for IDE Bus Master 0.
When written, this field points to the first entry in a PRD table. Once IDE Bus Master 0 is enabled (Command Register bit 0
= 1), it loads the pointer and updates this field (by adding 08h) so that is points to the next PRD.
When read, this register points to the next PRD.
1:0
Reserved. Must be set to 0.
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Table 5-36. F2BAR4+I/O Offset: IDE Controller Configuration Registers (Continued)
Bit
Description
Offset 08h
IDE Bus Master 1 Command Register — Secondary (R/W)
Reserved. Must be set to 0. Must return 0 on reads.
Reset Value: 00h
7:4
3
Read or Write Control. Sets the direction of bus master transfers.
0: PCI reads are performed.
1: PCI writes are performed.
This bit should not be changed when the bus master is active.
Reserved. Must be set to 0. Must return 0 on reads.
Bus Master Control. Controls the state of the bus master.
0: Disable master.
2:1
0
1: Enable master.
Bus master operations can be halted by setting this bit to 0. Once an operation has been halted, it cannot be resumed. If this
bit is set to 0 while a bus master operation is active, the command is aborted and the data transferred from the drive is dis-
carded. This bit should be reset after completion of data transfer.
Offset 09h
Offset 0Ah
Not Used
IDE Bus Master 1 Status Register — Secondary (R/W)
Reset Value: 00h
7
6
Reserved. (Read Only)
Drive 1 DMA Capable. Allow Drive 1 to perform DMA transfers.
0: Disable.
1: Enable.
5
Drive 0 DMA Capable. Allow Drive 0 to perform DMA transfers.
0: Disable.
1: Enable.
4:3
2
Reserved. Must be set to 0. Must return 0 on reads.
Bus Master Interrupt. Indicates if the bus master detected an interrupt.
0: No.
1: Yes. Write 1 to clear.
1
0
Bus Master Error. Indicates if the bus master detected an error during data transfer.
0: No.
1: Yes. Write 1 to clear.
Bus Master Active. Indicates if the bus master is active.
0: No.
1: Yes.
Offset 0Bh
Not Used
Offset 0Ch-0Fh
IDE Bus Master 1 PRD Table Address — Secondary (R/W)
Reset Value: 00000000h
31:2
Pointer to the Physical Region Descriptor Table. This bit field contains a PRD table pointer for IDE Bus Master 1.
When written, this field points to the first entry in a PRD table. Once IDE Bus Master 1 is enabled (Command Register bit 0
= 1), it loads the pointer and updates this field (by adding 08h) so that is points to the next PRD.
When read, this register points to the next PRD.
1:0
Reserved. Must be set to 0.
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Core Logic Module (Continued)
5.4.4 Audio Registers - Function 3
A Base Address register (F3BAR0), located in the PCI
Header registers of F3, is used for pointing to the register
space designated for support of audio, described later in
this section.
The register designated as Function 3 (F3) is used to con-
figure the PCI portion of support hardware for the audio
registers. The bit formats for the PCI Header registers are
given in Table 5-37.
Table 5-37. F3: PCI Header Registers for Audio Configuration
Bit
Description
Index 00h-01h
Index 02h-03h
Index 04h-05h
Vendor Identification Register (RO)
Device Identification Register (RO)
PCI Command Register (R/W)
Reset Value: 100Bh
Reset Value: 0503h
Reset Value: 0000h
15:3
2
Reserved. (Read Only)
Bus Master. Allow the Core Logic module bus mastering capabilities.
0: Disable.
1: Enable. (Default)
This bit must be set to 1.
1
0
Memory Space. Allow the Core Logic module to respond to memory cycles from the PCI bus.
0: Disable.
1: Enable.
This bit must be enabled to access memory offsets through F3BAR0 (See F3 Index 10h).
Reserved. (Read Only)
Index 06h-07h
Index 08h
PCI Status Register (RO)
Device Revision ID Register (RO)
PCI Class Code Register (RO)
PCI Cache Line Size Register (RO)
PCI Latency Timer Register (RO)
PCI Header Type (RO)
Reset Value: 0280h
Reset Value: 00h
Index 09h-0Bh
Index 0Ch
Reset Value: 040100h
Reset Value: 00h
Index 0Dh
Reset Value: 00h
Index 0Eh
Reset Value: 00h
Index 0Fh
PCI BIST Register (RO)
Reset Value: 00h
Index 10h-13h
Base Address Register - F3BAR0 (R/W)
Reset Value: 00000000h
This register sets the base address of the memory mapped audio interface control register block. This is a 128-byte block of registers
used to control the audio FIFO and codec interface, as well as to support VSA SMIs. Bits [11:0] are read only (0000 0000 0000), indicat-
ing a 4 KB memory address range. Refer to Table 5-38 on page 273 for the audio configuration register bit formats and reset values.
31:12
11:0
Audio Interface Base Address
Address Range. (Read Only)
Index 14h-2Bh
Index 2Ch-2Dh
Index 2Eh-2Fh
Index 30h-FFh
Reserved
Subsystem Vendor ID (RO)
Subsystem ID (RO)
Reserved
Reset Value: 00h
Reset Value: 100Bh
Reset Value: 0503h
Reset Value: 00h
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5.4.4.1 Audio Support Registers
F3 Index 10h, Base Address Register 0 (F3BAR0), points
to the base address of where the registers for audio sup-
port are located. Table 5-38 gives the bit formats of the
memory mapped audio configuration registers that are
accessed through F3BAR0.
Table 5-38. F3BAR0+Memory Offset: Audio Configuration Registers
Bit
Description
Offset 00h-03h
Codec GPIO Status Register (R/W)
Reset Value: 00000000h
31
30
Codec GPIO Interface.
0: Disable.
1: Enable.
Codec GPIO SMI. When asserted, allows codec GPIO interrupt to generate an SMI.
0: Disable.
1: Enable.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[1].
Second level SMI status is reported at F3BAR0+Memory Offset 10h/12h[1].
29:21
20
Reserved. Must be set to 0.
Codec GPIO Status Valid. (Read Only) Indicates if the status read is valid.
0: Yes.
1: No.
19:0
Codec GPIO Pin Status. (Read Only) This field indicates the GPIO pin status that is received from the codec in slot 12 on
the SDATA_IN signal.
Offset 04h-07h
Codec GPIO Control Register (R/W)
Reset Value: 00000000h
31:20
19:0
Reserved. Must be set to 0.
Codec GPIO Pin Data. This field indicates the GPIO pin data that is sent to the codec in slot 12 on the SDATA_OUT signal.
Codec Status Register (R/W) Reset Value: 00000000h
Offset 08h-0Bh
31:24
Codec Status Address. (Read Only) Address of the register for which status is being returned. This address comes from
slot 1 bits [19:12].
23
Codec Serial INT Enable. When asserted, allows codec serial interrupt to cause an SMI.
0: Disable.
1: Enable.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[1].
Second level SMI status is reported at F3BAR0+Memory Offset 10h/12h[1].
22
21
20
19
SYNC Pin. Sets SYNC high or low.
0: Low.
1: High.
SDATA_IN2_EN. When enabled, allows use of SDATA_IN2 input.
0: Disable.
1: Enable.
Audio Bus Master 5 AC97 Slot Select. Selects slot for Audio Bus Master 5 to receive data.
0: Slot 6.
1: Slot 11.
Audio Bus Master 4 AC97 Slot Select. Selects slot for Audio Bus Master 4 to transmit data.
0: Slot 6.
1: Slot 11.
18
17
Reserved. Must be set to 0.
Status Tag. (Read Only) The codec status data in bits [15:0] of this register is updated in the current AC97 frame. (codec
ready, slot1 and slot2 bits in tag slot are all set in current AC97 frame).
0: Not new.
1: New, updated in current frame.
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Table 5-38. F3BAR0+Memory Offset: Audio Configuration Registers (Continued)
Bit
Description
16
Codec Status Valid. (Read Only) Indicates if the status in bits [15:0] of this register is valid. This bit is high during slots 3 to
11 of the AC97 frame (i.e., for approximately 14.5 µs), for every frame.
0: No.
1: Yes.
15:0
Codec Status. (Read Only) This is the codec status data that is received from the codec in slot 2 on SDATA_IN. Only bits
[19:4] are used from slot 2. If this register is read with both bits 16 and 17 of this register set to 1, this field is updated in the
current AC97 frame, and codec status data is valid. This bit field is updated only if the codec sent status data.
Offset 0Ch-0Fh
Codec Command Register (R/W)
Reset Value: 00000000h
31:24
Codec Command Address. Address of the codec control register for which the command is being sent. This address goes
in slot 1 bits [19:12] on SDATA_OUT.
23:22
Codec Communication. Indicates the codec that the Core Logic module is communicating with.
00: Primary codec
01: Secondary codec
10: Third codec
11: Fourth codec
Only 00 and 01 are valid settings for this bit field.
21:17
16
Reserved. Must be set to 0.
Codec Command Valid. (Read Only) Indicates if the command in bits [15:0] of this register is valid.
0: No.
1: Yes.
This bit is set by hardware when a codec command is written to the Codec Command register. It remains set until the com-
mand has been sent to the codec.
15:0
Codec Command. This is the command being sent to the codec in bits [19:4] of slot 2 on SDATA_OUT.
Offset 10h-11h
Second Level Audio SMI Status Register (RC)
Reset Value: 0000h
The bits in this register contain second level SMI status reporting. Top level is reported at F1BAR0+I/O Offset 00h/02h[1]. Reading this
register clears the status bits at both the second and top levels. Note that bit 0 has a third level of status reporting which also must be
"read to clear".
A read-only “Mirror” version of this register exists at F3BAR0+I/O Memory Offset 12h. If the value of the register must be read without
clearing the SMI source (and consequently de-asserting SMI), F3BAR0+Memory Offset 12h can be read instead.
15:8
7
Reserved. Must be set to 0.
Audio Bus Master 5 SMI Status. Indicates if an SMI was caused by an event occurring on Audio Bus Master 5.
0: No.
1: Yes.
SMI generation is enabled when Audio Bus Master 5 is enabled (F3BAR0+Memory Offset 48h[0] = 1).
An SMI is then generated when the End of Page bit is set in the Audio Bus Master 5 SMI Status Register (F3BAR0+Memory
Offset 49h[0] = 1).
6
5
Audio Bus Master 4 SMI Status. Indicates if an SMI was caused by an event occurring on Audio Bus Master 4.
0: No.
1: Yes.
SMI generation is enabled when Audio Bus Master 4 is enabled (F3BAR0+Memory Offset 40h[0] = 1).
An SMI is then generated when the End of Page bit is set in the Audio Bus Master 4 SMI Status Register (F3BAR0+Memory
Offset 41h[0] = 1).
Audio Bus Master 3 SMI Status. Indicates if an SMI was caused by an event occurring on Audio Bus Master 3.
0: No.
1: Yes.
SMI generation is enabled when Audio Bus Master 3 is enabled (F3BAR0+Memory Offset 38h[0] = 1).
An SMI is then generated when the End of Page bit is set in the Audio Bus Master 3 SMI Status Register (F3BAR0+Memory
Offset 39h[0] = 1).
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Table 5-38. F3BAR0+Memory Offset: Audio Configuration Registers (Continued)
Bit
Description
4
Audio Bus Master 2 SMI Status. Indicates if an SMI was caused by an event occurring on Audio Bus Master 2.
0: No.
1: Yes.
SMI generation is enabled when Audio Bus Master 2 is enabled (F3BAR0+Memory Offset 30h[0] = 1).
An SMI is then generated when the End of Page bit is set in the Audio Bus Master 2 SMI Status Register (F3BAR0+Memory
Offset 31h[0] = 1).
3
2
Audio Bus Master 1 SMI Status. Indicates if an SMI was caused by an event occurring on Audio Bus Master 1.
0: No.
1: Yes.
SMI generation is enabled when Audio Bus Master 1 is enabled (F3BAR0+Memory Offset 28h[0] = 1).
An SMI is then generated when the End of Page bit is set in the Audio Bus Master 1 SMI Status Register (F3BAR0+Memory
Offset 29h[0] = 1).
Audio Bus Master 0 SMI Status. Indicates if an SMI was caused by an event occurring on Audio Bus Master 0.
0: No.
1: Yes.
SMI generation is enabled when Audio Bus Master 0 is enabled (F3BAR0+Memory Offset 20h[0] = 1).
An SMI is then generated when the End of Page bit is set in the Audio Bus Master 0 SMI Status Register (F3BAR0+Memory
Offset 21h[0] = 1).
1
0
Codec Serial or GPIO Interrupt SMI Status. Indicates if an SMI was caused by a serial or GPIO interrupt from codec.
0: No.
1: Yes.
SMI generation enabling for codec serial interrupt: F3BAR0+Memory Offset 08h[23] = 1.
SMI generation enabling for codec GPIO interrupt: F3BAR0+Memory Offset 00h[30] = 1.
I/O Trap SMI Status. Indicates if an SMI was caused by an I/O trap.
0: No.
1: Yes.
The next level (third level) of SMI status reporting is at F3BAR0+Memory Offset 14h.
Offset 12h-13h
Second Level Audio SMI Status Mirror Register (RO)
Reset Value: 0000h
Note: The bits in this register contain second level SMI status reporting. Top level is reported at F1BAR0+I/O Offset 00h/02h[1].
Reading this register does not clear the status bits. See F3BAR0+Memory Offset 10h.
15:8
7
Reserved. Must be set to 0.
Audio Bus Master 5 SMI Status. Indicates if an SMI was caused by an event occurring on Audio Bus Master 5.
0: No.
1: Yes.
SMI generation is enabled when Audio Bus Master 5 is enabled (F3BAR0+Memory Offset 48h[0] = 1). An SMI is then gen-
erated when the End of Page bit is set in the SMI Status Register (F3BAR0+Memory Offset 49h[0] = 1). The End of Page bit
must be cleared before this bit can be cleared.
6
5
Audio Bus Master 4 SMI Status. Indicates if an SMI was caused by an event occurring on Audio Bus Master 4.
0: No.
1: Yes.
SMI generation is enabled when Audio Bus Master 4 is enabled (F3BAR0+Memory Offset 40h[0] = 1). An SMI is then gen-
erated when the End of Page bit is set in the SMI Status Register (F3BAR0+Memory Offset 41h[0] = 1). The End of Page bit
must be cleared before this bit can be cleared.
Audio Bus Master 3 SMI Status. Indicates if an SMI was caused by an event occurring on Audio Bus Master 3.
0: No.
1: Yes.
SMI generation is enabled when Audio Bus Master 3 is enabled (F3BAR0+Memory Offset 38h[0] = 1). An SMI is then gen-
erated when the End of Page bit is set in the SMI Status Register (F3BAR0+Memory Offset 39h[0] = 1). The End of Page bit
must be cleared before this bit can be cleared.
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Core Logic Module (Continued)
Table 5-38. F3BAR0+Memory Offset: Audio Configuration Registers (Continued)
Bit
Description
4
Audio Bus Master 2 SMI Status. Indicates if an SMI was caused by an event occurring on Audio Bus Master 2.
0: No.
1: Yes.
SMI generation is enabled when Audio Bus Master 2 is enabled (F3BAR0+Memory Offset 30h[0] = 1). An SMI is then gen-
erated when the End of Page bit is set in the SMI Status Register (F3BAR0+Memory Offset 31h[0] = 1). The End of Page bit
must be cleared before this bit can be cleared.
3
2
Audio Bus Master 1 SMI Status. Indicates if an SMI was caused by an event occurring on Audio Bus Master 1.
0: No.
1: Yes.
SMI generation is enabled when Audio Bus Master 1 is enabled (F3BAR0+Memory Offset 28h[0] = 1). An SMI is then gen-
erated when the End of Page bit is set in the SMI Status Register (F3BAR0+Memory Offset 29h[0] = 1). The End of Page bit
must be cleared before this bit can be cleared.
Audio Bus Master 0 SMI Status. Indicates if an SMI was caused by an event occurring on Audio Bus Master 0.
0: No.
1: Yes.
SMI generation is enabled when Audio Bus Master 0 is enabled (F3BAR0+Memory Offset 20h[0] = 1). An SMI is then gen-
erated when the End of Page bit is set in the SMI Status Register (F3BAR0+Memory Offset 21h[0] = 1). The End of Page bit
must be cleared before this bit can be cleared.
1
0
Codec Serial or GPIO Interrupt SMI Status. Indicates if an SMI was caused by a serial or GPIO interrupt from codec.
0: No.
1: Yes.
SMI generation enabling for codec serial interrupt: F3BAR0+Memory Offset 08h[23] = 1.
SMI generation enabling for codec GPIO interrupt: F3BAR0+Memory Offset 00h[30] = 1.
I/O Trap SMI Status. Indicates if an SMI was caused by an I/O trap.
0: No.
1: Yes.
The next level (third level) of SMI status reporting is at F3BAR0+Memory Offset 14h.
Offset 14h-17h
I/O Trap SMI and Fast Write Status Register (RO/RC)
Reset Value: 00000000h
Note: For the four SMI status bits (bits [13:10]), if the activity was a fast write to an even address, no SMI is generated regardless of
the DMA, MPU, or Sound Card status. If the activity was a fast write to an odd address, an SMI is generated but bit 13 is set to
a 1.
31:24
23:16
Fast Path Write Even Access Data. (Read Only) This bit field contains the data from the last Fast Path Write Even
access. These bits change only on a fast write to an even address.
Fast Path Write Odd Access Data. (Read Only) This bit field contains the data from the last Fast Path Write Odd access.
These bits change on a fast write to an odd address, and also on any non-fast write.
15
14
Fast Write A1. (Read Only) This bit contains the A1 value for the last Fast Write access.
Read or Write I/O Access. (Read Only) Indicates if the last trapped I/O access was a read or a write.
0: Read.
1: Write.
13
Sound Card or FM Trap SMI Status. (Read to Clear) Indicates if an SMI was caused by a trapped I/O access to the Sound
Card or FM I/O Trap.
0: No.
1: Yes. (See the note included in the general description of this register above.)
Fast Path Write must be enabled, F3BAR0+Memory Offset 18h[11] = 1, for the SMI to be reported here. If Fast Path Write is
disabled, the SMI is reported in bit 10 of this register.
This is the third level of SMI status reporting.
Second level SMI status is reported at F3BAR0+Memory Offset 10h/12h[0].
Top level is reported at F1BAR0+I/O Offset 00h/02h[1].
SMI generation enabling is at F3BAR0+Memory Offset 18h[2].
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Table 5-38. F3BAR0+Memory Offset: Audio Configuration Registers (Continued)
Bit
Description
12
DMA Trap SMI Status. (Read to Clear) Indicates if an SMI was caused by a trapped I/O access to the DMA I/O Trap.
0: No.
1: Yes. (See the note included in the general description of this register above.)
This is the third level of SMI status reporting.
Second level SMI status is reported at F3BAR0+Memory Offset 10h/12h[0].
Top level is reported at F1BAR0+I/O Offset 00h/02h[1].
SMI generation enabling is at F3BAR0+Memory Offset 18h[8:7].
MPU Trap SMI Status. (Read to Clear) Indicates if an SMI was caused by a trapped I/O access to the MPU I/O Trap.
0: No.
11
1: Yes. (See the note included in the general description of this register above.)
This is the third level of SMI status reporting.
Second level of SMI status is reported at F3BAR0+Memory Offset 10h/12h[0].
Top level is reported at F1BAR0+I/O Offset 00h/02h[1].
SMI generation enabling is at F3BAR0+Memory Offset 18h[6:5].
10
Sound Card or FM Trap SMI Status. (Read to Clear) Indicates if an SMI was caused by a trapped I/O access to the Sound
Card or FM I/O Trap.
0: No.
1: Yes. (See the note included in the general description of this register above.)
Fast Path Write must be disabled, F3BAR0+Memory Offset 18h[11] = 0, for the SMI to be reported here. If Fast Path Write
is enabled, the SMI is reported in bit 13 of this register.
This is the third level of SMI status reporting.
Second level of SMI status is reported at F3BAR0+Memory Offset 10h/12h[0].
Top level is reported at F1BAR0+I/O Offset 00h/02h[1].
SMI generation enabling is at F3BAR0+Memory Offset 18h[2].
9:0
X-Bus Address (Read Only). This bit field] contains the captured ten bits of X-Bus address.
Offset 18h-19h
I/O Trap SMI Enable Register (R/W
)Reset Value: 0000h
15:12
11
Reserved. Must be set to 0.
Fast Path Write Enable. Fast Path Write (an SMI is not generated on certain writes to specified addresses).
0: Disable.
1: Enable.
In Fast Path Write, the Core Logic module responds to writes to addresses: 388h, 38Ah, 38B, 2x0h, 2x2h, and 2x8h.
10:9
8
Fast Read. These two bits hold part of the response that the Core Logic module returns for reads to several I/O locations.
High DMA I/O Trap. If this bit is enabled and an access occurs at I/O Port C0h-DFh, an SMI is generated.
0: Disable.
1: Enable.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[1].
Second level SMI status is reported at F3BAR0+Memory Offset 10h/12h[0].
Third level SMI status is reported at F3BAR0+Memory Offset 14h[12].
7
6
Low DMA I/O Trap. If this bit is enabled and an access occurs at I/O Port 00h-0Fh, an SMI is generated.
0: Disable.
1: Enable.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[1].
Second level SMI status is reported at F3BAR0+Memory Offset 10h/12h[0].
Third level SMI status is reported at F3BAR0+Memory Offset 14h[12].
High MPU I/O Trap. If this bit is enabled and an access occurs at I/O Port 330h-331h, an SMI is generated.
0: Disable.
1: Enable.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[1].
Second level SMI status is reported at F3BAR0+Memory Offset 10h/12h[0].
Third level SMI status is reported at F3BAR0+Memory Offset 14h[11].
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Table 5-38. F3BAR0+Memory Offset: Audio Configuration Registers (Continued)
Bit
Description
5
Low MPU I/O Trap. If this bit is enabled and an access occurs at I/O Port 300h-301h, an SMI is generated.
0: Disable.
1: Enable.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[1].
Second level SMI status is reported at F3BAR0+Memory Offset 10h/12h[0].
Third level SMI status is reported at F3BAR0+Memory Offset 14h[11].
4
Fast Path Read Enable/SMI Disable. When asserted, read Fast Path (an SMI is not generated on reads from specified
addresses).
0: Disable.
1: Enable.
In Fast Path Read the Core Logic module responds to reads of addresses: 388h-38Bh; 2x0h, 2x1, 2x2h, 2x3, 2x8 and 2x9h.
If neither sound card nor FM I/O mapping is enabled, then status read trapping is not possible.
3
2
FM I/O Trap. If this bit is enabled and an access occurs at I/O Port 388h-38Bh, an SMI is generated.
0: Disable.
1: Enable.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[1].
Second level SMI status is reported at F3BAR0+Memory Offset 10h/12h[0].
Sound Card I/O Trap. If this bit is enabled and an access occurs in the address ranges selected by bits [1:0], an SMI is gen-
erated.
0: Disable.
1: Enable.
Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[1].
Second level SMI status is reported at F3BAR0+Memory Offset 10h/12h[0].
Third level SMI status is reported at F3BAR0+Memory Offset 14h[10].
1:0
Sound Card Address Range Select. These bits select the address range for the sound card I/O trap.
00: I/O Port 220h-22Fh
01: I/O Port 240h-24Fh
10: I/O Port 260h-26Fh
11: I/O Port 280h-28Fh
Offset 1Ah-1Bh
Internal IRQ Enable Register (R/W)
Reset Value: 0000h
15
IRQ15 Internal. Configures IRQ15 for internal (software) or external (hardware) use.
0: External.
1: Internal.
14
IRQ14 Internal. Configures IRQ14 for internal (software) or external (hardware) use.
0: External.
1: Internal.
13
12
Reserved. Must be set to 0.
IRQ12 Internal. Configures IRQ12 for internal (software) or external (hardware) use.
0: External.
1: Internal.
11
10
9
IRQ11 Internal. Configures IRQ11 for internal (software) or external (hardware) use.
0: External.
1: Internal.
IRQ10 Internal. Configures IRQ10 for internal (software) or external (hardware) use.
0: External.
1: Internal.
IRQ9 Internal. Configures IRQ9 for internal (software) or external (hardware) use.
0: External.
1: Internal.
8
7
Reserved. Must be set to 0.
IRQ7 Internal. Configures IRQ7 for internal (software) or external (hardware) use.
0: External.
1: Internal.
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Table 5-38. F3BAR0+Memory Offset: Audio Configuration Registers (Continued)
Bit
Description
6
5
Reserved. Must be set to 0.
IRQ5 Internal. Configures IRQ5 for internal (software) or external (hardware) use.
0: External.
1: Internal.
4
3
IRQ4 Internal. Configures IRQ4 for internal (software) or external (hardware) use.
0: External.
1: Internal.
IRQ3 Internal. Configures IRQ3 for internal (software) or external (hardware) use.
0: External.
1: Internal.
2:0
Reserved. Must be set to 0.
Offset 1Ch-1Fh
Internal IRQ Control Register (R/W)
Reset Value: 00000000h
Note: Bits 31:16 of this register are Write Only. Reads to these bits always return a value of 0.
31
30
Mask Internal IRQ15. (Write Only)
0: Disable.
1: Enable.
Mask Internal IRQ14. (Write Only)
0: Disable.
1: Enable.
29
28
Reserved. (Write Only) Must be set to 0.
Mask Internal IRQ12. (Write Only)
0: Disable.
1: Enable.
27
26
25
Mask Internal IRQ11. (Write Only)
0: Disable.
1: Enable.
Mask Internal IRQ10. (Write Only)
0: Disable.
1: Enable.
Mask Internal IRQ9. (Write Only)
0: Disable.
1: Enable.
24
23
Reserved. (Write Only) Must be set to 0.
Mask Internal IRQ7. (Write Only)
0: Disable.
1: Enable.
22
21
Reserved. (Write Only) Must be set to 0.
Mask Internal IRQ5. (Write Only)
0: Disable.
1: Enable.
20
19
Mask Internal IRQ4. (Write Only)
0: Disable.
1: Enable.
Mask Internal IRQ3. (Write Only)
0: Disable.
1: Enable.
18:16
Reserved. (Write Only) Must be set to 0.
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Table 5-38. F3BAR0+Memory Offset: Audio Configuration Registers (Continued)
Bit
Description
15
Assert Masked Internal IRQ15.
0: Disable.
1: Enable.
14
Assert Masked Internal IRQ14.
0: Disable.
1: Enable.
13
12
Reserved. Set to 0.
Assert Masked Internal IRQ12.
0: Disable.
1: Enable.
11
10
9
Assert masked internal IRQ11.
0: Disable.
1: Enable.
Assert Masked Internal IRQ10.
0: Disable.
1: Enable.
Assert Masked Internal IRQ9.
0: Disable.
1: Enable.
8
7
Reserved. Set to 0.
Assert Masked Internal IRQ7.
0: Disable.
1: Enable.
6
5
Reserved. Set to 0.
Assert Masked Internal IRQ5.
0: Disable.
1: Enable.
4
3
Assert Masked Internal IRQ4.
0: Disable.
1: Enable.
Assert Masked Internal IRQ3.
0: Disable.
1: Enable.
2:0
Reserved. Must be set to 0.
Offset 20h
Audio Bus Master 0 Command Register (R/W)
Reset Value: 00h
Audio Bus Master 0: Output to codec; 32-bit; Left and Right Channels; Slots 3 and 4.
7:4
3
Reserved. Must be set to 0. Must return 0 on reads.
Read or Write Control. Sets the transfer direction of the Audio Bus Master.
0: PCI reads are performed.
1: PCI writes are performed.
This bit must be set to 0 (read), and should not be changed when the bus master is active.
Reserved. Must be set to 0. Must return 0 on reads.
Bus Master Control. Controls the state of the Audio Bus Master.
0: Disable.
2:1
0
1: Enable.
Setting this bit to 1 enables the bus master to begin data transfers.
When writing 0 to this bit, the bus master must either be paused, or reach EOT. Writing 0 to this bit while the bus master is
operating may result in unpredictable behavior (and may crash the bus master state machine). The only recovery from such
unpredictable behavior is a PCI reset.
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Table 5-38. F3BAR0+Memory Offset: Audio Configuration Registers (Continued)
Bit
Description
Offset 21h
Audio Bus Master 0 SMI Status Register (RC)
Reset Value: 00h
Audio Bus Master 0: Output to codec; 32-bit; Left and Right Channels; Slots 3 and 4.
7:2
1
Reserved.
Bus Master Error. Indicates if hardware encountered a second EOP before software has cleared the first.
0: No.
1: Yes.
If hardware encounters a second EOP (end of page) before software has cleared the first, it causes the bus master to pause
until this register is read to clear the error.
0
End of Page. Indicates if the bus master transferred data which is marked by EOP bit in the PRD table (bit 30).
0: No.
1: Yes.
Offset 22h-23h
Offset 24h-27h
Not Used
Audio Bus Master 0 PRD Table Address (R/W)
Reset Value: 00000000h
Audio Bus Master 0: Output to codec; 32-bit; Left and Right Channels; Slots 3 and 4.
31:2
Pointer to the Physical Region Descriptor Table. This bit field contains a PRD table pointer for Audio Bus Master 0.
When written, this register points to the first entry in a PRD table. Once Audio Bus Master 0 is enabled (Command Register
bit 0 = 1), it loads the pointer and updates this register (by adding 08h) so that it points to the next PRD.
When read, this register points to the next PRD.
1:0
Reserved. Must be set to 0.
Note: The Physical Region Descriptor (PRD) table consists of one or more entries - each describing a memory region to or from
which data is to be transferred. Each entry consists of two DWORDs.
DWORD 0:
DWORD 1:
[31:0]
31
= Memory Region Physical Base Address
= End of Table Flag
30
= End of Page Flag
29
= Loop Flag (JMP)
[28:16] = Reserved (0)
[15:0]
= Byte Count of the Region (Size)
Offset 28h
Audio Bus Master 1 Command Register (R/W)
Reset Value: 00h
Audio Bus Master 1: Input from codec; 32-Bit; Left and Right Channels; Slots 3 and 4.
7:4
3
Reserved. Must be set to 0. Must return 0 on reads.
Read or Write Control. Set the transfer direction of Audio Bus Master 1.
0: PCI reads are performed.
1: PCI writes are performed.
This bit must be set to 1 (write) and should not be changed when the bus master is active.
Reserved. Must be set to 0. Must return 0 on reads.
Bus Master Control. Controls the state of the Audio Bus Master 1.
0: Disable.
2:1
0
1: Enable.
Setting this bit to 1 enables the bus master to begin data transfers. When writing this bit to 0, the bus master must be either
paused or reached EOT. Writing this bit to 0 while the bus master is operating results in unpredictable behavior (and may
cause a crash of the bus master state machine). The only recovery from this condition is a PCI reset.
Offset 29h
Audio Bus Master 1 SMI Status Register (RC)
Reset Value: 00h
Audio Bus Master 1: Input from codec; 32-Bit; Left and Right Channels; Slots 3 and 4.
7:2
1
Reserved.
Bus Master Error. Indicates if hardware encountered a second EOP before software has cleared the first.
0: No.
1: Yes.
If hardware encounters a second EOP (end of page) before software has cleared the first, it causes the bus master to pause
until this register is read to clear the error.
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Table 5-38. F3BAR0+Memory Offset: Audio Configuration Registers (Continued)
Bit
Description
0
End of Page. Indicates if the bus master transferred data which is marked by EOP bit in the PRD table (bit 30).
0: No.
1: Yes.
Offset 2Ah-2Bh
Offset 2Ch-2Fh
Not Used
Audio Bus Master 1 PRD Table Address (R/W)
Reset Value: 00000000h
Audio Bus Master 1: Input from codec; 32-Bit; Left and Right Channels; Slots 3 and 4.
31:2
Pointer to the Physical Region Descriptor Table. This bit field is a PRD table pointer for Audio Bus Master 1.
When written, this register points to the first entry in a PRD table. Once Audio Bus Master 1 is enabled (Command Register
bit 0 = 1), it loads the pointer and updates this register (by adding 08h) so that it points to the next PRD.
When read, this register points to the next PRD.
1:0
Reserved. Must be set to 0.
Note: The Physical Region Descriptor (PRD) table consists of one or more entries - each describing a memory region to or from
which data is to be transferred. Each entry consists of two DWORDs.
DWORD 0:
DWORD 1:
[31:0]
31
= Memory Region Physical Base Address
= End of Table Flag
30
= End of Page Flag
29
= Loop Flag (JMP)
[28:16] = Reserved (0)
[15:0]
= Byte Count of the Region (Size)
Offset 30h
Audio Bus Master 2 Command Register (R/W)
Reset Value: 00h
Audio Bus Master 2: Output to codec; 16-Bit; Slot 5.
7:4
3
Reserved. Must be set to 0. Must return 0 on reads.
Read or Write Control. Sets the transfer direction of Audio Bus Master 2.
0: PCI reads are performed.
1: PCI writes are performed.
This bit must be set to 0 (read) and should not be changed when the bus master is active.
Reserved. Must be set to 0. Must return 0 on reads.
Bus Master Control. Controls the state of the Audio Bus Master 2.
0: Disable.
2:1
0
1: Enable.
Setting this bit to 1 enables the bus master to begin data transfers. When writing 0 to this bit, the bus master must be either
paused or reached EOT. Writing 0 to this bit while the bus master is operating results in unpredictable behavior (and may
crash the bus master state machine). The only recovery from this condition is a PCI reset.
Offset 31h
Audio Bus Master 2 SMI Status Register (RC)
Reset Value: 00h
Audio Bus Master 2: Output to codec; 16-Bit; Slot 5.
7:2
1
Reserved
Bus Master Error. Indicates if hardware encountered a second EOP before software has cleared the first.
0: No.
1: Yes.
If hardware encounters a second EOP (end of page) before software has cleared the first, it causes the bus master to pause
until this register is read to clear the error.
0
End of Page. Indicates if the Bus master transferred data which is marked by the EOP bit in the PRD table (bit 30).
0: No.
1: Yes.
Offset 32h-33h
Not Used
Reset Value: 00h
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Table 5-38. F3BAR0+Memory Offset: Audio Configuration Registers (Continued)
Bit
Description
Offset 34h-37h
Audio Bus Master 2 PRD Table Address (R/W)
Reset Value: 00000000h
Audio Bus Master 2: Output to codec; 16-Bit; Slot 5.
31:2
Pointer to the Physical Region Descriptor Table. This bit field contains a PRD table pointer for Audio Bus Master 2.
When written, this field points to the first entry in a PRD table. Once Audio Bus Master 2 is enabled (Command Register bit
0 = 1), it loads the pointer and updates this register (by adding 08h) so that it points to the next PRD.
When read, this register points to the next PRD.
1:0
Reserved. Must be set to 0.
Note: The Physical Region Descriptor (PRD) table consists of one or more entries - each describing a memory region to or from
which data is to be transferred. Each entry consists of two DWORDs.
DWORD 0:
DWORD 1:
[31:0]
31
= Memory Region Physical Base Address
= End of Table Flag
30
= End of Page Flag
29
= Loop Flag (JMP)
[28:16] = Reserved (0)
[15:0]
= Byte Count of the Region (Size)
Offset 38h
Audio Bus Master 3 Command Register (R/W)
Reset Value: 00h
Audio Bus Master 3: Input from codec; 16-Bit; Slot 5.
7:4
3
Reserved. Must be set to 0. Must return 0 on reads.
Read or Write Control. Sets the transfer direction of Audio Bus Master 3.
0: PCI reads are performed.
1: PCI writes are performed.
This bit must be set to 1 (write) and should not be changed when the bus master is active.
Reserved. Must be set to 0. Must return 0 on reads.
Bus Master Control. Controls the state of the Audio Bus Master 3.
0: Disable.
2:1
0
1: Enable.
Setting this bit to 1 enables the bus master to begin data transfers. When writing 0 to this bit, the bus master must be either
paused or have reached EOT. Writing 0 to this bit while the bus master is operating results in unpredictable behavior (and
may crash the bus master state machine). The only recovery from this condition is a PCI reset.
Offset 39h
Audio Bus Master 3 SMI Status Register (RC)
Reset Value: 00h
Audio Bus Master 3: Input from codec; 16-Bit; Slot 5.
7:2
1
Reserved.
Bus Master Error. Indicates if hardware encountered a second EOP before software cleared the first.
0: No.
1: Yes.
If hardware encounters a second EOP (end of page) before software cleared the first, it causes the bus master to pause
until this register is read to clear the error.
0
End of Page. Indicates if the bus master transferred data which is marked by the EOP bit in the PRD table (bit 30).
0: No.
1: Yes.
Offset 3Ah-3Bh
Not Used
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Table 5-38. F3BAR0+Memory Offset: Audio Configuration Registers (Continued)
Bit
Description
Offset 3Ch-3Fh
Audio Bus Master 3 PRD Table Address (R/W)
Reset Value: 00000000h
Audio Bus Master 3: Input from codec; 16-Bit; Slot 5.
31:2
Pointer to the Physical Region Descriptor Table. This bit field contains is a PRD table pointer for Audio Bus Master 3.
When written, this field points to the first entry in a PRD table. Once Audio Bus Master 3 is enabled (Command Register bit
0 = 1), it loads the pointer and updates this register (by adding 08h) so that it points to the next PRD.
When read, this register points to the next PRD.
1:0
Reserved. Must be set to 0.
Note: The Physical Region Descriptor (PRD) table consists of one or more entries - each describing a memory region to or from
which data is to be transferred. Each entry consists of two DWORDs.
DWORD 0:
DWORD 1:
[31:0]
31
= Memory Region Physical Base Address
= End of Table Flag
30
= End of Page Flag
29
= Loop Flag (JMP)
[28:16] = Reserved (0)
[15:0]
= Byte Count of the Region (Size)
Offset 40h
Audio Bus Master 4 Command Register (R/W)
Reset Value: 00h
Audio Bus Master 4: Output to codec; 16-Bit; Slot 6 or 11 (F3BAR0+Memory Offset 08h[19] selects slot).
7:4
3
Reserved. Must be set to 0. Must return 0 on reads.
Read or Write Control. Set the transfer direction of Audio Bus Master 4.
0: PCI reads are performed.
1: PCI writes are performed.
This bit must be set to 0 (read) and should not be changed when the bus master is active.
Reserved. Must be set to 0. Must return 0 on reads.
Bus Master Control. Controls the state of the Audio Bus Master 4.
0: Disable.
2:1
0
1: Enable.
Setting this bit to 1 enables the bus master to begin data transfers. When writing 0 to this bit, the bus master must be either
paused or have reached EOT. Writing 0 to this bit while the bus master is operating, results in unpredictable behavior (and
may crash the bus master state machine). The only recovery from this condition is a PCI reset.
Offset 41h
Audio Bus Master 4 SMI Status Register (RC)
Reset Value: 00h
Audio Bus Master 4: Output to codec; 16-Bit; Slot 6 or 11 (F3BAR0+Memory Offset 08h[19] selects slot).
7:2
1
Reserved.
Bus Master Error. Indicates if hardware encountered a second EOP before software cleared the first.
0: No.
1: Yes.
If hardware encounters a second EOP (end of page) before software cleared the first, it causes the bus master to pause
until this register is read to clear the error.
0
End of Page. Bus master transferred data which is marked by the EOP bit in the PRD table (bit 30).
0: No.
1: Yes.
Offset 42h-43h
Not Used
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Table 5-38. F3BAR0+Memory Offset: Audio Configuration Registers (Continued)
Bit
Description
Offset 44h-47h
Audio Bus Master 4 PRD Table Address (R/W)
Reset Value: 00000000h
Audio Bus Master 4: Output to codec; 16-Bit; Slot 6 or 11 (F3BAR0+Memory Offset 08h[19] selects slot).
31:2
Pointer to the Physical Region Descriptor Table. This register is a PRD table pointer for Audio Bus Master 4.
When written, this register points to the first entry in a PRD table. Once Audio Bus Master 4 is enabled (Command Register
bit 0 = 1), it loads the pointer and updates this register (by adding 08h) so that it points to the next PRD.
When read, this register points to the next PRD.
1:0
Reserved. Must be set to 0.
Note: The Physical Region Descriptor (PRD) table consists of one or more entries - each describing a memory region to or from
which data is to be transferred. Each entry consists of two DWORDs.
DWORD 0:
DWORD 1:
[31:0]
31
= Memory Region Physical Base Address
= End of Table Flag
30
= End of Page Flag
29
= Loop Flag (JMP)
[28:16] = Reserved (0)
[15:0]
= Byte Count of the Region (Size)
Offset 48h
Audio Bus Master 5 Command Register (R/W)
Reset Value: 00h
Audio Bus Master 5: Input from codec; 16-Bit; Slot 6 or 11 (F3BAR0+Memory Offset 08h[20] selects slot).
7:4
3
Reserved. Must be set to 0. Must return 0 on reads.
Read or Write Control. Set the transfer direction of Audio Bus Master 5.
0: PCI reads are performed.
1: PCI writes are performed.
This bit must be set to 1 (write) and should not be changed when the bus master is active.
Reserved. Must be set to 0. Must return 0 on reads.
Bus Master Control. Controls the state of the Audio Bus Master 5.
0: Disable.
2:1
0
1: Enable.
Setting this bit to 1 enables the bus master to begin data transfers. When writing 0 to this bit, the bus master must be either
paused or have reached EOT. Writing 0 to this bit while the bus master is operating, results in unpredictable behavior (and
may crash the bus master state machine). The only recovery from this condition is a PCI reset.
Offset 49h
Audio Bus Master 5 SMI Status Register (RC)
Reset Value: 00h
Audio Bus Master 5: Input from codec; 16-Bit; Slot 6 or 11 (F3BAR0+Memory Offset 08h[20] selects slot).
7:2
1
Reserved
Bus Master Error. Indicates if hardware encountered a second EOP before software cleared the first.
0: No.
1: Yes.
If hardware encounters a second EOP (end of page) before software cleared the first, it causes the bus master to pause
until this register is read to clear the error.
0
End of Page. Indicates if the Bus master transferred data which is marked by the EOP bit in the PRD table (bit 30).
0: No.
1: Yes.
Offset 4Ah-4Bh
Not Used
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Core Logic Module (Continued)
Table 5-38. F3BAR0+Memory Offset: Audio Configuration Registers (Continued)
Bit
Description
Offset 4Ch-4Fh
Audio Bus Master 5 PRD Table Address (R/W)
Reset Value: 00000000h
Audio Bus Master 5: Input from codec; 16-Bit; Slot 6 or 11 (F3BAR0+Memory Offset 08h[20] selects slot).
31:2
Pointer to the Physical Region Descriptor Table. This bit field contains a PRD table pointer for Audio Bus Master 5.
When written, this register points to the first entry in a PRD table. Once Audio Bus Master 5 is enabled (Command Register
bit 0 = 1), it loads the pointer and updates this register (by adding 08h) so that it points to the next PRD.
When read, this register points to the next PRD.
1:0
Reserved. Must be set to 0.
Note: The Physical Region Descriptor (PRD) table consists of one or more entries - each describing a memory region to or from
which data is to be transferred. Each entry consists of two DWORDs.
DWORD 0:
DWORD 1:
[31:0]
31
= Memory Region Physical Base Address
= End of Table Flag
30
= End of Page Flag
29
= Loop Flag (JMP)
[28:16] = Reserved (0)
[15:0] = Byte Count of the Region (Size)
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5.4.5 X-Bus Expansion Interface - Function 5
The register space designated as Function 5 (F5) is used
to configure the PCI portion of support hardware for
accessing the X-Bus Expansion support registers. The bit
formats for the PCI Header Registers are given in Table 5-
39.
Located in the PCI Header Registers of F5 are six Base
Address Registers (F5BARx) used for pointing to the regis-
ter spaces designated for X-Bus Expansion support,
described later in this section.
Table 5-39. F5: PCI Header Registers for X-Bus Expansion
Bit
Description
Index 00h-01h
Index 02h-03h
Index 04h-05h
Vendor Identification Register (RO)
Device Identification Register (RO)
PCI Command Register (R/W)
Reset Value: 100Bh
Reset Value: 0505h
Reset Value: 0000h
15:2
1
Reserved. (Read Only)
Memory Space. Allow the Core Logic module to respond to memory cycles from the PCI bus.
0: Disable.
1: Enable.
If F5BAR0, F5BAR1, F5BAR2, F5BAR3, F5BAR4, and F5BAR5 (F5 Index 10h, 14h, 18h, 1Ch, 20h, and 24h) are defined as
allowing access to memory mapped registers, this bit must be set to 1. BAR configuration is programmed through the corre-
sponding mask register (see F5 Index 40h, 44h, 48h, 4Ch, 50h, and 54h)
0
I/O Space. Allow the Core Logic module to respond to I/O cycle from the PCI bus.
0: Disable.
1: Enable.
If F5BAR0, F5BAR1, F5BAR2, F5BAR3, F5BAR4, and F5BAR5 (F5 Index 10h, 14h, 18h, 1Ch, 20h, and 24h) are defined as
allowing access to I/O mapped registers, this bit must be set to 1. BAR configuration is programmed through the corre-
sponding mask register (see F5 Index 40h, 44h, 48h, 4Ch, 50h, and 54h)
Index 06h-07h
Index 08h
PCI Status Register (RO)
Device Revision ID Register (RO)
PCI Class Code Register (RO)
PCI Cache Line Size Register (RO)
PCI Latency Timer Register (RO)
PCI Header Type (RO)
Reset Value: 0280h
Reset Value: 00h
Index 09h-0Bh
Index 0Ch
Reset Value: 068000h
Reset Value: 00h
Index 0Dh
Reset Value: 00h
Index 0Eh
Reset Value: 00h
Index 0Fh
PCI BIST Register (RO)
Reset Value: 00h
Index 10h-13h
Base Address Register 0 - F5BAR0 (R/W)
Reset Value: 00000000h
X-Bus Expansion Address Space. This register allows PCI access to I/O mapped X-Bus Expansion support registers. Bits [5:0] must
be set to 000001, indicating a 64-byte aligned I/O address space. Refer to Table 5-40 on page 290 for the X-Bus Expansion configura-
tion register bit formats and reset values.
Note: The size and type of accessed offsets can be reprogrammed through F5BAR0 Mask Register (F5 Index 40h).
31:6
5:0
X-Bus Expansion Base Address.
Address Range. This bit field must be set to 000001 for this register to operate correctly.
Index 14h-17h
Base Address Register 1 - F5BAR1 (R/W)
Reset Value: 00000000h
Reset Value: 00000000h
Reset Value: 00000000h
Reserved. Reserved for possible future use by the Core Logic module.
Configuration of this register is programmed through the F5BAR1 Mask Register (F5 Index 44h)
Index 18h-1Bh
Base Address Register 2 - F5BAR2 (R/W)
Reserved. Reserved for possible future use by the Core Logic module.
Configuration of this register is programmed through the F5BAR1 Mask Register (F5 Index 48h)
Index 1Ch-1Fh
Base Address Register 3 - F5BAR3 (R/W)
Reserved. Reserved for possible future use by the Core Logic module.
Configuration of this register is programmed through the F5BAR3 Mask Register (F5 Index 4Ch).
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Core Logic Module (Continued)
Table 5-39. F5: PCI Header Registers for X-Bus Expansion (Continued)
Bit
Description
Index 20h-23h
Base Address Register 4 - F5BAR4 (R/W)
Reset Value: 00000000h
Reset Value: 00000000h
Reserved. Reserved for possible future use by the Core Logic module.
Configuration of this register is programmed through the F5BAR4 Mask Register (F5 Index 50h).
Index 24h-27h
Base Address Register 5 - F5BAR5 (R/W)
Reserved. Reserved for possible future use by the Core Logic module.
Configuration of this register is programmed through the F5BAR5 Mask Register (F5 Index 54h).
Index 28h-2Bh
Index 2Ch-2Dh
Index 2Eh-2Fh
Index 30h-3Fh
Index 40h-43h
Reserved
Subsystem Vendor ID (RO)
Subsystem ID (RO)
Reset Value: 00h
Reset Value: 100Bh
Reset Value: 0505h
Reset Value: 00h
Reserved
F5BAR0 Mask Address Register (R/W)
Reset Value: FFFFFFC1h
To use F5BAR0, the mask register should be programmed first. The mask register defines the size of F5BAR0 and whether the
accessed offset registers are memory or I/O mapped.
Note: Whenever a value is written to this mask register, F5BAR0 must also be written (even if the value for F5BAR0 has not
changed).
Memory Base Address Register (Bit 0 = 0)
31:4
Address Mask. Determines the size of the BAR.
— Every bit that is a 1 is programmable in the BAR.
— Every bit that is a 0 is fixed 0 in the BAR.
Since the address mask goes down to bit 4, the smallest memory region is 16 bytes, however, the PCI specification sug-
gests not using less than a 4 KB address range.
3
Prefetchable. Indicates whether or not the data in memory is prefetchable. This bit should be set to 1 only if all the following
are true:
— There are no side-effects from reads (i.e., the data at the location is not changed as a result of the read).
— The device returns all bytes regardless of the byte enables.
— Host bridges can merge processor writes into this range without causing errors.
— The memory is not cached from the host processor.
0: Data is not prefetchable. This value is recommended if one or more of the above listed conditions is not true.
1: Data is prefetchable.
2:1
Type.
00: Located anywhere in the 32-bit address space
01: Located below 1 MB
10: Located anywhere in the 64-bit address space
11: Reserved
0
This bit must be set to 0, to indicate memory base address register.
I/O Base Address Register (Bit 0 = 1)
31:2
Address Mask. Determines the size of the BAR.
— Every bit that is a 1 is programmable in the BAR.
— Every bit that is a 0 is fixed 0 in the BAR.
Since the address mask goes down to bit 2, the smallest I/O region is 4 bytes, however, the PCI Specification suggests not
using less than a 4 KB address range.
1
0
Reserved. Must be set to 0.
This bit must be set to 1, to indicate an I/O base address register.
Index 44h-47h
F5BAR1 Mask Address Register (R/W)
Reset Value: 00000000h
To use F5BAR1, the mask register should be programmed first. The mask register defines the size of F5BAR1 and whether the
accessed offset registers are memory or I/O mapped. See F5 Index 40h (F5BAR0 Mask Address Register) above for bit descriptions.
Note: Whenever a value is written to this mask register, F5BAR1 must also be written (even if the value for F5BAR1 has not
changed).
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Table 5-39. F5: PCI Header Registers for X-Bus Expansion (Continued)
Bit
Description
Index 48h-4Bh
F5BAR2 Mask Address Register (R/W)
Reset Value: 00000000h
To use F5BAR2, the mask register should be programmed first. The mask register defines the size of F5BAR2 and whether the
accessed offset registers are memory or I/O mapped. See F5 Index 40h (F5BAR0 Mask Address Register) above for bit descriptions.
Note: Whenever a value is written to this mask register, F5BAR2 must also be written (even if the value for F5BAR2 has not
changed).
Index 4Ch-4Fh
F5BAR3 Mask Address Register (R/W)
Reset Value: 00000000h
To use F5BAR3, the mask register should be programmed first. The mask register defines the size of F5BAR3 and whether the
accessed offset registers are memory or I/O mapped. See F5 Index 40h (F5BAR0 Mask Address Register) above for bit descriptions.
Note: Whenever a value is written to this mask register, F5BAR3 must also be written (even if the value for F5BAR3 has not
changed).
Index 50h-53h
F5BAR4 Mask Address Register (R/W)
Reset Value: 00000000h
To use F5BAR4, the mask register should be programmed first. The mask register defines the size of F5BAR4 and whether the
accessed offset registers are memory or I/O mapped. See F5 Index 40h (F5BAR0 Mask Address Register) above for bit descriptions.
Note: Whenever a value is written to this mask register, F5BAR4 must also be written (even if the value for F5BAR4 has not
changed).
Index 54h-57h
F5BAR5 Mask Address Register (R/W)
Reset Value: 00000000h
To use F5BAR5, the mask register should be programmed first. The mask register defines the size of F5BAR5 and whether the
accessed offset registers are memory or I/O mapped. See F5 Index 40h (F5BAR0 Mask Address Register) above for bit descriptions.
Note: Whenever a value is written to this mask register, F5BAR5 must also be written (even if the value for F5BAR5 has not
changed).
Index 58h
F5BARx Initialized Register (R/W)
Reset Value: 00h
7:6
5
Reserved. Must be set to 0.
F5BAR5 Initialized. This bit indicates if F5BAR5 (F5 Index 24h) has been initialized.
At reset this bit is cleared (0). Writing F5BAR5 sets this bit to 1. If this bit programmed to 0, the decoding of F5BAR5 is dis-
abled until either this bit is set to 1 or F5BAR5 is written (which causes this bit to be set to 1).
4
3
2
1
0
F5BAR4 Initialized. This bit indicates if F5BAR4 (F5 Index 28h) has been initialized.
At reset this bit is cleared (0). Writing F5BAR4 sets this bit to 1. If this bit programmed to 0, the decoding of F5BAR4 is dis-
abled until either this bit is set to 1 or F5BAR4 is written (which causes this bit to be set to 1).
F5BAR3 Initialized. This bit indicates if F5BAR3 (F5 Index 1Ch) has been initialized.
At reset this bit is cleared (0). Writing F5BAR3 sets this bit to 1. If this bit programmed to 0, the decoding of F5BAR3 is dis-
abled until either this bit is set to 1 or F5BAR3 is written (which causes this bit to be set to 1).
F5BAR2 Initialized. This bit indicates if F5BAR2 (F5 Index 18h) has been initialized.
At reset this bit is cleared (0). Writing F5BAR2 sets this bit to 1. If this bit programmed to 0, the decoding of F5BAR2 is dis-
abled until either this bit is set to 1 or F5BAR2 is written (which causes this bit to be set to 1).
F5BAR1 Initialized. This bit indicates if F5BAR1 (F5 Index 14h) has been initialized.
At reset this bit is cleared (0). Writing F5BAR1 sets this bit to 1. If this bit programmed to 0, the decoding of F5BAR1 is dis-
abled until either this bit is set to 1 or F5BAR1 is written (which causes this bit to be set to 1).
F5BAR0 Initialized. This bit indicates if F5BAR0 (F5 Index 10h) has been initialized.
At reset this bit is cleared (0). Writing F5BAR0 sets this bit to 1. If this bit programmed to 0, the decoding of F5BAR0 is dis-
abled until either this bit is set to 1 or F5BAR0 is written (which causes this bit to be set to 1).
Index 59h-5Fh
Reserved
Reset Value: xxh
Index 60h-63h
Scratchpad: Usually used for Device Number (R/W)
Reset Value: 00000000h
BIOS writes a value, of the Device number. Expected value: 00001200h or 00001201h.
Index 64h-67h Scratchpad: Usually used for Configuration Block Address (R/W)
Reset Value: 00000000h
BIOS writes a value, of the Configuration Block Address.
Index 68h-FFh
Reserved
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5.4.5.1 X-Bus Expansion Support Registers
F5 Index 10h, Base Address Register 0 (F5BAR0) set the
base address that allows PCI access to additional I/O Con-
trol support registers. Table 5-40 shows the support regis-
ters accessed through F5BAR0.
Table 5-40. F5BAR0+I/O Offset: X-Bus Expansion Registers
Bit
Description
Offset 00h-03h
I/O Control Register 1 (R/W)
Reset Value: 010C0007h
31:28
27
Reserved.
IO_ENABLE_SIO_IR (Enable Integrated SIO Infrared).
0: Disable.
1: Enable.
26:25
IO_SIOCFG_IN (Integrated SIO Input Configuration). These two bits can be used to disable the integrated SIO totally or
limit/control the base address.
00: Integrated SIO disable.
01: Integrated SIO configuration access disable.
10: Integrated SIO base address 02Eh/02Fh enable.
11: Integrated SIO base address 015Ch/015Dh enable.
24
IO_ENABLE_SIO_DRIVING_ISA_BUS (Enable Integrated SIO ISA Bus Control). Allow the integrated SIO to drive the
internal ISA bus.
0: Disable.
1: Enable. (Default)
Reserved. Set to 0.
23:21
20
IO_USB_SMI_PWM_EN (USB Internal SMI). Route USB-generated SMI to SMI Status Register in F1BAR0+I/O Offset
00h/02h[14].
0: Disable.
1: Enable.
19
IO_USB_SMI_EN (USB SMI Configuration). Allow USB-generated SMIs.
0: Disable
1: Enable.
If bits 19 and 20 are enabled, the SMI generated by the USB is reported via the Top Level SMI status register at
F1BAR0+I/O Offset 00h/02h[14].
If only bit 19 is enabled, the USB can generate an SMI but there is no status reporting.
18
IO_USB_PCI_EN (USB). Enables USB ports.
0: Disable.
1: Enable.
Reserved.
17:0
Offset 04h-07h
I/O Control Register 2 (R/W)
Reset Value: 00000002h
31:2
1
Reserved. Write as read.
Video Processor Access Enable. Allows access to video processor using F4BAR0.
0: Disable.
1: Enable. (Default)
Note: This bit is readable after the register (F5BAR0+Offset 04h) has been written once.
IO_STRAP_IDSEL_SELECT (IDSEL Strap Override).
0
0: IDSEL: AD28 for Chipset Register Space (F0-F5), AD29 for USB Register Space (PCIUSB).
1: IDSEL: AD26 for Chipset Register Space (F0-F5), AD27 for USB Register Space (PCIUSB).
Offset 08h-0Bh
I/O Control Register 3 (R/W)
Reset Value: 00009000h
31:16
15:13
Reserved. Write as read.
IO_USB_XCVR_VADJ (USB Voltage Adjustment Connection). These bits connect to the voltage adjustment interface on
the three USB transceivers. Default = 100.
12:8
IO_USB_XCVT_CADJ (USB Current Adjustment). These bits connect to the current adjustment interface on the three
USB transceivers. Default = 10000.
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Table 5-40. F5BAR0+I/O Offset: X-Bus Expansion Registers (Continued)
Bit
Description
7
IO_TEST_PORT_EN (Debug Test Port Enable).
0: Disable
1: Enable
6:0
IO_TEST_PORT_REG (Debug Port Pointer). These bits are used to point to the 16-bit slice of the test port bus.
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Core Logic Module (Continued)
5.4.6 USB Controller Registers - PCIUSB
The registers designated as PCIUSB are 32-bit registers
decoded from the PCI address bits [7:2] and C/BE[3:0]#,
when IDSEL is high, AD[10:8] select the appropriate func-
tion, and AD[1:0] are 00.
USB Host Controller's operational register set into a 4K
memory space. Once the BAR register has been initialized,
and the PCI Command register at Index 04h has been set
to enable the Memory space decoder, these “USB Control-
ler” registers are accessible.
The memory-mapped USB Controller registers are listed in
Table 5-42. They follow the Open Host Controller Interface
(OHCI) specification. Registers marked as “Reserved”, and
reserved bits within a register, should not be changed by
software.
The PCI Configuration registers are listed in Table 5-41.
They can be accessed as any number of bytes within a sin-
gle 32-bit aligned unit. They are selected by the PCI-stan-
dard Index and Byte-Enable method.
In the PCI Configuration space, there is one Base Address
Register (BAR), at Index 10h, which is used to map the
Table 5-41. PCIUSB: USB PCI Configuration Registers
Bit
Description
Index 00h-01h
Index 02h-03h
Index 04h-05h
Vendor Identification Register (RO)
Device Identification Register (RO)
Command Register (R/W)
Reset Value: 0E11h
Reset Value: A0F8h
Reset Value: 00h
15:10
9
Reserved. Must be set to 0.
Fast Back-to-Back Enable. (Read Only) USB only acts as a master to a single device, so this functionality is not needed.
It is always disabled (i.e., this bit must always be set to 0).
8
SERR#. When this bit is enabled, USB asserts SERR# when it detects an address parity error.
0: Disable.
1: Enable.
7
6
Wait Cycle Control. USB does not need to insert a wait state between the address and data on the AD lines. It is always
disabled (i.e., this bit is set to 0).
Parity Error. USB asserts PERR# when it is the agent receiving data and it detects a data parity error.
0: Disable.
1: Enable.
5
4
VGA Palette Snoop Enable. (Read Only) USB does not support this function. It is always disabled (i.e., this bit is set to
0).
Memory Write and Invalidate. Allow USB to run Memory Write and Invalidate commands.
0: Disable.
1: Enable.
The Memory Write and Invalidate Command only occurs if the cache-line size is set to 32 bytes and the memory write is
exactly one cache line.
This bit must be set to 0.
3
2
Special Cycles. USB does not run special cycles on PCI. It is always disabled (i.e., this bit is set to 0).
PCI Master Enable. Allow the USB to run PCI master cycles.
0: Disable.
1: Enable.
1
0
Memory Space. Allow the USB to respond as a target to memory cycles from the PCI bus.
0: Disable.
1: Enable.
I/O Space. Allow the USB to respond as a target to I/O cycles from the PCI bus.
0
Disable.
1: Enable.
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Table 5-41. PCIUSB: USB PCI Configuration Registers (Continued)
Description
Bit
Index 06h-07h
Status Register (R/W)
Reset Value: 0280h
The PCI specification defines this register to record status information for PCI related events. This is a read/write register. However,
writes can only reset bits. A bit is reset whenever the register is written and the data in the corresponding bit location is a 1.
15
Detected Parity Error. This bit is set to 1 whenever the USB detects a parity error, even if the Parity Error (Response)
Detection Enable Bit (Command Register, bit 6) is disabled.
Write 1 to clear.
14
SERR# Status. This bit is set whenever the USB detects a PCI address error.
Write 1 to clear.
13
12
Received Master Abort Status. This bit is set when the USB, acting as a PCI master, aborts a PCI bus memory cycle.
Write 1 to clear.
Received Target Abort Status. This bit is set when a USB generated PCI cycle (USB is the PCI master) is aborted by a
PCI target.
Write 1 to clear.
11
Signaled Target Abort Status. This bit is set whenever the USB signals a target abort.
Write 1 to clear.
10:9
8
DEVSEL# Timing. (Read Only) These bits indicate the DEVSEL# timing when performing a positive decode. Since
DEVSEL# is asserted to meet the medium timing, these bits are encoded as 01b.
Data Parity Reported. (Read Only) This bit is set to 1 if the Parity Error Response bit (Command Register bit 6) is set,
and the USB detects PERR# asserted while acting as PCI master (whether or not PERR# was driven by USB).
7
Fast Back-to-Back Capable. The USB supports fast back-to-back transactions when the transactions are not to the same
agent.
This bit is always 1.
6:0
Reserved. Must be set to 0.
Index 08h
Device Revision ID Register (RO)
PCI Class Code Register (RO)
Reset Value: 08h
Index 09h-0Bh
Reset Value: 0C0310h
This register identifies the generic function of the USB the specific register level programming interface. The Base Class is 0Ch (Serial
Bus Controller). The Sub Class is 03h (Universal Serial Bus). The Programming Interface is 10h (OpenHCI).
Index 0Ch
Cache Line Size Register (R/W)
Reset Value: 00h
This register identifies the system cache-line size in units of 32-bit WORDs. The USB only stores the value of bit 3 in this register since
the cache-line size of 32 bytes is the only value applicable to the design. Any value other than 08h written to this register is read back
as 00h.
Index 0Dh
Latency Timer Register (R/W)
Reset Value: 00h
This register identifies the value of the latency timer in PCI clocks for PCI bus master cycles. Bits [2:0] of this register are always set to
0.
Index 0Eh
Header Type Register (RO)
Reset Value: 00h
This register identifies the type of the predefined header in the configuration space. Since the USB is a single function device and not a
PCI-to-PCI bridge, this byte should be read as 00h.
Index 0Fh
BIST Register (RO)
Reset Value: 00h
This register identifies the control and status of Built-In Self-Test (BIST). The USB does not implement BIST, so this register is read
only.
Index 10h-13h
Base Address Register- USB_BAR0 (R/W)
Reset Value: 00000000h
31:12
11:4
3
Base Address. POST writes the value of the memory base address to this register.
Always 0. Indicates that a 4 KB address range is requested.
Always 0. Indicates that there is no support for prefetchable memory.
2:1
0
Always 0. Indicates that the base register is 32-bits wide and can be placed anywhere in 32-bit memory space.
Always 0. Indicates that the operational registers are mapped into memory space.
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Table 5-41. PCIUSB: USB PCI Configuration Registers (Continued)
Description
Bit
Index 14h-2Bh
Index 2Ch-2Dh
Index 2Eh-2Fh
Index 30h-3Bh
Index 3Ch
Reserved
Subsystem Vendor ID (RO)
Subsystem ID (RO)
Reserved
Reset Value: 00h
Reset Value: 0E11h
Reset Value: A0F8h
Reset Value: 00h
Reset Value: 00h
Interrupt Line Register (R/W)
This register identifies the system interrupt controllers to which the device’s interrupt pin is connected. The value of this register is used
by device drivers and has no direct meaning to USB.
Index 3Dh
Interrupt Pin Register (R/W)
Reset Value: 01h
This register selects which interrupt pin the device uses. USB uses INTA# after reset. INTB#, INTC# or INTD# can be selected by writ-
ing 2, 3 or 4, respectively.
Index 3Eh
Min. Grant Register (RO)
Reset Value: 00h
This register specifies how long a burst is needed by the USB, assuming a clock rate of 33 MHz. The value in this register specifies a
period of time in units of 1/4 microsecond.
Index 3Fh
Max. Latency Register (RO)
Reset Value: 50h
This register specifies how often (in units of 1/4 microsecond) the USB needs access to the PCI bus assuming a clock rate of 33 MHz.
Index 40h-43h
ASIC Test Mode Enable Register (R/W)
Reset Value: 000F0000h
Reset Value: 00h
Used for internal debug and test purposes only.
Index 44h
ASIC Operational Mode Enable Register (R/W)
7:1
0
Write Only. Read as 0s.
Data Buffer Region 16
0: The size of the region for the data buffer is 32 bytes.
1: The size of the region for the data buffer is 16 bytes.
Index 45h-FFh
Reserved
Reset Value: 00h
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Table 5-42. USB_BAR+Memory Offset: USB Controller Registers
Bit
Description
Offset 00h-03h
HcRevision Register (RO)
Reset Value = 00000110h
31:8
7:0
Reserved. Read/Write 0s.
Revision (Read Only). Indicates the Open HCI Specification revision number implemented by the Hardware. USB sup-
ports 1.0 specification. (X.Y = XYh).
Offset 04h-07h
HcControl Register (R/W)
Reset Value = 00000000h
31:11
10
Reserved. Read/Write 0s.
RemoteWakeupConnectedEnable. If a remote wakeup signal is supported, this bit enables that operation. Since there is
no remote wakeup signal supported, this bit is ignored.
9
8
RemoteWakeupConnected (Read Only). This bit indicated whether the HC supports a remote wakeup signal. This imple-
mentation does not support any such signal. The bit is hard-coded to 0.
InterruptRouting. This bit is used for interrupt routing:
0: Interrupts routed to normal interrupt mechanism (INT).
1: Interrupts routed to SMI.
7:6
HostControllerFunctionalState. This field sets the HC state. The HC may force a state change from UsbSuspend to
UsbResume after detecting resume signaling from a downstream port. States are:
00: UsbReset
01: UsbResume
10: UsbOperational
11: UsbSuspend
5
4
3
BulkListEnable. When set, this bit enables processing of the Bulk list.
ControlListEnable. When set, this bit enables processing of the Control list.
IsochronousEnable. When clear, this bit disables the Isochronous List when the Periodic List is enabled (so Interrupt EDs
may be serviced). While processing the Periodic List, the HC will check this bit when it finds an isochronous ED.
2
PeriodicListEnable. When set, this bit enables processing of the Periodic (interrupt and isochronous) list. The HC checks
this bit prior to attempting any periodic transfers in a frame.
1:0
ControlBulkServiceRatio. Specifies the number of Control Endpoints serviced for every Bulk Endpoint. Encoding is N-1
where N is the number of Control Endpoints (i.e., 00: 1 Control Endpoint; 11: 3 Control Endpoints).
Offset 08h-0Bh
HcCommandStatus Register (R/W)
Reset Value = 00000000h
31:18
17:16
Reserved. Read/Write 0s.
ScheduleOverrunCount. This field increments every time the SchedulingOverrun bit in HcInterruptStatus is set. The
count wraps from 11 to 00.
15:4
3
Reserved. Read/Write 0s.
OwnershipChangeRequest. When set by software, this bit sets the OwnershipChange field in HcInterruptStatus. The bit
is cleared by software.
2
1
0
BulkListFilled. Set to indicate there is an active ED on the Bulk List. The bit may be set by either software or the HC and
cleared by the HC each time it begins processing the head of the Bulk List.
ControlListFilled. Set to indicate there is an active ED on the Control List. It may be set by either software or the HC and
cleared by the HC each time it begins processing the head of the Control List.
HostControllerReset. This bit is set to initiate a software reset. This bit is cleared by the HC upon completion of the reset
operation.
Offset 0Ch-0Fh
HcInterruptStatus Register (R/W)
Reset Value = 00000000h
31
30
Reserved. Read/Write 0s.
OwnershipChange. This bit is set when the OwnershipChangeRequest bit of HcCommandStatus is set.
Reserved. Read/Write 0s.
29:7
6
RootHubStatusChange. This bit is set when the content of HcRhStatus or the content of any HcRhPortStatus register has
changed.
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Table 5-42. USB_BAR+Memory Offset: USB Controller Registers (Continued)
Bit
Description
5
FrameNumberOverflow. Set when bit 15 of FrameNumber changes value.
UnrecoverableError (Read Only). This event is not implemented and is hard-coded to 0. Writes are ignored.
ResumeDetected. Set when HC detects resume signaling on a downstream port.
StartOfFrame. Set when the Frame Management block signals a Start of Frame event.
WritebackDoneHead. Set after the HC has written HcDoneHead to HccaDoneHead.
SchedulingOverrun. Set when the List Processor determines a Schedule Overrun has occurred.
All bits are set by hardware and cleared by software.
4
3
2
1
0
Note:
Offset 10h-13h
HcInterruptEnable Register (R/W)
Reset Value = 00000000h
31
30
MasterInterruptEnable. This bit is a global interrupt enable. A write of 1 allows interrupts to be enabled via the specific
enable bits listed above.
OwnershipChangeEnable.
0: Ignore.
1: Enable interrupt generation due to Ownership Change.
29:7
6
Reserved. Read/Write 0s.
RootHubStatusChangeEnable.
0: Ignore.
1: Enable interrupt generation due to Root Hub Status Change.
5
FrameNumberOverflowEnable.
0: Ignore.
1: Enable interrupt generation due to Frame Number Overflow.
4
3
UnrecoverableErrorEnable. This event is not implemented. All writes to this bit are ignored.
ResumeDetectedEnable.
0: Ignore.
1: Enable interrupt generation due to Resume Detected.
2
1
StartOfFrameEnable.
0: Ignore.
1: Enable interrupt generation due to Start of Frame.
WritebackDoneHeadEnable.
0: Ignore.
1: Enable interrupt generation due to Writeback Done Head.
0
SchedulingOverrunEnable.
0: Ignore.
1: Enable interrupt generation due to Scheduling Overrun.
Note:
Writing a 1 to a bit in this register sets the corresponding bit, while writing a 0 leaves the bit unchanged.
Offset 14h-17h
HcInterruptDisable Register (R/W)
Reset Value = 00000000h
31
30
MasterInterruptEnable. Global interrupt disable. A write of 1 disables all interrupts.
OwnershipChangeEnable.
0: Ignore.
1: Disable interrupt generation due to Ownership Change.
29:7
6
Reserved. Read/Write 0s.
RootHubStatusChangeEnable.
0: Ignore.
1: Disable interrupt generation due to Root Hub Status Change.
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Table 5-42. USB_BAR+Memory Offset: USB Controller Registers (Continued)
Bit
Description
5
FrameNumberOverflowEnable.
0: Ignore.
1: Disable interrupt generation due to Frame Number Overflow.
4
3
UnrecoverableErrorEnable. This event is not implemented. All writes to this bit will be ignored.
ResumeDetectedEnable.
0: Ignore.
1: Disable interrupt generation due to Resume Detected.
2
1
StartOfFrameEnable.
0: Ignore.
1: Disable interrupt generation due to Start of Frame.
WritebackDoneHeadEnable.
0: Ignore.
1: Disable interrupt generation due to Writeback Done Head.
0
SchedulingOverrunEnable.
0: Ignore.
1: Disable interrupt generation due to Scheduling Overrun.
Note:
Writing a 1 to a bit in this register clears the corresponding bit, while writing a 0 to a bit leaves the bit unchanged.
Offset 18h-1Bh
HcHCCA Register (R/W)
HcPeriodCurrentED Register (R/W)
HcControlHeadED Register (R/W)
HcControlCurrentED Register (R/W)
HcBulkHeadED Register (R/W)
HcBulkCurrentED Register (R/W)
HcDoneHead Register (R/W)
Reset Value = 00000000h
Reset Value = 00000000h
Reset Value = 00000000h
Reset Value = 00000000h
Reset Value = 00000000h
Reset Value = 00000000h
Reset Value = 00000000h
Reset Value = 00002EDFh
31:8
7:0
HCCA. Pointer to HCCA base address.
Reserved. Read/Write 0s.
Offset 1Ch-1Fh
31:4
3:0
PeriodCurrentED. Pointer to the current Periodic List ED.
Reserved. Read/Write 0s.
Offset 20h-23h
31:4
3:0
ControlHeadED. Pointer to the Control List Head ED.
Reserved. Read/Write 0s.
Offset 24h-27h
31:4
3:0
ControlCurrentED. Pointer to the current Control List ED.
Reserved. Read/Write 0s.
Offset 28h-2Bh
31:4
3:0
BulkHeadED. Pointer to the Bulk List Head ED.
Reserved. Read/Write 0s.
Offset 2Ch-2Fh
31:4
3:0
BulkCurrentED. Pointer to the current Bulk List ED.
Reserved. Read/Write 0s.
Offset 30h-33h
31:4
3:0
DoneHead. Pointer to the current Done List Head ED.
Reserved. Read/Write 0s.
Offset 34h-37h
HcFmInterval Register (R/W)
31
FrameIntervalToggle (Read Only). This bit is toggled by HCD when it loads a new value into FrameInterval.
30:16
FSLargestDataPacket (Read Only). This field specifies a value which is loaded into the Largest Data Packet Counter at
the beginning of each frame.
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Table 5-42. USB_BAR+Memory Offset: USB Controller Registers (Continued)
Bit
Description
15:14
13:0
Reserved. Read/Write 0s.
FrameInterval. This field specifies the length of a frame as (bit times - 1). For 12,000 bit times in a frame, a value of 11,999
is stored here.
Offset 38h-3Bh
HcFrameRemaining Register (RO)
Reset Value = 00000000h
31
FrameRemainingToggle (Read Only). Loaded with FrameIntervalToggle when FrameRemaining is loaded.
Reserved. Read 0s.
30:14
13:0
FrameRemaining (Read Only). When the HC is in the UsbOperational state, this 14-bit field decrements each 12 MHz
clock period. When the count reaches 0, (end of frame) the counter reloads with FrameInterval. In addition, the counter
loads when the HC transitions into UsbOperational.
Offset 3Ch-3Fh
HcFmNumber Register (RO)
Reset Value = 00000000h
31:16
15:0
Reserved. Read 0s.
FrameNumber (Read Only). This 16-bit incrementing counter field is incremented coincident with the loading of FrameR-
emaining. The count rolls over from FFFFh to 0h.
Offset 40h-43h
HcPeriodicStart Register (R/W)
Reset Value = 00000000h
31:14
13:0
Reserved. Read/Write 0s.
PeriodicStart. This field contains a value used by the List Processor to determine where in a frame the Periodic List pro-
cessing must begin.
Offset 44h-47h
HcLSThreshold Register (R/W)
Reset Value = 00000628h
31:12
11:0
Reserved. Read/Write 0s.
LSThreshold. This field contains a value used by the Frame Management block to determine whether or not a low speed
transaction can be started in the current frame.
Offset 48h-4Bh
HcRhDescriptorA Register (R/W)
Reset Value = 01000003h
31:24
PowerOnToPowerGoodTime. This field value is represented as the number of 2 ms intervals, ensuring that the power
switching is effective within 2 ms. Only bits [25:24] are implemented as R/W. The remaining bits are read only as 0. It is not
expected that these bits be written to anything other than 1h, but limited adjustment is provided. This field should be written
to support system implementation. This field should always be written to a non-zero value.
23:13
12
Reserved. Read/Write 0s.
NoOverCurrentProtection. This bit should be written to support the external system port over-current implementation.
0: Over-current status is reported.
1: Over-current status is not reported.
11
OverCurrentProtectionMode. This bit should be written 0 and is only valid when NoOverCurrentProtection is cleared.
0: Global Over-Current.
1: Individual Over-Current
10
9
DeviceType (Read Only). USB is not a compound device.
NoPowerSwitching. This bit should be written to support the external system port power switching implementation.
0: Ports are power switched.
1: Ports are always powered on.
8
PowerSwitchingMode. This bit is only valid when NoPowerSwitching is cleared. This bit should be written 0.
0: Global Switching.
1: Individual Switching
7:0
NumberDownstreamPorts (Read Only). USB supports three downstream ports.
Note:
This register is only reset by a power-on reset (PCIRST#). It is written during system initialization to configure the Root Hub.
These bit should not be written during normal operation.
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Table 5-42. USB_BAR+Memory Offset: USB Controller Registers (Continued)
Bit
Description
Offset 4Ch-4Fh
HcRhDescriptorB Register (R/W)
Reset Value = 00000000h
31:16
PortPowerControlMask. Global-power switching. This field is only valid if NoPowerSwitching is cleared and Power-
SwitchingMode is set (individual port switching). When set, the port only responds to individual port power switching com-
mands (Set/ClearPortPower). When cleared, the port only responds to global power switching commands
(Set/ClearGlobalPower).
0: Device not removable.
1: Global-power mask.
Port Bit relationship - Unimplemented ports are reserved, read/write 0.
0 = Reserved
1 = Port 1
2 = Port 2
...
15 = Port 15
15:0
DeviceRemoveable. USB ports default to removable devices.
0: Device not removable.
1: Device removable.
Port Bit relationship
0 = Reserved
1 = Port 1
2 = Port 2
...
15 = Port 15
Unimplemented ports are reserved, read/write 0.
Note:
This register is only reset by a power-on reset (PCIRST#). It is written during system initialization to configure the Root Hub.
These bit should not be written during normal operation.
Offset 50h-53h
HcRhStatus Register (R/W)
Reset Value = 00000000h
31
ClearRemoteWakeupEnable (Write Only). Writing a 1 to this bit clears DeviceRemoteWakeupEnable. Writing a 0 has no
effect.
30:18
17
Reserved. Read/Write 0s.
OverCurrentIndicatorChange. This bit is set when OverCurrentIndicator changes. Writing a 1 clears this bit. Writing a 0
has no effect.
16
15
Read: LocalPowerStatusChange. Not supported. Always read 0.
Write: SetGlobalPower. Write a 1 issues a SetGlobalPower command to the ports. Writing a 0 has no effect.
Read: DeviceRemoteWakeupEnable. This bit enables ports' ConnectStatusChange as a remote wakeup event.
0: Disabled.
1: Enabled.
Write: SetRemoteWakeupEnable. Writing a 1 sets DeviceRemoteWakeupEnable. Writing a 0 has no effect.
14:2
1
Reserved. Read/Write 0s.
OverCurrentIndicator. This bit reflects the state of the OVRCUR pin. This field is only valid if NoOverCurrentProtection
and OverCurrentProtectionMode are cleared.
0: No over-current condition.
1:Over-current condition.
0
Read: LocalPowerStatus. Not Supported. Always read 0.
Write: ClearGlobalPower. Writing a 1 issues a ClearGlobalPower command to the ports. Writing a 0 has no effect.
Note:
This register is reset by the UsbReset state.
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Table 5-42. USB_BAR+Memory Offset: USB Controller Registers (Continued)
Bit
Description
Offset 54h-57h
HcRhPortStatus[1] Register (R/W)
Reset Value = 00000000h
31:21
20
Reserved. Read/Write 0s.
PortResetStatusChange. This bit indicates that the port reset signal has completed.
0: Port reset is not complete.
1: Port reset is complete.
19
18
PortOverCurrentIndicatorChange. This bit is set when OverCurrentIndicator changes. Writing a 1 clears this bit. Writing
a 0 has no effect.
PortSuspendStatusChange. This bit indicates the completion of the selective resume sequence for the port.
0: Port is not resumed.
1: Port resume is complete.
17
16
PortEnableStatusChange. This bit indicates that the port has been disabled due to a hardware event (cleared PortEna-
bleStatus).
0: Port has not been disabled.
1: PortEnableStatus has been cleared.
ConnectStatusChange. This bit indicates a connect or disconnect event has been detected. Writing a 1 clears this bit.
Writing a 0 has no effect.
0: No connect/disconnect event.
1: Hardware detection of connect/disconnect event.
If DeviceRemoveable is set, this bit resets to 1.
15:10
9
Reserved. Read/Write 0s.
Read: LowSpeedDeviceAttached. This bit defines the speed (and bud idle) of the attached device. It is only valid when
CurrentConnectStatus is set.
0: Full Speed device.
1: Low Speed device.
Write: ClearPortPower. Writing a 1 clears PortPowerStatus. Writing a 0 has no effect.
8
Read: PortPowerStatus. This bit reflects the power state of the port regardless of the power switching mode.
0: Port power is off.
1: Port power is on.
If NoPowerSwitching is set, this bit is always read as 1.
Write: SetPortPower. Writing a 1 sets PortPowerStatus. Writing a 0 has no effect.
7:5
4
Reserved. Read/Write 0s.
Read: PortResetStatus.
0: Port reset signal is not active.
1: Port reset signal is active.
Write: SetPortReset. Writing a 1 sets PortResetStatus. Writing a 0 has no effect.
3
Read: PortOverCurrentIndicator. This bit reflects the state of the OVRCUR pin dedicated to this port. This field is only
valid if NoOverCurrentProtection is cleared and OverCurrentProtectionMode is set.
0: No over-current condition.
1: Over-current condition.
Write: ClearPortSuspend. Writing a 1 initiates the selective resume sequence for the port. Writing a 0 has no effect.
2
1
Read: PortSuspendStatus.
0: Port is not suspended.
1: Port is selectively suspended.
Write: SetPortSuspend. Writing a 1 sets PortSuspendStatus. Writing a 0 has no effect.
Read: PortEnableStatus.
0: Port disabled.
1: Port enabled.
Write: SetPortEnable. Writing a 1 sets PortEnableStatus. Writing a 0 has no effect.
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Table 5-42. USB_BAR+Memory Offset: USB Controller Registers (Continued)
Bit
Description
0
Read: CurrentConnectStatus.
0: No device connected.
1: Device connected.
If DeviceRemoveable is set (not removable) this bit is always 1.
Write: ClearPortEnable. Writing 1 a clears PortEnableStatus. Writing a 0 has no effect.
Note:
This register is reset by the UsbReset state.
Offset 58h-5Bh
HcRhPortStatus[2] Register (R/W)
Reset Value = 00000000h
31:21
20
Reserved. Read/Write 0s.
PortResetStatusChange. This bit indicates that the port reset signal has completed.
0: Port reset is not complete.
1: Port reset is complete.
19
18
PortOverCurrentIndicatorChange. This bit is set when OverCurrentIndicator changes. Writing a 1 clears this bit. Writing
a 0 has no effect.
PortSuspendStatusChange. This bit indicates the completion of the selective resume sequence for the port.
0: Port is not resumed.
1: Port resume is complete.
17
16
PortEnableStatusChange. This bit indicates that the port has been disabled due to a hardware event (cleared PortEna-
bleStatus).
0: Port has not been disabled.
1: PortEnableStatus has been cleared.
ConnectStatusChange. This bit indicates a connect or disconnect event has been detected. Writing a 1 clears this bit.
Writing a 0 has no effect.
0: No connect/disconnect event.
1: Hardware detection of connect/disconnect event.
If DeviceRemoveable is set, this bit resets to 1.
15:10
9
Reserved. Read/Write 0s.
Read: LowSpeedDeviceAttached. This bit defines the speed (and bud idle) of the attached device. It is only valid when
CurrentConnectStatus is set.
0: Full speed device.
1: Low speed device.
Write: ClearPortPower. Writing a 1 clears PortPowerStatus. Writing a 0 has no effect.
8
Read: PortPowerStatus. This bit reflects the power state of the port regardless of the power switching mode.
0: Port power is off.
1: Port power is on.
If NoPowerSwitching is set, this bit is always read as 1.
Write: SetPortPower. Writing a 1 sets PortPowerStatus. Writing a 0 has no effect.
7:5
4
Reserved. Read/Write 0s.
Read: PortResetStatus.
0: Port reset signal is not active.
1: Port reset signal is active.
Write: SetPortReset. Writing a 1 sets PortResetStatus. Writing a 0 has no effect.
3
Read: PortOverCurrentIndicator. This bit reflects the state of the OVRCUR pin dedicated to this port. This field is only
valid if NoOverCurrentProtection is cleared and OverCurrentProtectionMode is set.
0: No over-current condition.
1: Over-current condition.
Write: ClearPortSuspend. Writing a 1 initiates the selective resume sequence for the port. Writing a 0 has no effect.
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Table 5-42. USB_BAR+Memory Offset: USB Controller Registers (Continued)
Bit
Description
2
Read: PortSuspendStatus.
0: Port is not suspended.
1: Port is selectively suspended.
Write: SetPortSuspend. Writing a 1 sets PortSuspendStatus. Writing a 0 has no effect.
1
0
Read: PortEnableStatus.
0: Port disabled.
1: Port enabled.
Write: SetPortEnable. Writing a 1 sets PortEnableStatus. Writing a 0 has no effect.
Read: CurrentConnectStatus.
0: No device connected.
1: Device connected.
If DeviceRemoveable is set (not removable) this bit is always 1.
Write: ClearPortEnable. Writing 1 a clears PortEnableStatus. Writing a 0 has no effect.
Note:
This register is reset by the UsbReset state.
Offset 5Ch-5Fh
HcRhPortStatus[3] Register (R/W)
Reset Value = 00000000h
31:21
20
Reserved. Read/Write 0s.
PortResetStatusChange. This bit indicates that the port reset signal has completed.
0: Port reset is not complete.
1: Port reset is complete.
19
18
PortOverCurrentIndicatorChange. This bit is set when OverCurrentIndicator changes. Writing a 1 clears this bit. Writing
a 0 has no effect.
PortSuspendStatusChange. This bit indicates the completion of the selective resume sequence for the port.
0: Port is not resumed.
1: Port resume is complete.
17
16
PortEnableStatusChange. This bit indicates that the port has been disabled due to a hardware event (cleared PortEna-
bleStatus).
0: Port has not been disabled.
1: PortEnableStatus has been cleared.
ConnectStatusChange. This bit indicates a connect or disconnect event has been detected. Writing a 1 clears this bit.
Writing a 0 has no effect.
0: No connect/disconnect event.
1: Hardware detection of connect/disconnect event.
If DeviceRemoveable is set, this bit resets to 1.
15:10
9
Reserved. Read/Write 0s.
Read: LowSpeedDeviceAttached. This bit defines the speed (and bud idle) of the attached device. It is only valid when
CurrentConnectStatus is set.
0: Full speed device.
1: Low speed device.
Write: ClearPortPower. Writing a 1 clears PortPowerStatus. Writing a 0 has no effect.
8
Read: PortPowerStatus. This bit reflects the power state of the port regardless of the power switching mode.
0: Port power is off.
1: Port power is on.
If NoPowerSwitching is set, this bit is always read as 1.
Write: SetPortPower. Writing a 1 sets PortPowerStatus. Writing a 0 has no effect.
7:5
Reserved. Read/Write 0s.
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Table 5-42. USB_BAR+Memory Offset: USB Controller Registers (Continued)
Bit
Description
4
Read: PortResetStatus.
0: Port reset signal is not active.
1: Port reset signal is active.
Write: SetPortReset. Writing a 1 sets PortResetStatus. Writing a 0 has no effect.
3
Read: PortOverCurrentIndicator. This bit reflects the state of the OVRCUR pin dedicated to this port. This field is only
valid if NoOverCurrentProtection is cleared and OverCurrentProtectionMode is set.
0: No over-current condition.
1: Over-current condition.
Write: ClearPortSuspend. Writing a 1 initiates the selective resume sequence for the port. Writing a 0 has no effect.
2
1
0
Read: PortSuspendStatus.
0: Port is not suspended.
1: Port is selectively suspended.
Write: SetPortSuspend. Writing a 1 sets PortSuspendStatus. Writing a 0 has no effect.
Read: PortEnableStatus.
0: Port disabled.
1: Port enabled.
Write: SetPortEnable. Writing a 1 sets PortEnableStatus. Writing a 0 has no effect.
Read: CurrentConnectStatus.
0: No device connected.
1: Device connected.
If DeviceRemoveable is set (not removable) this bit is always 1.
Write: ClearPortEnable. Writing 1 a clears PortEnableStatus. Writing a 0 has no effect.
Note:
This register is reset by the UsbReset state.
Offset 60h-9Fh
Reserved
Reset Value = xxh
Offset 100h-103h
HceControl Register (R/W)
Reset Value = 00000000h
31:9
8
Reserved. Read/Write 0s.
A20State. Indicates current state of Gate A20 on keyboard controller. Compared against value written to 60h when
GateA20Sequence is active.
7
6
5
4
3
2
IRQ12Active. Indicates a positive transition on IRQ12 from keyboard controller occurred. Software writes this bit to 1 to
clear it (set it to 0); a 0 write has no effect.
IRQ1Active. Indicates a positive transition on IRQ1 from keyboard controller occurred. Software writes this bit to 1 to clear
it (set it to 0); a 0 write has no effect.
GateA20Sequence. Set by HC when a data value of D1h is written to I/O port 64h. Cleared by HC on write to I/O port 64h
of any value other than D1h.
ExternalIRQEn. When set to 1, IRQ1 and IRQ12 from the keyboard controller cause an emulation interrupt. The function
controlled by this bit is independent of the setting of the EmulationEnable bit in this register.
IRQEn. When set, the HC generates IRQ1 or IRQ12 as long as the OutputFull bit in HceStatus is set to 1. If the AuxOut-
putFull bit of HceStatus is 0, IRQ1 is generated: if 1, then an IRQ12 is generated.
CharacterPending. When set, an emulation interrupt will be generated when the OutputFull bit of the HceStatus register is
set to 0.
1
0
EmulationInterrupt (Read Only). This bit is a static decode of the emulation interrupt condition.
EmulationEnable. When set to 1 the HC is enabled for legacy emulation and will decode accesses to I/O registers 60h
and 64h and generate IRQ1 and/or IRQ12 when appropriate. The HC also generates an emulation interrupt at appropriate
times to invoke the emulation software.
Note:
This register is used to enable and control the emulation hardware and report various status information.
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Table 5-42. USB_BAR+Memory Offset: USB Controller Registers (Continued)
Bit
Description
Offset 104h-107h
HceInput Register (R/W)
Reset Value = 000000xxh
31:8
7:0
Reserved. Read/Write 0s.
InputData. This register holds data written to I/O ports 60h and 64h.
Note:
This register is the emulation side of the legacy Input Buffer register.
Offset 108h-10Bh
HceOutput Register (R/W)
Reset Value = 000000xxh
31:8
7:0
Reserved. Read/Write 0s.
OutputData. This register hosts data that is returned when an I/O read of port 60h is performed by application software.
Note:
This register is the emulation side of the legacy Output Buffer register where keyboard and mouse data is to be written by soft-
ware.
Offset 10Ch-10Fh
HceStatus Register (R/W)
Reset Value = 00000000h
31:8
7
Reserved. Read/Write 0s.
Parity. Indicates parity error on keyboard/mouse data.
Timeout. Used to indicate a time-out
6
5
AuxOutputFull. IRQ12 is asserted whenever this bit is set to 1 and OutputFull is set to 1 and the IRQEn bit is set.
Inhibit Switch. This bit reflects the state of the keyboard inhibit switch and is set if the keyboard is NOT inhibited.
CmdData. The HC will set this bit to 0 on an I/O write to port 60h and on an I/O write to port 64h the HC will set this bit to 1.
Flag. Nominally used as a system flag by software to indicate a warm or cold boot.
4
3
2
1
InputFull. Except for the case of a Gate A20 sequence, this bit is set to 1 on an I/O write to address 60h or 64h. While this
bit is set to 1 and emulation is enabled, an emulation interrupt condition exists.
0
OutputFull. The HC will set this bit to 0 on a read of I/O port 60h. If IRQEn is set and AuxOutputFull is set to 0 then an
IRQ1 is generated as long as this bit is set to 1. If IRQEn is set and AuxOutputFull is set to 1 then and IRQ12 will be gen-
erated a long as this bit is set to 1. While this bit is 0 and CharacterPending in HceControl is set to 1, an emulation inter-
rupt condition exists.
Note:
This register is the emulation side of the legacy Status register.
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Core Logic Module (Continued)
5.4.7 ISA Legacy Register Space
• DMA Channel Control Registers, see Table 5-43
• DMA Page Registers, see Table 5-44
The ISA Legacy registers reside in the ISA I/O address
space in the address range from 000h to FFFh and are
accessed through typical input/output instructions (i.e.,
CPU direct R/W) with the designated I/O port address and
8-bit data.
• Programmable Interval Timer Registers, see Table 5-45
• Programmable Interrupt Controller Registers, see Table
5-46
The bit formats for the ISA Legacy I/O Registers plus two
chipset-specific configuration registers used for interrupt
mapping in the Core Logic module are given in this section.
The ISA Legacy registers are separated into the following
categories:
• Keyboard Controller Registers, see Table 5-47
• Real-Time Clock Registers, see Table 5-48
• Miscellaneous Registers, see Table 5-49 (includes 4D0h
and 4D1h Interrupt Edge/Level Select Registers)
Table 5-43. DMA Channel Control Registers
Bit
Description
I/O Port 000h
DMA Channel 0 Address Register (R/W)
DMA Channel 0 Transfer Count Register (R/W)
DMA Channel 1 Address Register (R/W)
DMA Channel 1 Transfer Count Register (R/W)
DMA Channel 2 Address Register (R/W)
Written as two successive bytes, byte 0, 1.
I/O Port 001h
Written as two successive bytes, byte 0, 1.
I/O Port 002h
Written as two successive bytes, byte 0, 1.
I/O Port 003h
Written as two successive bytes, byte 0, 1.
I/O Port 004h
Written as two successive bytes, byte 0, 1.
I/O Port 005h
DMA Channel 2 Transfer Count Register (R/W)
DMA Channel 3 Address Register (R/W)
DMA Channel 3 Transfer Count Register (R/W)
Written as two successive bytes, byte 0, 1.
I/O Port 006h
Written as two successive bytes, byte 0, 1.
I/O Port 007h
Written as two successive bytes, byte 0, 1.
I/O Port 008h (R/W)
Read
DMA Status Register, Channels 3:0
7
6
5
4
3
Channel 3 Request. Indicates if a request is pending.
0: No.
1: Yes.
Channel 2 Request. Indicates if a request is pending.
0: No.
1: Yes.
Channel 1 Request. Indicates if a request is pending.
0: No.
1: Yes.
Channel 0 Request. Indicates if a request is pending.
0: No.
1: Yes.
Channel 3 Terminal Count. Indicates if TC was reached.
0: No.
1: Yes.
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Table 5-43. DMA Channel Control Registers (Continued)
Bit
Description
2
Channel 2 Terminal Count. Indicates if TC was reached.
0: No.
1: Yes.
1
0
Channel 1 Terminal Count. Indicates if TC was reached.
0: No.
1: Yes.
Channel 0 Terminal Count. Indicates if TC was reached.
0: No.
1: Yes.
Write
DMA Command Register, Channels 3:0
7
DACK Sense.
0: Active high.
1: Active low.
DREQ Sense.
0: Active high.
1: Active low.
Write Selection.
0: Late write.
1: Extended write.
Priority Mode.
0: Fixed.
6
5
4
1: Rotating.
3
Timing Mode.
0: Normal.
1: Compressed.
Channels 3:0.
0: Disable.
2
1: Enable.
1:0
Reserved. Must be set to 0.
I/O Port 009h
Software DMA Request Register, Channels 3:0 (W)
7:3
2
Reserved. Must be set to 0.
Request Type.
0: Reset.
1: Set.
1:0
Channel Number Request Select
00: Channel 0.
01: Channel 1.
10: Channel 2.
11: Channel 3.
I/O Port 00Ah
DMA Channel Mask Register, Channels 3:0 (WO)
7:3
2
Reserved. Must be set to 0.
Channel Mask.
0: Not masked.
1: Masked.
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Table 5-43. DMA Channel Control Registers (Continued)
Bit
Description
1:0
Channel Number Mask Select.
00: Channel 0.
01: Channel 1.
10: Channel 2.
11: Channel 3.
I/O Port 00Bh
DMA Channel Mode Register, Channels 3:0 (WO)
7:6
Transfer Mode.
00: Demand.
01: Single.
10: Block.
11: Cascade.
Address Direction.
0: Increment.
1: Decrement.
Auto-initialize.
0: Disable.
5
4
1: Enable.
3:2
Transfer Type.
00: Verify.
01: Memory read.
10: Memory write.
11: Reserved.
1:0
Channel Number Mode Select.
00: Channel 0.
01: Channel 1.
10: Channel 2.
11: Channel 3.
I/O Port 00Ch
I/O Port 00Dh
I/O Port 00Eh
I/O Port 00Fh
DMA Clear Byte Pointer Command, Channels 3:0 (W)
DMA Master Clear Command, Channels 3:0 (W)
DMA Clear Mask Register Command, Channels 3:0 (W)
DMA Write Mask Register Command, Channels 3:0 (W)
DMA Channel 4 Address Register (R/W)
I/O Port 0C0h
Not used.
I/O Port 0C2h
DMA Channel 4 Transfer Count Register (R/W)
DMA Channel 5 Address Register (R/W)
DMA Channel 5 Transfer Count Register (R/W)
DMA Channel 6 Address Register (R/W)
DMA Channel 6 Transfer Count Register (R/W)
DMA Channel 7 Address Register (R/W)
Not used.
I/O Port 0C4h
Memory address bytes 1 and 0.
I/O Port 0C6h
Transfer count bytes 1 and 0.
I/O Port 0C8h
Memory address bytes 1 and 0.
I/O Port 0CAh
Transfer count bytes 1 and 0.
I/O Port 0CCh
Memory address bytes 1 and 0.
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Core Logic Module (Continued)
Table 5-43. DMA Channel Control Registers (Continued)
Bit
Description
I/O Port 0CEh
DMA Channel 7 Transfer Count Register (R/W)
Transfer count bytes 1 and 0.
I/O Port 0D0h (R/W)
Read
DMA Status Register, Channels 7:4
7
6
5
Channel 7 Request. Indicates if a request is pending.
0: No.
1: Yes.
Channel 6 Request. Indicates if a request is pending.
0: No.
1: Yes.
Channel 5 Request. Indicates if a request is pending.
0: No.
1: Yes.
4
3
Undefined
Channel 7 Terminal Count. Indicates if TC was reached.
0: No.
1: Yes.
2
1
Channel 6 Terminal Count. Indicates if TC was reached.
0: No.
1: Yes.
Channel 5 Terminal Count. Indicates if TC was reached.
0: No.
1: Yes.
0
Write
7
Undefined.
DMA Command Register, Channels 7:4
DACK Sense.
0: Active high.
1: Active low.
DREQ Sense.
0: Active high.
1: Active low.
Write Selection.
0: Late write.
1: Extended write.
Priority Mode.
0: Fixed.
6
5
4
3
2
1: Rotating.
Timing Mode.
0: Normal.
1: Compressed.
Channels 7:4.
0: Disable.
1: Enable.
1:0
Reserved. Must be set to 0.
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Table 5-43. DMA Channel Control Registers (Continued)
Bit
Description
I/O Port 0D2h
Software DMA Request Register, Channels 7:4 (W)
7:3
2
Reserved. Must be set to 0.
Request Type.
0: Reset.
1: Set.
1:0
Channel Number Request Select.
00: Illegal.
01: Channel 5.
10: Channel 6.
11: Channel 7.
I/O Port 0D4h
DMA Channel Mask Register, Channels 7:4 (WO)
7:3
2
Reserved. Must be set to 0.
Channel Mask.
0: Not masked.
1: Masked.
1:0
Channel Number Mask Select.
00: Channel 4.
01: Channel 5.
10: Channel 6.
11: Channel 7.
I/O Port 0D6h
DMA Channel Mode Register, Channels 7:4 (WO)
7:6
Transfer Mode.
00: Demand.
01: Single.
10: Block.
11: Cascade.
Address Direction.
0: Increment.
1: Decrement.
Auto-initialize.
0: Disabled
5
4
1: Enable
3:2
Transfer Type.
00: Verify.
01: Memory read.
10: Memory write.
11: Reserved.
1:0
Channel Number Mode Select.
00: Channel 4.
01: Channel 5.
10: Channel 6.
11: Channel 7.
Channel 4 must be programmed in cascade mode. This mode is not the default.
I/O Port 0D8h
I/O Port 0DAh
I/O Port 0DCh
I/O Port 0DEh
DMA Clear Byte Pointer Command, Channels 7:4 (W)
DMA Master Clear Command, Channels 7:4 (W)
DMA Clear Mask Register Command, Channels 7:4 (W)
DMA Write Mask Register Command, Channels 7:4 (W)
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Table 5-44. DMA Page Registers
Bit
Description
I/O Port 081h
DMA Channel 2 Low Page Register (R/W)
DMA Channel 3 Low Page Register (R/W)
DMA Channel 1 Low Page Register (R/W)
DMA Channel 0 Low Page Register (R/W)
DMA Channel 6 Low Page Register (R/W)
DMA Channel 7 Low Page Register (R/W)
DMA Channel 5 Low Page Register (R/W)
ISA Refresh Low Page Register (R/W)
DMA Channel 2 High Page Register (R/W)
Address bits [23:16] (byte 2).
I/O Port 082h
Address bits [23:16] (byte 2).
I/O Port 083h
Address bits [23:16] (byte 2).
I/O Port 087h
Address bits [23:16] (byte 2).
I/O Port 089h
Address bits [23:16] (byte 2).
I/O Port 08Ah
Address bits [23:16] (byte 2).
I/O Port 08Bh
Address bits [23:16] (byte 2).
I/O Port 08Fh
Refresh address.
I/O Port 481h
Address bits [31:24] (byte 3).
Note: This register is reset to 00h on any access to Port 081h.
I/O Port 482h
DMA Channel 3 High Page Register (R/W)
Address bits [31:24] (byte 3).
Note: This register is reset to 00h on any access to Port 082h.
I/O Port 483h
DMA Channel 1 High Page Register (R/W)
Address bits [31:24] (byte 3).
Note: This register is reset to 00h on any access to Port 083h.
I/O Port 487h
DMA Channel 0 High Page Register (R/W)
Address bits [31:24] (byte 3).
Note: This register is reset to 00h on any access to Port 087h.
I/O Port 489h
DMA Channel 6 High Page Register (R/W)
Address bits [31:24] (byte 3).
Note: This register is reset to 00h on any access to Port 089h.
I/O Port 48Ah
DMA Channel 7 High Page Register (R/W)
Address bits [31:24] (byte 3).
Note: This register is reset to 00h on any access to Port 08Ah.
I/O Port 48Bh
DMA Channel 5 High Page Register (R/W)
Address bits [31:24] (byte 3).
Note: This register is reset to 00h on any access to Port 08Bh.
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Table 5-45. Programmable Interval Timer Registers
Bit
Description
I/O Port 040h
Write
PIT Timer 0 Counter
PIT Timer 0 Status
7:0
Read
Counter Value.
7
6
Counter Output. State of counter output signal.
Counter Loaded. Indicates if the last count written is loaded.
0: Yes.
1: No.
5:4
Current Read/Write Mode.
00: Counter latch command.
01: R/W LSB only.
10: R/W MSB only.
11: R/W LSB, followed by MSB.
Current Counter Mode. 0-5.
BCD Mode.
3:1
0
0: Binary.
1: BCD (Binary Coded Decimal).
I/O Port 041h
Write
PIT Timer 1 Counter (Refresh)
PIT Timer 1 Status (Refresh)
7:0
Read
Counter Value.
7
6
Counter Output. State of counter output signal.
Counter Loaded. Indicates if the last count written is loaded.
0: Yes.
1: No.
5:4
Current Read/Write Mode.
00: Counter latch command.
01: R/W LSB only.
10: R/W MSB only.
11: R/W LSB, followed by MSB.
Current Counter Mode. 0-5.
BCD Mode.
3:1
0
0: Binary.
1: BCD (Binary Coded Decimal).
I/O Port 042h
Write
PIT Timer 2 Counter (Speaker)
PIT Timer 2 Status (Speaker)
7:0
Read
Counter Value.
7
6
Counter Output. State of counter output signal.
Counter Loaded. Indicates if the last count written is loaded.
0: Yes.
1: No.
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Core Logic Module (Continued)
Table 5-45. Programmable Interval Timer Registers (Continued)
Bit
Description
5:4
Current Read/Write Mode.
00: Counter latch command.
01: R/W LSB only.
10: R/W MSB only.
11: R/W LSB, followed by MSB.
Current Counter Mode. 0-5.
BCD Mode.
3:1
0
0: Binary.
1: BCD (Binary Coded Decimal).
I/O Port 043h (R/W)
PIT Mode Control Word Register
Notes: 1. If bits [7:6] = 11: Register functions as Read Status Command and:
Bit 5 = Latch Count
Bit 4 = Latch Status
Bit 3 = Select Counter 2
Bit 2 = Select Counter 1
Bit 1 = Select Counter 0
Bit 0 = Reserved
2. If bits [5:4] = 00: Register functions as Counter Latch Command and:
Bits [7:6] = Selects Counter
Bits [3:0] = Don’t care
7:6
5:4
Counter Select.
00: Counter 0.
01: Counter 1.
10: Counter 2.
11: Read-back command (Note 1).
Current Read/Write Mode.
00: Counter latch command.
01: R/W LSB only.
10: R/W MSB only.
11: R/W LSB, followed by MSB.
Current Counter Mode. 0-5.
BCD Mode.
3:1
0
0: Binary.
1: BCD (Binary Coded Decimal).
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Table 5-46. Programmable Interrupt Controller Registers
Bit
Description
I/O Port 020h / 0A0h
Master / Slave PIC ICW1 (WO)
7:5
4
Reserved. Must be set to 0.
Reserved. Must be set to 1.
3
Trigger Mode.
0: Edge.
1: Level.
2
Vector Address Interval
0: 8 byte intervals.
1: 4 byte intervals.
1
0
Reserved. Must be set to 0 (cascade mode).
Reserved. Must be set to 1 (ICW4 must be programmed).
I/O Port 021h / 0A1h
Master / Slave PIC ICW2 (after ICW1 is written) (WO)
A[7:3]. Address lines [7:3] for base vector for interrupt controller.
Reserved. Must be set to 0.
7:3
2:0
I/O Port 021h / 0A1h
Master PIC ICW3
Master / Slave PIC ICW3 (after ICW2 is written) (WO)
7:0
Cascade IRQ. Must be 04h.
Slave PIC ICW3
7:0
Slave ID. Must be 02h.
I/O Port 021h / 0A1h
Master / Slave PIC ICW4 (after ICW3 is written) (WO)
7:5
4
Reserved. Must be set to 0.
Special Fully Nested Mode.
0: Disable.
1: Enable.
3:2
1
Reserved. Must be set to 0.
Auto EOI.
0: Normal EOI.
1: Auto EOI.
0
Reserved. Must be set to 1 (8086/8088 mode).
I/O Port 021h / 0A1h (R/W)
Master / Slave PIC OCW1
(except immediately after ICW1 is written)
7
6
5
4
3
IRQ7 / IRQ15 Mask.
0: Not Masked.
1: Mask.
IRQ6 / IRQ14 Mask.
0: Not Masked.
1: Mask.
IRQ5 / IRQ13 Mask.
0: Not Masked.
1: Mask.
IRQ4 / IRQ12 Mask.
0: Not Masked.
1: Mask.
IRQ3 / IRQ11 Mask.
0: Not Masked.
1: Mask.
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Table 5-46. Programmable Interrupt Controller Registers (Continued)
Bit
Description
2
IRQ2 / IRQ10 Mask.
0: Not Masked.
1: Mask.
1
0
IRQ1 / IRQ9 Mask.
0: Not Masked.
1: Mask.
IRQ0 / IRQ8 Mask.
0: Not Masked.
1: Mask.
I/O Port 020h / 0A0h
Master / Slave PIC OCW2 (WO)
7:5
Rotate/EOI Codes.
000: Clear rotate in Auto EOI mode
001: Non-specific EOI
010: No operation
100: Set rotate in Auto EOI mode
101: Rotate on non-specific EOI command
110: Set priority command (bits [2:0] must be valid)
111: Rotate on specific EOI command
011: Specific EOI (bits [2:0] must be valid)
4:3
2:0
Reserved. Must be set to 0.
IRQ Number (000-111)
I/O Port 020h / 0A0h
Master / Slave PIC OCW3 (WO)
7
Reserved. Must be set to 0.
6:5
Special Mask Mode.
00: No operation.
01: No operation.
10: Reset Special Mask Mode.
11: Set Special Mask Mode.
Reserved. Must be set to 0.
Reserved. Must be set to 1.
Poll Command.
4
3
2
0: Disable.
1: Enable.
1:0
Register Read Mode.
00: No operation.
01: No operation.
10: Read interrupt request register on next read of Port 20h.
11: Read interrupt service register on next read of Port 20h.
I/O Port 020h / 0A0h
Master / Slave PIC Interrupt Request and Service Registers
for OCW3 Commands (RO)
The function of this register is set with bits [1:0] in a write to 020h.
Interrupt Request Register
7
6
5
IRQ7 / IRQ15 Pending.
0: Yes.
1: No.
IRQ6 / IRQ14 Pending.
0: Yes.
1: No.
IRQ5 / IRQ13 Pending.
0: Yes.
1: No.
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Table 5-46. Programmable Interrupt Controller Registers (Continued)
Bit
Description
4
IRQ4 / IRQ12 Pending.
0: Yes.
1: No.
3
2
1
0
IRQ3 / IRQ11 Pending.
0: Yes.
1: No.
IRQ2 / IRQ10 Pending.
0: Yes.
1: No.
IRQ1 / IRQ9 Pending.
0: Yes.
1: No.
IRQ0 / IRQ8 Pending.
0: Yes.
1: No.
Interrupt Service Register
IRQ7 / IRQ15 In-Service.
7
6
5
4
3
2
1
0
0: No.
1: Yes.
IRQ6 / IRQ14 In-Service.
0: No.
1: Yes.
IRQ5 / IRQ13 In-Service.
0: No.
1: Yes.
IRQ4 / IRQ12 In-Service.
0: No.
1: Yes.
IRQ3 / IRQ11 In-Service.
0: No.
1: Yes.
IRQ2 / IRQ10 In-Service.
0: No.
1: Yes.
IRQ1 / IRQ9 In-Service.
0: No.
1: Yes.
IRQ0 / IRQ8 In-Service.
0: No.
1: Yes.
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Table 5-47. Keyboard Controller Registers
Bit
Description
I/O Port 060h
External Keyboard Controller Data Register (R/W)
Keyboard Controller Data Register. All accesses to this port are passed to the ISA bus. If the fast keyboard gate A20 and reset fea-
tures are enabled through bit 7 of the ROM/AT Logic Control Register (F0 Index 52h[7]), the respective sequences of writes to this port
assert the A20M# signal or cause a warm CPU reset.
I/O Port 061h
Port B Control Register (R/W)
Reset Value: 00x01100b
7
PERR#/SERR# Status. (Read Only) Indicates if a PCI bus error (PERR#/SERR#) was asserted by a PCI device or by the
SC1200/SC1201.
0: No.
1: Yes.
This bit can only be set if ERR_EN (bit 2) is set 0. This bit is set 0 after a write to ERR_EN with a 1 or after reset.
6
IOCHK# Status. (Read Only) Indicates if an I/O device is reporting an error to the SC1200/SC1201.
0: No.
1: Yes.
This bit can only be set if IOCHK_EN (bit 3) is set 0. This bit is set 0 after a write to IOCHK_EN with a 1 or after reset.
5
4
3
PIT OUT2 State. (Read Only) This bit reflects the current status of the of the PIT Counter 2 (OUT2).
Toggle. (Read Only) This bit toggles on every falling edge of Counter 1 (OUT1).
IOCHK# Enable
0: Generates an NMI if IOCHK# is driven low by an I/O device to report an error. Note that NMI is under SMI control.
1: Ignores the IOCHK# input signal and does not generate NMI.
2
1
0
PERR/ SERR Enable. Generate an NMI if PERR#/SERR# is driven active to report an error.
0: Enable.
1: Disable.
PIT Counter2 (SPKR)
0: Forces Counter 2 output (OUT2) to zero.
1: Allows Counter 2 output (OUT2) to pass to the speaker.
PIT Counter2 Enable.
0: Sets GATE2 input low.
1: Sets GATE2 input high.
I/O Port 062h
External Keyboard Controller Mailbox Register (R/W)
Keyboard Controller Mailbox Register.
I/O Port 064h
External Keyboard Controller Command Register (R/W)
Keyboard Controller Command Register. All accesses to this port are passed to the ISA bus. If the fast keyboard gate A20 and reset
features are enabled through bit 7 of the ROM/AT Logic Control Register (F0 Index 52h[7]), the respective sequences of writes to this
port assert the A20M# signal or cause a warm CPU reset.
I/O Port 066h
External Keyboard Controller Mailbox Register (R/W)
Keyboard Controller Mailbox Register.
I/O Port 092h
Port A Control Register (R/W)
Reset Value: 02h
7:2
1
Reserved. Must be set to 0.
A20M# Assertion. Assert A20# (internally).
0: Enable.
1: Disable.
This bit reflects A20# status and can be changed by keyboard command monitoring.
An SMI event is generated when this bit is changed, if enabled by F0 index 53h[0]. The SMI status is reported in
F1BAR0+I/O Offset 00h/02h[7].
0
Fast CPU Reset. WM_RST SMI is asserted to the BIOS.
0: Disable.
1: Enable.
This bit must be cleared before the generation of another reset.
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Table 5-48. Real-Time Clock Registers
Bit
Description
I/O Port 070h
RTC Address Register (WO)
This register is shadowed within the Core Logic module and is read through the RTC Shadow Register (F0 Index BBh).
7
NMI Mask.
0: Enable.
1: Mask.
6:0
RTC Register Index. A write of this register sends the data out on the ISA bus and also causes RTCALE to be triggered.
(RTCALE is an internal signal between the Core Logic module and the internal RTC controller.)
I/O Port 071h
RTC Data Register (R/W)
A read of this register returns the value of the register indexed by the RTC Address Register.
A write of this register sets the value into the register indexed by the RTC Address Register
I/O Port 072h
RTC Extended Address Register (WO)
7
Reserved.
6:0
RTC Register Index. A write of this register sends the data out on the ISA bus and also causes RTCALE to be triggered.
(RTCALE is an internal signal between the Core Logic module and the internal RTC controller.)
I/O Port 073h
RTC Data Register (R/W)
AA read of this register returns the value of the register indexed by the RTC Extended Address Register.
A write of this register sets the value into the register indexed by the RTC Extended Address Register
Table 5-49. Miscellaneous Registers
Bit
Description
I/O Port 0F0h, 0F1h
Coprocessor Error Register (W)
Reset Value: F0h
A write to either port when the internal FERR# signal is asserted causes the Core Logic Module to assert internal IGNNE#. IGNNE#
remains asserted until the FERR# de-asserts.
I/O Ports 170h-177h/376h-377h
Secondary IDE Registers (R/W)
When the local IDE functions are enabled, reads or writes to these registers cause the local IDE interface signals to operate according
to their configuration rather than generating standard ISA bus cycles.
I/O Ports 1F0h-1F7h/3F6h-3F7h
Primary IDE Registers (R/W)
When the local IDE functions are enabled, reads or writes to these registers cause the local IDE interface signals to operate according
to their configuration rather than generating standard ISA bus cycles.
I/O Port 4D0h
Interrupt Edge/Level Select Register 1 (R/W)
Reset Value: 00h
Notes: 1. If ICW1 - bit 3 in the PIC is set as level, it overrides the setting for bits [7:3] in this register.
2. Bits [7:3] in this register are used to configure a PCI interrupt mapped to IRQ[x] on the PIC as level-sensitive (shared).
7
6
5
4
IRQ7 Edge or Level Sensitive Select. Selects PIC IRQ7 sensitivity configuration.
0: Edge.
1: Level.
IRQ6 Edge or Level Sensitive Select. Selects PIC IRQ6 sensitivity configuration.
0: Edge.
1: Level.
IRQ5 Edge or Level Sensitive Select. Selects PIC IRQ5 sensitivity configuration.
0: Edge.
1: Level.
IRQ4 Edge or Level Sensitive Select. Selects PIC IRQ4 sensitivity configuration.
0: Edge.
1: Level.
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Table 5-49. Miscellaneous Registers (Continued)
Bit
Description
3
IRQ3 Edge or Level Sensitive Select. Selects PIC IRQ3 sensitivity configuration.
0: Edge.
1: Level.
2:0
Reserved. Must be set to 0.
I/O Port 4D1h
Interrupt Edge/Level Select Register 2 (R/W)
Reset Value: 00h
Notes: 1. If ICW1 - bit 3 in the PIC is set as level, it overrides the setting for bits 7:6 and 4:1 in this register.
2. Bits [7:6] and [4:1] in this register are used to configure a PCI interrupt mapped to IRQ[x] on the PIC as level-sensitive
(shared).
7
6
IRQ15 Edge or Level Sensitive Select. Selects PIC IRQ15 sensitivity configuration.
0: Edge.
1: Level.
IRQ14 Edge or Level Sensitive Select. Selects PIC IRQ14 sensitivity configuration.
0: Edge.
1: Level.
5
4
Reserved. Must be set to 0.
IRQ12 Edge or Level Sensitive Select. Selects PIC IRQ12 sensitivity configuration.
0: Edge.
1: Level.
3
2
1
0
IRQ11 Edge or Level Sensitive Select. Selects PIC IRQ11 sensitivity configuration.
0: Edge.
1: Level.
IRQ10 Edge or Level Sensitive Select. Selects PIC IRQ10 sensitivity configuration.
0: Edge.
1: Level.
IRQ9 Edge or Level Sensitive Select. Selects PIC IRQ9 sensitivity configuration.
0: Edge.
1: Level.
Reserved. Must be set to 0.
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Revision 6.0
6.0 Video Processor Module
The Video Processor module contains a high performance
Compatibility
video
back-end
accelerator,
a
video/graphics
• Supports Microsoft’s DirectDraw/Direct Video and
Display Control Interface (DCI) Version 2.0 for full
motion playback acceleration
Mixer/Blender, a Video Input Port (VIP), a Video Output
Port (VOP), and a TV encoder supporting three output
choices: TV, CRT, or TFT. The back-end accelerator func-
tions include horizontal and vertical scaling and filtering of
the video stream. The Mixer/Blender function includes
color space conversion, gamma correction, and mixing or
alpha blending the video and graphics streams. The high
performance TV encoder with horizontal scaling and flicker
filter provides all the necessary data formatting and timing
to create a quality TV output.
• Compliant with PC98 and PC99 V0.7
• Compatible with VESA, VGA, DPMS, and DDC2
standards for enhanced display control and power
management
TVOUT
• Supports graphics resolutions of 640x480 for NTSC, and
General Features
768x576 for PAL
• Hardware video acceleration
• Graphics/video overlay and blending
• Three-line flicker filter
• Integrated TV encoder
• Scaling to convert to TV resolution
• Integrated 10-bit TV DACs
• SCART support
• TVOUT block integrated in the Video Processor for
display interface to TV (NTSC/PAL)
• Integrated CRT and TV DACs and PLL
• Selection of interlaced and progressive video from the
• Macrovision copy protection version 7.1.L1 (SC1201
GX1 module and the Direct Video Port
only, see "Macrovision Product Notice" on page 445)
Video Input Port (VIP) Interface
• CCIR-656 compatible
• Direct pass-through of VBI data or direct pass-through
of active video data from VIP to the NTSC/PAL encoder
• Capture Video/VBI modes
• Direct Video/VBI modes
Integrated CRT and TV DACs and PLL
• Support up to 135 MHz (three 8-bit DACs)
• Integrated TV DACs (four 10-bit DACs)
Hardware Video Acceleration
— RS-343A/RS-170 compatible output
• Arbitrary X and Y interpolation using three line-buffers
• YUV-to-RGB color space conversion
• Horizontal filtering and downscaling
• PLL rate up to 135 MHz
Display Modes
• CRT modes:
• Supports 4:2:2, 4:2:0 YUV formats and RGB 5:6:5
— 640x480x16 bpp at 60-85 Hz vertical refresh rates
— 800x600x16 bpp at 60-85 Hz vertical refresh rates
— 1024x768x16 bpp at 60-85 Hz vertical refresh rates
— 1280x1024x8 bpp at 60-75 Hz vertical refresh rates
format
Graphics-Video Overlay and Blending
• Overlay of video up to 16 bpp
• TFT modes:
• Supports chroma key and color key for both graphics
— TFT on IDE: FPCLK max is 40 MHz
and video streams
— TFT on Parallel Port: FPCLK max is 80 MHz
— 640x480x16 bpp at 60-85 Hz vertical refresh rates
— 800x600x16 bpp at 60-85 Hz vertical refresh rates
— 1024x768x16 bpp at 60-75 Hz vertical refresh rates
— 1280x1024x8 bpp at 60 Hz vertical refresh rate
• Supports alpha-blending with up to three alpha windows
that can overlap one another
• 8-Bit alpha values with automatic increment or decre-
ment on each frame
• TV modes:
• RGB to YUV color space conversion for graphics, in
— NTSC: 720x480 and 640x480
— PAL: 720x576 and 768x576
— TEPBGA package does not support simultaneous
TV/CRT or TV/TFT operation
YUV blending mode (TVOUT display)
• Supports high quality video-blended images using
special YUV interlaced alpha-mixing for TVOUT
• Optional Gamma Correction for video or graphics
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Video Processor Module (Continued)
6.1 MODULE ARCHITECTURE
Figure 6-1 shows a top-level block diagram of the Video
Processor. For information about the relationship between
the Video Processor and the other modules of the
SC1200/SC1201, see Section 1.2 on page 17. The Video
Processor module includes the following functions:
• TV Encoder
— Horizontal scalers
— Scan rate converter
— Flicker filter
— VESA Video Interface Port Rev. 1.1 Task B encoder
— TV Timing Generator
— TV encoder
• Video Input Port
— CCIR-656 decoder
— Capture Video/VBI modes
• Outputs
— Direct Video/VBI modes
— TV interface with DACs
— CRT interface with DACs
— TFT interface
• Video Formatter
— Asynchronous video interface
— Horizontal/Vertical scalers
— Filters
— Video Output Port (VOP)
• Dot Clock PLL
• Mixer/Blender
The following subsections describe each block in detail.
— Overlay with color/chroma key
— Gamma correction
— Color space converters
— Alpha blender
GX1 Graphics Data
Capture Video/VBI Data to
GX1 Video Frame Buffer
Video Formatter
Horizontal Downscaler,
Line Buffer, Horizontal
and Vertical Upscalers,
and Filters
Video
Data
VIP
Video
Mux
VIP Data
Capture Video/VBI
Controller and
Bus Master,
Direct Video/VBI
Controller
TFT_IF
CRT_IF
Mixer/Blender
Overlay with Gamma
RAM and Alpha
Blending
VBI
Data
VBI
Mux
DACs
Video or VBI Data from GX1 Video Port
TVOUT
Flicker Filter,
VOP
Horizontal Scaling,
VESA Encoder,
Timing Generator,
and TV Encoder
TV_IF
DACs
Figure 6-1. Video Processor Block Diagram
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Video Processor Module (Continued)
6.2 FUNCTIONAL DESCRIPTION
To understand why the Video Processor functions as it
does, it is first important to understand the difference
between video and graphics. Video is pictures in motion,
which usually starts out in an encoded format (i.e.,
MPEG2, AVI, MPEG4) or is a TV broadcast. These pic-
tures or frames are generally dynamic and are drawn 24 to
30 frames per second. Conversely, graphic data is rela-
tively static and is drawn - usually using hardware accelera-
tors. Most IA devices need to support both video and
graphics displayed at the same time. For some IA devices,
such as set-top boxes, video is dominant. While for other
devices, such as consumer access devices and thin clients,
graphics is dominant. What this means for the Video Pro-
cessor is that for video centric devices, graphics overlays
the video; and for graphics centric devices, video overlays
the graphics.
Video Support
The SC1200/SC1201 gets video from two sources, either
the VIP block or the GX1 module’s video frame buffer. The
VIP block supports the CCIR-656 data protocol. The CCIR-
656 protocol supports TV data (NTSC or PAL) and defines
the format for active video data and vertical blanking inter-
val (VBI) data. Conforming CCIR-656 data matches exactly
what is needed for a TV: full frame, interlaced, 27 MHz
pixel clock, and 50 or 60 Hz refresh rate. Full frame pixel
resolution and the refresh rate depends on the TV stan-
dard: NTSC, PAL, or SECAM.
If the VIP input data is full frame (conforming data) and the
output is the TV interface, then the data can go directly
from the VIP block to the Video Formatter. This is known as
Direct Video mode. In this mode, the data never leaves the
Video Processor module. If the output is to a CRT or TFT
interface, or the VIP data is less than full frame (non con-
forming data), the VIP block will bus master the video data
to the GX1 module’s Video Frame Buffer. The GX1 mod-
ule’s Display Controller then moves the video data out of
the Video Frame Buffer and sends it to the Video Format-
ter. Using this method the temporal (refresh rate) and/or
spatial (image less then full screen) differences between
the VIP data and the output device are reconciled. This
method is known as Capture Video mode. How each mode
is setup and operates is explained further in Section 6.2.1
on page 323.
Video centric devices usually render video full frame. On a
TV, the video image is larger than the screen and will actu-
ally spill outside or overscan the TV’s viewable area by
about 10%. This is done intentionally to eliminate any black
border. Consequently graphic overlays, such as menus and
control buttons, must account for overscan when displaying
on a TV. Conversely, when the output device is a CRT mon-
itor or a TFT panel there is no overscan so the graphic
overlays do not have to deal with this issue. Common soft-
ware drivers can easily support either type of display
device.
Graphic centric devices render graphics full frame. Again, if
the TV is the output device, overscan comes into play, but
the graphic content cannot be allowed into the overscan
area. Software drivers and/or applications must take that
into account. The video overlay, when it is active, is usually
rendered less than full frame. For some IA devices the
video and graphics exchange dominance is application-
dependent. An example of this is an Internet enabled set-
top box where video is dominant during TV viewing and
graphics is dominant during Web browsing.
VBI Support
VBI (vertical blanking interval) data is placed in the video
data stream during a portion of the vertical retrace period.
The vertical retrace period physically consists of several
horizontal lines (24 for NTSC and 25 for PAL systems) of
non-active video. Data can be placed on some of these
lines for other uses.
The active video and vertical retrace period horizontal lines
are logically defined into 23 types: logical line 2 through
logical line 24 (no logical line 1). Logical lines 2 through 23
occur during the vertical retrace period and logical line 24
represents all the active video lines. Logical lines 10
through 21 for NTSC and 6 through 23 for PAL are the
nominal VBI lines. The rest of the logical lines, 2 through 9,
22, and 23 for NTSC and 2 through 6 for PAL occur during
the vertical retrace period but do not normally carry user
data. An example of VBI usage is Closed Captioning,
which occupies VBI logical line 21 for NTSC. Figure 6-2
and Figure 6-3 on page 322 show the (relationship
between the) physical scan lines and logical scan lines for
the odd and even fields in the NTSC format.
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Video Processor Module (Continued)
Vertical Retrace - Logical Lines 4-9 — Scan Lines 4-9
(Not normally User Data)
Vertical Retrace - Logical Lines 10-21 — Scan lines 10-21
(Nominal VBI Lines)
Vertical Retrace - Logical Lines 22, 23 — Scan lines 22, 23
(Not normally User Data)
VBI_Total_Count_Odd
Active Video
Logical Line 24 — Scan Lines 24-263
Vertical Retrace - Logical Line 24 — Scan Line 1
VBI_Line_Offset_Odd
VSYNC Start
VSYNC End
Vertical Retrace - Logical Lines 2, 3 — Scan Lines 2, 3
(Not normally User Data)
Figure 6-2. NTSC 525 Lines, 60 Hz, Odd Field
Vertical Retrace - Logical Lines 4-9 — Scan Lines 267-272
(Not normally User Data)
Nominal VBI Lines 10-21 — Scan lines 273-284
(Nominal VBI Lines)
Vertical Retrace - Logical Lines 22,23 — Scan lines 285, 286
(Not normally User Data)
VBI_Total_Count_Even
Active Video
Logical Line 24 — Scan Lines 287-525
Vertical Retrace - Logical Line 24 — Scan Line 264
Vertical Retrace - Logical Lines 2, 3 — Scan Lines 265, 266
(Not normally User Data)
VBI_Line_Offset_Even
VSYNC Start
VSYNC End
Figure 6-3. NTSC 525 Lines, 60 Hz, Even Field
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Video Processor Module (Continued)
6.2.1 Video Input Port (VIP)
processed by the CCIR-656 decoder. For Direct Video/VBI
modes, there are two FIFOs that buffer the CCIR-656
decoder’s data. A 2048-byte FIFO buffers Video data and a
128-byte FIFO buffers VBI data. The FIFOs are also used
to provide clock domain changes. The VIP interface clock
(nominally 27 MHz) is the input clock domain for all three
FIFOs. For the Capture Video/VBI FIFO, the data is
clocked out using the FPCI clock (33 or 66 MHz). For the
Direct Video FIFO, the Video data is clocked out using the
GX1’s Video port clock (75, 116, or 133 MHz GX1 core
clock divided by 2 or 4) and for the Direct VBI FIFO the
data is clocked out with the GX1’s pixel port clock (approxi-
mately 27 MHz only because VBI out is only supported for
TVs).
The VIP block is designed to interface the SC1200/SC1201
with external video processors (e.g., Geode CS1300 or
Sigma Designs EM8400) or external TV decoders (e.g.,
Philips SAA7114). It inputs CCIR-656 Video and VBI data
sourced by those devices, decodes the data, and delivers
the data directly to the Video Formatter (Direct Video/VBI
modes) or to the GX1 module’s Video Frame Buffer (Cap-
ture Video/VBI modes). Figure 6-4 shows a diagram of the
VIP block.
From the VIP block’s perspective, Direct Video/VBI modes
are always on. There are no registers that enable/disable
Direct Video/VBI modes. The data source selected at the
video mux (F4BAR0+Memory Offset 400h[1:0]) and VBI
mux (F4BAR0+Memory Offset 400h[2]) determine if the
data from the VIP interface is moved directly or must be
captured.
Since the VIP block treats Video data and VBI data inde-
pendently, this means that they can operate in Capture
Video/VBI or Direct Video/VBI modes independent of each
other, with some restrictions. Table 6-1 on page 324 shows
the supported Direct/Capture configurations.
Three FIFOs in the VIP block support the efficient move-
ment of Video and VBI data. For Capture Video/VBI
modes, a 128-byte FIFO buffers both Video and VBI data
CRT_VSYNC
GenLock
Stop DCLK
VIP_VSYNC
Control
Fast
X-Bus
to
Fast-PCI
Bridge
Capture Video/VBI
Controller and
Bus Master
Fast-PCI
GX1
Module
Fast-PCI Clock
Capture Video/VBI
FIFO
Video or VBI Data
Capture Video/VBI Data
VIP
Data
to Video
GX1 Video Clock
Direct Video Data
CCIR-656
Decoder
Formatter
to TVOUT
Direct Video
FIFO
Video
Mux
TV Clock
VIP
Clock
Direct VBI
FIFO
VBI
Mux
Direct VBI Data
F4BAR2
Control
Registers
VIP
Direct Video/VBI
Controller
Figure 6-4. VIP Block Diagram
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Video Processor Module (Continued)
6.2.1.1 Direct Video Mode
until the VIP vertical sync occurs (plus some additional
delay, via F4BAR0+Memory Offset 424h).
As stated previously, Direct Video mode is on by default so
no registers need to be programmed to support this mode
other than to select the direct video data at the video mux.
The video mux control register is located at F4BAR0+Mem-
ory Offset 400h[1:0].
The GenLock function provides
a
timeout feature
(GENLOCK_TOUT_EN, F4BAR0+Memory Offset 420h[4])
in case the video port input clock stops due to a problem
with incoming video.
GenLock
6.2.1.2 Direct VBI Mode
Because video input data from the VIP is sent directly, with-
out significant buffering, field-to-field synchronization is
required with the TV encoder, and frame-to-field synchroni-
zation is required with the GX1 module’s graphics data.
This synchronization is known as GenLock. The GenLock
registers are located at F4BAR0+Memory Offset 420h and
424h.
Direct VBI mode operation is very similar to Direct Video
mode and is also on by default. The VBI mux control is
located at F4BAR0+Memory Offset 400h[2]. Specific VBI
lines may be blocked or nulled before they are sent to the
TV Encoder, (F4BAR2+Memory Offsets 18h and 1Ch). VBI
GenLock is also required for Direct VBI mode to perform
correctly. See Section 6.2.1.1 for a more detailed explana-
tion on GenLock.
The odd/even fields of the video input data must be syn-
chronized with the odd/even fields produced by the TV
encoder. This field-to-field synchronization is accomplished
by setting the SG_GENLOCK_EN bit (F4BAR0+Memory
Offset 420h[0]). Field-to-field synchronization is only
required once.
6.2.1.3 Capture Video Mode
Capture Video mode is a process for bus mastering Video
data received from the VIP block to the GX1 module’s
Video Frame Buffer. The GX1 module’s Display Controller
then moves the data from the Video Frame Buffer to the
Video Formatter. Usually Capture Video mode is used
because the data coming in from the VIP block is interlaced
and has a 30 Hz refresh rate (NTSC format) and the output
device, CRT monitor or TFT panel, is progressive and has
a 60 to 85 Hz refresh rate. The Capture Video mode pro-
cess must convert the interlaced data to progressive data
and change the frames per second. There are two methods
to perform the interlaced to progressive conversion; Bob
and Weave. Each method uses a different mechanism to
up the refresh rate.
The GenLock control hardware is used to synchronize the
video input’s field with the GX1 module’s graphics frame.
The graphics data is always sent full frame. For the Gen-
Lock function to perform correctly, the GX1 module’s Dis-
play Controller must be programmed to have a slightly
faster frame time then the video input’s field time. This is
best accomplished by programming the GX1 module’s Dis-
play Controller with a few less (three to five) horizontal lines
then the VIP interface. GenLock is accomplished by stop-
ping the clock driving the GX1 module’s graphics frame
Table 6-1. Direct Mode and Capture Mode Configurations
Output
Video
Mode
VBI
Mode
Interface
Comments
Direct
Direct
Direct
TV
TV
Video data must be full frame. GX1 graphics/video frame buffers are not used.
Capture
Video data must be full frame. VBI data can be decoded, turned into graphic
information and placed in the GX1 module’s graphics frame buffer for display,
or it can be manipulated and placed into the video frame buffer as modified VBI
data.
Capture
Capture
Direct
TV
Unsupported
Capture
TV, CRT,
TFT
The only mode available for CRT and TFT displays and only necessary for TV
displays when video data is less then full frame. CRT and TFT displays do not
allow for VBI at all. However, VBI data can be decoded, turned into graphic
information and placed in the GX1 module’s graphics frame buffer for display.
Restriction: The GX1 module’s video frame buffer cannot be used to send both
video and VBI data.
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Video Processor Module (Continued)
Bob
– F4BAR2+Memory Offset 20h – Video Data Odd
Base Address
The Bob method displays the odd frame followed by the
even frame. If a full-scale image is displayed, each line in
the odd and even field must be vertically doubled (see Sec-
tion 6.2.2.5 "2-Tap Vertical and Horizontal Upscalers" on
page 330) because each odd and each even field only con-
tain one-half a frames worth of data. This means that the
Bob method reduces the video image resolution, but has a
higher effective refresh rate. If there is a change of refresh
rate from the VIP block to the display device, then a field
will sometimes be displayed twice. The advantage of this
method is that the process is simple as only half the data is
transmitted from the GX1 module’s Video Frame Buffer to
the Video Processor per a given amount of time, therefore
reducing the memory bandwidth requirement. The disad-
vantage is that there are some observable visual effects
due to the reduction in resolution.
– F4BAR2+Memory Offset 24h – Video Data Even
Base Address
– F4BAR2+Memory Offset 28h – Video Data Pitch
The Video Data Even Base Address must be sepa-
rated from the Video Data Odd Base Address by at
least the field data size. The Video Data Pitch register
must be programmed to 00000000h.
2) Program other VIP bus master support registers.
In F4BAR2+Memory Offset 00h, make sure that the
VIP FIFO bus request threshold is set to 32 bytes (bit
22 = 1) and that the Video Input Port mode is set to
CCIR-656. An interrupt needs to be generated so that
the GX1 module’s video frame buffer pointer can flip to
the field that has completed transfer to the video frame
buffer. So in F4BAR2+Memory Offset 04h, enable the
Field Interrupt bit. Auto-Flip is normally set to allow the
CCIR-656 Decoder to identify which field is being pro-
cessed. Capture video data needs to be enabled and
Run Mode Capture is set to Start Capture at beginning
of next field. Data is now being captured to the frame
buffer.
Figure 6-5 is an example of how the Bob method is per-
formed. The example assumes that the display device is a
CRT at 85 Hz refresh and single buffering is used for the
data. The example does not assume anything regarding
scaling that may be performed in the Video Processor. The
example is only presented to allow for a general under-
standing of how the SC1200/SC1201’s video support hard-
ware works and not as an all-inclusive statement of
operation.
3) Field Interrupt.
When the field interrupt occurs, the interrupt handler
must program the GX1 module’s video buffer start off-
set value (GX_BASE+Memory Offset 8320h) with the
address of the field that was just received from the VIP
interface. This action will cause the display controller
to ping-pong between the two fields. The new address
will not take affect until the start of a new display con-
troller frame. The field that was just received can be
known by reading the Current Field bit at
F4BAR2+Memory Offset 08h[24].
The following procedure is an example of how to create a
Bob method. This example assumes single buffering in the
GX1 module’s video frame buffer. The Video Processor
registers that control the VIP bus master only need to be
initialized.
1) Program the VIP bus master address registers.
Three registers control where the VIP video data is
stored in the GX1 module’s frame buffer:
Video Data Odd Base
(F4BAR2+Memory Offset 20h)
Address not changed
Video Data Even Base
(F4BAR2+Memory Offset 24h)
Address not changed during runtime
Odd
Field
Even
Field
during runtime
DC_VID_ST_OFFSET
(GX_BASE+Memory Offset 8320h)
Ping-pongs between the two buffers during runtime
GX1 Module’s Video Frame Buffer
30 frames per second
Buf #1
Capture video fill
sequence
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
Video subsystem
empty sequence
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
85 frames per second
Figure 6-5. Capture Video Mode Bob Example Using One Video Frame Buffer
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Video Processor Module (Continued)
Weave
The Video Data Even Base Address must be sepa-
rated from the Video Data Odd Base Address by one
horizontal line. The Video Data Pitch register must be
programmed to one horizontal line.
The Weave method assembles the odd field and even field
together to form the complete frame, and then renders the
“weaved” frames to the display device. The Video data is
converted from interlaced to progressive. Since both fields
are rendered simultaneously, the GX1 module’s video
frame buffer must be at least double buffered. The Weave
method has the advantage of not creating the temporal
effects that Bob does. The disadvantage of Weave is twice
as much data is transferred from the video frame buffer to
the Video Processor; meaning that Weave uses more
memory bandwidth.
2) Program other VIP bus master support registers.
Ensure the VIP FIFO Bus Request Threshold is set to
32 bytes (F4BAR2+Memory Offset 00h[22] = 1) and
the Video Input Port mode is set to CCIR-656
(F4BAR2+Memory Offset 00h[1:0] = 10). An interrupt
needs to be generated so that the GX1 module’s video
frame buffer pointer can flip to the field that has com-
pleted transfer to the video frame buffer. So the Field
Interrupt bit (F4BAR2+Memory Offset 04h[16] = 1).
must be enabled. Auto-Flip is normally set
(F4BAR2+Memory Offset 04h[10] = 0) to allow the
CCIR-656 decoder to identify which field is being pro-
cessed. Capture video data needs to be enabled
(F4BAR2+Memory Offset 04h[10] = 1) and Run Mode
Capture is set to Start Capture (F4BAR2+Memory Off-
set 04h[1:0] = 11) at beginning of next field. Data is
now being captured to the frame buffer.
Figure 6-6 on page 327 is an example of the Weave
method in action. As in the Bob example (Figure 6-5), a
CRT monitor at 85 Hz refresh is assumed. Double buffering
of the incoming data is also assumed. The example does
not assume anything about any scaling that may be done in
the Video Processor. No attempt has been made to assure
that this example is absolutely workable. The example is
only presented to allow for a general understanding of how
the SC1200/SC1201’s video support hardware works.
3) Field Interrupt.
The following procedure is an example of how to create the
Weave method. Since at least double buffering is required,
more of the VIP’s control registers are used for Weave than
required for Bob during video runtime.
When the field interrupt occurs on the completion of an
odd field, the interrupt must program the Video Data
Odd Base Address with the other buffer’s address. The
odd field will ping-pong between the two buffers. When
the interrupt is due to the completion of an even field,
the interrupt handler must program the GX1 module’s
video buffer start offset value (GX_BASE+Memory
Offset 8320h) with the address of the frame (both odd
and even fields) that was just received from the VIP
block. This new address will not take affect until the
start of a new frame. It must also program the Video
Data Even Base Address with the other buffer so that
the even field will ping-pong just like the odd field. The
field just received can be known by reading the Cur-
rent Field bit (F4BAR2+Memory Offset 08h[24]).
1) Program the VIP bus master address registers.
Three registers control where the VIP video data is
stored in the GX1 module’s frame buffer:
– F4BAR2+Memory Offset 20h – Video Data Odd
Base Address
– F4BAR2+Memory Offset 24h – Video Data Even
Base Address
– F4BAR2+Memory Offset 28h – Video Data Pitch
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Video Processor Module (Continued)
Ping-pongs between the two buffers during runtime
Video Frame Buffer #1
Line 1 Odd Field
Video Frame Buffer #2
Line 1 Odd Field
Video Data Odd Base
F4BAR2+Memory Offset 20h
Video Data Even Base
F4BAR2+Memory Offset 20h
Line 1 Even Field
Video Data Even Base
F4BAR2+Memory Offset 24h
Video Data Even Base
F4BAR2+Memory Offset 24h
Line 1 Even Field
Line 2 Odd Field
Line 2 Odd Field
Line 2 Even Field
Line 2 Even Field
VID_START_OFFSET
GX_BASE+Memory Offset 8320h
Ping-pongs between the
Line n-1 Odd Field
Line n-1 Odd Field
Line n-1 Even Field
Line n Odd Field
two buffers during runtime
Line n-1 Even Field
Line n Odd Field
Odd and Even fields are
“Weaved” together
Line n Even Field
Line n Even Field
GX1 Module’s Video Frame Buffer
Buf #1
Buf #2
30 frames per second
3
7
11
10 1 12 13 14 16 17
15
18
Capture video fill sequence
1
2
4
5
4
6
8
9
5
5
GX1 Module’s Display
Controller empty sequence
1
2
3
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
85 frames per second
Figure 6-6. Capture Video Mode Weave Example Using Two Video Frame Buffers
6.2.1.4 Capture VBI Mode
2) The altered VBI data can be sent to the TVOUT block
of the Video Processor via the video frame buffer. See
VIP block diagram (Figure 6-4 on page 323). The
Closed Captioning data could be altered and then sent
out this way. One reason to capture the Closed Cap-
tioning data would be to do a language conversion. If
the VIP block is in Capture Video mode then this
option is not possible because the video frame buffer
can be used for sending video or VBI, but not simulta-
neously.
There are three types of VBI data defined by the CCIR-656
protocol: Task A data, Task B data, and Ancillary data. The
VIP block supports the capture for each data type. Gener-
ally Task A data is the data type captured. Just as in Cap-
ture Video mode, there are three registers that tell the bus
master where to put the VBI data in the GX1 module’s
frame buffer. Once the VBI data has been captured, the
data can be manipulated or decoded. The VIP block has
two options of what to do with the altered VBI data. These
options are independent functions so both options can be
done simultaneously.
The registers, F4BAR2+Memory Offset 40h, 44h, and 48h,
tell the bus master the destination addresses for the VBI
data in the GX1 module’s frame buffer. Five bits
(F4BAR2+Memory Offset 00h[21:17]) are used to tell the
bus master the data types to store. Capture VBI mode
needs to be enabled at F4BAR2+Memory Offset
04h[9,1:0]. The Field Interrupt bit (F4BAR2+Memory Offset
04h[16]) should be used by the software driver to know
when the captured VBI data has been completed for a field.
1) The data can be used by an application. An example
of this would be an Internet address that is encoded on
one or more of the VBI lines, or have an application
decode the Closed Captioning information put in the
graphics frame buffer.
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Video Processor Module (Continued)
6.2.2 Video Block
RGB 5:6:5 – For this format each pixel is described as a
16-bit value:
The Video block receives video data from the VIP block or
the GX1 module’s video frame buffer. The video data is for-
matted and scaled and then sent to the Mixer/Blender. The
video data also changes clock domains while in the Video
block. It is clocked in with the GX1 module’s video clock
and it is clocked out with the GX1 module’s graphics clock.
A diagram of the Video block is shown in Figure 6-7.
Bits [15:11] = Red
Bits [10:5] = Green
Bits [4:0] = Blue
YUV 4:2:0 – This format is not supported by the GX1 mod-
ule. The Horizontal Downscaler in the Video block cannot
be used if the video data is in this format. In this format, 4
bytes of data are used to describe two pixels. The 4 bytes
contain two Y values one for each pixel; one U and one V
for both pixels. For each horizontal line, all the Y values are
received first. The U values are received next and the V
values are received last. For example for a horizontal line
that has 720 pixels, there are 720 bytes of Y, followed by
360 bytes of U, followed by 360 bytes of V.
6.2.2.1 Video Input Formatter
The Video Input Formatter accepts video data 8 bits at a
time in YUV 4:2:2, YUV 4:2:0, or RGB 6:5:6 format. The
GX1 module’s video clock is the source clock. The data can
be interlaced or progressive. When the data comes directly
from the VIP block it is usually interlaced. The video format
is configured via the EN_42X bit (F4BAR0+Memory Offset
00h[28] and the GV_SEL bit (F4BAR0+Memory Offset
4Ch[13]). The byte order for each format is configured in
the VID_FMT bits (F4BAR0+Offset 00h[3:2]).
YUV 4:2:2 – In this format each DWORD in the horizontal
line represent two pixels. There are two Y values and one
each U and V in a DWORD. Just as in the YUV 4:2:0 for-
mat, each U and V value describes the two pixels.
Video Input
Direct
GX1
Video 8 Module
8
Line Buffer 0
4-Tap Horizontal
Downscaler
Video Input
Formatter
Formatter
4:4:4
Line Buffer 1
Line Buffer 2
m
1
or
m+1
m+1
24
24
(3x360x32 bit)
(4:2:2 or 4:2:0)
2-Tap Vertical
Interpolating Upscaler
24
YUV 4:4:4/RGB 5:6:5
2-Tap Horizontal
Interpolating Upscaler
Figure 6-7. Video Block Diagram
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Video Processor Module (Continued)
6.2.2.2 Horizontal Downscaler with 4-Tap Filtering
The Video Processor implements up to 8:1 horizontal
downscaling with 4-tap filtering for horizontal interpolation.
Filtering is performed on video data input to the Video Pro-
cessor. This data is fed to the filter and then to the down-
scaler. There is a bypass path for both filtering and
downscaling logic. If this bypass is enabled, video data is
written directly into the line buffers. (See Figure 6-8.)
Maintaining Aspect Ratio
The main purpose of the horizontal downscaler is to main-
tain the aspect ratio of graphics data displayed on a TV,
which was originally generated for CRT display.
NTSC has an aspect ratio that is slightly different than a
CRT. When graphics is generated for a CRT and is dis-
played on a TV, the resulting TV image is narrowed. To cor-
rect the aspect ratio, graphics data should be generated in
640x480 resolution. The full screen video is in 720x480
resolution. The 4-tap horizontal downscaler must be
enabled to bring the video data down to the same resolu-
tion as the graphics data to allow for proper mixing/blend-
ing. In the TVOUT block (see Section 6.2.4 on page 337)
there is a horizontal upscaler/downscaler which is used to
bring the mixed/blended data back up to the required
720x480 resolution for TV. This process stretches the
graphics data horizontally and corrects the aspect ratio.
Filtering
There are four 4-bit coefficients which can have pro-
grammed values of 0 to 15. The filter coefficients can be
programmed via the Video Downscaler Coefficient register
(F4BAR0+Memory Offset 40h) to increase picture quality.
Horizontal Downscaler
The Video Processor supports horizontal downscaling. The
downscaler can be implemented in the Video Processor to
shrink the video window by a factor of up to 8:1, in 1-pixel
increments. The downscaler factor (m) is programmed in
the Video Downscaler Control register (F4BAR0+Memory
Offset 3Ch[4:1]). If bit 0 of this register is set to 0, the down-
scaler logic is bypassed.
PAL also has an aspect ratio different than a CRT. But
instead of the graphics being narrowed, it is stretched. To
correct this aspect ratio error the graphics data should be
generated in 768x576 resolution. The full screen video res-
olution is 720x576 and it must be scaled up using the hori-
zontal upscaler (see Section 6.2.2.5) to 768x576. In the
TVOUT block the horizontal upscaler/downscaler is used to
downscale the mixed/blended data to the required 720x576
resolution. This process narrows the graphics data horizon-
tally and corrects the aspect ratio.
The horizontal downscaler supports downscaling of video
data input format YUV 4:2:2 only.
The downscaler supports up to 29 downscaler factors.
There are two types of factors:
• Type A is (1/m+1). One pixel is retained, and m pixels
are dropped. This enables downscaling factors of 1/16,
1/15, 1/14, 1/13, 1/12, 1/11, 1/10, 1/9,1/8, 1/7, 1/6, 1/5,
1/4, 1/3, and 1/2.
For both NTSC and PAL, using the two scalers reduces the
quality of the video. Graphics data aspect ratio correction
should only be done when the graphics data (such as inter-
net content) is generated expecting a CRT display’s aspect
ratio. When graphics data is the only content viewed, this 4-
tap horizontal downscaler is not used but the TVOUT
block’s horizontal upscaler should still be used for graphics
data aspect ratio correction.
• Type B is (m/m+1). m pixels are retained, and one pixel
is dropped. This enables downscaling factors of 2/3, 3/4,
4/5, 5/6, 6/7, 7/8, 8/9, 9/10, 10/11, 11/12, 12/13, 13/14,
14/15, and 15/16.
Bit
6
of the Video Downscaler Control register
(F4BAR0+Memory Offset 3Ch) selects the type of down-
scaling factor to be used.
Note: There is no vertical downscaling in the Video Pro-
cessor.
Bypass
To Line
Buffers
Video
4-Tap
Input
Horizontal
Downscaler
Filtering
4x4
Coefficients
Downscale
Factors
Figure 6-8. Horizontal Downscaler Block Diagram
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Video Processor Module (Continued)
6.2.2.3 Line Buffers
6.2.2.5 2-Tap Vertical and Horizontal Upscalers
After the video data has been buffered, the upscaling algo-
rithm can be applied. The Video Processor employs a Digi-
tal Differential Analyzer-style (DDA) algorithm for both
horizontal and vertical upscaling. The scaling parameters
are programmed via the Video Upscale register
(F4BAR0+Memory Offset 10h). The scalers support up to
8x factors for both horizontal and vertical scaling. The
scaled video pixel stream is then passed through bi-linear
interpolating filters (2-tap, 8-phase) to smooth the output
video, significantly enhancing the quality of the displayed
image.
After the data has been optionally horizontally downscaled
the video data is stored in a 3-line buffer. Each line is 360
DWORDs, which means a line width of up to 720 pixels can
be stored. This buffer supports two functions. First, the
clock domain of the video data changes from the GX1
module’s video clock to the GX1 module’s graphics clock.
This clock domain change is required because the video
data and graphics data can only be mixed/blended in the
same clock domain. The second function the line buffer
performs is to provide the necessary look ahead and look
behind data in the vertical direction for the vertical
upscaler. There is no direct program control of the line
buffer.
The X and Y Upscaler uses the DDA and linear interpolat-
ing filter to calculate (via interpolation) the values of the pix-
els to be generated. The interpolation formula uses Ai,j,
Ai,j+1, Ai+1,j, and Ai+1,j+1 values to calculate the value of
intermediate points. The actual location of calculated
points is determined by the DDA algorithm.
6.2.2.4 Formatter
Video data in YUV 4:2:2 or YUV 4:2:0 format is converted
to YUV 4:4:4 format. RGB data is not translated. There is
no direct program control of the Formatter.
The location of each intermediate point is one of eight
phases between the original pixels (see Figure 6-9).
Notes:
A
i,j
A
i,j+1
x and y are 0 - 7
x
y
8 – y
y
b
b
= (A )----------- + (A
)--
1
2
i, j
i + 1, j
8
8
8 – y
y
b
z
b
2
1
= (A
)----------- + (A
)--
i, j + 1
i + 1, j + 1
8
8
8 – x
x
z = (b )----------- + (b )--
1
2
8
8
A
A
i+1,j+1
i+1,j
Figure 6-9. Linear Interpolation Calculation
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Video Processor Module (Continued)
6.2.3 Mixer/Blender Block
tion 6.2.3.1) is used on the video data when RGB mix-
ing/blending is desired and the RGB to YUV CSC is used
on the graphics data when YUV blending is desired. If
Gamma Correction (see Section 6.2.3.2) on the video data
is desired, it must be done in the color space of the input
video data, which can be either YUV or RGB. If Gamma
Correction on the graphics data is desired, it must be done
in the color space of the input graphics data, which is RGB.
The Mixer/Blender block of the Video Processor module
performs all the necessary functions to properly mix/blend
the video data and the graphics data. These functions
include Color Space Conversion (CSC), optional Gamma
correction, color/chroma key, and the mixing/blending logic.
See Figure 6-10 for block diagram of the Mixer/Blender
Block.
Video/Graphics mixing/blending can be performed in either
the YUV or RGB format. The YUV to RGB CSC (see Sec-
CSC_FOR_VIDEO
GV_GAMMA_SEL
GV_GAMMA_SEL * GAMMA_EN
Video, 4:4:4
YUV or RGB
CSC
YUV to
RGB
Optional
Gamma
Correction
RAM
Graphics,
RGB
CRT DACs and
TFT Interface
/GV_GAMMA_SEL * GAMMA_EN
FLICKER_FILT_CNTRL = 01
0
1
Color/Chroma
Key and
Mixer/Blender
1/2 Y
Flicker
Filter
0
1
YUV Data
TVOUT Block
CSC
RGB to
YUV
CSC_FOR_
GRAPHICS
Cursor Color Key
Compare
Compare
Color/Chroma Key
COLOR_CHROMA_SEL
Figure 6-10. Mixer/Blender Block Diagram
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Video Processor Module (Continued)
The video data can be in progressive or interlaced format,
while the graphics data is always in the progressive format.
The Mixer/Blender can mix/blend either format of video
data with graphics data. F4BAR0+Memory Offset 4Ch[9]
programs the mix/blend format. Considering the color
space and the data format, the Mixer/Blender supports five
types of mixing/blending. Some of the mixing/blending
types have additional programming considerations to
enable them to work optimally. The valid mixing/blending
configurations are listed in see Table 6-2 along with any
additional programming requirements.
Table 6-2. Valid Mixing/Blending Configurations
Mixing/Blending1
(Bit)
Flicker
Filter2 (Bit)
13
11
10
9
30
29
Mode
Comment
0
0
1
0
0
0
Input: YUV Progressive Video
Mixing: RGB
•
TV Display – Supported but not recommended.
— Two color space conversions are required.
— Non-optimal operation of the flicker filter.
Flicker Filter: ¼, ½, ¼
•
CRT/TFT Display.
— Produces highest quality RGB output (see
Section 6.2.1.3 "Capture Video Mode", Weave
subsection on page 326).
•
•
CRT/TFT and TV Display.
— Can be used to support simultaneous operation.
1
0
0
0
0
0
Input: RGB Progressive Video
Mixing: RGB
TV Display – Supported but not recommended.
— Non-optimal operation of the flicker filter.
•
CRT/TFT Display.
Flicker Filter: ¼, ½, ¼
— Produces highest quality RGB output (see
Section 6.2.1.3 "Capture Video Mode", Weave
subsection on page 326).
•
•
CRT/TFT and TV Display.
— Can be used to support simultaneous operation.
0
1
0
1
0
1
Input: YUV Interlaced Video
Mixing: YUV
TV Display – Supported and recommended.
— Produces the highest quality TV output.
— No video data color space conversions are
required
Flicker Filter: ½, 1, ½
— Optimally uses the flicker filter.
•
•
CRT/TFT Display - Not supported.
0
0
1
0
0
1
0
0
0
0
0
0
Input: YUV Progressive Video
Mixing: YUV
TV Display – Supported but not recommended.
— Non-optimal operation of the filter flicker
•
•
•
CRT/TFT Display - Not supported.
Typically Direct Video mode.
Flicker Filter: ¼, ½, ¼
Input: YUV Interlaced Video
upscaled by 2
TV Display – Supported but not recommended.
— Two color space conversions are required.
— Non-optimal operation of the filter flicker
Mixing: RGB
Flicker Filter: ¼, ½, ¼
•
•
CRT/TFT Display.
— Must be vertically upscaled by a factor of 2 (see
Section 6.2.2.5 "2-Tap Vertical and Horizontal
Upscalers" on page 330).
CRT/TFT and TV Display.
— Can be used to support simultaneous operation.
1. F4BAR0+Memory Offset 4Ch[13, 11:9].
2. F4BAR0+Memory Offset 814h[30:29].
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Video Processor Module (Continued)
6.2.3.1 YUV to RGB CSC in Video Data Path
If the video data is in the YUV color space and RGB mix-
ing/blending is desired, this CSC must be enabled. The
CSC_FOR_VIDEO bit, F4BAR0+Memory Offset 4Ch[10],
controls this CSC.
RGB graphics data or mixed/blended graphics/video data
is passed through this CSC to obtain 24-bit YUV data using
the following CCIR-601-1 recommended formula:
• Y = 0.257R + 0.504G + 0.098B + 16
• U = -0.148R – 0.291G + 0.439B + 128
• V = 0.439R – 0.368G – 0.071B + 128
YUV video data is passed through this CSC to obtain 24-bit
RGB data using the following CCIR-601-1 recommended
formula:
The CSC clamps inputs to prevent them from exceeding
acceptable limits.
• R = 1.1640625(Y – 16) + 1.59375(V – 128)
• G = 1.1640625(Y – 16) – 0.8125(V – 128) –
6.2.3.4 1/2 Y Flicker Filter
See Section 6.2.4.1 "Flicker Filter and Scan Rate Conver-
sion" on page 337 for details regarding the flicker filter.
0.390625(U – 128)
• B = 1.1640625(Y – 16) + 2.015625(U – 128)
The CSC clamps inputs to prevent them from exceeding
acceptable limits.
6.2.3.5 Color/Chroma Key
A color/chroma key mechanism is used to support the
Mixer/Blender logic. There are two keys: key1 is for the cur-
sor and key2 is for graphics or video data. Key1, the cursor
key, is always a color key. The cursor color key registers
are located at, F4BAR0+Memory Offset 50h-5CF. How the
cursor key mechanism works with the Mixer/Blender is
explained in Section 6.2.3.6. COLOR_CHROMA_KEY
(F4BAR0+Memory Offset 04h[20]) determines whether
key2 is a color key or a chroma key. The Video Color Key
Register (F4BAR0+Memory Offset 14h) stores the key.
Color keying is used when video is overlaid on the graphics
(GFX_INS_VIDEO, F4BAR0+Memory Offset 4Ch[8] = 0).
Chroma keying is used when graphics is overlaid on the
video (GFX_INS_VIDEO = 1). How the color/chroma key
mechanism works with the Mixer/Blender is explained in
Section 6.2.3.6.
6.2.3.2 Gamma Correction
Either the video or graphics data can be routed through an
integrated palette RAM for Gamma correction. There are
three 256-byte RAMs, one for each color component value.
Gamma correction supported in the YUV or RGB color
space for the video data and RGB color space for the
graphics data. Gamma correction is accomplished by treat-
ing each color component as an address into each RAM.
The output of the RAM is the new color. A simple RGB
Gamma correction example is to increase each color com-
ponent by one. The address 00h in the RAMs would con-
tain the data 01h. The address 01h would contain the data
02h and so on. This would have the effect of increasing
each original Red, Green, and Blue value by one.
• G_V_GAMMA, F4BAR0+Memory Offset 04h[21] selects
which data path (video or graphics) to send to the
Gamma correction block. GAMMA_EN,
6.2.3.6 Color/Chroma Key and Mixer/Blender
The Mixer/Blender takes each pixel of the graphics and
video data streams and mixes or blends them together.
Mixing is simply choosing the graphics pixel or the video
pixel. Blending takes a percentage of a graphics pixel
(Alpha_value * Graphics_pixel_value) and percentage of
the video pixel (1 - Alpha_Value * Video_pixel_value) and
adds them together. The percentages of each add up to
100%. The actual formula is:
F4BAR0+Memory Offset 28h[0] enables the Gamma
correction function. To load the Gamma correction
palette RAM, use F4BAR0+Memory Offset 1Ch and
20h.
6.2.3.3 RGB to YUV CSC
The RGB to YUV CSC serves two options: YUV blending
(TV output mode only) and RGB blending (TV, CRT, and
TFT output modes). Through several multiplexers, this
CSC is used to convert the graphics data from RGB to YUV
for YUV blending (CSC_FOR_GFX = 1, F4BAR0+Memory
Offset 4Ch[11]). When RGB blending is enabled
(CSC_FOR_GFX = 0), the CSC is used post blending to
convert the mixed/blended data from RGB to YUV for the
TVOUT block.
• Blended Pixel = (Alpha_value * Graphics_pixel_value) /
256 + ((256 – Alpha_value) * Video_pixel_value) / 256
Where: Alpha_value = 0 to 255
Mixing and blending are supported simultaneously for
every rendered frame, however, each pixel can only be
mixed or blended. The mix or blend question is decided by
the pixel position, whether video is overlaid on the graphics
or visa versa (GFX_INS_VIDEO, F4BAR0+Memory Offset
4Ch[8]), and several programmed “windows”. Figure 6-
11illustrates and example frame.
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Video Processor Module (Continued)
Graphics Window
Cursor Window
The graphics window is defined in the GX1 module’s dis-
play controller and is always the full screen resolution.
The cursor window can be managed two ways: with the
GX1 module’s hardware cursor or a software cursor. When
using the hardware cursor, the displayed colors of the hard-
ware cursor must be the cursor color keys (see Section
4.5.3 “Hardware Cursor” in the GX1 datasheet). When the
software cursor is used, the cursor size and position are
not defined using registers. The cursor size, position, and
image are determined through the use of the cursor color
key colors in the graphics frame buffer. When the cursor is
described in this manner, the cursor can be of any size and
shape.
Video Window
The video window tells the Mixer/Blender where the video
window is and its size. If Direct Video mode is enabled (see
Section 6.2.1.1 "Direct Video Mode" on page 324), the
video window must be defined as full screen (720x480 for
NTSC, 720x576 for PAL). Vertical scaling is not allowed.
Horizontal scaling is allowed. If the video source is from the
GX1 module’s video frame buffer (which includes Capture
Video mode, see Section 6.2.1.3 "Capture Video Mode" on
page 324) then the video data can be scaled both horizon-
tally and vertically. The video data size, scaled or unscaled,
must equal the video window size. The Video X Position
(horizontal) and Video Y Position (vertical) registers
(F4BAR0+Memory Offset 08h and 0Ch) define the video
window.
Alpha Windows
Up to three alpha windows can be defined. They are used
only for blending. They can be of any size up to the graph-
ics window size and they may overlap. To support overlap-
ping of the alpha windows they can be prioritized as to
which one is on top (F4BAR0+Memory Offset 4Ch[20:16]).
The alpha windows are programmed at F4BAR0+Memory
Offset 60h-88h.
Graphics Window (GFX_INS_VIDEO = 0)
Video Window
Video X
Position Register
Cursor
Window
Video Y
Position
Register
Alpha
Alpha Window #1
Window 3
Y Position
Register
Alpha Window 3
ALPHA1_WIN_PRIORITY = 10
ALPHA2_WIN_PRIORITY = 01
ALPHA3_WIN_PRIORITY = 00
X Position
Register
Alpha Window #3
Figure 6-11. Graphics/Video Frame with Alpha Windows
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Video Processor Module (Continued)
Mixing/Blending Operation
Table 6-3 on page 335 shows the truth table used to create
the flow diagram, Figure 6-12 on page 336, that the
Mixer/Blender logic uses to determine each pixels disposi-
tion.
Table 6-3. Truth Table for Alpha Blending
Graphics
Data Match Data Match
Graphics
Video Data
Match
COLOR_
CHROMA_SEL1
Cursor
Color Key
Normal
Color Key
Normal
Color Key
Windows
Configuration2
Mixer Output
x
x
x
x
x
Yes
No
x
x
x
x
Cursor Color
Not in Video
Window
Graphics Data
Graphics Color
Key
Not in an Alpha
Window
GFX_INS_VIDEO = 0
No
No
No
No
Yes
No
x
x
x
x
x
Video Data
Graphics Data
Video Data
(COLOR_
CHROMA_SEL
= 0)
GFX_INS_VIDEO = 1
Inside Alpha
Window x
ALPHAx_COLOR_REG_EN = 1
Yes
Color from
Color Register
ALPHAx_COLOR_REG_EN = 0
x
No
No
Yes
No
x
x
Video Data
Alpha-blended
Data
Video Chroma
Key
Not in an Alpha
Window
GFX_INS_VIDEO = 0
No
No
No
No
x
x
x
x
Yes
No
x
Graphics Data
Video Data
(COLOR_
CHROMA_SEL
= 1)
GFX_INS_VIDEO = 1
Graphics Data
Inside Alpha
Window x
ALPHAx_COLOR_REG_EN = 1
Yes
Color from
Color Register
ALPHAx_COLOR_REG_EN = 0
x
No
No
x
x
Yes
No
Graphics Data
Alpha-blended
Data
1. COLOR_CHROMA_SEL: F4BAR0+Memory Offset 04h[20].
2. GFX_INS_VIDEO: F4BAR0+Memory Offset 4Ch[8].
ALPHAx_COLOR_REG_EN: F4BAR0+Memory Offsets 68h[24], 78h[24], and 88h[24].
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Video Processor Module (Continued)
Start
Cursor color
key matches
graphics value
Yes
Yes
Use selected
cursor color for
pixel
No
Pixel outside
the video
window
Use graphics
value for this pixel
No
“Graphics2
inside Video”
is enabled
Pixel inside1
alpha window
No
Yes
Yes
Yes
No
Blend graphics
values and video
values using the
alpha value for
this window
Pixel value3
matches normal
color key
Pixel value3
matches normal
color key
No
No
Yes
Replace the value
with the color
register value
Color register
enabled for this
window
Yes
Yes
COLOR_CHROMA
_SEL = 1
COLOR_CHROMA
_SEL = 1
Yes
No
No
No
Yes
COLOR_CHROMA
_SEL = 1
No
Use video
value for this
pixel
Use video
value for this
pixel
Use graphics
value for this
pixel
Use graphics
value for this pixel
Notes:
1) Alpha window should not be placed outside of the video window.
2) “Graphics inside Video” is enabled via bit GFX_INS_VIDEO in the Video De-interlacing and Alpha Control register
(F4BAR0+Memory Offset 4Ch[8]).
3) The “Pixel Value” refers to either the Video value or the Graphics value, depending on the setting of bit COLOR_CHROMA_SEL
in the Display Configuration register (F4BAR0+Memory Offset 04h[20]).
Figure 6-12. Color Key and Alpha Blending Logic
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Video Processor Module (Continued)
6.2.4 TVOUT Block
Flicker Filter, Interlaced Video and
YUV Mixing/Blending Mode
The TVOUT block provides a full-featured TV output signal.
NTSC TV and PAL TV formats are both supported. A YUV
progressive scan image is delivered to the TVOUT block
from the Mixer/Blender block. Integrated horizontal scaling,
flicker filtering, scan rate conversion, and TV encoder pro-
duce a high quality TV output. See TVOUT block diagram,
Figure 6-13.
This is the recommended mode. With this mode only the
graphics data is flicker filtered. Interlaced video and YUV
blending must be the Mixer/Blender block’s mode (see Sec-
tion 6.2.3 "Mixer/Blender Block" on page 331). In this
mode, the Mixer/Blender block supports the flicker filter
process (see Figure 6-10 on page 331). Then the
mixed/blended data is flicker filtered using the formula
shown in Table 6-4. Using the ½, 1, ½ coefficients the
graphics data is pre-divided by 2 in the Mixer/Blender
block. The video data is interlaced so the previous and next
line of the video data stream is null. Therefore when the
coefficients are applied to the mixed data, the graphics
data is modified and the video data is not.
6.2.4.1 Flicker Filter and Scan Rate Conversion
The flicker filter uses a 3-line moving window buffer, and
has fixed coefficients. The maximum line width is 768 pix-
els. F4BAR0+Memory Offset 814h[30:29] enables the
flicker filter’s two operating modes: Flicker filter interlaced
video data and flicker filter progressive video data.
Video Output Port
VESA
YUV Image from
Mixer/Blender
Encoder
Flicker Filter
Progressive Scan to
Pre-Encoder
Horizontal
Scaler
3-Line Moving Window
Buffer
Interlace Scan
Converter
TV DACs
TV Encoder
TV
Timing Generator
Encoder
Figure 6-13. TVOUT Block Diagram
Table 6-4. Flicker Filter Operation
Mixer/Blender Block
½ Y Flicker Filter - Graphics Pixel
Flicker Filter ½, 1, ½ Coefficients
Graphics Pixel Video Pixel
Graphics Y(n-1) * ½
Graphics Y(n) * ½
Graphics Y(n+1) * ½
=
=
=
½ GY(n-1)
½ GY(n)
½ GY(n+1)
½ GY * ½
½ GY * 1
½ GY * ½
=
=
=
¼ GY(n-1)
½ GY(n)
¼ GY(n+1)
Video Y (m-1)
Null * ½
Video Y (m) * 1 = VY(m)
=
0
Null * ½
=
0
Video Y (m+1)
----------------
1 GY pixel
--------------
1 VY pixel
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Video Processor Module (Continued)
Flicker Filter, Progressive Video and
6.2.4.5 TV Encoder
YUV or RGB Mixing/Blending
This block creates the TV signals. Both NTSC and PAL
encodings are supported. F4FAR0+Memory Offset C00h-
C14h program the TV encoder.
If RGB mixing/blending is enabled, then the flicker filter’s ½,
1, ½ coefficients in the Mixer/Blender block can not be
used. If progressive video is mixed/blended the ½, 1, ½
coefficients can not be used because the video will be dis-
torted. Therefore the ¼, ½, ¼ coefficients must be used.
This setting of the flicker filter effects both the video and the
graphics data. This setting is not a recommended setting
but it is the only choice, other than disabling the flicker filter,
if simultaneous TV and CRT/TFT output is desired.
Closed captioning information can be output to the TV
under direct program control. F4FAR0+Memory Offset
818h-828h stores, controls, and positions the closed cap-
tioning information.
6.2.5 VESA DDSC2B and DPMS Support
The Video Processor supports VESA, DDSC2B, and
DPMS standards for enhanced monitor communications
and power management support. This support is provided
via signals DDC_SCL (muxed with IDE_DATA10) and
DDC_SDA (muxed with IDE_DATA9). F4BAR0+Memory
Offset 04h[24, 23, 22] controls the interface.
Flicker Filter, Interlaced Video and
RGB Mixing/Blending
Flicker filter should not be enabled. Neither flicker filter
choice results in an acceptable image.
Scan Rate Conversion
6.2.6 Integrated DACs
After the flicker filter, the image is scan rate converted from
progressive to interlace. This is the scan protocol needed
for TV. The image also crosses a clock domain. Up to this
point the image has been in the GX1 module’s graphics
clock domain. With the line buffer it moves into the TVOUT
block’s timing generator clock domain.
The Video Processor uses a Digital to Analog Converter
(DAC) for CRT and TV.
To interface directly with the CRT display, the Video Pro-
cessor incorporates triple 8-bit video DACs. The integrated
DACs drive the RED, GREEN and BLUE inputs of the CRT.
Each integrated DAC is an 8-bit current output type which
can run at a clock rate of up to 135 MHz. The integrated
DAC can generate voltage levels from 0 to 1.0V, when driv-
ing 75 Ω double-terminated loads.
6.2.4.2 Pre-Encoder Horizontal Scaler
The image can now be upscaled or downscaled horizon-
tally.
F4FAR0+Memory
Offset
810h[30:24]
and
F4FAR0+Memory Offset 814h[10] controls the pre-encoder
horizontal scaler.
Differential and integral linearity errors, over full tempera-
ture and voltage ranges, are less than one LSB.
6.2.4.3 Video Output Port (VOP)
The peak white voltage (VFR - full range output voltage),
generated at the DAC, is defined according to the following
formula:
The image is VESA Video Interface Port Rev. 1.1 Task B
encoded and sent to the VOP interface. The encoded data
only contains active video. It does not contain an ancillary
data block, sliced VBI data, or audio data. The VOP inter-
face is enabled through the pin multiplexing registers of the
General Configuration Block (see Section 3.2 "Multiplexing,
Interrupt Selection, and Base Address Registers" on page
86).
VFR = 3.35(VREF / RSET)*75
where:
VREF is the voltage at VREF (either internal bandgap refer-
ence, or externally connected voltage reference).
RSET is the value of resistance between SETRES and
AVSS (typically 470 Ω).
6.2.4.4 TV Encoder Timing Generator
The timing generator generates all the necessary clocks to
properly drive an NTSC TV or PAL TV and the Video Out-
put Port.
DAC
CRT
Monitor
RL
RL
AVSS
Figure 6-14. DAC Voltage Levels
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Video Processor Module (Continued)
• The TV interface consists of a set of four DACs.
— Normally, two DACs drive the composite TV output,
and two other DACs drive S-Video TV output.
— In SCART mode, three DACS drive TVR, TVG, and
TVB signals, and the fourth DAC drives the
composite signal.
TFT output signals are:
• TFTD[5:0] for blue signals
• TFTD[11:6] for green signals
• TFTD[17:12] for red signals
• HSYNC and VSYNC - sync signals
• TFTDCK - data clock signal.
• TFTDE - data enable signal.
• FP_VDD_ON - power control signal
Each TV DAC has a resolution of 10-bits, and is capable of
running at a clock rate of up to 30 MHz. These DACs can
generate voltage levels from 0 to 1.3V, when driving 75Ω
double terminated loads.
6.2.7 TFT Interface
The TFT interface can be programmed to one of two sets of
balls: IDE balls or Parallel Port balls. PMR[23] of the Gen-
eral Configuration registers program where the TFT inter-
face exists (see Table 3-2 on page 86).
Power Sequence
Power sequence is used to control assertion of
FP_VDD_ON and TFTD signals.
All bits related to power sequence configuration are located
in the Display Configuration register (F4BAR0+Memory
Offset 04h).
Note: If the TFT interface is on the IDE balls, the maxi-
mum FPCLK supported is 40 MHz. If the TFT inter-
face is on the Parallel Port balls the maximum
FPCLK supported is 80 MHz.
After enabling CRT_EN (bit 0), and FP_PWR_EN (bit 6),
the state machine waits until the next VSYNC to switch on
the FP_VDD_ON signal. The state machine then asserts
the TFTD[17:0] signals after the delay programmed via
PWR_SEQ_DLY (bits [19:17]) When FP_PWR_EN (bit 6)
is set to 0, the reverse sequence happens for powering
down the TFT.
Support for a TFT panel requires power sequencing and an
18-bit (6-bit RGB), digital output. The relevant digital output
signals are available from the SC1200/SC1201.
T0 is time to next VSYNC
T1 is a programmable multiple of frame time
FP_PWR_EN
bit
T0
FP_VDD_ON
T1
T1
TFTD[17:0],
HSYNC, VSYNC,
TFTDE, TFTDCK
T0+T1
Figure 6-15. TFT Power Sequence
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Video Processor Module (Continued)
6.2.8 Integrated PLL
The integrated PLL can generate any frequency by writing
into the CRT-m and CRT-n bit fields (FBAR0+Memory Off-
set 2Ch). Additionally, 16 preprogrammed VGA frequencies
can be selected via the PLL Clock Select register
(F4BAR0+Memory Offset 2Ch[19:16]), if the crystal oscilla-
tor has a frequency of 27 MHz. This PLL can be powered
down via the Miscellaneous register (F4BAR0+Memory
Offset 28h[12]).
The integrated (CRT) PLL can generate frequencies up to
135 MHz from a single 27 MHz source. The clock fre-
quency is programmable using two registers. Figure 6-16
shows the block diagram of the Video Processor integrated
PLL.
FREF is 27 MHz, generated by an external crystal and an
integrated oscillator. FOUT is calculated from:
FOUT = (m + 1) / (n+ 1) x FREF
Out
Divide
Phase
Compare
n
Charge
Pump
Loop
Filter
FREF
VCO
FOUT
Divider
m
Divider
Figure 6-16. PLL Block Diagram
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Video Processor Module (Continued)
6.3 REGISTER DESCRIPTIONS
The register space for accessing and configuring the Video
Processor is located in the Core Logic Chipset Register
Space (F0-F5). The Chipset Register Space is accessed
via the PCI interface using the PCI Type One Configuration
Mechanism (see Section 5.3.1 "PCI Configuration Space
and Access Methods" on page 189).
6.3.1 Register Summary
The tables in this subsection summarize the registers of
the Video Processor. Included in the tables are the regis-
ter’s reset values and page references where the bit for-
mats are found.
Table 6-5. F4: PCI Header Registers for Video Processor Support Summary
Width
(Bits)
Reset
Value
Reference
(Table 6-8)
F4 Index
Type
Name
00h-01h
02h-03h
04h-05h
06h-07h
08h
16
16
16
16
8
RO
RO
R/W
RO
RO
RO
RO
RO
RO
RO
R/W
Vendor Identification Register
Device Identification Register
PCI Command Register
PCI Status Register
100Bh
0504h
0000h
0280h
01h
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Device Revision ID Register
PCI Class Code Register
PCI Cache Line Size Register
PCI Latency Timer Register
PCI Header Type Register
PCI BIST Register
09h-0Bh
0Ch
24
8
030000h
00h
0Dh
8
00h
0Eh
8
00h
0Fh
8
00h
10h-13h
32
Base Address Register 0 (F4BAR0). Sets the base address for the
memory-mapped Video Configuration Registers within the Video
Processor. Refer to Table 6-9 on page 346 for programming infor-
mation regarding the register offsets accessed through this regis-
ter.
00000000h
14h-17h
18h-1Bh
32
32
R/W
R/W
Base Address Register 1 (F4BAR1). Reserved.
00000000h
00000000h
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Base Address Register 2 (F4BAR2). Sets the base address for the
memory-mapped VIP (Video Interface Port) Registers (summa-
rized in Table 6-10 on page 366).
1Ch-2Bh
2Ch-2Dh
2Eh-2Fh
30h-3Bh
3Ch
--
16
16
--
--
RO
RO
--
Reserved
00h
100Bh
0504h
00h
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Subsystem Vendor ID
Subsystem ID
Reserved
8
R/W
R/W
---
Interrupt Line Register
Interrupt Pin Register
Reserved
00h
3Dh
8
03h
3Eh-FFh
---
00h
Table 6-6. F4BAR0: Video Processor Configuration Registers Summary
F4BAR0+
Memory
Offset
Width
(Bits)
Reset
Value
Reference
(Table 6-9)
Type
Name
00h-03h
04h-07h
08h-0Bh
0Ch-0Fh
10h-13h
14h-17h
18h-1Bh
1Ch-1Fh
20h-23h
24h-27h
32
32
32
32
32
32
32
32
32
32
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
Video Configuration Register
Display Configuration Register
Video X Position Register
Video Y Position Register
Video Upscaler Register
Video Color Key Register
Video Color Mask Register
Palette Address Register
Palette Data Register
00000000h
x0000000h
00000000h
00000000h
00000000h
00000000h
00000000h
xxxxxxxxh
xxxxxxxxh
---
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Reserved
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Video Processor Module (Continued)
Table 6-6. F4BAR0: Video Processor Configuration Registers Summary (Continued)
F4BAR0+
Memory
Offset
Width
(Bits)
Reset
Value
Reference
(Table 6-9)
Type
Name
28h-2Bh
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
R/W
R/W
---
Miscellaneous Register
00001400h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
xxxxx100h
0000015xh
00060000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
001B0017h
00000000h
---
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2Ch-2Fh
30h-33h
PLL2 Clock Select Register
Reserved
34h-37h
RO
Reserved
38h-3Bh
3Ch-3Fh
40h-43h
RO
Reserved
R/W
R/W
R/W
RO
Video Downscaler Control Register
Video Downscaler Coefficient Register
CRC Signature Register
44h-47h
48h-4Bh
4Ch-4Fh
50h-53h
Device and Revision Identification
Video De-Interlacing and Alpha Control Register
Cursor Color Key Register
Cursor Color Mask Register
Cursor Color Register 1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
54h-57h
58h-5Bh
5Ch-5Fh
60h-63h
Cursor Color Register 2
Alpha Window 1 X Position Register
Alpha Window 1 Y Position Register
Alpha Window 1 Color Register
Alpha Window 1 Control Register
Alpha Window 2 X Position Register
Alpha Window 2 Y Position Register
Alpha Window 2 Color Register
Alpha Window 2 Control Register
Alpha Window 3 X Position Register
Alpha Window 3 Y Position Register
Alpha Window 3 Color Register
Alpha Window 3 Control Register
Video Request Register
64h-67h
68h-6Bh
6Ch-6Fh
70h-73h
74h-77h
78h-7Bh
7Ch-7Fh
80h-83h
84h-87h
88h-8Bh
8Ch-8Fh
90h-93h
94h-97h
Alpha Watch Register
98h-3FFh
400h-403h
404h-407h
408h-40Bh
40Ch-40Fh
410h-413h
414h-417h
418h-41B
41Ch-41F
420h-423h
424h-427h
428h-43Bh
43Ch-43Fh
---
Reserved
32
32
32
32
32
32
32
32
32
32
---
32
R/W
---
Video Processor Display Mode Register
Reserved
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
---
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
---
Video Processor Test Mode Register
VBI Line Enable Register - Odd
VBI Line Enable Register - Even
VBI Horizontal Control Register
VBI Total Count Register - Odd
VBI Total Count Register - Even
GenLock Register
GenLock Delay Register
Reserved
R/W
Continuous GenLock Time-out Register
1FFF1FFFh
TVOUT Configuration Registers
800h-803h
804h-807h
808h-80Bh
80Ch-80Fh
810h-813h
32
32
32
32
32
R/W
R/W
R/W
R/W
R/W
Horizontal Timing Register
00000000h
00000000h
00000000h
00000000h
00000000h
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Horizontal Sync Timing Register
Vertical Sync Timing Register
Display Line End Register
Horizontal Pre Encoder Scale Register
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Video Processor Module (Continued)
Table 6-6. F4BAR0: Video Processor Configuration Registers Summary (Continued)
F4BAR0+
Memory
Offset
Width
(Bits)
Reset
Value
Reference
(Table 6-9)
Type
Name
814h-817h
818h-81Bh
81Ch-81Fh
32
32
32
R/W
R/W
---
Horizontal Scaling Control Register
TVOUT Debug Register
Reserved
00000000h
00000440h
---
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Encoder Registers
C00h-C03h
C04h-C07h
C08h-C0Bh
C0Ch-C0Fh
C10h-C13h
C14h-C17h
C18h-C1Bh
C1Ch-C1Fh
C20h-C23h
C24h-C27h
C28h-C2Bh
C2Ch-C2Fh
C50h-C53h
32
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Timing and Encoder Control 1 Register
Timing and Encoder Control 2 Register
Timing and Encoder Control 3 Register
Subcarrier Frequency Register
Display Position Register
00000000h
1FF00000h
00000000h
21F07C1Fh
00120071h
00EF02CFh
00000000h
00000000h
00000000h
00000000h
00000000h
00000020h
00000004h
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32
32
32
32
32
32
32
32
32
32
32
32
Display Size Register
Closed Captioning Data Register
Extended Data Services Data Register
CGMS Data Register
WSS Data Register
Closed Captioning Control Register
DAC Control Register
VBI Scaler Register
Table 6-7. F4BAR2: VIP Support Registers Summary
F4BAR2+
Memory
Offset
Width
(Bits)
Reset
Value
Reference
(Table 6-10)
Type
Name
00h-03h
04h-07h
08h-0Bh
0Ch-0Fh
10h-13h
14h-17h
18h-1Bh
1Ch-1Fh
20h-23h
24h-27h
28h-2Bh
2Ch-3Fh
40h-43h
44h-47h
48h-4Bh
4Ch-1FFh
32
32
32
--
R/W
R/W
R/W
--
Video Interface Port Configuration Register
Video Interface Control Register
Video Interface Status Register
Reserved
00000000h
00000000h
xxxxxxxxh
00000000h
xxxxxxxxh
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
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32
32
32
32
32
32
32
--
RO
Video Current Line Register
Video Line Target Register
Odd Field VBI Line Enable Register
Even Field VBI Line Enable Register
Video Data Odd Base Register
Video Data Even Base Register
Video Data Pitch Register
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
--
32
32
32
--
R/W
R/W
R/W
--
VBI Data Odd Base Register
VBI Data Even Base Register
VBI Data Pitch Register
Reserved
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Video Processor Module (Continued)
6.3.2 Video Processor Registers - Function 4
The register space designated as Function 4 (F4) is used
to configure the PCI portion of support hardware for
accessing the Video Processor support registers, including
VIP (separate BAR). The bit formats for the PCI Header
registers are given in Table 6-8.
Located in the PCI Header Registers of F4 are three Base
Address Registers (F4BARx) used for pointing to the regis-
ter spaces designated for Video Processor support.
F4BAR0 is for Video Processor Configuration, F4BAR1 is
reserved, and F4BAR2 is for VIP configuration.
Table 6-8. F4: PCI Header Registers for Video Processor Support Registers
Bit
Description
Index 00h-01h
Index 02h-03h
Index 04h-05h
Vendor Identification Register (RO)
Device Identification Register (RO)
PCI Command Register (R/W)
Reset Value: 100Bh
Reset Value: 0504h
Reset Value: 0000h
15:2
1
Reserved. (Read Only)
Memory Space. Allow the Core Logic module to respond to memory cycles from the PCI bus.
0: Disable.
1: Enable.
This bit must be enabled to access memory offsets through F4BAR0, F4BAR1, and F4BAR2 (see F4 Index 10h, 14h, and
18h).
0
Reserved. (Read Only)
Index 06h-07h
Index 08h
PCI Status Register (RO)
Device Revision ID Register (RO)
PCI Class Code Register (RO)
PCI Cache Line Size Register (RO)
PCI Latency Timer Register (RO)
PCI Header Type (RO)
Reset Value: 0280h
Reset Value: 01h
Index 09h-0Bh
Index 0Ch
Reset Value: 030000h
Reset Value: 00h
Index 0Dh
Reset Value: 00h
Index 0Eh
Reset Value: 00h
Index 0Fh
PCI BIST Register (RO)
Reset Value: 00h
Index 10h-13h
Base Address Register 0 - F4BAR0 (R/W)
Reset Value: 00000000h
Video Processor Video Memory Address Space. This register allows PCI access to the memory mapped Video Processor configura-
tion registers. Bits [11:0] are read only (0000 0000 0000) indicating a 4 KB memory address range. See Table 6-9 on page 346 for bit for-
mats and reset values of the registers accessed through this base address register.
31:12
11:0
Video Processor Video Memory Base Address.
Address Range. (Read Only)
Index 14h-17h
Reserved.
Base Address Register 1 - F4BAR1 (R/W)
Reset Value: 00000000h
Reset Value: 00000000h
Index 18h-1Bh
Base Address Register 2 - F4BAR2 (R/W)
VIP Address Space. This register allows access to memory mapped VIP (Video Interface Port) related registers. Bits [11:0] are read
only (0000 0000 0000), indicating a 4 KB I/O address range. Refer to Table 6-10 for the VIP register bit formats and reset values.
31:12
11:0
VIP Base Address.
Address Range. (Read Only)
Index 1Ch-2Bh
Index 2Ch-2Dh
Index 2Eh-2Fh
Index 30h-3Bh
Index 3Ch
Reserved
Subsystem Vendor ID (RO)
Subsystem ID (RO)
Reserved
Reset Value: 00h
Reset Value: 100Bh
Reset Value: 0504h
Reset Value: 00h
Reset Value: 00h
Interrupt Line Register (R/W)
This register identifies the system interrupt controllers to which the device’s interrupt pin is connected. The value of this register is used
by device drivers and has no direct meaning to this function.
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Video Processor Module (Continued)
Table 6-8. F4: PCI Header Registers for Video Processor Support Registers (Continued)
Bit
Description
Index 3Dh
Interrupt Pin Register (R/W)
Reset Value: 03h
This register selects which interrupt pin the device uses. VIP uses INTC# after reset. INTA#, INTB# or INTD# can be selected by writing
1, 2 or 4, respectively.
Index 3Eh-FFh
Reserved
Reset Value: 00h
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Video Processor Module (Continued)
6.3.2.1 Video Processor Support Registers - F4BAR0
F4 Index 10h, Base Address Register 0 (F4BAR0) sets the
base address that allows PCI access to the Video Proces-
sor support registers, not including VIP. A separate base
address register (F4BAR2) is used to access VIP support
registers (see Section 6.3.2.2 on page 366).
Note: Reserved bits that are not defined as "must be set
to 0 or 1" should be written with a value that is read
from them.
Table 6-9. F4BAR0+Memory Offset: Video Processor Configuration Registers
Bit
Description
Offset 00h-03h
Video Configuration Register (R/W)
Reset Value: 00000000h
Configuration register for options of the motion video acceleration hardware.
31:29
28
Reserved. Must be set to 0.
EN_42X (Enable 4:2:x Format). Allows format selection.
0: 4:2:2 format.
1: 4:2:0 format.
Note: When input video stream is RGB (i.e., F4BAR0+Memory Offset 4Ch[13] = 1), this bit must be set to 0.
27
BIT_8_LINE_SIZE. When enabled, this bit increases line size from VID_LIN_SIZ (bits [15:8]) DWORDs by adding 256
DWORDs.
0: Disable.
1: Enable.
26:25
24:16
Reserved. Must be set to 0.
INIT_RD_ADDR (Initial Buffer Read Address). This field preloads the starting read address for the line buffers at the
beginning of each display line. It is used for hardware clipping of the video window at the left edge of the active display. It
represents the DWORD address of the source pixel which is to be displayed first.
For an unclipped window, this value should be 0. For 4:2:0 format, set bits [17:16] to 00.
15:8
7
VID_LIN_SIZ (Video Line Size). Represents the number of DWORDs that make up the horizontal size of the source video
data.
YFILT_EN (Y Filter Enable). Enables/disables the vertical filter.
0: Disable. Upscaling done by repeating pixels.
1: Enable. Upscaling done by interpolating pixels.
Note: This bit is used with Y upscaling logic. Reset to 0 when not required.
XFILT_EN (X Filter Enable). Enables/disables the horizontal filter.
0: Disable. Upscaling done by repeating pixels.
6
1: Enable. Upscaling done by interpolating pixels.
Note: This bit is used with X upscaling logic. Reset to 0 when not required.
Reserved.
5:4
3:2
VID_FMT (Video Format). Byte ordering of video data on the Video Input bus (VPD[7:0]). The interpretation of these bits
depends on the settings of bit 13 (GV_SEL) in the Video De-Interlacing and Alpha Control register (F4BAR0+Memory Offset
4Ch) and bit 28 (EN_42X) of this register.
If GV_SEL = 0 and EN_42X = 0:
00: Cb Y0 Cr Y1
01: Y1 Cr Y0 Cb
10: Y0 Cb Y1 Cr
11: Y0 Cr Y1 Cb
If GV_SEL = 0 and EN_42X = 1:
00: Y0 Y1 Y2 Y3
01: Y3 Y2 Y1 Y0
10: Y1 Y0 Y3 Y2
11: Y1 Y2 Y3 Y0
If GV_SEL = 1 and EN_42X = 0:
00: P1L P1M P2L P2M
01: P2M P2L P1M P1L
10: P1M P1L P2M P2L
11: P1M P2L P2M P1L
If GV_SEL = 1 and EN_42X = 1: Reserved
Note: Both RGB 5:6:5 and YUV 4:2:2 contain two pixels in each 32-bit DWORD. YUV 4:2:0 contains a stream of Y data
for each line, followed by U and V data for that same line.
1
Reserved.
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Video Processor Module (Continued)
Table 6-9. F4BAR0+Memory Offset: Video Processor Configuration Registers (Continued)
Bit
Description
0
VID_EN (Video Enable). Enables video acceleration hardware.
0: Disable (reset) video module.
1: Enable.
Offset 04h-07h
Display Configuration Register (R/W)
Reset Value: x0000000h
General configuration register for display control. This register is also used to determine how graphics and video data are to be com-
bined in the display on the output device.
31
DDC_SDA_IN (DDC Input Data). (Read Only) Returns the value from the DDC_SDA signal (muxed with IDE_DATA9) con-
nected to pin 12 of the VGA connector.
30:28
27
Reserved.
FP_ON_STATUS (Flat Panel On Status). (Read Only) Shows whether power to the attached flat panel is on or off. This bit
transitions at the end of the power-up or power-down sequence.
0: Power to the flat panel is off.
1: Power to the flat panel is on.
26
DAC_VREF (CRT DAC Voltage Reference). When set to 1, this bit enables use of an external voltage reference for CRT
DAC.
0: Disable external VREF. Enable Internal VREF.
1: Use external VREF. Connect an external voltage reference to the VREF signal.
Reserved. Must be set to 0.
25
24
DDC_OE (DDC Output Enable). Selects the direction of signal DDC_SDA (muxed with IDE_DATA9). This bit indicates the
direction of DDC data flow between the Video Processor and a CRT.
0: Input.
1: Output. DDC data is sent from the Video Processor to the CRT.
DDC_SDA_OUT (DDC Output Data). DDC data bit for output.
23
22
DDC_SCL (DDC Serial Clock). Provides the serial clock for the interface using the DDC_SCL signal (muxed with
IDE_DATA10).
21
GV_GAMMA_SEL (Graphics or Video Gamma Source Data). Selects whether the graphics or video data goes to the
Gamma Correction RAM. GAMMA_EN (F4BAR0+Memory Offset 28h[0]) must be enabled for the selected data source to
pass through the Gamma Correction RAM.
0: Graphics data to Gamma Correction RAM.
1: Video data to Gamma Correction RAM.
Note: Gamma Correction is always in the RGB domain for graphics data.
Gamma Correction can be in the YUV or RGB domain for video data.
20
COLOR_CHROMA_SEL (Color or Chroma Key Select). Selects whether the graphics is used for color keying or the video
data stream is used for chroma keying.
0: Graphics data is compared to the color key.
1: Video data is compared to the chroma key.
19:17
16:14
PWR_SEQ_DLY (Power Sequence Delay). Selects the number of frame periods that transpire between successive transi-
tions of the power sequence control lines.
CRT_SYNC_SKW (CRT Sync Skew). Represents the number of pixel clocks to skew the horizontal and vertical sync that
are sent to the CRT. This field should be programmed to 100 at the baseline. Via this register, the sync can be moved for-
ward (later) or backward (earlier) relative to the pixel data. This register can be used to compensate for possible delay of
pixel data being processed via the Video Processor.
000: Sync moved 4 clocks backward
001: Sync moved 3 clocks backward
010: Sync moved 2 clocks backward
011: Sync moved 1 clock backward
Reserved.
100: Baseline, sync not moved
101: Sync moved 1 clock forward
110: Sync moved 2 clocks forward
111: Sync moved 3 clocks forward
13:10
9
CRT_VSYNC_POL (CRT Vertical Synchronization Polarity). Selects CRT vertical sync polarity.
0: CRT vertical sync is normally low, and is set high during the sync interval.
1: CRT vertical sync is normally high, and is set low during the sync interval.
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Table 6-9. F4BAR0+Memory Offset: Video Processor Configuration Registers (Continued)
Bit
Description
8
CRT_HSYNC_POL (CRT Horizontal Synchronization Polarity). Selects CRT horizontal sync polarity.
0: CRT horizontal sync is normally low, and is set high during sync interval.
1: CRT horizontal sync is normally high, and is set low during sync interval.
7
6
FP_DATA_EN (Flat Panel Output Enable). Controls the data, data-enable, clock and sync output signals.
0: Flat panel data outputs are forced to zero depending on the value of bit 3 (DAC_BL_EN). Bit 6 (FP_PWR_EN) is
ignored.
1: Flat panel outputs are forced to zero until power-up, and later, data outputs are subject to the value of bit 3
(DAC_BL_EN).
FP_PWR_EN (Flat Panel Power Enable). Changing this bit initiates a flat panel power-up or power-down.
0-to-1: Power-up flat panel.
1-to-0: Power-down flat panel.
5:4
3
Reserved.
DAC_BL_EN (DAC Blank Enable). Controls blanking of the CRT DACs.
0: DACs are constantly blanked.
1: DACs are blanked normally (i.e., during horizontal and vertical blank).
2
1
0
VSYNC_EN (Vertical Sync Enable). Enables/disables display vertical sync (used for VESA DPMS support).
0: Disable.
1: Enable.
HSYNC_EN (Horizontal Sync Enable). Enables/disables display horizontal sync (used for VESA DPMS support).
0: Disable.
1: Enable.
CRT_EN (CRT Enable). Enables the CRT control logic. This bit is also used to reset the CRT control logic.
0: Reset CRT control logic.
1: Enable CRT control logic.
Offset 08h-0Bh
Video X Position Register (R/W)
Reset Value: 00000000h
Provides the window X position. This register is programmed relative to CRT horizontal sync input (not physical screen position).
Note: H_TOTAL and H_SYNC_END are values programmed in the GX1 module’s Display Controller Timing registers
(GX_BASE+Memory Offset 8330h[26:19] and 8338h[10:3], respectively). The value of (H_TOTAL – H_SYNC_END) is some-
times referred to as "horizontal back porch". For more information, see the GX1 Processor Series Datasheet.
31:28
27:16
Reserved.
VID_X_END (Video X End Position). Represents the horizontal end position of the video window (not inclusive). This value
is calculated according to the following formula:
Value = Desired screen position + (H_TOTAL – H_SYNC_END) – 13.
15:12
11:0
Reserved.
VID_X_START (Video X Start Position). Represents the horizontal start position of the video window. This value is calcu-
lated according to the following formula:
Value = Desired screen position + (H_TOTAL – H_SYNC_END) – 14.
Offset 0Ch-0Fh
Video Y Position Register (R/W)
Reset Value: 00000000h
Provides the window Y position. This register is programmed relative to CRT vertical sync input (not physical screen position).
Note: V_TOTAL and V_SYNC_END are values programmed in the GX1 module’s Display Controller Timing registers
(GX_BASE+Memory Offset 8340h[26:16] and 8348h[26:16], respectively). The value of (V_TOTAL – V_SYNC_END) is some-
times referred to as "vertical back porch". For more information, see the GX1 Processor Series Datasheet.
31:27
26:16
Reserved.
VID_Y_END (Video Y End Position). Represents the vertical end position of the video window (not inclusive). This value is
calculated according to the following formula:
Value = Desired screen position + (V_TOTAL – V_SYNC_END) + 2.
15:11
10:0
Reserved.
VID_Y_START (Video Y Start Position). Represents the vertical start position of the video window. This value is calculated
according to the following formula:
Value = Desired screen position + (V_TOTAL – V_SYNC_END) + 1.
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Table 6-9. F4BAR0+Memory Offset: Video Processor Configuration Registers (Continued)
Bit
Description
Offset 10h-13h
Video Upscale Register (R/W)
Reset Value: 00000000h
Provides horizontal and vertical upscale factors of the window.
31:30
29:16
Reserved.
VID_Y_SCL (Video Y Scale Factor). Represents the vertical upscale factor of the video window according to the following
formula:
VID_Y_SCL = 8192 * (Ys - 1) / (Yd - 1)
where:
Ys = Video source vertical size in pixels
Yd = Video destination vertical size in pixels
Note: Upscale factor must be used. Yd is equal or bigger than Ys. If no scaling is intended, set to 2000h. The actual scale
factor used is VID_Y_SCL/8192, but the formula above fits a given source number of lines into a destination win-
dow size.
Note: When progressive mixing/blending is programmed (F4BAR0+Memory Offset 4Ch[9] = 0) and the video data is
interlaced, this register should be programmed to 1000h to double the vertical lines,
15:14
13:0
Reserved.
VID_X_SCL (Video X Scale Factor). Represents horizontal upscale factor of the video window according to the following
formula:
VID_X_SCL = 8192 * (Xs - 1) / (Xd - 1)
where:
Xs = Video source horizontal size in pixels
Xd = Video destination vertical size in pixels
Note: Upscale factor must be used. Xd is equal or bigger than Xs. If no scaling is intended, set to 2000h. The actual scale
factor used is VID_X_SCL/8192, but the formula above fits a given source number of pixels into a destination win-
dow size.
Offset 14h-17h
Video Color Key Register (R/W)
Reset Value: 00000000h
Provides the video color key. The color key can be used to allow irregular shaped overlays of graphics onto video, or video onto graphics,
within a scaled video window.
31:24
23:0
Reserved.
VID_CLR_KEY (Video Color Key). The video color key is a 24-bit RGB or YUV value.
•
If the COLOR_CHROMA_SEL bit (F4BAR0+Memory Offset 04h[20]) = 0:
— The video pixel is selected within the target window if the corresponding graphics pixel matches the color key. The
color key in an RGB value.
•
If the COLOR_CHROMA_SEL bit (F4BAR0+Memory Offset 04h[20]) = 1:
— The video pixel is selected within the target window only if it (the video pixel) does not match the color key. The color
key is usually an RGB value. However, if both the CSC_for VIDEO and GV_SEL bits (F4BAR0+Memory Offset 4Ch
bits 10 and 13, respectively) are programmed to 0, the color key is a YUV value (i.e., video is not converted to RGB).
The graphics or video data being compared can be masked prior to the compare via the Video Color Mask register
(described in F4BAR0+Memory Offset 18h).
Offset 18h-1Bh
Video Color Mask Register (R/W)
Reset Value: 00000000h
Provides the video color mask. This value is used to mask bits of the graphics or video stream being compared to the video color key
(described in F4BAR0+Memory Offset 14h). It can be used to allow a range of values to serve as the color key.
31:24
23:0
Reserved.
VID_CLR_MASK (Video Color Mask). This mask is a 24-bit value. Zeros in the mask cause the corresponding bits in the
graphics or video stream to be ignored.
Offset 1Ch-1Fh
Palette (Gamma Correction RAM) Address Register (R/W)
Reset Value: xxxxxxxxh
31:8
7:0
Reserved.
PAL_ADDR (Palette Address). Specifies the address to be used for the next access to the Palette Data register
(F4BAR0+Memory Offset 20h[31:8]). Each access to the data register automatically increments the Palette Address regis-
ter. If non-sequential access is made to the palette, the address register must be loaded between each non-sequential data
block.
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Table 6-9. F4BAR0+Memory Offset: Video Processor Configuration Registers (Continued)
Bit
Description
Offset 20h-23h
Palette (Gamma Correction RAM) Data Register (R/W)
Reset Value: xxxxxxxxh
Provides the video palette data. The data can be read or written to the Gamma Correction RAM (palette) via this register. Prior to
accessing this register, an appropriate address should be loaded to the Palette Address register (F4BAR0+Memory Offset 1Ch[7:0]).
Subsequent accesses to the Palette Data register cause the internal address counter to be incremented for the next cycle.
31:8
PAL_DATA (Palette Data). Contains the read or write data for a Gamma Correction RAM (palette).
Note: When a read or write to the Gamma Correction RAM occurs, the previous output value is held for one additional DOT-
CLK period. This effect should go unnoticed during normal operation.
7:0
Reserved.
Offset 24h-27h
Offset 28h-2Bh
Reserved
Miscellaneous Register (R/W)
Reset Value: 00001400h
Configuration and control register for miscellaneous characteristics of the Video Processor.
31:13
12
Reserved.
PLL2_PWR_EN (PLL2 Power-Down Enable).
0: Power-down.
1: Normal.
11
10
A_PWR_DN (Analog Power-Down). Enables power-down of the PLL2 and the bandgap circuit that generates VREF.
0: Normal.
1: Power-down.
Note: If A_PWR_DN is set to 1 without also setting DAC_PWR_DN (bit 10) to 1, an unexpected increase in power con-
sumption may result.
DAC_PWR_DN (DAC Power-Down). Powers down the internal CRT DAC.
0: Normal.
1: Power-down.
Reserved.
9:1
0
GAMMA_EN (Gamma Correction RAM Enable). Allows video or graphics (selected by F4BAR0+Memory Offset 04h[21])
to go to the Gamma Correction RAM.
0: Enable.
1: Disable.
Offset 2Ch-2Fh
PLL2 Clock Select Register (R/W)
Reset Value: 00000000h
Determines the characteristics of the integrated PLL2.
31:23
22:21
Reserved. Must be set to 0.
CLK_DIV_SEL (Clock Divider Select).
00: No division
01: Divide by 2
10: Divide by 4
11: Divide by 8
Divides the clock generated by the PLL2, using the programmed m (bits [14:8]) and n (bits [3:0]) values.
SEL_REG_CAL. Selects specific or previously-calculated values.
20
0: Values previously calculated from the CLK_SEL bits (bits [19:16]).
1: Values according to the m (bits [14:8]), n (bits [3:0]), and CLK_DIV_SEL (bits [22:21]) fields.
CLK_SEL (Clock Select). Selects frequency (in MHz) of the display clock.
19:16
0000: 25.175
0001: 31.5
0010: 36
0100: 50
1000: 65
1001: 75
1010: 78.5
1011: 94.5
1100: 108
1101: 135
1110: 27
1111: 24.923052
0101: 49.5
0110: 56.25
0111: 44.9
0011: 40
15
LFTC (Loop Filter Time Constant). This bit should be set when m (bits [14:8]) value is higher than 30.
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Table 6-9. F4BAR0+Memory Offset: Video Processor Configuration Registers (Continued)
Bit
Description
14:8
m (Defines m PLL2 Value). Relevant when SEL_REG_CAL (bit 20) = 1. The following formula is used for calculating the
frequency using m and n values:
Fvco
Km
Kn
= OSCCLK * Km/Kn
= m + 1
= n + 1
OSCCLK = 27 MHz
7:4
3:0
Reserved.
n (Defines n PLL2 Value). Relevant when SEL_REG_CAL (bit 20) = 1. The following formula is used for calculating the fre-
quency using m and n values:
Fvco
Km
Kn
= OSCCLK * Km/Kn
= m + 1
= n + 1
OSCCL = 27 MHz
Offset 30h-33h
Offset 34h-37h
Offset 38h-3Bh
Offset 3Ch-3Fh
Reserved
Reserved
Reset Value: 00000000h
Reset Value: 00000000h
Reset Value: 00000000h
Reset Value: 00000000h
Reserved
Video Downscaler Control Register (R/W)
Controls the characteristics of the integrated video downscaler.
31:7
6
Reserved.
DTS (Downscale Type Select).
0: Type A (Downscale formula is 1/m+1, m pixels are dropped, 1 pixel is kept).
1: Type B (Downscale formula is m/m+1, m pixels are kept, 1 pixel is dropped).
Reserved.
5
4:1
DFS (Downscale Factor Select). Determines the downscale factor to be programmed into these bits, where m is used to
derive the desired downscale factor depending on bit 6 (DTS).
0
DCF (Downscaler and Filtering). Enables/disables downscaler and filtering logic.
0: Disable.
1: Enable.
Note: No downscaling support for RGB 5:6:5 and YUV 4:2:0 video formats.
Offset 40h-43h
Video Downscaler Coefficient Register (R/W)
Reset Value: 00000000h
Indicates filter coefficients. The filters can be programmed independently to increase video quality when the downscaler is implemented.
Valid values for each filter coefficient are 0-15. The sum of coefficients must be 16. FLT_CO_4 is used with the earliest pixels and
FLT_CO_1 is used with the latest. Only luminance values of pixels are filtered.
31:28
27:24
23:20
19:16
15:12
11:8
Reserved.
FLT_CO_4 (Filter Coefficient 4). For the tap-4 filter.
Reserved.
FLT_CO_3 (Filter Coefficient 3). For the tap-3 filter.
Reserved.
FLT_CO_2 (Filter Coefficient 2). For the tap-2 filter.
Reserved.
7:4
3:0
FLT_CO_1 (Filter Coefficient 1). For the tap-1 filter.
Offset 44h-47h
CRC Signature Register (R/W)
Reset Value: xxxxx100h
Signature values stored in this register can be read by the host. This register is used for test purposes.
31:8
7:3
SIG_VALUE (Signature Value). (Read Only) A 24-bit signature value is stored in this bit field and can be read at any time.
The signature is produced from the RGB data output of the mixer. This bit field is used for test purpose only.
See SIGN_EN (bit 0) description for more information.
Reserved.
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Table 6-9. F4BAR0+Memory Offset: Video Processor Configuration Registers (Continued)
Bit
Description
2
SIGN_FREE (Signature Free Run).
0: Disable. (Default) If this bit was previously set to 1, the signature process stops at the end of the current frame (i.e., at
the next falling edge of VSYNC).
1: Enable. If SIGN_EN (bit 0) = 1, the signature register captures data continuously across multiple frames.
1
0
Reserved.
SIGN_EN (Signature Enable).
0: Disable. (Default) The SIG_VALUE (bits [31:8]) is reset to 000001h and held (no capture).
1: Enable. The next falling edge of VSYNC is counted as the start of the frame to be used for CRC checking with each pixel
clock beginning with the next VSYNC.
If SIGN_FREE (bit 2) = 1, the signature register captures the pixel data signature continuously across multiple frames.
If SIGN_FREE (bit 2) = 0, a signature is captured for one frame at a time, starting from the next falling VSYNC.
After a signature capture, the SIG_VALUE can be read to determine the CRC check status. SIGN_EN can then be reset to
initialize the SIG_VALUE as an essential preparation for the next round of CRC check.
Offset 48h-4Bh
Device and Revision Identification (RO)
Reset Value: 0000xxxxh
31:16
15:8
7:0
Reserved.
REV_ID (Revision ID). See device errata for value.
DEV_ID (Device ID). See device errata for value.
Video De-Interlacing and Alpha Control Register (R/W)
Offset 4Ch-4Fh
Reset Value: 00060000h
31:22
21:20
Reserved.
ALPHA3_WIN_PRIORITY (Alpha Window 3 Priority). Determines the priority of Alpha Window 3. A higher number indi-
cates a higher priority. Priority is used to determine display order for overlapping alpha windows.
00: Lowest priority. (Default)
01: Medium priority.
10: Highest priority.
11: Illegal.
Note: Priority of enabled alpha windows must be different.
19:18
ALPHA2_WIN_PRIORITY (Alpha Window 2 Priority). Determines the priority of Alpha Window 2. A higher number indi-
cates a higher priority. Priority is used to determine display order for overlapping alpha windows.
00: Lowest priority. (Default)
01: Medium priority.
10: Highest priority.
11: Illegal.
Note: Priority of enabled alpha windows must be different.
17:16
ALPHA1_WIN_PRIORITY (Alpha Window 1 Priority). Determines the priority of Alpha Window 1. A higher number indi-
cates a higher priority. Priority is used to determine display order for overlapping alpha windows.
00: Lowest priority. (Default)
01: Medium priority.
10: Highest priority.
11: Illegal.
Note: Priority of enabled alpha windows must be different.
Reserved.
15:14
13
GV_SEL (GV Select). Selects input video format.
0: YUV format.
1: RGB format.
Note: Mixing and blending configurations are created using bits [13, 11:9] of this register. See Table 6-2 "Valid Mix-
ing/Blending Configurations" on page 332.
If this bit is set to 1, EN_42X (F4BAR0+Memory Offset 00h[28]) must be programmed to 0.
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Table 6-9. F4BAR0+Memory Offset: Video Processor Configuration Registers (Continued)
Bit
Description
12
VID_LIN_INV (Video Line Invert). When this bit is set, it allows the video window to be positioned at odd offsets with
respect to the first line. The values below are recommended if VID_Y_START (F4BAR0+Memory Offset 0Ch[10:0]) is an
odd (set to 1) or even (set to 0) number of lines from the start of the active display.
0: Even.
1: Odd.
11
10
9
CSC_FOR_GFX (RGB to YUV Color Space Converter). Determines if the input graphics stream or the mixed/blended
stream is passed through the RGB to YUV Color Space Converter (CSC).
0: The mixed/blended stream is passed through the CSC for TV support.
1: The graphics stream is passed through the CSC.
Note: Mixing and blending configurations are created using bits [13,11:9] of this register. See Table 6-2 "Valid Mix-
ing/Blending Configurations" on page 332.
CSC_FOR_VIDEO (Color Space Converter for Video). Determines whether or not the video stream from the video mod-
ule is passed through the CSC.
0: Disable. The video stream is sent "as is" to the video Mixer/Blender.
1: Enable. The video stream is passed through the CSC (for YUV to RGB conversion).
Note: Mixing and blending configurations are created using bits [13,11:9] of this register. See Table 6-2 "Valid Mix-
ing/Blending Configurations" on page 332.
VIDEO_BLEND_MODE (Video Blending Mode). Allows selection of the type of video (i.e., interlaced or progressive) used
for blending.
0: Progressive video used for blending.
1: Interlaced video used for blending.
Note: Mixing and blending configurations are created using bits [13,11:9] of this register. See Table 6-2 "Valid Mix-
ing/Blending Configurations" on page 332.
8
GFX_INS_VIDEO (Graphics Inside Video). This bit works in conjunction with bit COLOR_CHROMA_SEL (F4BAR0+Mem-
ory Offset 04h[20]). COLOR_CHROMA_SEL selects whether the graphics is used for color keying or the video data stream
is used for chroma keying. If COLOR_CHROMA_SEL = 0, graphics data is compared to the color key. If
COLOR_CHROMA_SEL = 1, video data is compared to the chroma key.
0: Outside the alpha windows, graphics or video is displayed depending on the result of the color key comparison.
1: Outside the alpha windows, only video is displayed (if COLOR_CHROMA_SEL = 0) or only graphics is displayed (if
COLOR_CHROMA_SEL = 1) color key comparison is not performed outside the alpha windows.
7
6
VID_WIN_PUSH_EN (Video Window Push Enable). Video window repositioning at an offset of 1 line below the pro-
grammed value. Facilitates line rate matching in both fields.
0: Disable. (Default)
1: Enable.
TOP_LINE_IN_ODD (Top Line in Odd Field). Allows selection of what field the top line is in.
0: Top line is in even field. (Default)
1: Top line is in odd field.
5
4
Reserved.
INSERT_EN (Insert Enable). When this bit is set, the odd frame is shifted with respect to the even frame.
0: No shifting occurs.
1: The odd frame is shifted according to the offset specified in bits [2:0].
3
Reserved.
2:0
OFFSET (Vertical Scaler Offset). For a non-interlaced video stream and when bob de-interlacing is used, program a value
of 100 (i.e., shift one line); otherwise, leave at 000.
Offset 50h-53h
Cursor Color Key Register (R/W)
Reset Value: 00000000h
31:29
28:24
Reserved.
COLOR_REG_OFFSET (Cursor Color Register Offset). This field indicates a bit in the incoming graphics stream. It is
used to indicate which of the two possible cursor color registers should be used for color key matches for the bits in the
graphics stream.
23:0
CUR_COLOR_KEY (Cursor Color Key). Specifies the 24-bit RGB value of the cursor color key. The incoming graphics
stream is compared with this value. If a match is detected, the pixel is replaced by a 24-bit value from one of the Cursor
Color registers.
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Video Processor Module (Continued)
Table 6-9. F4BAR0+Memory Offset: Video Processor Configuration Registers (Continued)
Bit
Description
Offset 54h-57h
Cursor Color Mask Register (R/W)
Reset Value: 00000000h
31:24
23:0
Reserved.
CUR_COLOR_MASK (Cursor Color Mask). This mask is a 24-bit value. Zeroes in the mask cause the corresponding bits
in the incoming graphics stream to be ignored.
Offset 58h-5Bh
Cursor Color Register 1 (R/W)
Reset Value: 00000000h
31:24
23:0
Reserved.
CUR_COLOR_REG1 (Cursor Color Register 1). Specifies a 24-bit cursor color value. This is an RGB value (for RGB
blending) or a YUV value (for YUV blending). In interlaced YUV blending mode, Y/2 value should be used.
This is one of two possible cursor color values. The COLOR_REG_OFFSET bits (F4BAR0+Memory Offset 50h[28:24])
determine a bit of the graphics data that if even, selects this color to be used.
Offset 5Ch-5Fh
Cursor Color Register 2 (R/W)
Reset Value: 00000000h
31:24
23:0
Reserved.
CUR_COLOR_REG2 (Cursor Color Register 2). Specifies a 24-bit cursor color value. This is an RGB value (for RGB
blending) or a YUV value (for YUV blending). In interlaced YUV blending mode, Y/2 value should be used.
This is one of two possible cursor color values. The COLOR_REG_OFFSET bits (F4BAR0+Memory Offset 50h[28:24])
determine a bit of the graphics data that if even, selects this color to be used.
Offset 60h-63h
Alpha Window 1 X Position Register (R/W)
Reset Value: 00000000h
Note: H_TOTAL and H_SYNC_END are values programmed in the GX1 module’s Display Controller Timing registers
(GX_BASE+Memory Offset 8330h[26:19] and 8338h[10:3], respectively). The value of (H_TOTAL – H_SYNC_END) is some-
times referred to as "horizontal back porch". For more information, see the GX1 Processor Series Datasheet.
Desired screen position should not be outside a video window (F4BAR0+Memory Offset 08h and 0Ch).
31:27
26:16
Reserved.
ALPHA1_X_END (Alpha Window 1 Horizontal End). Determines the horizontal end position of Alpha Window 1 (not inclu-
sive). This value is calculated according to the following formula:
Value = Desired screen position + (H_TOTAL – H_SYNC_END) – 1.
15:11
10:0
Reserved.
ALPHA1_X_START (Alpha Window 1 Horizontal Start). Determines the horizontal start position of Alpha Window 1. This
value is calculated according to the following formula:
Value = Desired screen position + (H_TOTAL – H_SYNC_END) – 2.
Offset 64h-67h
Alpha Window 1 Y Position Register (R/W)
Reset Value: 00000000h
Note: V_TOTAL and V_SYNC_END are values programmed in the GX1 module’s Display Controller Timing registers
(GX_BASE+Memory Offset 8340h[26:16] and 8348h[26:16], respectively). The value of (V_TOTAL – V_SYNC_END) is some-
times referred to as "vertical back porch". For more information, see the GX1 Processor Series Datasheet.
Desired screen position should not be outside a video window (F4BAR0+Memory Offset 08h and 0Ch).
31:27
26:16
Reserved.
ALPHA1_Y_END (Alpha Window 1 Vertical End). Determines the vertical end position of Alpha Window 1 (not inclusive).
This value is calculated according to the following formula:
Value = Desired screen position + (V_TOTAL – V_SYNC_END) + 2.
15:11
10:0
Reserved.
ALPHA1_Y_START (Alpha Window 1 Vertical Start). Determines the vertical start position of Alpha Window 1. This value
is calculated according to the following formula:
Value = Desired screen position + (V_TOTAL – V_SYNC_END) + 1.
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Video Processor Module (Continued)
Table 6-9. F4BAR0+Memory Offset: Video Processor Configuration Registers (Continued)
Bit
Description
Offset 68h-6Bh
Alpha Window 1 Color Register (R/W)
Reset Value: 00000000h
31:25
24
Reserved.
ALPHA1_COLOR_REG_EN (Alpha Window 1 Color Register Enable). Enable bit for the color key matching in Alpha
Window 1.
1: Enable. If this bit is enabled and the alpha window is enabled, then where there is a color key match. The color value (in
bits [23:0], ALPHA1_COLOR_REG) is displayed.
0: Disable. Where there is a color key match, no blending is performed.
23:0
ALPHA1_COLOR_REG (Alpha Window 1 Color Register). Specifies the color to be displayed inside Alpha Window 1
when there is a color key match in the alpha window. This is an RGB value (for RGB blending) or a YUV value (for YUV
blending). In interlaced YUV blending mode, Y/2 value should be used.
This color is only displayed if the alpha window is enabled and bit 24 (ALPHA1_COLOR_REG_EN) is enabled.
Offset 6Ch-6Fh
Alpha Window 1 Control Register (R/W)
Reset Value: 00000000h
31:18
17
Reserved.
LOAD_ALPHA (Load Alpha Value). (Write Only) When set to 1, this bit causes the Video Processor to load the alpha
value (in bits [7:0], ALPHA_VAL) at the start of the next frame.
16
ALPHA1_WIN_EN (Alpha Window 1 Enable). Enable bit for Alpha Window 1.
1: Enable Alpha Window 1.
0: Disable Alpha Window 1.
Note: Valid only if video window is enabled (F4BAR0+Memory Offset 00h[0] = 1).
15:8
7:0
ALPHA1_INC (Alpha Window 1 Increment). Specifies the alpha value increment/decrement. This is a signed 8-bit value
that is added to the alpha value for each frame. The MSB (bit 15) indicates the sign (i.e., increment or decrement). When
this value reaches either the maximum or the minimum alpha value (255 or 0) it keeps that value (i.e., it is not incre-
mented/decremented) until it is reloaded via bit 17 (LOAD_ALPHA).
ALPHA1_VAL (Alpha Window 1 Value). Specifies the alpha value to be used for this window.
Offset 70h-73h
Alpha Window 2 X Position Register (R/W)
Reset Value: 00000000h
Note: H_TOTAL and H_SYNC_END are values programmed in the GX1 module’s Display Controller Timing registers
(GX_BASE+Memory Offset 8330h[26:19] and 8338h[10:3], respectively). The value of (H_TOTAL – H_SYNC_END) is some-
times referred to as "horizontal back porch". For more information, see the GX1 Processor Series Datasheet.
Desired screen position should not be outside a video window (F4BAR0+Memory Offset 08h and 0Ch).
31:27
26:16
Reserved.
ALPHA2_X_END (Alpha Window 2 Horizontal End). Determines the horizontal end position of Alpha Window 2 (not inclu-
sive). This value is calculated according to the following formula:
Value = Desired screen position + (H_TOTAL – H_SYNC_END) – 1.
15:11
10:0
Reserved.
ALPHA2_X_START (Alpha Window 2 Horizontal Start). Determines the horizontal start position of Alpha Window 2. This
value is calculated according to the following formula:
Value = Desired screen position + (H_TOTAL – H_SYNC_END) – 2.
Offset 74h-77h
Alpha Window 2 Y Position Register (R/W)
Reset Value: 00000000h
Note: V_TOTAL and V_SYNC_END are values programmed in the GX1 module’s Display Controller Timing registers
(GX_BASE+Memory Offset 8340h[26:16] and 8348h[26:16], respectively). The value of (V_TOTAL – V_SYNC_END) is some-
times referred to as "vertical back porch". For more information, see the GX1 Processor Series Datasheet.
Desired screen position should not be outside a video window (F4BAR0+Memory Offset 08h and 0Ch).
31:27
26:16
Reserved.
ALPHA2_Y_END (Alpha Window 2 Vertical End). Determines the vertical end position of Alpha Window 2 (not inclusive).
This value is calculated according to the following formula:
Value = Desired screen position + (V_TOTAL – V_SYNC_END) + 2.
15:11
10:0
Reserved.
ALPHA2_Y_START (Alpha Window 2 Vertical Start). Determines the vertical start position of Alpha Window 2. This value
is calculated according to the following formula:
Value = Desired screen position + (V_TOTAL – V_SYNC_END) + 1.
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Video Processor Module (Continued)
Table 6-9. F4BAR0+Memory Offset: Video Processor Configuration Registers (Continued)
Bit
Description
Offset 78h-7Bh
Alpha Window 2 Color Register (R/W)
Reset Value: 00000000h
31:25
24
Reserved.
ALPHA2_COLOR_REG_EN (Alpha Window 2 Color Register Enable). Enable bit for the color key matching in Alpha
Window 2.
0: Disable. Where there is a color key match, graphics and video are alpha-blended.
1: Enable. If this bit is enabled and the alpha window is enabled, then where there is a color key match, the color value (in
bits [23:0], ALPHA2_COLOR_REG) is displayed.
23:0
ALPHA2_COLOR_REG (Alpha Window 1 Color Register). Specifies the color to be displayed inside Alpha Window 2
when there is a color key match in the alpha window. This is an RGB value (for RGB blending) or a YUV value (for YUV
blending). In Interlaced YUV blending mode, Y/2 value should be used.
This color is only displayed if the alpha window is enabled and bit 24 (ALPHA2_COLOR_REG_EN) is enabled.
Offset 7Ch-7Fh
Alpha Window 2 Control Register (R/W)
Reset Value: 00000000h
31:18
17
Reserved.
LOAD_ALPHA (Load Alpha Value). (Write Only) When set to 1, this bit causes the Video Processor to load the alpha
value (in bits [7:0], ALPHA2_VAL) at the start of the next frame.
16
ALPHA2_WIN_EN (Alpha Window 2 Enable). Enable bit for Alpha Window 2.
0: Disable Alpha Window 2.
1: Enable Alpha Window 2.
Note: Valid only if video window is enabled (F4BAR0+Memory Offset 00h[0] = 1).
ALPHA2_INCR (Alpha Window 2 Increment). Specifies the alpha value increment/decrement.
15:8
7:0
This is a signed 8-bit value that is added to the alpha value for each frame. The MSB (bit 15) indicates the sign (i.e., incre-
ment or decrement). When this value reaches either the maximum or the minimum alpha value (255 or 0) it keeps that value
(i.e., it is not incremented/decremented) until it is reloaded via bit 17 (LOAD_ALPHA).
ALPHA2_VAL (Alpha Window 1 Value). Specifies the alpha value to be used for this window.
Offset 80h-83h
Alpha Window 3 X Position Register (R/W)
Reset Value: 00000000h
Note: H_TOTAL and H_SYNC_END are values programmed in the GX1 module’s Display Controller Timing registers
(GX_BASE+Memory Offset 8330h[26:19] and 8338h[10:3], respectively). The value of (H_TOTAL – H_SYNC_END) is some-
times referred to as "horizontal back porch". For more information, see the GX1 Processor Series Datasheet.
Note: Desired screen position should not be outside a video window (F4BAR0+Memory Offset 08h and 0Ch).
31:27
26:16
Reserved.
ALPHA3_X_END (Alpha Window 3 Horizontal End). Determines the horizontal end position of Alpha Window 3 (not inclu-
sive). This value is calculated according to the following formula:
Value = Desired screen position + (H_TOTAL – H_SYNC_END) – 1.
15:11
10:0
Reserved.
ALPHA3_X_START (Alpha Window 3 Horizontal Start). Determines the horizontal start position of Alpha Window 3. This
value is calculated according to the following formula:
Value = Desired screen position + (H_TOTAL – H_SYNC_END) – 2.
Offset 84h-87h
Alpha Window 3 Y Position Register (R/W)
Reset Value: 00000000h
Note: V_TOTAL and V_SYNC_END are values programmed in the GX1 module’s Display Controller Timing registers
(GX_BASE+Memory Offset 8340h[26:16] and 8348h[26:16], respectively). The value of (V_TOTAL – V_SYNC_END) is some-
times referred to as "vertical back porch". For more information, see the GX1 Processor Series Datasheet.
Desired screen position should not be outside a video window (F4BAR0+Memory Offset 08h and 0Ch).
31:27
26:16
Reserved.
ALPHA3_Y_END (Alpha Window 3 Vertical End). Determines the vertical end position of Alpha Window 3 (not inclusive).
This value is calculated according to the following formula:
Value = Desired screen position + (V_TOTAL – V_SYNC_END) + 2.
15:11
10:0
Reserved.
ALPHA3_Y_START (Alpha Window 3 Vertical End). Determines the vertical start position of Alpha Window 3. This value
is calculated according to the following formula:
Value = Desired screen position + (V_TOTAL – V_SYNC_END) + 1.
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Video Processor Module (Continued)
Table 6-9. F4BAR0+Memory Offset: Video Processor Configuration Registers (Continued)
Bit
Description
Offset 88h-8Bh
Alpha Window 3 Color Register (R/W)
Reset Value: 00000000h
31:25
24
Reserved.
ALPHA3_COLOR_REG_EN (Alpha Window 3 Color Register Enable). Enable bit for the color key matching in Alpha
Window 3.
0: Disable. Where there is a color key match, graphics and video are alpha-blended.
1: Enable. If this bit is enabled and the alpha window is enabled, then where there is a color key match, the color value (in
bits [23:0], ALPHA3_COLOR_REG) is displayed.
23:0
ALPHA3_COLOR_REG (Alpha Window 3 Color Register). Specifies the color to be displayed inside Alpha Window 3
when there is a color key match in the alpha window. This is an RGB value (for RGB blending) or a YUV value (for YUV
blending). In Interlaced YUV blending mode, Y/2 value should be used.
This color is only displayed if the alpha window is enabled and the bit 24 (ALPHA3_COLOR_REG_EN) is enabled.
Offset 8Ch-8Fh
Alpha Window 3 Control Register (R/W)
Reset Value: 00000000h
31:18
17
Reserved.
LOAD_ALPHA (Load Alpha Value). (Write Only) When set to 1, this bit causes the Video Processor to load the alpha
value (in bits [7:0], ALPHA3_VAL) at the start of the next frame.
16
ALPHA3_WIN_EN (Alpha Window 3 Enable). Enable bit for Alpha Window 3.
0: Disable Alpha Window 3.
1: Enable Alpha Window 3.
Valid only if video window is enabled (F4BAR0+Memory Offset 00h[0] = 1)
15:8
7:0
ALPHA3_INCR (Alpha Window 3 Increment). Specifies the alpha value increment/decrement. This is a signed 8-bit value
that is added to the alpha value for each frame. The MSB (bit 15) indicates the sign (i.e., increment or decrement). When
this value reaches either the maximum or the minimum alpha value (255 or 0) it keeps that value (i.e., it is not incre-
mented/decremented) until it is reloaded via bit 17 (LOAD_ALPHA).
ALPHA3_VAL (Alpha Window 3 Value). Specifies the alpha value to be used for this window.
Offset 90h-93h
Video Request Register (R/W)
Reset Value: 001B0017h
31:28
27:16
Reserved. Set to 0.
VIDEO_X_REQ (Video Horizontal Request). Determines the horizontal (pixel) location at which to start requesting video
data out of the video FIFO. This value is calculated according to the following formula:
Value = Desired screen position + (H_TOTAL – H_SYNC_END) – 2.
15:11
10:0
Reserved.
VIDEO_Y_REQ (Video Vertical Request). Determines the line number at which to start requesting video data out of the
video FIFO. This value is calculated according to the following formula:
Value = Desired screen position + (V_TOTAL – V_SYNC_END) + 1.
Offset 94h-97h
Alpha Watch Register (RO)
Reset Value: 00000000h
Alpha values may be automatically incremented/decremented for successive frames. This register can be used to read the alpha values
that are being used in the current frame.
31:24
23:16
15:8
7:0
Reserved.
ALPHA3_VAL (Value for Alpha Window 3).
ALPHA2_VAL (Value for Alpha Window 2).
ALPHA1_VAL (Value for Alpha Window 1).
Offset 98h-3FFh
Reserved
Offset 400h-403h
Video Processor Display Mode Register (R/W)
Reset Value: 00000000h
Selects various Video Processor modes.
31
Video FIFO Underflow (Empty).
0: No underflow has occurred.
1: Underflow has occurred.
Write 1 to reset this bit.
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Video Processor Module (Continued)
Table 6-9. F4BAR0+Memory Offset: Video Processor Configuration Registers (Continued)
Bit
Description
30
Video FIFO OverFlow (Full).
0: No overflow has occurred.
1: Overflow has occurred.
Write 1 to reset this bit.
29
28
VBI FIFO Underflow (Empty).
0: No underflow has occurred.
1: Underflow has occurred.
Write 1 to reset this bit.
VBI FIFO Overflow (Full).
0: No overflow has occurred.
1: Overflow has occurred.
Write 1 to reset this bit.
27:4
3
Reserved. Set to 0.
Upscale horizontally VBI data by 2.
0: No upscale. VBI data pass through.
1: Upscale horizontally by 2.
VBI_SOURCE (VBI Source). Selects the VBI source.
0: VIP block.
2
1: GX1 module.
Note: VBI is enabled by setting one or more of the VBI (odd/even) line-enable register bits. (Odd lines enabled at
F4BAR0+Memory Offset 40Ch[24:2]; even lines enabled at F4BAR0+Memory Offset 410h[24:2].)
1:0
VID_SEL (Video Select). Selects the source of the video data.
00: GX1 module.
10: VIP block.
01: Reserved.
11: Reserved.
The GX1 module’s video clock must be active at all times, regardless of the source of video input.
Offset 404h-407h
Offset 408h-40Bh
Reserved
Reset Value: 00000000h
Reset Value: 00000000h
Video Processor Test Mode Register (R/W)
31:0
Reserved.
Offset 40Ch-40Fh
VBI Line Enable Register - Odd (R/W)
Reset Value: 00000000h
31:30
29:25
24:2
Reserved.
LINE_OFFSET_ODD (Odd Field Line Offset). Specifies the offset (in number of lines) of line 2 from VSYNC.
VBI_LINE_EN_ODD (VBI Odd Field Line Enable). Bits [24:2] enable VBI lines 24 to 2 respectively for odd fields.
0: Disable.
1: Enable.
Bit 24 controls active video line. If bit 24 is set, all active video lines are treated as VBI lines.
1:0
Reserved.
Offset 410h-413h
VBI Line Enable Register - Even (R/W)
Reset Value: 00000000h
31:30
29:25
24:2
Reserved.
LINE_OFFSET_EVEN (Even Field Line Offset). Specifies the offset (in number of lines) of line 2 from VSYNC.
VBI_LINE_EN_EVEN (VBI Even Field Line Enable). Bits [24:2] enable VBI lines 24 to 2 respectively for even fields.
0: Disable.
1: Enable.
Bit 24 controls active video line. If bit 24 is set, all active video lines are treated as VBI lines.
1:0
Reserved.
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Video Processor Module (Continued)
Table 6-9. F4BAR0+Memory Offset: Video Processor Configuration Registers (Continued)
Bit
Description
Offset 414h-417h
VBI Horizontal Control Register (R/W)
Reset Value: 00000000h
31:27
26:16
15:11
10:0
Reserved.
VBI_H_END (VBI Horizontal End). Specifies the horizontal end position for VBI data sent to the encoder.
Reserved.
VBI_H_START (VBI Horizontal Start). Specifies the horizontal start position for VBI data sent to the encoder.
Offset 418h-41Bh
VBI Total Count Register - Odd (R/W)
Reset Value: 00000000h
31:20
19:0
Reserved.
VBI_TOTAL_COUNT_ODD (VBI Odd Fields Total Count). Specifies the total count of VBI data in bytes for odd fields. This
field is used to separate VBI data from active video data when both types of data are received from the GX1 module’s video
port.
Offset 41Ch-41Fh
VBI Total Count Register - Even (R/W)
Reset Value: 00000000h
31:20
19:0
Reserved.
VBI_TOTAL_COUNT_EVEN (VBI Even Fields Total Count). Specifies the total count of VBI data in bytes for even fields.
This field is used to separate VBI data from active video data when both types of data are received from the GX1 module’s
video port.
Offset 420h-423h
GenLock Register (R/W)
Reset Value: 00000000h
31:24
23
Reserved. Must be set to 0.
0DD_TO (Odd Field Time Out). Indicates CGENTO0 (F4BAR0+Memory Offset 43Ch[15:0]) has expired. This bit can be
reset by writing 1 to it.
22
EVEN_TO (Even Field Time Out). Indicates CGENTO1 (F4BAR0+Memory Offset 43Ch[31:16]) has expired. This bit can
be reset by writing 1 to it.
21:9
8
Reserved.
GENLOCK_TO_ENC_TIMING (GenLock to Encoder Timing). Selects the timing to which the GX1 module’s vertical tim-
ing needs to be synchronized.
0: VIP vertical timing.
1: Encoder vertical timing. The TV encoder generates a reference for GenLock at the start of line 1 of its counters.
7
6
Reserved. Set to 0
RST_ENC_BFOR_DLY (Reset Encoder Before Delay). Selects the position of the encoder reset with respect to the pro-
grammed VIP_VSYNC edge and delay.
0: The encoder is reset after the programmed delay.
1: The encoder is reset before the programmed delay.
5
4
3
FIELD_EVEN (Encoder Field Even). Used in conjunction with bit 0 of this register for single GenLock field synchronization.
0: Encoder field is set to odd.
1: Encoder field is set to even.
GENLOCK_TOUT_EN (GenLock Timeout Enable).
0: Disable.
1: Enable timeout.
VIP_VSYNC_EDGE_SEL (VIP VSYNC Edge Select). Selects which edge of the VSYNC signal should be synchronized
with VIP.
0: Rising edge.
1: Falling edge.
2
1
GX1_VSYNC_EDGE_SEL (GX1 VSYNC Edge Select). Selects which edge of the VSYNC signal should be synchronized
with the GX1 module.
0: Rising edge.
1: Falling edge.
CT_GENLOCK_EN (Enable Continuous GenLock Function).
0: The continuous GenLock function is disabled.
1: Enable locking (i.e., synchronization) of the GX1 VSYNC with the VIP VSYNC on every VSYNC (i.e., continuous lock-
ing).
Note: If bit 0 (SG_GENLOCK_EN) = 1, it overrides the value of this bit.
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Video Processor Module (Continued)
Table 6-9. F4BAR0+Memory Offset: Video Processor Configuration Registers (Continued)
Bit
Description
0
SG_GENLOCK_EN (Enable a Single GenLock Function).
0: GenLock is disabled if bit 1 (CT_GENLOCK_EN) = 0.
1: Enable synchronization (i.e., locking) of GX1 VSYNC with the VIP VSYNC and synchronization of the TV encoder field
with the VIP field, once. During the synchronization process, the TV encoder field is determined by bit 5 of this register.
When in Direct Video mode, it is critical that the field of the TV encoder and the Video Input Port (F4BAR2+Memory Off-
set 08h[24]) be the same after the synchronization event. After locking once, this bit is reset by hardware to 0.
Note: If this bit = 1, it overrides the value of bit 1 (CT_GENLOCK_EN).
Offset 424h-427h
GenLock Delay Register (R/W)
Reset Value: 00000000h
31:21
20:0
Reserved.
GENLOCK_DEL (GenLock Delay). Indicates the delay (in 27 MHz clocks) between the VIP VSYNC and the GX1 module’s
Display Controller VSYNC.
Offset 428h-43Bh
Offset 43Ch-43Fh
Reserved
Continuous GenLock Timeout Register (R/W)
Reset Value: 1FFF1FFFh
Reset Value: 00000000h
31:16
15:0
CGENTO1 (Even Field Continuous GenLock Timeout).
CGENTO0 (Odd Field Continuous GenLock Timeout).
Offset 800h-803h
Horizontal Timing Register (R/W)
This register is updated at each occurrence of HSYNC.
31:28
27:16
15:12
11:0
Reserved.
H_DISP_START (Horizontal Display Start). Specifies the first horizontal valid pixel position on a TV screen, in pixel clocks.
Reserved.
H_TOTAL (Horizontal Total). Specifies the total number of pixels per line - 1, for TV. For NTSC, use 857; for PAL use 863.
Offset 804h-807h
Horizontal Sync Timing Register (R/W)
Reset Value: 00000000h
This register is updated at each occurrence of HSYNC.
31:28
27:16
15:12
11:0
Reserved.
H_SYNC_END (Horizontal Sync End). Specifies the horizontal synchronization end position in pixel clocks.
Reserved.
H_SYNC_START (Horizontal Sync Start). Specifies the horizontal synchronization start position in pixel clocks.
Offset 808h-80Bh
Vertical Sync Timing Register (R/W)
Reset Value: 00000000h
This register is updated at each occurrence of VSYNC.
31:28
27:26
Reserved.
V_DISP_SKEW_EVEN (Vertical Display Skew). Specifies the vertical display end skew in terms of horizontal lines for all
even fields. Recommended value is 1.
25:24
V_DISP_SKEW_ODD (Vertical Display Skew). Specifies the vertical display start skew in terms of horizontal lines for all
odd fields. Recommended value is 1.
23:22
21:12
11:10
9:0
Reserved.
V_SYNC_END (Vertical Sync End). Specifies the vertical synchronization end position in terms of horizontal lines.
Reserved.
VSYNC_START (Vertical Sync Start). Specifies the vertical synchronization start position in terms of horizontal lines.
Offset 80Ch-80Fh
Display Line End Register (R/W)
Reset Value: 00000000h
31:28
27:16
Reserved.
H_DISP_END (Horizontal Display End). Specifies the horizontal display end on a TV screen. The value is calculated
according to the following formula:
H_DISP_END = H_DISP_START + (Display_Active) + 512 - (H_TOTAL / 2)
Display_Active is the active number of pixels on a TV (i.e., 720).
Reserved.
15:9
8:0
VER_DISP (Vertical Display). Specifies the total number of display lines per field on a TV screen.
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Video Processor Module (Continued)
Table 6-9. F4BAR0+Memory Offset: Video Processor Configuration Registers (Continued)
Bit
Description
Offset 810h-813h
Horizontal Pre Encoder Scale Register (R/W)
Reset Value: 00000000h
31
Reserved. Must be set to 0.
30:24
PE_SCALE_STEP. Scale step of the pre-encoder scaler. The programmed value needs to be 64/(scale factor). Meaning,
use 64 for no scaling, use 58 for 11/10 upscale, or use 70 for 11/12 downscale.
23:22
Y/C Delay. Used to calibrate Y/C delay.
00: No change in delay
01: Luminance is delayed one pixel time (2 TV Encoder clock cycles).
10: Chrominance is delayed one pixel time (2 TV Encoder clock cycles).
11: Chrominance is delayed two pixel times (4 TV Encoder clock cycles)
Reserved. Set to 0.
21:0
Offset 814h-817h
Horizontal Scaling/Control Register (R/W)
Reset Value: 00000000h
31
Reserved.
FLICKER_FILT_CNTRL (Flicker Filter Control).
30:29
00: Flicker filter with 1/4, 1/2, 1/4. This setting must be used to enable the flicker filter when progressive blending is used.
01: Flicker filter with 1/2, 1, 1/2. This setting must be used to enable the flicker filter when interlaced blending is used.
10: Flicker filter disabled.
11: Reserved.
28
H_REF_SEL (Horizontal Reference Select). Selects reference for the horizontal display position.
0: HSYNC generated in the TVOUT timing generator.
1: HSYNC generated in the TV Encoder block. This is the recommended setting.
27:24
EX_RES_CTL (External Reset Control). To maintain field synchronization between the GX1 graphics module and the TV
encoder, the GX1 VSYNC signal can reset the TV encoder timing generator. This register selects the field interval between
resets.
0000: Once every odd field.
0010: Once every even field.
0101: The next odd field. Returns 0101 until the reset event occurs. After the reset event, returns 0100 and no further
resets occur.
0111: The next even field. Returns 0111 until the reset event occurs. After the reset event, returns 0110 and no further
resets occur.
1000: Once every programmable number of odd fields. See bits [15:12] and 11 (External Reset Interval bits).
1010: Once every programmable number of even fields. See bits [15:12] and 11 (External Reset Interval bits).
1110: Once every field.
All other settings: Reserved.
Reserved.
23:21
20:16
15:12
Reserved. Must be set to 2.
EX_RES_INTRVl (External Reset Interval). Specifies the interval (the number of frames) between resets of the encoder
minus 1 (i.e., a setting of 1 results in a reset to the encoder every 2 frames (or 4 fields)).
These bits are relevant only if bits [27:24] (EX_RES_CTL) are set to 1000 or 1010.
EX_RES_INTRVl_16 (External Reset Interval + 16). Adds 16 frames to the external Reset Interval.
These bits are relevant only if bits [27:24] (EX_RES_CTL) are set to 1000 or 1010.
HOR_INTP (Horizontal Interpolation).
11
10
0: Disables interpolation. Pixel replication is enabled for pre-encoder scaler.
1: Enables interpolation in pre-encoder scaler.
9:0
Reserved. Write as read.
Offset 818h-81Bh
TVOUT Debug Register
Reset Value: 00000440h
31:11
10
Reserved. These bits are used for test purposes only. Write as read.
Reserved. Write as read.
9
FIELD_INVR (Field Invert).
0: Field is not inverted. (Default)
1: Field is inverted
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Video Processor Module (Continued)
Table 6-9. F4BAR0+Memory Offset: Video Processor Configuration Registers (Continued)
Bit
Description
8
7
Reserved. Write as read.
ENC_OR_TV_FIELD (Encoder or TVOUT Current Field). Selects if the current field status bit (bit 6) is to be generated by
TVOUT or by the encoder.
0: Derive the field from the encoder timing generator. (Default)
1: Derive the field from the TVOUT module timing generator.
Reserved. Write as read.
6
5:0
Reserved. Write as read.
Offset 81Ch-81Fh
Offset C00h-C03h
Reserved
Timing & Encoder Control 1 Register
Reset Value: 00000000h
31
VTEN (Video Timing Enable). When this bit is set to 0, the counters in the video timing generator are disabled, the sync
signals are disabled, and the blank signals are asserted.
0: Disable.
1: Enable.
30
IPS (Invert PAL Switch). When set, inverts the sense of the “PAL Switch”. (Refer to Video Demystified, Third edition by
Keith Jack, Chapter 9, section “Color Subcarrier Generation” and section “GenLock”, subsection “Subcarrier Generation for
details regarding PAL Switch.)
29:28
SCRESET (Subcarrier Reset). Defines the interval between resets of the subcarrier generator.
00: Never reset.
01: Reset every two lines.
10: Reset every two frames. (Best setting for NTSC.)
11: Reset every four frames (PAL).
27
26
BLANK (Blank). When this bit is set to 1, the video output is blanked.
CBD (Color Burst Disable).
0: Color burst is enabled.
1: Color burst is disabled.
25
24
SETUP (Setup). Adds 7.5 IRE offset to the video signal and rescales the signal as required.
0: Do not add the IRE offset. This is the recommended value for PAL.
1: Add the IRE offset. This is the recommended value for NTSC.
PAL (PAL Select). Sets color encoding mode to PAL or NTSC.
0: NTSC.
1: PAL.
23
STD (Standard). Sets the overall timing of the video generator.
1: 525 lines / 60 Hz
0: 625 lines / 50 Hz
22:21
REFEN[1:0] (Enable FrameRef). Enables the externally provided FrameRef to initialize the horizontal and vertical counters
and/or the internal frame counter.
00: No initialization.
01: The horizontal and vertical counters are initialized to the values in HPhase and VPhase.
10: The internal frame counter is set to 3.
11: The horizontal and vertical counters are initialized to the values in HPhase and VPhase and the internal frame counter
is set to 3,
20:11
VPHASE (Vertical Phase). Defines the phase (i.e., the number of lines) between the internal vertical counter and the exter-
nally provided FrameRef.
If REFEN[0] (bit 21) = 1, the vertical counter in the video timing generator is set to this value when FrameRef is asserted.
Valid values are:
PAL:
1 to 625
1 to 525
NTSC:
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Table 6-9. F4BAR0+Memory Offset: Video Processor Configuration Registers (Continued)
Bit
Description
10:0
HPHASE. (Horizontal Phase). This bit field defines the phase (i.e., the number of pixels) between the internal horizontal
counter and an externally provided FrameRef.
If REFEN[0] (bit 21) = 1, the horizontal counter in the video generator is set to this value when FrameRef is asserted.
The counter is split into two parts, a 10-bit "half-line" counter and a single bit "line-half". The half-line counter counts half a
line and is reset. When the half-line counter is reset, the line-half indicator toggles.
In PAL mode, there are 1728 27 MHz clock cycles per line. In this mode, the half-line counter counts 0 to 863. To set the hor-
izontal phase to a value HP between 0 and 1727, HPHASE[10] is set to HP/864 and HPHASE[9:0] is set to HP%864.
In NTSC mode, there are 1716 27 MHz clock cycles per line, so HPHASE[10] is set to HP/858 and HPHASE[9:0] is set to
HP%858.
Offset C04h-C07h
Timing & Encoder Control 2 Register
Reset Value: 1FF00000h
31
30
Anlg (Analog Line). When set, the horizontal blanking interval is increased to comply with relevant specification.
TV DAC Mode Bit 2. See TV DAC Mode Bits [1:0] (F4BAR0+Memory Offset C08h[4:3]).
29:20
19
Reserved.
Y2BP (Luminance Bypass). Luminance 2x oversampling bypass.
0: Disable.
1: Enable.
18
C2BP (Chrominance Bypass). Chrominance 2x oversampling bypass.
0: Disable.
1: Enable.
17:16
CFS (Chrominance Lowpass Filter Select). Selects one of three frequency responses for the chrominance lowpass filter:
00 or 01: Filter is bypassed.
10: 1.3 MHz lowpass for composite video output.
11: 1.8 MHz lowpass for S-Video output.
15:8
7:0
HUE (Hue Offset). Defines a fixed hue offset which is added to the subcarrier phase during the active video portion of the
line. The value programmed is: hue (degrees) / 256.
SCPHASE (Subcarrier Phase). Defines the subcarrier phase at the start of a two-frame sequence (NTSC) or four-frame
sequence (PAL).
The number is: phase (in degrees) / 256.
Offset C08h-C0Bh
Timing & Encoder Control 3 Register
Reset Value: 00000000h
31:5
4:3
Reserved.
TV DAC Mode Bits [1:0]. Determines signal order of the TV DAC outputs. Used in conjunction with TV DAC Mode Bit 2
(F4BAR0+Memory Offset C04h[30]).
TV DAC Mode Bits [2:0]
Ball No.
EBGA: AD3
EBGA: AD1
EBGA: AC2
EBGA: AB3
C04h[30] C08h[4]
C08h[3] TEPBGA: D24 TEPBGA: A24 TEPBGA: C23 TEPBGA: A23 Mode
x
0
0
1
1
x
0
1
0
1
0
1
1
1
1
CVBS
CVBS
TVB
SVY
TVR
SVC
TVB
TVR
Cr
CVBS
TVG
TVG
Y
Super Video
SCART
SCART
YCbCr
CVBS
Cb
CVBS
Cr
CVBS
Cb
Y
YCbCr
2:1
SyncMode. Determines where sync is output in SCART mode.
00: Reserved.
01: Sync is added to TVG.
10: Sync is output on the CVBS signal.
11: Reserved.
0
CS (Component Setup).
0: No setup is applied.
1: A 7.5 IRE setup is applied to the YCbCr output.
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Video Processor Module (Continued)
Table 6-9. F4BAR0+Memory Offset: Video Processor Configuration Registers (Continued)
Bit
Description
Offset C0Ch-C0Fh
31:0 SCFREQ (Subcarrier Frequency). Defines the subcarrier frequency.
The value programmed is: round(fsc/fclk x 232
where fsc is the desired subcarrier frequency, and fclk is the clock frequency (27 MHz).
Offset C10h-C13h Display Position Register
Subcarrier Frequency Register
Reset Value: 21F07C1Fh
)
Reset Value: 00120071h
31:25
24:16
Reserved.
VSTART (Vertical Start). Defines the vertical start position of the top field, relative to the start of VSYNC (line 1 for PAL, line
4 for NTSC).
For 480-line NTSC this field is set to 18 (12h).
For 576-line PAL this field is set to 22 (16h).
Reserved.
15:10
9:0
HSTART (Horizontal Start). Defines the start of active video relative to the start of the line (hcount = 0) in 13.5 MHz clock
periods. The number programmed is START − 9.
For example:
NTSC:
Active video starts a nominal 122 13.5 MHz clock periods after the start of line.
The number programmed is 113 (71h).
PAL:
Active video starts 132 13.5 MHz clock periods after the start of line.
The number programmed is 123 (7Bh).
Offset C14h-C17h
Display Size Register
Reset Value: 00EF02CFh
31:25
24:16
Reserved.
DISPHEIGHT (Display Height). Defines the height of a displayed field in lines. Programmed value equals LINE − 1.
For 720x480 NTSC, set to 239 (EFh).
For 720x576 PAL, set to 287 (11Fh).
15:10
9:0
Reserved.
DISPWIDTH (Display Width). Defines the width of the displayed video in 13.5 MHz clock periods.
If “Frame_Width” is the displayed frame width in pixels, the number programmed is Frame_Width − 1.
For standard NTSC and PAL applications, the number programmed is 719 (2CFh).
Offset C18h-C1Bh
Closed Captioning Data Register
Reset Value: 00000000h
This register describes two closed captioning characters that are encoded onto the line programmed by CC_LINE (F4BAR0+Memory
Offset C28h[4:0]) of the odd video field. These characters are encoded onto the video output only once. The characters written must
have an odd parity MSB bit. If characters 1 and 2 are not updated before the next VSYNC at the start of a top field, NULL (0) characters
are encoded onto the line. Normally, closed captioning data is place on line 21 (CC_LINE = 11h) for NTSC operation.
31:16
15:8
7:0
Reserved.
CHAR2 (Second Closed Caption Character).
CHAR1 (First Closed Caption Character).
Offset C1Ch-C1Fh
Extended Data Services Data Register
Reset Value: 00000000h
This register describes two extended data services characters that are encoded onto the line programmed by CC_LINE (F4BAR0+Mem-
ory Offset C28h[4:0]) of the even video field. These characters are encoded onto the video output only once. The characters written
must have an odd parity MSB bit. If characters 1 and 2 are not updated before the next VSYNC at the start of a bottom field, NULL (0)
characters are encoded onto the line. Normally, extended data services data is place on line 21 (CC_LINE = 11h) for NTSC operation.
31:16
15:8
7:0
Reserved.
CHAR2 (Second Extended Data Services Character).
CHAR1 (First Extended Data Services Character).
Offset C20h-C23h
CGMS Data Register
Reset Value: 00000000h
31:20
19:0
Reserved.
CGMS_DATA (CGMS Data). This bit field contains the NTSC (JAPAN) CGMS data. This data in this field is modulated onto
the video signal on the field line specified in the CGMS_LINE bits of Closed Captioning Control register (F4BAR0+Memory
Offset C28h[12:8]). The data is modulated on to the specified line in the top and/or bottom field according to the setting of
bits [14:13] in the Closed Captioning Control register. The bits are modulated onto the video waveform in the order 19-0.
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Video Processor Module (Continued)
Table 6-9. F4BAR0+Memory Offset: Video Processor Configuration Registers (Continued)
Bit
Description
Offset C24h-C27h
WSS Data Register
Reset Value: 00000000h
31:14
13:0
Reserved.
WSS_DATA (Wide Screen Signalling Data). This register contains PAL “Wide Screen Signalling” data. The data in this
field is modulated onto line 23 of PAL frames if bit 15 (WSE) of the Closed Captioning Control register is set to 1
(F4BAR0+Memory Offset C28h[15] = 1). The bits are modulated onto the video waveform in the order 0-13.
Offset C28h-C2Bh
Closed Captioning Control Register
Reset Value: 00000000h
31:16
15
Reserved.
WSE (Wide Screen Signalling Enable). If this bit is asserted, and the encoder is in PAL mode, the contents of the WSS
Data register (F4BAR0+Memory Offset C24h[13:0]) are encoded onto line 23 of the bottom video field.
14
13
CTE (CGMS Odd Field Enable). If this bit is asserted, the contents of the CGMS Data register (F4BAR0+Memory Offset
C20h[19:0]) are encoded in the odd field onto the line set in GCMS_LINE (bits [12:8]).
CBE (CGMS Even Field Enable). If this bit is asserted, the contents of the CGMS Data register are encoded in the even
field onto the line set in GCMS_LINE (bits [12:8]).
12:8
CGMS_LINE (CGMS Line). This bit field selects the line on which CGMS Data should be encoded. programmed with “line
number minus 4”. Normally set to 16 NTSC operation.
7
6
Reserved. Must be set to 0.
CCE (Closed Captioning Enable). If this bit is asserted, the contents of the Closed Captioning Data register
(F4BAR0+Memory Offset C18h[15:0]) are encoded in the odd field onto the line set in CC_LINE (bits [4:0]).
5
EDSE (Extended Data Services Enable). If this bit is asserted, the contents of the Extended Data Services Data register
(F4BAR0+Memory Offset C1Ch[15:0]) are encoded in the even field onto the line set in CC_LINE (bits [4:0]).
4:0
CC_LINE (Closed Captioning Line). This bit field selects the line on which Closed Captioning and/or Extended Data Ser-
vices Data should be to encoded, programmed with the “line number minus 4”. Normally set to 17 for NTSC operation.
Offset C2Ch-C2Fh
DAC Control Register
Reset Value: 00000020h
31:7
6
Reserved.
TV_DAC_TEST (TV DAC Glitch Test). When this bit is asserted, the TV DACs operate in Test mode.
PDN (Power Down). When asserted, the TV DACs are placed in power-down mode.
VREF (VREF Select). Selects the source for the voltage reference for the TV DACs.
00 & 01: Select internal bandgap reference.
5
4:3
10 & 11: Select external voltage reference.
2:0
TRIM. The value in this field is used to adjust the internal voltage reference.
Offset C50h-C53h
VBI Scaler Register
Reset Value: 00000004h
31:17
16
Reserved.
VBI_TEST_MODE (VBI Test Mode). Precoded data (a square wave) sent as VBI data.
0: Not precoded VBI data.
1: Precoded VBI data.
15:8
7:0
VBI_SCALE_GAIN (VBI Scale Gain).The VBI value for each pixel is multiplied by this value, and the result is divided by
128.
VBI_SCALE_OFFSET (VBI Scale Offset). This field contains a signed number between −128 and +127. This value is
added to the VBI value of each pixel.
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Video Processor Module (Continued)
6.3.2.2 VIP Support Registers - F4BAR2
F4 Index 18h, Base Address Register 2 (F4BAR2) points to
the base address of where the VIP Configuration registers
are located. Table 6-10 shows the memory mapped VIP
support registers accessed through F4BAR2.
Table 6-10. F4BAR2+Memory Offset: VIP Configuration Registers
Bit
Description
Offset 00h-03h
Video Interface Port Configuration Register (R/W)
Reserved. Must be set to 0.
Reset Value: 00000000h
31:23
22
VIP FIFO Bus Request Threshold. VIP FIFO issues a bus request when it is filled with 32 or 64 bytes.
0: 64 bytes.
1: 32 bytes
21
20
19
VBI Task B Store to Memory. When this bit is enabled, VBI task B data is stored to memory.
0: Disable.
1: Enable.
This bit is relevant only if bit 18 (VBI Configuration Override) = 1 (enabled).
VBI Task A Store to Memory. When this bit is enabled, VBI task A data is stored to memory.
0: Disable.
1: Enable.
This bit is relevant only if bit 18 (VBI Configuration Override) = 1 (enabled).
VBI Ancillary Store to Memory. When this bit is enabled, VBI Ancillary data is stored to memory.
0: Disable.
1: Enable.
This bit is relevant only if bit 18 (VBI Configuration Override) = 1 (enabled).
18
17
VBI Configuration Override. When this bit is enabled, bits [21:19] override the setup specified in bits 17 and 16.
0: Disable.
1: Enable.
VBI Data Task. Specifies the CCIR-656 video stream task used to store VBI data to memory.
0: Task B.
1: Task A.
This bit is relevant only if bit 16 (VBI Mode for CCIR-656) = 1 and bit 18 (VBI Configuration Override) = 0 (disabled).
VBI Mode for CCIR-656. Specifies the mode in which to store VBI data to memory.
0: Use CCIR-656 ancillary data to store VBI data to memory.
1: Use CCIR-656 video task A or B to store VBI data to memory, depending on the value of bit 17 (VBI Task).
This bit is only used if bit 18 (VBI Configuration Override) = 0 (disabled).
Reserved. Set to 0.
16
15:2
1:0
Video Input Port Mode. Selects VIP operating mode.
10: CCIR-656 mode.
All other decodes: Reserved.
Offset 04h-07h
Video Interface Control Register (R/W)
Reset Value: 00000000h
31:18
17
Reserved. Must be set to 0.
Line Interrupt. When asserted, allows interrupt (INTC#) generation when the Video Current Line register (F4BAR2+ Mem-
ory Offset 10h) contents equal the Video Line Target Register (F4BAR2+ Memory Offset 14h) contents.
0: Disable.
1: Enable.
16
Field Interrupt. When asserted, allows interrupt (INTC#) generation at the end of a field (i.e., the end of active video for the
current field). Interrupt generation can be enabled regardless of whether or not video capture (store to memory) is enabled.
0: Disable.
1: Enable.
15:11
Reserved. Must be set to 0.
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Video Processor Module (Continued)
Table 6-10. F4BAR2+Memory Offset: VIP Configuration Registers (Continued)
Bit
Description
10
Auto-Flip. Video port operation mode.
0: The video port automatically detects the even and odd fields based on the VP_HREF and VP_VSYNC_IN signals or the
CCIR-656 control codes.
1: The even/odd field detect logic is disabled and the video port automatically toggles between the even and odd buffers
during capture. The odd buffer is the first to be filled in this mode.
This bit must be programmed to 0 when Direct Video mode is used. Direct Video mode is used when VID_SEL = 10
(F4BAR0+Memory Offset 400h[1:0]). Otherwise the video select from the GX1 module. VID_SEL indicates the source of the
video data.)
9
8
Capture (Store to Memory) VBI Data.
0: Disable.
1: Enable.
Capture (Store to Memory) Video Data.
0: Disable.
1: Enable.
7:2
1:0
Reserved. Must be set to 0.
Run Mode Capture. Selects capture run mode.
00: Stop capture at end of current line.
01: Stop capture at end of current field.
10 Reserved.
11: Start capture at beginning of next field.
Offset 08h-0Bh
Video Interface Status Register (R/W)
Reset Value: xxxxxxxxh
31:25
24
Reserved.(Read Only)
Current Field. (Read Only)
0: Even field is being processed.
1: Odd field is being processed.
Reserved. (Read Only)
23:22
21
Base Register Not Updated. (Read Only) When set to 1, this bit indicates that one of the base registers (at
F4BAR2+Memory Offset 20h, 24h, 40h, and 44h) has been written but has not yet been updated.
0: All base registers are updated.
1: One or more of the base registers has not been updated.
FIFO Overflow Status Indication.
0: No overflow occurred.
20
1: An overflow occurred for the FIFO between the VIP and the Fast X-Bus.
Writing a 1 to this bit clears the status.
Reserved. (Read Only)
19:18
17
Line Interrupt (INTC#) Pending Status.
0: Interrupt not pending.
1: Interrupt pending.
Writing a 1 to this bit clears the status.
Field Interrupt (INTC) Pending Status.
0: Interrupt not pending.
16
1: Interrupt pending.
Writing a 1 to this bit clears the status.
Reserved. (Read Only)
15:10
9
VBI Data Capture Active. (Read Only)
0: VBI data is not being stored to memory.
1: VBI data is now being stored to memory.
Video Data Capture Active. (Read Only)
0: Video data is not being stored to memory.
1: Video data is now being stored to memory.
8
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Video Processor Module (Continued)
Table 6-10. F4BAR2+Memory Offset: VIP Configuration Registers (Continued)
Bit
Description
7:1
0
Reserved. (Read Only)
Run Status. (Read Only)
0: Video port capture is not active.
1: Video port capture is in progress.
Offset 0Ch-0Fh
Offset 10h-13h
Reserved
Reset Value: 00h
Video Current Line Register (RO)
Reset Value: xxxxxxxxh
31:10
9:0
Reserved.
Current Line. Indicates the video line currently being stored to memory. The count indicated in this field is reset to 0 at the
start of each field.
Offset 14h-17h
Video Line Target Register (R/W)
Reset Value: 00000000h
31:10
9:0
Reserved. Must be set to 0.
Line Target. Indicates the video line to generate an interrupt on.
Offset 18h-1Bh
Odd Field VBI Line Enable Register (R/W)
Reset Value: 00000000h
31:24
23:0
Reserved.
VBI Odd Field Line Enable. In Direct VBI mode, each of bits [23:0] enables a received odd field VBI line to be passed
directly to the TVOUT block.
0: Disable the line.
1: Enable the line.
Offset 1Ch-1Fh
Even Field VBI Line Enable Register (R/W)
Reset Value: 00000000h
31:24
23:0
Reserved.
VBI Even Field Line Enable. In Direct VBI mode, each of bits [23:0] enables a received even field VBI line to be passed
directly to the TVOUT block.
0: Disable the line.
1: Enable the line.
Offset 20h-23h
Video Data Odd Base Register (R/W)
Reset Value: 00000000h
This register specifies the base address in graphics memory where odd video field data are stored. Changes to this register take effect
at the beginning of the next field. The value in this register is 16-byte aligned.
Note: This register is double-buffered. When a new value is written to this register, the new value is placed in a special "pending" reg-
ister, and the "Base Register Not Updated" bit (F4BAR2+MemoryOffset 08h[21]) is set to 1. The Video Data Odd Base register
(this register) is not updated at this point. When the first data of the next field is stored to memory, the pending values of all
base registers (including this one) are written to the appropriate base registers, and the "Base Register Not Updated" bit is
cleared.
31:0
Video Odd Base Address. Base address where odd video data are stored in graphics memory. Bits [3:0] are always 0, and
define the required address space.
Offset 24h-27h
Video Data Even Base Register (R/W)
Reset Value: 00000000h
This register specifies the base address in graphics memory where even video field data are stored. Changes to this register take effect
at the beginning of the next field. The value in this register is 16-byte aligned.
Note: This register is double-buffered. When a new value is written to this register, the new value is placed in a special "pending" reg-
ister, and the "Base Register Not Updated" bit (F4BAR2+MemoryOffset 08h[21]) is set to 1. The Video Data Even Base register
(this register) is not updated at this point. When the first data of the next field is stored to memory, the pending values of all
base registers (including this one) are written to the appropriate base registers, and the "Base Register Not Updated" bit is
cleared.
31:0
Video Even Base Address. Base address where even video data are stored in graphics memory. Bits [3:0] are always 0,
and define the required address space.
Offset 28h-2Bh
Video Data Pitch Register (R/W)
Reset Value: 00000000h
This register specifies the logical width of the video data buffer. This value is added to the start of the line address to get the address of
the next line where video data are stored to memory. This value must be an integral number of DWORDs.
31:16
15:0
Reserved.
Video Data Pitch. Specifies the logical width of the video data buffer. Bits [1:0] are always 0.
Offset 2Ch-3Fh
Reserved
Reset Value: 00000000h
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Video Processor Module (Continued)
Table 6-10. F4BAR2+Memory Offset: VIP Configuration Registers (Continued)
Bit
Description
Offset 40h-43h
VBI Data Odd Base Register (R/W)
Reset Value: 00000000h
This register specifies the base address in graphics memory where VBI data for odd fields are stored. Changes to this register take
effect at the beginning of the next field. The value in this register is 16-byte aligned.
Note: This register is double-buffered. When a new value is written this register, the new value is placed in a special "pending" regis-
ter, and the "Base Register Not Updated" bit (F4BAR2+MemoryOffset 08h[21]) is set to 1. The VBI Data Odd Base Register
(this register) is not updated at this point. When the first data of the next field is stored to memory, the pending values of all
base registers (including this one) are written to the appropriate base registers, and the "Base Register Not Updated" bit is
cleared.
31:0
VBI Odd Base Address. Base address where VBI data for odd fields is stored in graphics memory. Bits [3:0] are always 0
and define the required address space.
Offset 44h-47h
VBI Data Even Base Register (R/W)
Reset Value: 00000000h
This register specifies the base address in graphics memory where VBI data for even fields is stored. Changes to this register take effect
at the beginning of the next field. The value in this register is 16-byte aligned.
Note: This register is double-buffered. When a new value is written to this register, the new value is placed in a special "pending" reg-
ister, and the "Base Register Not Updated" bit (F4BAR2+MemoryOffset 08h[21]) is set to 1. The VBI Data Even Base Register
(this register) is not updated at this point. When the first data of the next field is stored to memory, the pending values of all
base registers (including this one) are written to the appropriate base registers, and the "Base Register Not Updated" bit is
cleared.
31:0
VBI Even Base Address. Base address where VBI data for even fields is stored in graphics memory. Bits [3:0] are always 0
and define the required address space.
Offset 48h-4Bh
VBI Data Pitch Register (R/W)
Reset Value: 00000000h
This register specifies the logical width of the VBI data buffer. This value is added to the start of the line address to get the address of the
next line where VBI data are stored to memory. This value must be an integral number of DWORDs.
31:16
15:0
Reserved.
VBI Data Pitch. Specifies the logical width of the video data buffer. Bits [1:0] are always 0.
Offset 4Ch-1FFh
Reserved
Reset Value: 00h
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7.0 Debugging and Monitoring
7.1.2 Optional Instruction Support
7.1 TESTABILITY (JTAG)
The TAP supports the following IEEE optional instructions:
The Test Access Port (TAP) allows board level interconnec-
tion verification and chip production tests. An IEEE-
1149.1a compliant test interface, TAP supports all IEEE
mandatory instructions as well as several optional instruc-
tions for added functionality. See Table 7-1 for a summary
of all instructions support. For further information on JTAG,
refer to IEEE Standard 1149.1a-1993 Test Access Port and
Boundary-Scan Architecture.
• IDCODE
Presents the contents of the Device Identification
register in serial format.
• CLAMP
Ensures that the Bypass register is connected between
TDI and TDO, and then drives data that was loaded into
the Boundary Scan register (e.g., via SAMPLE-
PRELOAD instruction) to output signals. These signals
do not change while the CLAMP instruction is selected.
7.1.1 Mandatory Instruction Support
The TAP supports all IEEE mandatory instructions, includ-
ing:
• HIZ
• BYPASS.
Puts all chip outputs in inactive (floating) state
(including all pins that do not require a TRI-STATE
output for normal functionality). Note that not all pull-up
resistors are disabled in this state.
Presents the shortest path through a given chip (a 1-bit
shift register).
• EXTEST
Drives data loaded into the JTAG path (possibly with a
SAMPLE/PRELOAD instruction) to output pins.
7.1.3 JTAG Chain
Balls that are not part of the JTAG chain:
• SAMPLE/PRELOAD
• TV DACs
• CRT DACs
• USB I/Os
Captures chip inputs and outputs.
Table 7-1. JTAG Mode Instruction Support
Instruction Activity
Code
000
001
010
011
100
101
110
111
EXTEST
SAMPLE/PRELOAD
IDCODE
Drives shifted data to output pins.
Captures inputs and system outputs.
Scans out device identifier.
HIZ
Puts all output and bidirectional pins in TRI-STATE mode.
Drives fixed data from Boundary Scan register.
CLAMP
Reserved
Reserved
BYPASS
Presents shortest external path through device.
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8.0 Electrical Specifications
This chapter provides information about:
8.1.2 Absolute Maximum Ratings
Stresses beyond those indicated in the following table may
cause permanent damage to the SC1200/SC1201, reduce
device reliability and result in premature failure, even when
there is no immediately apparent sign of failure. Prolonged
exposure to conditions at or near the absolute maximum
ratings may also result in reduced device life span and
reduced reliability.
• General electrical specifications
• DC characteristics
• AC characteristics
Note: All voltage values in this chapter are with respect
to VSS unless otherwise noted.
Note: The values in the following table are stress ratings
only. They do not imply that operation under other
conditions is impossible.
8.1 GENERAL SPECIFICATIONS
8.1.1 Power/Ground Connections and Decoupling
When testing and operating the SC1200/SC1201, use
standard high frequency techniques to reduce parasitic
effects. For example:
8.1.3 Operating Conditions
Table 8-2 lists the various power supplies of the
SC1200/SC1201 and provides the device operating condi-
tions.
• Filter the DC power leads with low-inductance decou-
pling capacitors.
• Use low-impedance wiring.
• Utilizing the PWR and GND pins.
Table 8-1. Absolute Maximum Ratings
Min Max
-45 110
Symbol
TCASE
Parameter
Unit
Comments
Operating case temperature1
oC
Storage temperature2
Supply voltage
oC
V
TSTORAGE
VCC
-45
125
See Table
8-2
VMAX
Voltage on
5V tolerant balls3
Others3,4
-0.5
-0.5
6.0
3.6
V
V
Input clamp current1
Output clamp current1
IIK
-0.5
10
25
mA
mA
IOK
1. Power applied - no clocks.
2. No bias.
3. Voltage min is -0.8V with a transient voltage of 20 ns or less.
4. Voltage max is 4.0V with a transient voltage of 20 ns or less.
Revision 6.0
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Electrical Specifications (Continued)
Table 8-2. Operating Conditions
Symbol1
Parameter
Min
0
Typ
-
Max
85
Unit
Comments
oC
V
TC
Operating case temperature
AVCCUSB
AVCCCRT
AVCCTV
Analog power supply. Powers internal ana-
log circuits and some external signals (see
Table 8-3).
3.14
3.3
3.46
VBAT
Battery supply voltage. Powers RTC and
ACPI when VBAT is greater than VSB (by at
2.4
3.0
3.46
V
least 0.5V), and some external signals (see
Table 8-3).
VIO
I/O buffer power supply. Powers most of the
external signals (see Table 8-3); certain
signals within this power plane are 5V
tolerant.
3.14
1.71
3.3
1.8
3.46
1.89
V
V
VCORE
Core processor and internal digital power
supply. Powers internal digital logic, includ-
ing internal frequency multipliers.
VPLL2
VPLL3
PLL. Internal Phase Locked Loops (PLLs)
power supply.
3.14
3.14
3.3
3.3
3.46
3.46
V
V
VSB
Standby power supply. Powers RTC and
ACPI when VSB is greater than VBAT-0.5V,
and some external signals (see Table 8-3).
VSBL
Standby logic. Powers internal logic
1.71
1.8
1.89
V
needed to support Standby VSB
VSBL requires a 0.1 µF bypass capacitor to
VSS
.
.
VCCCRT
CRT DAC. Powers CRT DAC digital
circuits.
1.71
1.8
1.89
V
1. For VIH (Input High Voltage), VIL (Input Low Voltage), IOH (Output High Current), and IOL (Output Low Current) operating
conditions refer to Section 8.2 "DC Characteristics" on page 377.
Notes:
1) All power sources must be connected to the
SC1200/SC1201, even if the function is not used
4) It is recommended that the voltage difference between
VCCCRT, VCORE and VSBL be less than 0.25V, in order
to reduce leakage current. If the voltage difference
exceeds 0.25V, excessive leakage current is used in
gates that are connected on the boundary between
voltage domains.
2) VSB, VSBL and VBAT must be on if any other voltage is
applied. VSB and VBAT voltages can be applied sepa-
rately. See Section 8.3.16 "Power-Up Sequencing" on
page 439.
5) It is recommended that the voltage difference between
VIO and VSB be less than 0.25V, in order to reduce
leakage current. If the voltage difference exceeds
0.25V, excessive leakage current is used in gates that
are connected on the boundary between voltage
domains.
3) The power planes of the SC1200/SC1201 can be
turned on or off. For more information, see Section
5.2.9 "Power Management Logic" on page 172.
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Revision 6.0
Electrical Specifications (Continued)
Table 8-3 indicates which power rails are used for each signal of the SC1200/SC1201 external interface. Power planes not
listed in this table are internal, and are not related to signals of the external interface.
Table 8-3. Power Planes of External Interface Signals
VCC Balls
VSS Balls
Power Plane
Signal Names
Standby
GPWIO[0:2], LED#, ONCTL#, PWRBTN#, PWRCNT[1:2],
THRM#, CLK32, IRRX1, RI2#, SDATA_IN2
VSB
VSS
Battery
X32I, X32O
VBAT
VSS
CRT DAC
TV DAC
RED, GREEN, BLUE, VREF, SETRES
AVCCCRT
AVCCTV
AVSSCRT
AVSSTV
CVBS, SVY, SVC, TVB, TVR, Cr, Cab, Y, TVREF, TVRSET,
TVIOM, TVCOMP
USB
I/O
DPOS_PORT1, DNEG_PORT1, DPOS_PORT2,
DNEG_PORT2, DPOS_PORT3, DNEG_PORT3
AVCCUSB
VIO
AVSSUSB
VSS
All other external interface signals
8.1.4 DC Current
8.1.4.2 Definition and Measurement Techniques of
SC1200/SC1201 Current Parameters
DC current is not a simple measurement. Three of the
SC1200/SC1201 power states (On, Active Idle, Sleep)
were selected for measurement. For each power state
measured, two functional characteristics (Typical Average,
Absolute Maximum) are used to determine how much cur-
rent the SC1200/SC1201 uses.
The
following
two
parameters
describes
the
SC1200/SC1201 current while in the On state:
• Typical Average: Indicates the average current used by
the SC1200/SC1201 while in the On state. This is
measured by running typical Windows applications in a
typical display mode. In this case, 800x600x8 bpp at 75
Hz, 50 MHz DCLK using a background image of vertical
stripes (4-pixel wide) alternating between black and
white with power management disabled (to guarantee
that the SC1200/SC1201 never goes into the Active Idle
state). This number is provided for reference only since
it can vary greatly depending on the usage model of the
system.
8.1.4.1 Power State Parameter Definitions
The DC characteristics tables in this section list Core and
I/O current for three of the power states. For more explana-
tion on the SC1200/SC1201 power states see Section
5.2.9 "Power Management Logic" on page 172.
• On (C0): All internal and external clocks with respect to
the SC1200/SC1201 are running and all functional
blocks inside the GX1 module (CPU Core, Memory
Controller, Display Controller, etc.) are actively gener-
ating cycles. This is equivalent to the ACPI specifica-
tion’s “S0,C0” state.
Note: This typical average should not be confused with
the typical power numbers. Typical power is based
on a combination of On (Typical Average) and
Active Idle states.
• Active Idle (C1): The CPU Core has been halted, all
other functional blocks (including the Display Controller
for refreshing the display) are actively generating cycles.
This state is entered when a HLT instruction is executed
by the CPU Core. From a user’s perspective, this state is
indistinguishable from the On state and is equivalent to
the ACPI specification’s “S0,C1” state.
• Absolute Maximum: Indicates the maximum instanta-
neous current used by the SC1200/SC1201. CPU Core
current is measured by running the Landmark Speed
200 benchmark test (with power management disabled)
and measuring the peak current at any given instant
during the test. I/O current is measured by running
Microsoft Windows 98 and using a background image of
vertical stripes (1-pixel wide) alternating between black
and white at the maximum display resolution of each of
the display type supported (CRT, TFT, and TV).
• Sleep (SL2): This is the lowest power state the
SC1200/SC1201 can be in with voltage still applied to
the device’s core and I/O supply pins. This is equivalent
to the ACPI specification’s “S1” state.
Revision 6.0
373
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Electrical Specifications (Continued)
8.1.4.3 Definition of System Conditions for Measur-
ing On Parameters
ports TV, CRT, and TFT displays, but it is expected that
generally only one display interface will be used. Power
consumed by the SC1200/SC1201 is different with different
displays. The CRT and TV DACs require current, while the
TFT interface even though it has no DAC to power, also
draws current while it is active. The CRT and TV DACs and
the TFT interface are presented as separate line items.
The chosen display type I/O current should be added to the
Typical, Absolute Maximum, and Active Idle I/O currents to
get total current.
The SC1200/SC1201’s current is highly dependent on two
functional characteristics, DCLK (DOT clock) and SDRAM
frequency. Table 8-4 shows how these factors are con-
trolled when measuring the typical average and absolute
maximum processor current parameters.
8.1.4.4 DC Current Measurements
Table 8-5 and Table 8-6 show the DC current measure-
ments of the SC1200/SC1201. The SC1200/SC1201 sup-
Table 8-4. System Conditions Used to Measure SC1200/SC1201’s Current Used During the “On” State
System Conditions
1
1
VCORE
VIO
CPU Current Measurement
Typical Average
DCLK Freq.
SDRAM Freq.
Nominal
Max
50 MHz2
Nominal
Max
Nominal
Max
135 MHz3
Absolute Maximum
1. See Table 8-2 on page 372 for nominal and maximum voltages.
2. A DCLK frequency of 50 MHz is derived by setting the display mode to 800x600x8 bpp at 75 Hz, using a display image
of vertical stripes (4-pixel wide) alternating between black and white with power management disabled.
3. A DCLK frequency of 135 MHz is derived by setting the display mode to 1280x1024x8 bpp at 75 Hz, using a display
image of vertical stripes (1-pixel wide) alternating between black and white with power management disabled.
Table 8-5. DC Characteristics On Mode
Symbol
Parameter1
Typ Avg
Abs Max
Unit
Comments
ICC3ON
fCLK = 266 MHz, I/O Current @ VIO = 3.3V
240
260
mA
ICC for VIO
(Nominal); CPU mode = On, excludes TFT
interface contribution and DACs
ICOREON
fCLK = 266 MHz, Core Current @ VCORE
1.8V (Nominal); CPU mode = On
=
900
1
1090
2
mA
mA
mA
ICC for VCORE
ISBON
SB Current @ VSB = 3.3V (Nominal); CPU
mode = On
ISBLON
SBL Current @ VSBL = 1.8V (Nominal); CPU
mode = On
10
20
ICC3ONTFT
ICCTV
I/O current contribution if TFT display is
used
30
50
mA
mA
If TV interface is used: CCTV Current @
VCCTV = 3.3 (Nominal); CPU mode = On
120
150
ICCCRT
If CRT interface is used: CCCRT Current @
60
80
mA
VCCCRT = 3.3 (Nominal); CPU mode = On
1.
fCLK ratings refer to internal clock frequency.
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Electrical Specifications (Continued)
Table 8-6. DC Characteristics for Active Idle, Sleep, and Off Modes
Symbol
Parameter1
Min
Typ
Max
Unit
Comments
ICC3IDLE
fCLK = 266 MHz, I/O Current @ VIO = 3.3V
(Nominal); CPU mode = Active Idle
240
mA
ICC for VIO
2
ICC3SLP
I/O Current @ VIO = 3.3V (Nominal);
CPU mode = Sleep
20
380
20
<1
<1
7
30
mA
mA
mA
mA
mA
µA
ICC for VIO
ICOREIDLE fCLK = 266 MHz, Core Current @ VCORE
1.8V (Nominal); CPU mode = Active Idle
=
ICC for VCORE
2
ICORESLP
Core Current @ VCORE = 1.8V (Nominal);
30
ICC for VCORE
CPU mode = Sleep
ISBOFF
SB Current @ VSB = 3.3V (Nominal);
CPU mode = Off
3
ISBLOFF
SBL Current @ VSBL = 1.8V (Nominal);
CPU mode = Off
ICC for VSBL
4
BAT Current @ VBAT = 3.0 (Nominal);
CPU mode = Off
50
15
TC = 25°C
TC = 25°C
IBAT
5
BAT Current @ VBAT = 3.0 (Nominal);
CPU mode = Off
7
µA
IBAT
1. fCLK ratings refer to internal clock frequency.
2. All inputs are at 0.2V or VIO – 0.2 (CMOS levels). All inputs are held static, and all outputs are unloaded (static IOUT
0 mA).
=
3. All VSBL supplied inputs are at 0.2V or VSBL – 0.2 (CMOS levels). All inputs are held static, and all outputs are unloaded
(static IOUT = 0 mA).
4. Applies to NSIDs SC1200UCL-266, SC1200UFH-266, SC1201UCL-266, and SC1201UFH-266.
5. Applies to NSID SC1201UFH-266B and SC1200UFH-266B.
8.1.5 Ball Capacitance and Inductance
Table 8-7 gives ball capacitance and inductance values.
Table 8-7. Ball Capacitance and Inductance
Symbol
Parameter
Min
Typ
Max
Unit
1
Input Pin Capacitance
4
7
pF
CIN
1
Clock Input Capacitance
I/O Pin Capacitance
Output Pin Capacitance
Pin Inductance
5
8
10
6
12
12
8
pF
pF
pF
nH
CIN
1
CIO
1
CO
2
20
LPIN
1. TA = 25°C, f = 1 MHz. All capacitances are not 100% tested.
2. Not 100% tested.
Revision 6.0
375
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Electrical Specifications (Continued)
8.1.6 Pull-Up and Pull-Down Resistors
Note: The resistors described in this table are imple-
mented as transistors. The resistance for PUs
The following table lists input balls that are internally con-
nected to a pull-up (PU) or pull-down (PD) resistor. If these
balls are not used, they do not require connection to an
external PU or PD resistor.
assumes VIN = VSS and for PDs assumes VIN
VIO.
=
Table 8-8. Balls with PU/PD Resistors
Ball No.
Ball No.
PU/
PD
Typ1
Value [Ω]
PU/
PD
Typ1
Value [Ω]
Signal Name
EBGA
TEPBGA
Signal Name
EBGA
TEPBGA
PCI
JTAG
TCK
FRAME#
C/BE[3:0]#
E1
D8
PU
PU
22.5K
22.5K
AL4
AJ5
AK5
AK4
E31
F28
F29
E29
PU
PU
PU
PU
22.5K
22.5K
22.5K
22.5K
A8, D8,
A10, A13
H4, F3, J2,
L1
TMS
TDI
PAR
C10
C8
J4
F2
F1
G1
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
22.5K
22.5K
22.5K
22.5K
22.5K
22.5K
22.5K
22.5K
22.5K
22.5K
22.5K
22.5K
22.5K
TRST#
IRDY#
GPIO2
TRDY#
STOP#
LOCK#
DEVSEL#
PERR#
SERR#
REQ[1:0]#
INTA#
B8
GPIO1
H2, AL12
AH3
AH4
AJ2
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
22.5K
22.5K
22.5K
22.5K
22.5K
22.5K
22.5K
22.5K
22.5K
22.5K
22.5K
22.5K
22.5K
22.5K
22.5K
22.5K
22.5K
22.5K
22.5K
22.5K
22.5K
22.5K
22.5K
22.5K
D10, N30
D28
C30
C31
C28
B29
AJ8
D9
GPIO6
C9
H3
E4
GPIO7
B5
GPIO8
B9
H2
GPIO9
AG4
AJ1
A9
H1
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO32
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
GPIO38
GPIO39
E3, C1
AE3
AF1
H4
A5, B5
D26
C26
C9
H30
AJ12
AL11
F1
N29
M29
D9
INTB#
INTC#
INTD#
B22
AA2
G3
A8
Low Pin Count (LPC)
AL15
J4
V31
A10
AG1
C9
LAD[3:0]
AJ10,AK10, L29, L30,
AL10, AJ11
PU
22.5K
L31, M28
A28
LDRQ
AL9
L28
PU
PU
22.5K
22.5K
H4
SERIRQ
AL8
J31
H3, AJ13
AJ11
AL10
AK10
AJ10
AL9
A9, N31
M28
L31
System (Straps)
CLKSEL[3:0]
AL13, AK3, P30, D29,
B27, F3
PD
100K
AF3, B8
BOOT16
G4
C8
PD
PD
PD
PD
PD
100K
100K
100K
100K
100K
L30
TFT_PRSNT
LPC_ROM
FPCI_MON
DID[1:0]
AK13
E4
P29
L29
D6
L28
D3
A4
AK9
AJ9
K31
K28
J31
D2, D4
C6, C5
ACCESS.bus2
AB1C
AL8
Power Management
AJ13
AL12
AJ12
AL11
N31
N30
N29
M29
PU
PU
PU
PU
22.5K
22.5K
22.5K
22.5K
PWRBTN#
E29
AH5
PU
PU
100K
100K
AB1D
GPWIO[2:0]
G29, G28,
E31
AJ6, AK5,
AH6
AB2C
AB2D
Test and Measurement
GTEST AL5
Parallel Port
AFD#/DSTRB#
PE
F30
PD
22.5K
AB2
T3
D22
D17
PU
22.5K
22.5K
1. Accuracy is: 22.5 KΩ resistors are within a range of 20 KΩ to
50 KΩ. 100 KΩ resistors are within a range of 90 KΩ to 250
KΩ.
PU2
PD2
PU
PU
PU
22.5K
2. Controlled by software.
SLIN#/ASTRB#
STB#/WRITE#
INIT#
W1
AB1
Y3
B20
A22
B21
22.5K
22.5K
22.5K
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Revision 6.0
Electrical Specifications (Continued)
8.2 DC CHARACTERISTICS
Table 8-9 describes the signal buffer types of the
SC1200/SC1201. (See Table 2-2 on page 23 for each sig-
nal’s buffer type.)
The subsections that follows provide detailed DC charac-
teristics according to buffer type.
Table 8-9. Buffer Types
Symbol
Description
Reference
Diode
INAB
Diodes only, no buffer
---
Input, ACCESS.bus compatible with Schmitt Trigger
Section 8.2.1
INBTN
INPCI
INSTRP
INT
Input, TTL compatible with Schmitt Trigger, low leakage
Input, PCI compatible
Section 8.2.2
Section 8.2.3
Section 8.2.4
Section 8.2.5
Section 8.2.6
Section 8.2.7
Section 8.2.8
Section 8.2.9
Section 8.2.10
Section 8.2.11
Section 8.2.12
Section 8.2.13
Section 8.2.14
Section 8.2.15
---
Input, Strap ball (min VIH is 0.6VIO) with weak pull-down
Input, TTL compatible
INTS
Input, TTL compatible with Schmitt Trigger type 200 mV
Input, with Schmitt Trigger type 200 mV
Input, USB compatible
INTS1
INUSB
OAC97
ODn
Output, Totem-Pole, AC97 compatible
Output, Open-Drain, capable of sinking n mA.1
ODPCI
Op/n
Output, Open-Drain, PCI compatible
Output, Totem-Pole, capable of sourcing p mA and sinking n mA
Output, PCI compatible, TRI-STATE
OPCI
OUSB
TSp/n
WIRE
Output, USB compatible
Output, TRI-STATE, capable of sourcing p mA and sinking n mA
Wire, no buffer
1. Output from these signals is open-drain and cannot be forced high.
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Electrical Specifications (Continued)
8.2.1 INAB DC Characteristics
Symbol
VIH
Parameter
Min
Max
Unit
V
Comments
Input High Voltage
Input Low Voltage
Input Leakage Current
1.4
-0.51
VIL
0.8
10
V
IIL
µA
µA
mV
VIN = VIO
VIN = VSS
-10
VHIS
Input hysteresis
150
1. Not 100% tested.
8.2.2 INBTN DC Characteristics
Symbol
Parameter
Min
Max
Unit
Comments
VSB+0.31
VIH
Input High Voltage
2.0
V
-0.51
VIL
IIL
Input Low Voltage
0.8
5
V
Input Leakage Current
µA
µA
mV
VIN = VSB
VIN = VSS
-36
Input Hysteresis1
VHIS
250
1. Not 100% tested.
8.2.3 INPCI DC Characteristics
Note that the buffer type for PCICLK (EBGA ball E2 / TEPBGA ball A7) is INT - not INPCI
.
Symbol
Parameter
Min
Max
Unit
Comments
VIO+0.31
0.3VIO
VIH
Input High Voltage
0.5VIO
V
-0.51
VIL
Input Low Voltage
V
V
Input Pull-up Voltage2
Input Leakage Current3,4
VIPU
0.7VIO
lIL
+/-10
µA
0 < VIN < VIO
1. Not 100% tested.
2. Not 100% tested. This parameter indicates the minimum voltage to which pull-up resistors are calculated in order to pull
a floated network.
3. Input leakage currents include HiZ output leakage for all bidirectional buffers with TRI-STATE outputs.
4. See Exceptions 2 and 3 in Section 8.2.15.1 on page 381.
8.2.4 INSTRP DC Characteristics
Symbol
Parameter
Min
Max
Unit
Comments
VIO+0.31
0.3VIO
36
VIH
Input High Voltage
0.6VIO
V
VIL
IIL
Input Low Voltage
V
Input Leakage Current
µA
µA
During Reset: VIN = VIO
VIN = VSS
−10
1. Not 100% tested.
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Electrical Specifications (Continued)
8.2.5 INT DC Characteristics
Symbol
Parameter
Min
Max
Unit
Comments
VIO+0.31
0.8
VIH
Input High Voltage
2.0
V
-0.51
VIL
IIL
Input Low Voltage
V
Input Leakage Current
10
µA
µA
VIN = VIO
VIN = VSS
−10
1. Not 100% tested.
8.2.6 INTS DC Characteristics
Symbol
Parameter
Min
Max
Unit
Comments
VIO+0.31
0.8
VIH
Input High Voltage
2.0
V
-0.51
VIL
IIL
Input Low Voltage
V
Input Leakage Current
10
µA
µA
mV
VIN = VIO
VIN = VSS
-10
VH
Input Hysteresis
200
1. Not 100% tested.
8.2.7 INTS1 DC Characteristics
Symbol
Parameter
Min
Max
Unit
Comments
VIO+0.31
0.3VIO
10
VIH
Input High Voltage
0.5VIO
V
-0.51
VIL
IIL
Input Low Voltage
V
Input Leakage Current
µA
µA
mV
VIN = VIO
VIN = VSS
-10
Input Hysteresis1
VHIS
200
1. Not 100% tested.
8.2.8 INUSB DC Characteristics
Symbol
Parameter
Min
Max
Unit
Comments
VIO+0.31
0.8
VIH
Input High Voltage
2.0
V
-0.51
VIL
IIL
Input Low Voltage
V
µA
µA
V
Input Leakage Current
10
VIN = VIO
-10
VIN = VSS
VDI
Differential Input Sensitivity
0.2
0.8
0.8
|(D+)-(D-)| and Figure 8-1
Includes VDI Range
VCM
VSE
Differential Common Mode Range
Single Ended Receiver Threshold
2.5
2.0
V
V
1. Not 100% tested.
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Electrical Specifications (Continued)
1.0
0.8
0.6
0.4
0.2
0.0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2
Common Mode Input Voltage (volts)
Figure 8-1. Differential Input Sensitivity for Common Mode Range
8.2.9 OAC97 DC Characteristics
Symbol
VOH
Parameter
Min
Max
Unit
V
Comments
lOH = -5 mA
lOL = 5 mA
Output High Voltage
Output Low Voltage
0.9VIO
VOL
0.1VIO
V
8.2.10 ODn DC Characteristics
Symbol
Parameter
Min
Min
Max
Unit
Comments
VOL
Output Low Voltage
0.4
V
IOL = n mA
8.2.11 ODPCI DC Characteristics
Symbol
Parameter
Max
Unit
Comments
VOL
Output Low Voltage
0.1VIO
V
lOL = 1500 µA
8.2.12 Op/n DC Characteristics
Symbol
VOH
Parameter
Min
Max
Unit
V
Comments
lOH = -p mA
lOL = n mA
Output High Voltage
Output Low Voltage
2.4
VOL
0.4
V
8.2.13 OPCI DC Characteristics
Symbol
VOH
Parameter
Min
Max
Unit
V
Comments
Output High Voltage
Output Low Voltage
0.9VIO
lOH = -500 µA
lOL =1500 µA
VOL
0.1VIO
V
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Electrical Specifications (Continued)
8.2.14 OUSB DC Characteristics
Symbol
Parameter
Min
Max
Unit
Comments
3.61
VUSB_OH
High-level Output Voltage
2.8
V
IOH = -0.25 mA
RL = 15 KΩ to GND
VUSB_OL
Low-level Output Voltage
0.3
2.0
V
V
IOL = 2.5 mA
RL = 1.5 KΩ to 3.6V
tUSB_CRS
Output Signal Crossover Voltage
1.3
1. Tested by characterization.
8.2.15 TSp/n DC Characteristics
Symbol
VOH
Parameter
Min
Max
Unit
V
Comments
IOH = -p mA
IOL = n mA
Output High Voltage
Output Low Voltage
2.4
VOL
0.4
V
8.2.15.1 Exceptions
1) OH is valid for a GPIO pin only when it is not configured as open-drain.
I
V
– V
power
IN
--------------------------------------
2) Signals with internal pull-ups have a maximum input leakage current of: –
R(pull – up)
Where Vpower is VIO, or VSB
.
V
– V
IN
SS
3) Signals with internal pull-downs have a maximum input leakage current of:
-----------------------------------------
+
R(pull – down)
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Electrical Specifications (Continued)
8.3 AC CHARACTERISTICS
The tables in this section list the following AC characteris-
tics:
Table 8-10. Default Levels for Measurement of
Switching Parameters
Symbol
VREF
VIHD
Parameter
Value (V)
1.5
• Output delays
• Input setup requirements
• Input hold requirements
• Output float delays
Reference Voltage
Input High Drive Voltage
Input Low Drive Voltage
Output High Drive Voltage
Output Low Drive Voltage
2.0
VILD
0.8
• Power-up sequencing requirements
VOHD
VOLD
2.4
The default levels for measurement of the rising clock edge
reference voltage (VREF), and other voltages are shown in
Table 8-10. Input or output signals must cross these levels
during testing. Unless otherwise specified, all measure-
ment points in this section conform to these default levels.
0.4
All AC tests are at VIO = 3.14V to 3.46V (3.3V nominal), TC
= 0 oC to 85 oC, CL = 50 pF, unless otherwise specified.
TX
VIHD
CLK
VREF
VILD
A
Max
B
Min
VOHD
VOLD
Valid Output n+1
VREF
Valid Output n
Outputs
Inputs
C
D
VIHD
VILD
VREF
Valid Input
Legend: A = Maximum Output or Float Delay Specification
B = Minimum Output or Float Delay Specification
C = Minimum Input Setup Specification
D = Minimum Input Hold Specification
Figure 8-2. Drive level and Measurement Points for Switching Parameters
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8.3.1 Memory Controller Interface
The minimum input setup and hold times described in Fig-
ure 8-3 (legend C and D) define the smallest acceptable
sampling window during which a synchronous input signal
must be stable to ensure correct operation.
tx
VOH
VOHD
SDCLK_OUT
VREF
SDCLK[3:0]
VOLD
VOL
A
Max
B
Min
VOH
Valid Output n
Valid Output n+1
VREF
OUTPUTS
VOL
tx
VIH
VIL
VIHD
VILD
VREF
SDCLK_IN
INPUTS
D
C
V
IH
VREF
VIL
Legend: A = Maximum Output Delay
B = Minimum Output Delay
C = Minimum Input Setup
D = Minimum Input Hold
Figure 8-3. Memory Controller Drive Level and Measurement Points for Switching Characters
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Electrical Specifications (Continued)
Table 8-11. Memory Controller Timing Parameters
Symbol
Parameter
Min
-3.0 + (x * y)
-3.2 + (x * y)
-2.2 + (x * y)
1.3
Max
Unit
ns
Control output1,2 Valid from SDCLK[3:0]
t1
t2
t3
t4
t5
t6
t7
0.1 + (x * y)
0.1 + (x * y)
0.7 + (x * y)
MA[12:0], BA[1.0] Output2 valid from SDCLK[3:0]
ns
MD[63.0] output2 valid from SDCLK[3:0]
MD[63.0] read data in setup to SDCLK_IN
ns
ns
MD[63:0] read data hold to SDCLK_IN
SDCLK[3:0], SDCLK_OUT cycle time
2.0
ns
8.3
13.5
2
ns
SDCLK[3:0], SDCLK_OUT fall/rise time between
ns
(VOLD-VOHD
)
t9
SDCLK_IN fall/rise time between (VILD-VIHD
SDCLK[3:0], SDCLK_OUT high time
SDCLK[3:0], SDCLK_OUT low time
)
2
ns
t10
t11
3.0
2.5)
1. Control output includes all the following signals: RASA#, CASA#, WEA#, CKEA, DQM[7:0], and CS[1:0]#.
Load = 50 pF, VCORE = 1.8V, VIO = 3.3V, @25oC.
2. Use the Min/Max equations [value+(x * y)]to calculate the actual value.
x is the shift value which is applied to the SHFTSDCLK field, and y is 0.45 the core clock period.
Note that the SHFTSDCLK field = GX_BASE+Memory Offset 8404h[5:3]. Refer to the GX1 Processor Series Datasheet
for more information.
For example, for a 266 MHz SC1200/SC1201 running an 88.7 MHz SDRAM clock, with a shift value of 3:
t1 Min = -3 + (3 * (3.76 * 0.45)) = 2.08 ns
t1 Max = 0.1 + (3 * (3.76 * 0.45)) = 5.18 ns
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t6
t10
t1, t2, t3
t11
VOHD
VOLD
VREF
SDCLK[3:0]
t7
t7
Control Output, MA[12:0]
BA[1:0], MD[63:0]
VREF
Figure 8-4. Memory Controller Output Valid Timing Diagram
VIHD
VREF
VILD
t9
SDCLK_IN
t9
t4
t5
t5
t4
MD[63:0]
Data Valid
Data Valid
Read Data In
Figure 8-5. Read Data In Setup and Hold Timing Diagram
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Electrical Specifications (Continued)
8.3.2 Video Port (VP) Interface
Table 8-12. Video Input Port Timing Parameters
Symbol
tVP_C
Parameter
Min
18
6
Max
Unit
ns
Comments
VPCKIN cycle time
tVP_S
Video Port input setup time before VPCKIN rising
edge
ns
tVP_H
Video Port input hold time after VPCKIN Rising
edge
0
-
ns
1
VPCKIN fall/rise time
VPCKIN duty cycle
2
ns
%
tVPCK_FR
tVPCK_D
35/65
1. Guaranteed by characterization.
tVP_C
VIHD
VPCKIN
VREF
VILD
tPCK_FR
tPCK_FR
tVP_S
tVP_H
VPD[7:0]
Figure 8-6. Video Input Port Timing Diagram
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Table 8-13. Video Output Port Timing Parameters
Symbol
tVP_C
Parameter
Min
Max
38
Unit
ns
Comments
VOPCK cycle time
36
tVP_V
Video Port output data valid after VOPCK rising
edge
15
ns
tVP_H
Video Port output data hold after VOPCK rising
edge
0
ns
1
VOPCK fall/rise time, CL = 40 pF
VOPCK duty cycle
3.5
ns
%
tVPCK_FR
tVPCK
40/60
1. Guaranteed by characterization.
tVP_C
VOHD
VOPCK
VOLD
tVPCK_FR
tVPCK_FR
tVP_V
tVP_H
VOP[7:0]
Figure 8-7. Video Output Port Timing Diagram
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Electrical Specifications (Continued)
8.3.3 CRT and TFT Interface
Table 8-14 and Figure 8-8 describe the timing of the digital
CRT interface of the SC1200/SC1201. All measurement
points in this table are identical to the voltage measure-
ment levels described in Table 8-10 on page 382.
Note that signals DDC_SCL and DDC_SDA of the CRT
interface are compliant with standard ACCESS.bus timing
and are controlled by software.
Table 8-14. TFT Timing Parameters
Min
Symbol
Parameter
Max
Unit
Comments
tOV
TFTD[17:0], TFTDE valid time after TFTDCK rising
edge (multiplexed on IDE)
0
8
ns
tOV
TFTD[17:0], TFTDE valid time after TFTDCK rising
edge (multiplexed on Parallel Port)
0
4
3
ns
ns
TFTDCK rise/fall time1 between 0.8V and 2.0V
TFTDCK period time (multiplexed on IDE)
TFTDCK period time (muxed on Parallel Port)
TFTDCK duty cycle
tCLK_RF
tCLK_P
tCLK_P
tCLK_D
25
ns
ns
%
12.5
40/60
1. Guaranteed by characterization
tCLK_P
tOV
TFTDCK
tCLK_RF
TFTD[17:0]
TFTDE
Figure 8-8. TFT Timing Diagram
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1
Table 8-15. CRT VESA Compatible DAC (RED, GREEN, and BLUE Outputs)
Symbol
Parameter
Min
Max
Unit
Comments
VFR
Full range output voltage
0.6
0.72
V
SETRES = 470
RL = 37.5
Digital input = FFh
IFR
Full range output current
16
19.2
mA
SETRES = 470
RL = 37.5
Digital input = FFh
CL = 40 pF
Integral linearity error2
Differential linearity error3
Full-scale settling time4
INL
DNL
tST
tR
±1
±1
10
4
LSB
LSB
ns
Rise time5
ns
DDM
COUT
DAC to DAC matching
Max output capacitance
5
%
15
pF
Power supply rejection ratio6
PSRR
3.5
%
At 0 to 1 MHz
1. Black level = Blank level = 0 mA, 0V.
2. The maximum difference between the ideal (straight) conversion line and the actual conversion curve.
3. The maximum difference between the ideal step size (1 LSB) and any actual step size.
4. The input changes from 00h to FFh. The time from output voltage at 50% of step change to output settling (within an
error of ±1 LSB) is the full-scale settling time.
5. The input changes from 00h to FFh. The output changes from 10% to 90%.
6. AVCCRT changes within the range of 3V to 3.6V. Output voltage is measured for peak-to-peak maximum change. PSSR
is the ratio of the measurement of output at AVCCRT = 3.3V.
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Electrical Specifications (Continued)
8.3.4 TV Interface
Table 8-16. TV DAC (4 Outputs, CVBS, SVY/TVR, SVC/TVB, CVBS/TVG)
Symbol
Parameter
Min
Max
Unit
Comments
RES
VFR
DAC Resolution
10
bits
IRE
Full range output voltage
182
TVRSET to GND = 1140Ω
RL = 37.5
Digital input = 3FFh
IFR
Full range output current
Integral linearity error1
32.9
36.4
mA
TVRSET to GND = 1140Ω
RL = 37.5
Digital input = 3FFh
Typically 1.235V
INL
±1.5
±1.5
LSB
LSB
Differential linearity error2
Internal reference voltage
Gain Error
DNL
TVREF
Gain Error
DDM
1.17
1.29
±5
V
%
DAC to DAC matching
Output impedance
2.5
15
%
ROUT
KΩ
COUT
K
Output capacitance
30
32
pF
IOUT = 0
DAC constant3
Total Noise4
NT
-55
dB
1. The maximum difference between the ideal (straight) conversion line and the actual conversion curve.
2. The maximum difference between the ideal step size (1 LSB) and any actual step size.
3. IOUT (mA) = K x TVREF (V) / TVRSET (Ω).
4. Not tested.
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8.3.5 ACCESS.bus Interface
The following tables describes the timing for all
ACCESS.bus signals.
Notes: 1) All ACCESS.bus timing is not 100% tested.
2) In this table tCLK = 1/24MHz = 41.7 ns.
Table 8-17. ACCESS.bus Input Timing Parameters
Min Max Unit Comments
Symbol
Parameter
tBUFi
Bus free time between
Stop and Start condition
tSCLhigho
tCSTOsi
tCSTRhi
tCSTRsi
tDHCsi
tDLCsi
tSCLfi
AB1C/AB2C setup time
AB1C/AB2C hold time
AB1C/AB2C setup time
Data high setup time
Data low setup time
8 * tCLK - tSCLri
8 * tCLK - tSCLri
8 * tCLK - tSCLri
2 * tCLK
Before Stop condition
After Start condition
Before Start condition
Before AB1C/AB2C rising edge
Before AB1C/AB2C rising edge
2 * tCLK
AB1D/AB2D fall time
AB1D/AB2D rise time
AB1C/AB2C low time
AB1C/AB2C high time
AB1D/AB2D fall time
AB1D/AB2D rise time
AB1D/AB2D hold time
AB1D/AB2D setup time
300
1
ns
tSCLri
µs
tSCLlowi
tSCLhighi
tSDAfi
16 * tCLK
16 * tCLK
After AB1C/AB2C falling edge
After AB1C/AB2C rising edge
300
1
ns
tSDAri
µs
tSDAhi
tSDAsi
0
After AB1C/AB2C falling edge
Before AB1C/AB2C rising edge
2 * tCLK
Table 8-18. ACCESS.bus Output Timing Parameters
Symbol
tSCLhigho
tSCLlowo
tBUFo
Parameter
Min
Max
Unit
Comments
After AB1C/AB2C rising edge1
After AB1C/AB2C falling edge
AB1C/AB2C high time
AB1C/AB2C low time
K * tCLK - 1 µs
K * tCLK - 1 µs
2
Bus free time between
Stop and Start condition
1
µs
tSCLhigho
2
tCSTOso
tCSTRho
tCSTRso
tDHCso
AB1C/AB2C setup time
AB1C/AB2C hold time
AB1C/AB2C setup time
Data high setup time
1
1
1
1
µs
µs
µs
µs
Before Stop condition
After Start condition
tSCLhigho
2
tSCLhigho
2
Before Start condition
Before AB1C/AB2C rising edge
tSCLhigho
2
tSCLhigho
- tSDAro
2
tDLCso
Data low setup time
1
µs
Before AB1C/AB2C rising edge
tSCLhigho
- tSDAfo
tSCLfo
tSCLro
AB1D/AB2D signal fall
time
300
1
ns
AB1D/AB2D signal rise
time
µs
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Table 8-18. ACCESS.bus Output Timing Parameters (Continued)
Symbol
Parameter
Min
Max
Unit
Comments
tSDAfo
AB1D/AB2D signal fall
time
300
ns
tSDAro
AB1D/AB2D signal rise
time
1
µs
tSDAho
tSDAvo
AB1D/AB2D hold time
AB1D/AB2D valid time
7 * tCLK - tSCLfo
After AB1C/AB2C falling edge
After AB1C/AB2C falling edge
7 * tCLK + tRD
1. K is determined by bits [7:1] of the ACBCTL2 register (LDN 05h/06h, Offset 05h).
2. This value depends on the signal capacitance and the pull-up value of the relevant pin.
0.7VIO
0.3VIO
0.7VIO
0.3VIO
AB1D
AB2D
tSDAr
tSDAf
0.7VIO
0.3VIO
0.7VIO
0.3VIO
AB1C
AB2C
tSCLr
Figure 8-9. ACB Signals: Rising and Falling Timing Diagram
tSCLf
Stop Condition
Start Condition
AB1D
AB2D
tDLCs
tDLCo
AB1C
AB2C
tCSTOsi
tCSTOso
tBUFi
tBUFo
tCSTRhi
tCSTRho
Figure 8-10. ACB Start and Stop Condition Timing Diagram
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Start Condition
AB1D
AB2D
AB1C
AB2C
tDHCsi
tDHCso
tCSTRsi
tCSTRso
tCSTRhi
tCSTRho
Figure 8-11. ACB Start Condition TIming Diagram
AB1D
AB2D
tSDAhi
tSDAho
tSDAsi
tSDAso
AB1C
AB2C
tSCLhighi
tSCLhigho
tSCLlowi
tSCLlowo
tSDAvo
tSDAho
Figure 8-12. ACB Data Bit Timing Diagram
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Electrical Specifications (Continued)
8.3.6 PCI Bus
The SC1200/SC1201 is compliant with PCI Bus Rev. 2.1
specifications. Relevant information from the PCI Bus
specifications is provided below.
All parameters in Table 8-19 are not 100% tested. The
parameters in this table are further described in Figure 8-
14.
Table 8-19. PCI AC Specifications
Min Max
Symbol
Parameter
Unit
mA
mA
Comments
IOH(AC)1, 2
Switching Current
High
-12VIO
0 < VOUT ≤ 0.3VIO
0.3VIO < VOUT < 0.9VIO
0.7VIO < VOUT < VIO
-17.1(VIO-VOUT
)
Equation A
(Figure 8-14)
Test Point2
-32VIO
mA
mA
mA
VOUT = 0.7VIO
IOL(AC)1
Switching Current
Low
16VIO
VIO > VOUT ≥ 0.6VIO
1
26.7VOUT
0.6VIO > VOUT > 0.1VIO
0.18VIO>VOUT>01 2
Equation B
(Figure 8-14)
,
Test Point2
38VIO
mA
mA
VOUT = 0.18VIO
ICL
Low Clamp Current
-25+(VIN+1)/0.015
25+(VIN-VIO-1)/0.015
1
-3 < VIN < -1
ICH
High Clamp Current
mA
VIO+4 > VIN > VIO+1
0.2VIO - 0.6VIO Load
3
Output Rise Slew
Rate
4
4
V/ns
SLEWR
3
Output Fall Slew Rate
1
V/ns
0.6VIO - 0.2VIO Load
SLEWF
1. Refer to the V/I curves in Figure 8-14. This specification does not apply to PCICLK0, PCICLK1, and PCIRST# which
are system outputs.
2. Maximum current requirements are met when drivers pull beyond the first step voltage. Equations which define these
maximum values (A and B) are provided with relevant diagrams in Figure 8-14. These maximum values are guaranteed
by design.
3. Rise slew rate does not apply to open-drain outputs. This parameter is interpreted as the cumulative edge rate across
the specified range, according to the test circuit in Figure 8-13.
Pin
0.5" max.
Output
Buffer
VCC
1 KΩ
10 pF
1 KΩ
Figure 8-13. Testing Setup for PCI Slew Rate and Minimum Timing
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Output Voltage
Output Voltage
Volts
Volts
Pull-Up
Pull-Down
VIO
Test Point
AC
Drive Point
0.9
VIO
0.6
VIO
0.5V
DC
Drive Point
IO
DC
Drive Point
0.3
VIO
AC
Drive Point
0.1
VIO
Test Point
I
OH mA
I
OL mA
-48VIO
1.5
-12VIO
Equation A
16VIO
Equation B
-0.5
64VIO
IOH = (98.0/VIO)*(VOUT-VIO)*(VOUT+0.4VIO)
for VIO>VOUT>0.7VIO
IOL = (256/VIO)*VOUT*(VIO-VOUT
)
for 0V<VOUT<0.18VIO
Figure 8-14. V/I Curves for PCI Output Signals
Table 8-20. PCI Clock Parameters
Symbol
tCYC
Parameter
Min
30
11
11
1
Max
Unit
ns
Comments
PCICLK Cycle time1
PCICLK High time2
PCICLK Low time2
PCICLK Slew Rate3
PCIRST# Slew Rate4
tHIGH
ns
tLOW
ns
PCICLKsr
PCIRSTsr
4
-
V/ns
mV/ns
50
1. Clock frequency is between nominal DC and 33 MHz. Device operational parameters at frequencies under 16 MHz are
not 100% tested. The clock can only be stopped in a low state.
2. Guaranteed by characterization.
3. Slew rate must be met across the minimum peak-to-peak portion of the clock waveform (see Figure 8-15).
4. The minimum PCIRST# slew rate applies only to the rising (de-assertion) edge of the reset signal. See Figure 8-19
for PCIRST# timing.
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0.6VIO
0.5 VIO
0.4 VIO
0.3 VIO
0.4 VIO, p-to-p
(minimum)
PCICLK
0.2VIO
tLOW
tHIGH
tCYC
Figure 8-15. PCICLK Timing and Measurement Points
Table 8-21. PCI Timing Parameters
Symbol
tVAL
VAL(ptp)
Parameter
Min
2
Max
11
9
Unit
ns
Comments
PCICLK to Signal Valid Delay1,2 (on the bus)
PCICLK to Signal Valid Delay1,2 (GNT#)
Float to Active Delay1,3
t
2
ns
tON
2
ns
Active to Float Delay1,3
tOFF
28
ns
Input Setup Time to PCICLK4 (on the bus)
Input Setup Time to PCICLK4 (REQ#)
Input Hold Time from PCICLK4
tSU
7
6
ns
tSU(ptp)
tH
ns
0
ns
PCIRST# Active Time After Power Stable5,3
PCIRST# Active Time After PCICLK Stable5,3
PCIRST# Active to Output Float Delay3,5,6
tRST
1
ms
µs
tRST-CLK
tRST-OFF
100
40
ns
1. See the timing measurement conditions in Figure 8-17.
2. Minimum times are evaluated with same load used for slew rate measurement (as shown in note 3 of Table ); maximum
times are evaluated with the load circuits shown in Figure 8-16, for high-going and low-going edges respectively.
3. Not 100% tested.
4. See the timing measurement conditions in Figure 8-18.
5. PCIRST# is asserted and de-asserted asynchronously with respect to PCICLK (see Figure 8-19).
6. All output drivers are asynchronously floated when PCIRST# is active.
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Electrical Specifications (Continued)
tVAL (Max) Rising Edge
tVAL (Max) Falling Edge
0.5" max.
0.5" max.
Pin
Output
Buffer
Output
Buffer
VCC
25 Ω
10 pF
25 Ω
10 pF
Figure 8-16. Load Circuits for PCI Maximum Time Measurements
8.3.6.1 Measurement and Test Conditions
Table 8-22. Measurement Condition Parameters
Symbol
Value
Unit
1
0.6 VIO
V
V
VTH
1
0.2 VIO
VTL
VTEST
0.4 VIO
0.285 VIO
0.615 VIO
0.4 VIO
V
V
V
V
VSTEP (Rising Edge)
VSTEP (Falling Edge)
2
VMAX
Input Signal Edge Rate
1
V/ns
1. The input test is performed with 0.1 VIO of overdrive. Timing parameters must not exceed this overdrive.
2. VMAX specifies the maximum peak-to-peak waveform allowed for measuring input timing.
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Electrical Specifications (Continued)
VTH
PCICLK
VTEST
VTL
tVAL
Output
Delay
VSTEP
Output Current ≤ Leakage Current
TRI-STATE
Output
tON
tOFF
Figure 8-17. PCI Output Timing Measurement Conditions
VTH
VTL
PCICLK
VTEST
tSU
tH
VTH
VTEST
Input Valid
VTEST
VMAX
Input
VTL
Figure 8-18. PCI Input Timing Measurement Conditions
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Electrical Specifications (Continued)
POWER
VIO
tFAIL
PCICLK
100 ms (typ)
POR#
) (
tRST
PCIRST#
) (
tRST-CLK
tRST-OFF
PCI
Signals
TRI_STATE
Note: The value of tFAIL is 500 ns (maximum) from the power rail which exceeds specified tolerance by more than
500 mV.
Figure 8-19. PCI Reset Timing
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Electrical Specifications (Continued)
8.3.7 Sub-ISA Interface
All output timing is guaranteed for 50 pF load, unless other-
wise specified.
The ISA Clock divisor (defined in F0 Index 50h[2:0] of the
Core Logic module) is 011.
Table 8-23. Sub-ISA Timing Parameters
Bus
Width
(Bits)
Min
(ns)
Max
(ns)
Symbol
Parameter
Type
Figure Comments
tRD1
MEMR#/DOCR#/RD#/TRDE# Read
active pulse width FE to RE
16
16
16
8
M
225
105
160
520
160
103
163
163
225
105
160
520
160
103
163
8-20
8-20
8-20
8-20
8-20
8-20
8-20
8-20
8-21
8-21
8-21
8-21
8-21
8-21
8-21
8-21
Standard
tRD2
MEMR#/DOCR#/RD#/TRDE# Read
active pulse width FE to RE
M
I/O
Zero wait state
Standard
tRD3
IOR#/RD#/TRDE# Read active pulse
width FE to RE
tRD4
IOR#/MEMR#/DOCR#/RD#/TRDE#
Read active pulse width FE to RE
M, I/O
M, I/O
M
Standard
tRD5
IOR#/MEMR#/DOCR#/RD#/TRDE#
Read active pulse width FE to RE
8
Zero wait state
tRCU1
tRCU2
tRCU3
tWR1
tWR2
tWR3
tWR4
tWR5
tWCU1
tWCU2
MEMR#/DOCR#/RD#/TRDE#
inactive pulse width
16
8
MEMR#/DOCR#/RD#/TRDE#
inactive pulse width
M
IOR#/RD#/TRDE# inactive pulse
width
8, 16
16
16
16
8
I/O
MEMW#/WR# Write active pulse
width FE to RE
M
Standard
MEMW#/DOCW#/WR# Write active
pulse width FE to RE
M
Zero wait state
Standard
IOW#/WR# Write active pulse width
FE to RE
I/O
IOW#/MEMW#/DOCW#/WR# Write
active pulse width FE to RE
M, I/O
M, I/O
M
Standard
IOW#/MEMW#/DOCW#/WR# Write
active pulse width FE to RE
8
Zero wait state
MEMW#/WR#/DOCW# inactive pulse
width
16
8
MEMW#/WR#/DOCW# inactive pulse
width
M
tWCU3
tRDYH
IOW#/WR# inactive pulse width
8, 16
8, 16
I/O
163
120
IOR#/MEMR#/RD#/DOCR#/IOW#/
MEMW#/WR#/DOCW# Hold after
IOCHRDY RE
M, I/O
8-20
8-21
tRDYA1
IOCHRDY valid after IOR#/MEMR#/
RD#/DOCR#/IOW#/MEMW#/WR#/
DOCW# FE
16
M, I/O
78
8-20
8-21
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Electrical Specifications (Continued)
Table 8-23. Sub-ISA Timing Parameters (Continued)
Bus
Width
(Bits)
Min
(ns)
Max
(ns)
Symbol
Parameter
Type
Figure Comments
tRDYA2
IOCHRDY valid after IOR#/MEMR#/
RD#/DOCR#/IOW#/MEMW#/WR#/
DOCW# FE
8
M, I/O
366
8-20
8-21
tIOCSA
tIOCSH
tAR1
tAR2
tAR3
tRA
IOCS[1:0]#/DOCS#/ROMCS# driven
active from A[23:0] valid
8, 16
8, 16
16
M, I/O
M, I/O
M
34
8-20
8-21
IOCS[1:0]#/DOCS#/ROMCS# valid
Hold after A[23:0] invalid
0
34
100
100
25
24
0
8-20
8-21
A[23:0]/BHE# valid before
MEMR#/DOCR# active
8-20
8-20
8-20
8-20
8-20
8-20
8-20
8-21
8-21
8-21
8-21
8-21
8-21
8-21
8-21
8-21
8-21
8-20
A[23:0]/BHE# valid before IOR#
active
16
I/O
A[23:0]/BHE# valid before
MEMR#/DOCR#/IOR# active
8
M, I/O
M, I/O
M, I/O
M, I/O
M, I/O
M
A[23:0]/BHE# valid Hold after
MEMR#/DOCR#/IOR# inactive
8, 16
8, 16
8, 16
8, 16
16
tRVDS
tRDH
tHZ
Read data D[15:0] valid setup before
MEMR#/DOCR#/IOR# inactive
Read data D[15:0] valid Hold after
MEMR#/DOCR#/IOR# inactive
Read data floating after
MEMR#/DOCR#/IOR# inactive
41
tAW1
tAW2
tAW3
tWA
A[23:0]/BHE# valid before
MEMW#/DOCW# active
34
100
100
25
A[23:0]/BHE# valid before IOW#
active
16
I/O
A[23:0]/BHE# valid before
MEMW#/DOCW#/IOW# active
8
M, I/O
M, I/O
M
A[23:0]/BHE# valid Hold after
MEMW#/DOCW#/IOW# invalid
8, 16
8, 16
8
tDV1
tDV2
tDV3
tWTR
tDH
Write data D[15:0] valid after
MEMW#/DOCW# active
40
Write data D[15:0] valid after IOW#
active
I/O
40
Write data D[15:0] valid after IOW#
active
16
I/O
-23
20
TRDE# inactive after
MEMW#/DOCW#/IOW# inactive
8, 16
8, 16
8, 16
8, 16
M, I/O
M, I/O
M, I/O
M, I/O
Write data D[15:0] after
MEMW#/DOCW#/IOW# inactive
45
tDF
Write data D[15:0] goes TRI-STATE
after MEMW#/DOCW#/IOW# inactive
105
tWDAR
Write data D[15:0] after read
MEMR#/DOCR#/IOR#
41
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Electrical Specifications (Continued)
tIOCSA
tIOCSH
ROMCS#/DOCCS#
IOCS[1:0]#
Valid
tRDx
Valid
A[23:0]/BHE#
tARx
tRCUx
IOR#/RD#/TRDE#
MEMR#/DOCR#
tRA
IOW#/WR#
MEMW#/DOCW#
tRVDS
Valid Data
tRDH
tHZ
D[15:0]
(Read)
tWDAR
D[15:0]
(Write)
IOCHRDY
tRDYAx
tRDYH
Note: x indicates a numeric index for the relevant symbol.
Figure 8-20. Sub-ISA Read Operation Timing Diagram
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Electrical Specifications (Continued)
tIOCSA
tIOCSH
DOCCS#/ROMCS#
IOCS[1:0]#
A[23:0]/BHE#
Valid
Valid
tAWx
tWRx
tWCUx
IOW#/WR#
MEMW#/DOCW#
tWA
TRDE#
D[15:0]
tDVx
tWTR
Valid Data
tDH
tDF
IOCHRDY
tRDYAx
tRDYH
IOR#/RD#
MEMR#/DOCR#
Note: x indicates a numeric index for the relevant symbol.
Figure 8-21. Sub-ISA Write Operation Timing Diagram
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Electrical Specifications (Continued)
8.3.8 LPC Interface
Table 8-24. LPC and SERIRQ
Symbol
tVAL
tON
Parameter
Min
0
Max
Unit
ns
Comments
Output Valid delay
Float to Active delay
Active to Float delay
Input Setup time
Input Hold time
17
After PCICLK rising edge
After PCICLK rising edge
After PCICLK rising edge
Before PCICLK rising edge
After PCICLK rising edge
2
ns
tOFF
tSU
28
ns
7
0
ns
tHI
ns
PCICLK
tVAL
tON
LPC Signals/
SERIRQ
tOFF
Figure 8-22. LPC Output Timing Diagram
PCICLK
tSU
tHI
LPC Signals/
SERIRQ
Input
Valid
Figure 8-23. LPC Input Timing Diagram
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8.3.9 IDE Interface Timing
Table 8-25. IDE General Timing Parameters
Symbol
Parameter
Min
Max
Unit
Comments
tIDE_FALL
Fall time of all IDE signals.
From 0.9VIO to 0.1VIO
5
ns
CL = 40 pF
tIDE_RISE
Rise time of all IDE signals.
From 0.1VIO to 0.9VIO
5
ns
µs
CL = 40 pF
tIDE_RST_PW IDE_RST# pulse width
25
tIDE_RST_PW
IDE_RST#
Figure 8-24. IDE Reset Timing Diagram
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Electrical Specifications (Continued)
Table 8-26. IDE Register Transfer to/from Device Timing Parameters
Mode 0
(ns)
Mode 1
(ns)
Mode2
(ns)
Mode3 Mode4
Symbol
Parameter
(ns)
180
30
(ns)
120
25
Cycle time1 (min)
t0
t1
600
70
383
50
240
30
Address valid to IDE_IOR[0:1]#/ IDE_IOW[0:1]#
setup (min)
IDE_IOR[0:1]#/IDE_IOW[0:1]# pulse width 8-bit1
(min)
t2
290
-
290
-
290
-
80
70
70
25
IDE_IOR[0:1]#/IDE_IOW[0:1]# recovery time1
(min)
t2i
t3
IDE_IOW[0:1]# data setup (min)
IDE_IOW[0:1]# data hold (min)
IDE_IOR[0:1]# data setup (min)
IDE_IOR[0:1]# data hold (min)
60
30
50
5
45
20
35
5
30
15
20
5
30
10
20
5
20
10
20
5
t4
t5
t6
IDE_IOR[0:1]# data TRI-STATE2 (max)
t6Z
t9
30
20
30
15
30
10
30
10
30
10
IDE_IOR[0:1]#/IDE_IOW[0:1]# to address valid
hold (min)
tRD
Read Data Valid to IDE_IORDY[0:1] active (if
IDE_IORDY[0:1] initially low after tA (min)
0
0
0
0
0
IDE_IORDY[0:1] Setup time3
tA
tB
tC
35
1250
5
35
1250
5
35
1250
5
35
1250
5
35
1250
5
IDE_IORDY[0:1] Pulse Width (max)
IDE_IORDY[0:1] assertion to release (max)
1. t0 is the minimum total cycle time, t2 is the minimum command active time, and t2i is the minimum command recovery
time or command inactive time. The actual cycle time equals the sum of the command active time and the command
inactive time. The three timing requirements of t0, t2, and t2i are met. The minimum total cycle time requirements is
greater than the sum of t2 and t2i. (This means that a host implementation can lengthen t2 and/or t2i to ensure that t0 is
equal to or greater than the value reported in the device’s IDENTIFY DEVICE data.)
2. This parameter specifies the time from the rising edge of IDE_IOR[0:1]# to the time that the data bus is no longer driven
by the device (TRI-STATE).
3. The delay from the activation of IDE_IOR[0:1]# or IDE_IOW[0:1]# until the state of IDE_IORDY[0,1] is first sampled. If
IDE_IORDY[0:1] is inactive, then the host waits until IDE_IORDY[0:1] is active before the PIO cycle is completed. If the
device is not driving IDE_IORDY[0:1] negated after activation (tA) of IDE_IOR[0:1]# or IDE_IOW[0:1]#, then t5 is met
and tRD is not applicable. If the device is driving IDE_IORDY[0:1] negated after activation (tA) of IDE_IOR[0:1]# or
IDE_IOW[0:1]#, then tRD is met and t5 is not applicable.
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t0
ADDR valid1
t1
t9
t2
t2i
IDE_IOR0#
IDE_IOW0#
WRITE
IDE_DATA[7:0]
t3
t4
READ
IDE_DATA[7:0]
t5
t6
IDE_IORDY02,3
IDE_IORDY02,4
t6z
tA
tC
tRD
IDE_IORDY02,5
tB
tC
Notes:
1) Device address consists of signals IDE_CS[0:1]# and IDE_ADDR[2:0].
2) Negation of IDE_IORDY0,1 is used to extend the PIO cycle. The determination of whether or not the cycle is to be
extended is made by the host after tA from the assertion of IDE_IOR[0:1]# or IDE_IOW[0:1]#.
3) Device never negates IDE_IORDY[0:1]. Device keeps IDE_IORDY[0:1] released, and no wait is generated.
4) Device negates IDE_IORDY[0:1] before tA but causes IDE_IORDY[0:1] to be asserted before tA. IDE_IORDY[0:1] is
released, and no wait is generated.
5) Device negates IDE_IORDY[0:1] before tA. IDE_IORDY[0:1] is released prior to negation and may be asserted for no
more than 5 ns before release. A wait is generated.
6) The cycle completes after IDE_IORDY[0:1] is reasserted. For cycles where a wait is generated and IDE_IOR[0:1] is
asserted, the device places read data on IDE_DATA[15:0] for tRD before asserting IDE_IORDY[0:1].
Figure 8-25. Register Transfer to/from Device Timing Diagram
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Electrical Specifications (Continued)
Table 8-27. IDE PIO Data Transfer to/from Device Timing Parameters
Mode0
(ns)
Mode
1 (ns)
Mode
2 (ns)
Mode
3 (ns)
Mode
4 (ns)
Symbol
Parameter
Cycle time1 (min)
t0
t1
600
70
383
50
240
30
180
30
120
25
Address valid to IDE_IOR[0:1]#/IDE_IOW[0:1]# setup
(min)
IDE_IOR[0:1]#/IDE_IOW[0:1]# 16-bit1 (min)
t2
165
-
125
-
100
-
80
70
30
10
20
5
70
25
20
10
20
5
IDE_IOR[0:1]#/IDE_IOW[0:1]# recovery time1 (min)
IDE_IOW[0:1]# data setup (min)
t2i
t3
60
30
50
5
45
20
35
5
30
15
20
5
t4
IDE_IOW[0:1]# data hold (min)
IDE_IOR[0:1]# data setup (min)
IDE_IOR[0:1]# data hold (min)
t5
t6
IDE_IOR[0:1]# data TRI-STATE2 (max)
t6Z
t9
30
20
30
15
30
10
30
10
30
10
IDE_IOR[0:1]#/IDE_IOW[0:1]# to address valid hold
(min)
tRD
Read Data Valid to IDE_IORDY[0,1] active
(if IDE_IORDY[0:1] initially low after tA) (min)
0
0
0
0
0
IDE_IORDY[0:1] Setup time3
tA
tB
tC
35
1250
5
35
1250
5
35
1250
5
35
1250
5
35
1250
5
IDE_IORDY[0:1] Pulse Width (max)
IDE_IORDY[0:1] assertion to release (max)
1. t0 is the minimum total cycle time, t2 is the minimum command active time, and t2i is the minimum command recovery
time or command inactive time. The actual cycle time equals the sum of the command active time and the command
inactive time. The three timing requirements of t0, t2, and t2i are met. The minimum total cycle time requirement is great-
er than the sum of t2 and t2i. (This means that a host implementation may lengthen t2 and/or t2i to ensure that t0 is equal
to or greater than the value reported in the device’s IDENTIFY DEVICE data.)
2. This parameter specifies the time from the rising edge of IDE_IOR[0:1]# to the time that the data bus is no longer driven
by the device (TRI-STATE).
3. The delay from the activation of IDE_IOR[0:1]# or IDE_IOW[0:1]# until the state of IDE_IORDY[0:1] is first sampled. If
IDE_IORDY[0:1] is inactive, then the host waits until IDE_IORDY[0:1] is active before the PIO cycle is completed. If the
device is not driving IDE_IORDY[0:1] negated after the activation (tA) of IDE_IOR[0:1]# or IDE_IOW[0:1]#, then t5 is
met and tRD is not applicable. If the device is driving IDE_IORDY[0:1] negated after the activation (tA) of IDE_IOR[0:1]#
or IDE_IOW[0:1]#, then tRD is met and t5 is not applicable.
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t0
ADDR valid1
t1
t9
t2
t2i
IDE_IOR0#
IDE_IOW0#
WRITE IDE_DATA[15:0]
t3
t4
READ IDE_DATA[15:0]
t5
t6
IDE_IORDY02,3
IDE_IORDY02,4
t6z
tA
tC
tRD
IDE_IORDY02,5
tB
tC
Notes:
1) Device address consists of signals IDE_CS[0:1]# and IDE_ADDR[2:0].
2) Negation of IDE_IORDY[0:1] is used to extend the PIO cycle. The determination of whether or not the cycle is to be
extended is made by the host after tA from the assertion of IDE_IOR[0:1]# or IDE_IOW[0:1]#.
3) Device never negates IDE_IORDY[0:1]. Devices keep IDE_IORDY[0:1] released, and no wait is generated.
4) Device negates IDE_IORDY[0:1] before tA but causes IDE_IORDY[0:1] to be asserted before tA. IDE_IORDY[0:1] is
released, and no wait is generated.
5) Device negates IDE_IORDY[0:1] before tA. IDE_IORDY[0:1] is released prior to negation and may be asserted for no
more than 5 ns before release. A wait is generated.
6) The cycle completes after IDE_IORDY[0:1] is reasserted. For cycles where a wait is generated and IDE_IOR[0:1]# is
asserted, the device places read data on IDE_DATA[15:0] for tRD before asserting IDE_IORDY[0:1].
Figure 8-26. PIO Data Transfer to/from Device Timing Diagram
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Electrical Specifications (Continued)
Table 8-28. IDE Multiword DMA Data Transfer Timing Parameters
Mode 0
(ns)
Mode 1
(ns)
Mode 2
(ns)
Symbol
t0
Parameter
Cycle time1 (min)
480
215
150
5
150
80
60
5
120
70
50
5
tD
IDE_IOR[0:1]#/IDE_IOW[0:1]# (min)
tE
IDE_IOR[0:1]# data access (max)
tF
IDE_IOR[0:1]# data hold (min)
tG
IDE_IOW[0:1]#/IDE_IOW[0:1]# data setup (min)
IDE_IOW[0:1]# data hold (min)
100
20
30
15
0
20
10
0
tH
tI
IDE_DACK[0:1]# to IDE_IOR[0:1]#/IDE_IOW[0:1]# setup (min)
IDE_IOR[0:1]#/IDE_IOW[0:1]# to IDE_DACK[0:1]# hold (min)
IDE_IOR[0:1]# negated pulse width (min)
IDE_IOW[0:1]# negated pulse width (min)
IDE_IOR[0:1]# to IDE_DREQ[0:1] delay (max)
IDE_IOW[0:1]# to IDE_DREQ0,1 delay (max)
IDE_CS[0:1]# valid to IDE_IOR[0:1]#/IDE_IOW[0:1]# (min)
IDE_CS[0:1]# hold
0
tJ
20
5
5
tKR
tKW
tLR
tLW
tM
50
50
50
40
40
30
10
25
25
25
35
35
25
10
25
215
120
40
50
tN
15
tZ
IDE_DACK[0:1]# to TRI-STATE
20
1. t0 is the minimum total cycle time, tD is the minimum command active time, and tKR or tKW is the minimum command
recovery time or command inactive time. The actual cycle time equals the sum of the command active time and the
command inactive time. The three timing requirements of t0, tD and tKR/KW, are met. The minimum total cycle time re-
quirement t0 is greater than the sum of tD and tKR/KW. (This means that a host implementation can lengthen tD and/or
tKR/KW to ensure that t0 is equal to or greater than the value reported in the device’s IDENTIFY DEVICE data.)
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Electrical Specifications (Continued)
IDE_CS[1:0]#
tM
tN
t0
IDE_DREQ0
IDE_DACK0#
tL
tI
tj
tD
tK
IDE_IOR0#
IDE_IOW0#
tE
tZ
IDE_DATA[15:0]
tF
tG
IDE_DATA[15:0]
tG
tH
Notes:
1) For Multiword DMA transfers, the Device may negate IDE_DREQ[0:1] within the tL specified time once IDE_DACK[0:1
is asserted, and reassert it again at a later time to resume the DMA operation. Alternatively, if the device is able to co
tinue the transfer of data, the device may leave IDE_DREQ[0:1] asserted and wait for the host to reasse
IDE_DACK[0:1]#.
2) This signal can be negated by the host to Suspend the DMA transfer in process.
Figure 8-27. Multiword DMA Data Transfer Timing Diagram
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Electrical Specifications (Continued)
Table 8-29. IDE UltraDMA Data Burst Timing Parameters
Mode 0 (ns) Mode 1 (ns)
Mode 2 (ns)
Symbol
Parameter
Min
Max
Min
Max
Min
Max
t2CYC
Typical sustained average two cycle time
240
235
160
156
120
117
Two cycle time allowing for clock variations (from rising
edge to next rising edge or from falling edge to next falling
edge of STROBE)
tCYC
Cycle time allowing for asymmetry and clock variations
(from STROBE edge to STROBE edge)
114
75
55
tDS
Data setup time (at recipient)
Data hold time (at recipient)
15
5
10
5
7
5
tDH
tDVS
Data valid setup time at sender (from data bus being valid
until STROBE edge)
70
48
34
tDVH
tFS
Data valid hold time at sender (from STROBE edge until
data may become invalid)
6
0
6
0
6
0
First STROBE time (for device to first negate
IDE_IRDY[0:1] (DSTROBE[0:1]) from IDE_IOW[0:1]#
(STOP[0:1]) during a data in burst)
230
150
200
150
170
150
Limited interlock time1
tLI
0
20
0
0
20
0
0
20
0
Interlock time with minimum1
Unlimited interlock time1
tMLI
tUI
tAZ
Maximum time allowed for output drivers to release (from
being asserted or negated)
10
10
10
tZAH
tZAD
tENV
Minimum delay time required for output drivers to assert or
negate (from released state)
20
0
20
0
20
0
Envelope time (from IDE_DACK[0:1]# to IDE_IOW[0:1]#
(STOP[0:1]) and IDE_IOR[0:1]# (HDMARDY[0:1]#) during
data out burst initiation)
20
70
50
75
20
70
30
60
20
70
20
50
tSR
STROBE to DMARDY time (if DMARDY# is negated before
this long after STROBE edge, the recipient shall receive no
more than one additional data WORD)
tRFS
Ready-to-final-STROBE time (no STROBE edges shall be
sent this long after negation of DMARDY#)
tRP
Ready-to-pause time (time that recipient shall wait to ini-
tiate pause after negating DMARDY#)
160
125
100
tIORDYZ
tZIORDY
TACK
TSS
Pull-up time before allowing IDE_IORDY[0:1] to be
released
20
20
20
Minimum time device shall wait before driving
IDE_IORDY[0:1]
0
0
0
Setup and hold times for IDE_DACK[0:1]# (before asser-
tion or negation)
20
50
20
50
20
50
Time from STROBE edge to negation of IDE_DREQ[0:1]
or assertion of IDE_IOW[0:1]# (STOP[0:1]) (when sender
terminates a burst)
1. tUI, tMLI, and tLI indicate sender-to-recipient or recipient-to-sender interlocks, that is, one agent (either sender or recipi-
ent) is waiting for the other agent to respond with a signal before proceeding. tUI is an unlimited interlock with no maxi-
mum time value. tMLI is a limited time-out with a defined minimum. tLI is a limited time-out with a defined maximum.
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Electrical Specifications (Continued)
All timing parameters are measured at the connector of the
device to which the parameter applies. For example, the
sender stops generating STROBE edges tRFS after the
negation of DMARDY. Both STROBE and DMARDY timing
measurements are taken at the connector of the sender.
IDE_REQ0
(device)
tUI
IDE_DACK0#
(host)
tFS
tACK
tENV
IDE_IOW0#
(STOP0)
(host)
tZAD
tENV
tACK
tFS
IDE_IOR0#
(HDMARDY0#)
(host)
tZIORDY
tZAD
IDE_IRDY0 (DSTROBE0)
(device)
tDVS
tDVH
tAZ
IDE_DATA[15:0]
IDE_ADDR[2:0]
IDE_CS[0:1]
tACK
Note: The definitions for the IDE_IOW[0:1]# (STOP[0:1]), IDE_IOR[0:1]# (HDMARDY[0:1]#) and IDE_IRDY[0:1]
(DSTROBE[0:1]) signal lines are not in effect until IDE_REQ[0:1] and IDE_DACK[0:1]# are asserted.
Figure 8-28. Initiating an UltraDMA Data in Burst Timing Diagram
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Electrical Specifications (Continued)
t2CYC
tCYC
tCYC
t2CYC
IDE_IRDY0
(DSTROBE0)
at device
tDVS
tDVS
tDVH
tDVH
tDVH
IDE_DATA[15:0]
at device
IDE_IRDY0
(DSTROBE0)
at host
tDH
tDH
tDS
tDS
tDH
IDE_DATA[15:0]
at host
Note: IDE_DATA[15:0] and IDE_IRDY[0:1] (DSTROBE[0:1]) signals are shown at both the host and the device to empha-
size that cable settling time and cable propagation delay do not allow the data signals to be considered stable at the
host until a certain amount of time after they are driven by the device.
Figure 8-29. Sustained UltraDMA Data In Burst Timing Diagram
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Electrical Specifications (Continued)
IDE_DREQ0
(device)
IDE_DACK0#
(host)
tRP
IDE_IOW0#(STOP0#)
(host)
tSR
IDE_IOR0#(HDMARDY0#)
(host)
tRFS
IDE_IRDY0
(DSTROBE0)
(device)
IDE_DATA[15:0]
(device)
Notes:
1) The host can assert IDE_IOW[0:1]# (STOP[0:1]#) to request termination of the UltraDMA burst no sooner than tRP
after IDE_IOR[0:1]# (HDMARDY[0:1]#) is de-asserted.
2) If the tSR timing is not satisfied, the host may receive up to two additional data WORDs from the device.
Figure 8-30. Host Pausing an UltraDMA Data In Burst Timing Diagram
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Electrical Specifications (Continued)
IDE_DREQ0
(device)
tMLI
IDE_DACK0#
(host)
tACK
tLI
tLI
IDE_IOW0# (STOP0#)
(host)
tACK
tLI
IDE_IOR0# (HDMARDY0#)
(host)
tSS
tIORDZ
IDE_IRDY0
(DSTROBE0)
(device)
tZAH
tDVS
tDVH
tAZ
IDE_DATA[15:0]
(device)
CR
tACK
IDE_CS[0:1]#
IDE_ADDR[2:0]
Note: The definitions for the IDE_IOW[0:1]# (STOP[0:1]#), IDE_IOR[0:1]# (HDMARDY[0:1]#), and IDE_IRDY[0:1]
(DSTROBE[0:1]) signal lines are no longer in effect after IDE_DREQ[0:1] and IDE_DACK[0:1]# are de-asserted.
Figure 8-31. Device Terminating an UltraDMA Data In Burst Timing Diagram
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Electrical Specifications (Continued)
IDE_DREQ0
(device)
tLI
tMLI
IDE_DACK0#
(host)
tACK
tZAH
tRP
tAZ
IDE_IOW0#
(STOP0#)
(host)
tACK
IDE_IOR0#
(HDMARDY0#)
(host)
tLI
tRFS
tMLI
tIORDYZ
IDE_IRDY0
(DSTROBE0)
(device)
tDVS
tDVH
IDE_DATA[15:0]
(device)
CR
tACK
IDE_CS[0:1]#
IDE_ADDR[2:0]
Note: The definitions for the IDE_IOW[0:1]# (STOP[0:1]#), IDE_IOR[0:1]# (HDMARDY[0:1]#), and IDE_IRDY[0:1]
(DSTROBE[0:1]) signal lines are no longer in effect after IDE_DREQ[0:1] and IDE_DACK[0:1] are de-asserted.
Figure 8-32. Host Terminating an UltraDMA Data In Burst Timing Diagram
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Electrical Specifications (Continued)
IDE_DREQ0
tUI
(device)
IDE_DACK0#
(host)
tACK
tENV
IDE_IOW0#
(STOP0#)
(host)
tZIORDY
tLI
tUI
IDE_IORDY0
(DDMARDY0)
(device)
tACK
IDE_IOR0#
(HSTROBE0#)
(host)
tDVH
tDVS
IDE_DATA[15:0]
(device)
tACK
IDE_ADDR[2:0]
IDE_CS[0:1]#
Note: The definitions for the IDE_IOW[0:1]]# (STOP[0:1]#), IDE_IORDY[0:1]# (DDMARDY[0:1]) and IDE_IOR[0:1]#
(HSTROBE[0:1]#) signal lines are not in effect until IDE_DREQ[0:1] and IDE_DACK[0:1]# are asserted.
Figure 8-33. Initiating an UltraDMA Data Out Burst Timing Diagram
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Electrical Specifications (Continued)
t2CYC
tCYC
tCYC
IDE_IOR0#
(HSTROBE0#)
at host
t2CYC
tDVS
tDVS
tDVH
tDVH
tDVH
IDE_DATA[15:0]
at host
IDE_IOR0#
(HSTROBE0#)
at device
tDH
tDH
tDS
tDS
tDH
IDE_DATA[15:0]
at device
Note: IDE_DATA[15:0] and IDE_IOR[0:1]# (HSTROBE[0:1]#) signals are shown at both the device and the host to
emphasize that cable settling time and cable propagation delay do not allow the data signals to be considered sta-
ble at the device until a certain amount of time after they are driven by the device.
Figure 8-34. Sustained UltraDMA Data Out Burst Timing Diagram
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Electrical Specifications (Continued)
tRP
IDE_DREQ0
(device)
IDE_DACK0#
(host)
IDE_IOW0# (STOP0#)
(host)
tSR
IDE_IORDY0# (DDMARDY0#)
(device)
tRFS
IDE_IOR0#
(HSTROBE0#)
(host)
IDE_DATA[15:0]
(host)
Notes:
1) The device can de-assert IDE_DREQ[0:1] to request termination of the UltraDMA burst no sooner than tRP after
IDE_IORDY[0:1]# (DDMARDY[0:1]#) is de-asserted.
2) If the tSR timing is not satisfied, the device may receive up to two additional datawords from the host.
Figure 8-35. Device Pausing an UltraDMA Data Out Burst Timing Diagram
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Electrical Specifications (Continued)
tLI
IDE_DREQ0
(device)
tMLI
IDE_DACK0#
(host)
tACK
tLI
tSS
IDE_IOW0#
(STOP0#)
(host)
tLI
tIORDYZ
IDE_IORDY0#
(DDMARDY0)#
(device)
tACK
IDE_IOR0#
(HSTROBE0#)
(host)
tDVH
tDVS
IDE_DATA[15:0]
(host)
CR
tACK
IDE_ADDR[2:0]
IDE_CS[0:1]#
Note: The definitions for the IDE_IOW[0:1]# (STOP[0:1]#), IDE_IORDY[0,1]# (DDMARDY[0:1]#) and IDE_IOR[0:1]#
(HSTROBE[0:1]#) signal lines are no longer in effect after IDE_DREQ[0:1] and IDE_DACK[0:1]# are de-asserted.
Figure 8-36. Host Terminating an UltraDMA Data Out Burst Timing Diagram
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Electrical Specifications (Continued)
IDE_DREQ0
(device)
IDE_DACK0
(host)
tACK
tLI
tMLI
IDE_IOW0# (STOP0#)
(host)
tIORDZ
tRP
IDE_IORDY0#
(DDMARDY0#)
(device)
tRFS
tLI
tMLI
tACK
IDE_IOR0#
(HSTROBE0#)
(host)
tDVS
tDVH
IDE_DATA[15:0]
(host)
CR
tACK
IDE_CS[0:1]#
IDE_ADDR[2:0]
Note: The definitions for the IDE_IOW[0:1]# (STOP[0:1]#), IDE_IORDY[0:1]# (DDMARDY[0:1]#) and IDE_IOR[0:1]#
(HSTROBE[0:1]#) signal lines are no longer in effect after IDE_DREQ[0:1] and IDE_DACK[0:1]# are de-asserted.
Figure 8-37. Device Terminating an UltraDMA Data Out Burst Timing Diagram
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Electrical Specifications (Continued)
8.3.10 Universal Serial Bus (USB)
Table 8-30. USB Timing Parameters
Symbol
Parameter
Min
Max
Unit
Figure Comments
Full Speed Source1 2
,
tUSB_R1
DPOS_Port1,2,3, DNEG_Port1,2,3
Driver Rise Time
4
4
20
20
ns
ns
8-38
8-38
(Monotonic) from 10% to
90% of the D_Port lines
tUSB_F1
DPOS_Port1,2,3, DNEG_Port1,2,3
Driver Fall Time
(Monotonic) from 90% to
10% of the D_Port lines
tUSB_FRFM Rise/Fall time matching
tUSB_FSDR Full-speed data rate
90
110
%
11.97
12.03
Mbps
Average bit rate 12 Mbps
± 0.25%
tUSB_FSF
tperiod_F
tUSB DOR
tUSB_DJ11
Full-speed frame interval
0.9995 1.0005
ms
ns
W
1.0 ms ± 0.05%
Full-speed period between data bits
Driver-output resistance
83.1
28
83.5
43
Average bit rate 12 Mbps
Steady-state drive
Source differential driver jitter3, 4 for
consecutive transition
–3.5
3.5
ns
8-39
8-39
Source differential driver jitter3, 4 for
paired transitions
tUSB_DJ12
–4.0
4.0
ns
Source EOP width4, 5
tUSB_SE1
tUSB_DE1
tUSB_RJ11
160
–2
175
5
ns
ns
ns
8-39
8-40
8-41
Differential to EOP transition skew4, 5
Receiver data jitter tolerance4 for
consecutive transition
–18.5
18.5
Receiver data jitter tolerance4 for
paired transitions
tUSB_RJ12
–9
9
ns
8-41
Full Speed Receiver EOP Width4
Must reject as EOP5
Must accept as EOP5
tUSB_RE11
tUSB_RE12
40
ns
ns
8-40
8-40
82
Low Speed Source1, 6
3006
tUSB_R2 DPOS_Port1,2,3, DNEG_Port1,2,3
75
75
80
ns
ns
8-38
8-38
(Monotonic) from 10% to
90% of the D_Port lines
Driver Rise Time
3006
120
tUSB_F2
DPOS_Port1,2,3, DNEG_Port1,2,3
Driver Fall Time
(Monotonic) from 90% to
10% of the D_Port lines
tUSB_LRFM Low-speed Rise/Fall time matching
%
tUSB_LSDR
Low-speed data rate
1.4775 1.5225
Mbps
Average bit rate 1.5 Mbps
± 1.5%
tPERIOD_L
Low-speed period
0.657
–75
0.677
75
µs
at 1.5 Mbps
Source differential driver jitter4 for
consecutive transactions
tUSB_DJD21
ns
Host (downstream)
Source differential driver jitter4 for
paired transactions
tUSB_DJD22
–45
–95
45
95
ns
ns
8-39
8-39
Host (downstream)
Source differential driver jitter4 for
consecutive transaction
tUSB_DJU21
Function (downstream)
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Electrical Specifications (Continued)
Table 8-30. USB Timing Parameters (Continued)
Symbol
Parameter
Min
Max
Unit
Figure Comments
Source differential driver jitter4 for
paired transactions
tUSB_DJU22
–150
150
ns
8-39
Function (downstream)
Source EOP width4, 5
tUSB_SE2
tUSB_DE2
tUSB_RJD21
1.25
–40
1.5
100
152
µs
ns
ns
8-40
8-40
8-41
Differential to EOP 5 transition skew
Receiver Data Jitter Tolerance4 for
consecutive transactions
–152
Host (upstream)
Receiver Data Jitter Tolerance4 for
paired transactions
tUSB_RJD22
tUSB_RJU21
tUSB_RJU22
–200
–75
200
75
ns
ns
ns
8-41
8-41
8-41
Host (upstream)
Receiver Data Jitter Tolerance4 for
consecutive transactions
Function (downstream)
Function (downstream)
Receiver Data Jitter Tolerance4 for
paired transactions
–45
45
Low Speed Receiver EOP Width5
tUSB_RE21
tUSB_RE22
Must reject as EOP
Must accept as EOP
330
ns
ns
8-39
8-39
675
1. Unless otherwise specified, all timings use a 50 pF capacitive load (CL) to ground.
2. Full-speed timing has a 1.5 KΩ pull-up to 2.8 V on the DPOS_Port1,2,3 lines.
3. Timing difference between the differential data signals (DPOS_PORT1,2,3 and DNEG_PORT1,2,3).
4. Measured at the crossover point of differential data signals (DPOS_PORT1,2,3 and DNEG_PORT1,2,3).
5. EOP is the End of Packet where DPOS_PORTt = DNEG_PORT = SE0. SE0 occurs when output level voltage ≤ VSE
(Min).
6. CL = 350 pF.
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Electrical Specifications (Continued)
Rise Time
Fall Time
CL
90%
90%
Differential
Data Lines
10%
10%
CL
tUSB_R1,2
tUSB_F1,2
Full Speed: 4 to 20 ns at CL = 50 pF
Low Speed: 75 ns at CL = 50 pF, 300 ns at CL = 350 pF
Figure 8-38. USB Data Signal Rise and Fall Timing Diagram
tUSB_DJ11
tUSB_DJD21
tUSB_DJU21
tperiod_F
tperiod_L
Crossover Points
(1.3-2.0) V
Differential
Data Lines
tUSB_DJ12
tUSB_DJD22
tUSB_DJU22
Consecutive Transitions
N*t
+ t
_
period F
USB_DJ11
N*tperiod_L + tUSB_DJD21
N*tperiod_L + tUSB_DJU21
Paired Transitions
N*tperiod_F + tUSB_DJ12
N*tperiod_L + tUSB_DJD22
N*tperiod_L + tUSB_DJU22
Figure 8-39. USB Source Differential Data Jitter Timing Diagram
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Electrical Specifications (Continued)
tperiod_F
tperiod_L
Data
Crossover
Level
Differential
Data Lines
Differential Data to SE0 Skew
N*tperiod_F + tUSB_DE1
tUSB_SE1, USB_SE2
t
Source:
N*tperiod_L + tUSB_DE2
tUSB_RE11, tUSB_RE12
Receiver:
tUSB_RE21, USB_RE22
t
EOP Width
Figure 8-40. USB EOP Width Timing Diagram
tUSB_RJ11
tUSB_RJD21
tUSB_RJU21
tperiod_F
tperiod_L
Crossover Points
Differential
Data Lines
tUSB_RJ12
tUSB_RJD22
tUSB_RJU22
Consecutive Transitions
N*tperiod_F + tUSB_RJ11
N*tperiod_L + tUSB_RJD21
N*tperiod_L + tUSB_RJU21
Paired Transitions
N*tperiod_F + tUSB_RJ12
N*tperiod_L + tUSB_RJD22
N*tperiod_L + tUSB_RJU22
Figure 8-41. USB Receiver Jitter Tolerance Timing Diagram
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Electrical Specifications (Continued)
8.3.11 Serial Port (UART)
Table 8-31. UART, Sharp-IR, SIR, and Consumer Remote Control Timing Parameters
Symbol
Parameter
Min
Max
Unit Comments
tBTN - 25 1
tBT
Single Bit Time in UART and
Sharp-IR
t
BTN + 25
ns Transmitter
tBTN - 2%
tBTN + 2%
tCWN + 25
ns Receiver
tCWN - 25 2
500
tCMW
Modulation Signal Pulse
Width in Sharp-IR and
Consumer Remote
Control
ns Transmitter
ns Receiver
tCPN - 25 3
tCMP
Modulation Signal Period in
Sharp-IR and Consumer
Remote Control
tCPN + 25
ns Transmitter
4
4
ns Receiver
tMMIN
tMMAX
(3/16) x tBTN - 15 1
(3/16) x tBTN + 15 1
tSPW
SIR Signal Pulse Width
ns Transmitter, Variable
1.48
1
1.78
µs Transmitter, Fixed
µs Receiver
Transmitter
SDRT
SIR Data Rate Tolerance
% of Nominal Data Rate
± 0.87%
± 2.0%
± 2.5%
± 6.5%
Receiver
tSJT
SIR Leading Edge Jitter
% of Nominal Bit Duration
Transmitter
Receiver
1. tBTN is the nominal bit time in UART, Sharp-IR, SIR and Consumer Remote Control modes. It is determined by the set-
ting of the Baud Generator Divisor registers.
2. tCWN is the nominal pulse width of the modulation signal for Sharp-IR and Consumer Remote Control modes. It is de-
termined by the MCPW field (bits [7:5]) of the IRTXMC register and the TXHSC bit (bit 2) of the RCCFG register.
3. tCPN is the nominal period of the modulation signal for Sharp-IR and Consumer Remote Control modes. It is determined
by the MCFR field (bits [4:0]) of the IRTXMC registerand the TXHSC bit (bit 2) of the RCCFG register.
4. tMMIN and tMMAX define the time range within which the period of the incoming subcarrier signal has to fall in order for
the signal to be accepted by the receiver. These time values are determined by the contents of register IRRXDC and
the setting of the RXHSC bit (bit 5) of the RCCFG register.
t
BT
UART
t
CMP
Sharp IR
Consumer
Remote
t
CMW
Control
t
SPW
SIR
Figure 8-42. UART, Sharp-IR, SIR, and Consumer Remote Control Timing Diagram
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Electrical Specifications (Continued)
8.3.12 Fast IR Port Timing
Table 8-32. Fast IR Port Timing Parameters
Symbol
Parameter
Min
Max
Unit
Comments
tMWN-251
60
tMPW
MIR Signal Pulse Width
tMWN+25
ns
Transmitter
ns
Receiver
MDRT
tMJT
MIR Transmitter Data Rate Tolerance
± 0.1%
± 2.9%
MIR Receiver Edge Jitter, % of Nominal Bit
Duration
tFPW
FIR Signal Pulse Width
120
90
130
160
ns
ns
ns
ns
Transmitter
Receiver
tFDPW
FIR Signal Double Pulse Width
FIR Transmitter Data Rate Tolerance
245
215
255
Transmitter
Receiver
285
FDRT
tFJT
± 0.01%
FIR Receiver Edge Jitter, % of Nominal Bit
Duration
± 4.0%
1. tMWN is the nominal pulse width for MIR mode. It is determined by the M_PWID field (bits [4:0]) in the MIR_PW register
at offset 01h in bank 6 of logical device 5.
tMPW
MIR
Data
Symbol
tFPW
tFDPW
FIR
Chips
Figure 8-43. Fast IR Timing (MIR and FIR) Diagram
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8.3.13 Parallel Port Timing
Table 8-33. Standard Parallel Port Timing Parameters
Symbol
Parameter
Min
Typ
Max
Unit
Comments
tPDH
Port Data Hold
500
ns
Times are system dependent and
are therefore not tested.
tPDS
tSW
Port Data Setup
Strobe Width
500
500
ns
ns
Times are system dependent and
are therefore not tested.
Times are system dependent and
are therefore not tested.
BUSY
ACK#
tPDH
tPDS
PD[7:0]
tSW
STB#
Figure 8-44. Standard Parallel Port Typical Data Exchange Timing Diagram
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Electrical Specifications (Continued)
Table 8-34. Enhanced Parallel Port Timing Parameters
Symbol
tWW19a
tWW19ia
tWST19a
tWEST
Parameter
Min
Max
45
EPP 1.7
EPP 1.9
Unit
ns
WRITE# active from WAIT# low
WRITE# inactive from WAIT# low
DSTRB# or ASTRB# active from WAIT# low
x
x
x
x
45
ns
65
ns
DSTRB# or ASTRB# active after WRITE#
active
10
0
x
ns
tWPDH
tWPDS
tEPDW
tEPDH
PD[7:0] Hold after WRITE# inactive
PD[7:0] Valid after WRITE# active
PD[7:0] Valid width
x
x
x
x
x
x
x
x
ns
ns
ns
ns
15
80
0
PD[7:0] Hold after DSTRB# or ASTRB# inactive
tWW19a
WRITE#
DSTRB#
or
ASTRB#
tWST19a
tWST19a
tEPDH
tWPDH
tWEST
Valid
tEPDW
PD[7:0]
WAIT#
tWPDS
tWW19ia
Figure 8-45. Enhanced Parallel Port Timing Diagram
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430
Revision 6.0
Electrical Specifications (Continued)
8.3.13.1 Extended Capabilities Port (ECP) Timing
Table 8-35. ECP Forward Mode Timing Parameters
Symbol
tECDSF
tECDHF
tECLHF
tECHHF
tECHLF
tECLLF
Parameter
Min
0
Max
Unit
ns
ns
ns
s
Comments
Data Setup before STB# Active
Data Hold after BUSY Inactive
BUSY Active after STB# Active
STB# Inactive after BUSY Active
BUSY Inactive after STB# Active
STB# Active after BUSY Inactive
0
75
0
1
0
35
ms
ns
0
tECDHF
PD[7:0]
AFD#
tECDSF
tECLLF
STB#
BUSY
tECHLF
tECLHF
tECHHF
Figure 8-46. ECP Forward Mode Timing Diagram
Revision 6.0
431
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Electrical Specifications (Continued)
Table 8-36. ECP Reverse Mode Timing Parameters
Symbol
tECDSR
tECDHR
tECLHR
tECHHR
tECHLR
tECLLR
Parameter
Min
0
Max
Unit
ns
ns
ns
ms
s
Comments
Data Setup before ACK# Active
Data Hold after AFD# Active
AFD# Inactive after ACK# Active
ACK# Inactive after AFD# Inactive
AFD# Active after ACK# Inactive
ACK# Active after AFD# Active
0
75
0
35
1
0
0
ns
tECDHR
PD[7:0]
BUSY#
tECDSR
ACK#
AFD#
tECLLR
tECHLR
tECLHR
tECHHR
Figure 8-47. ECP Reverse Mode Timing Diagram
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432
Revision 6.0
Electrical Specifications (Continued)
8.3.14 Audio Interface Timing (AC97)
Table 8-37. AC Reset Timing Parameters
Symbol
Parameter
Min
1.0
Typ
Max
Unit
µs
Comments
tRST_LOW AC97_RST# active low pulse width
tRST2CLK
AC97_RST# inactive to BIT_CLK
startup delay
162.8
ns
tRST2CLK
tRST_LOW
AC97_RST#
BIT_CLK
Figure 8-48. AC97 Reset Timing Diagram
Table 8-38. AC97 Sync Timing Parameters
Symbol
Parameter
Min
Typ
Max
Unit
µs
Comments
tSYNC_HIGH SYNC active high pulse width
1.3
tSYNC_IA
SYNC inactive to BIT_CLK startup
delay
162.8
ns
tSYNC_IA
tSYNC_HIGH
SYNC
BIT_CLK
Figure 8-49. AC97 Sync Timing Diagram
Revision 6.0
433
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Electrical Specifications (Continued)
Table 8-39. AC97 Clocks Parameters
Symbol
FBIT_CLK
tCLK_PD
tCLK_J
Parameter
Min
Typ
12.288
81.4
Max
Unit
MHz
ns
Comments
BIT_CLK frequency
BIT_CLK period
BIT_CLK output jitter
750
ps
BIT_CLK high pulse width1
tCLK_H
32.56
32.56
40.7
40.7
48.0
20.8
1.3
48.84
48.84
ns
BIT_CLK low pulse width1
SYNC frequency
tCLK_L
ns
FSYNC
KHz
µs
tSYNC_PD
tSYNC_H
tSYNC_L
FAC97_CLK
SYNC period
SYNC high pulse width
SYNC low pulse width
AC97_CLK Frequency
µs
19.5
24.576
40.7
µs
MHz
ns
tAC97_CLK_PD AC97_CLK Period
tAC97_CLK_D AC97_CLK Duty Cycle
tAC97_CLK_FR AC97_CLK Fall/Rise time
45
2
55
5
%
ns
tAC97_CLK_J
AC97_CLK output edge-to-
edge jitter
100
ps
Measured from edge to edge
1. Worst case duty cycle restricted to 40/60.
tCLK_L
tCLK_H
BIT_CLK
tCLK_PD
tSYNC_L
tSYNC_H
SYNC
tSYNC_PD
tAC97_CLK_PD
VOHD
VOLD
AC97_CLK
tAC97_CLK_FR
Figure 8-50. AC97 Clocks Diagram
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434
Revision 6.0
Electrical Specifications (Continued)
Table 8-40. AC97 I/O Timing Parameters
Symbol
tAC97_S
tAC97_H
tAC97_OV
Parameter
Min
15.0
10.0
Typ
Max
Unit
ns
Comments
Input setup to falling edge of BIT_CLK
Hold from falling edge of BIT_CLK
ns
SDATA_OUT or SYNC valid after rising
edge of BIT_CLK
15
ns
tAC97_OH
tAC97_SV
tAC97_SH
SDATA_OUT or SYNC hold time after
falling edge of BIT_CLK
5
5
ns
ns
ns
Sync out valid after rising edge of
BIT_CLK
15
Sync out hold after falling edge of
BIT_CLK
t
AC97_SV
tAC97_OV
tAC97_S
t
AC97_SH
tAC97_OH
BIT_CLK
SDATA_OUT/SYNC
SDATA_IN, SDATA_IN2
tAC97_H
Figure 8-51. AC97 Data TIming Diagram
Revision 6.0
435
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Electrical Specifications (Continued)
Table 8-41. AC97 Signal Rise and Fall Timing Parameters
Symbol
triseCLK
tfallCLK
Parameter
Min
2
Typ
Max
6
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Comments
BIT_CLK rise time
BIT_CLK fall time
2
6
triseSYNC SYNC rise time
2
6
CL = 50 pF
CL = 50 pF
tfallSYNC
triseDIN
tfallDIN
SYNC fall time
2
6
SDATA_IN rise time
SDATA_IN fall time
2
6
2
6
triseDOUT SDATA_OUT rise time
2
6
CL = 50 pF
CL = 50 pF
tfallDOUT
SDATA_OUT fall time
2
6
90%
10%
BIT_CLK
triseCLK
tfallCLK
90%
10%
SYNC
triseSYNC
tfallSYNC
90%
10%
SDATA_IN
triseDIN
tfallDIN
90%
10%
SDATA_OUT
triseDOUT
tfallDOUT
Figure 8-52. AC97 Rise and Fall Timing Diagram
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436
Revision 6.0
Electrical Specifications (Continued)
Table 8-42. AC97 Low Power Mode Timing Parameters
Symbol
Parameter
Min
Typ
Max
Unit
Comments
ts2_pdown
End of Slot 2 to BIT_CLK,
SDATA_IN low
1.0
µs
SYNC
Slot 1 Slot 2
BIT_CLK
SDATA_OUT
Write to 0x20 Write to PA4
Don’t Care
ts2_pdown
SDATA_IN
Note: BIT_CLK is not to scale
Figure 8-53. AC97 Low Power Mode Timing Diagram
Revision 6.0
437
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Electrical Specifications (Continued)
8.3.15 Power Management
LED# Cycle time: 1 s ± 0.1 s, 40%-60% duty cycle.
Table 8-43. PWRBTN# Timing Parameters
Symbol
tPBTNP
tPBTNE
Parameter
Min
16
Max
Unit
ms
Conditions
PWRBTN# Pulse Width1
Delay from PWRBTN# Events to
ONCTL#
14
16
ms
1. Not 100% tested.
tPBTNP
tPBTNP
PWRBTN#
ONCTL#
tPBTNE
tPBTNE
Figure 8-54. PWRBTN# Trigger and ONCTL# Timing Diagram
Table 8-44. Power Management Event (GPWIO) and ONCTL# Timing Parameters
Symbol
Parameter
Min
Max
Unit
Conditions
tPM
Power Management Event to ONCTL#
assertion
45
ns
GPWIOx
tPM
ONCTL#
PWRCNT1
PWRCNT2
Figure 8-55. GPWIO and ONCTL# Timing Diagram
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438
Revision 6.0
Electrical Specifications (Continued)
8.3.16 Power-Up Sequencing
Table 8-45. Power-Up Sequence Using the Power Button Timing Parameters
Symbol
Parameter
Min
-10
0
Max
10
1
Unit
ms
µs
Comments
t1
t2
Voltage sequence
PWRBTN# inactive after VSB or VSBL
applied, whichever is applied last
PWRBTN# is an input and must
be powered by VSB
.
t3
PWRBTN# active pulse width
16
4000
ms
If PWRBTN# max is exceeded,
ONCTL# will go inactive.
t4
t5
t6
ONCTL# inactive after VSB applied
Signal active after PWRBTN active
0
16
0
1
ms
ms
ms
32
VCORE and VIO applied after ONCTL#
active
System determines when VCORE
and VIO are applied, hence there
is no maximum constraint.
t7
POR# inactive after VCORE and VIO
applied
50
ms
POR# must not glitch during
active time.
VSBL
VSB
VCORE
VIO
t1
t1
t6
t2
t3
PWRBTN#
ONTCL#
t5
t4
PWRCNT[2:1]
POR#
t7
Figure 8-56. Power-Up Sequencing With PWRBTN# Timing Diagram
Revision 6.0
439
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Electrical Specifications (Continued)
Table 8-46. Power-Up Sequence Not Using the Power Button Timing Parameters
Symbol
Parameter
Min
-10
50
Max
Unit
ms
Comments
t1
t2
Voltage sequence
10
POR# inactive after VSBL, VCORE, VSB
,
ms
POR# must not glitch during
active time.
and VIO applied
t3
32KHZ startup time
1
s
Time required for 32 KHz oscilla-
tor and 14.318 MHz derived from
PLL6 to become stable at which
time the RTC can reliably count.
1
VSBL, VCORE
t1
2
VSB, VIO
t2
POR#
t3
32KHZ
1) VSBL and VCORE should be tied together.
2) SB and VIO should be tied together.
V
Figure 8-57. Power-Up Sequencing Without PWRBTN# Timing Diagram
ACPI is non-functional when the power-up sequence does not include using the power button. If ACPI functionality is
desired, the power button must be toggled. This can be done externally or internally. GPIO63 is internally connected to
PWRBTN#. To toggle the power button with software, GPIO63 must be programmed as an output using the normal GPIO
programming protocol (see Section 5.4.1.1 "GPIO Support Registers" on page 236). GPIO63 must be pulsed low for at
least 16 ms and not more than 4 sec. Asserting POR# has no effect on ACPI. If POR# is asserted and ACPI was active
prior to POR#, then ACPI will remain active after POR#. Therefore, BIOS must ensure that ACPI is inactive before GPIO63
is pulsed low.
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440
Revision 6.0
Electrical Specifications (Continued)
8.3.17 JTAG Interface
Table 8-47. JTAG Timing Parameters
Symbol
Parameter
Min
Max
Unit
Comments
TCK Frequency (MHz)
TCK Period
25
MHz
ns
t1
40
10
10
t2
TCK High time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t3
TCK Low time
t4
TCK Rise time
4
t5
TCK Fall Time
4
t6
TDO Valid delay
3
3
25
25
30
36
t7
Non-test outputs Valid delay
TDO Float delay
50 pF load
t8
t9
Non-test outputs Float delay
TDI, TMS Setup time
Non-test inputs Setup time
TDI, TMS Hold time
Non-test inputs Hold time
t10
t11
t12
t13
8
8
7
7
t
1
t
2
VIH(Min)
1.5V
VIL(Max)
TCK
t
3
t
t
4
5
Figure 8-58. TCK Measurement Points and Timing Diagram
Revision 6.0
441
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Electrical Specifications (Continued)
TCK
t
t
12
10
TDI,
TMS
t
t
t
6
8
TDO
t
9
7
Output
Signals
t
t
11
13
Input
Signals
Figure 8-59. JTAG Test Timing Diagram
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442
Revision 6.0
9.0 Package Specifications
The figures in this section provide the mechanical package outlines for the 432-Terminal EBGA (Enhanced Ball Grid Array)
and 481-Terminal TEPBGA (Thermally Enhanced Ball Grid Array) packages.
NOTES: UNLESS OTHERWISE SPECIFIED.
1) SOLDER BALL COMPOSITION: SN 63%, PB 37%.
2) DIMENSION IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO PRIMARY DATUM N.
3) REFERENCE JEDEC REGISTRATION MO-151, VARIATION -1.00, DATED JUNE 1997.
4) THETA JUNCTION TO CASE (TJC) = 1°C/WATT.
Figure 9-1. 432-Terminal EBGA Package (Body Size: 40x40x1.72 mm; Pitch: 1.27 mm)
Revision 6.0
443
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Package Specifications (Continued)
Lot code
example
VT224 AB
NOTES: UNLESS OTHERWISE SPECIFIED.
1) TEPBGA WITH LEAD (PB):
a) SOLDER BALL COMPOSITION: SN 63%, PB 37%.
b) SOLDERING PROFILE: 220o C.
c) PART IDENTIFICATION VIA LOT CODE. THE LAST TWO CHARACTERS OF THE SEVEN DIGIT CODE
ARE: AA . . . AZ, BA . . . BZ, CA . . . CZ, . . . , QA . . . QZ.
2) TEPBGA LEAD (PB) FREE:
a) SOLDER BALL COMPOSITION: SN 96.5%, AG 3.5%.
b) SOLDERING PROFILE: 260o C
c) PART IDENTIFICATION VIA LOT CODE. THE LAST TWO CHARACTERS OF THE SEVEN DIGIT CODE ARE: RA . . . RZ,
SA . . . SZ, TA . . . TZ, . . . , ZA . . . ZZ.
3) DIMENSION IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO PRIMARY DATUM N.
4) THE MOLD SURFACE AREA MAY INCLUDE DIMPLE FOR A1 BALL CORNER IDENTIFICATION.
5) REFERENCE JEDEC REGISTRATION MS-034, VARIATION BAU-1.
6) THETA JUNCTION TO CASE (TJC) = 5°C/WATT.
Figure 9-2. 481-Terminal TEPBGA Package (Body Size: 40x40x2.38 mm; Pitch: 1.27 mm)
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444
Revision 6.0
Appendix A Support Documentation
A.1 ORDER INFORMATION
Core
Voltage
(VCORE
Core
Frequency
(MHz)
Order Number
Temperature
(Degree C)
)
(NSID)
Part Marking
Package
EBGA
SC1200UCL-266
SC1200UFH-266
SC1200UCL-266
SC1200UFH-266
266
1.8V
0 - 85
TEPBGA1
SC1200UFH-266B2
SC1201UCL-266
SC1201UFH-266
TEPBGA1
EBGA
SC1200UFH-266B
SC1201UCL-266
SC1201UFH-266
266
1.8V
0 - 85
TEPBGA1
TEPBGA1
SC1201UFH-266B2
SC1201UFH-266B
1. A leadfree package version of this device is available. Use Spec. Flow NOPB to order the leadfree package. See Section
9.0 "Package Specifications" for how to identify the part.
2. Refer to IBAT in Table 8-6 on page 375 for details.
A.2 MACROVISION PRODUCT NOTICE
The SC1201 is protected by U.S. patent numbers 4,631,603, 4,577,216, and 4,819,098 and other intellectual property
rights. The use of Macrovision's copy protection technology in the SC1201 must be authorized by Macrovision and is
intended for home and other limited pay-per-view uses only, unless otherwise authorized in writing by Macrovision. Reverse
engineering or disassembly is prohibited.
Macrovision is a trademark of Macrovision Corporation.
A.3 DATASHEET REVISION HISTORY
This section is a report of the revision/creation process of the datasheet for the Geode SC1200/SC1201. Any revisions (i.e.,
additions, deletions, parameter corrections, etc.) are recorded in the table(s) below.
Table A-1. Revision History
Revision #
(PDF Date)
Revisions / Comments
0.1
First draft of datasheet.
(October 1999)
1.2
Preliminary datasheet. Updated various descriptions, such as ISA, sub-ISA and AC97 codec sta-
tus; added various test modes for Video Processor; changed specific values such as TVCOMP
compensation capacitor; fixed assorted typos.
(January 2000)
2.0
(July 2000)
Preliminary datasheet. PMR and MCR changes, IRQ3 changed to INTC#, IOCHRDY added
FMUL1 changed to PLL4, FMUL4 changed to PLL5, TRDE# enhancement.
2.12
(February 2001)
Preliminary datasheet. Video output protocol added (multiplexed with TFT/Parallel Port balls).
GNT[1:0]# strapping functions changed. TV interface AC specifications added. Minor modifications
and corrections.
2.13
Corrected typos and formatting errors. Added clarifications and missing information.
(August 2001)
3.0
Rolled in SC1210 functionality. Re-wrote Sections 2.0, 3.0, and 6.0. Changed ACCESS.bus in
Section 4.0. Added DC power and modified some AC specifications in Section 8.0.
(January 2002)
4.0
(April 2002)
Major additions added were Macrovision functionality and rolled in TEPBGA data. Several other
corrections/changes were made to specific sections. See revision 4.0 for a list of all changes.
4.1
(June 2002)
Release for posting on external web site. Changes made to the Architecture Overview, Signal Defi-
nitions, Core Logic Module, Video Processor Module, Electrical Specifications, and Package Spec-
ifications chapters.
Revision 6.0
445
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Support Documentation (Continued)
Table A-1. Revision History
Revision #
(PDF Date)
Revisions / Comments
5.0
Major edits include replacing VOP CCIR-656 references with VESA Video Interface Port Rev. 1.1
Task B. Major corrections include fixing TEPBGA ball numbers in “Two-Signal/Group Multiplexing”
table (Table 2-7) and GPIO signal descriptions (Section 2.4.17).
(August 2002)
5.1
Many minor changes mostly to the Video Processor and Electrical sections. Expounded on the
notes in the Mechanical section. See Table A-2 "Edits to Current Revision" for details.
(February 2003)
6.0
Many changes mostly to Video Processor and Electrical sections. Changed all references to Xpres-
sAUDIO to Audio.
(March 2003)
Table A-2. Edits to Current Revision
Revision
Section
General Description
Features
• No changes.
• Changed all references to XpressAUDIO to audio in all sections.
Section 1.0 "Architec-
ture Overview"
• No changes.
• No changes.
• No changes.
• No changes.
Section 2.0 "Signal
Definitions"
Section 3.0 "General
Configuration Block"
Section 4.0 "SuperI/O
Module"
Section 5.0 "Core
Logic Module"
• Section 5.2.12 "Integrated Audio" on page 181: Deleted the first bullet under supported
hardware - “XpressAUDIO with 16-bit stereo FM synthesis and OPL3 emulation.”
• Changed 4-byte boundary to 32-byte boundary in all references to audio.
• Added sentence to last bullet under Physical Region Descriptor Format on page 182: “The
target address must be on a 32-byte boundary so bits[4:0] must be written to 0.”
• Added 32-byte boundary label to Figure 5-12 on page 183.
Section 6.0 "Video
Processor Module"
• Updated Figure 6-10 on page 331.
• Changed 232 to 232 in Offset C0Ch-C0Fh Subcarrier Frequency Register Reset Value:
21F07C1Fh on page 364.
Section 7.0 "Debug-
ging and Monitoring"
• No changes.
Section 8.0 "Electrical
Specifications"
• In Table 8-6 on page 375: Changed last row (second IBAT row) and footnotes 4 and 5 from
engineering text to normal text and changed Max value in second IBAT row from 20 to 15.
Also added NSID # to footnote 5.
• Changed the Max value for VIH in Sections 8.2.2 through 8.2.8.
• Changed many values in Table 8-12 on page 386.
Section 9.0 "Package
Specifications"
• Changed values for Solder Ball Composition in Note 2 in Figure 9-2 on page 444 and
changed Note 2 from engineering to normal text.
Section Appendix A
"Support Documenta-
tion"
• Added rows for SC1200UFH-266B and SC1201UFH-266B and added footnotes in
Section A.1 "Order Information".
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Revision 6.0
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury to
the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
National Semiconductor
Europe
National Semiconductor
Japan Ltd.
Tel: 81-3-5639-7560
Fax: 81-3-5639-7507
Email: jpn.feedback@nsc.com
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Corporation
Americas
Email:
new.feedback@nsc.com
Tel: 1-800-272-9959
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Response Group
Tel: +65-62544466
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