SCAN921224SLCX/NOPB [TI]
SPECIALTY INTERFACE CIRCUIT, PBGA49, BGA-49;
| 型号： | SCAN921224SLCX/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SPECIALTY INTERFACE CIRCUIT, PBGA49, BGA-49 |
| 文件： | 总23页 (文件大小：975K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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information and details on our current products and services.
April 2001
SCAN921023 and SCAN921224
20-66 MHz 10 Bit Bus LVDS Serializer and Deserializer
with IEEE 1149.1 (JTAG) and at-speed BIST
use the synchronization-to-random-data feature. By using
the synchronization mode, the Deserializer will establish lock
General Description
The SCAN921023 transforms
a 10-bit wide parallel
to a signal within specified lock times. In addition, the em-
bedded clock guarantees a transition on the bus every 12-bit
cycle. This eliminates transmission errors due to charged
cable conditions. Furthermore, you may put the
SCAN921023 output pins into TRI-STATE to achieve a high
impedance state. The PLL can lock to frequencies between
20 MHz and 66 MHz.
LVCMOS/LVTTL data bus into a single high speed Bus
LVDS serial data stream with embedded clock. The
SCAN921224 receives the Bus LVDS serial data stream and
transforms it back into a 10-bit wide parallel data bus and
recovers parallel clock. Both devices are compliant with
IEEE 1149.1 Standard Test Access Port and Boundary Scan
Architecture with the incorporation of the defined boundary-
scan test logic and test access port consisting of Test Data
Input (TDI), Test Data Out (TDO), Test Mode Select (TMS),
Test Clock (TCK), and the optional Test Reset (TRST). IEEE
1149.1 features provide the designer or test engineer access
to the backplane or cable interconnects and the ability to
verify differential signal integrity to enhance their system test
strategy. The pair of devices also features an at-speed BIST
mode which allows the interconnects between the Serializer
and Deserializer to be verified at-speed.
Features
n IEEE 1149.1 (JTAG) Compliant and At-Speed BIST test
mode.
n Clock recovery from PLL lock to random data patterns.
n Guaranteed transition every data transfer cycle
<
n Chipset (Tx + Rx) power consumption 500 mW (typ)
@
66 MHz
n Single differential pair eliminates multi-channel skew
n Flow-through pinout for easy PCB layout
n 660 Mbps serial Bus LVDS data rate (at 66 MHz clock)
n 10-bit parallel interface for 1 byte data plus 2 control bits
n Synchronization mode and LOCK indicator
n Programmable edge trigger on clock
n High impedance on receiver inputs when power is off
n Bus LVDS serial output rated for 27Ω load
n Small 49-lead BGA package
The SCAN921023 transmits data over backplanes or cable.
The single differential pair data path makes PCB design
easier. In addition, the reduced cable, PCB trace count, and
connector size tremendously reduce cost. Since one output
transmits clock and data bits serially, it eliminates clock-to-
data and data-to-data skew. The powerdown pin saves
power by reducing supply current when not using either
device. Upon power up of the Serializer, you can choose to
activate synchronization mode or allow the Deserializer to
Block Diagrams
© 2004 National Semiconductor Corporation
DS200001
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Block Diagrams (Continued)
20000101
Application
20000102
power-on circuitry disables internal circuitry. When VCC
reaches VCCOK (2.5V) the PLL in each device begins lock-
ing to a local clock. For the Serializer, the local clock is the
transmit clock (TCLK) provided by the source ASIC or other
device. For the Deserializer, you must apply a local clock to
the REFCLK pin.
Functional Description
The SCAN921023 and SCAN921224 are a 10-bit Serializer
and Deserializer chipset designed to transmit data over dif-
ferential backplanes at clock speeds from 20 to 66 MHz. The
chipset is also capable of driving data over Unshielded
Twisted Pair (UTP) cable.
The Serializer outputs remain in TRI-STATE while the PLL
locks to the TCLK. After locking to TCLK, the Serializer is
now ready to send data or SYNC patterns, depending on the
levels of the SYNC1 and SYNC2 inputs or a data stream.
The SYNC pattern sent by the Serializer consists of six ones
and six zeros switching at the input clock rate.
The chipset has three active states of operation: Initializa-
tion, Data Transfer, and Resynchronization; and two passive
states: Powerdown and TRI-STATE. In addition to the active
and passive states, there are also test modes for JTAG
access and at-speed BIST.
The following sections describe each operation and passive
state and the test modes.
Note that the Deserializer LOCK output will remain high
while its PLL locks to the incoming data or to SYNC patterns
on the input.
Initialization
Step 2: The Deserializer PLL must synchronize to the Seri-
alizer to complete initialization. The Deserializer will lock to
non-repetitive data patterns. However, the transmission of
SYNC patterns enables the Deserializer to lock to the Seri-
alizer signal within a specified time. See Figure 9.
Initialization of both devices must occur before data trans-
mission begins. Initialization refers to synchronization of the
Serializer and Deserializer PLL’s to local clocks, which may
be the same or separate. Afterwards, synchronization of the
Deserializer to Serializer occurs.
The user’s application determines control of the SYNC1 and
SYNC 2 pins. One recommendation is a direct feedback loop
Step 1: When you apply VCC to both Serializer and/or Dese-
rializer, the respective outputs enter TRI-STATE, and on-chip
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2
terns for resynchronization is desirable when lock times
within a specific time are critical. However, the Deserializer
can lock to random data, which is discussed in the next
section.
Initialization (Continued)
from the LOCK pin. Under all circumstances, the Serializer
stops sending SYNC patterns after both SYNC inputs return
low.
When the Deserializer detects edge transitions at the Bus
LVDS input, it will attempt to lock to the embedded clock
information. When the Deserializer locks to the Bus LVDS
clock, the LOCK output will go low. When LOCK is low, the
Deserializer outputs represent incoming Bus LVDS data.
Random Lock Initialization and
Resynchronization
The initialization and resynchronization methods described
in their respective sections are the fastest ways to establish
the link between the Serializer and Deserializer. However,
the SCAN921224 can attain lock to a data stream without
requiring the Serializer to send special SYNC patterns. This
allows the SCAN921224 to operate in “open-loop” applica-
tions. Equally important is the Deserializer’s ability to support
hot insertion into a running backplane. In the open loop or
hot insertion case, we assume the data stream is essentially
random. Therefore, because lock time varies due to data
stream characteristics, we cannot possibly predict exact lock
time. However, please see Table 1 for some general random
lock times under specific conditions. The primary constraint
on the “random” lock time is the initial phase relation be-
tween the incoming data and the REFCLK when the Dese-
rializer powers up. As described in the next paragraph, the
data contained in the data stream can also affect lock time.
Data Transfer
After initialization, the Serializer will accept data from inputs
DIN0–DIN9. The Serializer uses the TCLK input to latch
incoming Data. The TCLK_R/F pin selects which edge the
Serializer uses to strobe incoming data. TCLK_R/F high
selects the rising edge for clocking data and low selects the
falling edge. If either of the SYNC inputs is high for 5*TCLK
cycles, the data at DIN0-DIN9 is ignored regardless of clock
edge.
After determining which clock edge to use, a start and stop
bit, appended internally, frame the data bits in the register.
The start bit is always high and the stop bit is always low.
The start and stop bits function as the embedded clock bits
in the serial stream.
If a specific pattern is repetitive, the Deserializer could enter
“false lock” - falsely recognizing the data pattern as the
clocking bits. We refer to such a pattern as a repetitive
multi-transition, RMT. This occurs when more than one Low-
High transition takes place in a clock cycle over multiple
cycles. This occurs when any bit, except DIN 9, is held at a
low state and the adjacent bit is held high, creating a 0-1
transition. In the worst case, the Deserializer could become
locked to the data pattern rather than the clock. Circuitry
within the SCAN921224 can detect that the possibility of
“false lock” exists. The circuitry accomplishes this by detect-
ing more than one potential position for clocking bits. Upon
detection, the circuitry will prevent the LOCK output from
becoming active until the potential “false lock” pattern
changes. The false lock detect circuitry expects the data will
eventually change, causing the Deserializer to lose lock to
the data pattern and then continue searching for clock bits in
the serial data stream. Graphical representations of RMT are
shown in Figure 1. Please note that RMT only applies to bits
DIN0-DIN8.
The Serializer transmits serialized data and clock bits (10+2
bits) from the serial data output (DO ) at 12 times the TCLK
frequency. For example, if TCLK is 66 MHz, the serial rate is
66 x 12 = 792 Mega-bits-per-second. Since only 10 bits are
from input data, the serial “payload” rate is 10 times the
TCLK frequency. For instance, if TCLK = 66 MHz, the pay-
load data rate is 66 x 10 = 660 Mbps. The data source
provides TCLK and must be in the range of 20 MHz to 66
MHz nominal.
The Serializer outputs (DO ) can drive a point-to-point con-
nection or in limited multi-point or multi-drop backplanes.
The outputs transmit data when the enable pin (DEN) is
high, PWRDN = high, and SYNC1 and SYNC2 are low.
When DEN is driven low, the Serializer output pins will enter
TRI-STATE.
When the Deserializer synchronizes to the Serializer, the
LOCK pin is low. The Deserializer locks to the embedded
clock and uses it to recover the serialized data. ROUT data
is valid when LOCK is low. Otherwise ROUT0–ROUT9 is
invalid.
Powerdown
The ROUT0-ROUT9 pins use the RCLK pin as the reference
to data. The polarity of the RCLK edge is controlled by the
RCLK_R/F input. See Figure 13.
When no data transfer occurs, you can use the Powerdown
state. The Serializer and Deserializer use the Powerdown
state, a low power sleep mode, to reduce power consump-
tion. The Deserializer enters Powerdown when you drive
PWRDN and REN low. The Serializer enters Powerdown
when you drive PWRDN low. In Powerdown, the PLL stops
and the outputs enterTRI-STATE, which disables load cur-
rent and reduces supply current to the milliampere range. To
exit Powerdown, you must drive the PWRDN pin high.
ROUT(0-9), LOCK and RCLK outputs will drive a maximum
of three CMOS input gates (15 pF load) with a 66 MHz clock.
Resynchronization
When the Deserializer PLL locks to the embedded clock
edge, the Deserializer LOCK pin asserts a low. If the Dese-
rializer loses lock, the LOCK pin output will go high and the
outputs (including RCLK) will enter TRI-STATE.
Before valid data exchanges between the Serializer and
Deserializer, you must reinitialize and resynchronize the de-
vices to each other. Initialization of the Serializer takes 510
TCLK cycles. The Deserializer will initialize and assert LOCK
high until lock to the Bus LVDS clock occurs.
The user’s system monitors the LOCK pin to detect a loss of
synchronization. Upon detection, the system can arrange to
pulse the Serializer SYNC1 or SYNC2 pin to resynchronize.
Multiple resynchronization approaches are possible. One
recommendation is to provide a feedback loop using the
LOCK pin itself to control the sync request of the Serializer
(SYNC1 or SYNC2). Dual SYNC pins are provided for mul-
tiple control in a multi-drop application. Sending sync pat-
TRI-STATE
The Serializer enters TRI-STATE when the DEN pin is driven
low. This puts both driver output pins (DO+ and DO−) into
3
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tions to test the LVDS interconnects. The first is EXTEST.
This is implemented at LVDS levels and is only intended as
a go no-go test (e.g. missing cables). The second method is
the RUNBIST instruction. It is an "at-system-speed" inter-
connect test. It is executed in approximately 33mS with a
system clock speed of 66MHz. There are two bits in the RX
BIST data register for notification of PASS/FAIL and
TEST_COMPLETE. Pass indicates that the BER (Bit-Error-
Rate) is better than 10-7.
TRI-STATE (Continued)
TRI-STATE. When you drive DEN high, the Serializer returns
to the previous state, as long as all other control pins remain
static (SYNC1, SYNC2, PWRDN, TCLK_R/F).
When you drive the REN pin low, the Deserializer enters
TRI-STATE. Consequently, the receiver output pins
(ROUT0–ROUT9) and RCLK will enter TRI-STATE. The
LOCK output remains active, reflecting the state of the PLL.
An important detail is that once both devices have the RUN-
BIST instruction loaded into their respective instruction reg-
isters, both devices must move into the RTI state within 4K
system clocks (At a SCLK of 66Mhz and TCK of 1MHz this
allows for 66 TCK cycles). This is not a concern when both
devices are on the same scan chain or LSP, however, it can
be a problem with some multi-drop devices. This test mode
has been simulated and verified using National’s SCAN-
STA111.
TABLE 1.
Random Lock Times for the SCAN921224
66 MHz
Units
µS
Maximum
Mean
18
3.0
µS
Minimum
Conditions:
0.43
µS
PRBS 215, VCC = 3.3V
1) Difference in lock times are due to different starting points in the data
pattern with multiple parts.
Ordering Information
NSID
Function
Serializer
Package
SLC49a
SLC49a
SCAN921023SLC
SCAN921224SLC
Test Modes
Deserializer
In addition to the IEEE 1149.1 test access to the digital TTL
pins, the SCAN921023 and SCAN921224 have two instruc-
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4
Ordering Information (Continued)
20000124
DIN0 Held Low-DIN1 Held High Creates an RMT Pattern
20000125
DIN4 Held Low-DIN5 Held High Creates an RMT Pattern
20000126
DIN8 Held Low-DIN9 Held High Creates an RMT Pattern
FIGURE 1. RMT Patterns Seen on the Bus LVDS Serial Output
5
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@
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
25˚C Package:
49L BGA
1.47 W
Package Derating:
11.8 mW/˚C above
+25˚C
Supply Voltage (VCC
)
−0.3V to +4V
−0.3V to (VCC +0.3V)
−0.3V to (VCC +0.3V)
−0.3V to +3.9V
49L BGA
θja
LVCMOS/LVTTL Input
Voltage
85˚C/W
ESD Rating
HBM
LVCMOS/LVTTL Output
Voltage
>
2kV
>
MM
250V
Bus LVDS Receiver Input
Voltage
Recommended Operating
Conditions
Bus LVDS Driver Output
Voltage
−0.3V to +3.9V
Bus LVDS Output Short
Circuit Duration
Junction Temperature
Storage Temperature
Lead Temperature
(Soldering, 4 seconds)
Min Nom Max Units
10mS
+150˚C
Supply Voltage (VCC
Operating Free Air
Temperature (TA)
)
3.0
−40
0
3.3
3.6
+85
2.4
V
˚C
V
+25
−65˚C to +150˚C
Receiver Input Range
Supply Noise Voltage
+260˚C
100 mVP-P
(VCC
)
Maximum Package Power Dissipation Capacity
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
SERIALIZER LVCMOS/LVTTL DC SPECIFICATIONS (apply to DIN0-9, TCLK, PWRDN, TCLK_R/F, SYNC1, SYNC2, DEN)
VIH
VIL
VCL
IIN
High Level Input Voltage
Low Level Input Voltage
Input Clamp Voltage
Input Current
2.0
VCC
0.8
V
V
GND
ICL = −18 mA
-0.86
1
−1.5
+10
V
VIN = 0V or 3.6V
−10
µA
DESERIALIZER LVCMOS/LVTTL DC SPECIFICATIONS (apply to pins PWRDN, RCLK_R/ F, REN, REFCLK = inputs; apply
to pins ROUT, RCLK, LOCK = outputs)
VIH
VIL
VCL
IIN
High Level Input Voltage
Low Level Input Voltage
Input Clamp Voltage
Input Current
2.0
VCC
0.8
V
V
GND
ICL = −18 mA
−0.62 −1.5
V
VIN = 0V or 3.6V
VIN = 0V or 3.6V
−10
-20
1
+15
µA
µA
IILR
Input Current, TMS, TDI, TRST
inputs
-10
VOH
VOL
IOS
High Level Output Voltage
Low Level Output Voltage
Output Short Circuit Current
Output Short Circuit Current, TDO
output
IOH = −9 mA
IOL = 9 mA
VOUT = 0V
2.2
GND
−15
-15
3.0
0.25
−47
-70
VCC
0.5
V
V
−85
-100
mA
mA
IOS
IOZ
TRI-STATE Output Current
PWRDN or REN = 0.8V, VOUT = 0V or VCC −10
0.1
+10
35
µA
SERIALIZER Bus LVDS DC SPECIFICATIONS (apply to pins DO+ and DO−)
VOD
Output Differential Voltage
(DO+)–(DO−)
RL = 27Ω, Figure 18
200
290
mV
mV
∆VOD
Output Differential Voltage
Unbalance
VOS
∆VOS
IOS
Offset Voltage
1.05
1.1
4.8
1.3
35
V
Offset Voltage Unbalance
Output Short Circuit Current
mV
D0 = 0V, DIN = High,PWRDN and DEN =
2.4V
−56
1
−90
+10
mA
µA
IOZ
TRI-STATE Output Current
PWRDN or DEN = 0.8V, DO = 0V or VCC
−10
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6
Electrical Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
IOX
Parameter
Conditions
Min
Typ
Max
Units
Power-Off Output Current
VCC = 0V, DO=0V or 3.6V
−20
1
+25
µA
DESERIALIZER Bus LVDS DC SPECIFICATIONS (apply to pins RI+ and RI−)
VTH
VTL
IIN
Differential Threshold High Voltage
Differential Threshold Low Voltage
Input Current
VCM = +1.1V
+6
−12
1
+50
mV
mV
µA
−50
−10
−10
VIN = +2.4V, VCC = 3.6V or 0V
VIN = 0V, VCC = 3.6V or 0V
+15
+10
0.05
µA
SERIALIZER SUPPLY CURRENT (apply to pins DVCC and AVCC)
ICCD
Serializer Supply Current
Worst Case
RL = 27Ω
f = 20 MHz
f = 66 MHz
47
75
47
60
90
mA
mA
µA
Figure 2
ICCXD
Serializer Supply Current Powerdown PWRDN = 0.8V
500
DESERIALIZER SUPPLY CURRENT (apply to pins DVCC and AVCC)
ICCR
Deserializer Supply Current
Worst Case
CL = 15 pF
f = 20 MHz
f = 66 MHz
58
75
mA
mA
Figure 3
110
130
ICCXR
Deserializer Supply Current
Powerdown
PWRDN = 0.8V, REN = 0.8V
0.36
1.0
mA
Serializer Timing Requirements for TCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
tTCP
Parameter
Transmit Clock Period
Transmit Clock High Time
Transmit Clock Low Time
TCLK Input Transition
Time
Conditions
Min
15.15
0.4T
0.4T
Typ
T
Max
50.0
0.6T
0.6T
Units
nS
tTCIH
tTCIL
tCLKT
0.5T
0.5T
nS
nS
3
6
nS
tJIT
TCLK Input Jitter
pS
Figure 17
150
(RMS)
Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Bus LVDS Low-to-High
Transition Time
Conditions
RL = 27Ω
CL=10pF to GND
Min
Typ
Max
Units
tLLHT
0.2
0.4
nS
Figure 4
tLHLT
Bus LVDS High-to-Low
Transition Time
0.25
0.4
nS
(Note 4)
tDIS
tDIH
tHZD
DIN (0-9) Setup to TCLK RL = 27Ω,
0
nS
nS
CL=10pF to GND
DIN (0-9) Hold from TCLK
4.0
Figure 7
DO HIGH to
RL = 27Ω,
CL=10pF to GND
Figure 8
3
3
10
10
10
10
nS
nS
nS
nS
TRI-STATE Delay
DO LOW to TRI-STATE
Delay
tLZD
tZHD
tZLD
(Note 5)
DO TRI-STATE to
HIGH Delay
5
DO TRI-STATE to LOW
Delay
6.5
tSPW
tPLD
tSD
SYNC Pulse Width
Serializer PLL Lock Time
Serializer Delay
RL = 27Ω
Figure 10
5*tTCP
nS
nS
nS
510*tTCP
tTCP+ 1.0
513*tTCP
tTCP+ 3.5
RL = 27Ω, Figure 11
tTCP+ 2.5
7
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Serializer Switching Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
RL = 27Ω,
CL=10pF
to GND,
(Note 6)
Min
Typ
Max
Units
tDJIT
Deterministic Jitter
20
MHz
66
-300
-135
35
pS
-245
-40
19
160
25
pS
MHz
tRJIT
Random Jitter
RL = 27Ω,
CL=10pF to GND
pS (RMS)
Deserializer Timing Requirements for REFCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
tRFCP
Parameter
REFCLK Period
Conditions
Min
15.15
30
Typ
T
Max
Units
nS
50
70
tRFDC
tRFCP
tTCP
REFCLK Duty Cycle
Ratio of REFCLK to
TCLK
50
%
/
95
1
3
105
6
tRFTT
REFCLK Transition Time
nS
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Receiver out Clock
Period
Conditions
tRCP = tTCP
Figure 11
Pin/Freq.
Min
Typ
Max
Units
tRCP
RCLK
15.15
50
nS
tCLH
CMOS/TTL Low-to-High CL = 15 pF
Rout(0-9),
LOCK,
Transition Time
Figure 5
1.2
4
nS
RCLK
tCHL
tDD
CMOS/TTL High-to-Low
Transition Time
Deserializer Delay
Figure 12
1.1
4
nS
nS
nS
All Temp./ All Freq.
Room
1.75*tRCP+1.25
1.75*tRCP+2.25
1.75*tRCP+5.0
1.75*tRCP+5.0
1.75*tRCP+7.5
1.75*tRCP+6.5
Temp./3.3V/20MHz
Room
1.75*tRCP+2.25
0.4*tRCP
1.75*tRCP+5.0
0.5*tRCP
1.75*tRCP+6.5
nS
nS
nS
Temp./3.3V/66MHz
tROS
ROUT Data Valid before Figure 13
RCLK
20MHz
RCLK
RCLK
0.38*tRCP
0.5*tRCP
66MHz
tROH
ROUT Data valid after
RCLK
Figure 13
Figure 14
20MHz
66MHz
−0.4*tRCP
−0.38*tRCP
45
−0.5*tRCP
−0.5*tRCP
50
nS
nS
%
tRDC
tHZR
RCLK Duty Cycle
HIGH to TRI-STATE
Delay
55
10
Rout(0-9)
2.8
2.8
4.2
4.2
nS
nS
nS
nS
tLZR
tZHR
tZLR
LOW to TRI-STATE
Delay
10
10
10
TRI-STATE to HIGH
Delay
TRI-STATE to LOW
Delay
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8
Deserializer Switching Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Figure 15
Pin/Freq.
Min
Typ
Max
Units
tDSR1 Deserializer PLL Lock
Time from PWRDWN
20MHz
2.6
4
µS
Figure 16
66MHz
0.84
3
µS
(with SYNCPAT)
(Note 7)
tDSR2 Deserializer PLL Lock
time from SYNCPAT
20MHz
66MHz
1
2
µS
µS
0.29
0.8
tZHLK TRI-STATE to HIGH
Delay (power-up)
LOCK
3.7
1.6
400
12
nS
nS
pS
tRNM
Deserializer Noise
Margin
Figure 17
20
MHz
66
1.0
(Note 8)
250
MHz
SCAN Circuitry Timing Requirements
Symbol
Parameter
Maximum TCK Clock
Frequency
Conditions
Min
Typ
Max
Units
fMAX
RL = 500Ω, CL = 35 pF
25.0
50.0
MHz
tS
TDI to TCK, H or L
TDI to TCK, H or L
TMS to TCK, H or L
TMS to TCK, H or L
TCK Pulse Width, H or L
TRST Pulse Width, L
Recovery Time, TRST to
TCK
1.0
2.0
2.5
1.5
10.0
2.5
2.0
ns
ns
ns
ns
ns
ns
ns
tH
tS
tH
tW
tW
tREC
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Typical values are given for V
= 3.3V and T = +25˚C.
A
CC
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground except VOD, ∆VOD,
VTH and VTL which are differential voltages.
Note 4: t
and t
specifications are Guaranteed By Design (GBD) using statistical analysis.
LHLT
LLHT
Note 5: Because the Serializer is in TRI-STATE mode, the Deserializer will lose PLL lock and have to resynchronize before data transfer.
Note 6: t specifications are Guaranteed By Design using statistical analysis.
DJIT
Note 7: For the purpose of specifying deserializer PLL performance, tDSR1 and tDSR2 are specified with the REFCLK running and stable, and with specific
conditions for the incoming data stream (SYNCPATs). It is recommended that the derserializer be initialized using either t timing or t timing. t is the
DSR1
DSR2
DSR1
time required for the deserializer to indicate lock upon power-up or when leaving the power-down mode. Synchronization patterns should be sent to the device before
initiating either condition. t is the time required to indicate lock for the powered-up and enabled deserializer when the input (RI+ and RI-) conditions change from
DSR2
not receiving data to receiving synchronization patterns (SYNCPATs).
Note 8: t is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors occur. The Deserializer Noise
RNM
Margin is Guaranteed By Design (GBD) using statistical analysis.
9
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AC Timing Diagrams and Test
Circuits
20000103
FIGURE 2. “Worst Case” Serializer ICC Test Pattern
20000104
FIGURE 3. “Worst Case” Deserializer ICC Test Pattern
20000105
FIGURE 4. Serializer Bus LVDS Output Load and Transition Times
20000106
FIGURE 5. Deserializer CMOS/TTL Output Load and Transition Times
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10
AC Timing Diagrams and Test Circuits (Continued)
20000107
FIGURE 6. Serializer Input Clock Transition Time
20000108
Timing shown for TCLK_R/F = LOW
FIGURE 7. Serializer Setup/Hold Times
20000109
FIGURE 8. Serializer TRI-STATE Test Circuit and Timing
11
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AC Timing Diagrams and Test Circuits (Continued)
20000110
FIGURE 9. Serializer PLL Lock Time, and PWRDN TRI-STATE Delays
20000123
FIGURE 10. SYNC Timing Delays
20000111
FIGURE 11. Serializer Delay
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12
AC Timing Diagrams and Test Circuits (Continued)
20000112
FIGURE 12. Deserializer Delay
20000113
Timing shown for RCLK_R/F = LOW
Duty Cycle (t
) =
RDC
FIGURE 13. Deserializer Data Valid Out Times
20000114
FIGURE 14. Deserializer TRI-STATE Test Circuit and Timing
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AC Timing Diagrams and Test Circuits (Continued)
20000115
FIGURE 15. Deserializer PLL Lock Times and PWRDN TRI-STATE Delays
20000122
FIGURE 16. Deserializer PLL Lock Time from SyncPAT
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14
AC Timing Diagrams and Test Circuits (Continued)
20000121
SW - Setup and Hold Time (Internal Data Sampling Window)
t
t
- Serializer Output Bit Position Jitter that results from Jitter on TCLK
= Receiver Noise Margin Time
DJIT
RNM
FIGURE 17. Receiver Bus LVDS Input Skew Margin
20000116
+
−
V
= (DO )–(DO ).
OD
Differential output signal is shown as (DO+)–(DO−), device in Data Transfer mode.
FIGURE 18. VOD Diagram
15
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clock information be received 4 times in a row to indicate
loss of lock. Since clock information has been lost, it is
possible that data was also lost during these cycles. There-
fore, after the Deserializer relocks to the incoming data
stream and the Deserializer LOCK pin goes low, at least
three previous data cycles should be suspect for bit errors.
Application Information
USING THE SCAN921023 AND SCAN921224
The Serializer and Deserializer chipset is an easy to use
transmitter and receiver pair that sends 10 bits of parallel
LVTTL data over a serial Bus LVDS link up to 660 Mbps. An
on-board PLL serializes the input data and embeds two clock
bits within the data stream. The Deserializer uses a separate
reference clock (REFCLK) and an onboard PLL to extract
the clock information from the incoming data stream and
then deserialize the data. The Deserializer monitors the
incoming clock information, determines lock status, and as-
serts the LOCK output high when loss of lock occurs.
The Deserializer can relock to the incoming data stream by
making the Serializer resend SYNC patterns, as described
above, or by random locking, which can take more time,
depending on the data patterns being received.
HOT INSERTION
All the BLVDS devices are hot pluggable if you follow a few
rules. When inserting, ensure the Ground pin(s) makes con-
tact first, then the VCC pin(s), and then the I/O pins. When
removing, the I/O pins should be unplugged first, then the
VCC, then the Ground. Random lock hot insertion is illus-
trated in Figure 21 .
POWER CONSIDERATIONS
An all CMOS design of the Serializer and Deserializer makes
them inherently low power devices. In addition, the constant
current source nature of the Bus LVDS outputs minimizes
the slope of the speed vs. ICC curve of conventional CMOS
designs.
PCB CONSIDERATIONS
The Bus LVDS Serializer and Deserializer should be placed
as close to the edge connector as possible. In multiple
Deserializer applications, the distance from the Deserializer
to the slot connector appears as a stub to the Serializer
driving the backplane traces. Longer stubs lower the imped-
ance of the bus, increase the load on the Serializer, and
lower the threshold margin at the Deserializers. Deserializer
devices should be placed much less than one inch from slot
connectors. Because transition times are very fast on the
Serializer Bus LVDS outputs, reducing stub lengths as much
as possible is the best method to ensure signal integrity.
POWERING UP THE DESERIALIZER
The SCAN921224 can be powered up at any time by follow-
ing the proper sequence. The REFCLK input can be running
before the Deserializer powers up, and it must be running in
order for the Deserializer to lock to incoming data. The
Deserializer outputs will remain in TRI-STATE until the De-
serializer detects data transmission at its inputs and locks to
the incoming data stream.
TRANSMITTING DATA
Once you power up the Serializer and Deserializer, they
must be phase locked to each other to transmit data. Phase
locking occurs when the Deserializer locks to incoming data
or when the Serializer sends patterns. The Serializer sends
SYNC patterns whenever the SYNC1 or SYNC2 inputs are
high. The LOCK output of the Deserializer remains high until
it has locked to the incoming data stream. Connecting the
LOCK output of the Deserializer to one of the SYNC inputs of
the Serializer will guarantee that enough SYNC patterns are
sent to achieve Deserializer lock.
TRANSMISSION MEDIA
The Serializer and Deserializer can also be used in point-to-
point configuration of a backplane, through a PCB trace, or
through twisted pair cable. In point-to-point configuration, the
transmission media need only be terminated at the receiver
end. Please note that in point-to-point configuration, the
potential of offsetting the ground levels of the Serializer vs.
the Deserializer must be considered. Also, Bus LVDS pro-
vides a +/− 1.2V common mode range at the receiver inputs.
The Deserializer can also lock to incoming data by simply
powering up the device and allowing the “random lock”
circuitry to find and lock to the data stream.
FAILSAFE BIASING FOR THE SCAN921224
The SCAN921224 has an improved input threshold sensitiv-
ity of +/− 50mV versus +/− 100mV for the DS92LV1210 or
DS92LV1212. This allows for greater differential noise mar-
gin in the SCAN921224. However, in cases where the re-
ceiver input is not being actively driven, the increased sen-
sitivity of the SCAN921224 can pickup noise as a signal and
cause unintentional locking. For example, this can occur
when the input cable is disconnected.
While the Deserializer LOCK output is low, data at the De-
serializer outputs (ROUT0-9) is valid, except for the specific
case of loss of lock during transmission which is further
discussed in the "Recovering from LOCK Loss" section be-
low.
NOISE MARGIN
External resistors can be added to the receiver circuit board
to prevent noise pick-up. Typically, the non-inverting receiver
input is pulled up and the inverting receiver input is pulled
down by high value resistors. the pull-up and pull-down
resistors (R1 and R2) provide a current path through the
termination resistor (RL) which biases the receiver inputs
when they are not connected to an active driver. The value of
the pull-up and pull-down resistors should be chosen so that
enough current is drawn to provide a +15mV drop across the
termination resistor. Please see Figure 19 for the Failsafe
Biasing Setup.
The Deserializer noise margin is the amount of input jitter
(phase noise) that the Deserializer can tolerate and still
reliably receive data. Various environmental and systematic
factors include:
Serializer: TCLK jitter, VCC noise (noise bandwidth and
out-of-band noise)
Media: ISI, Large VCM shifts
Deserializer: VCC noise
RECOVERING FROM LOCK LOSS
In the case where the Deserializer loses lock during data
transmission, up to 3 cycles of data that were previously
received can be invalid. This is due to the delay in the lock
detection circuit. The lock detect circuit requires that invalid
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16
The parameter tRNM is calculated by first measuring how
much of the ideal bit the receiver needs to ensure correct
sampling. After determining this amount, what remains of the
ideal bit that is available for external sources of noise is
called tRNM. It is the offset from tDJIT(min or max) for the test
mask within the eye opening.
Application Information (Continued)
USING TDJIT AND TRNM TO VALIDATE SIGNAL
QUALITY
The parameters tDJIT and tRNM can be used to generate an
eye pattern mask to validate signal quality in an actual
application or in simulation.
The vertical limits of the mask are determined by the
SCAN921224 receiver input threshold of +/− 50mV.
The parameter tDJIT measures the transmitter’s ability to
place data bits in the ideal position to be sampled by the
receiver. The typical tDJIT parameter of −80pS indicates that
the crossing point of the Tx data is 80pS ahead of the ideal
crossing point. The tDJIT(min) and tDJIT(max) parameters
specify the earliest and latest, repectively, time that a cross-
ing will occur relative to the ideal position.
Please refer to the eye mask pattern of Figure 20 for a
graphic representation of tDJIT and tRNM
.
20000127
FIGURE 19. Failsafe Biasing Setup
20000128
FIGURE 20. Using tDJIT and tRNM to Generate an Eye Pattern Mask and Validate Signal Quality
17
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Application Information (Continued)
20000117
FIGURE 21. Random Lock Hot Insertion
Pin Diagrams
SCAN921023SLC - Serializer
(Top View)
20000130
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18
Pin Diagrams (Continued)
SCAN921224SLC - Deserializer
(Top View)
20000131
19
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Serializer Pin Description
Pin Name
I/O
Ball Id.
A3, B1, C1,
D1, D2, D3,
E1, E2, F2, F4
G3
Description
Data Input. LVTTL levels inputs. Data on these pins are loaded into
a 10-bit input register.
DIN
I
TCLKR/F
I
Transmit Clock Rising/Falling strobe select. LVTTL level input.
Selects TCLK active edge for strobing of DIN data. High selects
rising edge. Low selects falling edge.
DO+
DO−
DEN
O
O
I
D7
D5
D6
+ Serial Data Output. Non-inverting Bus LVDS differential output.
− Serial Data Output. Inverting Bus LVDS differential output.
Serial Data Output Enable. LVTTL level input. A low puts the Bus
LVDS outputs in TRI-STATE.
PWRDN
I
C7
Powerdown. LVTTL level input. PWRDN driven low shuts down the
PLL and TRI-STATEs outputs putting the device into a low power
sleep mode.
TCLK
SYNC
I
I
E4
Transmit Clock. LVTTL level input. Input for 20 MHz–66 MHz
system clock.
A4, B3
Assertion of SYNC (high) for at least 1024 synchronization symbols
to be transmitted on the Bus LVDS serial output. Synchronization
symbols continue to be sent if SYNC continues to be asserted. TTL
level input. The two SYNC pins are ORed.
DVCC
DGND
I
I
C3, C4, E5
A1, C2, F5,
E6, G4
A5, A6, B4,
B7, G5
B5, B6, C6,
E7, F7
Digital Circuit power supply.
Digital Circuit ground.
AVCC
AGND
I
I
Analog power supply (PLL and Analog Circuits).
Analog ground (PLL and Analog Circuits).
TDI
I
F1
Test Data Input to support IEEE 1149.1
Test Data Output to support IEEE 1149.1
Test Mode Select Input to support IEEE 1149.1
Test Clock Input to support IEEE 1149.1
Test Reset Input to support IEEE 1149.1
Leave open circuit, do not connect
TDO
TMS
TCK
TRST
N/C
O
G1
I
E3
I
I
F3
G2
N/A
A2, A7, B2,
C5, D4, F6,
G6, G7
Deserializer Pin Description
Pin Name
I/O
Ball Id.
A5, B4, B6,
C4, C7, D6,
F5, F7, G4, G5
B3
Description
ROUT
O
Data Output. 9 mA CMOS level outputs.
RCLKR/F
I
Recovered Clock Rising/Falling strobe select. TTL level input.
Selects RCLK active edge for strobing of ROUT data. High selects
rising edge. Low selects falling edge.
RI+
I
I
I
D2
C1
D3
+ Serial Data Input. Non-inverting Bus LVDS differential input.
− Serial Data Input. Inverting Bus LVDS differential input.
Powerdown. TTL level input. PWRDN driven low shuts down the
PLL and TRI-STATEs outputs putting the device into a low power
sleep mode.
RI−
PWRDN
LOCK
O
E1
LOCK goes low when the Deserializer PLL locks onto the
embedded clock edge. CMOS level output. Totem pole output
structure, does not directly support wired OR connections.
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20
Deserializer Pin Description (Continued)
Pin Name
I/O
Ball Id.
Description
RCLK
REN
O
E2
Recovered Clock. Parallel data rate clock recovered from
embedded clock. Used to strobe ROUT, CMOS level output.
Output Enable. TTL level input. When driven low, TRI-STATEs
ROUT0–ROUT9 and RCLK.
I
I
I
D1
DVCC
DGND
A7, B7, C5,
C6, D5
Digital Circuit power supply.
A1, A6, B5,
D7, E4, E7,
G3
Digital Circuit ground.
AVCC
I
I
I
B1, C2, F1,
F2, G1
Analog power supply (PLL and Analog Circuits).
Analog ground (PLL and Analog Circuits).
AGND
A4, B2, F3,
F4, G2
REFCLK
A3
Use this pin to supply a REFCLK signal for the internal PLL
frequency.
TDI
I
F6
G6
G7
E5
E6
Test Data Input to support IEEE 1149.1
Test Data Output to support IEEE 1149.1
Test Mode Select Input to support IEEE 1149.1
Test Clock Input to support IEEE 1149.1
Test Reset Input to support IEEE 1149.1
TDO
TMS
TCK
TRST
N/C
O
I
I
I
N/A
A2, C3, D4, E3 Leave open circuit, do not connect
Deserializer Truth Table
INPUTS
OUTPUTS
PWRDN
REN
ROUT [0:9]
LOCK
RCLK
H (4)
H
H
X
L
Z
Active
Z
H
L
Z
Active
Z
H
L
Z
H
Z
Active
Z
1) LOCK Active indicates the LOCK output will reflect the state of the Deserializer with regard to the selected data stream.
2) RCLK Active indicates the RCLK will be running if the Deserializer is locked. The Timing of RCLK with respect to ROUT is determined by RCLK_R/F.
3) ROUT and RCLK are TRI-STATED when LOCK is asserted High.
4) During Power-up.
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Physical Dimensions inches (millimeters)
unless otherwise noted
Order Number SCAN921023SLC or SCAN921224SLC
NS Package Number SLC49A
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
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WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR
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1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and whose failure to perform when
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provided in the labeling, can be reasonably expected to result
in a significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
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