SCANSTA476TSD/NOPB [TI]
8 输入 IEEE 1149.1 模拟电压监控器 | NHQ | 16 | -40 to 85;型号: | SCANSTA476TSD/NOPB |
厂家: | TEXAS INSTRUMENTS |
描述: | 8 输入 IEEE 1149.1 模拟电压监控器 | NHQ | 16 | -40 to 85 监控 光电二极管 |
文件: | 总12页 (文件大小:324K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SCANSTA476
www.ti.com
SNLS171G –JANUARY 2005–REVISED APRIL 2013
SCANSTA476 Eight Input IEEE 1149.1 Analog Voltage Monitor
Check for Samples: SCANSTA476
1
FEATURES
DESCRIPTION
The SCANSTA476 is a low power, Analog Voltage
Monitor used for sampling or monitoring up to 8
analog/mixed-signal input channels. Analog Voltage
Monitors are valuable during product development,
environmental test, production, and field service for
verifying and monitoring power supply and reference
voltages. In a supervisory role, the 'STA476 is useful
for card or system-level health monitoring and
prognostics applications.
2
•
•
•
•
•
Eight Selectable Analog Input Channels
Analog Full-Scale Input Range 0V to VDD
Typical Accuracy of 2 mV at Maximum VDD
Very Low Power Operation
Small Package Footprint in 16-Lead, 5 x 5 x 0.8
mm WSON
•
•
Single +2.7V to +5.5V Supply Operation
IEEE 1149.1 (JTAG) Compliant Interface
Instead of requiring an external microcontroller with a
GPIO interface, the 'STA476 features a common
IEEE 1149.1 (JTAG) interface to select the analog
input, initiate a measurement, and access the results
- further extending the capabilities of an existing
JTAG infrastructure.
APPLICATIONS
•
•
•
•
Measurement of Point Voltages
Real-time Signal Monitoring
System Health Monitoring and Prognostics
The SCANSTA476 uses the VREF input as
a
Debug, Environmental Test, Production Test,
Field Service
reference. This enables the SCANSTA476 to operate
with a full-scale input range of 0 to VDD, which can
range from +2.7V to +5.5V.
•
•
Supplement In-Circuit Tester (ICT) Access
Vital in Servers, Computing,
Telecommunication and Industrial Equipment
The SCANSTA476 is packaged in a 16-lead non-
pullback WSON package that provides an extremely
small footprint for applications where space is a
critical consideration. This product operates over the
industrial temperature range of −40°C to +85°C.
•
Essential in Medical, Data Storage, and
Networking Equipment
Block Diagram
V
REF
A0
A1
A2
A3
A4
A5
A6
A7
Successive
Approximation
ADC
Control
Logic
IEEE 1149.1
TAP (JTAG)
TDI TDO TCK TMS TRST
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2013, Texas Instruments Incorporated
SCANSTA476
SNLS171G –JANUARY 2005–REVISED APRIL 2013
www.ti.com
Connection Diagram
V
A0
A1
A2
A3
A4
A5
A6
A7
DD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VREF
V
DD
TRST
TDO
TDI
DAP
(GND)
TMS
TCK
Figure 1. DAP = GND
(Top View)
Pin Descriptions
Pin No.
Symbol
Description
ANALOG I/O
16
15
14
13
12
11
10
9
A0
A1
Analog input 0. This signal can range from 0V to VREF
Analog input 1. This signal can range from 0V to VREF
Analog input 2. This signal can range from 0V to VREF
Analog input 3. This signal can range from 0V to VREF
Analog input 4. This signal can range from 0V to VREF
Analog input 5. This signal can range from 0V to VREF
Analog input 6. This signal can range from 0V to VREF
Analog input 7. This signal can range from 0V to VREF
.
.
.
.
.
.
.
.
A2
A3
A4
A5
A6
A7
2
VREF
Analog reference voltage input. VREF must be ≤ VDD. This pin should be connected to a quiet source
(not directly to VDD) and bypassed to GND with 0.1 µF and 1 µF monolithic capacitors located within 1
cm of the VREF pin.
DIGITAL I/O
6
TDI
TDO
TMS
TCK
TRST
Test Data Input to support IEEE 1149.1 features
Test Data Ouput to support IEEE 1149.1 features
Test Mode Select to support IEEE 1149.1 features
Test Clock to support IEEE 1149.1 features
Test Reset to support IEEE 1149.1 features
5
7
8
4
POWER SUPPLY
Positive supply pin. These pins should be connected to a quiet +2.7V to +5.5V source and bypassed to
GND with 0.1 µF and 1 µF monolithic capacitors located within 1 cm of the power pin.
1,3
VDD
Ground reference for CMOS circuitry. DAP is the exposed metal contact at the bottom of the WSON
package. The DAP is used as the primary GND connection to the device. It should be connected to the
ground plane with at least 4 vias for optimal low-noise and thermal performance.
(1)
See
GND
(1) Note that GND is not an actual pin on the package, the GND is connected thru the DAP on the back side of the WSON package.
2
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SNLS171G –JANUARY 2005–REVISED APRIL 2013
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1)(2)
Absolute Maximum Ratings
Supply Voltage VDD
−0.3V to +6.5V
−0.3V to VDD+0.3V
-0.3V to VDD+0.3V
±10 mA
Voltage on Any Analog Pin to GND
Voltage on Any Digital Pin to GND
(3)
Input Current at Any Pin
ESD Susceptibility
Human Body Model
Machine Model
8000V
>250V
Soldering Temperature
Junction Temperature
Storage Temperature
Thermal Resistance, θJA
Thermal Resistance, θJC
Refer to AN-1187 (SNOA401)
+150°C
−65°C to +150°C
42°C/W
14.3°C/W
(1) Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be
impaired. Functional operability under any of these conditions is not implied. Exposure to maximum ratings for extended periods may
affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
(3) Except power supply pins.
Recommended Operating Conditions
Operating Temperature Range
−40°C ≤ TA ≤ +85°C
+2.7V to +5.5V
+0V to VDD
VDD Supply Voltage
Digital Input Pins Voltage Range
Analog Input Pins Voltage Range
(1)
+0V to VREF
(1) For valid measurements, the analog VIN < VREF ≤ VDD
.
SCANSTA476 Electrical Characteristics
The following specifications apply for VDD = +2.7V to 5.5V, fTCK = 20 MHz, unless otherwise noted.
Symbol
Parameter
Conditions
Typical
Limits
Units
POWER SUPPLY CHARACTERISTICS
2.7
5.5
5.0
V (min)
V (max)
mA
VDD
Supply Voltage
−40°C ≤ TA ≤ 85°C
Normal Mode (Static)
VDD = +2.7V to +5.5V,
3.5
IDD
VDD = +2.7V to +5.5V,
fTCK = 1 MSPS
Normal Mode (Operational)
5.0
mA (max)
mW (max)
Power Consumption, Normal Mode
(Operational)
PD
VDD = +5.5V, fTCK = 1 MSPS
27.5
ANALOG INPUT CHARACTERISTICS (A0-A7)
VIN
Analog Input Range
VREF ≤ VDD
0 to VREF
VDD
V
V
VREF
IDCL
Reference Voltage Range
DC Leakage Current
0.1
1
±10
µA (max)
VDD = +2.7V
VDD = +5.5V
7.5
VMEAS
Analog Input Measurement Accuracy
mV
2
15
DIGITAL INPUT CHARACTERISTICS (TDI, TMS, TCK, TRST)
VDD = +2.7V to +3.6V
VDD = +5.5V
2.0
2.1
VIH
Input High Voltage
V (min)
VIL
VCL
IIN
Input Low Voltage
Input Clamp Voltage
Input Current
VDD = +5V
0.8
V (max)
V (max)
µA (max)
ICL = -18mA
-0.8
0.2
-1.5
±10
VIN = 0V or VDD
Copyright © 2005–2013, Texas Instruments Incorporated
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SNLS171G –JANUARY 2005–REVISED APRIL 2013
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SCANSTA476 Electrical Characteristics (continued)
The following specifications apply for VDD = +2.7V to 5.5V, fTCK = 20 MHz, unless otherwise noted.
Symbol
Parameter
Conditions
TRST, TDI, TMS only
Typical
Limits
Units
IILR
Input Current
-300
µA (max)
DIGITAL OUTPUT CHARACTERISTICS (TDO)
IOH = -100 µA, 2.7V ≤ VDD ≤ 5.5V
IOH = -4 mA, 3.0V ≤ VDD ≤ 5.5V
IOH = -4 mA, VDD = 2.7V
V
DD −0.2
V (min)
V (min)
VOH
Output High Voltage
2.4
2.2
V (min)
IOL = 100 µA, 2.7V ≤ VDD ≤ 5.5V
IOL = 4 mA, 2.7V ≤ VDD ≤ 5.5V
VOUT = 0V, VDD = 5.5V
0.2
V (max)
V (max)
mA (max)
µA (max)
VOL
Output Low Voltage
0.4
IOS
IOZ
Output Short Circuit Current
TRI-STATE Leakage Current
Output Coding
-85
±10
Straight (Natural) Binary
AC ELECTRICAL CHARACTERISTICS
FMAX Throughput Rate
INPUT TIMING CHARACTERISTICS
TCK = 20MHz
1
MSPS (max)
(1)
tSET
tHOLD
tSET
tHOLD
tW
TDI to TCK (H/L)
TDI to TCK (H/L)
TMS to TCK (H/L)
TMS to TCK (H/L)
TCK Pulse Width (H/L)
Recovery TIme TRST to TCK
TRST Pulse Width (L)
TCK
See
2.0
1.5
2.0
2.0
10.0
2.0
2.5
20
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
MHz (min)
(1)
See
(1)
See
(1)
See
(1)
See
(1)
tREC
tW
See
(1)
See
FMAX
(1) Data sheet min/max specification limits are specified by design or statistical analysis.
APPLICATIONS INFORMATION
POWER-UP TIMING
The SCANSTA476 typically requires 1 µs to power up, either after first applying VDD, or after an incomplete
conversion shift. To return to normal, one "dummy" conversion must be fully completed. After this first dummy
conversion, the SCANSTA476 will perform conversions properly.
STARTUP MODE
When the VDD supply is first applied, the SCANSTA476 requires one dummy conversion after start-up.
4
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SNLS171G –JANUARY 2005–REVISED APRIL 2013
Timing Diagrams
JTAG Reset
JTAG Instruction Shift
SHIFT IR
(IDLE)
TAP
State
SEL
DR
SEL
IR
CAP
IR
EX1
IR
UPD
IR
TLR (Test-Logic-Reset)
RTI
RTI (Run-Test/Idle)
TCK
TRST
TMS
8-bit instruction register op-code (40h to 47h)
TDI
x
x
x
x
0
0
1
0
8-bit instruction register capture value (81h)
TDO
1
0
0
0
0
0
0
1
LSB
MSB
Op-codes 40h to 47h select pins A0 to A7 respectively.
Note the JTAG reset preamble places the JTAG TAP controller in a stable state (RTI). Both the instruction and data shifts start in - and return to - the RTI state
Figure 2. Instruction Shift (Channel Select)
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SNLS171G –JANUARY 2005–REVISED APRIL 2013
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(IDLE)
JTAG Data Shift
SHIFT DR
(IDLE)
RTI
UPD
DR
SEL CAP
DR DR
EX1
DR
TAP
State
RTI
TCK
TRST
TMS
TDI
(don‘t care)
TDO
0
0
0
0
D11 D10 D9
MSB
D8
D7
D6
D5
D4
D3
D2
D1
D0
LSB
D11 through D0 correspond to the 12-bit sample from the ADC Core.
Note that Data shifts can be run back-to-back for continous sampling of a single channel, or can be interleaved with instruction shifts for rippling through all 8 channels.
Figure 3. Data Shift (A/D Sample)
6
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SCANSTA476
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SNLS171G –JANUARY 2005–REVISED APRIL 2013
REVISION HISTORY
Changes from Revision F (April 2013) to Revision G
Page
•
Changed layout of National Data Sheet to TI format ............................................................................................................ 6
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SCANSTA476TSD/NOPB
ACTIVE
WSON
NHQ
16
1000 RoHS & Green
SN
Level-3-260C-168 HR
-40 to 85
STA476T
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SCANSTA476TSD/NOPB WSON
NHQ
16
1000
178.0
12.4
5.3
5.3
1.3
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
WSON NHQ 16
SPQ
Length (mm) Width (mm) Height (mm)
208.0 191.0 35.0
SCANSTA476TSD/NOPB
1000
Pack Materials-Page 2
MECHANICAL DATA
NHQ0016A
SDA16A (Rev A)
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