SE370C702_技术文档

TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

FZ AND FN PACKAGES

(TOP VIEW)

CMOS/EEPROM/EPROM Technologies on

a Single Device

– Mask-ROM Devices for High-Volume

Production

– One-Time-Programmable (OTP) EPROM

Devices for Low Volume Production

– Reprogrammable EPROM Devices for

Prototyping Purposes

Internal System Memory Configurations

– On-Chip Program Memory Versions

– ROM: 8K Bytes

4

3

2

1

28 27 26

25

5

XTAL2/CLKIN

SCITXD

SCICLK

SCIRXD

T1IC/CR

T1PWM

T1EVT

MC

6

XTAL1

A6

24

23

22

21

20

19

7

8

A5

9

A4

10

11

A3

A2

– EPROM: 8K Bytes

12 13 14 15 16 1718

– Data EEPROM: 256 Bytes

– Static RAM: 256 Bytes Usable as

Registers

Flexible Operating Features

– Low-Power Modes: STANDBY and HALT

– Commercial, Industrial, and Automotive

Temperature Ranges

Serial Communications Interface 1 (SCI1)

– Asynchronous Mode: 156K bps

Maximum at 5 MHz SYSCLK

– Isosynchronous Mode: 25M bps

Maximum at 5 MHz SYSCLK

– Clock Options

– Divide-by-4 (0.5 to 5 MHz SYSCLK)

– Divide-by-1 (2 to 5 MHz SYSCLK)

Phase-Locked Loop (PLL)

– Full Duplex, Double-Buffered Receiver

(RX) and Transmitter (TX)

– Two Multiprocessor Communication

Formats

– Supply Voltage (V ) 5 V ±10%

CC

TMS370 Series Compatibility

16-Bit General-Purpose Timer

– Software Configurable as

a 16-Bit Event Counter, or

– Register-to-Register Architecture

– 256 General-Purpose Registers

– 14 Powerful Addressing Modes

– Instructions Upwardly Compatible With

All TMS370 Devices

CMOS/TTL Compatible I/O Pins/Packages

– All Peripheral Function Pins Software

Configurable for Digital I/O

– 21 Bidirectional Pins, 1 Input Pin

– 28-Pin Plastic and Ceramic Leaded Chip

Carrier Packages

Workstation/Personal Computed-Based

Development System

a 16-Bit Pulse Accumulator, or

a 16-Bit Input Capture Functions, or

Two Compare Registers, or a

Self-Contained Pulse-Width-Modulation

(PWM) Function

– Software Programmable Input Polarity

– Eight-Bit Prescaler, Providing a 24-Bit

Real-Time Timer

On-Chip 24-Bit Watchdog Timer

– EPROM/OTP Devices: Standard

Watchdog

– Mask-ROM Devices: Hard Watchdog,

Simple Counter, or Standard Watchdog

Flexible Interrupt Handling

– Two Software-Programmable Interrupt

Levels

– C Compiler and C Source Debugger

– Real-time In-Circuit Emulation

– Extensive Breakpoint/Trace Capability

– Multi-Window User Interface

– Microcontroller Programmer

– Global- and Individual-Interrupt Masking

– Programmable Rising or Falling Edge

Detect

– Individual Interrupt Vectors

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

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TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

Pin Descriptions

28 PINS

LCC

†

DESCRIPTION

I/O

NAME

NO.

A0

A1

A2

A3

A4

A5

A6

A7

14

13

11

10

9

8

7

3

I / O

Port A is a general-purpose bidirectional I/O port.

D3

D4

D5

D6

D7

28

26

15

1

I / O

Port D is a general-purpose bidirectional I/O port. D3 is also configurable as SYSCLK.

2

INT1

INT2

INT3

16

17

18

I

External interrupt (non-maskable or maskable)/general-purpose input pin

External maskable interrupt input/general-purpose bidirectional pin

I / O

T1IC/CR

T1PWM

T1EVT

22

21

20

Timer1 input capture/counter reset input pin /general-purpose bidirectional pin

Timer1 PWM output pin/general-purpose bidirectional pin

Timer1 external event input pin/general-purpose bidirectional pin

I / O

‡

SCITXD

SCIRXD

SCICLK

25

23

24

SCI transmit data output pin, general-purpose bidirectional pin

SCI receive data input pin/general-purpose bidirectional pin

SCI bidirectional serial clock pin/general-purpose bidirectional pin

System reset bidirectional pin; as input pin, RESET initializes the microcontroller; as open-drain output,

RESET indicates that an internal failure was detected by watchdog or oscillator fault circuit.

RESET

MC

27

19

I / O

I

Mode control input pin; enables EEPROM write protection override (WPO) mode, also EPROM V

PP

XTAL2/CLKIN

XTAL1

5

6

I

O

Internal oscillator crystal input/External clock source input

Internal oscillator output for crystal

V

4

Positive supply voltage

Ground reference

CC

12

SS

†

‡

I = input, O = output

The three-pin SCI configuration is referred to as SCI1.

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TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

functional block diagram

XTAL2/

CLKIN

INT1

INT2

INT3

XTAL1

MC

RESET

Clock Options:

Divide-By-4 Or

Divide-By-1 (PLL)

System

Control

Interrupts

SCIRXD

SCITXD

SCICLK

Serial

Communications

Interface 1

RAM

256 Bytes

CPU

Program Memory

ROM: 8K Bytes

EPROM: 8K Bytes

Data EEPROM

0 or 256 Bytes

T1IC/CR

T1EVT

Timer 1

T1PWM

Watchdog

V

CC

Port A

8

Port D

V

SS

5

description

The TMS370C002, TMS370C302, TMS370C702, and SE370C702 devices are members of the TMS370 family

of single-chip 8-bit microcontrollers. Unless otherwise noted, the term TMS370Cx0x refers to these devices.

The TMS370 family provides cost-effective real-time system control through integration of advanced peripheral

function modules and various on-chip memory configurations.

The TMS370Cx0x family of devices is implemented using high-performance silicon-gate CMOS EPROM and

EEPROM technologies. Low-operating power, wide-operating temperature range, and noise immunity of

CMOS technology coupled with the high performance and extensive on-chip peripheral functions make the

TMS370Cx0x devices attractive in system designs for automotive electronics, industrial motors, computer

peripheral controls, telecommunications, and consumer applications.

All TMS370Cx0x devices contain the following on-chip peripheral modules:

Serial communications interface 1 (SCI1)

One 16-bit general-purpose timer with an 8-bit prescaler

One 24-bit general-purpose watchdog timer

Table 1 provides a memory configuration overview of the TMS370Cx0x devices.

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TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

description (continued)

Table 1. Memory Configurations

PROGRAM MEMORY

(BYTES)

DATA MEMORY

(BYTES)

DEVICE

28-PIN PACKAGE

ROM

EPROM

RAM

EEPROM

TMS370C002A

TMS370C302A

TMS370C702

8K

—

256

FN – PLCC

FZ – CLCC

8K

—

8K

—

256

†

SE370C702

256

†

System evaluators and development are for use only in prototype environment and their reliability has not been characterized.

The suffix letter (A) appended to the device name (shown in the first column of Table 1) indicates the

configuration of the device. ROM and EPROM devices have different configurations as indicated in Table 2.

ROM devices with the suffix letter A are configured through a programmable contact during manufacture.

Table 2. Suffix Letter Configuration

DEVICE

WATCHDOG TIMER

Standard

CLOCK

LOW-POWER MODE

EPROM without A

Divide-by-4 (standard oscillator)

Enabled

Standard

Divide-by-4 or

Divide-by-1 (PLL)

ROM A

Hard

Enabled or disabled

Simple

The 8K bytes of mask-programmable ROM in the associated TMS370Cx0x devices are replaced in the

TMS370C702 with 8K bytes of EPROM. All other available memory and on-chip peripherals are identical, with

the exception of no data EEPROM on the TMS370C302 devices. The one-time programmable (OTP)

(TMS370C702) device and reprogrammable device (SE370C702) are available.

TMS370C702 OTP devices are available in plastic packages. This microcontroller is effective to use for

immediate production updates for other members of the TMS370Cx0x family or for low-volume production runs

when the mask charge or cycle time for low-cost mask ROM devices is not practical.

The SE370C702 has a windowed ceramic package to allow reprogramming of the program EPROM memory

during the development-prototyping phase of design. The SE370C702 devices allow quick updates to

breadboards and prototype systems while iterating initial designs.

The TMS370Cx0x family provides two low-power modes (STANDBY and HALT) for applications where

low-power consumption is critical. Both modes stop all CPU activity (that is, no instructions are executed). In

the STANDBY mode, the internal oscillator and the general purpose timer remain active. In the HALT mode,

all device activity is stopped. The device retains all RAM data and peripheral configuration bits throughout both

low-power modes.

The TMS370Cx0x features advanced register-to-register architecture that allows direct arithmetic and logical

operations without requiring an accumulator (for example, ADD R24, R47; add the contents of register 24 to

the contents of register 47 and store the result in register 47). The TMS370Cx0x family is fully

instruction-set-compatible, providing easy transition between members of the TMS370 8-bit microcontroller

family.

The TMS370Cx0x devices have two operational modes of serial communications provided by the SCI1 module.

The SCI1 allows standard RS-232-C communications with other common data transmission equipment.

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TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

description (continued)

The TMS370Cx0x family provides the system designer with an economical, efficient solution to real-time control

applications. The TMS370 family compact development tool (CDT ) solves the challenge of efficiently

developing the software and hardware required to design the TMS370Cx0x into an ever-increasing number of

complex applications. The application source code can be written in assembly and C-language, and the output

code can be generated by the linker. The TMS370 family CDT development tool can communicate through a

standard RS-232-C interface with an existing personal computer. This allows the use of the personal computer

editors and software utilities already familiar to the designer. The TMS370 family CDT emphasizes ease-of-use

through extensive menus and screen windowing so that a system designer with minimal training can begin

developing software. Precise real-time in-circuit emulation and extensive symbolic debug and analysis tools

ensure efficient software and hardware implementation as well as reduced time-to-market cycle.

The TMS370Cx0x family together with the TMS370 family CDT370, design kit, starter kit, software tools, the

SE370C712 reprogrammable devices, comprehensive product documentation, and customer support provide

a complete solution to the needs of the system designer.

central processing unit (CPU)

The CPU used on the TMS370Cx0x device is the high-performance 8-bit TMS370 CPU module. The ’x0x

implements an efficient register-to-register architecture that eliminates the conventional accumulator

bottleneck. The complete ’x0x instruction map is shown in Table 15 in the TMS370Cx0x instruction set overview

section.

The ’370Cx0x CPU architecture provides the following components:

CPU registers:

A stack pointer that points to the last entry in the memory stack

A status register that monitors the operation of the instructions and contains the global interrupt enable bits

A program counter (PC) that points to the memory location of the next instruction to be executed

Figure 1 illustrates the CPU registers and memory blocks.

CDT is a trademark of Texas Instruments Incorporated.

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TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

central processing unit (CPU) (continued)

Program Counter

15

0

Legend:

C=Carry

Stack Pointer (SP)

7

0

N=Negative

Z=Zero

V=Overflow

IE2=Level 2 interrupts Enable

IE1=Level 1 interrupts Enable

Status Register (ST)

C

7

N

6

Z

5

V

4

IE2 IE1

3

2

1

0

RAM (Includes 256-Byte Registers File)

0000h

00FFh

0100h

100Fh

1010h

256-Byte RAM (0000h - 00FFh)

0000h

†

Reserved

R0(A)

R1(B)

Peripheral File

Reserved

0001h

0002h

0003h

105Fh

1060h

R2

R3

1EFFh

1F00h

256-Byte Data EEPROM

1FFFh

‡

2000h

5FFFh

6000h

Not Available

R127

007Fh

8K-Byte ROM/EPROM (6000h–7FFFh)

7FBFh

7FC0h

Interrupts and Reset Vectors;

Trap Vectors

R255

7FFFh

00FFh

†

‡

Reserved means the address space is reserved for future expansion.

Not available means the address space is not accessible.

Figure 1. Programmer’s Model

A memory map that includes:

256-byte general-purpose RAM that can be used for data memory storage, program instructions,

general-purpose register, or the stack

A peripheral file that provides access to all internal peripheral modules, system-wide control functions and

EEPROM/EPROM programming control

256-byte EEPROM module that provides in-circuit programmability and data retention in power-off

conditions

8K-byte ROM or 8K-byte EPROM program memory

stack pointer (SP)

The SP is an 8-bit CPU register. Stack operates as a last-in, first-out, read/write memory. The stack is used

typically to store the return address on subroutine calls as well as the status-register contents during interrupt

sequences.

The SP points to the last entry or top of the stack. The SP is incremented automatically before data is pushed

onto the stack and decremented after data is popped from the stack. The stack can be placed anywhere in the

on-chip RAM memory.

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TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

central processing unit (CPU) (continued)

status register (ST)

The ST monitors the operation of the instructions and contains the global-interrupt-enable bits. The ST register

includes four status bits (condition flags) and two interrupt-enable bits:

The four status bits indicate the outcome of the previous instruction; conditional instructions (for example,

the conditional jump instructions) use the status bits to determine program flow.

The two interrupt enable bits control the two interrupt levels.

The ST register, status-bit notation, and status-bit definitions are shown in Table 3.

Table 3. Status Registers (ST)

7

C

6

N

5

Z

4

V

3

2

1

0

IE2

IE1

Reserved

RW-0

R = read, W = write, 0 = value after reset

program counter (PC)

The contents of the PC point to the memory location of the next instruction to be executed. The PC consists

of two 8-bit registers in the CPU: the program counter high (PCH) and program counter low (PCL). These

registers contain the most significant byte and least significant byte of a 16-bit address.

During reset, the contents of the reset vector (7FFEh, 7FFFh) are loaded into the program counter. The PCH

(MSbyte of the PC) is loaded with the contents of memory location 7FFEh, and the PCL (LSbyte of the PC) is

loaded with the contents of memory location 7FFFh. Figure 2 shows this operation using an example value of

6000h as the contents of the reset vector.

Program Counter (PC)

Memory

PCH

60

PCL

00

0000h

60

00

7FFEh

7FFFh

Figure 2. Program Counter After Reset

memory map

The TMS370Cx0x architecture is based on the Von Neuman architecture, where the program memory and data

memory share a common address space. All peripheral input/output is memory mapped in this same common

address space. As shown in Figure 3, the TMS370Cx0x provides memory-mapped RAM, ROM, Data

EEPROM, input/output pins, peripheral functions, and system interrupt vectors.

The peripheral file contains all input/output port control, peripheral status and control, EEPROM, EPROM, and

system-wide control functions. The peripheral file is located between 1010h to 105Fh and is divided logically

intofiveperipheral-fileframesof16byteseach. Eachon-chipperipheralisassignedtoaseparateframethrough

which peripheral control and data information is passed.

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TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

central processing unit (CPU) (continued)

Peripheral File Control Registers

System Control

1010h–101Fh

1020h–102Fh

1030h–103Fh

1040h–104Fh

1050h–105Fh

0000h

Digital Port Control

256-Byte RAM

(Register File/Stack)

†

Reserved

00FFh

0100h

Timer 1 Peripheral Control

SCI1 Peripheral Control

†

Reserved

100Fh

1010h

Peripheral File

105Fh

1060h

†

Reserved

1EFFh

1F00h

Vectors

256-Byte Data EEPROM

1FFFh

2000h

Trap 15–0

7FC0h–7FDFh

7FE0h–7FEFh

‡

†

Not Available

Reserved

5FFFh

Serial Communications Interface TX 7FF0h–7FF1h

Serial Communications Interface RX 7FF2h–7FF3h

6000h

6FFFh

7000h

8K-Byte ROM/EPROM

(6000h–7FFFh)

Timer 1

7FF4h–7FF5h

7FF6h–7FF7h

7FF8h–7FF9h

7FFAh–7FFBh

7FFCh–7FFDh

7FFEh–7FFFh

77FFh

7800h

7FBFh

7FC0h

†

Reserved

Interrupts and Reset Vectors;

Trap Vectors

Interrupt 3

Interrupt 2

Interrupt 1

Reset

7FFFh

8000h

‡

Not Available

FFFFh

†

‡

Reserved means the address space is reserved for future expansion.

Not available means the address space is not accessible.

Figure 3. TMS370Cx0x Memory Map

RAM/register file (RF)

Locations within the RAM address space can serve as the RF, general-purpose read/write memory, program

memory, or the stack instructions. The TMS370Cx0x devices contain 256 bytes of internal memory-mapped

RAM beginning at location 0000h (R0) and continuing through location 00FFh (R255) which is shown in

Figure 1.

The first two registers, R0 and R1, are also called register A and B, respectively. Some instructions implicitly

use register A or B; for example, the instruction LDSP (load SP) assumes that the value to be loaded into the

stack pointer is contained in register B. Registers A and B are the only registers cleared on reset.

peripheral file (PF)

The TMS370Cx0x control registers contain all the registers necessary to operate the system and peripheral

modules on the device. The instruction set includes some instructions that access the PF directly. These

instructions designate the register by the number of the PF relative to 1000h, preceded by P0 for a hexadecimal

designator or P for a decimal designator. For example, the system control register 0 (SCCR0) is located at

address 1010h; its peripheral file hexadecimal designator is P010, and its decimal designator is P16. Table 4

shows the TMS370Cx0x PF address map.

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TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

peripheral file (PF) (continued)

Table 4. TMS370Cx0x Peripheral File Address Map

PERIPHERAL FILE

ADDRESS RANGE

DESCRIPTION

DESIGNATOR

P000–P00F

P010–P01F

P020–P02F

P030–P03F

P040–P04F

P050–P05F

P060–P0FF

1000h–100Fh

1010h–101Fh

1020h–102Fh

1030h–103Fh

1040h–104Fh

1050h–105Fh

1060h–10FFh

Reserved

System and EPROM/EEPROM control registers

Digital I/O port control registers

Reserved

Timer 1 registers

Serial communications interface registers

Reserved

data EEPROM

The TMS370Cx0x devices, containing 256 bytes of data EEPROM, have their memory mapped beginning at

location 1F00h and continuing through location 1FFFh. Writing to the data EEPROM module is controlled by

the data EEPROM control register (DEECTL) and the write-protection register (WPR). Programming algorithm

examples are available in the TMS370 Family User’s Guide (literature number SPNU127) or the TMS370

Family Data Manual (literature number SPNS014B). The data EEPROM features include the following:

Programming:

–

Bit-, byte-, and block-write/erase modes

Internal charge pump circuitry. No external EEPROM programming voltage supply is needed.

Control register: Data EEPROM programming is controlled by the DEECTL located in the PF frame

beginning at location P01A. See Table 5.

–

In-circuit programming capability. There is no need to remove the device to program.

Write protection. Writes to the data EEPROM are disabled during the following conditions.

–

Reset. All programming of the data EEPROM module is halted.

Write protection active. There is one write-protect bit per 32-byte EEPROM block.

Low-power mode operation

Write protection can be overridden by applying 12 V to MC.

Table 5. Data EEPROM and Program EPROM Control Registers Memory Map

ADDRESS

P01A

SYMBOL

DEECTL

—

NAME

Data EEPROM control register

Reserved

P01B

P01C

EPCTL

Program EPROM control register

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TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

program EPROM

The TMS370C702 device contains 8K bytes of EPROM, mapped, at location 6000h and continuing through

location 7FFFh as shown in Figure 3. Memory addresses 7FF0h through 7FFFh are reserved for interrupt and

reset vectors. Trap vectors, used with TRAP0 through TRAP15 instructions, are located between addresses

7FC0h and 7FDFh. Reading the program EPROM modules is identical to reading other internal memory. During

programming, the EPROM is controlled by the EPROM control register (EPCTL). The program EPROM module

features include:

Programming

–

In-circuit programming capability if V is applied to MC

PP

Control register: EPROM programming is controlled by the EPROM control register (EPCTL) located in

the peripheral file (PF) frame at location P01Ch as shown in Table 5.

Write protection: Writes to the program EPROM are disabled under the following conditions:

–

Reset halts all programming to the EPROM module.

Low-power modes

13 V not applied to MC

program ROM

The program read-only memory (ROM) consists of 8K bytes of mask-programmable ROM. The program ROM

is used for permanent storage of data or instructions. Memory addresses 7FF0h through 7FFFh are reserved

for interrupt and reset vectors. Trap vectors, used with TRAP0 through TRAP15 instructions, are located

between addresses 7FC0h and 7FDFh. Programming of the mask ROM is performed at the time of device

fabrication. Refer to Figure 3 for ROM memory map.

system reset

The system reset operation ensures an orderly start-up sequence for the TMS370Cx0x CPU-based device.

There are up to three different actions that can cause a system reset to the device. Two of these actions are

internally generated, while one (RESET pin) is controlled externally. These actions are as follows:

External RESET pin. A low-level signal can trigger an external reset. To ensure a reset, the external signal

should be held low for one SYSCLK cycle. Signals of less than one SYSCLK can generate a reset. See the

TMS370 Family User’s Guide (literature number SPNU127) for more information.

Watchdog (WD) timer. A watchdog-generated reset occurs if an improper value is written to the WD key

register, or if the re-initialization does not occur before the watchdog timer times out . See the TMS370

Family User’s Guide (literature number SPNU127) for more information.

Oscillator reset. Reset occurs when the oscillator operates outside the recommended operating range. See

the TMS370 Family User’s Guide (literature number SPNU127) for more information.

Once a reset source is activated, the external RESET pin is driven (active) low for a minimum of eight SYSCLK

cycles. This allows the ’x0x device to reset external system components. Additionally, if a cold start (V

is off

CC

for several hundred milliseconds) condition or oscillator failure occurs or the RESET pin is held low, then the

reset logic holds the device in a reset state for as long as these actions are active.

After a reset, the program can check the oscillator fault flag (OSC FLT FLAG, SCCR0.4), the cold start flag

(COLD START, SCCR0.7), and the watchdog reset (WD OVRFL INT FLAG, T1CTL2.5) to determine the source

of the reset. A reset does not clear these flags. Table 6 lists the reset sources.

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TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

system reset (continued)

Table 6. Reset Sources

REGISTER

SCCR0

ADDRESS

1010h

PF

BIT NO.

CONTROL BIT

COLD START

SOURCE OF RESET

Cold (power-up)

P010

P04A

7

4

5

SCCR0

1010h

OSC FLT FLAG

Oscillator out of range

Watchdog timer timeout

T1CTL2

104Ah

WD OVRFL INT FLAG

Once a reset is activated, the following sequence of events occurs:

1. The CPU registers are initialized: ST = 00h, SP = 01h (reset state).

2. Registers A and B are initialized to 00h (no other RAM is changed).

3. The contents of the LSbyte of the reset vector (07FFh) are read and stored in the PCL.

4. The contents of the MSbyte of the reset vector (07FEh) are read and stored in the PCH.

5. Program execution begins with an opcode fetch from the address pointed to the PC.

The reset sequence takes 20 SYSCLK cycles from the time the reset pulse is released until the first opcode

fetch. During a reset, RAM contents (except for registers A and B) remain unchanged, and the module control

register bits are initialized to their reset state.

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TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

interrupts

The TMS370 family software programmable interrupt structure permits flexible on-chip and external interrupt

configurations to meet real-time interrupt-driven application requirements. The hardware interrupt structure

incorporates two priority levels as shown in Figure 4. Interrupt level 1 has a higher priority than interrupt

level 2. The two priority levels can be masked independently by the global-interrupt mask bits (IE1 and IE2) of

the status register.

EXT INT 3

INT 3

EXT INT 2

INT 2

INT3 PRI

TIMER1

Overflow

INT2 PRI

Compare1

EXT INT1

CPU

Ext Edge

INT1

Compare2

Input Capture

Watchdog

NMI

Priority

Logic

INT1 PRI

T1 PRI

STATUS REG

IE1

IE2

Level 1 INT

Level 2 INT

Enable

SCI INT

TX

TXRDY

RX

RXPRI

BRKDT

TXPRI

RXRDY

Figure 4. Interrupt Control

Each system interrupt is configured independently to either the high- or low-priority chain by the application

program during system initialization. Within each interrupt chain, the interrupt priority is fixed by the position of

the system interrupt. However, since each system interrupt is configured selectively on either the high- or

low-priority interrupt chain, the application program can elevate any system interrupt to the highest priority.

Arbitration between the two priority levels is performed within the CPU. Arbitration within each of the priority

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interrupts (continued)

chains is performed within the peripheral modules to support interrupt expansion for future modules.

Pending-interrupts are serviced upon completion of current instruction execution, depending on their interrupt

mask and priority conditions.

The TMS370Cx0x has six hardware system interrupts(plusRESET)asshowninTable 7. Each system interrupt

has a dedicated vector located in program memory through which control is passed to the interrupt service

routines. A system interrupt can have multiple interrupt sources. All of the interrupt sources are individually

maskable by local interrupt enable control bits in the associated peripheral file. Each interrupt source FLAG bit

is individually readable for software polling or for determining which interrupt source generated the associated

system interrupt.

Three of the system interrupts are generated by on-chip peripheral functions, and three external interrupts are

supported. Software configuration of the external interrupts is performed through the INT1, INT2, and INT3

control registers in peripheral file frame 1. Each external interrupt is individually software configurable for input

polarity (rising or falling edge) for ease of system interface. External interrupt INT1 is software configurable as

either a maskable or non-maskable interrupt. When INT1 is configured as non-maskable, it cannot be masked

by the individual- or global-enable-mask bits. The INT1 NMI bit is protected during non-privileged operation and,

therefore, should be configured during the initialization sequence following reset. To maximize pin flexibility,

external interrupts INT2 and INT3 can be software-configured as general-purpose input/output pins if the

interrupt function is not required (INT1 can be similarly configured as an input pin).

Table 7. Hardware System Interrupts

SYSTEM

INTERRUPT

VECTOR

ADDRESS

†

INTERRUPT SOURCE

External RESET

Watchdog Overflow

Oscillator Fault Detect

INTERRUPT FLAG

COLD START

WD OVRFL INT FLAG

OSC FLT FLAG

PRIORITY

‡

RESET

7FFEh, 7FFFh

1

‡

External INT1

External INT2

External INT3

INT1 FLAG

INT2 FLAG

INT3 FLAG

INT1

INT2

INT3

7FFCh, 7FFDh

7FFAh, 7FFBh

7FF8h, 7FF9h

2

3

4

Timer 1 Overflow

T1 OVRFL INT FLAG

T1C1 INT FLAG

T1C2 INT FLAG

T1EDGE INT FLAG

T1IC1 INT FLAG

WD OVRFL INT FLAG

Timer 1 Compare 1

Timer 1 Compare 2

Timer 1 External Edge

Timer 1 Input Capture 1

Watchdog Overflow

§

T1INT

7FF4h, 7FF5h

5

SCI RX Data Register Full

SCI RX Break Detect

RXRDY FLAG

BRKDT FLAG

‡

RXINT

7FF2h, 7FF3h

7FF0h, 7FF1h

6

7

SCI TX Data Register Empty

TXRDY FLAG

TXINT

†

‡

§

Relative priority within an interrupt level

Release microcontroller from STANDBY and HALT low-power modes.

Release microcontroller from STANDBY low-power mode.

privileged operation and EEPROM write protection override

The TMS370Cx0x family has significant flexibility to enable the designer to software configure the system and

peripherals to meet the requirements of a variety of applications. The nonprivileged mode of operation ensures

the integrity of the system configuration, once it is defined for an application. Following a hardware reset, the

TMS370Cx0x operates in the privileged mode, where all peripheral file registers have unrestricted read/write

access, and the application program configures the system during the initialization sequence following reset.

As the last step of system initialization, the PRIVILEGE DISABLE bit (SCCR2.0) is set to 1 to enter the

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privileged operation and EEPROM WPO (continued)

nonprivileged mode, thus disabling write operations to specific configuration control bits within the peripheral

file. Table8liststhesystemconfigurationbitswhicharewrite-protectedduringthenonprivilegedmodeandmust

be configured by software prior to exiting the privileged mode.

Table 8. Privileged Bits

†

REGISTER

CONTROL BIT

PF AUTO WAIT

NAME

LOCATION

P010.5

P010.6

SCCR0

OSC POWER

P011.2

P011.4

MEMORY DISABLE

AUTOWAIT DISABLE

SCCR1

SCCR2

P012.0

P012.1

P012.3

P012.4

P012.6

P012.7

PRIVILEGE DISABLE

INT1 NMI

CPU STEST

BUS STEST

PWRDWN/IDLE

HALT/STANDBY

P05F.4

P05F.5

P05F.6

P05F.7

SCI ESPEN

SCIRX PRIORITY

SCITX PRIORITY

SCI STEST

SCIPRI

T1PRI

P04F.6

P04F.7

T1 PRIORITY

T1 STEST

†

The privileged bits are shown in a bold typeface in Table 10.

The write protect override (WPO) mode is an external hardware method of overriding the write protection

registers (WPR) of data EEPROM on the TMS370Cx0x. WPO mode is entered by applying a 12-V input to the

MC pin after the RESET pin input goes high (logic 1). The high voltage (+ 12 V) on the MC pin during the WPO

mode is not the programming voltage for the data EEPROM or program EPROM. All EEPROM programming

voltages are generated on-chip. The WPO mode provides hardware system level capability to modify the

content of data EEPROM while the device remains in the application but only while requiring a 12-V external

input on the MC pin (normally not available in the end application except in a service or diagnostic environment).

low-power and IDLE modes

The TMS370Cx0x devices have two low-power modes (STANDBY and HALT) and an IDLE mode. For

mask-ROM devices, low-power modes can be disabled permanently through a programmable contact at the

time the mask is manufactured.

The STANDBY and HALT low-power modes significantly reduce power consumption by reducing or stopping

the activity of the various on-chip peripherals when processing is not required. Each of the low-power modes

is entered by executing the IDLE instruction when the PWRDWN/IDLE bit in SCCR2 has been set to 1. The

HALT/STANDBY bit in SCCR2 controls the low-power mode selection.

In the STANDBY mode (HALT/STANDBY = 0), all CPU activity and most peripheral module activity stops;

however, the oscillator, internal clocks, timer 1 and the receive-start bit detection circuit of the serial

communications interface remain active. System processing is suspended until a qualified interrupt (hardware

RESET, external interrupt on INT1, INT2, INT3, timer 1 interrupt, or low level on the receive pin of the SCI1) is

detected.

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low-power and IDLE modes (continued)

In the HALT mode (HALT/STANDBY = 1), the TMS370Cx0x is placed in its lowest power-consumption mode.

The oscillator and internal clocks are stopped, causing all internal activity to be halted. System activity is

suspended until a qualified interrupt (hardware RESET, external interrupt on the INT1, INT2, INT3, or low level

on the receive pin of the SCI1) is detected. The power-down mode selection bits are summarized in Table 9.

Table 9. Low-Power/Idle Control Bits

POWER-DOWN CONTROL BITS

MODE SELECTED

PWRDWN/IDLE

(SCCR2.6)

HALT/STANDBY

(SCCR2.7)

1

0

1

STANDBY

HALT

1

0

†

X

IDLE

†

Don’t care

When low-power modes are disabled through a programmable contact in the mask-ROM devices, writing to the

SCCR2.6-7 bits are ignored. In addition, if an idle instruction executes when low-power modes are disabled

through a programmable contact, the device always enters the IDLE mode.

To provide a method of always exiting low-power modes for mask-ROM devices, INT1 is enabled automatically

as a nonmaskable interrupt (NMI) during low-power modes when the hard watchdog mode is selected. This

means that the NMI is generated always, regardless of the interrupt enable flags.

The following information is preserved throughout both the STANDBY and HALT modes: RAM (register file),

CPUregisters(stackpointer, program counter, andstatusregister), I/Opindirectionandoutputdata, andstatus

registers of all on-chip peripheral functions. Since all CPU instruction processing stops during the STANDBY

and HALT modes, the clocking of the watchdog timer is inhibited.

clock modules

The ’x0x family provides two clock options that are referred to as divide-by-1 (phase-locked loop) and

divide-by-4 (standard oscillator). Both the divide-by-1 and divide-by-4 options are configurable during the

manufacturing process of a TMS370 microcontroller. The ’x0x ROM-masked devices offer both options to meet

system engineering requirements. Only one of the two clock options is allowed on each ROM device. The ’702A

EPROM has only the divide-by-4.

The divide-by-1 clock module option provides the capability for reduced electromagnetic interference (EMI) with

no added cost.

The divide-by-1 clock module option provides a one-to-one match of the external resonator frequency (CLKIN)

to the internal system clock (SYSCLK) frequency, whereas the divide-by-4 option produces a SYSCLK which

is one-fourth of the frequency of the external resonator. Inside of the divide-by-1 module, the frequency of the

external resonator is multiplied by four, and the clock module then divides the resulting signal by four to provide

the four-phased internal system clock signals. The resulting SYSCLK is equal to the resonator frequency.

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clock modules (continued)

These are formulated as follows:

external resonator frequency

CLKIN

4

Divide-by-4 : SYSCLK

Divide-by-1 : SYSCLK

4

external resonator frequency

4

CLKIN

The main advantage of choosing a divide-by-1 oscillator is the improved EMI performance. The harmonics of

low-speed resonators extend through less of the emissions spectrum than the harmonics of faster resonators.

The divide-by-1 option provides the capability of reducing the resonator speed by four times, resulting in a

steeper decay of emissions produced by the oscillator.

system configuration registers

Table 10 contains system configuration and control functions and registers for controlling EEPROM

programming. The privileged bits are shown in a bold typeface and shaded areas.

Table 10. Peripheral File Frame 1: System Configuration Registers

PF

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

COLD

START

OSC

POWER

PF AUTO

WAIT

OSC FLT

FLAG

MC PIN

WPO

MC PIN

DATA

µP/µC

MODE

P010

—

SCCR0

AUTO

WAIT

DISABLE

MEMORY

DISABLE

P011

—

SCCR1

SCCR2

HALT/

STANDBY

PWRDWN/

IDLE

BUS

STEST

CPU

STEST

INT1

NMI

PRIVILEGE

DISABLE

P012

—

P013

to

Reserved

P016

INT1

FLAG

INT1

PIN DATA

INT1

POLARITY

INT1

PRIORITY

INT1

ENABLE

P017

P018

P019

—

INT1

INT2

FLAG

INT2

PIN DATA

INT2

DATA DIR

INT2

DATA OUT

INT2

POLARITY

INT2

PRIORITY

INT2

ENABLE

INT3

FLAG

INT3

PIN DATA

INT3

DATA DIR

INT3

DATA OUT

INT3

POLARITY

INT3

PRIORITY

INT3

ENABLE

—

INT3

P01A

P01B

P01C

BUSY

—

AP

—

W1W0

W0

EXE

DEECTL

Reserved

VPPS

—

EPCTL

P01D

P01E

P01F

Reserved

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digital port control registers

Peripheral file frame 2 contains the digital I/O pin configuration and control registers. Table 11showsthespecific

addresses, registers, and control bits within this peripheral file frame.

Table 11. Peripheral File Frame 2: Digital Port Control Registers

PF

P020

P021

P022

P023

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

Reserved

BIT 2

BIT 1

BIT 0

REG

APORT1

APORT2

ADATA

ADIR

Port A Control Register 2 (must be 0)

Port A Data

Port A Direction

P024

to

Reserved

P02B

P02C

P02D

P02E

P02F

Port D Control Register 1 (must be 0)

—

DPORT1

DPORT2

DDATA

DDIR

†

Port D Control Register 2 (must be 0)

Port D Data

Port D Direction

†

To configure pin D3 as SYSCLK, set port D control register 2 = 08h.

Table 12. Port Configuration Register Setup

abcd

00q1

abcd

00y0

PORT

A

D

0 – 7

3 – 7

Data OUT q

Data In y

a = Port x Control Register 1

b = Port x Control Register 2

c = Data

d = Direction

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programmable timer 1

The programmable Timer 1 (T1) module of the TMS370Cx0x provides the designer with the enhanced timer

resources required to perform real-time system control. The T1 module contains the general-purpose timer and

the watchdog (WD) timer. The two independent 16-bit timers (T1 and WD) allow program selection of input clock

sources (real-time, external event, or pulse accumulate) with multiple 16-bit registers (input capture and

compare) for special timer function control. The timer 1 module includes three external device pins that can be

used for multiple counter functions (operation mode dependent) or used as general-purpose I/O pins. The T1

module block diagram is shown in Figure 5.

Edge

Select

16-Bit

Capt/Comp

T1IC/CR

Register

16-Bit

Counter

PWM

Toggle

MUX

T1PWM

16

16-Bit

Compare

Register

Interrupt

Logic

8-Bit

Prescaler

T1EVT

Interrupt

Logic

16-Bit

MUX

Watchdog Counter

(Aux. Timer)

Figure 5. Timer 1 Block Diagram

Three T1 I/O pins

–

T1IC/CR: Timer 1 input capture / counter reset input pin, or general-purpose bidirectional I/O pin

T1PWM: Timer 1 pulse-width-modulation (PWM) output pin, or general-purpose bidirectional I/O pin

T1EVT: Timer 1 event input pin, or general-purpose bidirectional I/O pin

–

Two operation modes:

–

Dual-compare mode: Provides PWM signal

Capture/compare mode: Provides input capture pin

One 16-bit general-purpose resettable counter

One 16-bit compare register with associated compare logic

One 16-bit capture/compare register, which, depending on the mode of operation, operates as either a

capture or compare register.

One 16-bit watchdog counter can be used as an event counter, a pulse accumulator, or an interval timer

if watchdog feature is not needed.

Prescaler/clock sources that determine one of eight clock sources for general-purpose timer

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programmable timer 1 (continued)

Selectable edge-detection circuitry that, depending on the mode of operation, senses active transitions on

the input capture pins (T1IC1/CR)

Interrupts that can be generated on the occurrence of:

–

A capture

A compare equal

A counter overflow

An external edge detection

Sixteen timer 1 module control registers located in the PF frame beginning at address P040.

The T1 module control registers are illustrated in Table 13.

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programmable timer 1 (continued)

Table 13. Timer 1 Module Register Memory Map

PF

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

Modes: Dual-Compare and Capture/Compare

P040 Bit 15

P041 Bit 7

P042 Bit 15

P043 Bit 7

P044 Bit 15

P045 Bit 7

P046 Bit 15

P047 Bit 7

P048 Bit 7

T1Counter MSbyte

T1 Counter LSbyte

Bit 8 T1CNTR

Bit 0

Compare Register MSbyte

Compare Register LSbyte

Bit 8 T1C

Bit 0

Capture/Compare Register MSbyte

Capture/Compare Register LSbyte

Watchdog Counter MSbyte

Watchdog Counter LSbyte

Watchdog Reset Key

Bit 8 T1CC

Bit 0

Bit 8 WDCNTR

Bit 0

Bit 0 WDRST

WD OVRFL WD INPUT

WD INPUT

SELECT1

WD INPUT

SELECT0

T1 INPUT

SELECT2

T1 INPUT

SELECT1

T1 INPUT

SELECT0

P049

P04A

—

T1CTL1

T1CTL2

†

TAP SEL

SELECT2

WD OVRFL WD OVRFL WD OVRFL

T1 OVRFL

INT ENA

T1 OVRFL

INT FLAG

T1

—

†

RST ENA

INT ENA

INT FLAG

SW RESET

Mode: Dual-Compare

T1EDGE

INT FLAG

T1C2

INT FLAG

T1C1

INT FLAG

T1EDGE

INT ENA

T1C2

INT ENA

T1C1

INT ENA

P04B

P04C

—

T1CTL3

T1CTL4

T1

MODE=0

T1C1

OUT ENA

T1C2

OUT ENA

T1C1

RST ENA

T1CR

OUT ENA

T1EDGE

POLARITY

T1CR

RST ENA

T1EDGE

DET ENA

Mode: Capture/Compare

T1EDGE

—

T1C1

INT FLAG

T1EDGE

INT ENA

T1C1

INT ENA

P04B

P04C

—

T1CTL3

T1CTL4

INT FLAG

T1

T1C1

RST ENA

T1EDGE

POLARITY

T1EDGE

DET ENA

—

MODE = 1

OUT ENA

Modes: Dual-Compare and Capture/Compare

T1EVT

DATA IN

T1EVT

DATA DIR

P04D

P04E

—

T1PC1

T1PC2

T1PRI

DATA OUT FUNCTION

T1IC/CR T1IC/CR

DATA OUT FUNCTION

T1PWM

DATA IN

T1PWM

DATA OUT FUNCTION

T1PWM

DATA DIR

T1IC/CR

DATA IN

T1IC/CR

DATA DIR

T1

P04F T1 STEST

—

PRIORITY

†

Once the WD OVRFL RST ENA bit is set, these bits cannot be changed until a reset; this applies only to the standard

watchdogandtothesimplecounter. Inthehardwatchdog, thesebitscanbemodifiedatanytime;theWDINPUTSELECT2

bits are ignored.

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programmable timer 1 (continued)

Figure 6 shows the timer 1 capture/compare mode block diagram. The annotations on the diagram identify the

register and the bit(s) in the peripheral frame. For example, the actual address of T1CTL2.0 is 104Ah, bit 0, in

the T1CTL2 register.

T1CC.15-0

16-Bit

LSB

T1C1

OUT ENA

Capt/Comp

Register

Prescale

Clock

Source

MSB

T1PC2.7-4

T1PWM

T1CTL4.6

T1CNTR.15-0

LSB

MSB

16-Bit

Counter

16

T1 PRIORITY

0

1

T1C1 INT FLAG

T1CTL3.5

T1PRI.6

Level 1 Int

Level 2 Int

Compare=

Reset

T1CTL3.0

T1C.15-0

T1 SW

RESET

T1C1 INT ENA

16-Bit

LSB

T1C1

RST ENA

Compare

Register

T1CTL2.0

MSB

T1 OVRFL INT FLAG

T1CTL2.3

T1CTL4.4

T1CTL2.4

T1 OVRFL INT ENA

T1PC2.3-0

T1IC/CR

T1EDGE DET ENA

T1EDGE INT FLAG

T1CTL3.7

Edge

Select

T1CTL4.0

T1CTL3.2

T1EDGE INT ENA

T1CTL4.2

T1EDGE POLARITY

Figure 6. Capture/Compare Mode

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programmable timer 1 (continued)

Figure 7 shows the timer 1 dual-compare mode block diagram. The annotations on the diagram identify the

register and the bit(s) in the peripheral frame. For example, the actual address of T1CTL2.0 is 104Ah, bit 0, in

the T1CTL2 register.

T1CC.15-0

16-Bit

Capt/Comp

Register

T1C2 INT FLAG

T1CTL3.6

LSB

Prescaler

Clock

Source

MSB

Output

Enable

T1CTL3.1

T1C2 INT ENA

T1CTL4.5

Compare=

T1CNTR.15-0

T1PC2.7-4

T1PWM

T1C2 OUT ENA

T1CTL4.6

LSB

MSB

16-Bit

Counter

16

T1C1 INT FLAG

T1CTL3.5

T1CTL3.0

Reset

Compare=

T1C1 OUT ENA

T1CTL4.3

T1C1

RST ENA

T1C.15-0

T1 SW

RESET

T1C1 INT ENA

16-Bit

Compare

Register

LSB

T1CTL4.4

T1CR OUT ENA

T1CTL2.0

MSB

T1 OVRFL INT FLAG

T1CTL2.3

T1CTL2.4

T1 OVRFL INT ENA

T1CTL4.1

T1CR

RST ENA

T1PC2.3-0

T1IC/CR

Edge

Select

T1 PRIORITY

T1PRI.6

0

1

T1CTL4.0

Level 1 Int

Level 2 Int

T1EDGE INT FLAG

T1CTL3.7

T1EDGE DET ENA

T1CTL4.2

T1CTL3.2

T1EDGE INT ENA

T1EDGE POLARITY

Figure 7. Dual-Compare Mode

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TMS370Cx0x

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programmable timer 1 (continued)

The TMS370Cx0x device includes a 24-bit watchdog (WD) timer, contained in the timer 1 module, which can

be programmed as an event counter, pulse accumulator, or interval timer if the watchdog function is not used.

The WD function is to monitor software and hardware operation and to implement a system reset when the WD

counter is not properly serviced (WD counter overflow or WD counter is re-initialized by an incorrect value). The

WD can be configured as one of three mask options as follows:

Standard watchdog configuration (see Figure 8) – for EPROM and mask-ROM devices:

–

Watchdog mode

–

Ten different WD overflow rates ranging from 6.55 ms to 3.35 s at 5-MHz SYSCLK

AWDresetkey(WDRST)registerisusedtoclearthewatchdogcounter(WDCNTR)whenacorrect

value is written.

–

Generates a system reset if an incorrect value is written to the watchdog reset key or if the counter

overflows

Awatchdog overflow flag (WD OVRFL INT FLAG) bit that indicates whether the WD timer initiated a

system reset

–

Non-watchdog mode

–

Watchdog timer can be configured as an event counter, a pulse accumulator, or an interval timer

WDCNTR.15-0

WD OVRFL

INT FLAG

T1CTL2.6

16-Bit

WatchdogCounter

T1CTL2.5

Interrupt

WD OVRFL

INT ENA

Reset

Clock

Prescaler

T1CTL2.7

T1CTL1.7

WD OVRFL

TAP SEL

System Reset

WD OVRFL

RST ENA

Watchdog Reset Key

WDRST.7-0

Figure 8. Standard watchdog

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programmable timer 1 (continued)

Hard watchdog configuration (see Figure 9) – for mask-ROM devices:

–

Eight different WD overflow rates ranging from 26.2 ms to 3.35 s at 5-MHz SYSCLK

A WD reset key (WDRST) register is used to clear the watchdog counter (WDCNTR) when a correct

value is written.

–

Generates a system reset if an incorrect value is written to the watchdog reset key or if the counter

overflows.

–

Automatic activation of the WD timer upon power-up reset

INT1 is enabled as a nonmaskable interrupt during low-power modes.

A watchdog overflow flag (WD OVRFL INT FLAG) bit that indicates whether the WD timer initiated a

system reset

WDCNTR.15-0

WD OVRFL

INT FLAG

16-Bit

Watchdog Counter

T1CTL2.5

Reset

Clock

Prescaler

T1CTL1.7

WD OVRFL

TAP SEL

System Reset

Watchdog Reset Key

WDRST.7-0

Figure 9. Hard Watchdog

Simple counter configuration – for mask-ROM devices only (see Figure 10)

Simple counter can be configured as an event counter, pulse accumulator, or an internal timer.

–

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programmable timer 1 (continued)

WDCNTR.15-0

WD OVFL

INT FLAG

T1CTL2.6

16-Bit

Watchdog Counter

T1CTL2.5

Interrupt

WD OVRFL

INT ENA

Reset

Clock

Prescaler

T1CTL1.7

WD OVRFL

TAP SEL

Watchdog Reset Key

WDRST.7-0

Figure 10. Simple Counter

serial communications interface 1 (SCI1) module

The TMS370Cx0x devices include a serial communications interface 1 (SCI1) module. The SCI1 module

supports digital communications between the TMS370 devices and other asynchronous peripherals and uses

thestandardnon-return-zeroformat(NRZ)format. TheSCI1’sreceiverandtransmitteraredoublebuffered, and

each has its own separate enable and interrupt bits. Both can be operated independently or simultaneously in

the full duplex mode. To ensure data integrity, the SCI1 checks received data for break detection, parity, overrun,

and framing errors. The speed of bit rate (baud) is programmable to over 65,000 different speeds through a

16-bit baud-select register.

Features of the SCI1 module include:

Three external pins:

–

SCITXD: SCI transmit-output pin or general-purpose bidirectional I/O pin

SCIRXD: SCI receive-input pin or general-purpose bidirectional I/O pin

SCICLK: SCI bidirectional serial-clock pin, or general-purpose bidirectional I/O pin

†

Two communications modes: asynchronous and isosynchronous

Baud rate: 64K different programmable rates

–

Asynchronous mode: 3 bps to 156K bps at 5-MHz SYSCLK

SYSCLK

(BAUD REG 1) 32

ASYNCHRONOUS BAUD

–

Isosynchronous mode: 39 bps to 2.5M bps at 5-MHz SYSCLK

SYSCLK

(BAUD REG 1)

ISOSYNCHRONOUS BAUD

2

†

Isosynchronous = Isochronous

25

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

serial communications interface 1 (SCI1) module (continued)

Data word format:

–

One start bit

Data word length programmable from one to eight bits

Optional even/odd/no parity bit

One or two stop bits

Four error-detection flags: parity, overrun, framing, and break detection

Two wake-up multiprocessor modes: Idle-line and address bit

Half or full-duplex operation

Double-buffered receiver and transmitter operations

Transmitter and receiver operations can be accomplished through either interrupt-driven or

polled-algorithms with status flags:

–

Transmitter: TXRDY flag (transmitter buffer register is ready to receive another character) and TX

EMPTY flag (Transmitter shift register is empty)

–

Receiver: RXRDY flag (receive buffer register ready to receive another character), BRKDT flag (break

condition occurred), and RX ERROR monitoring four interrupt conditions

–

Separate enable bits for transmitter and receiver interrupts

NRZ (non return-to-zero) format

Eleven SCI1 module control registers, located in control register frame beginning at address P050h

26

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

serial communications interface 1 (SCI1) module (continued)

The SCI1 module control registers are illustrated in Table 14.

Table 14. SCI1 Module Control Register Memory Map

PF

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

EVEN/ODD

PARITY

ENABLE

ASYNC/

ISOSYNC

ADDRESS/

IDLE WUP

SCI

CHAR2

P050 STOP BITS

SCI CHAR1 SCI CHAR0 SCICCR

SCI SW

RESET

P051

P052

P053

P054

P055

—

CLOCK

BAUDC

BAUD4

—

TXWAKE

BAUDB

BAUD3

—

SLEEP

BAUDA

BAUD2

—

TXENA

BAUD9

BAUD1

—

RXENA

BAUD8

SCICTL

BAUDF

(MSB)

BAUDE

BAUD6

TX EMPTY

RXRDY

BAUDD

BAUD5

—

BAUD MSB

BAUD LSB

TXCTL

BAUD0

(LSB)

BAUD7

TXRDY

SCI TX

INT ENA

RX

ERROR

SCI RX

INT ENA

BRKDT

FE

OE

PE

RXWAKE

RXCTL

P056

P057

P058

P059

Reserved

RXDT7

TXDT7

RXDT6

TXDT6

RXDT5

TXDT5

RXDT4

RXDT3

RXDT2

TXDT2

RXDT1

TXDT1

RXDT0

TXDT0

RXBUF

TXBUF

Reserved

TXDT4

TXDT3

P05A

P05B

P05C

Reserved

SCICLK

DATA IN

SCICLK

DATA DIR

P05D

P05E

—

SCIPC1

SCIPC2

SCIPRI

DATA OUT FUNCTION

SCIRXD SCIRXD

DATA OUT FUNCTION

SCITXD

DATA IN

SCITXD

SCIRXD

DATA IN

SCIRXD

DATA DIR

DATA OUT FUNCTION DATA DIR

SCITX

PRIORITY

SCIRX

PRIORITY

SCI

ESPEN

P05F SCI STEST

—

27

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

serial communications interface 1 (SCI1) module (continued)

The SCI1 module block diagram is illustrated in Figure 11.

TXBUF.7–0

TXWAKE

SCICTL.3

Frame Format and Mode

SCI TX Interrupt

SCITX PRIORITY

Transmit Data

Buffer Reg.

PARITY

EVEN/ODD ENABLE

1

0

1

SCIPRI.6

SCI TX INT ENA

TXRDY

TXCTL.7

Level 1 INT

Level 2 INT

SCICCR.6 SCICCR.5

WUT

TXCTL.0

8

TX EMPTY

TXCTL.6

SCIPC2.7–4

SCITXD

TXENA

SCITXD

TXSHF Reg.

BAUD MSB. 7–0

SCICTL.1

Baud Rate

MSbyte Reg.

CLOCK

SCIPC1.3–0

SCICLK

SYSCLK

SCICTL.4

BAUD LSB. 7–0

Baud Rate

LSbyte Reg.

SCIPC2.3–0

SCIRXD

RXSHF Reg.

RXWAKE

RXCTL.1

SCIRX PRIORITY

SCI RX Interrupt

RXENA

0

1

SCIPRI.5

SCI RX INT ENA

RXCTL.0

RXRDY

RXCTL.6

Level 1 INT

Level 2 INT

RX ERROR

SCICTL.0

8

RXCTL.4–2

FE OE PE

RXCTL.7

ERR

BRKDT

Receive Data

Buffer Reg.

RXCTL.5

RXBUF.7–0

Figure 11. SCI1 Block Diagram

instruction set overview

Table 15 provides an opcode-to-instruction cross-reference of all 73 instructions and 274 opcodes of the

‘370Cx0x instruction set. The numbers at the top of this table represent the most significant nibble of the opcode

while the numbers at the left side of the table represent the least significant nibble. The instructions for these

two opcode nibbles contain the mnemonic, operands, and byte/cycle particular to that opcode.

For example, the opcode B5h points to the CLR A instruction. This instruction contains one byte and executes

in eight SYSCLK cycles.

28

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

development system support

The TMS370 family development support tools include an assembler, a C compiler, a linker, and compact

development tool, and an EEPROM/UVEPROM programmer.

Assembler/linker (Part No. TMDS3740850–02 for PC)

–

Includes extensive macro capability

Allows high-speed operation

Provides format conversion utilities for popular formats

ANSI C Compiler (Part No. TMDS3740855–02 for PC, Part No. TMDS3740555–09 for HP700 , Sun-3

or Sun-4 )

–

Generates assembly code for the TMS370 that can be inspected easily

Improves code execution speed and reduces code size with optional optimizer pass

Enables direct reference to the TMS370’s port registers by using a naming convention

Provides flexibility in specifying the storage for data objects

Interfaces C functions and assembly functions easily

Includes assembler and linker

CDT370 (compact development tool) real-time in-circuit emulation

–

Base (Part Number EDSCDT370 – for PC, requires cable)

Cable for 28-pin PLCC (Part No. EDSTRG28PLCC02)

–

Includes EEPROM and EPROM programming support

Allows inspection and modification of memory locations

Allows uploading/downloading program and data memory

Executes programs and software routines

Includes 1024 samples trace buffer

Provides single-step executable instructions

Uses software breakpoints to halt program execution at selected address

Microcontroller programmer

–

Base (Part No. TMDS3760500A – for PC, requires programmer head)

Single unit head for 28-pin PLCC (Part No. TMDS3780510A)

–

Personal computer based, window/function-key-oriented user interface for ease of use and rapid

learning environment

HP700 is a trademark of Hewlett-Packard Company.

Sun-3 and Sun-4 are trademarks of Sun Microsystems, Inc.

31

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

development system support (continued)

Design kit (Part No. TMDS3770110 – for PC)

–

Includes TMS370 Application Board and TMS370 Assembler diskette and documentation

Supports quick evaluation of TMS370 functionality

Provides capability to upload and download code

Provides capability to execute programs and software routines, and to single-step executable

instructions

–

Provides software breakpoints to halt program execution at selected addresses

Includes wire-wrap prototype area

Includes reverse assembler

Starter Kit (Part No. TMDS37000 – for PC)

–

Includes TMS370 Assembler diskette and documentation

Includes TMS370 Simulator

Includes programming adapter board and programming software

Does not include (to be supplied by the user):

–

+ 5 V power supply

ZIF sockets

Nine-pin RS232 cable

32

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

device numbering conventions

Figure 12 illustrates the numbering and symbol nomenclature for the TMS370Cx0x family.

TMS 370 C

7

0

2

A FN T

Prefix: TMS = Standard prefix for fully qualified devices

SE = System evaluator that is used for

prototyping purpose.

Family: 370 = TMS370 8-Bit Microcontroller Family

Technology:

C = CMOS

Program Memory Types:

0 = Mask ROM

3 = Mask ROM, No Data EEPROM

7 = EPROM

Device Type:

0 = ’x0x devices containing the following modules:

— Timer 1

— Serial Communications Interface 1 (SCI1)

Memory Size:

2 = 8K bytes

Temperature Ranges:

A = –40°C to 85°C

L =

0°C to 70°C

T = –40°C to 105°C

Packages:

FN = Plastic Leaded Chip Carrier

FZ = Ceramic Leaded Chip Carrier

ROM and EPROM Option:

A = For ROM device, the watchdog timer can be configured

as one of the three different mask options:

– A standard watchdog

– A hard watchdog

– A simple watchdog

The clock mask option can be either:

– Divide-by-4 clock

– Divide-by-1 (PLL) clock

The low-power modes can be either:

– Enabled

– Disabled

NONE = For EPROM device, a standard watchdog, a

divide-by-4 clock, and low-power modes are enabled.

Figure 12. TMS370Cx0x Family Nomenclature

33

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

device part numbers

Table 16 provides all of the ’x0x devices available. The device part number nomenclature is designed to assist

ordering. Upon ordering, the customer must specify not only the device part number, but also the clock and

watchdog timer options desired. Each device can have only one of the three possible watchdog timer options

and one of the two clock options. The options to be specified pertain solely to orders involving ROM devices.

Table 16. Device Part Numbers

DEVICE PART NUMBERS

FOR 28 PINS (LCC)

TMS370C002AFNA

TMS370C002AFNL

TMS370C002AFNT

TMS370C302AFNA

TMS370C302AFNL

TMS370C302AFNT

TMS370C702FNT

†

SE370C702FZT

†

System evaluators are for use in prototype environment and their

reliability has not been characterized.

34

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

new code release form

Figure 13 shows a sample of the new code release form.

NEW CODE RELEASE FORM

TEXAS INSTRUMENTS

DATE:

TMS370 MICROCONTROLLER PRODUCTS

To release a new customer algorithm to TI incorporated into a TMS370 family microcontroller, complete this form and submit with the following information:

1. A ROM description in object form on Floppy Disk, Modem XFR, or EPROM (Verification file will be returned via same media)

2. An attached specification if not using TI standard specification as incorporated in TI’s applicable device data book.

Company Name:

Street Address:

City:

Contact Mr./Ms.:

Phone: (

)

Ext.:

State

Zip

Customer Purchase Order Number:

Customer Print Number *Yes:

No:

*If Yes: Customer must provide ”print” to TI w/NCRF for approval before ROM

code processing starts.

#

Customer Part Number:

Customer Application:

(Std. spec to be followed)

TMS370 Device:

TI Customer ROM Number:

(provided by Texas Instruments)

CONTACT OPTIONS FOR THE ’A’ VERSION TMS370 MICROCONTROLLERS

OSCILLATOR FREQUENCY

Low Power Modes

[] Enabled

[] Disabled

Watchdog counter

[] Standard

[] Hard Enabled

[] Simple Counter

Clock Type

[] Standard (/4)

[] PLL (/1)

MIN

TYP

MAX

[] External Drive (CLKIN)

[] Crystal

[] Ceramic Resonator

NOTE:

Non ’A’ version ROM devices of the TMS370 microcontrollers will have the

“Low-powermodesEnabled”, “Divide-by-4”Clock, and“Standard”Watchdog

options. See the TMS370 Family User’s Guide (literature number SPNU127)

or the TMS370 Family Data Manual (literature number SPNS014B).

[] Supply Voltage MIN:

(std range: 4.5V to 5.5V)

MAX:

TEMPERATURE RANGE

PACKAGE TYPE

[] ’L’:

[] ’A’:

[] ’T’:

0° to 70°C (standard)

–40° to 85°C

–40° to 105°C

[] ’N’ 28-pin PDIP

[] “FN” 28-pin PLCC

[] “N” 40-pin PDIP

[] “FN” 44-pin PLCC

[] “FN” 68-pin PLCC

[] “NM” 64-pin PSDIP

[] “NJ” 40-pin PSDIP (formerly known as N2)

SYMBOLIZATION

BUS EXPANSION

[] TI standard symbolization

[] YES

[] NO

[] TI standard w/customer part number

[] Customer symbolization

(per attached spec, subject to approval)

NON-STANDARD SPECIFICATIONS:

ALL NON-STANDARDS SPECIFICATIONS MUST BE APPROVED BY THE TI ENGINEERING STAFF: If the customer requires expedited production material

(i.e., product which must be started in process prior to prototype approval and full production release) and non-standard spec issues are not resolved to the

satisfaction of both the customer and TI in time for a scheduled shipment, the specification parameters in question will be processed/tested to the standard

TI spec. Any such devices which are shipped without conformance to a mutually approved spec, will be identified by a ’P’ in the symbolization preceding the

TI part number.

RELEASE AUTHORIZATION:

This document, including any referenced attachments, is and will be the controlling document for all orders placed for this TI custom device. Any changes must

be in writing and mutually agreed to by both the customer and TI. The prototype cycletime commences when this document is signed off and the verification

code is approved by the customer.

1. Customer:

Date:

2. TI: Field Sales:

Marketing:

Prod. Eng.:

Proto. Release:

Figure 13. Sample New Code Release Form

35

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

Table 17. Peripheral File Frame Compilation

Table 17 is a collection of all the peripheral file frames used in the ’Cx0x (provided for a quick reference).

PF

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

System Configuration Registers

COLD

START

OSC

POWER

PF AUTO

WAIT

OSC FLT

FLAG

MC PIN

WPO

MC PIN

DATA

µP/µC

MODE

P010

P011

P012

—

SCCR0

SCCR1

SCCR2

AUTO

WAIT

DISABLE

MEMORY

DISABLE

—

HALT/

STANDBY

PWRDWN/

IDLE

BUS

STEST

CPU

STEST

INT1

NMI

PRIVILEGE

DISABLE

—

P013

to

Reserved

P016

INT1

FLAG

INT1

PIN DATA

INT1

POLARITY

INT1

PRIORITY

INT1

ENABLE

P017

P018

P019

—

INT1

INT2

FLAG

INT2

PIN DATA

INT2

DATA DIR

INT2

DATA OUT

INT2

POLARITY

INT2

PRIORITY

INT2

ENABLE

INT3

FLAG

INT3

PIN DATA

INT3

DATA DIR

INT3

DATA OUT

INT3

POLARITY

INT3

PRIORITY

INT3

ENABLE

—

INT3

P01A

P01B

P01C

BUSY

—

AP

—

W1W0

W0

EXE

DEECTL

Reserved

VPPS

—

EPCTL

P01D

P01E

P01F

Reserved

Digital Port Control Registers

P020

P021

P022

P023

Reserved

APORT1

APORT2

ADATA

ADIR

Port A Control Register 2 (must be 0)

Port A Data

Port A Direction

P024

to

Reserved

P02B

P02C

P02D

P02E

P02F

Port D Control Register 1 (must be 0)

—

DPORT1

DPORT2

DDATA

DDIR

†

Port D Control Register 2 (must be 0)

Port D Data

Port D Direction

Timer Module Register Memory Map

Modes: Dual-Compare and Capture/Compare

P040 Bit 15

P041 Bit 7

P042 Bit 15

P043 Bit 7

T1Counter MSbyte

T1 Counter LSbyte

Bit 8 T1CNTR

Bit 0

Compare Register MSbyte

Compare Register LSbyte

Bit 8 T1C

Bit 0

†

To configure pin D3 as SYSCLK, set port D control register 2 = 08h.

36

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

Table 17. Peripheral File Frame Compilation (Continued)

PF

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

Modes: Dual-Compare and Capture/Compare (Continued)

P044 Bit 15

P045 Bit 7

P046 Bit 15

P047 Bit 7

P048 Bit 7

Capture/Compare Register MSbyte

Capture/Compare Register LSbyte

Watchdog Counter MSbyte

Watchdog Counter LSbyte

Watchdog Reset Key

Bit 8 T1CC

Bit 0

Bit 8 WDCNTR

Bit 0

Bit 0 WDRST

WD OVRFL

TAP SEL

WD INPUT

SELECT2

WD INPUT

SELECT1

WD INPUT

SELECT0

T1 INPUT

SELECT2

T1 INPUT

SELECT1

T1 INPUT

SELECT0

P049

P04A

—

T1CTL1

T1CTL2

†

WD OVRFL

INT ENA

WD OVRFL

INT FLAG

T1 OVRFL

INT ENA

T1 OVRFL

INT FLAG

T1

—

†

RST ENA

SW RESET

Mode: Dual-Compare

T1EDGE

INT FLAG

T1C2

INT FLAG

T1C1

INT FLAG

T1EDGE

INT ENA

T1C2

INT ENA

T1C1

INT ENA

P04B

—

T1CTL3

T1CTL4

T1C1

OUT ENA

T1C2

OUT ENA

T1C1

RST ENA

T1CR

OUT ENA

T1EDGE

POLARITY

T1CR

RST ENA

T1EDGE

DET ENA

P04C T1 MODE=0

Mode: Capture/Compare

T1EDGE

—

T1C1

INT FLAG

T1EDGE

INT ENA

T1C1

INT ENA

P04B

P04C

—

T1CTL3

T1CTL4

INT FLAG

T1

T1C1

RST ENA

T1EDGE

POLARITY

T1EDGE

DET ENA

—

MODE = 1

OUT ENA

Modes: Dual-Compare and Capture/Compare

T1EVT

DATA IN

T1EVT

DATA OUT

T1EVT

FUNCTION

T1EVT

DATA DIR

P04D

P04E

P04F

—

T1PC1

T1PC2

T1PRI

T1PWM

DATA IN

T1PWM

DATA OUT

T1PWM

FUNCTION

T1PWM

DATA DIR

T1IC/CR

DATA IN

T1IC/CR

DATA OUT

T1IC/CR

FUNCTION

T1IC/CR DATA

DIR

T1

T1 STEST

—

PRIORITY

SCI1 Module Control Memory Map

EVEN/ODD

PARITY

ENABLE

ASYNC/

ISOSYNC

ADDRESS/

IDLE WUP

P050 STOP BITS

SCI CHAR2

SLEEP

SCI CHAR1

TXENA

SCI CHAR0

RXENA

SCICCR

SCICTL

SCI SW

RESET

P051

—

CLOCK

TXWAKE

BAUDF

(MSB)

P052

P053

P054

BAUDE

BAUD6

BAUDD

BAUD5

—

BAUDC

BAUD4

—

BAUDB

BAUD3

—

BAUDA

BAUD2

—

BAUD9

BAUD1

—

BAUD8

BAUD MSB

BAUD7

TXRDY

BAUD0 (LSB) BAUD LSB

SCI TX

TXCTL

TX EMPTY

INT ENA

RX

ERROR

SCI RX

RXCTL

P055

RXRDY

RXDT6

BRKDT

RXDT5

FE

OE

PE

RXWAKE

RXDT1

INT ENA

P056

P057

P058

Reserved

RXDT7

RXDT4

RXDT3

RXDT2

RXDT0

RXBUF

Reserved

†

Once the WD OVRFL RST ENA bit is set, these bits cannot be changed until a reset; this applies only to the standard

watchdog and to simple counter. In the hard watchdog, these bits can be modified at any time; the WD INPUT SELECT2

bits are ignored.

37

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

Table 17. Peripheral File Frame Compilation (Continued)

PF

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

SCI1 Module Control Memory Map (Continued)

P059

TXDT7

TXDT6

TXDT5

TXDT4

TXDT3

Reserved

TXDT2

TXDT1

TXDT0

TXBUF

P05A

P05B

P05C

SCICLK

DATA IN

SCICLK

DATA OUT

SCICLK

FUNCTION

SCICLK DATA

DIR

P05D

P05E

—

SCIPC1

SCIPC2

SCIPRI

SCITXD

DATA IN

SCITXD

DATA OUT

SCITXD

FUNCTION

SCITXD

DATA DIR

SCIRXD

DATA IN

SCIRXD

DATA OUT

SCIRXD

FUNCTION

SCIRXD DATA

DIR

SCITX

PRIORITY

SCIRX

PRIORITY

SCI

ESPEN

P05F SCI STEST

—

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range,V

(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to 7 V

CC

Input voltage range, All pins except MC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to 7 V

MC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to 14 V

Input clamp current, I (V < 0 or V > V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA

(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA

IK

I

CC)

Output clamp current, I

OK

O

CC

Continuous output current per buffer, I (V = 0 to V ) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA

O

CC)

Maximum I

current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 mA

CC

Maximum I current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 170 mA

SS

Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mW

Operating free-air temperature range, T L version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

A:

A version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C

T version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 105°C

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. Unless otherwise noted, all voltage values are with respect to V

.

SS

2. Electrical characteristics are specified with all output buffers loaded with specified I current. Exceeding the specified I current in

O

any buffer can affect the levels on other buffers.

38

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

recommended operating conditions

MIN

4.5

3

NOM

MAX

5.5

UNIT

V

Supply voltage (see Note 1)

5

V

CC

RAM data-retention supply voltage (see Note 3)

All pins except MC

5.5

V

SS

0.8

Low-level input voltage

V

IL

MC, normal operation

V

SS

0.3

All pins except MC, XTAL2/CLKIN, and

RESET

2

V

CC

V

High-level input voltage

IH

XTAL2/CLKIN

0.8 V

0.7 V

V

CC

RESET

V

CC

13

EEPROM write protect override (WPO)

11.7

13

12

MC (mode control) voltage

EPROM programming voltage (V

Microcomputer

L version

)

13.2

13.5

0.3

70

V

MC

PP

V

SS

0

T

A

Operating free-air temperature

A version

– 40

85

°C

T version

105

NOTES: 1. Unless otherwise noted, all voltage values are with respect to V

.

SS

3. RESET must be activated externally when V

CC

or SYSCLK is not within the recommended operating range.

39

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

Low-level output voltage

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

I

= 1.4 mA

= –50 µA

= –2 mA

0.4

V

OL

OH

0.9 V

CC

High-level output voltage

Input current

V

OH

2.4

0 V ≤ V ≤ 0.3 V

10

I

µA

0.3 V < V ≤ 13 V

650

I

MC

I

See Note 4

50

mA

12 V ≤ V ≤ 13 V

I

I/O pins

0 V ≤ V ≤ V

± 10

µA

mA

µA

I

CC

I

Low-level output current

High-level output current

V

OL

V

OH

V

OH

= 0.4 V

1.4

– 50

– 2

OL

= 0.9 V

= 2.4 V

CC

OH

mA

See Notes 5 and 6

SYSCLK = 5 MHz

20

13

5

36

25

11

Supply current (operating mode)

OSC POWER bit = 0 (see Note 7)

See Notes 5 and 6

SYSCLK = 3 MHz

mA

See Notes 5 and 6

SYSCLK = 0.5 MHz

See Notes 5 and 6

SYSCLK = 5 MHz

10

6.5

2

17

11

Supply current (STANDBY mode)

OSC POWER bit = 0 (see Note 8)

See Notes 5 and 6

SYSCLK = 3 MHz

I

CC

See Notes 5 and 6

SYSCLK = 0.5 MHz

3.5

8.6

3.0

30

See Notes 5 and 6

SYSCLK = 3 MHz

4.5

1.5

1

Supply current (STANDBY mode)

OSC POWER bit = 1 (see Note 9)

mA

See Notes 5 and 6

SYSCLK = 0.5 MHz

See Note 5

XTAL2/CLKIN < 0.2 V

Supply current (HALT mode)

µA

NOTES: 4. Input current I

is a maximum of 50 mA only when programming EPROM.

PP

5. Single chip mode, ports configured as inputs or outputs with no load. All inputs ≤ 0.2 V or ≥ V

– 0.2 V.

CC

6. XTAL2/CLKIN is driven with an external square wave signal with 50% duty cycle and rise and fall times less than 10 ns. Current

can be higher with a crystal oscillator. At 5 MHz SYSCLK, this extra current = 0.01 mA x (total load capacitance + crystal capacitance

in pF).

7. Maximum operating current = 5.6 (SYSCLK) + 8 mA.

8. Maximum standby current = 3 (SYSCLK) + 2 mA. (OSC POWER bit = 0).

9. Maximum standby current = 2.24 (SYSCLK) + 1.9 mA. (OSC POWER bit = 1, only valid up to 3 MHz of SYSCLK).

40

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

XTAL2/CLKIN

XTAL1

XTAL2/CLKIN

XTAL1

C3 (see Note B)

C1

C2 (see Note B)

Crystal/Ceramic

Resonator

(see Note A)

External

Clock Signal

(see Note B)

NOTES: A. The crystal/ceramic resonator frequency is four times the reciprocal of the system clock period.

B. The values of C1 and C2 are typically 15 pF and C3 is typically 50 pF. See the manufacturer’s recommendations for ceramic

resonators.

Figure 14. Recommended Crystal/Clock Connections

Load Voltage

1.2 kΩ

V

O

20 pF

Case 1: V = V

= 2.4 V; Load Voltage = 0 V

= 0.4 V; Load Voltage = 2.1 V

O

OH

OL

Case 2: V = V

O

NOTE A: All measurements are made with the pin loading as shown unless otherwise noted. All measurements are made with XTAL2/CLKIN

driven by an external square wave signal with a 50% duty cycle and rise and fall times less than 10 ns unless otherwise stated.

Figure 15. Typical Output Load Circuit (See Note A)

V

CC

V

CC

300 Ω

30 Ω

Pin Data

6 kΩ

Output

Enable

I/O

INT1

20 Ω

GND

Figure 16. Typical Buffer Circuitry

41

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

PARAMETER MEASUREMENT INFORMATION

timing parameter symbology

Timing parameter symbols have been created in accordance with JEDEC Standard 100. In order to shorten the

symbols, some of the pin names and other related terminology have been abbreviated as follows:

AR

B

Array

SC

SYSCLK

Byte

SCC SCICLK

CI

XTAL2/CLKIN

TXD

SCITXD

RXD SCIRXD

Lowercase subscripts and their meanings are:

c

d

f

cycle time (period)

delay time

fall time

su

v

setup time

valid time

w

pulse duration (width)

r

rise time

The following additional letters are used with these meanings:

H

L

High

Low

Valid

V

All timings are measured between high and low measurement points as indicated in Figure 17 and Figure 18.

0.8 V

V (High)

2 V (High)

CC

0.8 V (Low)

Figure 17. XTAL2/CLKIN Measurement Points

Figure 18. General Measurement Points

42

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

external clocking requirements for divide-by-4 clock (see Note 10 and Figure 19)

NO.

1

MIN

MAX

UNIT

ns

t

Pulse duration, XTAL2/CLKIN (see Note 11)

Rise time, XTAL2/CLKIN

20

w(Cl)

2

30

100

20

5

ns

r(Cl)

3

Fall time, XTAL2/CLKIN

ns

f(CI)

4

Delay time, XTAL2/CLKIN rise to SYSCLK fall

Crystal operating frequency

ns

d(CIH-SCL)

CLKIN

2

MHz

†

SYSCLK

Internal system clock operating frequency

0.5

†

SYSCLK = CLKIN/4

NOTES: 10. For V and V , refer to recommended operating conditions.

IL IH

11. This pulse can be either a high pulse, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle, or

a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle.

1

XTAL2/CLKIN

2

3

4

SYSCLK

Figure 19. External Clock Timing for Divide-by-4

external clocking requirements for divide-by-1 clock (PLL) (see Note 10 and Figure 20)

NO.

1

MIN

MAX

UNIT

ns

t

Pulse duration, XTAL2/CLKIN (see Note 11)

Rise time, XTAL2/CLKIN

20

w(Cl)

2

30

100

5

ns

r(Cl)

3

Fall time, XTAL2/CLKIN

ns

f(CI)

4

Delay time, XTAL2/CLKIN rise to SYSCLK rise

Crystal operating frequency

ns

d(CIH-SCH)

CLKIN

2

MHz

‡

SYSCLK

Internal system clock operating frequency

5

‡

SYSCLK = CLKIN/1

NOTES: 10. For V and V , refer to recommended operating conditions.

IL IH

11. This pulse can be either a high pulse, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle, or

a low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle.

1

XTAL2/CLKIN

4

2

3

SYSCLK

Figure 20. External Clock Timing for Divide-by-1

43

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

switching characteristics and timing requirements (see Note 12 and Figure 21)

NO.

PARAMETER

MIN

200

MAX

2000

500

UNIT

Divide-by-4

Divide-by-1

5

t

c

Cycle time, SYSCLK (system clock)

ns

6

7

t

Pulse duration, SYSCLK low

Pulse duration, SYSCLK high

0.5 t –20

0.5 t

c

ns

w(SCL)

c

0.5 t

0.5 t + 20

c

w(SCH)

c

NOTE 12: t = system-clock cycle time = 1/SYSCLK

c

5

7

6

SYSCLK

Figure 21. SYSCLK Timing

general purpose output signal switching time requirements (see Figure 22)

MIN NOM

MAX

UNIT

ns

t

Rise time

Fall time

30

r

ns

f

t

r

t

f

Figure 22. Signal Switching Time

recommended EEPROM timing requirements for programming

MIN

10

MAX

UNIT

ms

t

Pulse duration, programming signal to ensure valid data is stored (byte mode)

Pulse duration, programming signal to ensure valid data is stored (array mode)

w(PGM)B

20

ms

w(PGM)AR

recommended EPROM operating conditions for programming

MIN NOM

MAX

6

UNIT

V

Supply voltage

4.75

13

5.5

13.2

30

CC

Supply voltage at MC pin

13.5

50

5

V

PP

I

Supply current at MC pin during programming (V

= 13 V)

mA

PP

Divide-by-4

Divide-by-1

0.5

2

SYSCLK

System clock operating frequency

MHz

5

recommended EPROM timing requirements for programming

MIN NOM

0.40 0.50

MAX

UNIT

t

Pulse duration, programming signal (see Note 13)

3

ms

w(EPGM)

NOTE 13: Programming pulse is active when both EXE (EPCTL.0) and V

(EPCTL.6) are set.

PPS

44

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

SCI1 isosynchronous mode timing characteristics and requirements for internal clock

(see Note 12 and Figure 23)

NO.

24

25

26

27

28

29

30

MIN

2t

MAX

UNIT

ns

t

Cycle time, SCICLK

131072t

c

c(SCC)

c

Pulse duration, SCICLK low

t

c

t

c

– 45

0.5t

+45

ns

w(SCCL)

c(SCC)

Pulse duration, SCICLK high

ns

w(SCCH)

c(SCC)

60

Delay time, SCITXD valid after SCICLK low

Valid time, SCITXD data valid after SCICLK high

Setup time, SCIRXD to SCICLK high

Valid time, SCIRXD data valid after SCICLK high

– 50

ns

d(SCCL-TXDV)

v(SCCH-TXD)

su(RXD-SCCH)

v(SCCH-RXD)

t

– 50

ns

w(SCCH)

0.25 t + 145

c

ns

0

ns

NOTE 12: t = system-clock cycle time = 1/SYSCLK

c

24

26

25

SCICLK

28

27

Data Valid

SCITXD

29

30

Data Valid

SCIRXD

Figure 23. SCI1 Isosynchronous Mode Timing for Internal Clock

45

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

SCI1 isosynchronous mode timing characteristics and requirements for external clock

(see Note 12 and Figure 24)

NO.

31

32

33

34

35

36

37

MIN

10t

MAX

UNIT

ns

t

Cycle time, SCICLK

c(SCC)

c

Pulse duration, SCICLK low

4.25t + 120

ns

w(SCCL)

c

Pulse duration, SCICLK high

t

c

+ 120

ns

w(SCCH)

Delay time, SCITXD valid after SCICLK low

Valid time, SCITXD data valid after SCICLK high

Setup time, SCIRXD to SCICLK high

Valid time, SCIRXD data after SCICLK high

4.25t + 145

ns

d(SCCL-TXDV)

v(SCCH-TXD)

su(RXD-SCCH)

v(SCCH-RXD)

c

t

ns

w(SCCH)

40

ns

2t

c

ns

NOTE 12: t = system-clock cycle time = 1/SYSCLK

c

31

33

32

SCICLK

35

34

Data Valid

SCITXD

36

37

Data Valid

SCIRXD

Figure 24. SCI1 Isosynchronous Timing for External Clock

Table 18 is designed to aid the user in referencing a device part number to a mechanical drawing. The table

shows a cross-reference of the device part number to the TMS370 generic package name and the associated

mechanical drawing by drawing number and name.

Table 18. TMS370Cx0x Family Package Type and Mechanical Cross-Reference

PKG TYPE

(mil pin spacing)

PKG TYPE NO. AND

MECHANICAL NAME

TMS370 GENERIC NAME

DEVICE PART NUMBERS

TMS370C002AFNA

TMS370C002AFNL

TMS370C002AFNT

TMS370C302AFNA

TMS370C302AFNL

TMS370C302AFNT

TMS370C702FNT

FN – 28 pin

(50-mil pin spacing)

PLASTIC LEADED CHIP CARRIER

(PLCC)

FN(S-PQCC-J**) PLASTIC J-LEADED

CHIP CARRIER

FZ – 28 pin

(50-mil pin spacing)

CERAMIC LEADED CHIP CARRIER

(CLCC)

FZ(S-CQCC-J**) J-LEADED CERAMIC

CHIP CARRIER

SE370C702FZT

46

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

MECHANICAL DATA

FN (S-PQCC-J**)

PLASTIC J-LEADED CHIP CARRIER

20 PIN SHOWN

Seating Plane

0.004 (0,10)

0.180 (4,57) MAX

0.120 (3,05)

D

0.090 (2,29)

D1

0.020 (0,51) MIN

3

1

19

0.032 (0,81)

0.026 (0,66)

4

18

D2/E2

E

E1

8

14

0.021 (0,53)

0.013 (0,33)

0.007 (0,18)

0.050 (1,27)

9

13

M

0.008 (0,20) NOM

D/E

D1/E1

D2/E2

NO. OF

PINS

**

MIN

0.385 (9,78)

MAX

MIN

MAX

MIN

MAX

0.395 (10,03)

0.350 (8,89)

0.356 (9,04)

0.141 (3,58)

0.191 (4,85)

0.291 (7,39)

0.341 (8,66)

0.169 (4,29)

0.219 (5,56)

0.319 (8,10)

0.369 (9,37)

20

28

44

52

68

84

0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58)

0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66)

0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20)

0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91)

1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45)

4040005/B 03/95

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-018

47

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx0x

8-BIT MICROCONTROLLER

SPNS029C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

MECHANICAL DATA

FZ (S-CQCC-J**)

J-LEADED CERAMIC CHIP CARRIER

28 LEAD SHOWN

0.040 (1,02)

45°

Seating Plane

0.180 (4,57)

0.155 (3,94)

0.140 (3,55)

A

B

1

0.120 (3,05)

26

4

25

5

0.050 (1,27)

C

(at Seating

Plane)

A

B

0.032 (0,81)

0.026 (0,66)

0.020 (0,51)

0.014 (0,36)

19

11

18

12

0.025 (0,64) R TYP

0.040 (1,02) MIN

0.120 (3,05)

0.090 (2,29)

A

B

C

JEDEC

NO. OF

PINS**

OUTLINE

MIN

MAX

MIN

MAX

MIN

MAX

0.485

0.495

0.430

0.455

0.410

0.430

MO-087AA

MO-087AB

MO-087AC

MO-087AD

28

44

52

68

(12,32)

(12,57)

(10,92)

(11,56)

(10,41)

(10,92)

0.685

0.695

0.630

0.655

0.610

0.630

(17,40)

(17,65)

(16,00)

(16,64)

(15,49)

(16,00)

0.785

0.795

0.730

0.765

0.680

0.740

(19,94)

(20,19)

(18,54)

(19,43)

(17,28)

(18,79)

0.985

0.995

0.930

0.955

0.910

0.930

(25,02)

(25,27)

(23,62)

(24,26)

(23,11)

(23,62)

4040219/B 03/95

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a ceramic lid using glass frit.

48

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

PACKAGE OPTION ADDENDUM

www.ti.com

4-May-2009

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

JLCC

PLCC

Drawing

SE370C702FZT

OBSOLETE

FZ

28

TBD

Call TI

TMS370C702FNT

FN

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

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information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	SE370C702
厂家：	TEXAS INSTRUMENTS
描述：	8-BIT MICROCONTROLLER 8位微控制器微控制器
文件：	总50页 (文件大小：744K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SE370C702 [TI]

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