SE370C777AFZT_技术文档

TMS370Cx7x

8-BIT MICROCONTROLLER

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

FN/FZ PACKAGE

(TOP VIEW)

CMOS/EEPROM/EPROM Technologies on a

Single Device

– Mask-ROM Devices for High-Volume

Production

9

8

7

6

5

4

3

2

1

6867 66 65 6463 62 61

60 D1

C3 10

– One-Time-Programmable (OTP) EPROM

Devices for Low-Volume Production

– Reprogrammable EPROM Devices for

Prototyping Purposes

11

12

13

14

15

16

59

58

57

56

55

54

C4

C5

C6

D2

D3/SYSCLK

D4

D5

D6

D7

C7

V

CC2

V

SS2

A0 17

53 RESET

52

18

19

20

21

22

23

A1

A2

A3

A4

A5

A6

A7

INT1 / NMI

Internal System Memory Configurations

– On-Chip Program Memory Versions

– ROM: 24K Bytes

– EPROM: 24K Bytes

– Data EEPROM: 256 Bytes

– Static RAM: 512 Bytes

51

50

49

48

47

INT2

INT3

G5

G4

G3

24

25

26

46

45

44

T1IC/CR

T1PWM

T1EVT

T2AEVT

T2AIC2/PWM

27 28 2930 31 32 3334 35 3637 38 39 4041 42 43

Flexible Operating Features

– Low-Power Modes: STANDBY and HALT

– Commercial, Industrial, and Automotive

Temperature Ranges

JN/NM PACKAGE

(TOP VIEW)

– Clock Options:

– Divide-by-4 (0.5 MHz – 5 MHz SYSCLK)

– Divide-by-1 (2 MHz – 5 MHz SYSCLK)

Phase-Locked Loop (PLL)

B5

B6

B7

C0

MC

C1

C2

B4

B3

B2

B1

B0

D0

1

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

2

3

4

– Supply Voltage (V ): 5 V ± 10%

CC

5

6

Eight-Channel 8-Bit Analog-to-Digital

Converter 1 (ADC1)

V

7

SS1

CC1

V

SS1

C3

8

D1

9

TMS370 Series Compatibility

– Instructions Upwardly Compatible With

All TMS370 Devices

– Register-to-Register Architecture

– 256 General-Purpose Registers

– 14 Powerful Addressing Modes

C4

C5

C6

C7

D3/SYSCLK

D4

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

D6

D7

RESET

INT1 / NMI

INT2

AN0 / E0

A0

A1

A2

INT3

A3

G5

A4

G4

A5

G3

Two 16-Bit General-Purpose Timers

On-Chip 24-Bit Watchdog Timer

Flexible Interrupt Handling

A6

A7

T1IC / CR

T1PWM

AN7 / E7

T1EVT

T2AEVT

T2AIC2 / PWM

T2AIC1 / CR

G0

V

SS1

AN6 / E6

AN5 / E5

AN4 / E4

AN3 / E3

AN2 / E2

AN1 / E1

CMOS/Package /TTL-Compatible I/O Pins

– 64-Pin Plastic and Ceramic Shrink

Dual-In-Line Packages /44 Bidirectional,

9 Input Pins

G1

G2

XTAL2 / CLKIN

XTAL1

V

CC1

CC3

V

SS3

– 68-Pin Plastic and Ceramic Leaded Chip

Carrier Packages /46 Bidirectional,

9 Input Pins

– All Peripheral Function Pins Are

Software Configurable for Digital I/O

Workstation/PC-Based Software

Development System

– Real-Time In-Circuit Emulation

– Extensive Breakpoint/Trace Capability

– Software Performance Analysis

– Multi-Window User Interface

– C Compiler and C Source Debugger

– Microcontroller Programmer

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

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TMS370Cx7x

8-BIT MICROCONTROLLER

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

Pin Descriptions

†

I/O

DESCRIPTION

SDIP

(64)

LCC

(68)

NAME

A0

A1

A2

A3

A4

A5

A6

A7

15

16

17

18

19

20

21

22

17

18

19

20

21

22

23

24

I/O Port A is a general-purpose bidirectional I/O port.

I/O Port B is a general-purpose bidirectional I/O port.

I/O Port C is a general-purpose bidirectional I/O port.

B0

B1

B2

B3

B4

B5

B6

B7

60

61

62

63

64

1

65

66

67

68

1

2

3

4

2

3

C0

C1

C2

C3

C4

C5

C6

C7

4

6

7

5

7

8

10

11

12

13

14

9

10

11

12

13

INT1/NMI

INT2

INT3

50

49

48

52

51

50

I

External (nonmaskable or maskable) interrupt/general-purpose input pin

I/O External maskable interrupt input/general-purpose bidirectional pin

AN0/E0

AN1/E1

AN2/E2

AN3/E3

AN4/E4

AN5/E5

AN6/E6

AN7/E7

14

34

35

36

37

38

39

42

36

37

38

39

40

41

42

43

ADC1 analog input (AN0–AN7) or positive reference pins (AN1–AN7)

PortEcanbeprogrammedindividuallyasgeneral-purposeinputpinsifnotusedasADC1analoginput

or positive reference input.

I

V

CC3

V

SS3

32

33

34

35

ADC1 positive-supply voltage and optional positive-reference input pin

ADC1 ground reference pin

System reset bidirectional pin. As an input, RESET initializes the microcontroller; as open-drain out-

put, RESET indicates that an internal failure was detected by the watchdog or oscillator fault circuit.

RESET

51

5

53

6

I/O

I

Mode control (MC) pin. MC enables EEPROM write-protection-override (WPO) mode, also EPROM

MC

V

.

PP

XTAL2/CLKIN

XTAL1

29

30

31

32

I

O

Internal oscillator crystal input/external clock source input

Internal oscillator output for crystal

V

31, 57 33, 61

15,63

Positive supply voltage

CC1

—

Positive supply voltage for digital I/O

CC2

†

I = input, O = output

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TMS370Cx7x

8-BIT MICROCONTROLLER

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

Pin Descriptions (Continued)

†

I/O

DESCRIPTION

SDIP

(64)

LCC

(68)

NAME

8,

58,40

V

9

Ground reference for digital logic

SS1

—

16,62

Ground reference for digital I/O logic

SS2

D0

D1

D2

59

56

—

55

54

—

53

52

64

60

59

58

57

56

55

54

D3/SYSCLK

I/O Port D is a general-purpose bidirectional I/O port. D3 also can be configured as SYSCLK.

D4

D5

D6

D7

G0

G1

G2

G3

G4

G5

26

27

28

45

46

47

28

29

30

47

48

49

I/O Port G is a general-purpose bidirectional I/O port.

T1IC/CR

T1PWM

T1EVT

44

43

41

46

45

44

Timer1 input capture/counter-reset input pin/general-purpose bidirectional pin

I/O Timer1 pulse-width-modulation (PWM) output pin/general-purpose bidirectional pin

Timer1 external event input pin/general-purpose bidirectional pin

T2AIC1/CR

T2AIC2/PWM

T2AEVT

25

24

23

27

26

25

Timer2A input capture 1/counter reset input pin/general-purpose bidirectional pin

I/O Timer2A input capture 2/PWM output pin/general-purpose bidirectional pin

Timer2A external event input pin/general-purpose bidirectional pin

†

I = input, O = output

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TMS370Cx7x

8-BIT MICROCONTROLLER

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

functional block diagram

E0–E7

or

AN0–AN7

INT1 INT2 INT3 XTAL1 XTAL2/

CLKIN

MC RESET

V

CC3

Clock Options:

Divide-by-4 or

Divide-by-1(PLL)

Interrupts

System Control

A-to-D Converter 1

SS3

T2AIC1/CR

T2AEVT

Timer 2A

Timer 1

RAM

512 Bytes

T2AIC2/PWM

CPU

T1IC/CR

T1EVT

Data EEPROM

256 Bytes

Program Memory

ROM: 24K Bytes

EPROM: 24K Bytes

T1PWM

Watchdog

†

Port A

V

Port B

8

Port G

6

Port C

8

Port D

CC1

V

SS1

8

8/6

‡

V

SS2

V

CC2

†

‡

For the 64-pin devices, there are only six pins for port D.

For the 64-pin devices, omit these power pins

description

The TMS370C077, TMS370C777, and SE370C777 devices are members of the TMS370 family of single-chip

8-bit microcontrollers. Unless otherwise noted, the term TMS370Cx7x refers to these devices. The TMS370

family provides cost-effective real-time system control through integration of advanced peripheral function

modules and various on-chip memory configurations.

The TMS370Cx7x family is implemented using high-performance silicon-gate CMOS EPROM and EEPROM

technologies. The low-operating power, wide-operating temperature range, and noise immunity of CMOS

technology, coupled with the high performance and extensive on-chip peripheral functions make the

TMS370Cx7x devices attractive in system designs for automotive electronics, industrial motor control,

computer peripheral control, telecommunications, and consumer application.

All TMS370Cx7x devices contain the following on-chip peripheral modules:

Eight-channel, 8-bit analog-to-digital converter 1 (ADC1)

One 24-bit general-purpose watchdog timer

Two 16-bit general-purpose timers (one with an 8-bit prescaler)

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TMS370Cx7x

8-BIT MICROCONTROLLER

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

description (continued)

Table 1 provides a memory configuration overview of the TMS370Cx7x devices.

Table 1. Memory Configurations

PROGRAM

DATA MEMORY

MEMORY

(BYTES)

PACKAGES

68-PIN PLCC/CLCC, OR

64-PIN PSDIP/CSDIP

(BYTES)

DEVICE

ROM EPROM

RAM

EEPROM

256

TMS370C077A

TMS370C777A

24K

—

512

FN – PLCC / NM –PSDIP

FZ – CLCC / JN –CSDIP

24K

256

†

SE370C777A

—

256

†

System evaluators and development tools are for use only in a prototype environment, and their reliability has not been characterized.

The suffix letter A appended to the device names shown in the device column of Table 1 indicates the

configuration of the device. ROM and EPROM devices have a different configuration as indicated in Table 2.

ROM devices with the suffix letter A are configured through a programmable contact during manufacture.

Table 2. Suffix Letter Configuration

‡

DEVICE

WATCHDOG TIMER

CLOCK

LOW-POWER MODE

EPROM A

Standard

Divide-by-4 (Standard oscillator)

Enabled

Standard

Hard

ROM A

Divide-by-4 or Divide-by-1 (PLL)

Enabled or disabled

Simple

‡

Refer to the “device numbering conventions” section for device nomenclature and the “device part numbers” section for ordering.

The 24K bytes of mask-programmable ROM in the associated TMS370C077 device are replaced with

24K bytes of EPROM in the TMS370C777 while all other available memory and on-chip peripherals are

identical. A one-time-programmable device (OTP) (TMS370C777) and a reprogrammable device

(SE370C777) are available.

The TMS370C777 OTP device is available in a plastic package. This microcontroller is effective for use as an

immediate production update for the TMS370C077 ROM device or for low-volume production runs when the

mask charge or cycle time for the low-cost mask-ROM device is not practical.

TheSE370C777hasawindowedceramicpackagethatallowsreprogrammingoftheprogramEPROMmemory

during the development/prototyping design phase. The SE370C777 device allows quick updates to

breadboards and prototype systems while iterating initial designs.

The TMS370Cx7x family provides two low-power modes (STANDBY and HALT) for applications where

low-power consumption is critical. Both modes stop all CPU activity (that is, no instructions are executed). In

the STANDBY mode, the internal oscillator and the general-purpose timer remain active. In the HALT mode,

all device activity is stopped. The device retains all RAM data and peripheral configuration bits throughout both

low-power modes.

The TMS370Cx7x features advanced register-to-register architecture that allows direct arithmetic and logical

operations without requiring an accumulator (for example, ADD R24, R47; add the contents of register 24 to

the contents of register 47 and store the result in register 47). The TMS370Cx7x family is fully

instruction-set-compatible, allowing easy transition between members of the TMS370 8-bit microcontroller

family.

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TMS370Cx7x

8-BIT MICROCONTROLLER

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

description (continued)

The TMS370Cx7x family provides the system designer with very economical, efficient solutions to real-time

control applications. The TMS370 family compact development tool (CDT ) solves the challenge of efficiently

developing the software and hardware required to design the TMS370Cx7x into an ever-increasing number of

complex applications. The application source code can be written in assembly and C language, and the output

code can be generated by the linker. The TMS370 family CDT development tool can communicate through a

standard RS-232-C interface with an existing personal computer. This allows the use of personal-computer

editors and software utilities already familiar to the designer. The TMS370 family CDT emphasizes ease-of-use

through extensive use of menus and screen windowing so that a system designer with minimal training can

begin developing software. Precise real-time in-circuit emulation and extensive symbolic debug and analysis

tools ensure efficient software and hardware implementation as well as a reduced time-to-market cycle.

The TMS370Cx7x family, together with the TMS370 family CDT370, starter kit, software tools, the SE370C777

reprogrammable device, comprehensive product documentation, and customer support, provide a complete

solution to the needs of the system designer.

CPU

The CPU used on TMS370Cx7x devices is the high-performance 8-bit TMS370 CPU module. The ’x7x

implements an efficient register-to-register architecture that eliminates the conventional accumulator

bottleneck. The complete ’x7x instruction set is summarized in Table 17. Figure 1 illustrates the CPU registers

and memory blocks.

CDT is a trademark of Texas Instruments Incorporated.

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TMS370Cx7x

8-BIT MICROCONTROLLER

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

CPU (continued)

Program Counter (PC)

0

15

0

Legend:

C=Carry

N=Negative

Z=Zero

Stack Pointer (SP)

7

V=Overflow

IE2=Level2 interrupts Enable

IE1=Level1 interrupts Enable

Status Register (ST)

C

7

N

6

Z

5

V

4

IE2 IE1

3

2

1

0

0000h

512-Byte RAM (0000h – 01FFh)

0100h

0200h

†

Reserved

1000h

10C0h

1100h

Peripheral File

†

Reserved

1F00h

2000h

Data EEPROM, 256 Bytes (1F00h–1FFFh)

24K-Byte ROM/EPROM (2000h–7FFFh)

Interrupts and Reset Vectors; Trap Vectors

RAM (Includes 256-Byte Registers File)

0000h

0001h

0002h

0003h

R0(A)

R1(B)

R2

7FC0h

8000h

R3

007Fh

‡

R127

Not Available

00FFh

R255

FFFFh

†

‡

Reserved means that the address space is reserved for future expansion.

Not available means that the address space is not accessible.

Figure 1. Programmer’s Model

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TMS370Cx7x

8-BIT MICROCONTROLLER

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

CPU (continued)

The ’x7x CPU architecture provides the following components:

CPU registers:

–

A stack pointer that points to the last entry in the memory stack

A status register that monitors the operation of the instructions and contains the global-interrupt-enable

bits

–

A program counter (PC) that points to the memory location of the next instruction to be executed

A memory map that includes:

–

512 bytes of general-purpose RAM that can be data memory storage, program instructions,

general-purpose register, or the stack (can be located only in the first 256 bytes)

A peripheral file that provides access to all internal peripheral modules, system-wide control functions,

and EEPROM/EPROM programming control

A 256-byte EEPROM module that provides in-circuit programmability and data retention in power-off

conditions

24K-bytes of ROM or 24K-bytes of EPROM program memory

stack pointer (SP)

The SP is an 8-bit CPU register. Stack operates as a last-in, first-out, read/write memory. The stack is used

typically to store the return address on subroutine calls as well as the status register contents during interrupt

sequences.

The SP points to the last entry or to the top of the stack. The SP increments automatically before data is pushed

onto the stack and decrements after data is popped from the stack. The stack can be located only in the first

256 bytes of the on-chip RAM memory.

status register (ST)

The ST monitors the operation of the instructions and contains the global-interrupt-enable bits. The ST includes

four status bits (condition flags) and two interrupt-enable bits:

The four status bits indicate the outcome of the previous instruction; conditional instructions (for example,

the conditional jump instructions) use these status bits to determine program flow.

The two interrupt-enable bits control the two interrupt levels.

The ST register and status-bit notation are shown in Table 3.

Table 3. Status Register

7

C

6

N

5

Z

4

V

3

2

1

0

IE2

IE1

Reserved

RW-0

R = read, W = write, 0 = value after reset

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TMS370Cx7x

8-BIT MICROCONTROLLER

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

CPU (continued)

program counter (PC)

The contents of the PC point to the memory location of the next instruction to be executed. The PC consists

of two 8-bit registers in the CPU: the program counter high (PCH) and program counter low (PCL). These

registers contain the most-significant byte (MSbyte) and least-significant byte (LSbyte) of a 16-bit address.

The contents of the reset vector (7FFEh, 7FFFh) are loaded into the program counter during reset. The PCH

(MSbyte of the PC) is loaded with the contents of memory location 7FFEh, and the PCL (LSbyte of the PC) is

loaded with the contents of memory location 7FFFh. Figure 2 shows this operation using an example value of

2000h as the contents of memory locations 7FFEh and 7FFFh (reset vector).

Program Counter (PC)

Memory

PCH

20

PCL

00

0000h

20

00

7FFEh

7FFFh

Figure 2. Program Counter After Reset

memory map

The TMS370Cx7x architecture is based on the Von Neuman architecture, where the program memory and data

memory share a common address space. All peripheral input/output is memory-mapped in this same common

address space. As shown in Figure 3, the TMS370Cx7x provides a memory-mapped RAM, ROM, data

EEPROM, EPROM, input/output pins, peripheral functions, and system-interrupt vectors.

The peripheral file contains all input/output port control, peripheral status and control, EPROM, EEPROM

programming, and system-wide control functions. The peripheral file consists of 256 contiguous addresses

located from 1000h to 10FFh. The 256 contiguous addresses are divided logically into 16 peripheral file frames

of 16 bytes each. Each on-chip peripheral is assigned to a separate frame through which peripheral control and

data information is passed. The TMS370Cx7x has its on-chip peripherals and system control assigned to

peripheral file frames 1 through 7, addresses 1010h through 107Fh.

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TMS370Cx7x

8-BIT MICROCONTROLLER

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

memory map (continued)

Peripheral File Control Registers

0000h

†

Reserved

1000h–100Fh

1010h–101Fh

1020h–102Fh

1030h–103Fh

1040h–104Fh

1050h–105Fh

1060h–106Fh

1070h–107Fh

1080h–10BFh

System Control

512-Byte RAM

(0000h–01FFh)

Digital Port Control

†

Reserved

Timer 1 Peripheral Contr.

0200h

†

Reserved

†

Reserved

Timer 2A Peripheral Contr.

ADC1 Peripheral Contr.

1000h

10C0h

Peripheral File

†

Reserved

†

Reserved

1100h

Reserved

Vectors

Trap 15–0

7FC0h–7FDFh

7FE0h–7FEBh

7FECh–7FEDh

7FEEh–7FEFh

7FF0h–7FF1h

7FF2h–7FF3h

7FF4h–7FF5h

7FF6h–7FF7h

7FF8h–7FF9h

7FFAh–7FFBh

7FFCh–7FFDh

7FFEh–7FFFh

256-Byte Data EEPROM

(1F00h–1FFFh)

1F00h

2000h

†

Reserved

ADC1

24K-Byte ROM

(2000h–7FFFh)

Timer 2A

†

Reserved

Timer 1

†

7FC0h

8000h

Interrupts and Reset

Vectors; Trap Vectors

†

Reserved

Interrupt 3

Interrupt 2

Interrupt 1

Reset

‡

Not Available

FFFFh

†

‡

Reserved = the address space is reserved for future expansion.

Not available = address space is unavailable in the mode illustrated.

Figure 3. TMS370Cx7x Memory Map

RAM/register file (RF)

Locations within RAM address space can serve as either register file or general-purpose read/write memory,

program memory, or stack instructions. The TMS370Cx7x device contains 512 bytes of internal RAM mapped

beginning at location 0000h and continuing through location 01FFh which is shown in Figure 3. The first

256 bytes of RAM (0000h – 00FFh) are the register files, R0 through R255.

The first two registers, R0 and R1, are also called registers A and B, respectively. Some instructions implicitly

use register A or B; for example, the instruction LDSP (load SP) assumes that the value to be loaded into the

stack pointer is contained in register B. Registers A and B are the only registers cleared on reset.

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TMS370Cx7x

8-BIT MICROCONTROLLER

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

peripheral file (PF)

The TMS370Cx7x control registers contain all the registers necessary to operate the system and peripheral

modules on the device. The instruction set includes some instructions that access the peripheral file (PF)

directly. These instructions designate the register by the number of the PF relative to 1000h, preceded by P0

for a hexadecimal designator, or by P for a decimal designator. For example, the system control register 0

(SCCR0) is located at address 1010h; its peripheral file hexadecimal designator is P010, and its decimal

designator is P16. Table 4 shows the TMS370Cx7x peripheral files.

Table 4. TMS370Cx7x Peripheral File Address Map

PERIPHERAL FILE

ADDRESS RANGE

DESCRIPTION

DESIGNATOR

P000–P00F

P010–P01F

P020–P03F

P040–P04F

P050–P05F

P060–P06F

P070–P07F

P080–P0FF

1000h–100Fh

1010h–101Fh

1020h–103Fh

1040h–104Fh

1050h–105Fh

1060h–106Fh

1070h–107Fh

1080h–10FFh

Reserved for factory test

System and EEPROM/EPROM control registers

Digital I/O port control registers

Timer 1 registers

Reserved

Timer 2A registers

Analog-to-digital converter 1 registers

Reserved

data EEPROM

The TMS370Cx7x devices contain 256 bytes of data EEPROM, and have a memory map beginning at location

1F00h, and continuing through location 1FFFh. Writing to the data EEPROM module is controlled by the data

EEPROM control register (DEECTL) and the write-protection register (WPR). Programming algorithm

examples are available in the TMS370 Family User’s Guide (literature number SPNU127), or the TMS370

Family Data Manual (SPNS014B). The data EEPROM features include the following:

Programming:

–

Bit, byte, and block write/erase modes

Internal charge pump circuitry: No external EEPROM programming voltage supply is needed.

Control register: Data EEPROM programming is controlled by the data EEPROM control register

(DEECTL) located in the PF frame beginning at location P01A.

–

In-circuit programming capability: There is no need to remove the device to program.

Write-protection: Writes to the data EEPROM are disabled during the following conditions:

–

Reset: All programming of the data EEPROM module is halted.

Write protection active: There is one write-protect bit per 32-byte EEPROM block.

Low-power mode operation

Write protection can be overridden by applying 12 V to MC.

Table 5 shows the memory map of the control registers.

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TMS370Cx7x

8-BIT MICROCONTROLLER

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

data EEPROM (continued)

Table 5. Data EEPROM and Program EPROM Control Registers Memory Map

†

NAME

ADDRESS

101Ah (P01A)

101Bh (P01B)

101Ch (P01C)

101Dh (P01D)

101Eh (P01E)

SYMBOL

DEECTL

Data EEPROM control register

Reserved

EPCTLM

EPCTLL

Program EPROM control register – middle array

Reserved

Program EPROM control register – low array

† For the 24K-byte EPROM device, the program memory is controlled by P01C and P01E.

program EPROM

The TMS370C777 contains 24K bytes of program EPROM made up of one 16K-byte array and one 8K-byte

array. The 16K-byte array is located at address locations 2000h through 5FFFh, and the 8K-byte array is located

at address locations 6000h through 7FFFh, as shown in Table 6.

Table 6. TMS370C777 EPROM Memory Map

PARAMETER

EPROM size

VALUE

24K Bytes

Memory mapped

Control registers

16K Bytes at 2000h–5FFFh

EPCTLL (P01E)

8K Bytes at 6000h–7FFFh

EPCTLM (P01C)

As shown in Table 6 for the two EPROM areas, the 16K-byte array is controlled by register EPCTLL located at

101Eh (P01E), and the 8K-byte array is controlled by register EPCTLM located at 101Ch (P01C).

Reading the program-EPROM modules is identical to reading other internal memory. During programming, the

EPROM is controlled by the program EPROM control registers EPCTLL and EPCTLM. The program EPROM

modules’ features include:

Programming

–

In-circuit programming capability if V is applied to the MC pin

PP

Control register: Program EPROM programming is controlled by the program EPROM control registers

EPCTLL and EPCTLM, located at the addresses in PF frame 1 as shown in Table 5.

–

Programming one EPROM module while executing the other

Write-protection: Writes to the program EPROM are disabled under the following conditions:

–

Reset: All programming to the EPROM module is halted.

Low-power modes

13 V not applied to MC

program ROM

The program ROM consists of 24K bytes of mask-programmable ROM. The program ROM is used for

permanent storage of data or instructions. Programming of the mask ROM is performed at the time of device

fabrication. Memory addresses 7FE0h–7FEBh is reserved for Texas Instruments (TI ). 7FECh to 7FFFh are

reserved for interrupt and reset vectors. Trap vectors, used with TRAP0 through TRAP15 instructions, are

located between addresses 7FC0h and 7FDFh.

TI is a trademark of Texas Instruments Incorporated.

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TMS370Cx7x

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system reset

The system-reset operation ensures an orderly start-up sequence for the TMS370Cx7x CPU-based device.

There are up to three different actions that can cause a system reset to the device. Two of these actions are

generated internally, while one (RESET) is controlled externally. These actions are as follows:

External RESET pin. A low-level signal can trigger an external reset. To ensure a reset, the external signal

should be held low for one SYSCLK cycle (it is possible, however, that a signal of less than one SYSCLK

could cause a reset). See the TMS370 Family User’s Guide (literature number SPNU127) or the TMS370

Family Data Manual (SPNS014B) for more information.

Watchdog (WD) timer. A watchdog-generated reset occurs when an improper value is written to the WD

key register or when the re-initialization does not occur before the watchdog timer timeout. See the TMS370

Family User’s Guide (literature number SPNU127) or the TMS370 Family Data Manual (SPNS014B) for

more information.

Oscillator reset. Reset occurs when the oscillator operates outside the recommended operating range. See

the TMS370 Family User’s Guide (literature number SPNU127) or the TMS370 Family Data Manual

(SPNS014B) for more information.

Once a reset source is activated, the external RESET pin is driven (active) low for a minimum of eight SYSCLK

cycles. This allows the ’x7x device to reset external system components. Additionally, if a cold-start condition

(e.g., V

is off for several hundred milliseconds) exists, an oscillator failure occurs, or the RESET pin is held

CC

low, then the reset logic holds the device in a reset state for as long as these actions are active.

After a reset, the program can check the oscillator fault flag (OSC FLT FLAG, SCCR0.4), the cold start flag

(COLD START, SCCR0.7), and the watchdog reset (WD OVRFL INT FLAG, T1CTL2.5) to determine the source

of the reset. A reset does not clear these flags. Table 7 lists the reset sources.

Table 7. Reset Sources

REGISTER

SCCR0

ADDRESS

1010h

PF

BIT NO.

CONTROL BIT NAME

COLD START

SOURCE OF RESET

Cold (power-up)

P010

P04A

7

4

5

SCCR0

1010h

OSC FLT FLAG

Oscillator out of range

Watchdog timer timeout

T1CTL2

104Ah

WD OVRFL INT FLAG

Once a reset is activated, the following sequence of events occurs:

1. The CPU registers initialize: ST = 00h, SP = 01h (reset state).

2. Registers A and B initialize to 00h (no other RAM is changed).

3. The contents of the LSbyte of the reset vector (07FFh) are read and stored in the PCL.

4. The contents of the MSbyte of the reset vector (07FEh) are read and stored in the PCH.

5. Program execution begins with an opcode fetch from the address pointed to by the PC.

The reset sequence takes 20 SYSCLK cycles from the time the reset pulse is released until the first opcode

fetch. During a reset, RAM contents (except for registers A and B) remain unchanged, and the module control

register bits are initialized to their reset state.

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interrupts

The TMS370 family software programmable interrupt structure permits flexible on-chip and external-interrupt

configurations to meet real-time interrupt-driven application requirements. The hardware-interrupt structure

incorporates two priority levels as shown in Figure 4. Interrupt level 1 has a higher priority than interrupt

level 2. The two priority levels can be masked independently by the global-interrupt mask bits (IE1 and IE2) of

the status register.

Each system interrupt is configured independently to either the high- or low-priority chain by the application

program during system initialization. Within each interrupt chain, the interrupt priority is fixed by the position of

the system interrupt. However, since each system interrupt is configured selectively on either the high- or

low-priority interrupt chain, the application program can elevate any system interrupt to the highest priority.

Arbitration between the two priority levels is performed within the CPU. Arbitration within each of the priority

chains is performed within the peripheral modules to support interrupt expansion for future modules. Pending

interrupts are serviced upon completion of current instruction execution, depending on their interrupt mask and

priority conditions.

The TMS370Cx7x has six hardware-system interrupts (plus RESET) as shown in Table 8. Each system

interrupt has a dedicated vector located in program memory through which control is passed to the interrupt

service routines. All of the interrupt sources are maskable individually by local interrupt-enable control bits in

the associated peripheral file (PF). Each interrupt source FLAG bit is readable individually for software polling

or for determining which interrupt source generated the associated system interrupt. The interrupt-control block

diagram is illustrated in Figure 4.

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interrupts (continued)

EXT INT 3

INT 3

EXT INT 2

INT 2

TIMER 2A

Overflow

TIMER 1

Overflow

INT3 PRI

Compare1

Ext Edge

Compare1

Ext Edge

INT2 PRI

EXT INT1

CPU

Compare2

INT1

Input Capture 1

NMI

Input Capture 2

Watchdog

T2A PRI

T1 PRI

Priority

Logic

INT1 PRI

STATUS REG

IE1

Level 1 INT

Level 2 INT

IE2

Enable

AD INT

AD PRI

A/D

Figure 4. Interrupt Control

Of the six system interrupts, three are generated by on-chip peripherals (T1INT, T2AINT, and ADINT) and three

are external interrupts (INT1 – INT3). Software configuration of the external interrupts is performed through the

INT1, INT2, and INT3 control registers in PF frame 1.

Each external interrupt is individually software configurable for input polarity (rising or falling edge) for ease of

system interface. External interrupt INT1 is software configurable as either a maskable or non-maskable

interrupt. When INT1 is configured as nonmaskable, it cannot be masked by the individual- or global-enable

mask bits. The INT1 NMI bit is protected during non-privileged operation and therefore should be configured

during the initialization sequence following reset. To maximize pin flexibility, external interrupts INT2 and INT3

can be software configured as general-purpose input/output pins if the interrupt function is not required (INT1

can be configured similarly as an input pin). Table 8 lists the interrupt vector sources, corresponding addresses,

and hardware priorities.

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interrupts (continued)

Table 8. Hardware System Interrupts

SYSTEM

INTERRUPT

VECTOR

ADDRESS

†

INTERRUPT SOURCE

External RESET

Watchdog overflow

Oscillator fault detect

INTERRUPT FLAG

PRIORITY

COLD START

WD OVRFL INT FLAG

OSC FLT FLAG

‡

RESET

7FFEh, 7FFFh

1

‡

External INT1

External INT2

External INT3

INT1 FLAG

INT2 FLAG

INT3 FLAG

INT1

INT2

INT3

7FFCh, 7FFDh

7FFAh, 7FFBh

7FF8h, 7FF9h

2

3

4

Timer 1 overflow

T1 OVRFL INT FLAG

T1C1 INT FLAG

T1C2 INT FLAG

T1EDGE INT FLAG

T1IC1 INT FLAG

WD OVRFL INT FLAG

Timer 1 compare 1

Timer 1 compare 2

Timer 1 external edge

Timer 1 input capture 1

Watchdog overflow

§

T1INT

7FF4h, 7FF5h

5

Timer 2A overflow

T2A OVRFL INT FLAG

T2AC1 INT FLAG

T2AC2 INT FLAG

T2AEDGE INT FLAG

T2AIC1 INT FLAG

T2AIC2 INT FLAG

Timer 2A compare 1

Timer 2A compare 2

Timer 2A external edge

Timer 2A input capture 1

Timer 2A input capture 2

T2AINT

ADINT

7FEEh, 7FEFh

7FECh, 7FEDh

6

7

ADC1 conversion complete

AD INT FLAG

†

Relative priority within an interrupt level

‡

§

Releases microcontroller from STANDBY and HALT low-power modes

Releases microcontroller from STANDBY low-power mode

privileged operation and EEPROM write-protection override

The TMS370Cx7x family has significant flexibility to enable the designer to software-configure the system and

peripherals to meet the requirements of a broad variety of applications. The nonprivileged mode of operation

ensures the integrity of the system configuration, once it is defined for an application. Following a hardware

reset, the TMS370Cx7x operates in the privileged mode, where all peripheral file registers have unrestricted

read/write access, and the application program configures the system during the initialization sequence

following reset. As the last step of system initialization, the PRIVILEGE DISABLE bit (SCCR2.0) should be set

to 1 to enter the nonprivileged mode, thereby disabling write operations to specific configuration control bits

within the peripheral file. Table 9 lists the system configuration bits that are write-protected during the

nonprivileged mode and must be configured by software prior to exiting the privileged mode.

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privileged operation and EEPROM write-protection override (continued)

Table 9. Privileged Bits

†

REGISTER

CONTROL BIT

NAME

LOCATION

P010.5

P010.6

PF AUTOWAIT

OSC POWER

SCCRO

P011.2

P011.4

MEMORY DISABLE

AUTOWAIT DISABLE

SCCR1

SCCR2

P012.0

P012.1

P012.3

P012.4

P012.6

P012.7

PRIVILEGE DISABLE

INT1 NMI

CPU STEST

BUS STEST

PWRDWN/IDLE

HALT/STANDBY

P04F.6

P04F.7

T1 PRIORITY

T1 STEST

T1PRI

P06F.6

P06F.7

T2A PRIORITY

T2A STEST

T2APRI

P07F.5

P07F.6

P07F.7

AD ESPEN

AD PRIORITY

AD STEST

ADPRI

†

The privileged bits are shown in a bold typeface in the peripheral file frame 1 section.

The write-protect-override (WPO) mode provides an external hardware method of overriding the

write-protection registers of the data EEPROM on the TMS370Cx7x. To enter the WPO mode apply a 12-V input

to the MC pin after the RESET input goes high (logic 1). The high voltage on MC during the WPO mode is not

the programming voltage for the data EEPROM or program EPROM. All EEPROM programming voltages are

generated on-chip. The WPO mode provides hardware-system-level capability to modify the content of the data

EEPROM while the device remains in the application but only while requiring a 12-V external input on the MC

pin (normally not available in the end application except in a service or diagnostic environment).

low-power and IDLE modes

The TMS370Cx7x devices have two low-power modes (STANDBY and HALT) and an IDLE mode. For

mask-ROM devices, low-power modes can be disabled permanently through a programmable contact at the

time when the mask is manufactured.

The STANDBY and HALT low-power modes significantly reduce power consumption by reducing or stopping

the activity of the various on-chip peripherals when processing is not required. Each of the low-power modes

is entered by executing the idle instruction when the PWRDWN/IDLE bit in register SCCR2 has been set to 1.

The HALT/STANDBY bit in SCCR2 controls which low-power mode is entered.

In the STANDBY mode (HALT/STANDBY = 0), all CPU activity and most peripheral module activity is stopped;

however, the oscillator, internal clocks, and timer 1 remain active. System processing is suspended until a

qualified interrupt (hardware RESET, external interrupt on INT1, INT2, INT3, or timer 1 interrupt) is detected.

In the HALT mode (HALT/STANDBY = 1), the TMS370Cx7x is placed in its lowest power-consumption mode.

The oscillator and internal clocks are stopped, causing all internal activity to be halted. System activity is

suspended until a qualified interrupt (hardware RESET or an external interrupt on INT1, INT2, INT3) is detected.

The low-power mode selection bits are summarized in Table 10.

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low-power and IDLE modes (continued)

Table 10. Low-Power/Idle Control Bits

POWER-DOWN CONTROL BITS

MODE SELECTED

PWRDWN/IDLE

(SCCR2.6)

HALT/STANDBY

(SCCR2.7)

1

0

1

STANDBY

HALT

1

0

X

IDLE

X = don’t care

When low-power modes are disabled through a programmable contact in the mask-ROM devices, writing to the

SCCR2.6–7 bits is ignored. In addition, if an IDLE instruction is executed when low-power modes are disabled

through a programmable contact, the device always enters the IDLE mode.

To provide a method of always exiting low-power modes for mask-ROM devices, INT1 is enabled automatically

as a nonmaskable interrupt (NMI) during low-power modes when the hard watchdog is selected. This means

that the NMI always is generated, regardless of the interrupt enable flags.

The following information is preserved throughout both the STANDBY and HALT modes: RAM (register file),

CPU registers (stack pointer, program counter, and status register), I/O pin direction and output data, and status

registers of all on-chip peripheral functions. Since all CPU instruction processing is stopped during the

STANDBY and HALT modes, the clocking of the watchdog timer is inhibited.

clock modules

The ‘370Cx7x family provides two clock options which are referred to as divide-by-1 (PLL) and divide-by-4

(standard oscillator). Both the divide-by-1 and divide-by-4 options are configurable during the manufacturing

process of a TMS370 microcontroller. The ‘370Cx7x ROM-masked devices offer both options to meet system

engineering requirements. Only one of the two clock options is allowed on the ROM device while the EPROM

devices have the divide-by-4 option.

The divide-by-1 clock module option provides the capability for reduced electromagnetic interference (EMI) with

no added cost.

The divide-by-1 provides a 1-to-1 match of the external resonator frequency to the internal system clock

(SYSCLK) frequency. The divide-by-4 produces a SYSCLK which is one-fourth the frequency of the external

resonator. Inside the divide-by-1 module, the frequency of the external resonator is multiplied by four. The clock

module then divides the resulting signal by four to provide the four-phased internal system clock signals. The

resulting SYSCLK is equal to the resonator frequency. The frequencies are formulated as follows:

external resonator frequency

CLKIN

4

Divide-by-4 option : SYSCLK

Divide-by-1 option : SYSCLK

4

external resonator frequency

4

CLKIN

The main advantage of choosing a divide-by-1 oscillator is the improved EMI performance. The harmonics of

low-speed resonators extend through less of the emissions spectrum than the harmonics of faster resonators.

The divide-by-1 provides the capability of reducing the resonator speed by four times, and this results in a

steeper decay of emissions produced by the oscillator.

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system configuration registers

Table 11 lists system configuration, control functions, and registers for controlling EEPROM programming. The

privileged bits are bold typefaced and shaded.

Table 11. Peripheral File Frame 1: System Configuration Registers

PF

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

COLD

START

OSC

POWER

PF AUTO

WAIT

OSC FLT

FLAG

MC PIN

WPO

MC PIN

DATA

µP/µC

MODE

P010

—

SCCR0

AUTOWAIT

DISABLE

MEMORY

DISABLE

P011

P012

—

SCCR1

SCCR2

HALT/

STANDBY

PWRDWN/

IDLE

BUS

STEST

CPU

STEST

INT1

NMI

PRIVILEGE

DISABLE

—

P013

to

Reserved

P016

INT1

FLAG

INT1

PIN DATA

INT1

POLARITY

INT1

PRIORITY

INT1

ENABLE

P017

P018

P019

—

INT1

INT2

FLAG

INT2

PIN DATA

INT2

DATA DIR

INT2

DATA OUT

INT2

POLARITY

INT2

PRIORITY

INT2

ENABLE

INT3

FLAG

INT3

PIN DATA

INT3

DATA DIR

INT3

DATA OUT

INT3

POLARITY

INT3

PRIORITY

INT3

ENABLE

—

INT3

P01A

P01B

P01C

P01D

P01E

P01F

BUSY

—

AP

—

W1W0

W0

EXE

DEECTL

Reserved

VPPS

—

EPCTLM

EPCTLL

Reserved

—

W0

Reserved

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digital port control registers

Peripheral file frame 2 contains the digital I/O pin configuration and control registers. Table 12 lists the specific

addresses, registers, and control bits within this peripheral file frame. Table 13 shows the port-configuration

register setup.

Table 12. Peripheral File Frame 2: Digital Port Control Registers

PF

P020

P021

P022

P023

P024

P025

P026

P027

P028

P029

P02A

P02B

P02C

P02D

P02E

P02F

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

Reserved

APORT1

APORT2

ADATA

ADIR

Port A Control Register 2

Port A Data

Port A Direction

Reserved

BPORT1

BPORT2

BDATA

BDIR

Port B Control Register 2

Port B Data

Port B Direction

Reserved

CPORT1

CPORT2

CDATA

CDIR

Port C Control Register 2

Port C Data

Port C Direction

Port D Control Register 1

DPORT1

DPORT2

DDATA

DDIR

†

Port D Control Register 2

Port D Data

Port D Direction

P030

to

Reserved

P035

P036

P037

–

Port G Data

Port G Direction

GDATA

GDIR

†

To configure pin D3 as SYSCLK, set port D control register 2 = 08h.

Table 13. Port Configuration Register Setup

abcd

00y0

abcd

00q1

PORT

A

B

C

D

G

0–7

0–5

Data In y

Data Out q

Data In y

‡

a = Port x Control Register 1

b = Port x Control Register 2

c = Data

d = Direction

‡

DPORT only

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timer 1 (T1) module

The programmable timer 1 (T1) module of the TMS370Cx7x provides the designer with the enhanced timer

resources required to perform real-time system control. The T1 module contains the general-purpose timer and

the watchdog (WD) timer. The two independent 16-bit timers, T1 and WD, allow program selection of input clock

sources (real-time, external event, or pulse-accumulate) with multiple 16-bit registers (input capture and

compare) for special timer function control. The T1 module includes three external device pins that can be used

for multiple counter functions (operation-mode dependent) or used as general-purpose I/O pins. The T1 module

block diagram is shown in Figure 5.

Edge

Select

16-Bit

Capt/Comp

T1IC/CR

Register

16-Bit

Counter

PWM

Toggle

MUX

T1PWM

16

16-Bit

Compare

Register

Interrupt

Logic

8-Bit

Prescaler

T1EVT

Interrupt

Logic

16-Bit

MUX

Watchdog Counter

(Aux. Timer)

Figure 5. Timer 1 Block Diagram

Three T1 I/O pins:

–

T1IC/CR: Timer 1 input capture / counter reset input pin, or general-purpose bidirectional I/O pin

T1PWM: Timer 1 pulse-width-modulation (PWM) output pin, or general-purpose bidirectional I/O pin

T1EVT: Timer 1 event input pin, or general-purpose bidirectional I/O pin

Two operation modes:

–

Dual-compare mode: Provides PWM signal

Capture/compare mode: Provides input-capture pin

One 16-bit general-purpose resettable counter

One 16-bit compare register with associated compare logic

One 16-bit capture/compare register, which, depending on the mode of operation, operates as either

capture or compare register.

One 16-bit watchdog counter can be used as an event counter, a pulse accumulator, or an interval timer

if watchdog feature is not needed.

Prescaler/clock sources that determine one of eight clock sources for general-purpose timer

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timer 1 (T1) module (continued)

Selectable edge-detection circuitry that, depending on the mode of operation, senses active transitions on

the input capture pins (T1IC/CR).

Interrupts that can be generated on the occurrence of:

–

A capture

A compare equal

A counter overflow

An external edge detection

Sixteen T1 module control registers: Located in the PF frame beginning at address P040

Table 14 lists the T1 module control register.

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timer 1 (T1) module (continued)

Table 14. Timer 1 Module Register Memory Map

PF

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

Modes: Capture/Compare and Dual-Compare

P040 Bit 15

P041 Bit 7

P042 Bit 15

P043 Bit 7

P044 Bit 15

P045 Bit 7

P046 Bit 15

P047 Bit 7

P048 Bit 7

T1 Counter MSbyte

T1 Counter LSbyte

Bit 8 T1CNTR

Bit 0

Compare Register MSbyte

Compare Register LSbyte

Capture/Compare Register MSbyte

Capture/Compare Register LSbyte

Watchdog Counter MSbyte

Watchdog Counter LSbyte

Watchdog Reset Key

Bit 8 T1C

Bit 0

Bit 8 T1CC

Bit 0

Bit 8 WDCNTR

Bit 0

Bit 0 WDRST

WD

INPUT

SELECT2

WD

INPUT

SELECT1

WD

INPUT

†

SELECT0

T1

INPUT

SELECT2

T1

INPUT

SELECT1

WD OVRFL

TAP SEL

T1 INPUT

SELECT0

P049

P04A

—

T1CTL1

T1CTL2

†

WD OVRFL WD OVRFL WD OVRFL

T1 OVRFL

INT ENA

T1 OVRFL

INT FLAG

T1 SW

RESET

—

†

RST ENA

INT ENA

INT FLAG

Mode: Dual-Compare

T1EDGE

INT FLAG

T1C2

INT FLAG

T1C1

INT FLAG

T1EDGE

INT ENA

T1C2

INT ENA

T1C1

INT ENA

P04B

P04C

—

T1CTL3

T1CTL4

T1

T1C1

OUT ENA

T1C2

OUT ENA

T1C1

RST ENA

T1CR

OUT ENA

T1EDGE

POLARITY

T1CR

RST ENA

T1EDGE

DET ENA

MODE = 0

Mode: Capture/Compare

T1EDGE

—

T1C1

INT FLAG

T1EDGE

INT ENA

T1C1

INT ENA

P04B

P04C

—

T1CTL3

T1CTL4

INT FLAG

T1

T1C1

RST ENA

T1EDGE

POLARITY

T1EDGE

DET ENA

—

MODE = 1

OUT ENA

Modes: Capture/Compare and Dual-Compare

T1EVT

DATA IN

T1EVT

DATA OUT

T1EVT

FUNCTION

T1EVT

DATA DIR

P04D

P04E

—

T1PC1

T1PC2

T1PRI

T1PWM

DATA IN

T1PWM

DATA OUT

T1PWM

FUNCTION

T1PWM

DATA DIR

T1IC/CR

DATA IN

T1IC/CR

DATA OUT

T1IC/CR

FUNCTION

T1IC/CR

DATA DIR

T1

P04F T1 STEST

—

PRIORITY

†

Once the WD OVRFL RST ENA bit is set, these bits cannot be changed until a reset; this applies only to the standard

watchdog and to simple counter. In the hard watchdog, these bits can be modified at any time; the WD INPUT SELECT2

bits are ignored.

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8-BIT MICROCONTROLLER

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

timer 1 (T1) module (continued)

The T1 capture/compare-mode block diagram is illustrated in Figure 6. The annotations on the diagram identify

the register and the bit(s) in the peripheral frame. For example, the actual address of T1CTL2.0 is 104Ah,

bit 0, in the T1CTL2 register.

T1CC.15-0

16-Bit

LSB

T1C1

OUT ENA

Capt/Comp

Register

Prescale

Clock

Source

MSB

T1PC2.7-4

T1PWM

T1CTL4.6

T1CNTR.15-0

LSB

MSB

16-Bit

Counter

16

T1 PRIORITY

0

1

T1C1 INT FLAG

T1CTL3.5

T1PRI.6

Level 1 Int

Level 2 Int

Compare=

Reset

T1CTL3.0

T1C.15-0

T1 SW

RESET

T1C1 INT ENA

16-Bit

LSB

T1C1

RST ENA

Compare

Register

T1CTL2.0

MSB

T1 OVRFL INT FLAG

T1CTL2.3

T1CTL4.4

T1CTL2.4

T1 OVRFL INT ENA

T1PC2.3-0

T1IC/CR

T1EDGE DET ENA

T1EDGE INT FLAG

T1CTL3.7

Edge

Select

T1CTL4.0

T1CTL3.2

T1EDGE INT ENA

T1CTL4.2

T1EDGE POLARITY

Figure 6. Capture/Compare Mode

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx7x

8-BIT MICROCONTROLLER

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

timer 1 (T1) module (continued)

The T1 dual-compare mode block diagram is illustrated in Figure 7. The annotations on the diagram identify

the register and the bit(s) in the peripheral frame. For example, the actual address of T1CTL2.0 is 104Ah,

bit 0, in the T1CTL2 register.

T1CC.15-0

16-Bit

Capt/Comp

Register

T1C2 INT FLAG

T1CTL3.6

LSB

Prescaler

Clock

Source

MSB

Output

Enable

T1CTL3.1

T1C2 INT ENA

T1CTL4.5

Compare=

T1CNTR.15-0

T1PC2.7-4

T1PWM

T1C2 OUT ENA

T1CTL4.6

LSB

MSB

16-Bit

Counter

16

T1C1 INT FLAG

T1CTL3.5

Reset

Compare=

T1C1 OUT ENA

T1CTL4.3

T1CTL3.0

T1C1 INT ENA

T1C1

RST ENA

T1C.15-0

T1 SW

RESET

16-Bit

Compare

Register

LSB

T1CTL4.4

T1CR OUT ENA

T1CTL2.0

MSB

T1 OVRFL INT FLAG

T1CTL2.3

T1CTL2.4

T1 OVRFL INT ENA

T1CTL4.1

T1CR

RST ENA

T1PC2.3-0

T1IC/CR

Edge

Select

T1 PRIORITY

T1PRI.6

T1CTL4.0

0

1

Level 1 Int

Level 2 Int

T1EDGE INT FLAG

T1CTL3.7

T1EDGE DET ENA

T1CTL4.2

T1CTL3.2

T1EDGE INT ENA

T1EDGE POLARITY

Figure 7. Dual-Compare Mode

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx7x

8-BIT MICROCONTROLLER

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

timer 1 (T1) module (continued)

The TMS370Cx7x device includes a 24-bit watchdog (WD) timer, contained in the T1 module, which can be

software programmed as an event counter, pulse accumulator, or interval timer if the WD function is not used.

The WD function is to monitor software and hardware operation, and it implements a system reset when the

WD counter is not serviced properly (WD counter overflow or WD counter is reinitialized by an incorrect value).

The WD can be configured as one of the three mask options: standard WD, hard WD, or simple counter.

Standard watchdog configuration for EPROM and mask-ROM devices (see Figure 8)

–

Watchdog

–

Ten different WD overflow rates ranging from 6.55 ms to 3.35 s at 5-MHz SYSCLK

AWDresetkey(WDRST)registerisusedtoclearthewatchdogcounter(WDCNTR)whenacorrect

value is written.

–

Generates a system reset if an incorrect value is written to the WD reset key or if the counter

overflows

A WD overflow flag (WD OVRFL INT FLAG) bit that indicates whether the WD timer initiated a

system reset

–

Non-watchdog

Watchdog timer can be configured as an event counter, pulse accumulator, or an interval timer

–

WDCNTR.15-0

WD OVRFL

INT FLAG

T1CTL2.6

16-Bit

Watchdog Counter

T1CTL2.5

Interrupt

WD OVRFL

INT ENA

Reset

Clock

Prescaler

T1CTL1.7

T1CTL2.7

WD OVRFL

TAP SEL

System Reset

WD OVRFL

RST ENA

Watchdog Reset Key

WDRST.7-0

Figure 8. Standard Watchdog

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx7x

8-BIT MICROCONTROLLER

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

timer 1 (T1) module (continued)

Hard watchdog configuration for mask-ROM device (see Figure 9)

–

Eight different WD overflow rates ranging from 26.2 ms to 3.35 s at 5-MHz SYSCLK

A WD reset key (WDRST) register is used to clear the watchdog counter (WDCNTR) when a correct

value is written.

–

Generates a system reset if an incorrect value is written to the watchdog reset key or if the counter

overflows

–

Automatic activation of the WD timer upon power-up reset

INT1 is enabled as nonmaskable interrupt during low-power modes

A WD overflow flag (WD OVRFL INT FLAG) bit that indicates whether the WD timer initiated a system

reset

WDCNTR.15-0

WD OVRFL

INT FLAG

16-Bit

Watchdog Counter

T1CTL2.5

Reset

Clock

Prescaler

T1CTL1.7

System Reset

WD OVRFL

TAP SEL

Watchdog Reset Key

WDRST.7-0

Figure 9. Hard Watchdog

27

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx7x

8-BIT MICROCONTROLLER

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

timer 1 (T1) module (continued)

Simple-counter configuration for mask-ROM devices only (see Figure 10)

–

Simple counter can be configured as an event counter, pulse accumulator, or an interval timer.

WDCNTR.15-0

WD OVFL

16-Bit

Watchdog Counter

T1CTL2.6

INT FLAG

Interrupt

T1CTL2.5

WD OVRFL

INT ENA

Reset

Clock

Prescaler

T1CTL1.7

WD OVRFL

TAP SEL

Watchdog Reset Key

WDRST.7-0

Figure 10. Simple Counter

timer 2A (T2A) module

The 16-bit general-purpose timer 2A (T2A) module is composed of a 16-bit resettable counter, 16-bit compare

register with associated compare logic, 16-bit capture register, and a 16-bit register that functions as a capture

register in one mode and as a compare register in the other mode. The T2A module adds an additional timer

that provides event count, input capture, and compare functions. The T2A module includes three external

device pins that can be dedicated as timer functions or used as general-purpose I/O pins. The T2A module block

diagram is shown in Figure 11.

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx7x

8-BIT MICROCONTROLLER

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

timer 2A (T2A) module (continued)

Edge

Detect

T2AIC1/CR

16-Bit

Capt/Comp

Register

Edge

Detect

T2AIC2/PWM

(Dual-Capture Mode)

PWM

Toggle

T2AIC2/PWM

16-Bit

Capture

Register

INT

Logic

(Dual-Compare Mode)

16

16-Bit

Compare

Register

Clock

T2AEVT

16-Bit

Counter

Select

Figure 11. Timer 2A Block Diagram

The T2A module features include the following:

Three T2A I/O pins:

–

T2AIC1/CR: T2A input capture 1/counter reset input pin, or general-purpose bidirectional I/O pin

T2AIC2/PWM: T2A input capture 2/pulse-width-modulation (PWM) output pin, or general-purpose

bidirectional I/O pin

–

T2AEVT: T2A event input pin, or general-purpose bidirectional I/O pin

Two operation modes:

–

Dual-compare mode: Provides PWM signal

Dual-capture mode: Provides input capture pin

One 16-bit general-purpose resettable counter

One 16-bit compare register with associated compare logic

One 16-bit capture register with associated capture logic

One 16-bit capture/compare register, which, depending on the mode of operation, operates as either a

capture or compare register

T2A clock sources can be any of the following:

–

System clock

No clock (the counter is stopped)

External clock synchronized to the system clock (event counter)

System clock while external input is high (pulse accumulation)

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx7x

8-BIT MICROCONTROLLER

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

timer 2A (T2A) module (continued)

Selectable edge-detection circuitry that, depending on the mode of operation, senses active transitions on

the input capture pins (T2AIC1/CR)

Interrupts that can be generated on the occurrence of:

–

A compare equal to dedicated-compare register

A compare equal to capture-compare register

A counter overflow

An external edge 1 detection

An external edge 2 detection

Fourteen T2A module control registers located in the PF frame beginning at address P060

The T2A module control registers are listed in Table 15.

Table 15. Timer 2A Module Register Memory Map

PF

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

Modes: Dual-Compare and Dual-Capture

P060 Bit 15

P061 Bit 7

P062 Bit 15

P063 Bit 7

P064 Bit 15

P065 Bit 7

P066 Bit 15

P067 Bit 7

T2A Counter MSbyte

T2A Counter LSbyte

Bit 8

T2ACNTR

T2AC

Bit 0

Bit 8

Bit 0

Bit 8

Bit 0

Bit 8

Bit 0

Compare Register MSbyte

Compare Register LSbyte

Capture/Compare Register MSbyte

Capture/Compare Register LSbyte

Capture Register 2 MSbyte

Capture Register 2 LSbyte

T2ACC

T2AIC

T2A

OVRFL INT

ENA

T2A

OVRFL INT

FLAG

T2A

INPUT

SELECT1

T2A INPUT

SELECT0

T2A SW

RESET

P06A

—

T2ACTL1

Mode: Dual-Compare

T2AEDGE1

INT FLAG

T2AC2

INT FLAG

T2AC1

INT FLAG

T2AEDGE1

INT ENA

T2AC2

INT ENA

T2AC1

INT ENA

P06B

P06C

—

T2ACTL2

T2ACTL3

T2A

MODE = 0

T2AC1

OUT ENA

T2AC2

OUT ENA

T2AC1

RST ENA

T2AEDGE1 T2AEDGE1 T2AEDGE1 T2AEDGE1

OUT ENA

POLARITY

RST ENA

DET ENA

Mode: Dual-Capture

T2AEDGE1

INT FLAG

T2AEDGE2

INT FLAG

T2AC1

INT FLAG

T2AEDGE1 T2AEDGE2

INT ENA INT ENA

T2AC1

INT ENA

P06B

P06C

—

T2ACTL2

T2ACTL3

T2A

MODE = 1

T2AC1

RST ENA

T2AEDGE2 T2AEDGE1 T2AEDGE2 T2AEDGE1

—

POLARITY

DET ENA

Modes: Dual-Compare and Dual-Capture

T2AEVT

DATA IN

T2AEVT

DATA OUT

T2AEVT

FUNCTION

T2AEVT

DATA DIR

P06D

P06E

P06F

—

T2APC1

T2APC2

T2APRI

T2AIC2/PWM T2AIC2/PWM T2AIC2/PWM T2AIC2/PWM T2AIC1/CR T2AIC1/CR

T2AIC1/CR

FUNCTION

T2AIC/CR

DATA DIR

DATA IN

DATA OUT

FUNCTION

DATA DIR

DATA IN

DATA OUT

T2A

PRIORITY

T2A STEST

—

30

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx7x

8-BIT MICROCONTROLLER

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

timer 2A (T2A) module (continued)

The timer 2A dual-compare mode block diagram is illustrated in Figure 12. The annotations on the diagram

identify the register and the bit(s) in the peripheral frame. For example, the actual address of T2ACTL2.0 is

106Bh, bit 0, in the T2ACTL2 register.

T2ACC.15-0

16-Bit

LSB

Capt/Comp

Register

MSB

Output

Enable

Clock

Source

T2AC2 INT FLAG

T2ACTL2.6

T2ACTL2.1

T2AC2 INT ENA

T2ACTL3.5

Compare=

16

T2ACNTR.15-0

T2APC2.7-4

T2AC2 OUT ENA

T2ACTL3.6

LSB

MSB

16-Bit

Counter

T2AIC2/PWM

T2AC1 INT FLAG

T2ACTL2.5

T2ACTL2.0

T2AC1 INT ENA

Reset

Compare=

T2AC.15-0

T2AC1 OUT ENA

T2ACTL3.3

T2A SW

RESET

T2AC1

RST ENA

T2ACTL3.4

16-Bit

Compare

Register

LSB

T2ACTL1.0

T2AEDGE1

OUT ENA

MSB

T2A OVRFL INT FLAG

T2ACTL1.3

T2ACTL3.1

T2AEDGE1

RST ENA

T2ACTL1.4

T2APC2.3-0

T2AIC1/CR

T2A OVRFL INT ENA

Edge 1

Select

T2A PRIORITY

T2APRI.6

T2ACTL3.0

T2AEDGE1 DET ENA

0

1

T2AEDGE1 INT FLAG

T2ACTL2.7

Level 1 Int

Level 2 Int

T2ACTL3.2

T2ACTL2.2

T2AEDGE1 POLARITY

T2AEDGE1 INT ENA

Figure 12. Dual-Compare Mode

31

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx7x

8-BIT MICROCONTROLLER

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

timer 2A (T2A) module (continued)

The timer 2A dual-capture mode block diagram is illustrated in Figure 13. The annotations on the diagram

identify the register and the bit(s) in the peripheral frame. For example, the actual address of T2ACTL2.0 is

106Bh, bit 0, in the T2ACTL2 register.

T2AIC.15–0

T2ACC.15–0

16-Bit

Capture

Register 2

16-Bit

Capt/Comp

Register 1

LSB

MSB

Clock

Source

T2ACNTR.15–0

LSB

16-Bit

Counter

16

MSB

T2A PRIORITY

T2APRI.6

0

1

T2AC1 INT FLAG

T2ACTL2.5

Level 1 Int

Level 2 Int

Compare =

Reset

T2ACTL2.0

T2AC.15–0

T2AC1 INT ENA

T2A SW

RESET

T2A OVRFL INT FLAG

T2ACTL1.3

16-Bit

Compare

Register

LSB

T2AC1

RST ENA

MSB

T2ACTL1.0

T2ACTL1.4

T2A OVRFL INT ENA

T2ACTL3.4

T2ACTL3.0

T2AEDGE1 INT FLAG

T2AEDGE1 DET ENA

T2ACTL2.7

T2APC2.3–0

Edge1

Select

T2ACTL2.2

T2AIC1/CR

T2ACTL3.2

T2AEDGE1 INT ENA

T2AEDGE1 POLARITY

T2ACTL3.1

T2AEDGE2 INT FLAG

T2ACTL2.6

T2APC2.7–4

T2AIC2/PWM

Edge 2

Select

T2AEDGE2 DET ENA

T2ACTL3.3

T2ACTL2.1

T2AEDGE2 POLARITY

T2AEDGE2 INT ENA

Figure 13. Dual-Capture Mode

32

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx7x

8-BIT MICROCONTROLLER

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

analog-to-digital converter 1 (ADC1) module

The analog-to-digital converter 1 (ADC1) module is an 8-bit, successive approximation converter with internal

sample-and-hold circuitry. The module has eight multiplexed analog input channels that allow the processor to

convert the voltage levels from up to eight different sources. The ADC1 module features include the following:

Minimum conversion time: 32.8 µs at 5-MHz SYSCLK

Ten external pins:

–

Eight analog input channels (AN0–AN7), any of which can be software configured as digital inputs

(E0–E7) if not needed as analog channels. AN1–AN7 also can be configured as positive input voltage

reference.

–

V

: ADC1 module high-voltage reference input

CC3

V

: ADC1 module low-voltage reference input

SS3

The ADDATA register which contains the digital result of the last ADC1 conversion

ADC1 operations can be accomplished through either interrupt driven or polled algorithms

Six ADC1 module control registers are located in the control register frame beginning at address 1070h.

The ADC1 module control registers are listed in Table 16.

Table 16. ADC1 Module Control Register Memory Map

PF

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

CONVERT

START

SAMPLE

START

REF VOLT

SELECT2

REF VOLT

SELECT1

REF VOLT

SELECT0

AD INPUT

SELECT2

AD INPUT

SELECT1

AD INPUT

SELECT0

P070

ADCTL

AD INT

FLAG

AD INT

ENA

P071

P072

—

AD READY

ADSTAT

ADDATA

A/D Conversion Data Register

Reserved

P073

to

P07C

P07D

P07E

Port E Data Input Register

Port E Input Enable Register

ADIN

ADENA

AD

PRIORITY

P07F AD STEST

AD ESPEN

—

ADPRI

33

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TMS370Cx7x

8-BIT MICROCONTROLLER

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

analog-to-digital converter 1 (ADC1) module (continued)

The ADC1 module block diagram is illustrated in Figure 14.

Port E Input

Port E Data

ENA 0

AN 0

ADENA.0

SAMPLE

START

CONVERT

START

ADIN.0

2

1

0

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

ADCTL.2–0

ADCTL.6

ADCTL.7

Port E Input

ENA 1

Port E Data

AN 1

AD INPUT SELECT

ADENA.1

ADIN.1

Port E Input

ENA 2

Port E Data

AN 2

ADENA.2

ADIN.2

Port E Input

ENA 3

Port E Data

AN 3

ADENA.3

ADIN.3

ADC1

Port E Input

ENA 4

Port E Data

AN 4

ADENA.4

ADIN.4

ADDATA.7–0

Port E Input

ENA 5

Port E Data

AN 5

A/D

Conversion

ADENA.5

ADIN.5

Data Register

Port E Input

ENA 6

AD READY

ADSTAT.2

Port E Data

AN 6

ADENA.6

ADIN.6

5

4

3

AD PRIORITY

ADCTL.5–3

Port E Input

ENA 7

Port E Data

AN 7

0

1

Level 1 INT

Level 2 INT

ADPRI.6

REF VOLTS SELECT

ADENA.7

ADIN.7

V

AD INT FLAG

ADSTAT.1

CC3

V

SS3

ADSTAT.0

AD INT ENA

Figure 14. ADC1 Block Diagram

34

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx7x

8-BIT MICROCONTROLLER

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

instruction set overview

Table 17 provides an opcode-to-instruction cross reference of all 73 instructions and 274 opcodes of the

‘370Cx7x instruction set. The numbers at the top of this table represent the most significant nibble of the opcode

while the numbers at the left side of the table represent the least significant nibble. The instruction of these two

opcode nibbles contains the mnemonic, operands, and byte/cycle particular to that opcode.

For example, the opcode B5h points to the CLR A instruction. This instruction contains one byte and executes

in eight SYSCLK cycles.

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TMS370Cx7x

8-BIT MICROCONTROLLER

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

development system support

The TMS370 family development support tools include an assembler, a C compiler, a linker, compact

development tool, and an EEPROM/UVEPROM programmer.

Assembler/linker (Part No. TMDS3740850–02 for PC)

–

Includes extensive macro capability

Provides high-speed operation

Provides format conversion utilities for popular formats

ANSI C compiler (Part No. TMDS3740855–02 for PC, Part No. TMDS3740555–09 for HP700 , Sun-3 ,

or Sun-4 )

–

Generates assembly code for the TMS370 that can be easily inspected

Improves code execution speed and reduces code size with optional optimizer pass

Enables direct referencing of the TMS370’s port registers by using a naming convention

Provides flexibility in specifying the storage for data objects

Interfaces C functions and assembly functions easily

Includes assembler and linker

CDT370 (compact development tool) Timer real-time in-circuit emulation

–

Base (Part Number EDSCDT37T – for PC, requires cable)

–

Cable for 68-pin PLCC (Part No. EDSTRG68PLCC)

Cable for 64-pin SDIP (Part No. EDSTRG64SDIL)

–

Includes EEPROM and EPROM programming support

Allows inspection and modification of memory locations

Uploads/downloads program and data memory

Executes programs and software routines

Includes 1024 samples trace buffer

Includes single-step executable instructions

Uses software breakpoints to halt program execution at selected address

Microcontroller programmer

–

Base (Part No. TMDS3760500A — for PC, requires programmer head)

–

Single unit head for 68-pin PLCC (Part No. TMDS3780510A)

Single unit head for 64-pin SDIP (Part No. TMDS3780511A)

–

Includes PC-based, window/function-key oriented user interface for ease of use and rapid learning

environment

HP700 is a trademark of Hewlett-Packard Company.

Sun-3 and Sun-4 are trademarks of Sun Microsystems, Inc.

38

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx7x

8-BIT MICROCONTROLLER

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

development system support (continued)

Starter Kit (Part No. TMDS37000 — for PC)

–

Includes TMS370 assembler diskette and documentation

Includes TMS370 simulator

Includes programming adapter board and programming software

Not included (to be supplied by the user):

–

+ 5 V power supply

ZIF sockets

9-pin RS232 cable

device numbering conventions

Figure 15 illustrates the numbering and symbol nomenclature for the TMS370Cx7x family.

TMS 370 C

7

A FN T

Prefix: TMS = Standard prefix for fully qualified devices

SE = System evaluator (window EPROM) that is used for

prototyping purpose

Family: 370 = TMS370 8-Bit Microcontroller Family

Technology:

C = CMOS

Program Memory Types:

0 = Mask ROM

7 = EPROM

Device Type:

7 = ’x7x device containing the following modules:

– Timer 1

– Timer 2A

– Analog-to-Digital Converter 1

Memory Size:

7 = 24K bytes

Temperature Ranges:

A = –40°C to 85°C

L =

0°C to 70°C

T = –40°C to 105°C

Packages:

FN = Plastic Leaded Chip Carrier

FZ = Ceramic Leaded Chip Carrier

NM = Plastic Shrink Dual-In-Line

JN = Ceramic Shrink Dual-in-Line

ROM and EPROM Option:

A = For ROM device, the watchdog timer can be configured

as one of the three different mask options:

– A standard watchdog

– A hard watchdog

– A simple watchdog

The clock can be either:

– Divide-by-4 clock

– Divide-by-1 (PLL) clock

The low-power modes can be either:

– Enabled

– Disabled

A = For EPROM device, standard watchdog, divide-by-4

clock, and low-power modes are enabled

Figure 15. TMS370Cx7x Family Nomenclature

39

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx7x

8-BIT MICROCONTROLLER

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

device part numbers

Table 18 lists all the TMS370Cx7x devices available. The device part-number nomenclature is designed to

assist ordering. Upon ordering, the customer must specify not only the device part number, but also the clock

and watchdog-timer options desired. Each device can have only one of the three possible watchdog-timer

options and one of the two clock options. The options to be specified pertain solely to orders involving ROM

devices.

Table 18. Device Part Numbers

DEVICE PART NUMBERS

FOR 68 PINS (LCC)

DEVICE PART NUMBERS

FOR 64 PINS (DIP)

TMS370C077AFNA

TMS370C077AFNL

TMS370C077AFNT

TMS370C077ANMA

TMS370C077ANML

TMS370C077ANMT

TMS370C777AFNT

TMS370C777ANMT

†

SE370C777AJNT

SE370C777AFZT

†

System evaluators are for use only in prototype environment, and their

reliability has not been characterized.

40

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx7x

8-BIT MICROCONTROLLER

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

new code release form

Figure 16 shows a sample of the new code release form.

NEW CODE RELEASE FORM

TEXAS INSTRUMENTS

DATE:

TMS370 MICROCONTROLLER PRODUCTS

To release a new customer algorithm to TI incorporated into a TMS370 family microcontroller, complete this form and submit with the following information:

1. A ROM description in object form on Floppy Disk, Modem XFR, or EPROM (Verification file will be returned via same media)

2. An attached specification if not using TI standard specification as incorporated in TI’s applicable device data book.

Company Name:

Street Address:

City:

Contact Mr./Ms.:

Phone: (

)

Ext.:

State

Zip

Customer Purchase Order Number:

Customer Print Number *Yes:

No:

*If Yes: Customer must provide ”print” to TI w/NCRF for approval before ROM

code processing starts.

#

Customer Part Number:

Customer Application:

(Std. spec to be followed)

TMS370 Device:

TI Customer ROM Number:

(provided by Texas Instruments)

CONTACT OPTIONS FOR THE ’A’ VERSION TMS370 MICROCONTROLLERS

OSCILLATOR FREQUENCY

Low Power Modes

[] Enabled

[] Disabled

Watchdog counter

[] Standard

[] Hard Enabled

[] Simple Counter

Clock Type

[] Standard (/4)

[] PLL (/1)

MIN

TYP

MAX

[] External Drive (CLKIN)

[] Crystal

[] Ceramic Resonator

NOTE:

Non ’A’ version ROM devices of the TMS370 microcontrollers will have the

“Low-powermodesEnabled”, “Divide-by-4”Clock, and“Standard”Watchdog

options. See the TMS370 Family User’s Guide (literature number SPNU127)

or the TMS370 Family Data Manual (literature number SPNS014B).

[] Supply Voltage MIN:

(std range: 4.5V to 5.5V)

MAX:

TEMPERATURE RANGE

PACKAGE TYPE

[] ’L’:

[] ’A’:

[] ’T’:

0° to 70°C (standard)

–40° to 85°C

–40° to 105°C

[] ’N’ 28-pin PDIP

[] “FN” 28-pin PLCC

[] “N” 40-pin PDIP

[] “FN” 44-pin PLCC

[] “FN” 68-pin PLCC

[] “NM” 64-pin PSDIP

[] “NJ” 40-pin PSDIP (formerly known as N2)

SYMBOLIZATION

BUS EXPANSION

[] TI standard symbolization

[] YES

[] NO

[] TI standard w/customer part number

[] Customer symbolization

(per attached spec, subject to approval)

NON-STANDARD SPECIFICATIONS:

ALL NON-STANDARDS SPECIFICATIONS MUST BE APPROVED BY THE TI ENGINEERING STAFF: If the customer requires expedited production material

(i.e., product which must be started in process prior to prototype approval and full production release) and non-standard spec issues are not resolved to the

satisfaction of both the customer and TI in time for a scheduled shipment, the specification parameters in question will be processed/tested to the standard

TI spec. Any such devices which are shipped without conformance to a mutually approved spec, will be identified by a ’P’ in the symbolization preceding the

TI part number.

RELEASE AUTHORIZATION:

This document, including any referenced attachments, is and will be the controlling document for all orders placed for this TI custom device. Any changes must

be in writing and mutually agreed to by both the customer and TI. The prototype cycletime commences when this document is signed off and the verification

code is approved by the customer.

1. Customer:

Date:

2. TI: Field Sales:

Marketing:

Prod. Eng.:

Proto. Release:

Figure 16. Sample New Code Release Form

41

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx7x

8-BIT MICROCONTROLLER

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

Table 19 is a collection of all the peripheral file frames using the ’Cx7x (provided for a quick reference).

Table 19. Peripheral File Frame Compilation

PF

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

System Configuration Registers

COLD

START

OSC

POWER

PF AUTO

WAIT

OSC FLT

FLAG

MC PIN

WPO

MC PIN

DATA

µP/µC

MODE

P010

P011

P012

—

SCCR0

SCCR1

SCCR2

AUTOWAIT

DISABLE

MEMORY

DISABLE

—

HALT/

STANDBY

PWRDWN/

IDLE

BUS

STEST

CPU

STEST

INT1

NMI

PRIVILEGE

DISABLE

—

P013

to

Reserved

P016

INT1

FLAG

INT1

PIN DATA

INT1

POLARITY

INT1

PRIORITY

INT1

ENABLE

P017

P018

P019

—

INT1

INT2

FLAG

INT2

PIN DATA

INT2

DATA DIR

INT2

DATA OUT

INT2

POLARITY

INT2

PRIORITY

INT2

ENABLE

INT3

FLAG

INT3

PIN DATA

INT3

DATA DIR

INT3

DATA OUT

INT3

POLARITY

INT3

PRIORITY

INT3

ENABLE

—

INT3

P01A

P01B

P01C

P01D

P01E

P01F

BUSY

—

AP

—

W1W0

W0

EXE

DEECTL

Reserved

VPPS

—

EPCTLM

EPCTLL

Reserved

—

W0

Reserved

Digital Port Control Registers

Reserved

P020

P021

P022

P023

P024

P025

P026

P027

P028

P029

P02A

P02B

P02C

P02D

P02E

P02F

APORT1

APORT2

ADATA

ADIR

Port A Control Register 2

Port A Data

Port A Direction

Reserved

BPORT1

BPORT2

BDATA

BDIR

Port B Control Register 2

Port B Data

Port B Direction

Reserved

CPORT1

CPORT2

CDATA

CDIR

Port C Control Register 2

Port C Data

Port C Direction

Port D Control Register 1

DPORT1

DPORT2

DDATA

DDIR

†

Port D Control Register 2

Port D Data

Port D Direction

P030

to

Reserved

P035

P036

P037

—

Port G Data

GDATA

GDIR

Port G Direction

†

To configure pin D3 as SYSCLK, set port D control register 2 = 08h.

42

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx7x

8-BIT MICROCONTROLLER

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

Table 19. Peripheral File Frame Compilation (Continued)

PF

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

Timer 1 Module Register

Modes: Capture/Compare and Dual-Compare

P040 Bit 15

P041 Bit 7

T1 Counter MSbyte

T1 Counter LSbyte

Bit 8 T1CNTR

Bit 0

P042

Compare Register MSbyte

Compare Register LSbyte

Capture/Compare Register MSbyte

Capture/Compare Register LSbyte

Watchdog Counter MSbyte

Watchdog Counter LSbyte

Watchdog Reset Key

Bit 8 T1C

Bit 0

Bit 15

P043 Bit 7

P044 Bit 15

P045 Bit 7

P046 Bit 15

P047 Bit 7

P048 Bit 15

Bit 8 T1CC

Bit 0

Bit 8 WDCNTR

Bit 0

Bit 0 WDRST

WD

INPUT

SELECT2

WD

INPUT

SELECT1

WD

INPUT

SELECT0

T1

INPUT

SELECT2

T1

INPUT

SELECT1

WD OVRFL

TAP SEL

T1 INPUT

SELECT0

P049

P04A

—

T1CTL1

T1CTL2

†

WD OVRFL

INT ENA

WD OVRFL

INT FLAG

T1 OVRFL

INT ENA

T1 OVRFL

INT FLAG

T1 SW

RESET

—

†

RST ENA

Mode: Dual-Compare

T1EDGE

INT FLAG

T1C2

INT FLAG

T1C1

INT FLAG

T1EDGE

INT ENA

T1C2

INT ENA

T1C1

INT ENA

P04B

P04C

—

T1CTL3

T1CTL4

T1

T1C1

OUT ENA

T1C2

OUT ENA

T1C1

RST ENA

T1CR

OUT ENA

T1EDGE

POLARITY

T1CR

RST ENA

T1EDGE

DET ENA

MODE = 0

Mode: Capture/Compare

T1EDGE

—

T1C1

INT FLAG

T1EDGE

INT ENA

T1C1

INT ENA

P04B

P04C

—

T1CTL3

T1CTL4

INT FLAG

T1

T1C1

RST ENA

T1EDGE

POLARITY

T1EDGE

DET ENA

—

MODE = 1

OUT ENA

Modes: Capture/Compare and Dual-Compare

T1EVT

DATA IN

T1EVT

DATA OUT

T1EVT

FUNCTION

T1EVT DATA

DIR

P04D

P04E

P04F

—

T1PC1

T1PC2

T1PRI

T1PWM

DATA IN

T1PWM

DATA OUT

T1PWM

FUNCTION

T1PWM

DATA DIR

T1IC/CR

DATA IN

T1IC/CR

DATA OUT

T1IC/CR

FUNCTION

T1IC/CR

DATA DIR

T1

T1 STEST

—

PRIORITY

T2A Module Register

Modes: Dual-Compare and Dual-Capture

P060 Bit 15

P061 Bit 7

P062 Bit 15

P063 Bit 7

P064 Bit 15

P065 Bit 7

P066 Bit 15

P067 Bit 7

T2A Counter MSbyte

T2A Counter LSbyte

Bit 8

T2ACNTR

T2AC

Bit 0

Bit 8

Bit 0

Bit 8

Bit 0

Bit 8

Bit 0

Compare Register MSbyte

Compare Register LSbyte

Capture/Compare Register MSbyte

Capture/Compare Register LSbyte

Capture Register 2 MSbyte

Capture Register 2 LSbyte

T2ACC

T2AIC

†

Once the WD OVRFL RST ENA bit is set, these bits cannot be changed until a reset; this applies only to the standard WD

and to simple counter. The WD input select 2 bits are ignored.

43

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx7x

8-BIT MICROCONTROLLER

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

Table 19. Peripheral File Frame Compilation (Continued)

PF

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

REG

T2A Module Register (Continued)

T2A

INPUT

SELECT1

T2A OVRFL

INT ENA

T2A OVRFL

INT FLAG

T2A INPUT

SELECT0

T2A SW

RESET

P06A

—

T2ACTL1

Mode: Dual-Compare

T2AEDGE1

INT FLAG

T2AC2

INT FLAG

T2AC1

INT FLAG

T2AEDGE1

INT ENA

T2AC2

INT ENA

T2AC1

INT ENA

P06B

P06C

—

T2ACTL2

T2ACTL3

T2A

MODE = 0

T2AC1

OUT ENA

T2AC2

OUT ENA

T2AC1

RST ENA

T2AEDGE1

OUT ENA

T2AEDGE1

POLARITY

T2AEDGE1

RST ENA

T2AEDGE1

DET ENA

Mode: Dual-Capture

T2AEDGE1

INT FLAG

T2AEDGE2

INT FLAG

T2AC1

INT FLAG

T2AEDGE1

INT ENA

T2AEDGE2

INT ENA

T2AC1

INT ENA

P06B

P06C

—

T2ACTL2

T2ACTL3

T2A

MODE = 1

T2AC1

RST ENA

T2AEDGE2

POLARITY

T2AEDGE1

POLARITY

T2AEDGE2

DET ENA

T2AEDGE1

DET ENA

—

Modes: Dual-Compare and Dual-Capture

T2AEVT

DATA IN

T2AEVT

DATA OUT

T2AEVT

FUNCTION

T2AEVT

DATA DIR

P06D

P06E

P06F

—

T2APC1

T2APC2

T2APRI

T2AIC2/PWM T2AIC2/PWM T2AIC2/PWM T2AIC2/PWM T2AIC1/CR

T2AIC1/CR

DATA OUT

T2AIC1/CR

FUNCTION

T2AIC1/CR

DATA DIR

DATA IN

DATA OUT

FUNCTION

DATA DIR

DATA IN

T2A

PRIORITY

T2A STEST

—

ADC1 Module Control Register

CONVERT

START

SAMPLE

START

REF VOLT

SELECT2

REF VOLT

SELECT1

REF VOLT

SELECT0

AD INPUT

SELECT2

AD INPUT

SELECT1

AD INPUT

SELECT0

P070

ADCTL

AD INT

FLAG

P071

P072

—

AD READY

AD INT ENA ADSTAT

ADDATA

A/D Conversion Data Register

Reserved

P073

to

P07C

P07D

P07E

Port E Data Input Register

Port E Input Enable Register

ADIN

ADENA

AD

PRIORITY

P07F

AD STEST

AD ESPEN

—

ADPRI

44

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx7x

8-BIT MICROCONTROLLER

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

‡

Supply voltage range V

, V

(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to 7 V

CC1 CC2 CC3

Input voltage range, All pins except MC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to 7 V

MC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to 14 V

Input clamp current, I (V < 0 or V > V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA

IK

I

CC1)

Output clamp current, I

(V < 0 or V > V

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA

OK

O

CC1

§

Continuous output current per buffer, I (V = 0 to V )

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA

O

CC1

Maximum I

current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 mA

CC

Maximum I current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 170 mA

SS

Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W

Operating free-air temperature range, T L version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

A:

A version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C

T version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 105°C

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

‡

§

V

= V

CC

CC1

Electrical characteristics are specified with all output buffers loaded with specified I current. Exceeding the specified I current in any buffer

O

can affect the levels on other buffers.

NOTE 1: Unless otherwise noted, all voltage values are with respect to V

.

SS1

recommended operating conditions

MIN

4.5

NOM

MAX

5.5

0.3

0.8

0.3

UNIT

Supply voltage (see Note 1)

5

V

CC1

RAM data-retention supply voltage (see Note 2)

Digital I/O supply voltage (see Note 1)

Analog supply voltage (see Note 1)

Digital I/O supply ground

3

V

CC2

V

CC3

V

SS2

V

SS3

4.5

5

0

V

4.5

– 0.3

V

Analog supply ground

All pins except MC

MC, normal operation

V

SS1

V

IL

Low-level input voltage

V

SS1

All pins except MC, XTAL2/CLKIN, and

RESET

2

V

CC

MC (non-WPO mode)

XTAL2/CLKIN

V

–0.3

V

+0.3

V

High-level input voltage

CC1

V

IH

0.8 V

0.7 V

V

CC1

RESET

V

CC1

13

EEPROM write protect override (WPO)

11.7

12

EPROM programming voltage (V

Microprocessor

Microcomputer

L version

)

13

13.2

13.5

MC (mode control) voltage

(see Note 3)

PP

V

MC

V

CC1

–0.3

+0.3

CC1

0.3

V

SS1

0

70

85

T

A

Operating free-air temperature

A version

– 40

°C

T version

105

NOTES: 1. Unless otherwise noted, all voltage values are with respect to V

.

SS1

2. RESET must be activated externally when V

or SYSCLK is out of the recommended operating range.

3. The basic microcomputer and microprocessor operating modes are selected by the voltage level applied to the dedicated MC pin

CC1

two system clock cycles (t ) before RESET goes inactive (high). The WPO mode can be selected anytime a sufficient voltage is

c

present on MC.

45

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx7x

8-BIT MICROCONTROLLER

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

= 1.4 mA

MIN

TYP

MAX

UNIT

V

Low-level output voltage

I

0.4

V

OL

OH

= –50 µA

0.9 V

CC1

High-level output voltage

Input current

V

OH

= –2 mA

2.4

0 V < V ≤ 0.3 V

10

50

I

0.3 V < V < V

–0.3 V

CC1

I

µA

MC

V

–0.3 V ≤ V ≤ V

+0.3 V

CC1

10

CC1

I

+ 0.3 V < V ≤ 13 V

650

50

CC1

I

12 V ≤ V ≤ 13 V

See Note 4

mA

µA

I

I/O pins

0 V ≤ V ≤ V

± 10

I

CC1

I

Low-level output current

High-level output current

V

OL

V

OH

V

OH

= 0.4 V

1.4

– 50

– 2

mA

µA

OL

= 0.9 V

= 2.4 V

CC1

OH

mA

SYSCLK = 5 MHz

See Notes 5 and 6

35

25

13

12

8

56

36

18

17

11

3.5

8.6

3

Supply current (operating mode)

OSC POWER bit = 0 (see Note 7)

SYSCLK = 3 MHz

See Notes 5 and 6

mA

SYSCLK = 0.5 MHz

See Notes 5 and 6

SYSCLK = 5 MHz

See Notes 5 and 6

Supply current (STANDBY mode)

OSC POWER bit = 0 (see Note 8)

SYSCLK = 3 MHz

See Notes 5 and 6

I

CC

SYSCLK = 0.5 MHz

See Notes 5 and 6

2.5

6

SYSCLK = 3 MHz

See Notes 5 and 6

Supply current (STANDBY mode)

OSC POWER bit = 1 (see Note 9)

mA

SYSCLK = 0.5 MHz

See Notes 5 and 6

2

XTAL2/CLKIN < 0.2 V

See Note 5

Supply current (HALT mode)

2

30

µA

NOTES: 4. Input current I

is a maximum of 50 mA only when programming EPROM.

PP

5. In single chip mode, ports are configured as inputs or outputs with no load. All inputs ≤ 0.2 V or ≥ V

– 0.2V.

CC1

6. XTAL2/CLKIN is driven with an external square wave signal with 50% duty cycle and rise and fall times less than 10 ns. Current

can be higher with a crystal oscillator. At 5 MHz SYSCLK, this extra current = 0.01 mA x (total load capacitance + crystal capacitance

in pF).

7. Maximum operating current for TMS370Cx7x = 10 (SYSCLK) + 5.8 mA.

8. Maximum standby current for TMS370Cx7x = 3 (SYSCLK) + 2 mA. (OSC POWER bit = 0).

9. Maximum standby current for TMS370Cx7x = 2.24 (SYSCLK) + 1.9 mA. (OSC POWER bit =1, only valid up to 3 MHz SYSCLK).

46

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx7x

8-BIT MICROCONTROLLER

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

PARAMETER MEASUREMENT INFORMATION

XTAL2/CLKIN

XTAL1

XTAL2/CLKIN

XTAL1

C3

(see Note B)

C1

(see Note B)

C2

Crystal/Ceramic

Resonator

(see Note A)

External

Clock Signal

(see Note B)

NOTES: A. The crystal/ceramic resonator frequency is four times the reciprocal of the system clock period.

B. The values of C1 and C2 are typically 15 pF and C3 is typically 50 pF. See the manufacturer’s recommendations for ceramic

resonators.

Figure 17. Recommended Crystal/Clock Connections

Load Voltage

1.2 kΩ

V

O

20 pF

Case 1: V = V

= 2.4 V; Load Voltage = 0 V

= 0.4 V; Load Voltage = 2.1 V

O

OH

OL

Case 2: V = V

O

NOTE A: All measurements are made with the pin loading as shown unless otherwise noted. All measurements are made with XTAL2/CLKIN

driven by an external square wave signal with a 50% duty cycle and rise and fall times less than 10 ns unless otherwise stated.

Figure 18. Typical Output Load Circuit (see Note A)

V

CC2

V

CC2

Pin Data

300 Ω

30 Ω

6 kΩ

Output

Enable

I/O

INT1

20 Ω

GND

Figure 19. Typlcal Buffer Circuitry

47

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx7x

8-BIT MICROCONTROLLER

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

PARAMETER MEASUREMENT INFORMATION

timing parameter symbology

Timing parameter symbols have been created in accordance with JEDEC Standard 100. In order to shorten the

symbols, some of the pin names and other related terminology have been abbreviated as follows:

A

Address

Array

PGM

R

Program

Read

AR

B

Byte

SC

W

SYSCLK

Write

CI

D

XTAL2/CLKIN

Data

Lowercase subscripts and their meanings are:

c

d

f

cycle time (period)

delay time

fall time

r

su

v

rise time

setup time

valid time

h

hold time

w

pulse duration (width)

The following additional letters are used with these meanings:

H

L

High

Low

V

Z

Valid

High impedance

All timings are measured between high and low measurement points as indicated in Figure 20 and Figure 21.

0.8 V

V (High)

2 V (High)

CC

0.8 V (Low)

Figure 20. XTAL2/CLKIN Measurement Points

Figure 21. General Measurement Points

48

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx7x

8-BIT MICROCONTROLLER

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

†

external clocking requirements for clock divided by 4 (see Figure 22)

NO.

1

PARAMETER

Pulse duration, XTAL2/CLKIN (see Note 10)

Rise time, XTAL2/CLKIN

MIN

MAX

UNIT

ns

t

20

w(Cl)

2

30

100

20

5

ns

r(Cl)

3

Fall time, XTAL2/CLKIN

ns

f(CI)

4

Delay time, XTAL2/CLKIN rise to SYSCLK fall

Crystal operating frequency

ns

d(CIH-SCL)

CLKIN

2

MHz

‡

SYSCLK

System clock

0.5

†

‡

For V and V , refer to recommended operating conditions.

IL IH

SYSCLK = CLKIN/4

NOTE 10: This pulse can be either a high pulse, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle, or a

low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle.

1

XTAL2/CLKIN

2

3

4

SYSCLK

Figure 22. External Clock Timing for Divide-by-4

†

external clocking requirements for clock divided by 1 (PLL) (see Figure 23)

NO.

1

PARAMETER

Pulse duration, XTAL2/CLKIN (see Note 10)

Rise time, XTAL2/CLKIN

MIN

MAX

UNIT

ns

t

20

w(Cl)

2

30

100

5

ns

r(Cl)

3

Fall time, XTAL2/CLKIN

ns

f(CI)

4

Delay time, XTAL2/CLKIN rise to SYSCLK rise

Crystal operating frequency

ns

d(CIH-SCH)

CLKIN

2

MHz

§

SYSCLK

System clock

5

†

§

For V and V , refer to recommended operating conditions.

IL IH

SYSCLK = CLKIN/1

NOTE 10: This pulse can be either a high pulse, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle, or a

low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle.

1

XTAL2/CLKIN

2

3

4

SYSCLK

Figure 23. External Clock Timing for Divide-by-1

49

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx7x

8-BIT MICROCONTROLLER

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

general-purpose output signal switching time requirements (see Figure 24)

MIN NOM

MAX

UNIT

ns

t

Rise time

Fall time

30

r

ns

f

t

r

t

f

Figure 24. Signal Switching Timing

recommended EEPROM timing requirements for programming

MIN

10

MAX

UNIT

ms

t

Pulse duration, programming signal to ensure valid data is stored (byte mode)

Pulse duration, programming signal to ensure valid data is stored (array mode)

w(PGM)B

20

ms

w(PGM)AR

recommended EPROM operating conditions for programming

MIN NOM

MAX

6

UNIT

V

Supply voltage

4.75

13

5.5

13.2

30

CC1

Supply voltage at MC pin

13.5

50

5

V

PP

I

Supply current at MC pin during programming (V

= 13 V)

mA

PP

Divide-by-4

Divide-by-1

0.5

2

SYSCLK

System clock

MHz

5

recommended EPROM timing requirements for programming

MIN NOM

0.40 0.50

MAX

UNIT

t

Pulse duration, programming signal (see Note 11)

3

ms

w(EPGM)

NOTE 11: Programming pulse is active when both EXE (EPCTL.0) and V

(EPCTL.6) are set.

PPS

50

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx7x

8-BIT MICROCONTROLLER

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

†

switching characteristics and timing requirements (see Figure 25)

NO.

PARAMETER

MIN

200

MAX

2000

500

UNIT

Divide-by-4 clock

Divide-by-1-(PLL)

5

t

c

Cycle time, SYSCLK (system clock)

ns

6

7

t

Pulse duration, SYSCLK low

Pulse duration, SYSCLK high

0.5t –20

0.5t

c

ns

w(SCL)

c

0.5t

0.5t +20

c

w(SCH)

c

†

t = system-clock cycle time = 1/SYSCLK

c

7

5

6

SYSCLK

Figure 25. SYSCLK Timing

51

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx7x

8-BIT MICROCONTROLLER

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

analog-to-digital converter 1 (ADC1)

The ADC1 has a separate power bus for its analog circuitry. These pins are referred to as V

and V

. The

CC3

SS3

purpose is to enhance ADC1 performance by preventing digital switching noise in the logic circuitry that can

be present on V and V when coupling into the A/D analog stage. All ADC1 specifications are given with

SS1

SS3

CC1

respect to V

unless otherwise noted.

Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-bits (256 values)

Monotonic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Yes

Output conversion mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 00h to FFh (00 for V ≤ V

Conversion time (excluding sample time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 t

≤; FF for V ≤ V

)

I

SS3

I

ref

c

recommended operating conditions

MIN

NOM

MAX

UNIT

4.5

5

5.5

V

Analog supply voltage

Analog ground

V

CC3

V

–0.3

CC1

V

+0.3

CC1

V

–0.3

SS1

V

+0.3

SS1

V

SS3

†

V

ref

Non-V

CC3

reference

2.5

V

+ 0.1

CC3

Analog input for conversion

V

ref

SS3

†

V

ref

must be stable, within ± 1/2 LSB of the required resolution, during the entire conversion time.

operating characteristics over recommended ranges of operating conditions

PARAMETER

TEST CONDITIONS

MIN

MAX

±1.5

±0.9

2

UNIT

LSB

mA

µA

‡

Absolute accuracy

V

= 5.5 V

V

rerf

= 5.1 V

CC3

‡§

Differential/integral linearity error

V

rerf

CC3

Converting

I

Analog supply current

CC3

Nonconverting

5

I

Input current, AN0–AN7

Input charge current

0 V ≤ V ≤ 5.5 V

2

µA

I

1

mA

kΩ

ref

SYSCLK ≤ 3 MHz

24

10

Z

Source impedance of V

ref

3 MHz < SYSCLK ≤ 5 MHz

kΩ

‡

§

Absolute resolution = 20 mV. At V = 5 V, this is one LSB. As V decreases, LSB size decreases; therefore, the absolute accuracy and

differential/integral linearity errors in terms of LSBs increase.

Excluding quantization error of 1/2 LSB

ref

52

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx7x

8-BIT MICROCONTROLLER

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

analog-to-digital converter 1 (ADC1) (continued)

The ADC1 module allows complete freedom in design of the sources that supply the analog inputs. The period

of the sample time is user-defined so that the high impedance can be accommodated without penalty to the

low-impedance sources. The sample period begins when the SAMPLE START bit of the ADC1 control register

(ADCTL.6) is set to 1. The end of the signal sample period occurs when the conversion bit (CONVERT START,

ADCTL.7) is set to 1. After a hold time, the converter resets the SAMPLE START and CONVERT START bits,

signaling that a conversion has started and that the analog signal can be removed.

analog timing requirements (see Figure 26)

MIN

MAX

UNIT

ns

t

Setup time, analog to sample command

0

su(S)

h(AN)

w(S)

Hold time, analog input from start of conversion

Pulse duration, sample time per kilohm of source impedance

18t

ns

c

†

1

µs/kΩ

†

The value given is valid for a signal with a source impedance > 1 kΩ. If the source impedance is < 1 kΩ, use a minimum sampling time of 1µs.

Analog Stable

Analog In

t

su(S)

Sample Start

Convert Start

t

h(AN)

t

w(S)

Figure 26. Analog Timing

53

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx7x

8-BIT MICROCONTROLLER

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

Table 20 is designed to aid the user in referencing a device part number to a mechanical drawing. The table

shows a cross-reference of the device part number to the TMS370 generic package name and the associated

mechanical drawing by drawing number and name.

Table 20. TMS370Cx7x Family Package Type and Mechanical Cross-Reference

PKG TYPE

(mil pin spacing)

PKG TYPE NO. AND

MECHANICAL NAME

TMS370 GENERIC NAME

DEVICE PART NUMBERS

TMS370C077AFNA

TMS370C077AFNL

TMS370C077AFNT

TMS370C777AFNT

FN – 68 pin

(50-mil pin spacing)

PLASTIC LEADED CHIP CARRIER

(PLCC)

FN(S-PQCC-J**) PLASTIC J-LEADED

CHIP CARRIER

FZ – 68 pin

(50-mil pin spacing)

CERAMIC LEADED CHIP CARRIER

(CLCC)

FZ(S-CQCC-J**) J-LEADED CERAMIC

CHIP CARRIER

SE370C777AFZT

SE370C777AJNT

JN – 64 pin

(70-mil pin spacing)

CERAMIC SHRINK DUAL-IN-LINE

PACKAGE (CSDIP)

JN(R-CDIP-T64) CERAMIC DUAL-IN-LINE

PACKAGE

TMS370C077ANMA

TMS370C077ANML

TMS370C077ANMT

TMS370C777ANMT

NM – 64 pin

(70-mil pin spacing)

PLASTIC SHRINK DUAL-IN-LINE

PACKAGE (PSDIP)

NM(R-PDIP-T64) PLASTIC SHRINK

DUAL-IN-LINE PACKAGE

54

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx7x

8-BIT MICROCONTROLLER

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

MECHANICAL DATA

FN (S-PQCC-J**)

PLASTIC J-LEADED CHIP CARRIER

20 PIN SHOWN

Seating Plane

0.004 (0,10)

0.180 (4,57) MAX

0.120 (3,05)

D

0.090 (2,29)

D1

0.020 (0,51) MIN

3

1

19

0.032 (0,81)

0.026 (0,66)

4

18

D2/E2

E

E1

8

14

0.021 (0,53)

0.013 (0,33)

0.007 (0,18)

0.050 (1,27)

9

13

M

0.008 (0,20) NOM

D/E

D1/E1

D2/E2

NO. OF

PINS

**

MIN

0.385 (9,78)

MAX

MIN

MAX

MIN

MAX

0.395 (10,03)

0.350 (8,89)

0.356 (9,04)

0.141 (3,58)

0.191 (4,85)

0.291 (7,39)

0.341 (8,66)

0.169 (4,29)

0.219 (5,56)

0.319 (8,10)

0.369 (9,37)

20

28

44

52

68

84

0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58)

0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66)

0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20)

0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91)

1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45)

4040005/B 03/95

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-018

55

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx7x

8-BIT MICROCONTROLLER

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

MECHANICAL DATA

FZ (S-CQCC-J**)

J-LEADED CERAMIC CHIP CARRIER

28 LEAD SHOWN

0.040 (1,02)

45°

Seating Plane

0.180 (4,57)

0.155 (3,94)

0.140 (3,55)

A

B

1

0.120 (3,05)

26

4

25

5

0.050 (1,27)

C

(at Seating

Plane)

A

B

0.032 (0,81)

0.026 (0,66)

0.020 (0,51)

0.014 (0,36)

19

11

18

12

0.025 (0,64) R TYP

0.040 (1,02) MIN

0.120 (3,05)

0.090 (2,29)

A

B

C

JEDEC

NO. OF

PINS**

OUTLINE

MIN

MAX

MIN

MAX

MIN

MAX

0.485

0.495

0.430

0.455

0.410

0.430

MO-087AA

MO-087AB

MO-087AC

MO-087AD

28

44

52

68

(12,32)

(12,57)

(10,92)

(11,56)

(10,41)

(10,92)

0.685

0.695

0.630

0.655

0.610

0.630

(17,40)

(17,65)

(16,00)

(16,64)

(15,49)

(16,00)

0.785

0.795

0.730

0.765

0.680

0.740

(19,94)

(20,19)

(18,54)

(19,43)

(17,28)

(18,79)

0.985

0.995

0.930

0.955

0.910

0.930

(25,02)

(25,27)

(23,62)

(24,26)

(23,11)

(23,62)

4040219/B 03/95

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a ceramic lid using glass frit.

56

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx7x

8-BIT MICROCONTROLLER

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

MECHANICAL DATA

JN (R-CDIP-T64)

CERAMIC DUAL-IN-LINE PACKAGE

2.424 (61,57)

2.376 (60,35)

64

33

0.750 (19,05)

0.730 (18,54)

1

32

0.040 (1,02) TYP

0.094 (2,39)

0.078 (1,98)

0.760 (19,30)

0.740 (18,80)

0.060 (1,52)

0.040 (1,02)

Seating Plane

0.088 (2,24)

0.072 (1,83)

0.175 (4,45) TYP

0.020 (0,51)

0.016 (0,41)

0.012 (0,31)

0.009 (0,23)

0.070 (1,78)

See Note C

2.178 (55,32)

2.162 (54,91)

4040224/A 09/95

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Each pin centerline located within 0.010 (0,26) of it true longitudinal position.

57

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS370Cx7x

8-BIT MICROCONTROLLER

SPNS034C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

MECHANICAL DATA

NM (R-PDIP-T64)

PLASTIC SHRINK DUAL-IN-LINE PACKAGE

2.280 (57,91) MAX

64

33

0.680 (17,27)

0.670 (17,02)

1

32

0.048 (1,216)

0.032 (0,816)

0.222 (5,64) MAX

0.760 (19,30)

0.740 (18,80)

0.020 (0,51) MIN

Seating Plane

0°–15°

0.010 (0,25) NOM

4040056/B 05/95

0.070 (1,78)

0.010 (0,25)

0.125 (3,18) MIN

0.022 (0,56)

0.014 (0,36)

M

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

58

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF

DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL

APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR

WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER

CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO

BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

semiconductor products or services might be or are used. TI’s publication of information regarding any third

party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.


型号：	SE370C777AFZT
厂家：	TEXAS INSTRUMENTS
描述：	8-BIT MICROCONTROLLER
文件：	总59页 (文件大小：865K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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