SE555C [TI]
PRECISION TIMERS; 精密定时器
| 型号： | SE555C |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | PRECISION TIMERS |
| 文件： | 总15页 (文件大小：254K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NE555, NE555Y, SA555, SE555, SE555C
PRECISION TIMERS
SLFS022 – SEPTEMBER 1973 – REVISED FEBRUARY 1992
Timing From Microseconds to Hours
Astable or Monostable Operation
Adjustable Duty Cycle
D, JG, OR P PACKAGE
(TOP VIEW)
GND
TRIG
OUT
V
CC
1
2
3
4
8
7
6
5
TTL-Compatible Output Can Sink or
Source up to 200 mA
DISCH
THRES
CONT
RESET
Functionally Interchangeable With the
Signetics NE555, SA555, SE555, SE555C;
Have Same Pinout
FK PACKAGE
(TOP VIEW)
SE555C FROM TI IS NOT RECOMMENDED
FOR NEW DESIGNS
3
2
1
20 19
18
description
NC
NC
4
5
6
7
8
DISCH
NC
TRIG
NC
17
16
15
14
These devices are precision monolithic timing
circuitscapableofproducingaccuratetimedelays
or oscillation. In the time-delay or monostable
mode of operation, the timed interval is controlled
by a single external resistor and capacitor
network. In the astable mode of operation, the
frequency and duty cycle may be independently
controlled with two external resistors and a single
external capacitor.
THRES
NC
OUT
NC
9 10 11 12 13
NC–No internal connection
The threshold and trigger levels are normally two-thirds and one-third, respectively, of V . These levels can
CC
be altered by use of the control voltage terminal. When the trigger input falls below the trigger level, the flip-flop
is set and the output goes high. If the trigger input is above the trigger level and the threshold input is above
the threshold level, the flip-flop is reset and the output is low. RESET can override all other inputs and can be
used to initiate a new timing cycle. When RESET goes low, the flip-flop is reset and the output goes low.
Whenever the output is low, a low-impedance path is provided between DISCH and ground.
The output circuit is capable of sinking or sourcing current up to 200 mA. Operation is specified for supplies of
5 V to 15 V. With a 5-V supply, output levels are compatible with TTL inputs.
The NE555 is characterized for operation from 0°C to 70°C. The SA555 is characterized for operation from
–40°C to 85°C. The SE555 and SE555C are characterized for operation over the full military range of –55°C
to 125°C.
AVAILABLE OPTIONS
PACKAGE
CHIP FORM
T
V
V
max
SMALL OUTLINE
(D)
CHIP CARRIER
(FK)
CERAMIC DIP
(J)
PLASTIC DIP
(P)
A
THRES
= 15 V
(Y)
CC
11.2 V
0°C to 70°C
NE555D
SA555D
NE555P
SA555P
–40°C to 85°C
11.2 V
NE555Y
10.6 V
11.2 V
SE555D
SE555CD
SE555FK
SE555CFK
SE555JG
SE555CJG
SE555P
SE555CP
–55°C to 125°C
The D package is available taped and reeled. Add the suffix R to the device type (e.g., NE555DR).
Copyright 1992, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
NE555, NE555Y, SA555, SE555, SE555C
PRECISION TIMERS
SLFS022 – SEPTEMBER 1973 – REVISED FEBRUARY 1992
FUNCTION TABLE
†
†
RESET
Low
TRIGGER VOLTAGE
THRESHOLD VOLTAGE
Irrelevant
OUTPUT
Low
DISCHARGE SWITCH
Irrelevant
On
Off
On
High
< 1/3 V
> 1/3 V
> 1/3 V
Irrelevant
High
DD
DD
DD
High
> 2/3 V
Low
DD
DD
High
< 2/3 V
As previously established
†
Voltage levels shown are nominal.
functional block diagram
V
8
RESET
4
CC
CONT
5
R
R1
R
6
THRES
3
1
OUT
S
R
R
2
1
TRIG
7
DISCH
GND
RESET can override TRIG, which can override THRES.
Pin numbers shown are for the D, JG, and P packages only.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
NE555, NE555Y, SA555, SE555, SE555C
PRECISION TIMERS
SLFS022 – SEPTEMBER 1973 – REVISED FEBRUARY 1992
chip information
These chips, properly assembled, display characteristics similar to the NE555 (see electrical table for NE555Y).
Thermal compression or ultrasonic bonding may be used on the doped aluminum bonding pads. Chips may be
mounted with conductive epoxy or a gold-silicon preform.
CONT
(5)
RESET
(4)
BONDING PAD ASSIGNMENTS
V
CC
(8)
R
R
(6)
R1
R
THRES
TRIG
(3)
(2)
1
OUT
(3)
S
(4)
(2)
R
(7)
DISCH
41
(1)
GND
(1)
(5)
(6)
(8)
CHIP THICKNESS: 15 TYPICAL
BONDING PADS: 4 × 4 MINIMUM
T
J
max = 150° C
(7)
TOLERANCES ARE ± 10%
ALL DIMENSIONS ARE IN MILS
42
PIN (1) INTERNALLY CONNECTED
TO BACKSIDE OF CHIP
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
NE555, NE555Y, SA555, SE555, SE555C
PRECISION TIMERS
SLFS022 – SEPTEMBER 1973 – REVISED FEBRUARY 1992
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
(See Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
CC
Input voltage (CONT, RESET, THRES, and TRIG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
CC
Output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±225 mA
Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range: NE555 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
SA555 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
SE555, SE555C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or P package . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG package . . . . . . . . . . . . . . . . . . . . 300°C
NOTE 1: All voltage values are with respect to network ground terminal.
DISSIPATION RATING TABLE
T
≤ 25°C
DERATING FACTOR
T
= 70°C
T
= 85°C
T = 125°C
A
POWER RATING
A
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING
POWER RATING
A
D
725 mW
5.8 mW/°C
11.0 mW/°C
8.4 mW/°C
6.6 mW/°C
8.0 mW/°C
464 mW
377 mW
N/A
FK
1375 mW
1050 mW
825 mW
880 mW
715 mW
275 mW
210 mW
N/A
JG (SE555, SE555C)
JG (SA555, NE555C)
P
672 mW
546 mW
528 mW
429 mW
1000 mW
640 mW
520 mW
N/A
recommended operating conditions
NE555
SA555
SE555
SE555C
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Supply voltage, V
CC
4.5
16
4.5
16
4.5
18
4.5
16
V
V
Input voltage (CONT, RESET, THRES, and TRIG)
Output current
V
V
V
V
CC
CC
CC
CC
±200
±200
±200
±200
mA
°C
Operating free-air temperature, T
0
70
–40
85
–55
125
–55
125
A
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
NE555, NE555Y, SA555, SE555, SE555C
PRECISION TIMERS
SLFS022 – SEPTEMBER 1973 – REVISED FEBRUARY 1992
electrical characteristics, V
= 5 V to 15 V, T = 25°C (unless otherwise noted)
CC
A
NE555, SA555,
SE555C
SE555
PARAMETER
TEST CONDITIONS
UNIT
MIN
9.4
TYP
10
MAX
10.6
4
MIN
TYP
10
MAX
V
V
= 15 V
8.8
2.4
11.2
4.2
250
5.6
2.2
2
CC
THRES voltage level
THRES current (see Note 2)
TRIG voltage level
V
nA
V
= 5 V
2.7
3.3
30
3.3
30
CC
250
5.2
1.9
0.9
1
V
V
= 15 V
= 5 V
4.8
5
4.5
1.1
5
CC
1.45
1.67
0.5
0.7
0.1
–0.4
20
1.67
0.5
0.7
0.1
–0.4
20
CC
TRIG current
TRIG at 0 V
µA
RESET voltage level
0.3
0.3
1
V
RESET at V
0.4
–1
0.4
–1.5
100
11
CC
RESET current
mA
nA
V
RESET at 0 V
DISCH switch off-state current
CONT voltage (open circuit)
100
10.4
3.8
0.15
0.5
2.2
V
V
= 15 V
= 5 V
9.6
2.9
10
9
10
CC
3.3
0.1
0.4
2
2.6
3.3
0.1
0.4
2
4
CC
I
I
I
I
I
I
I
I
I
= 10 mA
0.25
0.75
2.5
OL
OL
OL
OL
OL
OL
OH
OH
OH
= 50 mA
V
= 15 V
= 5 V
CC
CC
= 100 mA
= 200 mA
= 5 mA
Low-level output voltage
V
2.5
0.1
0.15
13.3
12.5
3.3
10
2.5
0.1
0.15
13.3
12.5
3.3
10
0.2
0.35
0.4
V
= 8 mA
0.25
= –100 mA
= –200 mA
= –100 mA
13
3
12.75
2.75
V
V
= 15 V
= 5 V
CC
High-level output voltage
Supply current
V
CC
V
V
V
V
= 15 V
= 5 V
12
5
15
6
CC
CC
CC
CC
Output low,
No load
3
3
mA
= 15 V
= 5 V
9
10
4
9
13
5
Output high, No load
2
2
NOTE 2: This parameter influences the maximum value of the timing resistors R and R in the circuit of Figure 12. For example, when
A
B
V
CC
= 5 V, the maximum value is R = R + R ≈ 3.4 MΩ, and for V
= 15 V, the maximum value is 10 MΩ.
A
B
CC
operating characteristics, V
= 5 V and 15 V
CC
NE555, SA555,
SE555
TYP
TEST
CONDITIONS
SE555C
TYP
1%
PARAMETER
UNIT
†
MIN
MAX
MIN
MAX
Each timer, monostable§
Each timer, astable¶
0.5% 1.5%
1.5%
3%
Initial error of timing interval‡
T
= 25°C
A
2.25%
50
Each timer, monostable§
Each timer, astable¶
30
90
100
Temperature coefficient
of timing interval
T
= MIN to MAX
ppm/°C
%/V
A
150
Each timer, monostable§
Each timer, astable¶
0.05
0.15
100
100
0.2
0.1
0.5
Supply voltage sensitivity
of timing interval
T
= 25°C
A
0.3
Output pulse rise time
Output pulse fall time
200
200
100
300
300
C
T
= 15 pF,
= 25°C
L
ns
100
A
†
‡
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
Timing interval error is defined as the difference between the measured value and the average value of a random sample from each process
run.
§
¶
Values specified are for a device in a monostable circuit similar to Figure 9, with component values as follow: R = 2 kΩ to 100 kΩ, C = 0.1 µF.
A
Values specified are for a device in an astable circuit similar to Figure 12, with component values as follow: R = 1 kΩ to 100 kΩ, C = 0.1 µF.
A
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
NE555, NE555Y, SA555, SE555, SE555C
PRECISION TIMERS
SLFS022 – SEPTEMBER 1973 – REVISED FEBRUARY 1992
electrical characteristics, V
= 5 V to 15 V, T = 25°C (unless otherwise noted)
A
CC
PARAMETER
TEST CONDITIONS
= 15 V
MIN
8.8
TYP
10
MAX
11.2
4.2
250
5.6
2.2
2
UNIT
V
V
V
CC
THRES voltage level
THRES current (see Note 2)
TRIG voltage level
= 5 V
2.4
3.3
30
CC
nA
V
V
V
= 15 V
= 5 V
4.5
1.1
5
CC
1.67
0.5
0.7
0.1
–0.4
20
CC
TRIG current
TRIG at 0 V
µA
RESET voltage level
0.3
1
V
RESET at V
0.4
–1.5
100
11
CC
RESET current
mA
nA
V
RESET at 0 V
DISCH switch off-state current
CONT voltage (open circuit)
V
V
= 15 V
= 5 V
9
10
CC
2.6
3.3
0.1
0.4
2
4
CC
I
I
I
I
I
I
I
I
I
= 10 mA
= 50 mA
= 100 mA
= 200 mA
= 5 mA
0.25
0.75
2.5
OL
OL
OL
OL
OL
OL
OH
OH
OH
V
= 15 V
= 5 V
CC
CC
Low-level output voltage
V
2.5
0.1
0.15
13.3
12.5
3.3
10
0.35
0.4
V
= 8 mA
= –100 mA 12.75
= –200 mA
V
V
= 15 V
= 5 V
CC
High-level output voltage
Supply current
V
= –100 mA
= 15 V
= 5 V
2.75
CC
V
V
V
V
15
6
CC
CC
CC
CC
Output low, No load
Output high, No load
3
mA
= 15 V
= 5 V
9
13
5
2
NOTE 2: This parameter influences the maximum value of the timing resistors R and R in the circuit of Figure 12. For example, when
A
B
V
CC
= 5 V, the maximum value is R = R + R ≈ 3.4 MΩ, and for V
= 15 V, the maximum value is 10 MΩ
A
B
CC
operating characteristics, V
= 5 V and 15 V, T = 25°C (unless otherwise noted)
CC
A
TEST
CONDITIONS
PARAMETER
MIN
TYP
MAX
UNIT
‡
‡
Each timer, monostable
1%
2.25%
0.1
3%
†
Initial error of timing interval
§
Each timer, astable
Each timer, monostable
0.5
Supply voltage sensitivity of timing interval
%/V
ns
§
Each timer, astable
0.3
Output pulse rise time
Output pulse fall time
100
300
300
C
= 15 pF
L
100
†
Timing interval error is defined as the difference between the measured value and the average value of a random sample from each process
run.
‡
§
Values specified are for a device in a monostable circuit similar to Figure 9, with component values as follow: R = 2 kΩ to 100 kΩ, C = 0.1 µF.
A
Values specified are for a device in an astable circuit similar to Figure 12, with component values as follow: R = 1 kΩ to 100 kΩ, C = 0.1 µF.
A
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
NE555, NE555Y, SA555, SE555, SE555C
PRECISION TIMERS
SLFS022 – SEPTEMBER 1973 – REVISED FEBRUARY 1992
†
TYPICAL CHARACTERISTICS
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
10
7
10
7
V
CC
= 10 V
V
CC
= 5 V
4
2
4
2
T
A
= – 55°C
T
A
= 25°C
1
0.7
1
0.7
T = – 55°C
A
T
A
= 25°C
0.4
0.2
0.4
0.2
T
A
= 125°C
T
A
= 125°C
0.1
0.1
0.07
0.07
0.04
0.04
0.02
0.01
0.02
0.01
1
2
4
7
10
20
40
70 100
1
2
4
7
10
20
40
70 100
I
– Low-Level Output Current – mA
I
– Low-Level Output Current – mA
OL
OL
Figure 1
Figure 2
DROP BETWEEN SUPPLY VOLTAGE AND OUTPUT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT CURRENT
2.0
10
7
T
= – 55°C
A
V
CC
= 15 V
1.8
1.6
4
2
T
A
= – 55°C
T
A
= 25°C
1.4
1.2
1
1
0.7
T
= 125°C
A
0.4
0.2
T
= 25°C
A
0.8
0.6
0.4
T
= 125°C
A
0.1
0.07
0.04
0.02
0.01
0.2
0
V
= 5 V to 15 V
CC
1
2
I
4
7
10
20
40
70 100
1
2
4
7
10
20
40
70 100
– High-Level Output Current – mA
I
– Low-Level Output Current – mA
OH
OL
Figure 3
Figure 4
†
Data for temperatures below 0°C and above 70°C are applicable for SE555 circuits only.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
NE555, NE555Y, SA555, SE555, SE555C
PRECISION TIMERS
SLFS022 – SEPTEMBER 1973 – REVISED FEBRUARY 1992
†
TYPICAL CHARACTERISTICS
NORMALIZED OUTPUT PULSE DURATION
(MONOSTABLE OPERATION)
vs
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
10
1.015
1.010
1.005
1
Output Low,
No Load
9
8
T
A
= 25°C
7
6
5
4
3
T
= –55°C
A
T
A
= 125°C
0.995
0.990
0.985
2
1
0
5
6
7
8
9
10 11 12 13 14 15
0
5
10
15
20
V
CC
– Supply Voltage – V
V
CC
– Supply Voltage – V
Figure 5
Figure 6
NORMALIZED OUTPUT PULSE DURATION
(MONOSTABLE OPERATION)
vs
PROPAGATION DELAY TIME
vs
LOWEST VOLTAGE LEVEL
OF TRIGGER PULSE
FREE-AIR TEMPERATURE
1.015
1.010
1.005
1
300
250
200
150
100
50
V
CC
= 10 V
T
= –55°C
A
T
A
= 0°C
0.995
0.990
0.985
T
= 25°C
A
T
A
= 70°C
T
A
= 125°C
0
–75 –50 –25
0
25
50
75
100 125
0
0.1 x V
0.2 x V
CC
0.3 x V
CC
0.4 x V
CC
CC
T
A
– Free-Air Temperature – °C
Lowest Voltage Level of Trigger Pulse
Figure 7
Figure 8
†
8
Data for temperatures below 0°C and above 70°C are applicable for SE555 circuits only.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
NE555, NE555Y, SA555, SE555, SE555C
PRECISION TIMERS
SLFS022 – SEPTEMBER 1973 – REVISED FEBRUARY 1992
APPLICATION INFORMATION
monostable operation
For monostable operation, any of these timers may be connected as shown in Figure 9. If the output is low,
application of a negative-going pulse to TRIG sets the flip-flop (Q goes low), drives the output high, and turns
off Q1. Capacitor C is then charged through R until the voltage across the capacitor reaches the threshold
A
voltage of THRES input. If TRIG has returned to a high level, the output of the threshold comparator will reset
the flip-flop (Q goes high), drive the output low, and discharge C through Q1.
R
C
R
= 9.1 kΩ
= 0.01 µF
= 1 kΩ
A
L
L
V
See Figure 9
CC
(5 V to 15 V)
Input Voltage
5
8
R
A
CONT
V
CC
4
7
RESET
R
L
DISCH
3
OUT
Output
Output Voltage
6
2
THRES
TRIG
Input
GND
1
Capacitor Voltage
Time – 0.1 ms/div
Pin numbers shown are for the D, JG, and P packages.
Figure 9. Circuit for Monostable Operation
Figure 10. Typical Monostable Waveforms
10
Monostable operation is initiated when TRIG
voltage falls below the trigger threshold. Once
initiated, the sequence ends only if TRIG is high
at the end of the timing interval. Because of the
threshold level and saturation voltage of Q1,
the output pulse duration is approximately
R
A
= 10 MΩ
A
1
R
= 1 MΩ
–1
10
t
= 1.1R C. Figure 11 is a plot of the time
w
A
constant for various values of R and C. The
A
threshold levels and charge rates are both directly
–2
10
proportionaltothesupplyvoltage,V
Thetiming
CC.
interval is therefore independent of the supply
voltage, so long as the supply voltage is constant
during the time interval.
–3
–4
–5
10
10
10
R
= 100 kΩ
A
R
= 10 kΩ
A
Applying a negative-going trigger pulse simulta-
neously to RESET and TRIG during the timing
interval discharges C and re-initiates the cycle,
commencing on the positive edge of the reset
pulse. The output is held low as long as the reset
pulse is low. To prevent false triggering, when
R
= 1 kΩ
A
0.001
0.01
0.1
1
10
100
C – Capacitance – µF
RESETisnotused,itshouldbeconnectedtoV
.
CC
Figure 11. Output Pulse Duration vs Capacitance
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
NE555, NE555Y, SA555, SE555, SE555C
PRECISION TIMERS
SLFS022 – SEPTEMBER 1973 – REVISED FEBRUARY 1992
APPLICATION INFORMATION
astable operation
As shown in Figure 12, adding a second resistor, R to the circuit of Figure 9 and connecting the trigger input
B,
to the threshold input causes the timer to self-trigger and run as a multivibrator. The capacitor C will charge
through R and R and then discharge through R only. The duty cycle may be controlled, therefore, by the
A
B
B
values of R and R
A
B.
This astable connection results in capacitor C charging and discharging between the threshold-voltage level
(≈0.67•V ) and the trigger-voltage level (≈0.33•V ). As in the monostable circuit, charge and discharge
CC
CC
times (and therefore the frequency and duty cycle) are independent of the supply voltage.
V
CC
(5 V to 15 V)
R
R
= 5 kΩ
= 3 kΩ
R = 1 kΩ
L
See Figure 12
A
B
C = 0.15 µF
0.01 µF
Open
(see Note A)
5
8
R
A
B
CONT
V
CC
4
7
R
L
RESET
DISCH
3
OUT
Output
6
2
R
C
THRES
TRIG
t
H
Output Voltage
t
L
GND
1
Pin numbrs shown are for the D, JG, and P packages.
NOTE A: Decoupling CONT voltage to ground with
Capacitor Voltage
Time – 0.5 ms/div
a
capacitor may improve operation. This should be
evaluated for individual applications.
Figure 12. Circuit for Astable Operation
Figure 13. Typical Astable Waveforms
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
NE555, NE555Y, SA555, SE555, SE555C
PRECISION TIMERS
SLFS022 – SEPTEMBER 1973 – REVISED FEBRUARY 1992
APPLICATION INFORMATION
Figure 13 shows typical waveforms generated during astable operation. The output high-level duration t and
H
low-level duration t may be calculated as follows:
L
100 k
R
+ 2 R = 1 kΩ
B
A
t
t
0.693 (R
0.693 (R
R
C
R
+ 2 R = 10 kΩ
B
H
L
A
B)
A
R
10 k
1 k
C
+ 2 R = 100 kΩ
A
B
B)
Other useful relationships are shown below.
period
t
t
0.693 (R
2R ) C
B
H
L
A
1.44
100
frequency
(R
2R ) C
A
B
10
t
R
B
L
Output driver duty cycle
t
t
R
2R
H
L
A
B
1
R
+ 2 R = 1 MΩ
B
A
Output waveform duty cycle
t
R
R
+ 2 R = 10 MΩ
B
A
H
B
2R
1–
R
0.1
t
t
R
0.001
0.01
0.1
1
10
100
H
t
L
A
B
C – Capacitance – µF
L
B
Low-to-high ratio
t
R
R
Figure 14. Free-Running Frequency
H
A
B
missing-pulse detector
The circuit shown in Figure 15 may be used to detect a missing pulse or abnormally long spacing between
consecutive pulses in a train of pulses. The timing interval of the monostable circuit is continuously retriggered
by the input pulse train as long as the pulse spacing is less than the timing interval. A longer pulse spacing,
missing pulse, or terminated pulse train permits the timing interval to be completed, thereby generating an
output pulse as illustrated in Figure 16.
V
CC
(5 V to 15 V)
V
R
= 5 V
= 1 kΩ
CC
A
C = 0.1 µF
R
R
A
L
4
8
See Figure 15
RESET
V
CC
OUT
Input
3
Output
2
5
TRIG
Input Voltage
7
6
DISCH
CONT
THRES
0.01 µF
GND
1
Output Voltage
C
A5T3644
Capacitor Voltage
Time – 0.1 ms/div
Pin numbers shown are shown for the D, JG, and P packages.
Figure 15. Circuit for Missing Pulse Detector
Figure 16. Circuit for Missing Pulse Detector
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
NE555, NE555Y, SA555, SE555, SE555C
PRECISION TIMERS
SLFS022 – SEPTEMBER 1973 – REVISED FEBRUARY 1992
APPLICATION INFORMATION
frequency divider
By adjusting the length of the timing cycle, the basic circuit of Figure 9 can be made to operate as a frequency
divider. Figure 17 illustrates a divide-by-three circuit that makes use of the fact that retriggering cannot occur
during the timing cycle.
V
R
= 5 V
= 1250 Ω
CC
A
C = 0.02 µF
See Figure 9
Input Voltage
Output Voltage
Capacitor Voltage
Time – 0.1 ms/div
Figure 17. Divide-By-Three Circuit Waveforms
pulse-width modulation
The operation of the timer may be modified by modulating the internal threshold and trigger voltages, which is
accomplished by applying an external voltage (or current) to CONT. Figure 18 shows a circuit for pulse-width
modulation. A continuous input pulse train triggers the monostable circuit, and a control signal modulates the
threshold voltage. Figure 19 illustrates the resulting output pulse-width modulation. While a sine-wave
modulation signal is illustrated, any wave shape could be used.
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
NE555, NE555Y, SA555, SE555, SE555C
PRECISION TIMERS
SLFS022 – SEPTEMBER 1973 – REVISED FEBRUARY 1992
APPLICATION INFORMATION
V
CC
(5 V to 15 V)
R
= 3 kΩ
A
C = 0.02 µF
R
= 1 kΩ
L
See Figure 18
R
R
L
A
4
8
Modulation Input Voltage
Clock Input Voltage
RESET
V
CC
OUT
3
2
5
Output
Clock
Input
TRIG
7
6
DISCH
THRES
Modulation
Input
(see Note A)
CONT
GND
1
C
Output Voltage
Pin numbers shown are for the D, JG, and P packages only.
NOTE A: The modulating signal may be direct or capacitively
coupled to CONT. For direct coupling, the effects of
modulation source voltage and impedance on the bias of
the timer should be considered.
Capacitor Voltage
Time – 0.5 ms/div
Figure 18. Circuit for Pulse-Width Modulation
Figure 19. Pulse-Width Modulation Waveforms
pulse-position modulation
As shown in Figure 20, any of these timers may be used as a pulse-position modulator. This application
modulates the threshold voltage, and thereby the time delay, of a free-running oscillator. Figure 21 illustrates
a triangular-wave modulation signal for such a circuit; however, any wave shape could be used.
V
(5 V to 15 V)
CC
R
R
R
= 3 kΩ
= 500 Ω
= 1 kΩ
A
B
L
See Figure 20
R
R
A
4
8
L
3
RESET
TRIG
V
CC
OUT
2
5
Output
Modulation Input Voltage
7
6
DISCH
THRES
R
Modulation
Input
B
CONT
(see Note A)
GND
C
Output Voltage
Pin numbers shown are for the D, JG, and P packages only.
NOTE A: The modulating signal may be direct or capacitively
coupled to CONT. For direct coupling, the effects of
modulation source voltage and impedance on the bias of
the timer should be considered.
Capacitor Voltage
Time – 0.1 ms/div
Figure 21. Pulse-Position-Modulation Waveforms
Figure 20. Circuit for Pulse-Position Modulation
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
NE555, NE555Y, SA555, SE555, SE555C
PRECISION TIMERS
SLFS022 – SEPTEMBER 1973 – REVISED FEBRUARY 1992
APPLICATION INFORMATION
sequential timer
V
CC
4
8
4
8
4
8
33 kΩ
33 kΩ
RA
R
R
C
B
RESET
V
RESET
V
RESET
V
CC
OUT
CC
CC
OUT
3
7
6
3
7
6
3
7
2
5
2
5
OUT
DISCH
THRES
2
TRIG
TRIG
TRIG
0.001
µF
0.001
µF
S
DISCH
DISCH
5
CONT
CONT
CONT
6
THRES
THRES
GND
GND
GND
0.01
µF
0.01
µF
0.01
µF
1
1
1
C
C
C
C
B
A
C
R
= 14.7 µF
= 100 kΩ
C
= 10 µF
C
C
A
Output A
Output B
Output C
R
= 100 kΩ
A
C
R
= 4.7 µF
= 100 kΩ
B
B
S closes momentarily at t = 0.
Pin numbers shown are for the D, JG, and P packages only.
Figure 22. Sequential Timer Circuit
Many applications, such as computers, require signals for initializing conditions during start-up. Other
applications, such as test equipment, require activation of test signals in sequence. These timing circuits may
be connected to provide such sequential control. The timers may be used in various combinations of astable
ormonostablecircuitconnections, withorwithoutmodulation, forextremelyflexiblewaveformcontrol. Figure 22
illustrates a sequencer circuit with possible applications in many systems, and Figure 23 shows the output
waveforms.
See Figure 22
t
A
w
t
A = 1.1 R C
A A
Output A
Output B
Output C
w
t
B
w
t
B = 1.1 R C
B B
w
t
C = 1.1 R C
C C
w
t
C
w
t = 0
t – Time – 1 s/div
Figure 23. Sequential Timer Waveforms
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
相关型号：
SE555C106KBR
Ceramic Capacitor, Ceramic, 50V, 10% +Tol, 10% -Tol, X7R, -/+15ppm/Cel TC, 10uF, 5020,
KYOCERA AVX
SE555C106MBA
Ceramic Capacitor, Ceramic, 50V, 20% +Tol, 20% -Tol, X7R, -/+15ppm/Cel TC, 10uF, 5020,
KYOCERA AVX
SE555C106ZAR
Ceramic Capacitor, Ceramic, 50V, 80% +Tol, 20% -Tol, X7R, 15% TC, 10uF, Through Hole Mount, 5020, RADIAL LEADED, ROHS COMPLIANT
KYOCERA AVX
SE555C116KBA
Ceramic Capacitor, Ceramic, 50V, 10% +Tol, 10% -Tol, X7R, -/+15ppm/Cel TC, 11uF, 5020,
KYOCERA AVX
SE555C116MAR
Ceramic Capacitor, Ceramic, 50V, 20% +Tol, 20% -Tol, X7R, 15% TC, 11uF, Through Hole Mount, 5020, RADIAL LEADED, ROHS COMPLIANT
KYOCERA AVX
SE555C116ZAATR1
Ceramic Capacitor, Ceramic, 50V, 80% +Tol, 20% -Tol, X7R, -/+15ppm/Cel TC, 11uF, 5020,
KYOCERA AVX
SE555C116ZAR
Ceramic Capacitor, Ceramic, 50V, 80% +Tol, 20% -Tol, X7R, 15% TC, 11uF, Through Hole Mount, 5020, RADIAL LEADED, ROHS COMPLIANT
KYOCERA AVX
SE555C116ZBA
Ceramic Capacitor, Ceramic, 50V, 80% +Tol, 20% -Tol, X7R, -/+15ppm/Cel TC, 11uF, 5020,
KYOCERA AVX
SE555C126MAR
Ceramic Capacitor, Ceramic, 50V, 20% +Tol, 20% -Tol, X7R, 15% TC, 12uF, Through Hole Mount, 5020, RADIAL LEADED, ROHS COMPLIANT
KYOCERA AVX
SE555C126MBA
Ceramic Capacitor, Ceramic, 50V, 20% +Tol, 20% -Tol, X7R, -/+15ppm/Cel TC, 12uF, 5020,
KYOCERA AVX
SE555C126ZAR
Ceramic Capacitor, Ceramic, 50V, 80% +Tol, 20% -Tol, X7R, 15% TC, 12uF, Through Hole Mount, 5020, RADIAL LEADED, ROHS COMPLIANT
KYOCERA AVX
SE555C685KAR
Ceramic Capacitor, Ceramic, 50V, 10% +Tol, 10% -Tol, X7R, 15% TC, 6.8uF, Through Hole Mount, 5020, RADIAL LEADED, ROHS COMPLIANT
KYOCERA AVX
©2020 ICPDF网 联系我们和版权申明