SM28VLT32-HT [TI]
具有串行外设接口 (SPI) 总线的 32Mb 高温闪存;
| 型号： | SM28VLT32-HT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有串行外设接口 (SPI) 总线的 32Mb 高温闪存 闪存 |
| 文件： | 总16页 (文件大小：405K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SM28VLT32-HT
www.ti.com.cn
ZHCSAT2C –NOVEMBER 2012–REVISED MARCH 2013
32 位高温闪存存储器
此存储器具有串行外设接口 (SPI) 接口
查询样品: SM28VLT32-HT
1
特性
•
•
•
•
•
•
•
•
•
•
•
针对高温环境的 32 兆位闪存
支持极端温度环境下的应用
串行外设接口 (SPI) 兼容（模式 0 和 3）
用于 IO 的 3.3V 电源，用于内核的 1.9V 电源
2M x 16 位字存取
•
•
•
•
受控基线
一个组装和测试场所
一个制造场所
异步读取、写入和擦除操作
极端（-55°C 至 210°C）
温度范围内可用
(1)
只在 -55°C 至 125°C 温度范围内支持擦除操作
12MHz 最高时钟频率
•
•
•
•
延长的产品生命周期
延长的产品变更通知
产品可追溯性
使用寿命：1000 个程序和擦除周期
数据保留：1000 小时
德州仪器 （TI） 高温产品利用高度优化的硅（芯
片）解决方案，此解决方案对设计和制造工艺进行
了提升以在拓展的温度范围内大大地提高性能。 在
最大额定温度下，所有器件可连续正常运行1000
小时。
ESD 保护：2kV HBM，500V CDM
8mm x 20mm 14 引脚陶瓷 HKN 封装和 KGD（裸
芯片）封装
应用范围
HKN 封装
(顶视图)
•
•
•
•
浅孔能源钻井
测试和测量仪器
VSS
HOLD#
VCORE
VIO
极端环境下的地震数据采集
在极高和极低温度环境下的通用数据采集应用
RST#
WP#
CS#
SO
FLCLK
VIO
SI
SCK
VSS
VCORE
(1) 可定制工作温度范围
说明
SM28VLT32 是一款 32 兆位闪存存储器，此存储器设计用于存储程序代码和/或采集到的数据。 这个器件的宽温度
额定值使得它非常适合于需要在恶劣环境中可靠执行的应用。 SM28VLT32 借助于它的串行外设接口 (SPI) 提供低
引脚数量以实现额外的可靠性以及这些应用中的简便组装。
存储器被分区成扇区以提供每个 16 位的 2M 字寻址。 因此，存储器地址为 21 位宽。
SM28VLT32 支持串行外设接口以在闪存存储器中读取/写入/擦除数据。 此接口与模式 0 (CPOL = 0，CPHA = 0)
和 3 (CPOL = 1，CPHA = 1) 兼容。 将 CS# 置为有效将使器件进入通信模式。 在 CS# 被取消置位时，器件忽略
SPI 引脚上的所有活动。 如图 1中所示，为了在应用中实现较大存储器，可通过独立控制 CS# 引脚由一个单个主
控器件来控制多个 SM28VLT32 器件。 将 HOLD# 引脚置为有效（同时 CS# 也被置位）将使器件忽略其它 SPI 输
入引脚（SCK 和 SI）上的活动。
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
版权 © 2012–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
English Data Sheet: SLVSAO2
SM28VLT32-HT
ZHCSAT2C –NOVEMBER 2012–REVISED MARCH 2013
www.ti.com.cn
SM28VLT32
SM28VLT32
SM28VLT32
SM28VLT32
CS#
CS#
SCK SI SO
CS#
SCK SI SO
CS#
SCK SI SO
SCK SI SO
CS1#
CS2#
SCK SI SO
SPI Bus
Master /
Micro-
CS3#
CS4#
Controller
图 1. 显示使用多个 SM28VLT32 器件来实现较大存储器的系统方框图
SM28VLT32 使用 WP# 引脚来支持一个硬件数据保护机制。 如果 WP# 为低电平，擦除和编程操作被禁止。
2
Copyright © 2012–2013, Texas Instruments Incorporated
SM28VLT32-HT
www.ti.com.cn
ZHCSAT2C –NOVEMBER 2012–REVISED MARCH 2013
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
TJ
PACKAGE
14-Pin HKN
ORDERABLE PART NUMBER
TOP-SIDE MARKING
28VLT32SHKN
N/A
SM28VLT32SHKN
–55°C to 210°C
KGD (Bare Die)
SM28LVT32SKGD3
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
UNIT
VIO
VCORE
VI
Supply voltage range (for IO)
Supply voltage range (for Core)
Input voltage range
–0.3 V to 4.5 V
–0.3 V to 2.5 V
–0.2 V to (VIO + 0.2)
–0.2 V to (VIO + 0.2)
> 2000 V
VO
Output voltage range
ESD
TJ
Electrostatic discharge (HBM, 1.5 kΩ, 100 pF)
Operating junction temperature range
–55°C to 215°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
PACKAGE DISSIPATION RATINGS
θJA THERMAL IMPEDANCE
JUNCTION TO AMBIENT
θJC THERMAL IMPEDANCE
JUNCTION TO CASE (THERMAL PAD)
θJB THERMAL IMPEDANCE
JUNCTION TO BOARD
PACKAGE
HKN
63°C/W
0.84°C/W
55°C/W
RECOMMENDED OPERATING CONDITIONS
MIN
3.1
TYP
3.3
MAX UNIT
VIO
Device supply voltage for IO
Device supply voltage for Core
Junction temperature
3.6
1.98
210
V
V
VCORE
TJ
1.8
1.9
–55
°C
ELECTRICAL CHARACTERISTICS: IO
VIO = 3.1 V to 3.6 V, VCore = 1.8 V to 1.98 V, TJ = –55°C to 210°C (unless otherwise noted)
PARAMETER
Input high voltage
Input low voltage
Output high current
Output low current
Output high voltage
Output low voltage
Input capacitance
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
VIH
VIL
IOH
IOL
VOH
VOL
CI
2.5
0.9
8
V
VOH = VOHmin
-8
mA
mA
V
VOL = VOLmax
IOH = IOHmin
IOL = IOLmax
2.8
0.8
V
6.5
pF
Copyright © 2012–2013, Texas Instruments Incorporated
3
SM28VLT32-HT
ZHCSAT2C –NOVEMBER 2012–REVISED MARCH 2013
www.ti.com.cn
ELECTRICAL CHARACTERISTICS: MEMORY
VIO = 3.1 V to 3.6 V, VCore = 1.8 V to 1.98 V, TJ = –55°C to 210°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
hrs
tLife
Continuous operating life
1000
IDDVCORE
IDDVIO
127
14
160
22
mA
mA
mA
mA
s
Erase current
-55°C to 125°C
76
Program current
85
Sector erase time
Program time 1 16-bit word
-55°C to 125°C
TJ = 30°C
2
3
30
300
µs
Nf
Flash endurance for the array
(write/erase cycles)
1000
cycles
ELECTRICAL CHARACTERISTICS: SPI(1)(2)
VIO = 3.1 V to 3.6 V, VCore = 1.8 V to 1.98 V, TJ = –55°C to 210°C (unless otherwise noted)
PARAMETER
SPI input clock frequency(3)
Flash clock(3)
TEST CONDITIONS
MIN
TYP
MAX
10
UNIT
MHz
MHz
ns
fSCK
fCLK
tWH
tWL
tSU1
tSU2
tOEN
tDIS
tHD
12
Clock high time
25
25
15
10
5
Clock low time
ns
CS# setup time before SCK
SI setup time before SCK
CS# to SO enabled
CS# to SO disabled(4)
Data hold time after SCK
ns
ns
CL = 16 pF
16.5
16.5
ns
CL = 16 pF
5
ns
5
ns
tr/tf
10% to 90% on all input pins
CL = 50 pF
20
30
ns
tV
Clock low to data valid
15
ns
(1) See Figure 3.
(2) AC parameters apply to tr/tf of 5 ns.
(3) The ratio of fCLK/fSCK must be 6/5 or higher to insure proper asynchronous operation. Operation below 12 MHz is acceptable, however,
some configuration changes are required to set proper internal timing. See Provisions for Operating With fCLK Frequencies Less than 12
MHz for details if planned fCLK usage is below 12 MHz.
(4) Disable parameters are specified when the outputs are no longer driven.
4
Copyright © 2012–2013, Texas Instruments Incorporated
SM28VLT32-HT
www.ti.com.cn
ZHCSAT2C –NOVEMBER 2012–REVISED MARCH 2013
100000.00
10000.00
1000.00
105
115
125
135
145
155
165
175
185
195
205
215
Continuous T (°C)
J
(1) See datasheet for absolute maximum and minimum recommended operating conditions.
(2) Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect
life).
(3) The predicted operating lifetime vs. junction temperature is based on reliability modeling and available qualification
data.
Figure 2. SM28VLT32-HT Operating Life Derating Chart
CS#
TWH
SCK
TSU1
TWL TSU2
THD
SI
TOEN
TV
TDIS
SO
Figure 3. SPI Timing Diagram
Copyright © 2012–2013, Texas Instruments Incorporated
5
SM28VLT32-HT
ZHCSAT2C –NOVEMBER 2012–REVISED MARCH 2013
www.ti.com.cn
DIE LAYOUT
A. All dimensions are in microns
B. Substrate can either float or be grounded
C. Die thickness = 381 µm
Table 1. Bare Die Information
DIE
THICKNESS
DIE PAD
COMPOSITION
BACKSIDE
POTENTIAL
BACKSIDE FINISH
15 Mils
AlCu/TiN
Silicon with backgrind
Float
6
Copyright © 2012–2013, Texas Instruments Incorporated
SM28VLT32-HT
www.ti.com.cn
PAD NO.
ZHCSAT2C –NOVEMBER 2012–REVISED MARCH 2013
Table 2. Bond Pad Coordinates
BOND PAD COORDINATES (µm)
DESCRIPTION
X MIN
Y MIN
11182.64
82.11
X MAX
Y MAX
11267.69
167.16
1
VCORE
VSS
439.985
525.035
73
449.715
534.765
74
HOLD#
RST#
WP#
FLCLK
VIO
989.765
82.11
1074.815
1614.865
2154.915
2694.965
3235.015
3775.065
3765.335
3229.205
2685.235
2135.035
1605.135
1065.085
167.16
75
1529.815
2069.865
2609.915
3149.965
3690.015
3680.285
3144.155
2600.185
2049.985
1520.085
980.035
82.11
167.16
76
82.11
167.16
77
82.11
167.16
78
82.11
167.16
79
VCORE
VSS
82.11
167.16
145
146
147
148
149
150
11182.64
11182.64
11182.64
11182.64
11182.64
11182.64
11267.69
11267.69
11267.69
11267.69
11267.69
11267.69
SCK
SI
SO
CS#
VIO
Copyright © 2012–2013, Texas Instruments Incorporated
7
SM28VLT32-HT
ZHCSAT2C –NOVEMBER 2012–REVISED MARCH 2013
www.ti.com.cn
DEVICE INFORMATION
HKN PACKAGE PIN ASSIGNMENT (TOP VIEW)
VSS
HOLD#
RST#
VCORE
VIO
CS#
WP#
SO
FLCLK
VIO
SI
SCK
VSS
VCORE
TERMINAL FUNCTIONS
TERMINAL
TYPE
DESCRIPTION
NAME
NO.
6, 13
7, 14
1, 8
12
9
VIO
Power 3.3-V supply for IO
Power 1.9-V supply for core
Ground Device ground
VCORE
VSS
CS#
Input
Input
Input
Active low SPI chip select
SPI clock for serial communication
SPI data input to device
SCK
SI
10
11
2
SO
Output SPI data output from device (Hi impedance when CS# is 1)
HOLD#
WP#
RST#
FLCLK
Input
Input
Input
Input
Active low hold input to freeze SPI communication
Active low input for sector protection
Active low reset to IC
4
3
5
Flash pump clock
FUNCTIONAL BLOCK DIAGRAM
Flash Pump
4 Mb
Bank
4 Mb
Bank
CS#
SCK
SI
4 Mb
Bank
4 Mb
Bank
SPI &
Memory
Controll
er
SO
Addr, Data,
Ctrl Buses
HOLD#
WP#
4 Mb
Bank
4 Mb
Bank
Config,
Status,
4 Mb
Bank
4 Mb
Bank
Memory
Protectio
Figure 4. Block Diagram of SM28VLT32 and Memory Architecture
8
Copyright © 2012–2013, Texas Instruments Incorporated
SM28VLT32-HT
www.ti.com.cn
ZHCSAT2C –NOVEMBER 2012–REVISED MARCH 2013
DETAILED DESCRIPTION
SERIAL COMMUNICATION
SM28VLT32 supports mode 0 and mode 3 SPI protocols. In mode 0, the inactive state of SCK is 0 whereas, in
mode 3, the state is 1. The input data on SI is always latched on rising edge of SCK and data on SO is output on
falling edge of SCK in both modes. CS# is brought low to start a new SPI data frame. The SPI data frame
consists of an 8-bit command byte followed by a variable number of bytes of input data as shown in Table 3. The
first 8 bits of SO always output the quick status bits. These bits define error conditions and status of the FLASH
(see Table 4). These bits should be evaluated after each command is executed to determine if the preceding
command completed successfully. This can be implemented as part of the SPI communication protocol with the
host device. For more information see the Application Information section. The output data on SO follows after
the complete data is provided to the device on SI pin. Invalid command bytes are ignored. Also, any additional
SCK clock cycles and additional data on SI beyond the depicted frame size are ignored. CS# going high
delineates the end of current data frame.
CS#
SCK
SI
Command Byte
Quick Status Byte
Input Bytes (Address/Data/Dummy)
Dummy Output Output Data Bytes
SO
Figure 5. SPI Data Frame to Read, Write, Erase Memory Data and to Access Config/Status Registers
Copyright © 2012–2013, Texas Instruments Incorporated
9
SM28VLT32-HT
ZHCSAT2C –NOVEMBER 2012–REVISED MARCH 2013
www.ti.com.cn
Table 3. Serial Peripheral Interface (SPI) Data Frame(1)
DUMMY
BYTES ON
SI(2)
COMMAND
BYTE ON SI
ADDRESS
BYTES ON SI
DATA BYTES
ON SI
DATA BYTES TOTAL BYTES
COMMAND NAME
DESCRIPTION
ON SO
IN FRAME
Read Word
15h
16h
17h
18h
19h
22
3
0
3
0
3
0
3
3
0
0
2
2
0
0
0
2
1 (3)
1 (3)
1 (1)
1 (1)
1 (1)
0 (2)
1 (1)
1 (1)
2
2
0
0
0
2
0
0
7
4
7
4
5
3
5
7
Read word at given address
Read Word with
auto addressing
Burst read from previous
address
Write Word
Write word at given address
Write Word with
auto addressing
Erase Segment(3)
Burst write from previous
address
Erase addressed segment
Read SPI status register
Validates addressed segment
Read Status
Register
Validate Segment
Write Register
1A
Writes to address in
configuration register
1D
Reads from address in
configuration register
Read Register
1E
1F
3
0
0
2
1 (3)
1 (1)
2
0
7
4
Flash controller command
interface for special functions.
See Application Information
section.
Write Command
(1) Multi-byte inputs and results are MSB first, LSB last.
(2) (#) indicates total number of dummy SI bytes including overlap with SO output.
(3) Permanent damage to flash array may occur if erase is executed when TJ exceeds 125°C.
REGISTER DEFINITIONS
Table 4. Quick Status Register
DEFAULT
VALUE
BITS
TYPE
DESCRIPTION
7
6
0
R
R
Unused
SPI Frame error: indicates frame ended with less than required
bytes to complete
0
5
4
3
0
0
0
R
R
R
Write Busy: indicates that a program operation is in progress
Erase Busy: indicates that a sector is being erased
Device Busy
Invalid Data: indicates that an attempt was made to set a bit to 1
that has already been programmed to 0
2
1
0
0
0
0
R
R
R
Read error: indicates that read was attempted on address when
data was not available
Command error: indicates that a prior command failed. Must be
cleared.
Table 5. Status Register (Command 22h)
DEFAULT
VALUE
BITS
TYPE
DESCRIPTION
15:12
0
R
R
R
R
R
R
R
R
R
R
Reserved
11:08
RevID
Revision ID (current revision 1001)
Unused
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Read Busy
Write Busy
Erase Busy
Write Suspend
Erase Suspend
Flash Pump Ready
SPI Frame error
10
Copyright © 2012–2013, Texas Instruments Incorporated
SM28VLT32-HT
www.ti.com.cn
ZHCSAT2C –NOVEMBER 2012–REVISED MARCH 2013
APPLICATION INFORMATION
The quick status register is intended to be used as feedback of device and command status. The host should
evaluate the quick status results at each command execution to determine device status. Additionally, two of the
error fields in the quick status are sticky. They will need to be intentionally cleared by the host once detected.
The Command and Invalid Data error flags will not self clear. The command error bit indicates that a command
failed. This can be either an erase or program command. If this was a program attempt, then the data written
may not be valid. The host may decide to re-write this data or pursue some other error recovery path. The Invalid
data bit will get set if an attempt to write a bit to a logical 1 (erased state) in a word that has that bit already
programmed to a 0. This would likely be the first error seen when writing to an array that contains data. To clear
a Command error or Invalid Data error, the host must execute the following SPI command sequence: 1F 00 40
xx. xx is a dummy byte and values are don't care. This SPI command is a special command that is sent to the
internal flash controller to clear errors.
It is important to note that the quick status capture of the internal setting of the Command error and the Invalid
Data flags are delayed by one transaction. Similarly, the Device Busy flag does not get cleared until a second
transaction. For example, in the case of polling after a write. If this write generated an Invalid Data error, the
sequence would be as follows.
SPI WRITE
SPI READ
DESCRIPTION
Write to address 0 with erased value This will cause Invalid Data error if word has
been programmed.
0x17_0000_FFFF
00_xxxx_xxxx
0xFF
0xFF
08
04
Execute quick status. This result is Device Busy.
Execute quick status with Invalid Data error.
Similarly, if a write or program fails, then the Command error status will show on the second transaction after the
failed command. To effectively deal with this in a protocol, the best method is to poll the quick status twice to
validate no error occurred. For applications that this method is too costly for SPI bandwidth, the error can be
trapped on execution of the following commands with the knowledge that the error belonged to the command 2
transactions earlier.
The SPI Frame error and the Read error are errors that return correct status on the next quick status. These two
errors are not sticky and only apply to the prior transaction.
Provisions for Operating With fCLK Frequencies Less than 12 MHz
The SM28VLT32 uses a state machine and registers to implement the correct algorithms for programing, erasure
and validation. The register values define counters and loops that determine appropriate setup and hold times,
maximum attempts, pulse widths, and other critical parameters. The default values of these registers are defined
for fCLK operation in the 10 MHz to 12 MHz range. Operating below 10 MHhz requires changing key registers to
properly implement the algorithm. See Table 6 for register settings for specific fCLK ranges. Note, the 10 MHz to
12 MHz values are provided, but are not required to be written as they are the reset defaults. Additionally, the
SPI SCLK frequency must be 5/6ths of fCLK or slower for reliable operation.
The values below represent the address and value that should be written using the 1D command. Note that first
line is a write to F004. This must be first, as it unlocks the test control register and allows modification of the
memory mapped registers. Without this write, the contents of the register would not change. It is recommended
to follow the register writes with a read to verify that change was properly implemented. The last line is a write
back to the test control register to relock it preventing accidental modification of the registers.
Copyright © 2012–2013, Texas Instruments Incorporated
11
SM28VLT32-HT
ZHCSAT2C –NOVEMBER 2012–REVISED MARCH 2013
www.ti.com.cn
Table 6. Required Register Modifications for Operating at Frequencies Below 10 MHz(1)
ADDRESS
F004
8006
8008
8009
8010
8014
8015
8016
8017
8018
800D
800E
F004
12-10 MHz
2BC0
0764
10-8 MHz
2BC0
0654
8-6 MHz
2BC0
0544
3050
0808
0808
0020
5460
0FA0
0808
0040
0808
0140
03C0
6-4 MHz
2BC0
0434
303C
0606
0606
0018
3F48
0BB8
0606
0030
0606
00F0
03C0
4-2 MHz
2BC0
0324
3028
0404
0404
0010
2A30
07D0
0404
0020
0404
00A0
03C0
Unlock TCR
307D
0D0D
0D0D
0032
3064
0A0A
0A0A
0028
83D6
186A
6978
1388
0D0D
0064
0A0A
0050
0D0D
01F4
0A0A
0190
03C0
03C0
Lock TCR
(1) fCLK cannot be operated lower than 2 MHz.
Initialization of the register values must be repeated on power cycle or RST assertion.
Power Supply Sequencing
The ideal power supply sequence is VCORE coming up before VIO (VCORE > 1.65 V before VIO greater than
0.8 V).
For powerdown, the reverse is also true. VIO should be below 0.8 V before VCORE is < 1.65 V.
Alternatively, VIO can come up first or simultaneously with VCORE if RST is asserted low until both supplies are
within recommended operating range. Similarly if device is active, it is necessary to assert RST prior to powering
down to minimize chance of corrupting the flash array.
Power Saving Features
The device has power saving capabilities that allow it to be put into either standby or sleep states for the banks
and flash pump when periods of inactivity are detected. When an access is initiated during sleep or standby, the
pump and banks will transition to the active state automatically. Use of these features does not have protocol
impact on programming (other than additional time required to wake up), as the device will report Write Busy.
However, during read operations, the device will report Read error on next quick status read. This is due to the
fact that a read transaction is immediate, while a write is queued. The value read from an address that is in
standby or sleep will be 00 00. Reference Application Note: "Using the SM28VLT32-HT With Power Saving
Features" (SLVA550).
12
Copyright © 2012–2013, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
4-Feb-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SM28VLT32SHKN
SM28VLT32SKGD3
ACTIVE
CFP
HKN
14
0
10
RoHS & Green
RoHS & Green
AU
N / A for Pkg Type
N / A for Pkg Type
-55 to 210
-55 to 210
28VLT32S
HKN
ACTIVE
XCEPT
KGD
12
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
4-Feb-2021
Addendum-Page 2
重要声明和免责声明
TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没
有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他 TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款 (https:www.ti.com.cn/zh-cn/legal/termsofsale.html) 或 ti.com.cn 上其他适用条款/TI 产品随附的其他适用条款
的约束。TI 提供这些资源并不会扩展或以其他方式更改 TI 针对 TI 产品发布的适用的担保或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2021 德州仪器半导体技术（上海）有限公司
相关型号：
©2020 ICPDF网 联系我们和版权申明