首页 |元器件品牌

SM320C31 [TI]

DIGITAL SIGNAL PROCESSORS;
SM320C31
型号： SM320C31
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

DIGITAL SIGNAL PROCESSORS
文件： 总54页 (文件大小：1263K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
 查看货源
Not Recommended for New Designs  
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢉꢆ ꢃ ꢇꢈ ꢀꢁꢊ ꢃ ꢄꢅ ꢉꢆ ꢃꢇ  
ꢋꢌ ꢍꢌ ꢎꢏꢉ ꢀꢌ ꢍ ꢐꢏꢉ ꢑꢒꢓ ꢆ ꢔꢀ ꢀ ꢓ ꢒꢀ  
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006  
D
D
Processed to MIL-PRF-38535 (QML)  
D
D
Two Low-Power Modes  
Operating Temperature Ranges:  
− Military (M) −55°C to 125°C  
− Special (S) −55°C to 105°C  
On-Chip Memory-Mapped Peripherals:  
− One Serial Port Supporting  
8-/16-/24-/32-Bit Transfers  
− Two 32-Bit Timers  
D
D
SMD Approval  
− One-Channel Direct Memory Access  
(DMA) Coprocessor for Concurrent I/O  
and CPU Operation  
High-Performance Floating-Point Digital  
Signal Processor (DSP):  
− SMJ320C31-60 (5 V)  
D
Fabricated Using Enhanced Performance  
Implanted CMOS (EPIC) Technology by  
Texas Instruments (TI)  
33-ns Instruction Cycle Time  
330 Million Operations Per Second  
(MOPS), 60 Million Floating-Point  
Operations Per Second (MFLOPS),  
30 Million Instructions Per Second  
(MIPS)  
D
D
D
Two- and Three-Operand Instructions  
40 / 32-Bit Floating-Point /Integer Multiplier  
and Arithmetic Logic Unit (ALU)  
− SMJ320C31-50 (5 V)  
Parallel ALU and Multiplier Execution in a  
Single Cycle  
40-ns Instruction Cycle Time  
275 MOPS, 50 MFLOPS, 25 MIPS  
− SMJ320C31-40 (5 V)  
50-ns Instruction Cycle Time  
220 MOPS, 40 MFLOPS, 20 MIPS  
− SMJ320LC31-40 (3.3 V)  
50-ns Instruction Cycle Time  
220 MOPS, 40 MFLOPS, 20 MIPS  
− SMQ320LC31-40 (3.3 V)  
50-ns Instruction Cycle Time  
220 MOPS, 40 MFLOPS, 20 MIPS  
D
Block-Repeat Capability  
D
Zero-Overhead Loops With Single-Cycle  
Branches  
D
D
D
Conditional Calls and Returns  
Interlocked Instructions for  
Multiprocessing Support  
Bus-Control Registers Configure  
Strobe-Control Wait-State Generation  
D
Validated Ada Compiler  
D
D
D
D
D
D
D
D
32-Bit High-Performance CPU  
D
Integer, Floating-Point, and Logical  
Operations  
16-/32-Bit Integer and 32-/40-Bit  
Floating-Point Operations  
D
D
D
32-Bit Barrel Shifter  
32-Bit Instruction and Data Words, 24-Bit  
Addresses  
One 32-Bit Data Bus (24-Bit Address)  
Packaging  
Two 1K Word × 32-Bit Single-Cycle  
Dual-Access On-Chip RAM Blocks  
− 132-Lead Ceramic Quad Flatpack With  
Nonconductive Tie-Bar (HFG Suffix)  
− 141-Pin Ceramic Staggered Pin  
Grid- Array Package (GFA Suffix)  
− 132-Lead TAB Frame  
Boot-Program Loader  
64-Word × 32-Bit Instruction Cache  
Eight Extended-Precision Registers  
Two Address Generators With Eight  
Auxiliary Registers and Two Auxiliary  
Register Arithmetic Units (ARAUs)  
− 132-Lead Plastic Quad Flatpack  
(PQ Suffix)  
description  
The SMJ320C31, SMJ320LC31, and SMQ320LC31 digital signal processors (DSPs) are 32-bit, floating-point  
processors manufactured in 0.6-µm triple-level-metal CMOS technology. The devices are part of the  
SMJ320C3x generation of DSPs from Texas Instruments.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
ꢑ
ꢑ
ꢒ
ꢓ
ꢥ
ꢋ
ꢕ
ꢝ
ꢆ
ꢞ
ꢎ
ꢟ
ꢩ
ꢌ
ꢙ
ꢓ
ꢗ
ꢚ
ꢐ
ꢘ
ꢋ
ꢏ
ꢎ
ꢏ
ꢖ
ꢗ
ꢡ
ꢠ
ꢘ
ꢙ
ꢟ
ꢟ
ꢚ
ꢛ
ꢜ
ꢜ
ꢗ
ꢝ
ꢝ
ꢖ
ꢖ
ꢢ
ꢙ
ꢙ
ꢚ
ꢗ
ꢗ
ꢙ
ꢖ
ꢞ
ꢞ
ꢢ
ꢞ
ꢟ
ꢠ
ꢝ
ꢫ
ꢚ
ꢧ
ꢚ
ꢡ
ꢡ
ꢗ
ꢝ
ꢜ
ꢛ
ꢞ
ꢞ
ꢞ
ꢗ
ꢙ
ꢘ
ꢢ
ꢠ
ꢣ
ꢞ
ꢞ
ꢤ
ꢖ
ꢟ
ꢜ
ꢞ
ꢝ
ꢖ
ꢝ
ꢪ
ꢙ
ꢚ
ꢗ
ꢠ
ꢥ
ꢜ
ꢗ
ꢥ
ꢝ
ꢝ
ꢡ
ꢞ
ꢡ
ꢦ
Copyright 2006, Texas Instruments Incorporated  
ꢓ ꢗ ꢢ ꢚ ꢙꢥ ꢠꢟ ꢝꢞ ꢟꢙ ꢛꢢ ꢤꢖ ꢜꢗ ꢝ ꢝꢙ ꢁꢌ ꢉꢬ ꢑꢒ ꢭ ꢬꢃꢮꢯ ꢃꢯꢈ ꢜ ꢤꢤ ꢢꢜ ꢚ ꢜ ꢛꢡ ꢝꢡꢚ ꢞ ꢜ ꢚ ꢡ ꢝꢡ ꢞꢝꢡ ꢥ  
ꢚ
ꢙ
ꢠ
ꢟ
ꢙ
ꢚ
ꢛ
ꢝ
ꢙ
ꢞ
ꢢ
ꢖ
ꢘ
ꢖ
ꢟ
ꢡ
ꢚ
ꢝ
ꢡ
ꢚ
ꢙ
ꢘ
ꢎ
ꢡ
ꢨ
ꢜ
ꢌ
ꢗ
ꢛ
ꢡ
ꢞ
ꢝ
ꢜ
ꢗ
ꢥ
ꢜ
ꢚ
ꢥ
ꢜ
ꢝ ꢡ ꢞ ꢝꢖ ꢗꢫ ꢙꢘ ꢜ ꢤ ꢤ ꢢꢜ ꢚ ꢜ ꢛ ꢡ ꢝ ꢡ ꢚ ꢞ ꢦ  
ꢚ
ꢜ
ꢗ
ꢝ
ꢪ
ꢦ
ꢑ
ꢚ
ꢙ
ꢥ
ꢝ
ꢖ
ꢙ
ꢟ
ꢡ
ꢞ
ꢖ
ꢗ
ꢥ
ꢙ
ꢡ
ꢙ
ꢝ
ꢗ
ꢡ
ꢟ
ꢡ
ꢞ
ꢜ
ꢚ
ꢖ
ꢤ
ꢖ
ꢗ
ꢟ
ꢤ
ꢠ
ꢠ ꢗꢤ ꢡꢞꢞ ꢙ ꢝꢧꢡ ꢚ ꢩꢖ ꢞꢡ ꢗ ꢙꢝꢡ ꢥꢦ ꢓ ꢗ ꢜꢤ ꢤ ꢙ ꢝꢧꢡ ꢚ ꢢꢚ ꢙ ꢥꢠꢟ ꢝꢞ ꢈ ꢢꢚ ꢙ ꢥꢠꢟ ꢝꢖꢙꢗ  
ꢡ
ꢢ
ꢚ
ꢙ
ꢟ
ꢡ
ꢞ
ꢞ
ꢖ
ꢗ
ꢫ
ꢥ
ꢙ
ꢡ
ꢞ
ꢗ
ꢙ
ꢝ
ꢗ
ꢡ
ꢟ
ꢡ
ꢞ
ꢞ
ꢜ
ꢚ
ꢖ
ꢤ
ꢪ
ꢖ
ꢗ
ꢟ
ꢤ
ꢠ
ꢥ
ꢡ
ꢝ
ꢞ
ꢝ
ꢖ
ꢗ
ꢫ
ꢙ
ꢘ
ꢜ
ꢤ
ꢤ
ꢢ
ꢜ
ꢚ
ꢜ
ꢛ
ꢡ
ꢝ
ꢡ
ꢚ
ꢞ
ꢦ
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
Not Recommended for New Designs  
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈ ꢀꢁꢂ ꢃ ꢄ ꢅ ꢉꢆ ꢃ ꢇꢈ ꢀ ꢁꢊ ꢃꢄ ꢅ ꢉ ꢆꢃꢇ  
ꢋ ꢌꢍ ꢌꢎꢏ ꢉ ꢀꢌ ꢍꢐ ꢏ ꢉ ꢑ ꢒꢓ ꢆꢔ ꢀꢀ ꢓꢒ ꢀ  
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006  
description (continued)  
The SMJ320C3x internal busing and special digital-signal-processing instruction set have the speed and  
flexibility to execute up to 60 MFLOPS. The SMJ320C3x optimizes speed by implementing functions in  
hardware that other processors implement through software or microcode. This hardware-intensive approach  
provides performance previously unavailable on a single chip.  
The SMJ320C3x can perform parallel multiply and ALU operations on integer or floating-point data in a single  
cycle. Each processor also possesses a general-purpose register file, a program cache, dedicated ARAUs,  
internal dual-access memories, one DMA channel supporting concurrent I/O, and a short machine-cycle time.  
High performance and ease of use are results of these features.  
General-purpose applications are greatly enhanced by the large address space, multiprocessor interface,  
internally and externally generated wait states, one external interface port, two timers, one serial port, and  
multiple-interrupt structure. The SMJ320C3x supports a wide variety of system applications from host processor  
to dedicated coprocessor.  
High-level-language support is easily implemented through a register-based architecture, large address space,  
powerful addressing modes, flexible instruction set, and well-supported floating-point arithmetic.  
For additional information when designing for cold temperature operation, please see Texas Instruments  
application report 320C3x, 320C4x and 320MCM42x Power-up Sensitivity at Cold Temperature, literature  
number SGUA001.  
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
Not Recommended for New Designs  
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢉꢆ ꢃ ꢇꢈ ꢀꢁ ꢊ ꢃꢄ ꢅꢉ ꢆꢃ ꢇ  
ꢋꢌ ꢍꢌ ꢎꢏꢉ ꢀꢌ ꢍ ꢐꢏꢉ ꢑꢒꢓ ꢆ ꢔꢀ ꢀ ꢓ ꢒꢀ  
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006  
141-PIN GFA STAGGERED GRID ARRAY  
PACKAGE  
TA PACKAGE  
(TOP VIEW)  
(BOTTOM VIEW)  
1
3
2
4
5
7
9
6
8
100  
99  
Tab Leads Up  
132  
1
10  
11  
12  
14  
16  
18  
13  
15  
17  
19  
Die Face Up  
67  
33  
B
D
F
H
K
M
P
T
V
34  
66  
A
C
E
G
J
L
N
R
U
W
132-PIN HFG QUAD FLATPACK  
(TOP VIEW)  
TB PACKAGE  
(TOP VIEW)  
1
99  
100  
99  
132  
1
Tab Leads Up  
Die Face Up  
67  
33  
34  
66  
33  
67  
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
Not Recommended for New Designs  
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈ ꢀꢁꢂ ꢃ ꢄ ꢅ ꢉꢆ ꢃ ꢇꢈ ꢀ ꢁꢊ ꢃꢄ ꢅ ꢉ ꢆꢃꢇ  
ꢋ ꢌꢍ ꢌꢎꢏ ꢉ ꢀꢌ ꢍꢐ ꢏ ꢉ ꢑ ꢒꢓ ꢆꢔ ꢀꢀ ꢓꢒ ꢀ  
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006  
SMQ320LC31 pinout (top view)  
The SMQ320LC31 device is also packaged in a132-pin plastic quad flatpack (PQ Suffix). The full part numbers  
are SMQ320LC31PQM40 and 5962-9760601NXB.  
PQ PACKAGE  
(TOP VIEW)  
ꢀ ꢁ ꢀꢂ ꢀꢃ ꢀꢄ ꢀꢅ ꢀꢆ ꢀꢀ ꢀꢇ  
ꢈ
ꢉ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢀ
ꢀꢅꢆ ꢀꢅꢀ ꢀꢅꢇ ꢀꢆꢈ ꢀꢆꢉ ꢀꢆꢁ ꢀꢆꢂ ꢀꢆꢃ ꢀꢆꢄ ꢀꢆꢅ ꢀꢆꢆ ꢀꢆꢀ ꢀꢆꢇ ꢀꢀꢈ ꢀꢀꢉ ꢀꢀꢁ  
ꢀꢀ ꢂ  
A9  
ꢀ ꢉ  
ꢀ ꢈ  
ꢆ ꢇ  
ꢆ ꢀ  
ꢆ ꢆ  
ꢆ ꢅ  
ꢆ ꢄ  
ꢆ ꢃ  
ꢆ ꢂ  
ꢆ ꢁ  
ꢆ ꢉ  
ꢆ ꢈ  
ꢅ ꢇ  
ꢅ ꢀ  
ꢅ ꢆ  
ꢅ ꢅ  
ꢅ ꢄ  
ꢅ ꢃ  
ꢅ ꢂ  
ꢅ ꢁ  
ꢅ ꢉ  
ꢅ ꢈ  
ꢄ ꢇ  
ꢄ ꢀ  
ꢄ ꢆ  
ꢄ ꢅ  
ꢄ ꢄ  
ꢄ ꢃ  
ꢄ ꢂ  
ꢄ ꢁ  
ꢄ ꢉ  
ꢄ ꢈ  
ꢃ ꢇ  
DX0  
V
V
ꢀꢀ ꢃ  
ꢀꢀ ꢄ  
ꢀꢀ ꢅ  
ꢀꢀ ꢆ  
ꢀꢀꢀ  
ꢀꢀ ꢇ  
ꢀꢇꢈ  
ꢀꢇꢉ  
ꢀꢇꢁ  
ꢀꢇꢂ  
ꢀꢇꢃ  
ꢀꢇꢄ  
ꢀꢇꢅ  
ꢀꢇꢆ  
ꢀꢇꢀ  
ꢀꢇꢇ  
ꢈꢈ  
V
SS  
A8  
DD  
FSX0  
A7  
A6  
A5  
V
SS  
CLKX0  
CLKR0  
FSR0  
DD  
A4  
V
SS  
DR0  
INT3  
INT2  
A3  
A2  
A1  
A0  
V
V
DD  
V
SS  
D31  
DD  
INT1  
V
V
V
DD  
SS  
V
DD  
D30  
SS  
INT0  
IACK  
XF1  
V
SS  
SS  
SS  
V
V
ꢈ
ꢉ
ꢈ
ꢁ
V
DD  
XF0  
D29  
ꢈ
ꢂ
D28  
ꢈ
ꢃ
RESET  
R/W  
V
ꢈ
ꢄ
DD  
D27  
ꢈ
ꢅ
STRB  
RDY  
V
ꢈ
ꢆ
SS  
D26  
ꢈ
ꢀ
V
DD  
D25  
D24  
D23  
D22  
D21  
ꢈ
ꢇ
HOLD  
HOLDA  
X1  
ꢉ
ꢈ
ꢉ
ꢉ
ꢉ
ꢁ
X2/CLKIN  
ꢉ
ꢂ
V
V
V
SS  
SS  
SS  
V
ꢉ
ꢃ
DD  
D20  
ꢉ
ꢄ
ꢃ
ꢀ
ꢃ
ꢆ
ꢃ
ꢅ
ꢃ
ꢄ
ꢃ
ꢃ
ꢃ
ꢂ
ꢃ
ꢁ
ꢃ
ꢉ
ꢃ
ꢈ
ꢂ
ꢇ
ꢂ
ꢀ
ꢂ
ꢆ
ꢂ
ꢅ
ꢂ
ꢄ
ꢂ
ꢃ
ꢂ
ꢂ
ꢂ
ꢁ
ꢂ
ꢉ
ꢂ
ꢈ
ꢁ
ꢇ
ꢁ
ꢀ
ꢁ
ꢆ
ꢁ
ꢅ
ꢁ
ꢄ
ꢁ
ꢃ
ꢁ
ꢂ
ꢁ
ꢁ
ꢁ
ꢉ
ꢉ
ꢁ
ꢈ
ꢉ
ꢀ
ꢉ
ꢆ
ꢉ
ꢅ
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
Not Recommended for New Designs  
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢉꢆ ꢃ ꢇꢈ ꢀꢁ ꢊ ꢃꢄ ꢅꢉ ꢆꢃ ꢇ  
ꢋꢌ ꢍꢌ ꢎꢏꢉ ꢀꢌ ꢍ ꢐꢏꢉ ꢑꢒꢓ ꢆ ꢔꢀ ꢀ ꢓ ꢒꢀ  
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006  
Terminal Assignments  
PIN  
PIN  
NUMBER  
NUMBER  
NAME  
NAME  
PQ  
PKG  
HFG  
PKG  
GFA  
PKG  
PQ  
PKG  
HFG  
PKG  
GFA  
PKG  
29  
28  
27  
26  
25  
23  
22  
21  
20  
18  
16  
14  
13  
12  
11  
10  
9
12  
11  
L1  
K2  
A0  
A1  
64  
63  
47  
46  
45  
43  
41  
39  
38  
37  
36  
35  
33  
31  
30  
29  
28  
27  
26  
24  
22  
21  
17  
14  
91  
99  
107  
108  
109  
106  
93  
97  
73  
72  
64  
65  
82  
83  
W9  
U9  
D10  
D11  
10  
9
J1  
A2  
62  
V8  
D12  
J3  
A3  
60  
W7  
U7  
D13  
8
G1  
A4  
58  
D14  
6
F2  
A5  
56  
V6  
D15  
5
E1  
A6  
55  
W5  
U5  
D16  
4
E3  
A7  
54  
D17  
3
D2  
A8  
53  
V4  
D18  
1
C1  
A9  
52  
W3  
U3  
D19  
131  
129  
128  
127  
126  
125  
124  
123  
122  
120  
117  
116  
113  
112  
94  
95  
63  
62  
61  
60  
59  
58  
56  
55  
51  
50  
C3  
A10  
A11  
A12  
A13  
A14  
A15  
A16  
A17  
A18  
A19  
A20  
A21  
A22  
A23  
CLKR0  
CLKX0  
D0  
50  
D20  
B2  
48  
V2  
D21  
A1  
47  
W1  
R3  
D22  
C5  
46  
D23  
B4  
45  
T2  
D24  
A3  
44  
U1  
D25  
C7  
43  
N3  
D26  
8
B6  
41  
P2  
D27  
7
C9  
39  
R1  
D28  
5
B8  
38  
L3  
D29  
2
A7  
34  
M2  
N1  
D30  
1
A9  
31  
D31  
130  
129  
111  
112  
80  
79  
78  
77  
76  
75  
73  
72  
68  
67  
B10  
A11  
E17  
A19  
W19  
V16  
W17  
U13  
V14  
W15  
U11  
V12  
W11  
V10  
108  
116  
124  
125  
126  
123  
110  
114  
81  
C19  
C17  
B14  
A13  
B12  
A15  
D18  
B18  
P18  
R19  
V18  
U17  
H18  
J17  
DR0  
DX0  
EMU0  
EMU1  
EMU2  
EMU3  
FSR0  
FSX0  
HOLD  
HOLDA  
H1  
D1  
D2  
D3  
D4  
D5  
82  
D6  
90  
D7  
89  
H3  
D8  
99  
IACK  
INT0  
D9  
100  
†
‡
§
CV , V  
, and IV  
SS  
are on the same plane.  
are on the same plane.  
SS SSL  
AV , DV , CV , and PV  
DD  
SUBS  
DD  
DD  
DD  
V
connects to die metallization. Tie this pin to clean ground.  
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
Not Recommended for New Designs  
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈ ꢀꢁꢂ ꢃ ꢄ ꢅ ꢉꢆ ꢃ ꢇꢈ ꢀ ꢁꢊ ꢃꢄ ꢅ ꢉ ꢆꢃꢇ  
ꢋ ꢌꢍ ꢌꢎꢏ ꢉ ꢀꢌ ꢍꢐ ꢏ ꢉ ꢑ ꢒꢓ ꢆꢔ ꢀꢀ ꢓꢒ ꢀ  
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006  
Terminal Assignments (Continued)  
PIN  
PIN  
NUMBER  
NUMBER  
NAME  
NAME  
PQ  
PKG  
HFG  
PKG  
GFA  
PKG  
PQ  
PKG  
HFG  
PKG  
GFA  
PKG  
†
†
103  
106  
107  
127  
92  
86  
89  
E19  
F18  
G17  
C11  
L19  
N17  
K18  
A17  
M18  
B16  
C15  
G5  
INT1  
INT2  
30  
35  
18  
19  
20  
25  
34  
40  
44  
52  
53  
54  
67  
68  
69  
84  
85  
92  
96  
100  
102  
111  
71  
70  
79  
81  
P4  
T10  
K4  
V
V
SSL  
SSL  
90  
INT3  
36  
DV  
SS  
†
110  
77  
MCBL/MP  
R/W  
37  
T4  
IV  
SS  
42  
G3  
DV  
SS  
†
95  
75  
RDY  
51  
K16  
T8  
CV  
SS  
†
94  
78  
RESET  
SHZ  
57  
IV  
SS  
118  
93  
101  
76  
61  
T12  
R11  
J15  
W13  
D10  
D16  
T16  
D12  
F16  
H16  
D14  
U15  
C13  
T18  
U19  
J19  
G19  
F6  
DV  
SS  
†
STRB  
TCLK0  
TCLK1  
69  
V
SSL  
SSL  
†
120  
103  
105  
121  
130  
7
70  
V
71  
DV  
SS  
‡
‡
‡
†
AV  
AV  
AV  
84  
CV  
DD  
DD  
DD  
SS  
†
6
15  
24  
32  
33  
40  
49  
59  
65  
66  
74  
83  
91  
97  
104  
105  
115  
121  
131  
132  
3
E7  
85  
IV  
SS  
E5  
86  
DV  
SS  
†
15  
N5  
V
DDL  
V
DDL  
101  
102  
109  
113  
117  
119  
128  
88  
V
SSL  
CV  
†
16  
R5  
SS  
‡
‡
‡
†
23  
H4  
DV  
DV  
DV  
IV  
SS  
DD  
DD  
DD  
§
32  
J5  
V
SUBS  
DV  
42  
T14  
R7  
SS  
†
48  
V
DDL  
V
DDL  
CV  
SS  
X1  
49  
R9  
‡
‡
‡
‡
57  
R13  
R15  
P16  
N15  
G15  
E15  
L15  
E9  
DV  
DV  
CV  
CV  
X2/CLKIN  
XF0  
DD  
DD  
DD  
DD  
66  
87  
74  
96  
XF1  
80  
98  
No Connect  
87  
V
DDL  
D4  
DV  
DV  
DV  
DV  
DV  
DV  
DV  
DV  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
SS  
88  
V
DDL  
N19  
R17  
L17  
M16  
D6  
‡
‡
98  
PV  
PV  
DD  
104  
114  
115  
118  
119  
132  
2
DD  
E13  
E11  
L5  
V
V
DDL  
DDL  
†
V
A5  
SSL  
DV  
H2  
D8  
SS  
†
4
M4  
CV  
SS  
DV  
17  
19  
F4  
SS  
†
13  
T6  
CV  
SS  
†
‡
§
CV , V  
, and IV  
SS  
are on the same plane.  
are on the same plane.  
SS SSL  
AV , DV , CV , and PV  
DD  
SUBS  
DD  
DD  
DD  
V
connects to die metallization. Tie this pin to clean ground.  
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
Not Recommended for New Designs  
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢉꢆ ꢃ ꢇꢈ ꢀꢁ ꢊ ꢃꢄ ꢅꢉ ꢆꢃ ꢇ  
ꢋꢌ ꢍꢌ ꢎꢏꢉ ꢀꢌ ꢍ ꢐꢏꢉ ꢑꢒꢓ ꢆ ꢔꢀ ꢀ ꢓ ꢒꢀ  
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006  
Terminal Functions  
CONDITIONS  
WHEN  
SIGNAL IS Z TYPE  
TERMINAL  
†
DESCRIPTION  
TYPE  
NAME  
QTY  
‡
PRIMARY-BUS INTERFACE  
D31−D0  
A23−A0  
32  
24  
I/O/Z 32-bit data port  
S
S
H
H
R
R
O/Z  
O/Z  
O/Z  
I
24-bit address port  
Read/write. R/W is high when a read is performed and low when a write is performed  
over the parallel interface.  
R/W  
STRB  
RDY  
1
1
1
S
S
H
H
R
External-access strobe  
Ready. RDY indicates that the external device is prepared for a transaction  
completion.  
Hold. When HOLD is a logic low, any ongoing transaction is completed. A23−A0,  
D31−D0, STRB, and R/W are placed in the high-impedance state and all transac-  
tions over the primary-bus interface are held until HOLD becomes a logic high or until  
the NOHOLD bit of the primary-bus-control register is set.  
HOLD  
1
1
I
Hold acknowledge. HOLDA is generated in response to a logic low on HOLD. HOLDA  
indicates that A23−A0, D31−D0, STRB, and R/W are in the high-impedance state  
and that all transactions over the bus are held. HOLDA is high in response to a logic  
high of HOLD or the NOHOLD bit of the primary-bus-control register is set.  
HOLDA  
O/Z  
S
CONTROL SIGNALS  
Reset. When RESET is a logic low, the device is in the reset condition. When RESET  
becomes a logic high, execution begins from the location specified by the reset vector.  
RESET  
1
4
1
1
I
INT3−INT0  
IACK  
I
O/Z  
I
External interrupts  
Interrupt acknowledge. IACK is generated by the IACK instruction. IACK can be used  
to indicate the beginning or the end of an interrupt-service routine.  
S
MCBL/MP  
Microcomputer boot-loader/microprocessor mode-select  
Shutdown high impedance. When active, SHZ shuts down the device and places all  
pins in the high-impedance state. SHZ is used for board-level testing to ensure that  
no dual-drive conditions occur. CAUTION: A low on SHZ corrupts the device memory  
and register contents. Reset the device with SHZ high to restore it to a known  
operating condition.  
SHZ  
1
2
I
External flags. XF1 and XF0 are used as general-purpose I/Os or to support  
interlocked processor instruction.  
XF1, XF0  
I/O/Z  
S
R
SERIAL PORT 0 SIGNALS  
CLKR0  
CLKX0  
1
1
I/O/Z Serial port 0 receive clock. CLKR0 is the serial shift clock for the serial port 0 receiver.  
S
S
R
R
Serial port 0 transmit clock. CLKX0 is the serial shift clock for the serial port 0  
I/O/Z  
transmitter.  
DR0  
DX0  
1
1
I/O/Z Data-receive. Serial port 0 receives serial data on DR0.  
S
S
R
R
I/O/Z Data-transmit output. Serial port 0 transmits serial data on DX0.  
Frame-synchronization pulse for receive. The FSR0 pulse initiates the data-receive  
process using DR0.  
FSR0  
FSX0  
1
1
I/O/Z  
S
S
R
R
Frame-synchronization pulse for transmit. The FSX0 pulse initiates the data-transmit  
process using DX0.  
I/O/Z  
TIMER SIGNALS  
Timer clock 0. As an input, TCLK0 is used by timer 0 to count external pulses. As an  
output, TCLK0 outputs pulses generated by timer 0.  
TCLK0  
TCLK1  
1
1
I/O/Z  
S
S
Timer clock 1. As an input, TCLK0 is used by timer 1 to count external pulses. As an  
output, TCLK1 outputs pulses generated by timer 1.  
I/O/Z  
†
‡
I = input, O = output, Z = high-impedance state  
S = SHZ active, H = HOLD active, R = RESET active  
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
Not Recommended for New Designs  
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈ ꢀꢁꢂ ꢃ ꢄ ꢅ ꢉꢆ ꢃ ꢇꢈ ꢀ ꢁꢊ ꢃꢄ ꢅ ꢉ ꢆꢃꢇ  
ꢋ ꢌꢍ ꢌꢎꢏ ꢉ ꢀꢌ ꢍꢐ ꢏ ꢉ ꢑ ꢒꢓ ꢆꢔ ꢀꢀ ꢓꢒ ꢀ  
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006  
Terminal Functions (Continued)  
CONDITIONS  
WHEN  
SIGNAL IS Z TYPE  
TERMINAL  
NAME  
†
DESCRIPTION  
TYPE  
QTY  
‡
SUPPLY AND OSCILLATOR SIGNALS  
H1  
H3  
1
1
O/Z  
O/Z  
External H1 clock. H1 has a period equal to twice CLKIN.  
External H3 clock. H3 has a period equal to twice CLKIN.  
5-V supply for ’C31 devices and 3.3-V supply for ’LC31 devices. All must be  
S
S
V
V
20  
25  
1
I
I
DD  
§
connected to a common supply plane.  
Ground. All grounds must be connected to a common ground plane.  
SS  
Output from the internal-crystal oscillator. If a crystal is not used, X1 should be left  
unconnected.  
X1  
O
I
X2/CLKIN  
1
Internal-oscillator input from a crystal or a clock  
RESERVED  
EMU2−EMU0  
EMU3  
3
1
I
Reserved for emulation. Use pullup resistors to V  
Reserved for emulation  
DD  
O/Z  
S
†
‡
§
I = input, O = output, Z = high-impedance state  
S = SHZ active, H = HOLD active, R = RESET active  
Recommended decoupling capacitor value is 0.1 µF.  
Follow the connections specified for the reserved pins. Use 18-kΩ−22-kΩ pullup resistors for best results. All V  
to a common supply plane, and all ground pins must be connected to a common ground plane.  
supply pins must be connected  
DD  
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
Not Recommended for New Designs  
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢉꢆ ꢃ ꢇꢈ ꢀꢁ ꢊ ꢃꢄ ꢅꢉ ꢆꢃ ꢇ  
ꢋꢌ ꢍꢌ ꢎꢏꢉ ꢀꢌ ꢍ ꢐꢏꢉ ꢑꢒꢓ ꢆ ꢔꢀ ꢀ ꢓ ꢒꢀ  
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006  
functional block diagram  
RAM  
RAM  
Cache  
(64 × 32)  
Block 0  
Block 1  
Boot  
Loader  
(1K × 32)  
(1K × 32)  
32  
24  
32  
24  
32  
32  
24  
24  
PDATA Bus  
PADDR Bus  
RDY  
HOLD  
DDATA Bus  
HOLDA  
STRB  
DADDR1 Bus  
R /W  
DADDR2 Bus  
D31−D0  
A23 −A0  
DMADATA Bus  
DMAADDR Bus  
32  
24  
24  
32  
32  
24  
24  
DMA Controller  
Serial Port 0  
Serial-Port-Control  
Register  
FSX0  
DX0  
Global-Control  
Register  
MUX  
CLKX0  
FSR0  
DR0  
Receive/Transmit  
IR  
(R /X) Timer Register  
Source-Address  
Register  
PC  
CPU1  
CPU2  
REG1  
REG2  
RESET  
Data-Transmit  
Register  
CLKR0  
INT(3 −0)  
IACK  
Destination-  
Address  
Register  
Data-Receive  
Register  
MCBL /MP  
XF(1,0)  
Transfer-  
Counter  
Register  
V
(19 −0)  
(24 −0)  
DD  
V
32  
32  
40  
40  
SS  
32-Bit  
Barrel  
Shifter  
Multiplier  
Timer 0  
Global-Control  
Register  
ALU  
40  
40  
X1  
X2 /CLKIN  
H1  
TCLK0  
Timer-Period  
Register  
40  
40  
40  
Extended-  
Precision  
Registers  
(R7−R0)  
40  
32  
H3  
EMU(3 −0)  
Timer-Counter  
Register  
Timer 1  
DISP0, IR0, IR1  
Global-Control  
Register  
ARAU0  
ARAU1  
BK  
TCLK1  
Timer-Period  
Register  
24  
24  
Timer-Counter  
Register  
24  
24  
Auxiliary  
Registers  
(AR0 −AR7)  
32  
32  
Port Control  
32  
32  
STRB-Control  
Register  
32  
32  
Other  
Registers  
(12)  
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
Not Recommended for New Designs  
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈ ꢀꢁꢂ ꢃ ꢄ ꢅ ꢉꢆ ꢃ ꢇꢈ ꢀ ꢁꢊ ꢃꢄ ꢅ ꢉ ꢆꢃꢇ  
ꢋ ꢌꢍ ꢌꢎꢏ ꢉ ꢀꢌ ꢍꢐ ꢏ ꢉ ꢑ ꢒꢓ ꢆꢔ ꢀꢀ ꢓꢒ ꢀ  
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006  
†
memory map  
0h  
0h  
Reset, Interrupt, Trap Vector, and  
Reserved Locations (64)  
(External STRB Active)  
03Fh  
040h  
Reserved for Boot-Loader  
Operations  
FFFh  
1000h  
Boot 1  
External  
STRB Active  
External  
STRB  
(8M Words − 64 Words)  
Active  
(8M Words −  
4K Words)  
400000h  
Boot 2  
7FFFFFh  
800000h  
7FFFFFh  
800000h  
Reserved  
Reserved  
(32K Words)  
(32K Words)  
807FFFh  
808000h  
807FFFh  
808000h  
Peripheral Bus  
Memory-Mapped Registers  
(6K Words Internal)  
Peripheral Bus  
Memory-Mapped Registers  
(6K Words Internal)  
8097FFh  
809800h  
8097FFh  
809800h  
RAM Block 0  
(1K Words Internal)  
RAM Block 0  
(1K Words Internal)  
809BFFh  
809C00h  
809BFFh  
809C00h  
RAM Block 1  
(1K Words − 63 Words Internal)  
RAM Block 1  
(1K Words Internal)  
809FC0h  
809FC1h  
User-Program Interrupt  
and Trap Branches  
(63 Words Internal)  
809FFFh  
80A000h  
809FFFh  
80A000h  
External  
External  
STRB Active  
(8M Words − 40K Words)  
STRB Active  
(8M Words −  
40K Words)  
Boot 3  
FFF000h  
FFFFFFh  
FFFFFFh  
(b) Microcomputer/Boot-Loader Mode  
(a) Microprocessor Mode  
†
Figure 1 depicts the memory map for the SMJ320C31. See the TMS320C3x Users Guide (literature number SPRU031) for a detailed description  
of this memory mapping.  
Figure 1. SMJ320C31 Memory Map  
10  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
Not Recommended for New Designs  
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢉꢆ ꢃ ꢇꢈ ꢀꢁ ꢊ ꢃꢄ ꢅꢉ ꢆꢃ ꢇ  
ꢋꢌ ꢍꢌ ꢎꢏꢉ ꢀꢌ ꢍ ꢐꢏꢉ ꢑꢒꢓ ꢆ ꢔꢀ ꢀ ꢓ ꢒꢀ  
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006  
memory map (continued)  
00h  
809FC1h  
809FC2h  
809FC3h  
809FC4h  
809FC5h  
Reset  
INT0  
INT1  
01h  
02h  
INT0  
INT1  
INT2  
INT2  
INT3  
03h  
04h  
INT3  
XINT0  
RINT0  
Reserved  
TINT0  
TINT1  
DINT  
05h  
06h  
XINT0  
RINT0  
809FC6h  
07h  
08h  
809FC7h  
809FC8h  
Reserved  
TINT0  
09h  
809FC9h  
809FCAh  
0Ah  
0Bh  
TINT1  
809FCBh  
DINT  
0Ch  
1Fh  
809FCCh  
809FDFh  
Reserved  
TRAP 0  
Reserved  
TRAP 0  
809FE0h  
20h  
3Bh  
TRAP 27  
809FFBh  
TRAP 27  
Reserved  
3Ch  
3Fh  
809FFCh  
809FFFh  
Reserved  
(a) Microprocessor Mode  
(b) Microcomputer/Boot-Loader Mode  
Figure 2. Reset, Interrupt, and Trap Vector/Branches Memory-Map Locations  
11  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
Not Recommended for New Designs  
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈ ꢀꢁꢂ ꢃ ꢄ ꢅ ꢉꢆ ꢃ ꢇꢈ ꢀ ꢁꢊ ꢃꢄ ꢅ ꢉ ꢆꢃꢇ  
ꢋ ꢌꢍ ꢌꢎꢏ ꢉ ꢀꢌ ꢍꢐ ꢏ ꢉ ꢑ ꢒꢓ ꢆꢔ ꢀꢀ ꢓꢒ ꢀ  
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006  
memory map (continued)  
808000h  
808004h  
808006h  
808008h  
808020h  
808024h  
808028h  
808030h  
808034h  
808038h  
808040h  
DMA Global Control  
DMA Source Address  
DMA Destination Address  
DMA Transfer Counter  
Timer 0 Global Control  
Timer 0 Counter  
Timer 0 Period Register  
Timer 1 Global Control  
Timer 1 Counter  
Timer 1 Period Register  
Serial Global Control  
808042h  
808043h  
808044h  
808045h  
808046h  
FSX/DX/CLKX Serial Port Control  
FSR/DR/CLKR Serial Port Control  
Serial R/X Timer Control  
Serial R/X Timer Counter  
Serial R/X Timer Period Register  
808048h  
80804Ch  
808064h  
Data-Transmit  
Data-Receive  
Primary-Bus Control  
†
Shading denotes reserved address locations  
†
Figure 3. Peripheral Bus Memory-Mapped Registers  
12  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
Not Recommended for New Designs  
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢉꢆ ꢃ ꢇꢈ ꢀꢁ ꢊ ꢃꢄ ꢅꢉ ꢆꢃ ꢇ  
ꢋꢌ ꢍꢌ ꢎꢏꢉ ꢀꢌ ꢍ ꢐꢏꢉ ꢑꢒꢓ ꢆ ꢔꢀ ꢀ ꢓ ꢒꢀ  
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006  
†
absolute maximum ratings over specified temperature range (unless otherwise noted)  
’C31  
’LC31  
Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V  
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V  
Output voltage, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V  
. . . . . . . . . . −0.3 V to 5 V  
. . . . . . . . . . −0.3 V to 5 V  
. . . . . . . . . . −0.3 V to 5 V  
Continuous power dissipation (worst case) (see Note 2) . . . . . . . . . . . . . . . . . . 1.7 W  
(for SMJ320C31-33)  
. . . . . . . . . . . . . . 850 mW  
(for SMJ320LC31-33)  
Operating case temperature, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C  
Storage temperature, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 65°C to 150°C  
. . . . . . − −55°C to 125°C  
. . . . . . . − 65°C to 150°C  
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTES: 1. All voltage values are with respect to V  
.
SS  
2. Actual operating power is less. This value was obtained under specially produced worst-case test conditions for the TMS320C31-33  
and the TMS320LC31-33, which are not sustained during normal device operation. These conditions consist of continuous parallel  
writes of a checkerboard pattern to both primary and extension buses at the maximum rate possible. See normal (I ) current  
CC  
specification in the electrical characteristics table and also read Calculation of TMS320C30 Power Dissipation Application Report  
(literature number SPRA020).  
recommended operating conditions (see Note 3)  
’C31  
NOM  
5
’LC31  
NOM  
3.3  
UNIT  
MIN  
MAX  
MIN  
MAX  
V
V
Supply voltage (DV , etc.)  
DD  
4.75  
5.25  
3.13  
3.47  
V
V
DD  
Supply voltage (CV , etc.)  
SS  
0
0
SS  
High-level input voltage (except RESET)  
High-level input voltage (RESET)  
Low-level input voltage  
2.1  
2.2  
V
V
+ 0.3*  
1.8  
2.2  
V
V
+ 0.3*  
V
DD  
DD  
V
V
IH  
+ 0.3*  
0.8  
+ 0.3*  
0.6  
V
DD  
DD  
− 0.3*  
− 0.3*  
V
IL  
I
I
High-level output current  
− 300  
2
− 300  
2
µA  
mA  
OH  
Low-level output current  
OL  
’320C31-40  
−55  
−55  
−55  
125  
125  
105  
’320C31-50  
’320C31-60  
’320LC31-40  
T
C
Operating case temperature  
°C  
−55  
2.5  
125  
V
TH  
High-level input voltage for CLKIN  
3.0  
V
DD  
+ 0.3*  
V
+ 0.3*  
V
DD  
* This parameter is not production tested.  
NOTE 3: All voltage values are with respect to V . All input and output voltage levels are TTL-compatible. CLKIN can be driven by a CMOS  
SS  
clock.  
13  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
Not Recommended for New Designs  
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈ ꢀꢁꢂ ꢃ ꢄ ꢅ ꢉꢆ ꢃ ꢇꢈ ꢀ ꢁꢊ ꢃꢄ ꢅ ꢉ ꢆꢃꢇ  
ꢋ ꢌꢍ ꢌꢎꢏ ꢉ ꢀꢌ ꢍꢐ ꢏ ꢉ ꢑ ꢒꢓ ꢆꢔ ꢀꢀ ꢓꢒ ꢀ  
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006  
electrical characteristics over recommended ranges of supply voltage (unless otherwise noted)  
†
(see Note 3)  
’C31  
’LC31  
PARAMETER  
TEST CONDITIONS  
UNIT  
‡
‡
MIN TYP  
MAX  
MIN TYP  
MAX  
V
V
High-level output voltage  
Low-level output voltage  
High-impedance current  
Input current  
V
V
V
= MIN, I  
= MIN, I  
= MAX  
= MAX  
= MAX  
2.4  
3
2
V
V
OH  
DD  
DD  
DD  
OH  
0.3  
0.6  
+ 20  
+ 10  
0.4  
+ 20  
+ 10  
OL  
OH  
I
I
− 20  
− 10  
− 20  
− 10  
µA  
µA  
Z
V = V  
I SS  
to V  
DD  
I
Input current (with internal  
pullup)  
§
I
IP  
Inputs with internal pullups  
− 600  
20 − 600  
10  
µA  
’C31-40  
’LC31-40  
f = 40 MHz  
160  
400  
150  
20  
300  
x
T
V
= 25°C,  
A
¶#  
I
I
Supply current  
mA  
CC  
f = 50 MHz ’C31-50  
200  
225  
50  
425  
475  
= MAX  
x
DD  
f = 60 MHz ’C31-60  
x
Supply current  
Standby,  
All inputs except CLKIN  
CLKIN  
IDLE2  
Clocks shut off  
µA  
DD  
15*  
25  
15*  
25  
Input  
capacitance  
C
C
pF  
pF  
i
Output capacitance  
20*  
20*  
o
†
‡
§
All input and output voltage levels are TTL compatible.  
For ’C31, all typical values are at V = 5 V, T = 25°C. For ’LC31, all typical values are at V  
= 3.3 V, T = 25°C.  
DD DD  
A
A
Pins with internal pullup devices: INT3−INT0, MCBL/MP.  
Actual operating current is less than this maximum value. This value was obtained under specially produced worst-case test conditions, which  
are not sustained during normal device operation. These conditions consist of continuous parallel writes of a checkerboard pattern to both primary  
and expansion buses at the maximum rate possible. See Calculation of TMS320C30 Power Dissipation Application Report (literature number  
SPRA020).  
#
f is the input clock frequency.  
x
* This parameter is not production tested.  
NOTE 3: All voltage values are with respect to V . All input and output voltage levels are TTL-compatible. CLKIN can be driven by a CMOS  
SS  
clock.  
14  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
Not Recommended for New Designs  
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢉꢆ ꢃ ꢇꢈ ꢀꢁ ꢊ ꢃꢄ ꢅꢉ ꢆꢃ ꢇ  
ꢋꢌ ꢍꢌ ꢎꢏꢉ ꢀꢌ ꢍ ꢐꢏꢉ ꢑꢒꢓ ꢆ ꢔꢀ ꢀ ꢓ ꢒꢀ  
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006  
PARAMETER MEASUREMENT INFORMATION  
I
OL  
Output  
Under  
Test  
Tester Pin  
Electronics  
V
Load  
C
T
I
OH  
Where:  
I
I
V
= 2 mA (all outputs)  
= 300 µA (all outputs)  
= Selected to emulate 50-Ω termination (typical value = 1.54 V).  
= 80-pF typical load-circuit capacitance  
OL  
OH  
LOAD  
T
C
Figure 4. SMJ320C31 Test Load Circuit  
signal transition levels for ’C31 (see Figure 5 and Figure 6)  
TTL-level outputs are driven to a minimum logic-high level of 2.4 V and to a maximum logic-low level of 0.6 V.  
Output transition times are specified as follows:  
D
D
For a high-to-low transition on a TTL-compatible output signal, the level at which the output is said to be  
no longer high is 2 V and the level at which the output is said to be low is 1 V.  
For a low-to-high transition, the level at which the output is said to be no longer low is 1 V and the level at  
which the output is said to be high is 2 V.  
2.4 V  
2 V  
1 V  
0.6 V  
Figure 5. TTL-Level Outputs  
Transition times for TTL-compatible inputs are specified as follows:  
D
D
For a high-to-low transition on an input signal, the level at which the input is said to be no longer high is  
2.1 V and the level at which the input is said to be low is 0.8 V.  
For a low-to-high transition on an input signal, the level at which the input is said to be no longer low is  
0.8 V and the level at which the input is said to be high is 2.1 V.  
2.1 V  
0.8 V  
Figure 6. TTL-Level Inputs  
15  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
Not Recommended for New Designs  
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈ ꢀꢁꢂ ꢃ ꢄ ꢅ ꢉꢆ ꢃ ꢇꢈ ꢀ ꢁꢊ ꢃꢄ ꢅ ꢉ ꢆꢃꢇ  
ꢋ ꢌꢍ ꢌꢎꢏ ꢉ ꢀꢌ ꢍꢐ ꢏ ꢉ ꢑ ꢒꢓ ꢆꢔ ꢀꢀ ꢓꢒ ꢀ  
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006  
PARAMETER MEASUREMENT INFORMATION  
I
OL  
Output  
Under  
Test  
Tester Pin  
Electronics  
V
Load  
C
T
I
OH  
Where:  
I
I
V
= 2 mA (all outputs)  
= 300 µA (all outputs)  
= 2.15 V  
OL  
OH  
LOAD  
T
C
= 80-pF typical load-circuit capacitance  
Figure 7. SMJ320LC31 Test Load Circuit  
signal transition levels for ’LC31 (see Figure 8 and Figure 9)  
Outputs are driven to a minimum logic-high level of 2 V and to a maximum logic-low level of 0.4 V. Output  
transition times are specified as follows:  
D
D
For a high-to-low transition on an output signal, the level at which the output is said to be no longer high  
is 2 V and the level at which the output is said to be low is 1 V.  
For a low-to-high transition, the level at which the output is said to be no longer low is 1 V and the level at  
which the output is said to be high is 2 V.  
2 V  
1.8 V  
0.6 V  
0.4 V  
Figure 8. ’LC31 Output Levels  
Transition times for inputs are specified as follows:  
D
D
For a high-to-low transition on an input signal, the level at which the input is said to be no longer high is  
1.8 V and the level at which the input is said to be low is 0.6 V.  
For a low-to-high transition on an input signal, the level at which the input is said to be no longer low is  
0.6 V and the level at which the input is said to be high is 1.8 V.  
1.8 V  
0.6 V  
Figure 9. ’LC31 Input Levels  
16  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
Not Recommended for New Designs  
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢉꢆ ꢃ ꢇꢈ ꢀꢁ ꢊ ꢃꢄ ꢅꢉ ꢆꢃ ꢇ  
ꢋꢌ ꢍꢌ ꢎꢏꢉ ꢀꢌ ꢍ ꢐꢏꢉ ꢑꢒꢓ ꢆ ꢔꢀ ꢀ ꢓ ꢒꢀ  
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006  
PARAMETER MEASUREMENT INFORMATION  
timing parameter symbology  
Timing parameter symbols used herein were created in accordance with JEDEC Standard 100-A. In order to  
shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows,  
unless otherwise noted:  
A
A23−A0  
H
H1 and H3  
ASYNCH  
C
Asynchronous reset signals  
HOLD  
HOLDA  
IACK  
INT  
HOLD  
CLKX0  
HOLDA  
CI  
CLKIN  
IACK  
CLKR  
CONTROL  
D
CLKR0  
INT3−INT0  
Control signals  
RDY  
RW  
RDY  
D31−D0  
R/W  
DR  
DR  
RESET  
S
RESET  
DX  
DX  
STRB  
FS  
FSX/R  
SCK  
SHZ  
TCLK  
XF  
CLKX/R  
FSX  
FSR  
GPI  
FSX0  
SHZ  
FSR0  
TCLK0, TCLK1, or TCLKx  
XF0, XF1, or XFx  
XFx switching from input to output  
General-purpose input  
General-purpose input/output; peripheral pin  
General-purpose output  
GPIO  
GPO  
XFIO  
17  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
Not Recommended for New Designs  
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈ ꢀꢁꢂ ꢃ ꢄ ꢅ ꢉꢆ ꢃ ꢇꢈ ꢀ ꢁꢊ ꢃꢄ ꢅ ꢉ ꢆꢃꢇ  
ꢋ ꢌꢍ ꢌꢎꢏ ꢉ ꢀꢌ ꢍꢐ ꢏ ꢉ ꢑ ꢒꢓ ꢆꢔ ꢀꢀ ꢓꢒ ꢀ  
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006  
timing  
Timing specifications apply to the SMJ320C31 and SMJ320LC31.  
X2/CLKIN, H1, and H3 timing  
The following table defines the timing parameters for the X2/CLKIN, H1, and H3 interface signals.  
timing parameters for X2/CLKIN, H1, H3 (see Figure 10, Figure 11, Figure 12, and Figure 13)  
’C31-40  
’LC31-40  
’C31-50  
’C31-60  
NO.  
UNIT  
MIN  
MAX  
MIN  
MAX  
MIN  
MAX  
1
2
3
4
5
6
7
8
9
t
t
t
t
t
t
t
t
t
Fall time, CLKIN  
5*  
5*  
4*  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
f(CI)  
Pulse duration, CLKIN low t  
= min  
= min  
9
9
7
7
6
6
w(CIL)  
w(CIH)  
r(CI)  
c(CI)  
Pulse duration, CLKIN high t  
Rise time, CLKIN  
c(CI)  
5*  
303  
3
5*  
4*  
303  
3
Cycle time, CLKIN  
25  
20  
303 16.67  
3
c(CI)  
f(H)  
Fall time, H1 and H3  
†
P−5  
†
P−5  
†
P−4  
Pulse duration, H1 and H3 low  
Pulse duration, H1 and H3 high  
Rise time, H1 and H3  
w(HL)  
w(HH)  
r(H)  
†
P−6  
†
P−6  
†
P−5  
3
4
3
4
3
4
Delay time. from H1 low to H3 high or from H3 low to H1  
high  
10  
t
0
0
0
ns  
ns  
d(HL-HH)  
c(H)  
11  
t
Cycle time, H1 and H3  
50  
606  
40  
606  
33.3  
606  
†
P = t  
c(CI)  
* This parameter is not production tested.  
5
4
1
X2/CLKIN  
3
2
Figure 10. Timing for X2/CLKIN  
18  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
Not Recommended for New Designs  
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢃ
ꢇ
ꢈ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢉ
ꢆ
ꢃ
ꢇ
ꢈ
ꢀ
ꢋꢌ ꢍꢌ ꢎꢏꢉ ꢀꢌ ꢍ ꢐꢏꢉ ꢑꢒꢓ ꢆ ꢔꢀ ꢀ ꢓ ꢒꢀ  
ꢁ
ꢊ
ꢃ
ꢄ
ꢅ
ꢉ
ꢆ
ꢃ
ꢇ
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006  
X2/CLKIN, H1, and H3 timing (continued)  
11  
9
6
H1  
8
7
10  
10  
H3  
9
6
7
8
11  
Figure 11. Timing for H1 and H3  
8
7
6
5
4
3
2
1
0
8
7
6
4.5 V Band  
5
4
3
2
1
0
5.5 V Band  
−60  
−40  
−20  
0
20  
40  
60  
80  
100  
120  
140  
Temperature  
Figure 12. SMJ320C31 CLKIN to H1/H3 as a Function of Temperature  
(Typical)  
19  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
Not Recommended for New Designs  
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈ ꢀꢁꢂ ꢃ ꢄ ꢅ ꢉꢆ ꢃ ꢇꢈ ꢀ ꢁꢊ ꢃꢄ ꢅ ꢉ ꢆꢃꢇ  
ꢋ ꢌꢍ ꢌꢎꢏ ꢉ ꢀꢌ ꢍꢐ ꢏ ꢉ ꢑ ꢒꢓ ꢆꢔ ꢀꢀ ꢓꢒ ꢀ  
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006  
X2/CLKIN, H1, and H3 timing (continued)  
12  
12  
10  
10  
2.5 V Band  
8
8
6
6
4
4
3.8 V Band  
2
2
0
0
−60  
−40  
−20  
0
20  
40  
60  
80  
100  
120  
140  
Temperature  
Figure 13. SMJ320LC31 CLKIN to H1/H3 as a Function of Temperature  
(Typical)  
20  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
Not Recommended for New Designs  
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢉꢆ ꢃ ꢇꢈ ꢀꢁ ꢊ ꢃꢄ ꢅꢉ ꢆꢃ ꢇ  
ꢋꢌ ꢍꢌ ꢎꢏꢉ ꢀꢌ ꢍ ꢐꢏꢉ ꢑꢒꢓ ꢆ ꢔꢀ ꢀ ꢓ ꢒꢀ  
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006  
memory read/write timing  
The following table defines memory read/write timing parameters for STRB.  
†
timing parameters for memory (STRB = 0) read/write (see Figure 14 and Figure 15)  
’C31-40  
’LC31-40  
’C31-50  
’C31-60  
NO.  
UNIT  
MIN  
0*  
0*  
0*  
0*  
14  
0
MAX  
MIN MAX  
MIN MAX  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
t
t
t
t
t
t
t
t
t
t
t
Delay time, H1 low to STRB low  
Delay time, H1 low to STRB high  
Delay time, H1 high to R/W low (read)  
Delay time, H1 low to A valid  
6
6
0*  
0*  
0*  
0*  
10  
0
5
5
0*  
0*  
0*  
0*  
9
5
5
6
8
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
d(H1L-SL)  
d(H1L-SH)  
9
7
d(H1H-RWL)R  
d(H1L-A)  
10  
10  
Setup time, D before H1 low (read)  
Hold time, D after H1 low (read)  
Setup time, RDY before H1 high  
Hold time, RDY after H1 high  
su(D-H1L)R  
h(H1L-D)R  
0
8
6
5
su(RDY-H1H)  
h(H1H-RDY)  
d(H1H-RWH)W  
v(H1L-D)W  
h(H1H-D)W  
0
0
0
Delay time, H1 high to R/W high (write)  
Valid time, D after H1 low (write)  
Hold time, D after H1 high (write)  
9
7
6
17  
14  
12  
0
0
0
Delay time, H1 high to A valid on back-to-back  
write cycles (write)  
23  
t
15  
7*  
14  
6*  
10  
6*  
ns  
ns  
d(H1H-A)W  
24  
t
Delay time, RDY from A valid  
d(A-RDY)  
†
See Figure 16 for address bus timing variation with load capacitance greater than typical load-circuit capacitance (C = 80 pF).  
T
* This parameter is not production tested.  
H3  
H1  
12  
13  
STRB  
R/W  
15  
14  
A
D
16  
17  
24  
18  
19  
RDY  
NOTE A: STRB remains low during back-to-back read operations.  
Figure 14. Timing for Memory (STRB = 0) Read  
21  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
Not Recommended for New Designs  
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈ ꢀꢁꢂ ꢃ ꢄ ꢅ ꢉꢆ ꢃ ꢇꢈ ꢀ ꢁꢊ ꢃꢄ ꢅ ꢉ ꢆꢃꢇ  
ꢋ ꢌꢍ ꢌꢎꢏ ꢉ ꢀꢌ ꢍꢐ ꢏ ꢉ ꢑ ꢒꢓ ꢆꢔ ꢀꢀ ꢓꢒ ꢀ  
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006  
memory read/write timing (continued)  
H3  
H1  
13  
12  
STRB  
20  
14  
R/W  
A
15  
23  
21  
22  
D
19  
18  
RDY  
Figure 15. Timing for Memory (STRB = 0) Write  
Address-Bus Timing Variation Load Capacitance  
4.00  
3.50  
3.00  
2.50  
2.00  
1.50  
1.00  
0.50  
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100  
Change in Load Capacitance, pF  
NOTE A: 30 pF/ns slope  
Figure 16. Address-Bus Timing Variation With Load Capacitance (see Note A)  
22  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
Not Recommended for New Designs  
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢉꢆ ꢃ ꢇꢈ ꢀꢁ ꢊ ꢃꢄ ꢅꢉ ꢆꢃ ꢇ  
ꢋꢌ ꢍꢌ ꢎꢏꢉ ꢀꢌ ꢍ ꢐꢏꢉ ꢑꢒꢓ ꢆ ꢔꢀ ꢀ ꢓ ꢒꢀ  
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006  
XF0 and XF1 timing when executing LDFI or LDII  
The following table defines the timing parameters for XF0 and XF1 during execution of LDFI or LDII.  
timing for XF0 and XF1 when executing LDFI or LDII for SMJ320C31 (see Figure 17)  
’C31-40  
MIN MAX MIN MAX MIN MAX MIN MAX  
13 13 12 11  
’LC31-40  
’C31-50  
’C31-60  
NO.  
UNIT  
25  
26  
27  
t
t
t
Delay time, H3 high to XF0 low  
Setup time, XF1 before H1 low  
Hold time, XF1 after H1 low  
ns  
ns  
ns  
d(H3H-XF0L)  
su(XF1-H1L)  
h(H1L-XF1)  
9
0
10  
0
8
0
8
0
Fetch  
LDFI or LDII  
Decode  
Read  
Execute  
H3  
H1  
STRB  
R/W  
A
D
RDY  
25  
XF0 Pin  
26  
27  
XF1 Pin  
Figure 17. Timing for XF0 and XF1 When Executing LDFI or LDII  
23  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
Not Recommended for New Designs  
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢃ
ꢇ
ꢈ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢉ
ꢆ
ꢃ
ꢇ
ꢈ
ꢀ
ꢋ ꢌꢍ ꢌꢎꢏ ꢉ ꢀꢌ ꢍꢐ ꢏ ꢉ ꢑ ꢒꢓ ꢆꢔ ꢀꢀ ꢓꢒ ꢀ  
ꢁ
ꢊ
ꢃꢄ  
ꢅ
ꢉ
ꢆ
ꢃ
ꢇ
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006  
†
XF0 timing when executing STFI and STII  
The following table defines the timing parameters for the XF0 pin during execution of STFI or STII.  
timing for XF0 when executing STFI or STII (see Figure 18)  
’C31-40  
’C31-50  
’C31-60  
’LC31-40  
MIN MAX MIN MAX MIN MAX  
13 12 11  
NO.  
UNIT  
28  
t
Delay time, H3 high to XF0 high  
ns  
d(H3H-XF0H)  
†
XF0 is always set high at the beginning of the execute phase of the interlock-store instruction. When no pipeline conflicts occur, the address of  
the store is also driven at the beginning of the execute phase of the interlock-store instruction. However, if a pipeline conflict prevents the store  
from executing, the address of the store will not be driven until the store can execute.  
Fetch  
STFI or STII  
Decode  
Read  
Execute  
H3  
H1  
STRB  
R/W  
A
D
28  
RDY  
XF0 Pin  
Figure 18. Timing for XF0 When Executing an STFI or STII  
24  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
Not Recommended for New Designs  
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢉꢆ ꢃ ꢇꢈ ꢀꢁ ꢊ ꢃꢄ ꢅꢉ ꢆꢃ ꢇ  
ꢋꢌ ꢍꢌ ꢎꢏꢉ ꢀꢌ ꢍ ꢐꢏꢉ ꢑꢒꢓ ꢆ ꢔꢀ ꢀ ꢓ ꢒꢀ  
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006  
XF0 and XF1 timing when executing SIGI  
The following table defines the timing parameters for the XF0 and XF1 pins during execution of SIGI.  
timing for XF0 and XF1 when executing SIGI for SMJ320C31 (see Figure 19)  
’C31-40  
’LC31-40  
’C31-50  
’C31-60  
NO.  
UNIT  
MIN MAX MIN MAX MIN MAX MIN MAX  
29  
30  
31  
32  
t
t
t
t
Delay time, H3 high to XF0 low  
Delay time, H3 high to XF0 high  
Setup time, XF1 before H1 low  
Hold time, XF1 after H1 low  
13  
13  
13  
13  
12  
12  
11  
11  
ns  
ns  
ns  
ns  
d(H3H-XF0L)  
d(H3H-XF0H)  
su(XF1-H1L)  
h(H1L-XF1)  
9
0
10  
0
8
0
8
0
Fetch  
SIGI  
Decode  
Read  
Execute  
H3  
H1  
XF0  
XF1  
29  
30  
31  
32  
Figure 19. Timing for XF0 and XF1 When Executing SIGI  
25  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
Not Recommended for New Designs  
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈ ꢀꢁꢂ ꢃ ꢄ ꢅ ꢉꢆ ꢃ ꢇꢈ ꢀ ꢁꢊ ꢃꢄ ꢅ ꢉ ꢆꢃꢇ  
ꢋ ꢌꢍ ꢌꢎꢏ ꢉ ꢀꢌ ꢍꢐ ꢏ ꢉ ꢑ ꢒꢓ ꢆꢔ ꢀꢀ ꢓꢒ ꢀ  
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006  
loading when XF is configured as an output  
The following table defines the timing parameter for loading the XF register when the XFx pin is configured as  
an output.  
timing for loading the XF register when configured as an output pin (see Figure 20)  
’C31-40  
’C31-50  
’C31-60  
’LC31-40  
MIN MAX MIN MAX MIN MAX  
13 12 11  
NO.  
UNIT  
33  
t
Valid time, H3 high to XFx  
ns  
v(H3H-XF)  
Fetch Load  
Instruction  
Decode  
Read  
Execute  
H3  
H1  
OUTXFx Bit  
(see Note A)  
1 or 0  
33  
XFx Pin  
NOTE A: OUTXFx represents either bit 2 or 6 of the IOF register.  
Figure 20. Timing for Loading XF Register When Configured as an Output Pin  
26  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
Not Recommended for New Designs  
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢉꢆ ꢃ ꢇꢈ ꢀꢁ ꢊ ꢃꢄ ꢅꢉ ꢆꢃ ꢇ  
ꢋꢌ ꢍꢌ ꢎꢏꢉ ꢀꢌ ꢍ ꢐꢏꢉ ꢑꢒꢓ ꢆ ꢔꢀ ꢀ ꢓ ꢒꢀ  
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006  
changing XFx from an output to an input  
The following table defines the timing parameters for changing the XFx pin from an output pin to an input pin.  
timing of XFx changing from output to input mode for SMJ320C31 (see Figure 21)  
’C31-40  
’LC31-40  
’C31-50  
’C31-60  
NO.  
UNIT  
MIN  
MAX  
13*  
MIN  
MAX  
13*  
MIN  
MAX  
12*  
MIN  
MAX  
11*  
34  
35  
36  
t
t
t
Hold time, XFx after H3 high  
Setup time, XFx before H1 low  
Hold time, XFx after H1 low  
ns  
ns  
ns  
h(H3H-XF)  
su(XF-H1L)  
h(H1L-XF)  
9
0
10  
0
8
0
8
0
* This parameter is not production tested.  
Buffers Go  
From Output  
to Output  
Synchronizer  
Delay  
Execute  
Load of IOF  
Value on Pin  
Seen in IOF  
H3  
H1  
35  
36  
I/OxFx Bit  
(see Note A)  
34  
XFx Pin  
Output  
INXFx Bit  
Data  
(see Note A)  
Sampled  
Data  
Seen  
NOTE A: I/OxFx represents either bit 1 or bit 5 of the IOF register, and INXFx represents either bit 3 or bit 7 of the IOF register.  
Figure 21. Timing for Change of XFx From Output to Input Mode  
27  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
Not Recommended for New Designs  
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈ ꢀꢁꢂ ꢃ ꢄ ꢅ ꢉꢆ ꢃ ꢇꢈ ꢀ ꢁꢊ ꢃꢄ ꢅ ꢉ ꢆꢃꢇ  
ꢋ ꢌꢍ ꢌꢎꢏ ꢉ ꢀꢌ ꢍꢐ ꢏ ꢉ ꢑ ꢒꢓ ꢆꢔ ꢀꢀ ꢓꢒ ꢀ  
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006  
changing XFx from an input to an output  
The following table defines the timing parameter for changing the XFx pin from an input pin to an output pin.  
timing for XFx changing from input to output mode (see Figure 22)  
’C31-40  
’C31-50  
’C31-60  
’LC31-40  
MIN MAX MIN MAX MIN MAX  
17 17 16  
NO.  
UNIT  
37  
t
Delay time, H3 high to XFx switching from input to output  
ns  
d(H3H-XFIO)  
Execution of  
Load of IOF  
H3  
H1  
I/OxFx  
Bit  
(see Note A)  
37  
XFx Pin  
NOTE A: I/OxFx represents either bit 1 or bit 5 of the IOF register.  
Figure 22. Timing for Change of XFx From Input to Output Mode  
reset timing  
RESET is an asynchronous input that can be asserted at any time during a clock cycle. If the specified timings  
are met, the exact sequence shown in Figure 23 occurs; otherwise, an additional delay of one clock cycle is  
possible.  
The asynchronous reset signals include XF0/1, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, and TCLK0/1.  
Resetting the device initializes the primary- and expansion-bus control registers to seven software wait states  
and therefore results in slow external accesses until these registers are initialized.  
HOLD is an asynchronous input and can be asserted during reset.  
28  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
Not Recommended for New Designs  
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢉꢆ ꢃ ꢇꢈ ꢀꢁ ꢊ ꢃꢄ ꢅꢉ ꢆꢃ ꢇ  
ꢋꢌ ꢍꢌ ꢎꢏꢉ ꢀꢌ ꢍ ꢐꢏꢉ ꢑꢒꢓ ꢆ ꢔꢀ ꢀ ꢓ ꢒꢀ  
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006  
RESET timing (see Figure 23)  
’C31-40  
MIN MAX  
’LC31-40  
’C31-50  
’C31-60  
NO.  
UNIT  
ns  
MIN MAX  
MIN MAX  
MIN MAX  
Setup time, RESET before  
CLKIN low  
†
†
†
†
38  
39  
40  
t
t
t
10  
2
P *  
10  
2
P *  
10  
2
P *  
7
2
2
P *  
su(RESET-CIL)  
d(CLKINH-H1H)  
d(CLKINH-H1L)  
Delay time, CLKIN high to  
H1 high (see Note 4)  
14  
14  
14  
14  
10  
10  
10  
10  
ns  
Delay time, CLKIN high to  
H1 low (see Note 4)  
2
2
2
ns  
Setup time, RESET high  
before H1 low and after ten  
H1 clock cycles  
41  
t
9
9
7
6
ns  
su(RESETH-H1L)  
Delay time, CLKIN high to  
H3 low (see Note 4)  
42  
43  
44  
45  
46  
47  
48  
t
t
t
t
t
t
t
2
2
14  
14  
15*  
9*  
2
2
14  
14  
13*  
9*  
2
2
10  
10  
12*  
8*  
2
2
10  
10  
11*  
7*  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
d(CLKINH-H3L)  
d(CLKINH-H3H)  
dis(H1H-DZ)  
Delay time, CLKIN high to  
H3 high (see Note 4)  
Disable time, H1 high to D  
(high impedance)  
Disable time, H3 high to A  
(high impedance)  
dis(H3H-AZ)  
Delay time, H3 high to  
control signals high  
9*  
9*  
8*  
7*  
d(H3H-CONTROLH)  
d(H1H-RWH)  
Delay time, H1 high to R/W  
high  
9*  
9*  
8*  
7*  
Delay time, H1 high to IACK  
high  
9*  
9*  
8*  
7*  
d(H1H-IACKH)  
Disable time, RESET low to  
asynchronous reset signals  
disabled (high impedance)  
49  
t
21*  
21*  
17*  
14*  
ns  
dis(RESETL-ASYNCH)  
†
P = t  
c(CI)  
* This parameter is not production tested.  
NOTE 4: See Figure 12 and Figure 13 for typical temperature dependence.  
29  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
Not Recommended for New Designs  
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈ ꢀꢁꢂ ꢃ ꢄ ꢅ ꢉꢆ ꢃ ꢇꢈ ꢀ ꢁꢊ ꢃꢄ ꢅ ꢉ ꢆꢃꢇ  
ꢋ ꢌꢍ ꢌꢎꢏ ꢉ ꢀꢌ ꢍꢐ ꢏ ꢉ ꢑ ꢒꢓ ꢆꢔ ꢀꢀ ꢓꢒ ꢀ  
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006  
RESET timing (continued)  
CLKIN  
38  
RESET  
(see Notes A and B)  
39  
40  
41  
H1  
42  
H3  
Ten H1 Clock Cycles  
44  
D
(see Note C)  
45  
46  
43  
A
(see Note C)  
Control Signals  
(see Note D)  
47  
48  
SMJ320C31 R/W  
(see Note E)  
IACK  
49  
Asynchronous  
Reset Signals  
(see Note A)  
NOTES: A. Asynchronous reset signals include XF0/1, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, and TCLK0/1.  
B. RESET is an asynchronous input and can be asserted at any point during a clock cycle. If the specified timings are met, the exact  
sequence shown occurs; otherwise, an additional delay of one clock cycle is possible.  
C. In microprocessor mode, the reset vector is fetched twice, with seven software wait states each time. In microcomputer mode, the  
reset vector is fetched twice, with no software wait states.  
D. Control signals include STRB.  
E. The R/W outputs are placed in a high-impedance state during reset and can be provided with a resistive pullup, nominally  
18−22 kΩ, if undesirable spurious writes are caused when these outputs go low.  
Figure 23. Timing for RESET  
30  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
Not Recommended for New Designs  
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢉꢆ ꢃ ꢇꢈ ꢀꢁ ꢊ ꢃꢄ ꢅꢉ ꢆꢃ ꢇ  
ꢋꢌ ꢍꢌ ꢎꢏꢉ ꢀꢌ ꢍ ꢐꢏꢉ ꢑꢒꢓ ꢆ ꢔꢀ ꢀ ꢓ ꢒꢀ  
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006  
interrupt response timing  
The following table defines the timing parameters for the INT signals.  
timing for INT3−INT0 response (see Figure 24)  
’C31-40  
’LC31-40  
’C31-50  
MIN MAX  
’C31-60  
MIN MAX  
NO.  
50  
UNIT  
ns  
MIN  
MAX  
MIN  
MAX  
t
t
Setup time, INT3−INT0 before H1 low  
13  
15  
11  
8
su(INT-H1L)  
Pulse duration, interrupt to ensure  
only one interrupt  
†
†
†
2P *  
†
2P *  
51  
P
2P *  
P
2P *  
P
P
ns  
w(INT)  
†
P = t  
c(H)  
* This parameter is not production tested.  
The interrupt (INT) pins are asynchronous inputs that can be asserted at any time during a clock cycle. The  
SMJ320C3x interrupts are level-sensitive, not edge-sensitive. Interrupts are detected on the falling edge of H1.  
Therefore, interrupts must be set up and held to the falling edge of H1 for proper detection. The CPU and DMA  
respond to detected interrupts on instruction-fetch boundaries only.  
For the processor to recognize only one interrupt on a given input, an interrupt pulse must be set up and held  
to:  
D
D
A minimum of one H1 falling edge  
No more than two H1 falling edges  
The SMJ320C3x can accept an interrupt from the same source every two H1 clock cycles.  
If the specified timings are met, the exact sequence shown in Figure 24 occurs; otherwise, an additional delay  
of one clock cycle is possible.  
31  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
Not Recommended for New Designs  
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈ ꢀꢁꢂ ꢃ ꢄ ꢅ ꢉꢆ ꢃ ꢇꢈ ꢀ ꢁꢊ ꢃꢄ ꢅ ꢉ ꢆꢃꢇ  
ꢋ ꢌꢍ ꢌꢎꢏ ꢉ ꢀꢌ ꢍꢐ ꢏ ꢉ ꢑ ꢒꢓ ꢆꢔ ꢀꢀ ꢓꢒ ꢀ  
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006  
timing parameters for INT3−INT0 response (continued)  
Fetch First  
Instruction of  
Service  
Reset or  
Interrupt  
Vector Read  
Routine  
H3  
H1  
50  
INT3 −INT0  
Pin  
51  
INT3 −INT0  
Flag  
ADDR  
Vector Address  
First Instruction Address  
Data  
Figure 24. Timing for INT3−INT0 Response  
32  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
Not Recommended for New Designs  
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢉꢆ ꢃ ꢇꢈ ꢀꢁ ꢊ ꢃꢄ ꢅꢉ ꢆꢃ ꢇ  
ꢋꢌ ꢍꢌ ꢎꢏꢉ ꢀꢌ ꢍ ꢐꢏꢉ ꢑꢒꢓ ꢆ ꢔꢀ ꢀ ꢓ ꢒꢀ  
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006  
interrupt-acknowledge timing  
The IACK output goes active on the first half-cycle (HI rising) of the decode phase of the IACK instruction and  
goes inactive at the first half-cycle (HI rising) of the read phase of the IACK instruction.  
timing for IACK (see Note 5 and Figure 25)  
’C31-40  
’C31-50  
’C31-60  
’LC31-40  
MIN MAX MIN MAX MIN MAX  
NO.  
UNIT  
52  
53  
t
t
Delay time, H1 high to IACK low  
Delay time, H1 high to IACK high  
9
9
7
7
6
6
ns  
ns  
d(H1H-IACKL)  
d(H1H-IACKH)  
NOTE 5: IACK goes active on the first half-cycle (H1 rising) of the decode phase of the IACK instruction and goes inactive at the first half-cycle  
(H1 rising) of the read phase of the IACK instruction. Because of pipeline conflicts, IACK remains low for one cycle even if the decode  
phase of the IACK instruction is extended.  
Decode IACK  
Instruction  
Fetch IACK  
Instruction  
IACK Data  
Read  
H3  
H1  
52  
53  
IACK  
ADDR  
Data  
Figure 25. Timing for IACK  
33  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
Not Recommended for New Designs  
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈ ꢀꢁꢂ ꢃ ꢄ ꢅ ꢉꢆ ꢃ ꢇꢈ ꢀ ꢁꢊ ꢃꢄ ꢅ ꢉ ꢆꢃꢇ  
ꢋ ꢌꢍ ꢌꢎꢏ ꢉ ꢀꢌ ꢍꢐ ꢏ ꢉ ꢑ ꢒꢓ ꢆꢔ ꢀꢀ ꢓꢒ ꢀ  
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006  
serial-port timing for SMJ320C31-40 and SMJ320LC31-40 (see Figure 26 and Figure 27)  
’C31-40  
’LC31-40  
NO.  
UNIT  
MIN  
MAX  
54  
55  
t
t
Delay time, H1 high to internal CLKX/R  
Cycle time, CLKX/R  
13  
ns  
ns  
d(H1H-SCK)  
CLKX/R ext  
CLKX/R int  
CLKX/R ext  
CLKX/R int  
t
x2.6  
x2  
c(H)  
t
c(SCK)  
t
x232  
c(H)  
c(H)  
t
+10  
c(H)  
56  
t
Pulse duration, CLKX/R high/low  
ns  
w(SCK)  
[t  
/2]−5  
[t  
/2]+5  
c(SCK)  
7
c(SCK)  
57  
58  
t
t
Rise time, CLKX/R  
Fall time, CLKX/R  
ns  
ns  
r(SCK)  
7
30  
17  
f(SCK)  
CLKX ext  
CLKX int  
CLKR ext  
CLKR int  
CLKR ext  
CLKR int  
CLKX ext  
CLKX int  
CLKR ext  
CLKR int  
CLKX/R ext  
CLKX/R int  
CLKX ext  
CLKX int  
CLKX ext  
CLKX int  
59  
60  
61  
62  
63  
64  
65  
66  
t
t
t
t
t
t
t
t
Delay time, CLKX to DX valid  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
d(C-DX)  
9
21  
9
Setup time, DR before CLKR low  
Hold time, DR from CLKR low  
su(DR-CLKRL)  
h(CLKRL-DR)  
d(C-FSX)  
0
27  
15  
Delay time, CLKX to internal FSX high/low  
Setup time, FSR before CLKR low  
Hold time, FSX/R input from CLKX/R low  
Setup time, external FSX before CLKX  
9
9
9
0
su(FSR-CLKRL)  
h(SCKL-FS)  
su(FSX-C)  
−[t  
c(H)  
−8]* [t  
/2]−10*  
c(SCK)  
[t  
c(H)  
−21]*  
t
/2*  
c(SCK)  
30*  
Delay time, CLKX to first DX bit, FSX  
precedes CLKX high  
d(CH-DX)V  
18*  
30*  
67  
68  
t
Delay time, FSX to first DX bit, CLKX precedes FSX  
ns  
ns  
d(FSX-DX)V  
d(CH-DXZ)  
Delay time, CLKX high to DX high impedance following last data  
bit  
17  
*
t
* This parameter is not production tested.  
34  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
Not Recommended for New Designs  
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢉꢆ ꢃ ꢇꢈ ꢀꢁ ꢊ ꢃꢄ ꢅꢉ ꢆꢃ ꢇ  
ꢋꢌ ꢍꢌ ꢎꢏꢉ ꢀꢌ ꢍ ꢐꢏꢉ ꢑꢒꢓ ꢆ ꢔꢀ ꢀ ꢓ ꢒꢀ  
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006  
serial-port timing for SMJ320C31-50 (see Figure 26 and Figure 27)  
’C31-50  
NO.  
UNIT  
MIN  
MAX  
54  
55  
t
t
Delay time, H1 high to internal CLKX/R  
Cycle time, CLKX/R  
10  
ns  
d(H1H-SCK)  
CLKX/R ext  
CLKX/R int  
CLKX/R ext  
CLKX/R int  
t
x2.6  
c(H)  
t
ns  
ns  
c(SCK)  
x2  
t
x232  
c(H)  
c(H)  
t
+10  
c(H)  
56  
t
Pulse duration, CLKX/R high/low  
w(SCK)  
[t  
/2]−5  
[t  
/2]+5  
c(SCK)  
6
c(SCK)  
57  
58  
t
t
Rise time, CLKX/R  
Fall time, CLKX/R  
ns  
ns  
r(SCK)  
6
24  
16  
f(SCK)  
CLKX ext  
CLKX int  
CLKR ext  
CLKR int  
CLKR ext  
CLKR int  
CLKX ext  
CLKX int  
CLKR ext  
CLKR int  
CLKX/R ext  
CLKX/R int  
CLKX ext  
CLKX int  
CLKX ext  
CLKX int  
59  
60  
61  
62  
63  
64  
65  
66  
t
t
t
t
t
t
t
t
Delay time, CLKX to DX valid  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
d(C-DX)  
9
17  
7
Setup time, DR before CLKR low  
Hold time, DR from CLKR low  
su(DR-CLKRL)  
h(CLKRL-DR)  
d(C-FSX)  
0
22  
15  
Delay time, CLKX to internal FSX high/low  
Setup time, FSR before CLKR low  
Hold time, FSX/R input from CLKX/R low  
Setup time, external FSX before CLKX  
7
7
7
0
su(FSR-CLKRL)  
h(SCKL-FS)  
su(FSX-C)  
−[t  
c(H)  
−8]* [t  
/2]−10*  
c(SCK)  
−[t  
c(H)  
−21]*  
t
/2*  
c(SCK)  
24*  
Delay time, CLKX to first DX bit, FSX  
precedes CLKX high  
d(CH-DX)V  
14*  
24*  
67  
68  
t
Delay time, FSX to first DX bit, CLKX precedes FSX  
ns  
ns  
d(FSX-DX)V  
d(CH-DXZ)  
Delay time, CLKX high to DX high impedance following last  
data bit  
t
14*  
* This parameter is not production tested.  
35  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
Not Recommended for New Designs  
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈ ꢀꢁꢂ ꢃ ꢄ ꢅ ꢉꢆ ꢃ ꢇꢈ ꢀ ꢁꢊ ꢃꢄ ꢅ ꢉ ꢆꢃꢇ  
ꢋ ꢌꢍ ꢌꢎꢏ ꢉ ꢀꢌ ꢍꢐ ꢏ ꢉ ꢑ ꢒꢓ ꢆꢔ ꢀꢀ ꢓꢒ ꢀ  
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006  
serial-port timing for SMJ320C31-60 (see Figure 26 and Figure 27)  
’C31-60  
NO.  
UNIT  
MIN  
MAX  
54  
55  
t
t
Delay time, H1 high to internal CLKX/R  
Cycle time, CLKX/R  
8
ns  
d(H1H-SCK)  
CLKX/R ext  
CLKX/R int  
CLKX/R ext  
CLKX/R int  
t
x2.6  
c(H)  
t
ns  
ns  
c(SCK)  
x2  
t
x232  
c(H)  
c(H)  
t
+10  
c(H)  
56  
t
Pulse duration, CLKX/R high/low  
w(SCK)  
[t  
/2]−5  
[t  
/2]+5  
c(SCK)  
5
c(SCK)  
57  
58  
t
t
Rise time, CLKX/R  
Fall time, CLKX/R  
ns  
ns  
r(SCK)  
5
20  
15  
f(SCK)  
CLKX ext  
CLKX int  
CLKR ext  
CLKR int  
CLKR ext  
CLKR int  
CLKX ext  
CLKX int  
CLKR ext  
CLKR int  
CLKX/R ext  
CLKX/R int  
CLKX ext  
CLKX int  
CLKX ext  
CLKX int  
59  
60  
61  
62  
63  
64  
65  
66  
t
t
t
t
t
t
t
t
Delay time, CLKX to DX valid  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
d(C-DX)  
8
15  
6
Setup time, DR before CLKR low  
Hold time, DR from CLKR low  
su(DR-CLKRL)  
h(CLKRL-DR)  
d(C-FSX)  
0
20  
14  
Delay time, CLKX to internal FSX high/low  
Setup time, FSR before CLKR low  
Hold time, FSX/R input from CLKX/R low  
Setup time, external FSX before CLKX  
6
6
6
0
su(FSR-CLKRL)  
h(SCKL-FS)  
su(FSX-C)  
−[t  
c(H)  
−8]* [t  
/2]−10*  
c(SCK)  
−[t  
c(H)  
−21]*  
t
/2*  
c(SCK)  
20*  
Delay time, CLKX to first DX bit, FSX  
precedes CLKX high  
d(CH-DX)V  
12*  
20*  
67  
68  
t
Delay time, FSX to first DX bit, CLKX precedes FSX  
ns  
ns  
d(FSX-DX)V  
d(CH-DXZ)  
Delay time, CLKX high to DX high impedance following last  
data bit  
t
12*  
* This parameter is not production tested.  
36  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
Not Recommended for New Designs  
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢉꢆ ꢃ ꢇꢈ ꢀꢁ ꢊ ꢃꢄ ꢅꢉ ꢆꢃ ꢇ  
ꢋꢌ ꢍꢌ ꢎꢏꢉ ꢀꢌ ꢍ ꢐꢏꢉ ꢑꢒꢓ ꢆ ꢔꢀ ꢀ ꢓ ꢒꢀ  
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006  
data-rate timing modes  
Unless otherwise indicated, the data-rate timings shown in Figure 26 and Figure 27 are valid for all serial-port  
modes, including handshake. For a functional description of serial-port operation, see subsection 8.2.12 of the  
TMS320C3x User’s Guide (literature number SPRU031).  
55  
54  
H1  
54  
56  
56  
61  
CLKX/R  
58  
57  
68  
59  
Bit n-2  
66  
Bit n-1  
Bit 0  
DX  
DR  
60  
Bit n-1  
Bit n-2  
FSR  
63  
62  
62  
FSX(INT)  
FSX(EXT)  
64  
64  
65  
NOTES: A. Timing diagrams show operations with CLKXP = CLKRP = FSXP = FSRP = 0.  
B. Timing diagrams depend on the length of the serial-port word, where n = 8, 16, 24, or 32 bits, respectively.  
Figure 26. Timing for Fixed Data-Rate Mode  
37  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
Not Recommended for New Designs  
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈ ꢀꢁꢂ ꢃ ꢄ ꢅ ꢉꢆ ꢃ ꢇꢈ ꢀ ꢁꢊ ꢃꢄ ꢅ ꢉ ꢆꢃꢇ  
ꢋ ꢌꢍ ꢌꢎꢏ ꢉ ꢀꢌ ꢍꢐ ꢏ ꢉ ꢑ ꢒꢓ ꢆꢔ ꢀꢀ ꢓꢒ ꢀ  
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006  
data-rate timing modes (continued)  
CLKX/R  
62  
FSX(INT)  
67  
65  
FSX(EXT)  
59  
68  
66  
63  
Bit n-1  
Bit n-2  
Bit n-3  
Bit 0  
DX  
64  
FSR  
Bit n-1  
Bit n-2  
Bit n-3  
DR  
60  
61  
NOTES: A. Timing diagrams show operation with CLKXP = CLKRP = FSXP = FSRP = 0.  
B. Timing diagrams depend on the length of the serial-port word, where n = 8, 16, 24, or 32 bits, respectively.  
C. The timings that are not specified expressly for the variable data-rate mode are the same as those that are specified for the fixed  
data-rate mode.  
Figure 27. Timing for Variable Data-Rate Mode  
38  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
Not Recommended for New Designs  
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢉꢆ ꢃ ꢇꢈ ꢀꢁ ꢊ ꢃꢄ ꢅꢉ ꢆꢃ ꢇ  
ꢋꢌ ꢍꢌ ꢎꢏꢉ ꢀꢌ ꢍ ꢐꢏꢉ ꢑꢒꢓ ꢆ ꢔꢀ ꢀ ꢓ ꢒꢀ  
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006  
HOLD timing  
HOLD is an asynchronous input that can be asserted at any time during a clock cycle. If the specified timings  
are met, the exact sequence shown in Figure 27 occurs; otherwise, an additional delay of one clock cycle is  
possible.  
The NOHOLD bit of the primary-bus control register overrides the HOLD signal. When this bit is set, the device  
comes out of hold and prevents future hold cycles.  
Asserting HOLD prevents the processor from accessing the primary bus. Program execution continues until a  
read from or a write to the primary bus is requested. In certain circumstances, the first write is pending, thus  
allowing the processor to continue until a second write is encountered.  
timing for HOLD/HOLDA (see Figure 28)  
’C31-40  
’LC31-40  
’C31-50  
’C31-60  
NO.  
69  
UNIT  
ns  
MIN  
MAX  
MIN  
MAX  
MIN  
MAX  
MIN  
MAX  
Setup time, HOLD before  
H1 low  
t
t
13  
13  
10  
8
su(HOLD-H1L)  
Valid time, HOLDA after H1  
low  
†
0
70  
9
0*  
9
0*  
7
0*  
6
ns  
v(H1L-HOLDA)  
†
71  
72  
t
t
Pulse duration, HOLD low  
Pulse duration, HOLDA low  
2t  
2t  
2t  
2t  
ns  
ns  
w(HOLD)  
c(H)  
c(H)  
c(H)  
c(H)  
t
−5*  
t
−5*  
t
−5*  
t
−5*  
w(HOLDA)  
cH  
cH  
cH  
cH  
Delay time, H1 low to STRB  
high for a HOLD  
73  
t
0*  
9
0*  
9
0*  
7
0*  
6
ns  
d(H1L-SH)H  
Disable time, H1 low to  
STRB to the  
high-impedance state  
74  
t
0*  
9*  
0*  
9*  
0*  
7*  
0*  
7*  
ns  
dis(H1L-S)  
Enable time, H1 low to  
STRB enabled (active)  
75  
76  
77  
t
t
t
0*  
0*  
0*  
9
9*  
9
0*  
0*  
0*  
9
9*  
9
0*  
0*  
0*  
7
8*  
7
0*  
0*  
0*  
6
7*  
6
ns  
ns  
ns  
en(H1L-S)  
Disable time, H1 low to R/W  
to the high-impedance state  
dis(H1L-RW)  
en(H1L-RW)  
Enable time, H1 low to R/W  
enabled (active)  
Disable time, H1 low to  
address to the  
high-impedance state  
78  
79  
80  
t
t
t
0*  
0*  
0*  
9*  
13  
0*  
0*  
0*  
10*  
13  
9*  
0*  
0*  
0*  
8*  
10  
0*  
0*  
0*  
7*  
11?  
7*  
ns  
ns  
ns  
dis(H1L-A)  
en(H1L-A)  
dis(H1H-D)  
Enable time, H1 low to  
address enabled (valid)  
Disable time, H1 high to  
data to the high-impedance  
state  
12*  
10*  
†
HOLD is an asynchronous input and can be asserted at any point during a clock cycle. If the specified timings are met, the exact sequence shown  
in Figure 28 occurs; otherwise, an additional delay of one clock cycle is possible.  
* This parameter is not production tested.  
39  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
Not Recommended for New Designs  
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈ ꢀꢁꢂ ꢃ ꢄ ꢅ ꢉꢆ ꢃ ꢇꢈ ꢀ ꢁꢊ ꢃꢄ ꢅ ꢉ ꢆꢃꢇ  
ꢋ ꢌꢍ ꢌꢎꢏ ꢉ ꢀꢌ ꢍꢐ ꢏ ꢉ ꢑ ꢒꢓ ꢆꢔ ꢀꢀ ꢓꢒ ꢀ  
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006  
HOLD timing (continued)  
H3  
H1  
69  
69  
71  
HOLD  
70  
70  
72  
HOLDA  
75  
73  
74  
STRB  
77  
79  
76  
R/W  
A
78  
80  
D
Write Data  
NOTE A: HOLDA goes low in response to HOLD going low and continues to remain low until one H1 cycle  
after HOLD goes back high.  
Figure 28. Timing for HOLD/HOLDA  
40  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
Not Recommended for New Designs  
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢉꢆ ꢃ ꢇꢈ ꢀꢁ ꢊ ꢃꢄ ꢅꢉ ꢆꢃ ꢇ  
ꢋꢌ ꢍꢌ ꢎꢏꢉ ꢀꢌ ꢍ ꢐꢏꢉ ꢑꢒꢓ ꢆ ꢔꢀ ꢀ ꢓ ꢒꢀ  
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006  
general-purpose I/O timing  
Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1. The contents of the internal  
control registers associated with each peripheral define the modes for these pins.  
peripheral pin I/O timing  
The table, timing parameters for peripheral pin general-purpose I/O, defines peripheral pin general-purpose I/O  
timing parameters.  
timing requirements for peripheral pin general-purpose I/O (see Note 6 and Figure 29)  
’C31-40  
’LC31-40  
’C31-33  
MIN MAX  
12  
’C31-50  
MIN MAX  
9
’C31-60  
MIN MAX  
8
NO.  
UNIT  
MIN MAX  
Setup time, general-purpose input  
before H1 low  
81  
82  
83  
t
t
t
10  
0
ns  
ns  
ns  
su(GPIO-H1L)  
h(H1L-GPIO)  
d(H1H-GPIO)  
Hold time, general-purpose input after  
H1 low  
0
0
0
Delay time, general-purpose output  
after H1 high  
15  
13  
10  
8
NOTE 6: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1. The modes of these pins are defined by the contents  
of internal-control registers associated with each peripheral.  
H3  
H1  
82  
83  
81  
83  
Peripheral  
Pin  
(see Note A)  
NOTE A: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1.  
Figure 29. Timing for Peripheral Pin General-Purpose I/O  
41  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
Not Recommended for New Designs  
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈ ꢀꢁꢂ ꢃ ꢄ ꢅ ꢉꢆ ꢃ ꢇꢈ ꢀ ꢁꢊ ꢃꢄ ꢅ ꢉ ꢆꢃꢇ  
ꢋ ꢌꢍ ꢌꢎꢏ ꢉ ꢀꢌ ꢍꢐ ꢏ ꢉ ꢑ ꢒꢓ ꢆꢔ ꢀꢀ ꢓꢒ ꢀ  
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006  
changing the peripheral pin I/O modes  
The following tables show the timing parameters for changing the peripheral pin from a general-purpose output  
pin to a general-purpose input pin and vice versa.  
timing requirements for peripheral pin changing from general-purpose output to input mode  
(see Note 6 and Figure 30)  
’C31-40  
’C31-50  
’C31-60  
’LC31-40  
MIN MAX MIN MAX MIN MAX  
13 10  
NO.  
UNIT  
84  
85  
86  
t
t
t
Hold time, peripheral pin after H1 high  
Setup time, peripheral pin before H1 low  
Hold time, peripheral pin after H1 low  
8
ns  
ns  
ns  
h(H1H)  
9
0
9
0
8
0
su(GPIO-H1L)  
h(H1L-GPIO)  
NOTE 6: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1. The modes of these pins are defined by the contents  
of internal-control registers associated with each peripheral.  
Execution  
of Store of  
Peripheral-  
Control  
Value on Pin  
Seen in  
Peripheral-  
Control  
Buffers Go  
From  
Output to  
Input  
Synchronizer Delay  
Register  
Register  
H3  
H1  
85  
I/O  
Control Bit  
86  
84  
Peripheral  
Pin  
Output  
(see Note A)  
Data Bit  
Data  
Data  
Seen  
Sampled  
NOTE A: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1.  
Figure 30. Timing for Change of Peripheral Pin From General-Purpose Output to Input Mode  
42  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
Not Recommended for New Designs  
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢉꢆ ꢃ ꢇꢈ ꢀꢁ ꢊ ꢃꢄ ꢅꢉ ꢆꢃ ꢇ  
ꢋꢌ ꢍꢌ ꢎꢏꢉ ꢀꢌ ꢍ ꢐꢏꢉ ꢑꢒꢓ ꢆ ꢔꢀ ꢀ ꢓ ꢒꢀ  
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006  
timing for peripheral pin changing from general-purpose input to output mode (see Note 6 and  
Figure 31)  
’C31-40  
’LC31-40  
’C31-50  
MIN MAX  
10  
’C31-60  
MIN MAX  
8
NO.  
UNIT  
MIN MAX  
Delay time, H1 high to peripheral pin switching from input  
to output  
87  
t
13  
ns  
d(H1H-GPIO)  
NOTE 6: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1. The modes of these pins are defined by the contents  
of internal-control registers associated with each peripheral.  
Execution of Store  
of Peripheral-  
Control Register  
H3  
H1  
I/O  
Control  
Bit  
87  
Peripheral  
Pin  
(see Note A)  
NOTE A: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1.  
Figure 31. Timing for Change of Peripheral Pin From General-Purpose Input to Output Mode  
43  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
Not Recommended for New Designs  
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈ ꢀꢁꢂ ꢃ ꢄ ꢅ ꢉꢆ ꢃ ꢇꢈ ꢀ ꢁꢊ ꢃꢄ ꢅ ꢉ ꢆꢃꢇ  
ꢋ ꢌꢍ ꢌꢎꢏ ꢉ ꢀꢌ ꢍꢐ ꢏ ꢉ ꢑ ꢒꢓ ꢆꢔ ꢀꢀ ꢓꢒ ꢀ  
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006  
timer pin timing  
Valid logic-level periods and polarity are specified by the contents of the internal control registers.  
The following tables define the timing requirements for the timer pin.  
timing for timer pin (see Figure 32 and Note 7)  
’C31-40,  
’LC31-40  
’C31-50  
’C31-60  
NO.  
UNIT  
MIN  
MAX  
MIN  
MAX  
Setup time, TCLK external  
before H1 low  
88  
89  
90  
t
t
t
10  
6
ns  
ns  
ns  
su(TCLK-H1L)  
h(H1L-TCLK)  
d(H1H-TCLK)  
Hold time, TCLK external after  
H1 low  
0
0
Delay time, H1 high to TCLK  
internal valid  
9
8
TCLK ext  
t
×2.6  
×2  
t
×2.6  
×2  
c(H)  
t
c(H)  
t
91  
92  
t
Cycle time, TCLK  
ns  
ns  
c(TCLK)  
w(TCLK)  
TCLK int  
TCLK ext  
TCLK int  
t
×232  
*
t
×232*  
c(H)  
c(H)  
c(H)  
c(H)  
t
+10  
t
+10  
Pulse duration,  
TCLK high/low  
c(H)  
c(H)  
t
[t  
/2]−5 [t  
/2]+5  
[t  
/2]−5 [t  
/2]+5  
c(TCLK)  
c(TCLK)  
c(TCLK)  
c(TCLK)  
NOTE 7: Numbers 88 and 89 are applicable for a synchronous input clock. Timing parameters 91 and 92 are applicable for an asynchronous  
input clock.  
* This parameter is not production tested.  
H3  
H1  
89  
90  
90  
88  
Peripheral  
Pin  
(see Note A)  
92  
91  
NOTE A: HOLDA goes low in response to HOLD going low and continues to remain low until one H1 cycle  
after HOLD goes back high.  
Figure 32. Timing for Timer Pin  
44  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
Not Recommended for New Designs  
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢉꢆ ꢃ ꢇꢈ ꢀꢁ ꢊ ꢃꢄ ꢅꢉ ꢆꢃ ꢇ  
ꢋꢌ ꢍꢌ ꢎꢏꢉ ꢀꢌ ꢍ ꢐꢏꢉ ꢑꢒꢓ ꢆ ꢔꢀ ꢀ ꢓ ꢒꢀ  
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006  
SHZ pin timing  
The following table defines the timing parameter for the SHZ pin.  
timing parameters for SHZ (see Figure 33)  
’C31  
’LC31  
NO.  
UNIT  
MIN  
MAX  
†
2P *  
93  
t
Disable time, SHZ low to all O, I/O pins disabled (high impedance)  
0*  
ns  
dis(SHZ)  
†
P = t  
c(CI)  
* This parameter is not production tested.  
H3  
H1  
SHZ  
93  
All I/O Pins  
NOTE A: Enabling SHZ destroys SMJ320C3x register and memory contents.  
Assert SHZ = 1 and reset the SMJ320C3x to restore it to a known  
condition.  
Figure 33. Timing for SHZ  
45  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
Not Recommended for New Designs  
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈ ꢀꢁꢂ ꢃ ꢄ ꢅ ꢉꢆ ꢃ ꢇꢈ ꢀ ꢁꢊ ꢃꢄ ꢅ ꢉ ꢆꢃꢇ  
ꢋ ꢌꢍ ꢌꢎꢏ ꢉ ꢀꢌ ꢍꢐ ꢏ ꢉ ꢑ ꢒꢓ ꢆꢔ ꢀꢀ ꢓꢒ ꢀ  
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006  
part order information  
POWER  
SUPPLY  
OPERATING  
FREQUENCY  
PROCESSING  
LEVEL  
DEVICE  
TECHNOLOGY  
PACKAGE TYPE  
5962-9205803MXA  
SMJ320C31GFAM40  
SM320C31GFAM40  
0.6-µm CMOS  
0.6-µm CMOS  
0.6-µm CMOS  
5 V 5%  
5 V 5%  
5 V 5%  
40 MHz  
40 MHz  
40 MHz  
Ceramic 141-pin staggered PGA  
Ceramic 141-pin staggered PGA  
Ceramic 141-pin staggered PGA  
DSCC SMD  
QML  
Std  
Ceramic 132-pin quad flatpack with  
nonconductive tie bar.  
5962-9205803MYA  
SMJ320C31HFGM40  
SM320C31HFGM40  
0.6-µm CMOS  
0.6-µm CMOS  
0.6-µm CMOS  
5 V 5%  
5 V 5%  
5 V 5%  
40 MHz  
40 MHz  
40 MHz  
DSCC SMD  
QML  
Ceramic 132-lead quad flatpack with a  
nonconductive tie bar  
Ceramic 132-lead quad flatpack with a  
nonconductive tie bar  
Std  
5962-9205803Q9A  
SMJ320C31KGDM40B  
5962-9205804MXA  
SMJ320C31GFAM50  
SM320C31GFAM50  
0.72-µm CMOS  
0.72-µm CMOS  
0.6-µm CMOS  
0.6-µm CMOS  
0.6-µm CMOS  
5 V 5%  
5 V 5%  
5 V 5%  
5 V 5%  
5 V 5%  
40 MHz  
40 MHz  
50 MHz  
50 MHz  
50 MHz  
C31−40 KGD (known good die)  
C31−40 KGD (known good die)  
Ceramic 141-pin staggered PGA  
Ceramic 141-pin staggered PGA  
Ceramic 141-pin staggered PGA  
DSCC SMD  
QML  
DSCC SMD  
QML  
Std  
Ceramic 132-pin quad flatpack with  
nonconductive tie bar.  
5962-9205804MYA  
SMJ320C31HFGM50  
SM320C31HFGM50  
0.6-µm CMOS  
0.6-µm CMOS  
0.6-µm CMOS  
5 V 5%  
5 V 5%  
5 V 5%  
50 MHz  
50 MHz  
50 MHz  
DSCC SMD  
QML  
Ceramic 132-lead quad flatpack with  
nonconductive tie bar  
Ceramic 132-lead quad flatpack with  
nonconductive tie bar  
Std  
5962-9205805QXA  
SMJ320C31GFAS60  
SM320C31GFAS60  
0.6-µm CMOS  
0.6-µm CMOS  
0.6-µm CMOS  
5 V 5%  
5 V 5%  
5 V 5%  
60 MHz  
60 MHz  
60 MHz  
Ceramic 141-pin staggered PGA  
Ceramic 141-pin staggered PGA  
Ceramic 141-pin staggered PGA  
DSCC SMD  
QML  
Std  
Ceramic 132-pin quad flatpack with  
nonconductive tie bar.  
5962-9205805QYA  
SMJ320C31HFGS60  
SM320C31HFGS60  
0.6-µm CMOS  
0.6-µm CMOS  
0.6-µm CMOS  
5 V 5%  
5 V 5%  
5 V 5%  
60 MHz  
60 MHz  
60 MHz  
DSCC SMD  
QML  
Ceramic 132-lead quad flatpack with  
nonconductive tie bar  
Ceramic 132-lead quad flatpack with  
nonconductive tie bar  
Std  
5962-9760601NXB  
0.72-µm CMOS  
0.72-µm CMOS  
0.72-µm CMOS  
0.72-µm CMOS  
3.3 V 5%  
3.3 V 5%  
3.3 V 5%  
3.3 V 5%  
40 MHz  
40 MHz  
40 MHz  
40 MHz  
Plastic 132-lead good flatpack  
Plastic 132-lead good flatpack  
LC31−40 KGD (known good die)  
LC31−40 KGD (known good die)  
DSCC SMD  
QML  
SMQ320LC31PQM40  
5962-9760601Q9A  
DSCC SMD  
QML  
SMJ320LC31KGDM40B  
46  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
Not Recommended for New Designs  
ꢀ
ꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢃ ꢇ ꢈ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢉꢆ ꢃ ꢇꢈ ꢀꢁ ꢊ ꢃꢄ ꢅꢉ ꢆꢃ ꢇ  
ꢋꢌ ꢍꢌ ꢎꢏꢉ ꢀꢌ ꢍ ꢐꢏꢉ ꢑꢒꢓ ꢆ ꢔꢀ ꢀ ꢓ ꢒꢀ  
SGUS026G − APRIL 1998 − REVISED SEPTEMBER 2006  
part order information (continued)  
SMJ  
320 (L)  
C
31  
GFA  
M
50  
SPEED RANGE  
PREFIX  
40  
50  
60  
=
=
=
40 MHz  
50 MHz  
60 MHz  
SMJ = MIL-PRF-38535 (QML)  
SM  
=
Standard Processing  
SMQ = Plastic (QML)  
TEMPERATURE RANGE  
M = − 55°C to125°C  
S = − 55°C to105°C  
DEVICE FAMILY  
320  
= SMJ320 Family  
L =  
0°C to 70°C  
TECHNOLOGY  
L
=
Low Voltage  
(3.3−V option)  
TECHNOLOGY  
C = CMOS  
TB  
=
=
132-lead TAB frame, bare-die  
option  
Known Good Die  
DEVICE  
31 = ’320C31 or ’320LC31  
KGD  
Figure 34. Device Nomenclature  
47  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
PACKAGE OPTION ADDENDUM  
www.ti.com  
1-Jun-2012  
PACKAGING INFORMATION  
Status (1)  
Eco Plan (2)  
MSL Peak Temp (3)  
Samples  
Orderable Device  
Package Type Package  
Drawing  
Pins  
Package Qty  
Lead/  
Ball Finish  
(Requires Login)  
5962-9205803MXA  
5962-9205803MXC  
5962-9205803MYA  
5962-9205804MXA  
5962-9205804MXC  
5962-9205804MYA  
5962-9205805QXA  
5962-9205805QYA  
5962-9760601NXB  
NRND  
NRND  
NRND  
NRND  
NRND  
NRND  
NRND  
NRND  
NRND  
CPGA  
CPGA  
CFP  
GFA  
GFA  
HFG  
GFA  
GFA  
HFG  
GFA  
HFG  
PQ  
141  
141  
132  
141  
141  
132  
141  
132  
132  
1
1
1
1
1
1
1
1
1
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
Call TI  
Call TI  
Call TI  
Call TI  
Call TI  
Call TI  
Call TI  
Call TI  
Call TI  
N / A for Pkg Type  
Call TI  
CPGA  
CPGA  
CFP  
Call TI  
N / A for Pkg Type  
Call TI  
CPGA  
CFP  
Call TI  
Call TI  
BQFP  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-4-260C-72 HR  
5962-9760601Q9A  
SM320C31GFAM50  
SM320C31GFAS60  
SM320C31HFGM40  
SM320C31HFGM50  
SMJ320C31GFAM40  
SMJ320C31GFAM50  
SMJ320C31GFAS60  
SMJ320C31HFGM40  
SMJ320C31HFGM50  
SMJ320C31HFGS60  
SMQ320LC31PQM40  
OBSOLETE  
NRND  
NRND  
NRND  
NRND  
NRND  
NRND  
NRND  
NRND  
NRND  
NRND  
NRND  
XCEPT  
CPGA  
CPGA  
CFP  
KGD  
GFA  
GFA  
HFG  
HFG  
GFA  
GFA  
GFA  
HFG  
HFG  
HFG  
PQ  
0
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
Call TI  
Call TI  
Call TI  
Call TI  
Call TI  
Call TI  
Call TI  
Call TI  
Call TI  
Call TI  
Call TI  
Call TI  
Call TI  
141  
141  
132  
132  
141  
141  
141  
132  
132  
132  
132  
1
1
1
1
1
1
1
1
1
1
1
N / A for Pkg Type  
N / A for Pkg Type  
N / A for Pkg Type  
N / A for Pkg Type  
N / A for Pkg Type  
N / A for Pkg Type  
N / A for Pkg Type  
N / A for Pkg Type  
N / A for Pkg Type  
N / A for Pkg Type  
Call TI  
CFP  
CPGA  
CPGA  
CPGA  
CFP  
CFP  
CFP  
BQFP  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
1-Jun-2012  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
OTHER QUALIFIED VERSIONS OF SM320C31, SMJ320C31 :  
Catalog: TMS320C31, TMS320C31  
•
Military: SMJ320C31  
•
NOTE: Qualified Version Definitions:  
Catalog - TI's standard catalog product  
•
Military - QML certified for Military and Defense Applications  
•
Addendum-Page 2  
MECHANICAL DATA  
MBQF001A – NOVEMBER 1995  
PQ (S-PQFP-G***)  
PLASTIC QUAD FLATPACK  
100 LEAD SHOWN  
13  
1 100  
89  
14  
88  
0.012 (0,30)  
0.008 (0,20)  
0.006 (0,15)  
M
”D3” SQ  
0.025 (0,635)  
0.006 (0,16) NOM  
64  
38  
0.150 (3,81)  
0.130 (3,30)  
39  
63  
Gage Plane  
”D1” SQ  
”D” SQ  
0.010 (0,25)  
0.020 (0,51) MIN  
Seating Plane  
”D2” SQ  
0°–8°  
0.046 (1,17)  
0.036 (0,91)  
0.004 (0,10)  
0.180 (4,57) MAX  
LEADS ***  
100  
132  
DIM  
MAX  
MIN  
0.890 (22,61)  
0.870 (22,10)  
0.766 (19,46)  
0.734 (18,64)  
0.912 (23,16)  
0.888 (22,56)  
0.600 (15,24)  
1.090 (27,69)  
1.070 (27,18)  
0.966 (24,54)  
0.934 (23,72)  
1.112 (28,25)  
1.088 (27,64)  
0.800 (20,32)  
”D”  
MAX  
MIN  
”D1”  
MAX  
MIN  
”D2”  
”D3”  
NOM  
4040045/C 11/95  
NOTES: A. All linear dimensions are in inches (millimeters).  
B. This drawing is subject to change without notice.  
C. Falls within JEDEC MO-069  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
MECHANICAL DATA  
MCPG015B – FEBRUARY 1996 – REVISED DECEMBER 2001  
GFA (S-CPGA-P141)  
CERAMIC PIN GRID ARRAY  
1.080 (27,43)  
1.040 (26,42)  
SQ  
0.900 (22,86) TYP  
0.100 (2,54) TYP  
0.050 (1,27) TYP  
W
U
R
N
L
V
T
P
M
K
H
F
J
G
E
C
A
D
B
A1 Corner  
1
3
5
7
9
11 13 15 17 19  
10 12 14 16 18  
2
4
6
8
0.026 (0,66)  
0.006 (0,15)  
0.145 (3,68)  
0.105 (2,67)  
Bottom View  
0.034 (0,86) TYP  
0.140 (3,56)  
0.120 (3,05)  
0.022 (0,56)  
0.016 (0,41)  
DIA TYP  
0.048 (1,22) DIA TYP  
4 Places  
4040133/E 11/01  
NOTES: A. All linear dimensions are in inches (millimeters).  
B. This drawing is subject to change without notice.  
C. Index mark can appear on top or bottom, depending on package vendor.  
D. Pins are located within 0.010 (0,25) diameter of true position relative to  
each other at maximum material condition and within 0.030 (0,76) diameter  
relative to the edge of the ceramic.  
E. This package can be hermetically sealed with metal lids or with ceramic lids using glass frit.  
F. The pins can be gold-plated or solder-dipped.  
G. Falls within JEDEC MO-128AB  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,  
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should  
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are  
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.  
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard  
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where  
mandated by government requirements, testing of all parameters of each product is not necessarily performed.  
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and  
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide  
adequate design and operating safeguards.  
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,  
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information  
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a  
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual  
property of the third party, or a license from TI under the patents or other intellectual property of TI.  
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied  
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive  
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional  
restrictions.  
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all  
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not  
responsible or liable for any such statements.  
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably  
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing  
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and  
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products  
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be  
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in  
such safety-critical applications.  
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are  
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military  
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at  
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.  
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are  
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated  
products in automotive applications, TI will not be responsible for any failure to meet such requirements.  
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:  
Products  
Audio  
Applications  
www.ti.com/audio  
amplifier.ti.com  
dataconverter.ti.com  
www.dlp.com  
Automotive and Transportation www.ti.com/automotive  
Communications and Telecom www.ti.com/communications  
Amplifiers  
Data Converters  
DLP® Products  
DSP  
Computers and Peripherals  
Consumer Electronics  
Energy and Lighting  
Industrial  
www.ti.com/computers  
www.ti.com/consumer-apps  
www.ti.com/energy  
dsp.ti.com  
Clocks and Timers  
Interface  
www.ti.com/clocks  
interface.ti.com  
logic.ti.com  
www.ti.com/industrial  
www.ti.com/medical  
www.ti.com/security  
Medical  
Logic  
Security  
Power Mgmt  
Microcontrollers  
RFID  
power.ti.com  
Space, Avionics and Defense www.ti.com/space-avionics-defense  
microcontroller.ti.com  
www.ti-rfid.com  
Video and Imaging  
www.ti.com/video  
OMAP Mobile Processors www.ti.com/omap  
Wireless Connectivity www.ti.com/wirelessconnectivity  
TI E2E Community Home Page  
e2e.ti.com  
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265  
Copyright © 2012, Texas Instruments Incorporated  

相关型号：

SM320C31GFAM40

 DIGITAL SIGNAL PROCESSORS

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI

SM320C31GFAM50

 DIGITAL SIGNAL PROCESSORS

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI

SM320C31GFAS60

 DIGITAL SIGNAL PROCESSORS

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI

SM320C31GFM27

 Digital Signal Processor, 32-Ext Bit, 27MHz, CMOS, CPGA141, PGA-141

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ROCHESTER

SM320C31GFM33

 Digital Signal Processor, 32-Ext Bit, 33MHz, CMOS, CPGA141, PGA-141

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ROCHESTER

SM320C31HFGM40

 DIGITAL SIGNAL PROCESSORS

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI

SM320C31HFGM50

 DIGITAL SIGNAL PROCESSORS

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI

SM320C31HFGS60

 DIGITAL SIGNAL PROCESSORS

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI

SM320C32-EP

 DIGITAL SIGNAL PROCESSOR

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI

SM320C40

 军用级 C40 浮点 DSP

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI

SM320C40GFM33

 32-BIT, 33.33MHz, OTHER DSP, CPGA325

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI

SM320C40GFM40

 DIGITAL SIGNAL PROCESSORS

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
©2020 ICPDF网 联系我们和版权申明