SM320C6201BGLP_技术文档

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SGUS031 – APRIL 2000

GLP

D

Highest Performance Fixed-Point Digital

Signal Processor (DSP) SM/SMJ320C6201B

– 5-, 6.7-ns Instruction Cycle Time

– 150 and 200-MHz Clock Rate

– Eight 32-Bit Instructions/Cycle

– 1200 and 1600 MIPS

429-PIN BALL GRID ARRAY (BGA) PACKAGE

(BOTTOM VIEW)

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VelociTI Advanced Very Long Instruction

Word (VLIW) ’C62x CPU Core

– Eight Independent Functional Units:

– Six ALUs (32-/40-Bit)

– Two 16-Bit Multipliers (32-Bit Results)

– Load-Store Architecture With 32 32-Bit

General-Purpose Registers

– Instruction Packing Reduces Code Size

– All Instructions Conditional

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B

A

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Instruction Set Features

– Byte-Addressable (8-, 16-, 32-Bit Data)

– 32-Bit Address Range

– 8-Bit Overflow Protection

– Saturation

1

3

5

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9

11 13 15 17 19 21

10 12 14 16 18 20

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– Bit-Field Extract, Set, Clear

– Bit-Counting

– Normalization

D

Two Multichannel Buffered Serial Ports

(McBSPs)

– Direct Interface to T1/E1, MVIP, SCSA

Framers

D

1M-Bit On-Chip SRAM

– 512K-Bit Internal Program/Cache

(16K 32-Bit Instructions)

– 512K-Bit Dual-Access Internal Data

(64K Bytes) Organized as Two Blocks for

Improved Concurrency

– ST-Bus-Switching Compatible

– Up to 256 Channels Each

– AC97-Compatible

– Serial Peripheral Interface (SPI)

Compatible (Motorola )

32-Bit External Memory Interface (EMIF)

– Glueless Interface to Synchronous

Memories: SDRAM and SBSRAM

– Glueless Interface to Asynchronous

Memories: SRAM and EPROM

D

Two 32-Bit General-Purpose Timers

Flexible Phase-Locked Loop (PLL) Clock

Generator

†

IEEE-1149.1 (JTAG ) Boundary-Scan

Compatible

D

Four-Channel Bootloading

Direct-Memory-Access (DMA) Controller

with an Auxiliary Channel

D

429-Pin BGA Package (GLP Suffix)

D

CMOS Technology

– 0.18-µm/5-Level Metal Process

16-Bit Host-Port Interface (HPI)

– Access to Entire Memory Map

D

3.3-V I/Os, 1.8-V Internal

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

VelociTI is a trademark of Texas Instruments Incorporated.

Motorola is a trademark of Motorola, Inc.

†

IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

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description

The 320C6201B DSP is a member of the fixed-point DSP family in the 320C6000 platform. The

SM/SMJ320C6201B (’C6201B) device is based on the high-performance, advanced VelociTI

very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI ), making this DSP an

excellent choice for multichannel and multifunction applications. With performance of up to 1600 million

instructions per second (MIPS) at a clock rate of 200 MHz, the ’C6201B offers cost-effective solutions to

high-performance DSP programming challenges. The ’C6201B is a newer revision of the ’C6201. The ’C6201B

DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array

processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent

functional units. The eight functional units provide six arithmetic logic units (ALUs) for a high degree of

parallelism and two 16-bit multipliers for a 32-bit result. The ’C6201B can produce two multiply-accumulates

(MACs) per cycle—for a total of 400 million MACs per second (MMACS). The ’C6201B DSP also has

application-specific hardware logic, on-chip memory, and additional on-chip peripherals.

The ’C6201B includes a large bank of on-chip memory and has a powerful and diverse set of peripherals.

Program memory consists of a 64K-byte block that is user-configurable as cache or memory-mapped program

space. Data memory of the ’C6201B consists of two 32K-byte blocks of RAM for improved concurrency. The

peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a

host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM

or SBSRAM and asynchronous peripherals.

The ’C6201B has a complete set of development tools which includes: a new C compiler, a third-party Ada 95

compiler, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface

for visibility into source code execution.

device characteristics

Table 1 provides an overview of the ’C62x DSP. The table shows significant features of each device, including

the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count.

Table 1. Characteristics of the ’C6201B Processor

CHARACTERISTICS

DESCRIPTION

Device Number

320C6201B

512-Kbit Program Memory

512-Kbit Data Memory (organized as two blocks)

On-Chip Memory

Peripherals

2 Multichannel Buffered Serial Ports (McBSPs)

2 General-Purpose Timers

Host-Port Interface (HPI)

External Memory Interface (EMIF)

6.7 ns (320C6201B 150 MHz),

5 ns (320C6201B 200 MHz)

Cycle Time

Package Type

Nominal Voltage

27 mm × 27 mm, 429-Pin Ceramic D-BGA (GLP)

1.8 V Core

3.3 V I/O

TI is a trademark of Texas Instruments Incorporated.

Windows is a registered trademark of the Microsoft Corporation.

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functional block diagram

Timers

Interrupt Selector

McBSPs

Data Memory

Peripheral

Bus

Controller

HPI Control

DMA Control

EMIF Control

Data Memory

Controller

DMA

Controller

Host-Port Interface

PLL

CPU

EMIF

Power

Down

Program Memory Controller

Program Memory/Cache

Boot-

Config.

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CPU description

The CPU fetches VelociTI advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight

32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture features

controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The

first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the

previous instruction, or whether it should be executed in the following clock as a part of the next execute packet.

Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length

execute packets are a key memory-saving feature, distinguishing the ’C62x CPU from other VLIW architectures.

The CPU features two sets of functional units. Each set contains four units and a register file. One set contains

functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files

each contain 16 32-bit registers for a total of 32 general-purpose registers. The two sets of functional units, along

with two register files, compose sides A and B of the CPU (see Figure 1 and Figure 2). The four functional units

on each side of the CPU can freely share the 16 registers belonging to that side. Additionally, each side features

a single data bus connected to all the registers on the other side, by which the two sets of functional units can

access data from the register files on the opposite side. While register access by functional units on the same

side of the CPU as the register file can service all the units in a single clock cycle, register access using the

register file across the CPU supports one read and one write per cycle.

Another key feature of the ’C62x CPU is the load/store architecture, where all instructions operate on registers

(as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data

transfers between the register files and the memory. The data address driven by the .D units allows data

addresses generated from one register file to be used to load or store data to or from the other register file. The

’C62x CPU supports a variety of indirect addressing modes using either linear- or circular-addressing modes

with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers. Some

registers, however, are singled out to support specific addressing or to hold the condition for conditional

instructions (if the condition is not automatically “true”). The two .M functional units are dedicated for multiplies.

The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results

available every clock cycle.

The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory.

The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least

significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous

execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain,

effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the fetch

packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of the

current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet can

vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per

clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch

packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units

for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit

registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store

instructions are byte-, half-word, or word-addressable.

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CPU description (continued)

Program Memory

32-Bit Address

256-Bit Data

’C62x CPU

Program Fetch

Control

Registers

Instruction Dispatch

Instruction Decode

Data Path A

Data Path B

Register File B

Control

Logic

External Memory

Interface

Register File A

Test

Emulation

Interrupts

.M2

.S2 .L2

.L1 .S1 .M1 .D1

.D2

Additional

Peripherals:

Timers,

Serial Ports,

etc.

Data Memory

32-Bit Address

8-, 16-, 32-Bit Data

Figure 1. 320C62x CPU Block Diagram

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CPU description (continued)

src1

src2

dst

long dst

long src

.L1

8

32

ST1

8

long src

long dst

dst

Register

File A

Data Path A

.S1

src1

(A0–A15)

src2

dst

src1

.M1

.D1

src2

LD1

dst

src1

src2

DA1

2X

1X

src2

src1

dst

DA2

.D2

LD2

src2

.M2

.S2

src1

dst

src2

Register

File B

(B0–B15)

Data Path B

src1

dst

long dst

long src

8

32

8

ST2

8

long src

long dst

dst

.L2

src2

src1

Control

Register

File

Figure 2. 320C62x CPU Data Paths

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signal groups description

CLKIN

CLKOUT2

CLKOUT1

CLKMODE1

CLKMODE0

PLLFREQ3

PLLFREQ2

PLLFREQ1

PLLV

BOOTMODE4

BOOTMODE3

BOOTMODE2

BOOTMODE1

BOOTMODE0

Boot Mode

Clock/PLL

RESET

NMI

PLLG

PLLF

EXT_INT7

EXT_INT6

EXT_INT5

EXT_INT4

IACK

Reset and

Interrupts

INUM3

INUM2

TMS

TDO

INUM1

INUM0

TDI

TCK

TRST

EMU1

EMU0

JTAG

Emulation

Little ENDIAN

Big ENDIAN

LENDIAN

RSV9

RSV8

RSV7

RSV6

RSV5

RSV4

RSV3

RSV2

RSV1

RSV0

DMAC3

DMAC2

DMAC1

DMAC0

DMA Status

Reserved

Power-Down

Status

PD

Control/Status

HPI

16

(Host-Port Interface)

HD[15:0]

Data

HAS

HR/W

HCS

HDS1

HDS2

HRDY

HINT

HCNTL0

HCNTL1

Register Select

Control

HHWIL

HBE1

HBE0

Half-Word/Byte

Select

Figure 3. CPU and Peripheral Signals

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signal groups description (continued)

32

ED[31:0]

Data

ARE

Asynchronous

Memory

AOE

AWE

ARDY

CE3

CE2

CE1

CE0

Control

Memory Map

Space Select

SSADS

SSOE

SSWE

SSCLK

SBSRAM

Control

20

EA[21:2]

Word Address

Byte Enables

BE3

BE2

BE1

BE0

SDA10

SDRAS

SDCAS

SDWE

SDRAM

Control

SDCLK

HOLD

HOLD/

HOLDA

EMIF

(External Memory Interface)

TOUT1

TINP1

TOUT0

TINP0

Timer 1

Timer 0

Timers

McBSP1

Transmit

McBSP0

Transmit

CLKX1

FSX1

DX1

CLKX0

FSX0

DX0

CLKR1

FSR1

DR1

CLKR0

FSR0

DR0

Receive

Clock

Receive

Clock

CLKS1

CLKS0

McBSPs

(Multichannel Buffered Serial Ports)

Figure 4. Peripheral Signals

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Signal Descriptions

SIGNAL

NAME

†

DESCRIPTION

TYPE

NO.

CLOCK/PLL

CLKIN

A14

Y6

I

Clock Input

CLKOUT1

O

Clock output at full device speed

Clock output at half of device speed

Clock mode select

CLKOUT2

V9

CLKMODE1

CLKMODE0

PLLFREQ3

PLLFREQ2

PLLFREQ1

B17

C17

C13

G11

F11

D12

G10

C12

I

•

Selects whether the output clock frequency = input clock freq x4 or x1

PLL frequency range (3, 2, and 1)

The target range for CLKOUT1 frequency is determined by the 3-bit value of the PLLFREQ pins.

•

I

‡

§

PLLV

A

PLL analog V connection for the low-pass filter

CC

‡

§

PLLG

A

PLL analog GND connection for the low-pass filter

PLL low-pass filter connection to external components and a bypass capacitor

JTAG EMULATION

§

PLLF

A

TMS

TDO

TDI

K19

R12

R13

M20

N18

R20

T18

I

JTAG test port mode select (features an internal pull-up)

JTAG test port data out

O/Z

I

JTAG test port data in (features an internal pull-up)

JTAG test port clock

TCK

TRST

EMU1

EMU0

JTAG test port reset (features an internal pull-down)

Emulation pin 1, pull-up with a dedicated 20-kΩ resistor

Emulation pin 0, pull-up with a dedicated 20-kΩ resistor

RESET AND INTERRUPTS

I/O/Z

RESET

NMI

J20

I

Device reset

Nonmaskable interrupt

K21

•

Edge-driven (rising edge)

EXT_INT7

EXT_INT6

EXT_INT5

EXT_INT4

IACK

R16

P20

R15

R18

R11

T19

T20

T14

T16

External interrupts

Edge-driven (rising edge)

I

•

O

Interrupt acknowledge for all active interrupts serviced by the CPU

Active interrupt identification number

INUM3

INUM2

•

Valid during IACK for all active interrupts (not just external)

Encoding order follows the interrupt service fetch packet ordering

O

INUM1

INUM0

LITTLE ENDIAN/BIG ENDIAN

If high, selects little-endian byte/half-word addressing order within a word

If low, selects big-endian addressing

LENDIAN

G20

I

POWER DOWN STATUS

PD

D19

O

Power-down mode 2 or 3 (active if high)

†

‡

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

PLLV and PLLG signals are not part of external voltage supply or ground. See the CLOCK/PLL documentation for information on how to connect

those pins.

A = Analog Signal (PLL Filter)

§

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Signal Descriptions (Continued)

SIGNAL

NAME

†

DESCRIPTION

TYPE

NO.

HOST PORT INTERFACE (HPI)

HINT

H2

O/Z

Host interrupt (from DSP to host)

HCNTL1

HCNTL0

HHWIL

HBE1

HBE0

HR/W

HD15

HD14

HD13

HD12

HD11

HD10

HD9

J6

H6

E4

I

Host control – selects between control, address or data registers

Host halfword select – first or second halfword (not necessarily high or low order)

Host byte select within word or half-word

G6

F6

Host byte select within word or half-word

D4

D11

B11

A11

G9

D10

A10

C10

B9

Host read or write select

HD8

I/O/Z

Host port data (used for transfer of data, address and control)

HD7

F9

HD6

C9

A9

HD5

HD4

B8

HD3

D9

D8

B7

HD2

HD1

HD0

C7

L6

HAS

I

Host address strobe

Host chip select

HCS

C5

C4

K6

HDS1

HDS2

HRDY

I

Host data strobe 1

Host data strobe 2

Host ready (from DSP to host)

BOOT MODE

I

H3

O

BOOTMODE4

BOOTMODE3

BOOTMODE2

BOOTMODE1

BOOTMODE0

B16

G14

F15

C18

D17

I

Boot mode

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

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Signal Descriptions (Continued)

SIGNAL

NAME

†

DESCRIPTION

TYPE

NO.

EMIF – CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY

CE3

Y5

V3

T6

U2

R8

T3

T2

R2

O/Z

CE2

CE1

CE0

BE3

BE2

BE1

BE0

Memory space enables

•

Enabled by bits 24 and 25 of the word address

Only one asserted during any external data access

Byte enable control

•

Decoded from the two lowest bits of the internal address

Byte write enables for most types of memory

Can be directly connected to SDRAM read and write mask signal (SDQM)

EMIF – ADDRESS

EA21

EA20

EA19

EA18

EA17

EA16

EA15

EA14

EA13

EA12

EA11

EA10

EA9

L4

L3

J2

J1

K1

K2

L2

L1

M1

M2

M6

N4

N1

N2

N6

P4

P3

P2

P1

P6

O/Z

External address (word address)

EA8

EA7

EA6

EA5

EA4

EA3

EA2

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

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Signal Descriptions (Continued)

SIGNAL

NAME

†

DESCRIPTION

TYPE

NO.

EMIF – DATA

ED31

U18

ED30

ED29

ED28

ED27

ED26

ED25

ED24

ED23

ED22

ED21

ED20

ED19

ED18

ED17

ED16

ED15

ED14

ED13

ED12

ED11

ED10

ED9

U20

T15

V18

V17

V16

T12

W17

T13

Y17

T11

Y16

W15

V14

Y15

R9

I/O/Z

External data

Y14

V13

AA13

T10

Y13

W12

Y12

Y11

V10

AA10

Y10

W10

Y9

ED8

ED7

ED6

ED5

ED4

ED3

ED2

AA9

Y8

ED1

ED0

W9

EMIF – ASYNCHRONOUS MEMORY CONTROL

Asynchronous memory read enable

ARE

R7

T7

V5

R4

O/Z

I

AOE

AWE

ARDY

Asynchronous memory output enable

Asynchronous memory write enable

Asynchronous memory ready input

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

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Signal Descriptions (Continued)

SIGNAL

NAME

†

DESCRIPTION

TYPE

NO.

EMIF – SYNCHRONOUS BURST SRAM CONTROL

SBSRAM address strobe

SSADS

V8

W7

Y7

O/Z

SSOE

SSWE

SSCLK

SBSRAM output enable

SBSRAM write enable

AA8

SBSRAM clock

EMIF – SYNCHRONOUS DRAM CONTROL

SDRAM address 10 (separate for deactivate command)

SDRAM row address strobe

SDRAM column address strobe

SDRAM write enable

SDA10

SDRAS

SDCAS

SDWE

SDCLK

V7

V6

W5

T8

O/Z

T9

SDRAM clock

EMIF – BUS ARBITRATION

Hold request from the host

HOLD

R6

I

HOLDA

B15

O

Hold request acknowledge to the host

TIMERS

TOUT1

TINP1

TOUT0

TINP0

G2

K3

O/Z

Timer 1 or general-purpose output

Timer 1 or general-purpose input

Timer 0 or general-purpose output

Timer 0 or general-purpose input

DMA ACTION COMPLETE

I

O/Z

I

M18

J18

DMAC3

DMAC2

DMAC1

DMAC0

E18

F19

E20

G16

O

I

DMA action complete

MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)

CLKS1

CLKR1

CLKX1

DR1

F4

H4

J4

External clock source (as opposed to internal)

Receive clock

I/O/Z

I

Transmit clock

E2

G4

F3

F2

Receive data

DX1

O/Z

I/O/Z

Transmit data

FSR1

FSX1

Receive frame sync

Transmit frame sync

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

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Signal Descriptions (Continued)

SIGNAL

NAME

†

DESCRIPTION

TYPE

NO.

MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)

CLKS0

K18

I

External clock source (as opposed to internal)

Receive clock

CLKR0

CLKX0

DR0

L21

K20

J21

I/O/Z

I

Transmit clock

Receive data

DX0

M21

P16

N16

O/Z

I/O/Z

Transmit data

FSR0

FSX0

Receive frame sync

Transmit frame sync

RESERVED FOR TEST

RSV0

RSV1

RSV2

RSV3

RSV4

RSV5

RSV6

RSV7

RSV8

RSV9

N21

K16

B13

B14

F13

C15

F7

I

Reserved for testing, pull-up with a dedicated 20-kΩ resistor

Reserved for testing, pull-down with a dedicated 20-kΩ resistor

Reserved (leave unconnected, do not connect to power or ground)

Reserved for testing, pull-up with a dedicated 20-kW resistor

Reserved (leave unconnected, do not connect to power or ground)

SUPPLY VOLTAGE PINS

I

O

I

D7

I

B5

I

F16

O

C14

C8

E19

E3

H11

H13

H9

J10

J12

J14

J19

J3

DV

S

3.3-V supply voltage

DD

J8

K11

K13

K15

K7

K9

L10

L12

L14

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

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Signal Descriptions (Continued)

SIGNAL

NAME

†

DESCRIPTION

SUPPLY VOLTAGE PINS (CONTINUED)

TYPE

NO.

L8

M11

M13

M15

M7

M9

N10

N12

N14

N19

N3

DV

S

3.3-V supply voltage

DD

N8

P11

P13

P9

U19

U3

W14

W8

A12

A13

B10

B12

B6

D15

D16

F10

F14

F8

CV

S

1.8-V supply voltage

DD

G13

G7

G8

K4

M3

M4

A3

A5

A7

A16

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

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Signal Descriptions (Continued)

SIGNAL

NAME

†

DESCRIPTION

SUPPLY VOLTAGE PINS (CONTINUED)

TYPE

NO.

A18

AA4

AA6

AA15

AA17

AA19

B2

B4

B19

C1

C3

C20

D2

D21

E1

E6

E8

CV

S

1.8-V supply voltage

DD

E10

E12

E14

E16

F5

F17

F21

G1

H5

H17

K5

K17

M5

M17

P5

P17

R21

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

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Signal Descriptions (Continued)

SIGNAL

NAME

†

DESCRIPTION

SUPPLY VOLTAGE PINS (CONTINUED)

TYPE

NO.

T1

T5

T17

U6

U8

U10

U12

U14

U16

U21

V1

V20

W2

W19

W21

Y3

Y18

Y20

AA11

AA12

F20

G18

H16

H18

L18

L19

L20

N20

P18

P19

R10

R14

U4

CV

S

1.8-V supply voltage

DD

V11

V12

V15

W13

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

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Signal Descriptions (Continued)

SIGNAL

NAME

†

DESCRIPTION

TYPE

NO.

GROUND PINS

C11

C16

C6

D5

G3

H10

H12

H14

H7

H8

J11

J13

J7

J9

K8

L7

L9

M8

N7

R3

V

SS

GND

Ground pins

A4

A6

A8

A15

A17

A19

AA3

AA5

AA7

AA14

AA16

AA18

B3

B18

B20

C2

C19

C21

D1

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

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Signal Descriptions (Continued)

SIGNAL

NAME

†

DESCRIPTION

GROUND PINS (CONTINUED)

TYPE

NO.

D20

E5

E7

E9

E11

E13

E15

E17

E21

F1

G5

G17

G21

H1

J5

J17

L5

L17

N5

V

SS

GND

Ground pins

N17

P21

R1

R5

R17

T21

U1

U5

U7

U9

U11

U13

U15

U17

V2

V21

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

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Signal Descriptions (Continued)

SIGNAL

NAME

†

DESCRIPTION

GROUND PINS (CONTINUED)

TYPE

NO.

W1

W3

W20

Y2

Y4

Y19

F18

G19

H15

J15

J16

K10

K12

K14

L11

L13

L15

M10

M12

M14

N11

N13

N15

N9

V

SS

GND

Ground pins

P10

P12

P14

P15

P7

P8

R19

T4

W11

W16

W6

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

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SIGNAL

NAME

†

DESCRIPTION

REMAINING UNCONNECTED PINS

TYPE

NO.

D13

D14

D18

D3

D6

F12

G12

G15

H19

H20

H21

L16

M16

M19

V19

V4

NC

Unconnected pins

W18

W4

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

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development support

Texas Instruments offers an extensive line of development tools for the ’C6000 generation of DSPs, including

tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and

fully integrate and debug software and hardware modules.

The following products support development of ’C6000-based applications:

Software Development Tools:

Assembly optimizer

Assembler/Linker

Simulator

Optimizing ANSI C compiler

Application algorithms

C/Assembly debugger and code profiler

Hardware Development Tools:

Extended development system (XDS ) emulator (supports ’C6000 multiprocessor system debug)

EVM (Evaluation Module)

The TMS320 DSP Development Support Reference Guide (SPRU011) contains information about

development-support products for all TMS320 family member devices, including documentation. See this

document for further information on TMS320 documentation or any TMS320 support products from Texas

Instruments. An additional document, the TMS320 Third-Party Support Reference Guide (SPRU052), contains

information about TMS320-related products from other companies in the industry. To receive TMS320 literature,

contact the Product Information Center at (800) 477-8924.

See Table 2 for a complete listing of development-support tools for the ’C6000. For information on pricing and

availability, contact the nearest TI field sales office or authorized distributor.

Table 2. 320C6000 Development-Support Tools

DEVELOPMENT TOOL

PLATFORM

Software

PART NUMBER

AD0345AS8500RF - Single User

AD0345BS8500RF - Multi-user

†

‡

Ada 95 Compiler

Sun Solaris 2.3

C Compiler/Assembler/Linker/Assembly Optimizer

Simulator

Win32

SPARC Solaris

Win32

TMDX3246855-07

TMDX324655-07

TMDS3246851-07

TMDS3246551-07

TMDX324016X-07

Simulator

SPARC Solaris

XDS510 Debugger/Emulation Software

Win32, Windows NT

Hardware

§

XDS510 Emulator

PC

TMDS00510

¶

XDS510WS Emulator

SCSI

TMDS00510WS

Software/Hardware

PC/Win95/Windows NT

EVM Evaluation Kit

TMDX3260A6201

TMDX326006201

EVM Evaluation Kit (including TMDX3246855–07)

†

‡

§

¶

Contact IRVINE Compiler Corporation (949) 250-1366 to order.

NT support estimated availability 1Q00.

Includes XDS510 board and JTAG emulation cable. TMDX324016X-07 C-source Debugger/Emulation software is not included.

Includes XDS510WS box, SCSI cable, power supply, and JTAG emulation cable.

XDS, XDS510, and XDS510WS are trademarks of Texas Instruments Incorporated.

Win32 and Windows NT are trademarks of Microsoft Corporation.

SPARC is a trademark of SPARC International, Inc.

Solaris is a trademark of Sun Microsystems, Inc.

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device and development-support tool nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320

devices and support tools. Each TMS320 member has one of three prefixes: SMX, SM, or SMJ. Texas

Instruments recommends two of three possible prefix designators for support tools: TMDX and TMDS. These

prefixes represent evolutionary stages of product development from engineering prototypes (SMX/TMDX)

through fully qualified production devices/tools (SMJ/TMDS). This development flow follows.

Device development evolutionary flow:

SMX

SM

Experimental device that is not necessarily representative of the final device’s electrical

specifications, 25°C tested, military/industrial ceramic dimpled Ball Grid Array package

Fully TI-qualified production device; offered in extended temperature ranges: –40°C to +90°C (S

range), and –55°C to +115°C (W range); in ceramic dimpled BGA package

SMJ

Fully SMD-qualified production device, –55°C to +115°C (W temperature range), in the ceramic

dimpled Ball Grid Array package processed to MIL-PRF-38535

Support tool development evolutionary flow:

TMDX

Development-support product that has not yet completed Texas Instruments internal qualification

testing.

TMDS

Fully qualified development-support product

TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:

“Developmental product is intended for internal evaluation purposes.”

TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability

of the device have been demonstrated fully. TI’s standard warranty applies.

Predictions show that prototype devices (SMX or SM) have a greater failure rate than the standard production

devices. Texas Instruments recommends that these devices not be used in any production system because their

expected end-use failure rate still is undefined. Only qualified production devices are to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type

(GLP) and the device speed range in megahertz (for example, 15 is 150 MHz). Figure 5 provides a legend for

reading the complete device name.

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device and development-support tool nomenclature (continued)

SMJ 320

C

6201B GLP

15

W

PREFIX

DEVICE SPEED RANGE

SMX = Experimental device

SMJ = MIL-PRF-38535, QML

15 = 150 MHz

16 = 160 MHz

20 = 200 MHz

SM

=

Commercial

processing

TEMPERATURE RANGE

S

= –40 to 90°C, extended temperature

W = –55 to 115°C, extended temperature

DEVICE FAMILY

320 = TMS320 family

†

PACKAGE TYPE

GLP = 429-ball ceramic BGA

TECHNOLOGY

C = CMOS

DEVICE

’6x DSP:

6201

6201B

6203

6701

†

BGA

=

Ball Grid Array

Figure 5. TMS320 Device Nomenclature (Including SMJ320C6201B)

documentation support

Extensive documentation supports all TMS320 family generations of devices from product announcement

through applications development. The types of documentation available include: data sheets, such as this

document, with design specifications; complete user’s reference guides for all devices; technical briefs;

development-support tools; and hardware and software applications. The following is a brief, descriptive list of

support documentation specific to the ’C6x devices:

The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the

’C6000 CPU architecture, instruction set, pipeline, and associated interrupts.

The TMS320C6000 Peripherals Reference Guide (literature number SPRU190) describes the functionality of

the peripherals available on ’C6x devices, such as the external memory interface (EMIF), host-port interface

(HPI), multichannel buffered serial ports (McBSPs), direct-memory-access (DMA), enhanced

direct-memory-access (EDMA) controller, expansion bus (XB), clocking and phase-locked loop (PLL); and

power-down modes. This guide also includes information on internal data and program memories.

The TMS320C6000 Programmer’s Guide (literature number SPRU198) describes ways to optimize C and

assembly code for ’C6x devices and includes application program examples.

The TMS320C6x C Source Debugger User’s Guide (literature number SPRU188) describes how to invoke the

’C6x simulator and emulator versions of the C source debugger interface and discusses various aspects of the

debugger, including: command entry, code execution, data management, breakpoints, profiling, and analysis.

The TMS320C6x Peripheral Support Library Programmer’s Reference (literature number SPRU273) describes

the contents of the ’C6x peripheral support library of functions and macros. It lists functions and macros both

by header file and alphabetically, provides a complete description of each, and gives code examples to show

how they are used.

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documentation support (continued)

TMS320C6000 Assembly Language Tools User’s Guide (literature number SPRU186) describes the assembly

language tools (assembler, linker, and other tools used to develop assembly language code), assembler

directives, macros, common object file format, and symbolic debugging directives for the ’C6000 generation of

devices.

The TMS320C6x Evaluation Module Reference Guide (literature number SPRU269) provides instructions for

installing and operating the ’C6x evaluation module. It also includes support software documentation,

application programming interfaces, and technical reference material.

TMS320C62x Multichannel Evaluation Module User’s Guide (literature number SPRU285) provides

instructions for installing and operating the ’C62x multichannel evaluation module. It also includes support

software documentation, application programming interfaces, and technical reference material.

TMS320C62x Multichannel Evaluation Module Technical Reference (SPRU308) provides provides technical

reference information for the ’C62x multichannel evaluation module (McEVM). It includes support software

documentation, application programming interface references, and hardware descriptions for the ’C62x

McEVM.

TMS320C6000 DSP/BIOS User’s Guide (literature number SPRU303) describes how to use DSP/BIOS tools

and APIs to analyze embedded real-time DSP applications.

Code Composer User’s Guide (literature number SPRU296) explains how to use the Code Composer

development environment to build and debug embedded real-time DSP applications.

Code Composer Studio Tutorial (literature number SPRU301) introduces the Code Composer Studio integrated

development environment and software tools.

The TMS320C6000 Technical Brief (literature number SPRU197) gives an introduction to the ’C62x/C67x

devices, associated development tools, and third-party support.

A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support DSP research and

education. The TMS320 newsletter, Details on Signal Processing, is published quarterly and distributed to

update TMS320 customers on product information. The TMS320 DSP bulletin board service (BBS) provides

access to information pertaining to the TMS320 family, including documentation, source code, and object code

for many DSP algorithms and utilities. The BBS can be reached at 281/274-2323.

Information regarding TI DSP products is also available on the Worldwide Web at http://www.ti.com uniform

resource locator (URL).

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clock PLL

All of the ’C62x clocks are generated from a single source through the CLKIN pin. This source clock either drives

the PLL, which generates the internal CPU clock, or bypasses the PLL to become the CPU clock.

To use the PLL to generate the CPU clock, the filter circuit shown in Figure 6 must be properly designed. For

the ’C6201B, it must be powered by the I/O voltage (3.3 V).

To configure the ’C62x PLL clock for proper operation, see Figure 6 and Table 3. To minimize the clock jitter,

a single clean power supply should power both the ’C62x device and the external clock oscillator circuit. The

minimum CLKIN rise and fall times should also be observed. See the input and output clocks section for input

clock timing requirements.

0 1 0 – ’C6201B CLKOUT1 Frequency Range 130–233 MHz

0 0 1 – ’C6201B CLKOUT1 Frequency Range 65–200 MHz

0 0 0 – ’C6201B CLKOUT1 Frequency Range 50–140 MHz

3.3 V 2.5 V

3 OUT

’C6201B

PLLV

PLLF

EMIF

R1

CLKOUT1

CLKOUT2

SSCLK

1 IN

CLKOUT

2

PLLG

10 µF

0.1 µF C1 C2

GND

(Bypass)

SDCLK

CLKIN

1 1 – MULT×4

0 1 – Reserved

1 0 – Reserved

0 0 – MULT×1

f(CLKOUT)=f(CLKIN)×4

f(CLKOUT)=f(CLKIN)

NOTES: A. For the ’C6201B CLKMODE x4, values for C1, C2, and R1 are fixed and apply to all valid frequency ranges of CLKIN and CLKOUT.

B. For CLKMODE x1, the PLL is bypassed and all six external PLL components can be removed. For this case, the PLLV terminal has

to be connected to a clean supply and the PLLG and PLLF terminals should be tied together.

C. Due to overlap of frequency ranges when choosing the PLLFREQ, more than one frequency range can contain the CLKOUT1

frequency. Choose the lowest frequency range that includes the desired frequency. For example, for CLKOUT1 = 133 MHz, a

PLLFREQ value of 000b should be used for the ’C6201B. For CLKOUT1 = 200 MHz, PLLFREQ should be set to 001b for the

’C6201B. PLLFREQ values other than 000b, 001b, and 010b are reserved.

D. For the ’C6201B, the 3.3-V supply for the EMI filter (and PLLV) must be from the same 3.3-V power plane supplying the I/O voltage,

DV

.

DD

Figure 6. PLL Block Diagram

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I

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SGUS031 – APRIL 2000

clock PLL (continued)

Table 3. 320C6201B PLL Component Selection Table

CPU CLOCK

CLKOUT2

CLKIN

RANGE

(MHz)

TYPICAL

R1

(Ω)

C1

(nF)

C2

(pF)

FREQUENCY

(CLKOUT1)

CLKMODE

RANGE

(MHz)

LOCK TIME

†

(µs)

RANGE (MHz)

x4

12.5–50

50–200

25–100

60.4

27

560

75

†

Under some operating conditions, the maximum PLL lock time may vary as much as 150% from the specified typical value. For example, if the

typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs.

power supply sequencing

For the ’C6201B device, the 1.8-V supply powers the core and the 3.3-V supply powers the I/O buffers. The core

supply should be powered up first, or at the same time as the I/O buffers. This is to ensure that the I/O buffers

have valid inputs from the core before the output buffers are powered up, thus preventing bus contention with

other chips on the board.

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I

G

A

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SGUS031 – APRIL 2000

absolute maximum ratings over operating case temperature range (unless otherwise noted)^†

Supply voltage range, CV (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 2.3 V

DD

Supply voltage range, DV (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V

DD

Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V

Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V

Operating case temperature range T : (S temp version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40_C to 90_C

C

(W temp version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55_C to 115_C

Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55_C to 150_C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to V

SS

.

recommended operating conditions

’C6201B

UNIT

MIN NOM

MAX

1.89

3.46

0

CV

DV

Supply voltage

1.71

3.14

0

1.8

3.30

0

V

DD

Supply voltage

V

Supply ground

V

SS

High-level input voltage

Low-level input voltage

High-level output current

Low-level output current

2.0

V

IH

IL

0.8

–12

12

V

I

mA

OH

OL

I

S temp version

W temp version

–40

–55

90

‡

T

C

_C

Operating case temperature

115

‡

Case temperature is measured at package bottom. There is no direct thermal path from the chip through the lid.

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SGUS031 – APRIL 2000

electrical characteristics over recommended ranges of supply voltage and operating case

temperature (unless otherwise noted)

’C6201B

PARAMETER

High-level output voltage

TEST CONDITIONS

UNIT

V

MIN

TYP

MAX

DV = MIN,

DD

V

2.4

OH

I

= MAX

OH

DV = MIN,

DD

Low-level output voltage

0.6

V

OL

I

OL

= MAX

†

I

Input current

V = V to DV

±10

uA

I

SS

DD

Off-state output current

V

O

= DV or 0 V

OZ

DD

CV = NOM,

CPU clock = 167 MHz

DD

‡

I

Supply current, CPU + CPU memory access

380

240

90

mA

DD2V

CV = NOM,

DD

§

Supply current, peripherals

DD2V

DD3V

CPU clock = 167 MHz

DV = NOM,

DD

¶

Supply current, I/O pins

CPU clock = 167 MHz

C

Input capacitance

Output capacitance

15

pF

i

o

†

‡

TMS and TDI are not included due to internal pullups.

TRST is not included due to internal pulldown.

Measured with average CPU activity:

50% of time:

8 instructions per cycle, 32-bit DMEM access per cycle

2 instructions per cycle, 16-bit DMEM access per cycle

§

¶

Measured with average peripheral activity:

50% of time: Timers at max rate, McBSPs at E1 rate, and DMA burst transfer between DMEM and SDRAM

50% of time: Timers at max rate, McBSPs at E1 rate, and DMA servicing McBSPs

Measured with average I/O activity (30-pF load):

25% of time:

50% of time:

Reads from external SDRAM

Writes to external SDRAM

No activity

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2

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I

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A

L

SGUS031 – APRIL 2000

PARAMETER MEASUREMENT INFORMATION

I

OL

Tester Pin

Electronics

Output

Under

Test

50 Ω

V

ref

†

C = 30 pF

T

I

OH

†

Typical distributed load circuit capacitance

Figure 7. TTL-Level Outputs

signal transition levels

All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels.

V

ref

= 1.5 V

Figure 8. Input and Output Voltage Reference Levels for AC Timing Measurements

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

SM 3 2 0 C6 2 0 1 B, SM J 32 0C 62 01 B

DI GI TAL SI G NAL P RO C ES S O R

SGUS031 – APRIL 2000

INPUT AND OUTPUT CLOCKS

timing requirements for CLKIN (see Figure 9)

’C6201B-15

’C6201B-20

CLKMODE

= x1

CLKMODE

= x4

CLKMODE

= x1

NO.

UNIT

= x4

MIN MAX

26.7

MIN MAX

6.67

MIN MAX

1

2

3

4

t

Cycle time, CLKIN

20

*8

*5

5

*2.35

*0.6

ns

c(CLKIN)

w(CLKINH)

w(CLKINL)

t(CLKIN)

Pulse duration, CLKIN high

Pulse duration, CLKIN low

Transition time, CLKIN

*9.8

*2.7

*9.8

*2.7

*5

*0.6

*Not production tested.

1

4

2

CLKIN

3

4

Figure 9. CLKIN Timings

switching characteristics for CLKOUT1^†‡(see Figure 10)

’C6201B

CLKMODE = x4

CLKMODE = x1

NO.

PARAMETER

UNIT

MIN

MAX

MIN

MAX

1

2

3

4

t

Cycle time, CLKOUT1

*P – 0.7

*P + 0.7

*P – 0.7

*PH – 0.5

*PL – 0.5

*P + 0.7

*PH + 0.5

*PL + 0.5

*0.6

ns

c(CKO1)

w(CKO1H)

w(CKO1L)

t(CKO1)

Pulse duration, CLKOUT1 high

Pulse duration, CLKOUT1 low

Transition time, CLKOUT1

*(P/2) – 0.5 *(P/2 ) + 0.5

*0.6

†

‡

PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns.

P = 1/CPU clock frequency in nanoseconds (ns).

*Not production tested.

1

4

2

CLKOUT1

3

4

Figure 10. CLKOUT1 Timings

P

R

s

e

a

O

D

n

U

C

T

P

R

E

V

I

E

W

i

n

f

d

n

o

e

r

m

a

t

i

p

a

o

m

l

n

c

o

n

c

e

C

s

r

n

h

s

a

I

w

p

r

e

u

o

r

m

u

d

u

t

e

c

t

s

i

d

n

a

e

t

a

h

e

f

o

d

r

m

a

t

i

v

e

o the r

o

r

d

e

i

g

p

n

r

h

a

s

e

o

f

v

e

l

o

e

.

n

t

.

r

n

a

c

t

i

s

i

c

t

s

a

n

s

p

c

n

i

f

i

c

e

a

t

i

o

s

a

s

r

e

d

e

u

s

i

g

e

o

s

T

e

u

x

c

a

t

s

t

r

n

t r

not ice .

s

e

r

v

s

t

h

e

r

i

g

h

t

o

c

h

g

o

d

i

c

o

n

t

i

n

e

t

h

e

p

r

o

d

i

t

h

t

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I

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A

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SGUS031 – APRIL 2000

INPUT AND OUTPUT CLOCKS (CONTINUED)

switching characteristics for CLKOUT2^†(see Figure 11)

’C6201B

MIN

NO.

PARAMETER

UNIT

MAX

1

2

3

4

t

Cycle time, CLKOUT2

*2P – 0.7

*P – 0.9

*P – 0.7

*2P + 0.7

*P + 0.7

*P + 0.9

*0.6

ns

c(CKO2)

w(CKO2H)

w(CKO2L)

t(CKO2)

Pulse duration, CLKOUT2 high

Pulse duration, CLKOUT2 low

Transition time, CLKOUT2

†

P = 1/CPU clock frequency in ns.

*Not production tested.

1

4

2

CLKOUT2

3

4

Figure 11. CLKOUT2 Timings

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SGUS031 – APRIL 2000

INPUT AND OUTPUT CLOCKS (CONTINUED)

SDCLK, SSCLK timing parameters

SDCLK timing parameters are the same as CLKOUT2 parameters.

SSCLK timing parameters are the same as CLKOUT1 or CLKOUT2 parameters, depending on SSCLK

configuration.

switching characteristics for the relation of SSCLK, SDCLK, and CLKOUT2 to CLKOUT1

(see Figure 12)^†

’C6201B

NO.

PARAMETER

UNIT

MIN

MAX

1

2

3

4

t

Delay time, CLKOUT1 edge to SSCLK edge

(P/2) + 0.2

(P/2) – 1

(P/2) + 4.2

(P/2) + 2.4

ns

d(CKO1-SSCLK)

d(CKO1-SSCLK1/2)

d(CKO1-CKO2)

Delay time, CLKOUT1 edge to SSCLK edge (1/2 clock rate)

Delay time, CLKOUT1 edge to CLKOUT2 edge

Delay time, CLKOUT1 edge to SDCLK edge

*(P/2) – 1 *(P/2) + 2.4

(P/2) – 1 (P/2) + 2.4

d(CKO1-SDCLK)

†

P = 1/CPU clock frequency in ns.

*Not production tested.

CLKOUT1

1

2

3

4

SSCLK

SSCLK (1/2rate)

CLKOUT2

SDCLK

Figure 12. Relation of CLKOUT2, SDCLK, and SSCLK to CLKOUT1

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SGUS031 – APRIL 2000

ASYNCHRONOUS MEMORY TIMING

timing requirements for asynchronous memory cycles^†(see Figure 13 and Figure 14)

’C6201B

NO.

UNIT

MIN MAX

6

7

t

Setup time, read EDx valid before CLKOUT1 high

Hold time, read EDx valid after CLKOUT1 high

Setup time, ARDY valid before CLKOUT1 high

Hold time, ARDY valid after CLKOUT1 high

4.0

0.8

3.0

1.8

ns

su(EDV-CKO1H)

h(CKO1H-EDV)

su(ARDY-CKO1H)

h(CKO1H-ARDY)

10

11

†

To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. If ARDY does meet setup or hold

time, it may be recognized in the current cycle or the next cycle. Thus, ARDY can be an asynchronous input.

switching characteristics for asynchronous memory cycles^‡(see Figure 13 and Figure 14)

’C6201B

NO.

PARAMETER

UNIT

MIN

MAX

4.0

1

2

t

Delay time, CLKOUT1 high to CEx valid

Delay time, CLKOUT1 high to BEx valid

Delay time, CLKOUT1 high to BEx invalid

Delay time, CLKOUT1 high to EAx valid

Delay time, CLKOUT1 high to EAx invalid

Delay time, CLKOUT1 high to AOE valid

Delay time, CLKOUT1 high to ARE valid

Delay time, CLKOUT1 high to EDx valid

Delay time, CLKOUT1 high to EDx invalid

Delay time, CLKOUT1 high to AWE valid

–0.2

ns

d(CKO1H-CEV)

d(CKO1H-BEV)

d(CKO1H-BEIV)

d(CKO1H-EAV)

d(CKO1H-EAIV)

d(CKO1H-AOEV)

d(CKO1H-AREV)

d(CKO1H-EDV)

d(CKO1H-EDIV)

d(CKO1H-AWEV)

4.0

3

*–0.2

4

4.0

5

*–0.2

–0.2

8

4.0

9

12

13

14

*–0.2

–0.2

4.0

‡

The minimum delay is also the minimum output hold after CLKOUT1 high.

*Not production tested.

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SGUS031 – APRIL 2000

ASYNCHRONOUS MEMORY TIMING (CONTINUED)

Not ready = 2

Setup = 2

Strobe = 5

HOLD = 1

CLKOUT1

CEx

1

2

4

1

3

BE[3:0]

EA[21:2]

ED[31:0]

AOE

5

7

6

8

9

ARE

AWE

11

10

ARDY

Figure 13. Asynchronous Memory Read Timing

Not ready = 2

Setup = 2

Strobe = 5

HOLD = 1

CLKOUT1

1

2

4

1

3

5

CEx

BE[3:0]

EA[21:2]

12

13

14

ED[31:0]

AOE

ARE

14

AWE

11

10

ARDY

Figure 14. Asynchronous Memory Write Timing

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SGUS031 – APRIL 2000

SYNCHRONOUS-BURST MEMORY TIMING

timing requirements for synchronous-burst SRAM cycles (full-rate SSCLK) (see Figure 15)

’C6201B

NO.

UNIT

MIN

1.7

MAX

7

8

t

Setup time, read EDx valid before SSCLK high

Hold time, read EDx valid after SSCLK high

ns

su(EDV-SSCLKH)

1.5

h(SSCLKH-EDV)

switching characteristics for synchronous-burst SRAM cycles^†(full-rate SSCLK)

(see Figure 15 and Figure 16)

’C6201B

MIN

NO.

PARAMETER

UNIT

MAX

1

2

t

Output setup time, CEx valid before SSCLK high

Output hold time, CEx valid after SSCLK high

Output setup time, BEx valid before SSCLK high

Output hold time, BEx invalid after SSCLK high

Output setup time, EAx valid before SSCLK high

Output hold time, EAx invalid after SSCLK high

Output setup time, SSADS valid before SSCLK high

Output hold time, SSADS valid after SSCLK high

Output setup time, SSOE valid before SSCLK high

Output hold time, SSOE valid after SSCLK high

Output setup time, EDx valid before SSCLK high

Output hold time, EDx invalid after SSCLK high

Output setup time, SSWE valid before SSCLK high

Output hold time, SSWE valid after SSCLK high

0.5P – 1.3

ns

osu(CEV-SSCLKH)

oh(SSCLKH-CEV)

osu(BEV-SSCLKH)

oh(SSCLKH-BEIV)

osu(EAV-SSCLKH)

oh(SSCLKH-EAIV)

osu(ADSV-SSCLKH)

oh(SSCLKH-ADSV)

osu(OEV-SSCLKH)

oh(SSCLKH-OEV)

osu(EDV-SSCLKH)

oh(SSCLKH-EDIV)

osu(WEV-SSCLKH)

0.5P – 2.3

0.5P – 1.3

*0.5P – 2.3

0.5P – 1.3

*0.5P – 2.3

0.5P – 1.3

0.5P – 2.3

0.5P – 1.3

0.5P – 2.3

0.5P – 1.3

*0.5P – 2.3

0.5P – 1.3

0.5P – 2.3

3

4

5

6

9

10

11

12

13

14

15

16

oh(SSCLKH-WEV)

†

When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.

For CLKMODE x1, 0.5P is defined as PH (pulse duration of CLKIN high) for all output setup times; 0.5P is defined as PL (pulse duration of CLKIN

low) for all output hold times.

*Not production tested.

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,

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SM J 32 0C 62 01 B

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I

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A

L

SGUS031 – APRIL 2000

SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)

SSCLK

CEx

1

2

3

5

4

BE[3:0]

BE1

A1

BE2

BE3

BE4

6

EA[21:2]

A2

7

A3

8

A4

Q1

Q2

Q3

Q4

ED[31:0]

SSADS

9

10

11

12

SSOE

SSWE

Figure 15. SBSRAM Read Timing (Full-Rate SSCLK)

SSCLK

CEx

1

3

2

4

BE[3:0]

BE1

A1

BE2

A2

BE3

A3

BE4

5

6

EA[21:2]

ED[31:0]

A4

13

14

D4

D1

D2

D3

9

10

SSADS

SSOE

15

16

SSWE

Figure 16. SBSRAM Write Timing (Full-Rate SSCLK)

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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

S M 32 0C 6 2 01 B, S MJ 3 20 C 6 20 1 B

DI GI TA L SI GN AL P RO CE SS OR

SGUS031 – APRIL 2000

SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)

timing requirements for synchronous-burst SRAM cycles (half-rate SSCLK)

(see Figure 17)

’C6201B

NO.

UNIT

MIN

2.5

MAX

7

8

t

Setup time, read EDx valid before SSCLK high

Hold time, read EDx valid after SSCLK high

ns

su(EDV-SSCLKH)

1.5

h(SSCLKH-EDV)

switching characteristics for synchronous-burst SRAM cycles^†(half-rate SSCLK)

(see Figure 17 and Figure 18)

’C6201B

MIN

NO.

PARAMETER

UNIT

MAX

1

2

t

Output setup time, CEx valid before SSCLK high

Output hold time, CEx valid after SSCLK high

Output setup time, BEx valid before SSCLK high

Output hold time, BEx invalid after SSCLK high

Output setup time, EAx valid before SSCLK high

Output hold time, EAx invalid after SSCLK high

Output setup time, SSADS valid before SSCLK high

Output hold time, SSADS valid after SSCLK high

Output setup time, SSOE valid before SSCLK high

Output hold time, SSOE valid after SSCLK high

Output setup time, EDx valid before SSCLK high

Output hold time, EDx invalid after SSCLK high

Output setup time, SSWE valid before SSCLK high

1.5P – 3

0.5P – 1.5

1.5P – 3

ns

osu(CEV-SSCLKH)

oh(SSCLKH-CEV)

osu(BEV-SSCLKH)

oh(SSCLKH-BEIV)

osu(EAV-SSCLKH)

oh(SSCLKH-EAIV)

osu(ADSV-SSCLKH)

oh(SSCLKH-ADSV)

osu(OEV-SSCLKH)

oh(SSCLKH-OEV)

osu(EDV-SSCLKH)

oh(SSCLKH-EDIV)

osu(WEV-SSCLKH)

3

4

*0.5P – 1.5

1.5P – 3

5

6

*0.5P – 1.5

1.5P – 3

9

10

11

12

13

14

15

0.5P – 1.5

1.5P – 3

0.5P – 1.5

1.5P – 3

*0.5P – 1.5

1.5P – 3

16

t

Output hold time, SSWE valid after SSCLK high

0.5P – 1.5

ns

oh(SSCLKH-WEV)

†

When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.

For CLKMODE x1:

1.5P = P + PH, where P = 1/CPU clock frequency, and PH = pulse duration of CLKIN high.

0.5P = PL, where PL = pulse duration of CLKIN low.

*Not production tested.

P

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r

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d

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t

s

t

r

n

t r

not ice .

s

er

v

s

t

h

e

r

i

g

h

t

to

c

h

g

o

d

i

c

o

n

ti

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t

h

e

p

r

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i

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h

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38

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

S

D

M

3

I

2

T

0

A

C

L

6

2

0

S

1

I

B

G

,

N

SM J 32 0C 62 01 B

P RO C ES S O R

I

G

A

L

SGUS031 – APRIL 2000

SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)

SSCLK

1

2

CEx

3

4

6

BE[3:0]

BE1

BE2

A2

BE3

A3

BE4

5

A1

A4

8

EA[21:2]

7

Q1

Q2

Q3

10

Q4

ED[31:0]

SSADS

9

11

12

SSOE

SSWE

Figure 17. SBSRAM Read Timing (1/2 Rate SSCLK)

SSCLK

1

3

2

CEx

BE[3:0]

4

6

BE1

BE2

A2

BE3

A3

BE4

5

EA[21:2]

A1

A4

Q4

13

14

10

Q1

Q2

Q3

ED[31:0]

9

SSADS

SSOE

15

16

SSWE

Figure 18. SBSRAM Write Timing (1/2 Rate SSCLK)

39

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

S M 32 0C 6 2 01 B, S MJ 3 20 C 6 20 1 B

DI GI TA L SI GN AL P RO CE SS OR

SGUS031 – APRIL 2000

SYNCHRONOUS DRAM TIMING

timing requirements for synchronous DRAM cycles (see Figure 19)

’C6201B

NO.

UNIT

MIN MAX

7

8

t

Setup time, read EDx valid before SDCLK high

Hold time, read EDx valid after SDCLK high

0.5

3

ns

su(EDV-SDCLKH)

h(SDCLKH-EDV)

switching characteristics for synchronous DRAM cycles^†(see Figure 19–Figure 24)

’C6201B

NO.

PARAMETER

UNIT

MIN

MAX

1

2

t

Output setup time, CEx valid before SDCLK high

Output hold time, CEx valid after SDCLK high

Output setup time, BEx valid before SDCLK high

Output hold time, BEx invalid after SDCLK high

Output setup time, EAx valid before SDCLK high

Output hold time, EAx invalid after SDCLK high

Output setup time, SDCAS valid before SDCLK high

Output hold time, SDCAS valid after SDCLK high

Output setup time, EDx valid before SDCLK high

Output hold time, EDx invalid after SDCLK high

Output setup time, SDWE valid before SDCLK high

Output hold time, SDWE valid after SDCLK high

Output setup time, SDA10 valid before SDCLK high

Output hold time, SDA10 invalid after SDCLK high

Output setup time, SDRAS valid before SDCLK high

Output hold time, SDRAS valid after SDCLK high

1.5P – 3.5

0.5P – 1

ns

osu(CEV-SDCLKH)

oh(SDCLKH-CEV)

3

1.5P – 3.5

*0.5P – 1

1.5P – 3.5

*0.5P – 1

1.5P – 3.5

0.5P – 1

osu(BEV-SDCLKH)

oh(SDCLKH-BEIV)

osu(EAV-SDCLKH)

oh(SDCLKH-EAIV)

osu(SDCAS-SDCLKH)

oh(SDCLKH-SDCAS)

osu(EDV-SDCLKH)

oh(SDCLKH-EDIV)

osu(SDWE-SDCLKH)

oh(SDCLKH-SDWE)

osu(SDA10V-SDCLKH)

oh(SDCLKH-SDA10IV)

osu(SDRAS-SDCLKH)

oh(SDCLKH-SDRAS)

4

5

6

9

10

11

12

13

14

15

16

17

18

1.5P – 3.5

*0.5P – 1

1.5P – 3.5

0.5P – 1

1.5P – 3.5

*0.5P – 1

1.5P – 3.5

0.5P – 1

†

When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.

For CLKMODE x1:

1.5P = P + PH, where P = 1/CPU clock frequency, and PH = pulse duration of CLKIN high.

0.5P = PL, where PL = pulse duration of CLKIN low.

*Not production tested.

P

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to

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40

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

S

D

M

3

I

2

T

0

A

C

L

6

2

0

S

1

I

B

G

,

N

SM J 32 0C 62 01 B

P RO C ES S O R

I

G

A

L

SGUS031 – APRIL 2000

SYNCHRONOUS DRAM TIMING (CONTINUED)

READ

SDCLK

CEx

1

5

2

3

4

BE[3:0]

EA[15:2]

BE1

BE2

CA3

BE3

7

6

CA1

CA2

8

D1

D2

D3

ED[31:0]

15

9

16

10

SDA10

SDRAS

SDCAS

SDWE

Figure 19. Three SDRAM Read Commands

WRITE

SDCLK

CEx

1

2

3

4

BE[3:0]

BE1

CA1

BE2

CA2

D2

BE3

5

6

EA[15:2]

CA3

D3

11

12

D1

ED[31:0]

SDA10

15

16

SDRAS

SDCAS

9

10

14

13

SDWE

Figure 20. Three SDRAM WRT Commands

41

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

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D

M

3

I

2

TA

0

C

L

6

2

0

S

1

I

B

G

,

N

S MJ 3 20 C 6 20 1 B

P RO CE SS OR

I

G

A

L

SGUS031 – APRIL 2000

SYNCHRONOUS DRAM TIMING (CONTINUED)

ACTV

SDCLK

1

2

CEx

BE[3:0]

5

Bank Activate/Row Address

EA[15:2]

ED[31:0]

15

Row Address

SDA10

17

18

SDRAS

SDCAS

SDWE

Figure 21. SDRAM ACTV Command

DCAB

SDCLK

1

2

CEx

BE[3:0]

EA[15:2]

ED[31:0]

15

16

SDA10

17

18

SDRAS

SDCAS

13

14

SDWE

Figure 22. SDRAM DCAB Command

42

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

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3

I

2

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0

A

C

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6

2

0

S

1

I

B

G

,

N

SM J 32 0C 62 01 B

P RO C ES S O R

I

G

A

L

SGUS031 – APRIL 2000

SYNCHRONOUS DRAM TIMING (CONTINUED)

REFR

SDCLK

CEx

1

2

BE[3:0]

EA[15:2]

ED[31:0]

SDA10

SDRAS

17

18

9

10

SDCAS

SDWE

Figure 23. SDRAM REFR Command

MRS

SDCLK

1

2

6

CEx

BE[3:0]

5

EA[15:2]

ED[31:0]

SDA10

MRS Value

17

18

10

14

SDRAS

9

SDCAS

SDWE

13

Figure 24. SDRAM MRS Command

43

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

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3

I

2

TA

0

C

L

6

2

0

S

1

I

B

G

,

N

S MJ 3 20 C 6 20 1 B

P RO CE SS OR

I

G

A

L

SGUS031 – APRIL 2000

HOLD/HOLDA TIMING

timing requirements for the HOLD/HOLDA cycles^†(see Figure 25)

’C6201B

NO.

UNIT

MIN MAX

1

2

t

Setup time, HOLD high before CLKOUT1 high

Hold time, HOLD low after CLKOUT1 high

*1

*4

ns

su(HOLDH-CKO1H)

h(CKO1H-HOLDL)

†

HOLD is synchronized internally. Therefore, if setup and hold times are not met, it will either be recognized in the current cycle or in the next cycle.

Thus, HOLD can be an asynchronous input.

*Not production tested.

switching characteristics for the HOLD/HOLDA cycles^‡(see Figure 25)

’C6201B

NO.

PARAMETER

UNIT

MIN

*4P

*P

MAX

§

3

4

5

6

7

8

9

t

Response time, HOLD low to EMIF Bus high impedance

Response time, EMIF Bus high impedance to HOLDA low

Response time, HOLD high to HOLDA high

ns

R(HOLDL-BHZ)

R(BHZ-HOLDAL)

R(HOLDH-HOLDAH)

d(CKO1H-HOLDAL)

d(CKO1H-BHZ)

*2P

*7P

8

*4P

*1

Delay time, CLKOUT1 high to HOLDA valid

¶

Delay time, CLKOUT1 high to EMIF Bus high impedance

*3

*11

*6P

¶

Delay time, CLKOUT1 high to EMIF Bus low impedance

*3

d(CKO1H-BLZ)

Response time, HOLD high to EMIF Bus low impedance

*3P

R(HOLDH-BLZ)

‡

P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.

*Not production tested.

§

All pending EMIF transactions are allowed to complete before HOLDA is asserted. The worst cases for this is an asynchronous read or write

with external ARDY used or a minimum of eight consecutive SDRAM reads or writes when RBTR8 = 1. If no bus transactions are occurring, then

the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.

¶

EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, and SDWE.

DSP Owns Bus

External Requester

DSP Owns Bus

5

4

9

2

3

CLKOUT1

HOLD

2

1

6

HOLDA

7

8

†

EMIF Bus

’C62x

Ext Req

’C62x

†

EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, and SDWE.

Figure 25. HOLD/HOLDA Timing

44

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

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3

I

2

T

0

A

C

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6

2

0

S

1

I

B

G

,

N

SM J 32 0C 62 01 B

P RO C ES S O R

I

G

A

L

SGUS031 – APRIL 2000

RESET TIMING

timing requirements for reset (see Figure 26)

’C6201B

NO.

UNIT

MIN

MAX

CLKOUT1

cycles

†

Width of the RESET pulse (PLL stable)

*10

1

t

w(RST)

‡

Width of the RESET pulse (PLL needs to sync up)

250

µs

†

‡

This parameter applies to CLKMODE x1 when CLKIN is stable and applies to CLKMODE x4 when CLKIN and PLL are stable.

This parameter only applies to CLKMODE x4. The RESET signal is not connected internally to the clock PLL circuit. The PLL, however, may

need up to 250 µs to stabilize following device power up or after PLL configuration has been changed. During that time, RESET must be asserted

to ensure proper device operation. See the clock PLL section for PLL lock times.

*Not production tested.

switching characteristics during reset^§¶(see Figure 26)

’C6201B

NO.

PARAMETER

UNIT

MIN

MAX

CLKOUT1

cycles

2

t

Response time to change of value in RESET signal

2

R(RST)

3

4

t

Delay time, CLKOUT1 high to CLKOUT2 invalid

Delay time, CLKOUT1 high to CLKOUT2 valid

Delay time, CLKOUT1 high to SDCLK invalid

Delay time, CLKOUT1 high to SDCLK valid

Delay time, CLKOUT1 high to SSCLK invalid

Delay time, CLKOUT1 high to SSCLK valid

Delay time, CLKOUT1 high to low group invalid

Delay time, CLKOUT1 high to low group valid

Delay time, CLKOUT1 high to high group invalid

Delay time, CLKOUT1 high to high group valid

Delay time, CLKOUT1 high to Z group high impedance

Delay time, CLKOUT1 high to Z group valid

*–1

ns

d(CKO1H-CKO2IV)

d(CKO1H-CKO2V)

d(CKO1H-SDCLKIV)

d(CKO1H-SDCLKV)

d(CKO1H-SSCKIV)

d(CKO1H-SSCKV)

d(CKO1H-LOWIV)

d(CKO1H-LOWV)

d(CKO1H-HIGHIV)

d(CKO1H-HIGHV)

d(CKO1H-ZHZ)

10

5

*–1

6

7

8

10

9

10

11

12

13

14

*10

d(CKO1H-ZV)

§

¶

Low group consists of:

High group consists of:

Z group consists of:

IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1

HINT

EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS,

SDWE, HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, and FSR1.

HRDY is gated by input HCS.

If HCS = 0 at device reset, HRDY belongs to the high group.

If HCS = 1 at device reset, HRDY belongs to the low group.

*Not production tested.

45

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

S

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3

I

2

TA

0

C

L

6

2

0

S

1

I

B

G

,

N

S MJ 3 20 C 6 20 1 B

P RO CE SS OR

I

G

A

L

SGUS031 – APRIL 2000

RESET TIMING (CONTINUED)

CLKOUT1

1

2

RESET

CLKOUT2

SDCLK

3

4

6

5

7

8

SSCLK

9

10

12

14

†‡

LOW GROUP

11

13

†‡

HIGH GROUP

†‡

Z GROUP

†

‡

Low group consists of:

High group consists of:

Z group consists of:

IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1

HINT

EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS,

SDWE, HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, and FSR1.

HRDY is gated by input HCS.

If HCS = 0 at device reset, HRDY belongs to the high group.

If HCS = 1 at device reset, HRDY belongs to the low group.

Figure 26. Reset Timing

46

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

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D

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3

I

2

T

0

A

C

L

6

2

0

S

1

I

B

G

,

N

SM J 32 0C 62 01 B

P RO C ES S O R

I

G

A

L

SGUS031 – APRIL 2000

EXTERNAL INTERRUPT TIMING

timing requirements for interrupt response cycles^†‡(see Figure 27)

’C6201B

NO.

UNIT

MIN

*2P

MAX

2

3

t

Width of the interrupt pulse low

Width of the interrupt pulse high

ns

w(ILOW)

w(IHIGH)

†

‡

Interrupt signals are synchronized internally and are potentially recognized one cycle later if setup and hold times are violated. Thus, they can

be connected to asynchronous inputs.

P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.

*Not production tested.

switching characteristics during interrupt response cycles^§(see Figure 27)

’C6201B

NO.

PARAMETER

UNIT

MIN

*9P

*–4

MAX

1

4

5

6

t

Response time, EXT_INTx high to IACK high

Delay time, CLKOUT2 low to IACK valid

Delay time, CLKOUT2 low to INUMx valid

Delay time, CLKOUT2 low to INUMx invalid

ns

R(EINTH-IACKH)

d(CKO2L-IACKV)

d(CKO2L-INUMV)

6

*–4

d(CKO2L-INUMIV)

§

P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.

When the PLL is used (CLKMODE x4), 0.5P = 1/(2 × CPU clock frequency).

For CLKMODE x1: 0.5P = PH, where PH is the high period of CLKIN.

*Not production tested.

1

CLKOUT2

3

2

EXT_INTx, NMI

Intr Flag

4

IACK

6

5

Interrupt Number

INUMx

Figure 27. Interrupt Timing

47

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

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3

I

2

TA

0

C

L

6

2

0

S

1

I

B

G

,

N

S MJ 3 20 C 6 20 1 B

P RO CE SS OR

I

G

A

L

SGUS031 – APRIL 2000

HOST-PORT INTERFACE TIMING

timing requirements for host-port interface cycles^†‡(see Figure 28, Figure 29, Figure 30, and

Figure 31)

’C6201B

NO.

UNIT

MIN

4

MAX

§

1

2

t

Setup time, select signals valid before HSTROBE low

ns

su(SEL-HSTBL)

h(HSTBL-SEL)

w(HSTBL)

§

Hold time, select signals valid after HSTROBE low

2

3

Pulse duration, HSTROBE low

2P

*2P

4

Pulse duration, HSTROBE high between consecutive accesses

w(HSTBH)

§

10

11

12

13

Setup time, select signals valid before HAS low

su(SEL-HASL)

h(HASL-SEL)

su(HDV-HSTBH)

h(HSTBH-HDV)

§

Hold time, select signals valid after HAS low

2

Setup time, host data valid before HSTROBE high

Hold time, host data valid after HSTROBE high

4

2

Hold time, HSTROBE low after HRDY low. HSTROBE shoul not be inactivated

until HRDY is active (low); otherwise, HPI writes will not complete properly.

14

t

*1

ns

h(HRDYL-HSTBL)

18

19

t

Setup time, HAS low before HSTROBE low

Hold time, HAS low after HSTROBE low

*2

ns

su(HASL-HSTBL)

h(HSTBL-HASL)

†

‡

HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency

in ns. For example, when running parts at 200 MHz, use P = 5 ns.

§

Select signals include: HCNTRL[1:0], HR/W, and HHWIL.

*Not production tested.

switching characteristics during host-port interface cycles^†‡(see Figure 28, Figure 29, Figure 30,

and Figure 31)

’C6201B

NO.

PARAMETER

UNIT

MIN MAX

¶

5

6

t

Delay time, HCS to HRDY

*1

*3

*4

9

ns

d(HCS-HRDY)

#

Delay time, HSTROBE low to HRDY high

12

d(HSTBL-HRDYH)

7

Output hold time, HD low impedance after HSTROBE low for an HPI read

Delay time, HD valid to HRDY low

oh(HSTBL-HDLZ)

8

*P – 3 *P + 3

d(HDV-HRDYL)

oh(HSTBH-HDV)

d(HSTBH-HDHZ)

9

Output hold time, HD valid after HSTROBE high

Delay time, HSTROBE high to HD high impedance

Delay time, HSTROBE low to HD valid

*1

*3

*2

*3

*12

12

15

16

17

d(HSTBL-HDV)

||

Delay time, HSTROBE high to HRDY high

d(HSTBH-HRDYH)

†

‡

HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency

in ns. For example, when running parts at 200 MHz, use P = 5 ns.

¶

#

||

HCS enables HRDY, and HRDY is always low when HCS is high. The case where HRDY goes high when HCS falls indicates that HPI is busy

completing a previous HPID write or READ with autoincrement.

This parameter is used during an HPID read. At the beginning of the first half-word transfer on the falling edge of HSTROBE, the HPI sends the

request to the DMA auxiliary channel, and HRDY remains high until the DMA auxiliary channel loads the requested data into HPID.

This parameter is used after the second half-word of an HPID write or autoincrement read. HRDY remains low if the access is not an HPID write

or autoincrement read. Reading or writing to HPIC or HPIA does not affect the HRDY signal.

*Not production tested.

48

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

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3

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2

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0

A

C

L

6

2

0

S

1

I

B

G

,

N

SM J 32 0C 62 01 B

P RO C ES S O R

I

G

A

L

SGUS031 – APRIL 2000

HOST-PORT INTERFACE TIMING (CONTINUED)

HAS

HCNTL[1:0]

HR/W

1

2

1

HHWIL

4

3

†

HSTROBE

HCS

15

9

15

9

7

16

HD[15:0] (output)

HRDY (case 1)

HRDY (case 2)

5

1st Half-Word

2nd Half-Word

5

8

17

6

†

HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

Figure 28. HPI Read Timing (HAS Not Used, Tied High)

HAS

19

11

19

11

10

HCNTL[1:0]

HR/W

11

10

HHWIL

4

3

†

HSTROBE

18

HCS

15

7

9

16

9

17

HD[15:0] (output)

HRDY (case 1)

HRDY (case 2)

1st half-word

2nd half-word

5

8

5

6

†

HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

Figure 29. HPI Read Timing (HAS Used)

49

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

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D

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3

I

2

TA

0

C

L

6

2

0

S

1

I

B

G

,

N

S MJ 3 20 C 6 20 1 B

P RO CE SS OR

I

G

A

L

SGUS031 – APRIL 2000

HOST-PORT INTERFACE TIMING (CONTINUED)

HAS

1

2

HCNTL[1:0]

HBE[1:0]

12

13

1

2

HR/W

HHWIL

3

4

14

†

HSTROBE

HCS

HD[15:0] (input)

HRDY

12

13

2nd Half-Word

13

17

1st Half-Word

5

†

HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

Figure 30. HPI Write Timing (HAS Not Used, Tied High)

HAS

HBE[1:0]

12

19

13

19

13

11

10

HCNTL[1:0]

10

HR/W

HHWIL

3

4

14

†

HSTROBE

18

12

18

HCS

HD[15:0] (input)

HRDY

12

13

1st half-word

2nd half-word

5

17

†

HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

Figure 31. HPI Write Timing (HAS Used)y

50

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

S

D

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3

I

2

T

0

A

C

L

6

2

0

S

1

I

B

G

,

N

SM J 32 0C 62 01 B

P RO C ES S O R

I

G

A

L

SGUS031 – APRIL 2000

MULTICHANNEL BUFFERED SERIAL PORT TIMING

timing requirements for McBSP^†‡(see Figure 32)

’C6201B

NO.

UNIT

MIN

MAX

2

3

t

Cycle time, CLKR/X

CLKR/X ext

CLKR int

CLKR ext

CLKR int

CLKR ext

CLKR int

CLKR ext

CLKR int

CLKR ext

CLKX int

CLKX ext

CLKX int

CLKX ext

*2P

ns

c(CKRX)

Pulse duration, CLKR/X high or CLKR/X low

*P – 1

w(CKRX)

*9

2

5

6

t

Setup time, external FSR high before CLKR low

Hold time, external FSR high after CLKR low

Setup time, DR valid before CLKR low

ns

su(FRH-CKRL)

h(CKRL-FRH)

su(DRV-CKRL)

h(CKRL-DRV)

su(FXH-CKXL)

h(CKXL-FXH)

*6

3

8

7

1

3

8

Hold time, DR valid after CLKR low

4

9

10

11

Setup time, external FSX high before CLKX low

Hold time, external FSX high after CLKX low

2

6

3

†

‡

CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.

*Not production tested

51

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

S

D

M

3

I

2

TA

0

C

L

6

2

0

S

1

I

B

G

,

N

S MJ 3 20 C 6 20 1 B

P RO CE SS OR

I

G

A

L

SGUS031 – APRIL 2000

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

switching characteristics for McBSP^†‡§(see Figure 32)

’C6201B

MIN

NO.

PARAMETER

UNIT

MAX

Delay time, CLKS high to CLKR/X high for internal CLKR/X

generated from CLKS input

1

t

3

10

ns

d(CKSH-CKRXH)

2

3

4

t

Cycle time, CLKR/X

CLKR/X int

CLKR int

CLKX int

CLKX ext

CLKX int

CLKX ext

CLKX int

CLKX ext

2P

ns

c(CKRX)

¶

Pulse duration, CLKR/X high or CLKR/X low

Delay time, CLKR high to internal FSR valid

*C – 1.6

*–2.5

*–2

*C + 1

w(CKRX)

3

d(CKRH-FRV)

3

*9

*4

*9

*4

*9

9

t

Delay time, CLKX high to internal FSX valid

ns

d(CKXH-FXV)

dis(CKXH-DXHZ)

d(CKXH-DXV)

*3

*–1

Disable time, DX high impedance following last data bit from

CLKX high

12

13

*3

*–1

Delay time, CLKX high to DX valid

Delay time, FSX high to DX valid

*3

FSX int

FSX ext

*–1

*3

*9

14

t

ns

d(FXH-DXV)

ONLY applies when in data

delay 0 (XDATDLY = 00b) mode

†

‡

§

CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

Minimum delay times also represent minimum output hold times.

P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.

*Not production tested.

¶

C = H or L

S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)

=

sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)

H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

52

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

S

D

M

3

I

2

T

0

A

C

L

6

2

0

S

1

I

B

G

,

N

SM J 32 0C 62 01 B

P RO C ES S O R

I

G

A

L

SGUS031 – APRIL 2000

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

CLKS

1

2

3

CLKR

4

FSR (int)

5

6

FSR (ext)

7

8

DR

Bit(n-1)

(n-2)

(n-3)

2

3

CLKX

9

FSX (int)

11

10

FSX (ext)

FSX (XDATDLY=00b)

13

(n-2)

14

13

12

DX

Bit 0

Bit(n-1)

(n-3)

Figure 32. McBSP Timings

53

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

S

D

M

3

I

2

TA

0

C

L

6

2

0

S

1

I

B

G

,

N

S MJ 3 20 C 6 20 1 B

P RO CE SS OR

I

G

A

L

SGUS031 – APRIL 2000

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

timing requirements for FSR when GSYNC = 1 (see Figure 33)

’C6201B

NO.

UNIT

MIN

4

MAX

1

2

t

Setup time, FSR high before CLKS high

Hold time, FSR high after CLKS high

ns

su(FRH-CKSH)

4

h(CKSH-FRH)

CLKS

1

2

FSR External

CLKR/X (no need to resync)

CLKR/X (needs resync)

Figure 33. FSR Timing When GSYNC = 1

timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0^†‡(see Figure 34)

’C6201B

MASTER

SLAVE

MIN MAX

NO.

UNIT

MIN

12

4

MAX

4

5

t

Setup time, DR valid before CLKX low

Hold time, DR valid after CLKX low

2 – 3P

5 + 6P

ns

su(DRV-CKXL)

h(CKXL-DRV)

†

‡

P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

54

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

S

D

M

3

I

2

T

0

A

C

L

6

2

0

S

1

I

B

G

,

N

SM J 32 0C 62 01 B

P RO C ES S O R

I

G

A

L

SGUS031 – APRIL 2000

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0^†‡

(see Figure 34)

’C6201B

§

MASTER

SLAVE

MIN

NO.

PARAMETER

UNIT

MIN

MAX

¶

1

2

3

t

Hold time, FSX low after CLKX low

T – 2 *T + 3

ns

h(CKXL-FXL)

d(FXL-CKXH)

d(CKXH-DXV)

#

Delay time, FSX low to CLKX high

Delay time, CLKX high to DX valid

*L – 2

*–2

L + 3

4

*3P + 4

5P + 17

Disable time, DX high impedance following last data bit from

CLKX low

6

t

*L – 2 *L + 3

ns

dis(CKXL-DXHZ)

Disable time, DX high impedance following last data bit from

FSX high

7

8

t

*P + 3 *3P + 17

*2P + 2 4P + 17

ns

dis(FXH-DXHZ)

Delay time, FSX low to DX valid

d(FXL-DXV)

†

‡

§

P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)

=

sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)

T = CLKX period = (1 + CLKGDV) * S

H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX

and FSR is inverted before being used internally.

¶

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP

CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

*Not production tested.

#

FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock

(CLKX).

CLKX

1

2

8

FSX

7

6

3

DX

DR

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

4

5

Bit 0

(n-2)

(n-3)

(n-4)

Figure 34. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0

¶

#

FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX

and FSR is inverted before being used internally.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP

CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock

(CLKX).

55

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

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D

M

3

I

2

TA

0

C

L

6

2

0

S

1

I

B

G

,

N

S MJ 3 20 C 6 20 1 B

P RO CE SS OR

I

G

A

L

SGUS031 – APRIL 2000

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0^†‡(see Figure 35)

’C6201B

MASTER

SLAVE

MIN MAX

NO.

UNIT

MIN

12

4

MAX

4

5

t

Setup time, DR valid before CLKX high

Hold time, DR valid after CLKX high

2 – 3P

5 + 6P

ns

su(DRV-CKXH)

h(CKXH-DRV)

†

‡

P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

switching characteristics for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0^†‡

(see Figure 35)

’C6201B

§

MASTER

MIN

SLAVE

MIN

NO.

PARAMETER

UNIT

MAX

¶

1

2

3

t

Hold time, FSX low after CLKX low

L – 2

*T – 2

*–2

*L + 3

T + 3

4

ns

h(CKXL-FXL)

d(FXL-CKXH)

d(CKXL-DXV)

#

Delay time, FSX low to CLKX high

Delay time, CLKX low to DX valid

*3P + 4

5P + 17

Disable time, DX high impedance following last data bit

from CLKX low

6

t

*–2

*4 *3P + 3 *5P + 17

H + 4 *2P + 2 4P + 17

ns

dis(CKXL-DXHZ)

7

t

Delay time, FSX low to DX valid

*H – 2

d(FXL-DXV)

†

‡

§

P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)

=

sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)

T = CLKX period = (1 + CLKGDV) * S

H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX

and FSR is inverted before being used internally.

¶

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP

CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

*Not production tested.

#

FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock

(CLKX).

CLKX

1

2

7

FSX

DX

6

3

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

4

5

DR

Bit 0

(n-2)

(n-4)

Figure 35. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0

56

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

S

D

M

3

I

2

T

0

A

C

L

6

2

0

S

1

I

B

G

,

N

SM J 32 0C 62 01 B

P RO C ES S O R

I

G

A

L

SGUS031 – APRIL 2000

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1^†‡(see Figure 36)

’C6201B

MASTER

SLAVE

MIN MAX

NO.

UNIT

MIN

12

4

MAX

4

5

t

Setup time, DR valid before CLKX high

Hold time, DR valid after CLKX high

2 – 3P

5 + 6P

ns

su(DRV-CKXH)

h(CKXH-DRV)

†

‡

P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1^†‡

(see Figure 36)

’C6201B

§

MASTER

MIN

SLAVE

MIN

NO.

PARAMETER

UNIT

MAX

¶

1

2

3

t

Hold time, FSX low after CLKX high

T – 2

*H – 2

*–2

*T + 3

H + 3

4

ns

h(CKXH-FXL)

d(FXL-CKXL)

d(CKXL-DXV)

#

Delay time, FSX low to CLKX low

Delay time, CLKX low to DX valid

*3P + 4

5P + 17

Disable time, DX high impedance following last data bit

from CLKX high

6

t

*H – 2

*H + 3

ns

dis(CKXH-DXHZ)

Disable time, DX high impedance following last data bit

from FSX high

7

8

t

*P + 3 *3P + 17

*2P + 2 4P + 17

ns

dis(FXH-DXHZ)

Delay time, FSX low to DX valid

d(FXL-DXV)

†

‡

§

P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)

=

sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)

T = CLKX period = (1 + CLKGDV) * S

H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX

and FSR is inverted before being used internally.

¶

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP

CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

*Not production tested.

#

FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock

(CLKX).

CLKX

1

2

8

FSX

7

6

3

DX

DR

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

4

5

Bit 0

(n-2)

(n-3)

(n-4)

Figure 36. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1

57

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

S

D

M

3

I

2

TA

0

C

L

6

2

0

S

1

I

B

G

,

N

S MJ 3 20 C 6 20 1 B

P RO CE SS OR

I

G

A

L

SGUS031 – APRIL 2000

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1^†‡(see Figure 37)

’C6201B

MASTER

SLAVE

MIN MAX

NO.

UNIT

MIN

12

4

MAX

4

5

t

Setup time, DR valid before CLKX low

Hold time, DR valid after CLKX low

2 – 3P

5 + 6P

ns

su(DRV-CKXL)

h(CKXL-DRV)

†

‡

P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

switching characteristics for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1^†‡

(see Figure 37)

’C6201B

§

MASTER

MIN

SLAVE

MIN

NO.

PARAMETER

UNIT

MAX

¶

1

2

3

t

Hold time, FSX low after CLKX high

H – 2

*T – 2

*–2

*H + 3

T + 1

4

ns

h(CKXH-FXL)

d(FXL-CKXL)

d(CKXH-DXV)

#

Delay time, FSX low to CLKX low

Delay time, CLKX high to DX valid

*3P + 3

5P + 17

Disable time, DX high impedance following last data bit

from CLKX high

6

t

*–2

*4

*3P + 3 *5P + 17

*2P + 2 4P + 17

ns

dis(CKXH-DXHZ)

7

t

Delay time, FSX low to DX valid

*L – 2

L + 4

d(FXL-DXV)

†

‡

§

P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)

=

sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)

T = CLKX period = (1 + CLKGDV) * S

H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX

and FSR is inverted before being used internally.

¶

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP

CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

*Not production tested.

#

FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock

(CLKX).

CLKX

1

2

FSX

DX

7

6

3

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

4

5

DR

(n-2)

(n-3)

(n-4)

Figure 37. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1

58

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

S

D

M

3

I

2

T

0

A

C

L

6

2

0

S

1

I

B

G

,

N

SM J 32 0C 62 01 B

P RO C ES S O R

I

G

A

L

SGUS031 – APRIL 2000

DMAC, TIMER, POWER-DOWN TIMING

switching characteristics for DMAC outputs (see Figure 38)

’C6201B

NO.

PARAMETER

UNIT

MIN

MAX

10

1

t

Delay time, CLKOUT1 high to DMAC valid

*2

ns

d(CKO1H-DMACV)

*Not production tested.

CLKOUT1

1

DMAC[0:3]

Figure 38. DMAC Timing

timing requirements for timer inputs^†(see Figure 39)

’C6201B

NO.

UNIT

MIN

MAX

1

t

Pulse duration, TINP high or low

*2P

ns

w(TINP)

†

P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.

*Not production tested.

switching characteristics for timer outputs (see Figure 39)

’C6201B

NO.

PARAMETER

UNIT

MIN

MAX

2

t

Delay time, CLKOUT1 high to TOUT valid

*2

9

ns

d(CKO1H-TOUTV)

*Not production tested.

CLKOUT1

1

TINP

2

TOUT

Figure 39. Timer Timing

switching characteristics for power-down outputs (see Figure 40)

’C6201B

NO.

PARAMETER

UNIT

MIN

MAX

1

t

Delay time, CLKOUT1 high to PD valid

*2

9

ns

d(CKO1H-PDV)

*Not production tested.

CLKOUT1

1

PD

Figure 40. Power-Down Timing

59

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

S

D

M

3

I

2

TA

0

C

L

6

2

0

S

1

I

B

G

,

N

S MJ 3 20 C 6 20 1 B

R

I

G

A

L

P

O

C

E

S

O

R

SGUS031 – APRIL 2000

JTAG TEST-PORT TIMING

timing requirements for JTAG test port (see Figure 41)

’C6201B

NO.

UNIT

MIN

*50

*10

*5

MAX

1

3

4

t

Cycle time, TCK

ns

c(TCK)

Setup time, TDI/TMS/TRST valid before TCK high

Hold time, TDI/TMS/TRST valid after TCK high

su(TDIV-TCKH)

h(TCKH-TDIV)

*Not production tested.

switching characteristics for JTAG test port (see Figure 41)

’C6201B

NO.

PARAMETER

Delay time, TCK low to TDO valid

UNIT

MIN

MAX

*15

2

t

*0

ns

d(TCKL-TDOV)

*Not production tested.

1

TCK

TDO

2

4

3

TDI/TMS/TRST

Figure 41. JTAG Test-Port Timing

60

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

S

D

M

3

I

2

T

0

A

C

L

6

2

0

S

1

I

B

G

,

N

SM J 32 0C 62 01 B

P RO C ES S O R

I

G

A

L

SGUS031 – APRIL 2000

MECHANICAL DATA

GLP (S-CBGA-N429)

CERAMIC BALL GRID ARRAY

27,20

26,80

SQ

25,40 TYP

1,27

AA

Y

W

V

U

T

R

P

N

M

L

1,27

K

J

H

G

F

E

D

C

B

A

1

3

5

7

9

11 13 15 17 19 21

10 12 14 16 18 20

2

4

6

8

1,22

1,00

3,30 MAX

Seating Plane

0,15

0,90

0,60

M

0,10

0,70

0,50

4164732/A 08/98

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MO-156

D. Flip chip application only

E. For 320C6201B (1.8 V core device).

F. Package weight for GLP is 7.65 grams.

thermal resistance characteristics (S-CBGA package)

NO

°C/W

3.0

Air Flow

N/A

1

2

3

4

5

6

RΘ

Junction-to-Case, measured to the bottom of solder ball

Junction-to-Case, measured to the top of the package lid

Junction-to-Ambient

JC

JA

7.3

N/A

14.5

11.8

11.1

10.2

0

150 fpm

250 fpm

500 fpm

RΘ

Junction-to-Moving-Air

JMA

JB

Junction-to-Board, measured by soldering a thermocouple to one of the middle

traces on the board at the edge of the package

7

6.2

N/A

61

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

Customers are responsible for their applications using TI components.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

semiconductor products or services might be or are used. TI’s publication of information regarding any third

party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.


型号：	SM320C6201BGLP
厂家：	TEXAS INSTRUMENTS
描述：	DIGITAL SIGNAL PROCESSOR 数字信号处理器数字信号处理器
文件：	总62页 (文件大小：867K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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