SM320C6701S16 [TI]
FLOATING-POINT DIGITAL SIGNAL PROCESSOR; 浮点数字信号处理器
| 型号： | SM320C6701S16 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | FLOATING-POINT DIGITAL SIGNAL PROCESSOR |
| 文件： | 总64页 (文件大小：925K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ꢊ ꢋꢌ ꢍꢎ ꢏꢐꢑ ꢒꢓ ꢌꢏ ꢐꢎ ꢔꢏ ꢑꢏ ꢎꢍꢋ ꢀꢏ ꢑ ꢐꢍꢋ ꢓꢕ ꢌ ꢆꢖ ꢀ ꢀꢌ ꢕ
SGUS030B – APRIL 2000 – REVISED MAY 2001
D
Highest Performance Floating-Point Digital
Signal Processor (DSP) SMJ320C6701
– 7-, 6-ns Instruction Cycle Time
– 140-, 167-MHz Clock Rate
– Eight 32-Bit Instructions/Cycle
– Up to 1 GFLOPS Performance
– Pin-Compatible With ’C6201 Fixed-Point
DSP
D
1M-Bit On-Chip SRAM
– 512K-Bit Internal Program/Cache
(16K 32-Bit Instructions)
– 512K-Bit Dual-Access Internal Data
(64K Bytes)
D
D
32-Bit External Memory Interface (EMIF)
– Glueless Interface to Synchronous
Memories: SDRAM and SBSRAM
– Glueless Interface to Asynchronous
Memories: SRAM and EPROM
D
D
D
SMJ: QML Processing to MIL-PRF-38535
SM: Standard Processing
Four-Channel Bootloading
Direct-Memory-Access (DMA) Controller
With an Auxiliary Channel
Operating Temperature Ranges
– Extended (W) –55°C to 115°C
– Extended (S) –40°C to 90°C
D
D
16-Bit Host-Port Interface (HPI)
– Access to Entire Memory Map
D
VelociTI Advanced Very Long Instruction
Word (VLIW) ’C67x CPU Core
– Eight Highly Independent Functional
Units:
Two Multichannel Buffered Serial Ports
(McBSPs)
– Direct Interface to T1/E1, MVIP, SCSA
Framers
– Four ALUs (Floating- and Fixed-Point)
– Two ALUs (Fixed-Point)
– Two Multipliers (Floating- and
Fixed-Point)
– Load-Store Architecture With 32 32-Bit
General-Purpose Registers
– Instruction Packing Reduces Code Size
– All Instructions Conditional
– ST-Bus-Switching Compatible
– Up to 256 Channels Each
– AC97-Compatible
– Serial-Peripheral-Interface (SPI)
Compatible (Motorola )
D
D
Two 32-Bit General-Purpose Timers
D
Instruction Set Features
– Hardware Support for IEEE
Single-Precision Instructions
– Hardware Support for IEEE
Double-Precision Instructions
– Byte-Addressable (8-, 16-, 32-Bit Data)
– 32-Bit Address Range
– 8-Bit Overflow Protection
– Saturation
Flexible Phase-Locked-Loop (PLL) Clock
Generator
†
D
D
D
D
IEEE-1149.1 (JTAG )
Boundary-Scan-Compatible
429-Pin Ceramic Ball Grid Array (CBGA)
Package (GLP Suffix)
0.18-µm/5-Level Metal Process
– CMOS Technology
– Bit-Field Extract, Set, Clear
– Bit-Counting
– Normalization
3.3-V I/Os, 1.9-V Internal
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
VelociTI is a trademark of Texas Instruments Incorporated.
Motorola is a trademark of Motorola, Inc.
†
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
Copyright 2001, Texas Instruments Incorporated
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1
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SGUS030B – APRIL 2000 – REVISED MAY 2001
GLP PACKAGE
(BOTTOM VIEW)
AA
Y
W
V
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N
M
L
K
J
H
G
F
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description
The SMJ320C67x DSPs are the floating-point DSP family in the SMJ320C6000 platform. The SMJ320C6701
(’C6701) device is based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW)
architecture developed by Texas Instruments (TI ), making this DSP an excellent choice for multichannel and
multifunction applications. With performance of up to 1 giga floating-point operations per second (GFLOPS) at
a clock rate of 167 MHz, the ’C6701 offers cost-effective solutions to high-performance DSP programming
challenges. The ’C6701 DSP possesses the operational flexibility of high-speed controllers and the numerical
capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight
highly independent functional units. The eight functional units provide four floating-/fixed-point ALUs, two
fixed-point ALUs, and two floating-/fixed-point multipliers. The ’C6701 can produce two multiply-accumulates
(MACs) per cycle for a total of 334 million MACs per second (MMACS). The ’C6701 DSP also has
application-specific hardware logic, on-chip memory, and additional on-chip peripherals.
The ’C6701 includes a large bank of on-chip memory and has a powerful and diverse set of peripherals.
Program memory consists of a 64K-byte block that is user-configurable as cache or memory-mapped program
space. Data memory consists of two 32K-byte blocks of RAM. The peripheral set includes two multichannel
buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external
memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals.
The ’C6701 has a complete set of development tools which includes: a new C compiler, an assembly optimizer
to simplify programming and scheduling, and a Windows debugger interface for visibility into source code
execution.
TI is a trademark of Texas Instruments Incorporated.
Windows is a registered trademark of the Microsoft Corporation.
2
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SGUS030B – APRIL 2000 – REVISED MAY 2001
device characteristics
Table 1 provides an overview of the ’C6701 DSP. The table shows significant features of each device, including
the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count.
Table 1. Characteristics of the ’C6701 Processors
CHARACTERISTICS
DESCRIPTION
Device Number
SMJ320C6701
512-Kbit Program Memory
512-Kbit Data Memory (organized as 2 blocks)
On-Chip Memory
Peripherals
2 Mutichannel Buffered Serial Ports (McBSP)
2 General-Purpose Timers
Host-Port Interface (HPI)
External Memory Interface (EMIF)
Cycle Time
7 ns at 140 MHz, and 6 ns at 167 MHz
Package Type
27 mm × 27 mm, 429-Pin BGA (GLP)
1.9 V Core
3.3 V I/O
Nominal Voltage
functional and CPU block diagram
’C6701 Digital Signal Processor
SDRAM
SBSRAM
32
SRAM
Internal Program Memory
1 Block Program/Cache
(64K Bytes)
Program
Access/Cache
Controller
External Memory
Interface (EMIF)
ROM/FLASH
I/O Devices
’C67x CPU
Timer 0
Timer 1
Instruction Fetch
Control
Registers
Instruction Dispatch
Instruction Decode
Control
Logic
Multichannel
Buffered Serial
Port 0
Framing Chips:
H.100, MVIP,
SCSA, T1, E1
AC97 Devices,
SPI Devices,
Codecs
Data Path A
A Register File
Data Path B
Test
B Register File
In-Circuit
Emulation
Multichannel
Buffered Serial
Port 1
Interrupt
Control
†
†
†
†
†
†
.L1 .S1 .M1 .D1
.D2 .M2 .S2 .L2
Direct Memory
Access Controller
(DMA)
Internal Data
Memory
(64K Bytes)
2 Blocks of 8 Banks
Each
HOST CONNECTION
MC68360 Glueless
MPC860 Glueless
PCI9050 Bridge + Inverter
MC68302 + PAL
Data
Access
Controller
Power-
Down
Logic
(4 Channels)
Host Port
Interface
(HPI)
16
PLL
(x1, x4)
MPC750 + PAL
MPC960 (Jx/Rx) + PAL
†
These functional units execute floating-point instructions.
3
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SGUS030B – APRIL 2000 – REVISED MAY 2001
CPU description
The CPU fetches VelociTI advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight
32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture features
controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The
first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the
previous instruction, or whether it should be executed in the following clock as a part of the next execute packet.
Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length
execute packets are a key memory-saving feature, distinguishing the ’C67x CPU from other VLIW architectures.
The CPU features two sets of functional units. Each set contains four units and a register file. One set contains
functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files
contain 16 32-bit registers each for the total of 32 general-purpose registers. The two sets of functional units,
along with two register files, compose sides A and B of the CPU (see the functional and CPU block diagram
and Figure 1). The four functional units on each side of the CPU can freely share the 16 registers belonging to
that side. Additionally, each side features a single data bus connected to all registers on the other side, by which
the two sets of functional units can access data from the register files on opposite sides. While register access
by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle,
register access using the register file across the CPU supports one read and one write per cycle.
The ’C67x CPU executes all ’C62x instructions. In addition to ’C62x fixed-point instructions, the six out of eight
functional units (.L1, .M1, .D1, .D2, .M2, and .L2) also execute floating-point instructions. The remaining two
functional units (.S1 and .S2) also execute the new LDDW instruction which loads 64 bits per CPU side for a
total of 128 bits per cycle.
Another key feature of the ’C67x CPU is the load/store architecture, where all instructions operate on registers
(as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data
transfers between the register files and the memory. The data address driven by the .D units allows data
addresses generated from one register file to be used to load or store data to or from the other register file. The
’C67x CPU supports a variety of indirect-addressing modes using either linear- or circular-addressing modes
with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers. Some
registers, however, are singled out to support specific addressing or to hold the condition for conditional
instructions (if the condition is not automatically “true”). The two .M functional units are dedicated for multiplies.
The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results
available every clock cycle.
The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory.
The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least
significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous
execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain,
effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the
fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of
the current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet
can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one
per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch
packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units
for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit
registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store
instructions are byte-, half-word, or word-addressable.
4
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SGUS030B – APRIL 2000 – REVISED MAY 2001
CPU description (continued)
src1
†
.L1
src2
dst
8
8
long dst
long src
8
32
LD1 32 MSB
ST1
32
Register
File A
(A0–A15)
long src
long dst
dst
8
Data Path A
†
.S1
src1
src2
dst
†
.M1
src1
src2
LD1 32 LSB
DA1
dst
src1
src2
.D1
2X
1X
src2
src1
dst
DA2
.D2
.M2
LD2 32 LSB
src2
†
src1
dst
src2
Register
File B
(B0–B15)
src1
dst
†
.S2
Data Path B
8
8
long dst
long src
8
32
32
LD2 32 MSB
ST2
long src
long dst
dst
8
†
.L2
src2
src1
Control
Register File
†
These functional units execute floating-point instructions.
Figure 1. SMJ320C67x CPU Data Paths
5
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SGUS030B – APRIL 2000 – REVISED MAY 2001
signal groups description
CLKIN
CLKOUT2
CLKOUT1
CLKMODE1
CLKMODE0
BOOTMODE4
BOOTMODE3
BOOTMODE2
BOOTMODE1
BOOTMODE0
Boot Mode
CLOCK/PLL
PLLFREQ3
PLLFREQ2
PLLFREQ1
PLLV
RESET
NMI
EXT_INT7
PLLG
PLLF
EXT_INT6
EXT_INT5
EXT_INT4
IACK
Reset and
Interrupts
INUM3
INUM2
INUM1
INUM0
TMS
TDO
TDI
IEEE Standard
1149.1
(JTAG)
Emulation
TCK
TRST
EMU1
EMU0
Little ENDIAN
Big ENDIAN
LENDIAN
RSV9
RSV8
RSV7
RSV6
RSV5
RSV4
RSV3
RSV2
RSV1
RSV0
DMAC3
DMAC2
DMAC1
DMAC0
DMA Status
Reserved
Power-Down
Status
PD
Control/Status
HPI
16
(Host-Port Interface)
HD[15:0]
Data
HAS
HR/W
HCS
HDS1
HDS2
HRDY
HINT
HCNTL0
HCNTL1
Register Select
Control
HHWIL
HBE1
HBE0
Half-Word/Byte
Select
Figure 2. CPU and Peripheral Signals
6
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SGUS030B – APRIL 2000 – REVISED MAY 2001
signal groups description (continued)
32
ED[31:0]
Data
ARE
Asynchronous
Memory
AOE
AWE
ARDY
Control
CE3
CE2
CE1
CE0
Memory Map
Space Select
SSADS
SSOE
SSWE
SSCLK
SBSRAM
Control
20
EA[21:2]
Word Address
Byte Enables
BE3
BE2
BE1
BE0
SDA10
SDRAS
SDCAS
SDWE
SDRAM
Control
SDCLK
HOLD
HOLD/
HOLDA
HOLDA
EMIF
(External Memory Interface)
TOUT1
TINP1
TOUT0
TINP0
Timer 1
Timer 0
Timers
McBSP1
Receive
McBSP0
Receive
CLKX1
FSX1
DX1
CLKX0
FSX0
DX0
CLKR1
FSR1
DR1
CLKR0
FSR0
DR0
Transmit
Clock
Transmit
Clock
CLKS1
CLKS0
McBSPs
(Multichannel Buffered Serial Ports)
Figure 3. Peripheral Signals
7
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SGUS030B – APRIL 2000 – REVISED MAY 2001
Signal Descriptions
SIGNAL
†
TYPE
DESCRIPTION
NAME
NO.
CLOCK/PLL
CLKIN
A14
Y6
I
Clock Input
CLKOUT1
O
O
Clock output at full device speed
Clock output at half of device speed
Clock mode select
CLKOUT2
V9
CLKMODE1
CLKMODE0
PLLFREQ3
PLLFREQ2
PLLFREQ1
B17
C17
C13
G11
F11
D12
G10
C12
I
•
Selects whether the output clock frequency = input clock freq x4 or x1
PLL frequency range (3, 2, and 1)
The target range for CLKOUT1 frequency is determined by the 3-bit value of the PLLFREQ pins.
•
I
‡
§
A
§
A
§
A
PLLV
PLL analog V connection for the low-pass filter
CC
‡
PLLG
PLL analog GND connection for the low-pass filter
PLL low-pass filter connection to external components and a bypass capacitor
JTAG EMULATION
PLLF
TMS
TDO
TDI
K19
R12
R13
M20
N18
R20
T18
I
JTAG test port mode select (features an internal pull-up)
JTAG test port data out
O/Z
I
I
I
JTAG test port data in (features an internal pull-up)
JTAG test port clock
TCK
TRST
EMU1
EMU0
JTAG test port reset (features an internal pull-down)
¶
¶
I/O/Z
I/O/Z
Emulation pin 1, pull-up with a dedicated 20-kΩ resistor
Emulation pin 0, pull-up with a dedicated 20-kΩ resistor
RESET AND INTERRUPTS
RESET
NMI
J20
I
I
Device reset
Nonmaskable interrupt
K21
•
Edge-driven (rising edge)
EXT_INT7
EXT_INT6
EXT_INT5
EXT_INT4
IACK
R16
P20
R15
R18
R11
T19
T20
T14
T16
External interrupts
Edge-driven (rising edge)
I
•
O
Interrupt acknowledge for all active interrupts serviced by the CPU
Active interrupt identification number
INUM3
INUM2
•
•
Valid during IACK for all active interrupts (not just external)
Encoding order follows the interrupt service fetch packet ordering
O
INUM1
INUM0
LITTLE ENDIAN/BIG ENDIAN
If high, selects little-endian byte/half-word addressing order within a word
If low, selects big-endian addressing
LENDIAN
G20
I
POWER DOWN STATUS
PD
D19
O
Power-down mode 2 or 3 (active if high)
†
‡
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
PLLV and PLLG signals are not part of external voltage supply or ground. See the CLOCK/PLL documentation for information on how to connect
those pins.
A = Analog Signal (PLL Filter)
§
¶
For emulation and normal operation, pull up EMU1 and EMU0 with a dedicated 20-kΩ resistor. For boundary scan, pull down EMU1 and EMU0
with a dedicated 20-kΩ resistor.
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢅ ꢉ
ꢊ ꢋꢌ ꢍꢎ ꢏꢐꢑ ꢒꢓ ꢌꢏ ꢐꢎ ꢔꢏ ꢑꢏ ꢎꢍꢋ ꢀꢏ ꢑ ꢐꢍꢋ ꢓꢕ ꢌ ꢆꢖ ꢀ ꢀꢌ ꢕ
SGUS030B – APRIL 2000 – REVISED MAY 2001
Signal Descriptions (Continued)
SIGNAL
NAME
†
TYPE
DESCRIPTION
NO.
HOST PORT INTERFACE (HPI)
Host interrupt (from DSP to host)
HINT
H2
J6
O/Z
HCNTL1
HCNTL0
HHWIL
HBE1
HBE0
HR/W
HD15
HD14
HD13
HD12
HD11
HD10
HD9
I
I
I
I
I
I
Host control – selects between control, address or data registers
Host control – selects between control, address or data registers
Host halfword select – first or second halfword (not necessarily high or low order)
Host byte select within word or half-word
H6
E4
G6
F6
Host byte select within word or half-word
D4
D11
B11
A11
G9
D10
A10
C10
B9
Host read or write select
HD8
I/O/Z
Host port data (used for transfer of data, address and control)
HD7
F9
HD6
C9
A9
HD5
HD4
B8
HD3
D9
D8
B7
HD2
HD1
HD0
C7
L6
HAS
I
I
Host address strobe
Host chip select
HCS
C5
C4
K6
HDS1
HDS2
HRDY
I
Host data strobe 1
Host data strobe 2
Host ready (from DSP to host)
BOOT MODE
I
H3
O
BOOTMODE4
BOOTMODE3
BOOTMODE2
BOOTMODE1
BOOTMODE0
B16
G14
F15
C18
D17
I
Boot mode
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢅꢉ
ꢊ ꢋ ꢌꢍꢎ ꢏ ꢐ ꢑꢒꢓꢌꢏ ꢐ ꢎ ꢔꢏ ꢑ ꢏ ꢎꢍꢋ ꢀ ꢏ ꢑꢐ ꢍꢋ ꢓ ꢕꢌ ꢆꢖꢀ ꢀꢌ ꢕ
SGUS030B – APRIL 2000 – REVISED MAY 2001
Signal Descriptions (Continued)
SIGNAL
†
TYPE
DESCRIPTION
NAME
NO.
EMIF – CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY
CE3
Y5
V3
T6
U2
R8
T3
T2
R2
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
CE2
CE1
CE0
BE3
BE2
BE1
BE0
Memory space enables
•
•
Enabled by bits 24 and 25 of the word address
Only one asserted during any external data access
Byte enable control
•
•
•
Decoded from the two lowest bits of the internal address
Byte write enables for most types of memory
Can be directly connected to SDRAM read and write mask signal (SDQM)
EMIF – ADDRESS
EA21
EA20
EA19
EA18
EA17
EA16
EA15
EA14
EA13
EA12
EA11
EA10
EA9
L4
L3
J2
J1
K1
K2
L2
L1
M1
M2
M6
N4
N1
N2
N6
P4
P3
P2
P1
P6
O/Z
External address (word address)
EA8
EA7
EA6
EA5
EA4
EA3
EA2
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
10
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢅ ꢉ
ꢊ ꢋꢌ ꢍꢎ ꢏꢐꢑ ꢒꢓ ꢌꢏ ꢐꢎ ꢔꢏ ꢑꢏ ꢎꢍꢋ ꢀꢏ ꢑ ꢐꢍꢋ ꢓꢕ ꢌ ꢆꢖ ꢀ ꢀꢌ ꢕ
SGUS030B – APRIL 2000 – REVISED MAY 2001
Signal Descriptions (Continued)
SIGNAL
NAME
†
TYPE
DESCRIPTION
NO.
EMIF – DATA
ED31
U18
U20
T15
V18
V17
V16
T12
W17
T13
Y17
T11
Y16
W15
V14
Y15
R9
ED30
ED29
ED28
ED27
ED26
ED25
ED24
ED23
ED22
ED21
ED20
ED19
ED18
ED17
ED16
ED15
ED14
ED13
ED12
ED11
ED10
ED9
I/O/Z
External data
Y14
V13
AA13
T10
Y13
W12
Y12
Y11
V10
AA10
Y10
W10
Y9
ED8
ED7
ED6
ED5
ED4
ED3
ED2
AA9
Y8
ED1
ED0
W9
EMIF – ASYNCHRONOUS MEMORY CONTROL
Asynchronous memory read enable
ARE
R7
T7
V5
R4
O/Z
O/Z
O/Z
I
AOE
AWE
ARDY
Asynchronous memory output enable
Asynchronous memory write enable
Asynchronous memory ready input
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
11
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢅꢉ
ꢊ ꢋ ꢌꢍꢎ ꢏ ꢐ ꢑꢒꢓꢌꢏ ꢐ ꢎ ꢔꢏ ꢑ ꢏ ꢎꢍꢋ ꢀ ꢏ ꢑꢐ ꢍꢋ ꢓ ꢕꢌ ꢆꢖꢀ ꢀꢌ ꢕ
SGUS030B – APRIL 2000 – REVISED MAY 2001
Signal Descriptions (Continued)
SIGNAL
†
TYPE
DESCRIPTION
NAME
NO.
EMIF – SYNCHRONOUS BURST SRAM CONTROL
SBSRAM address strobe
SSADS
V8
W7
Y7
O/Z
O/Z
O/Z
O/Z
SSOE
SSWE
SSCLK
SBSRAM output enable
SBSRAM write enable
AA8
SBSRAM clock
EMIF – SYNCHRONOUS DRAM CONTROL
SDRAM address 10 (separate for deactivate command)
SDRAM row address strobe
SDRAM column address strobe
SDRAM write enable
SDA10
SDRAS
SDCAS
SDWE
SDCLK
V7
V6
W5
T8
O/Z
O/Z
O/Z
O/Z
O/Z
T9
SDRAM clock
EMIF – BUS ARBITRATION
Hold request from the host
HOLD
R6
I
HOLDA
B15
O
Hold request acknowledge to the host
TIMERS
TOUT1
TINP1
TOUT0
TINP0
G2
K3
O/Z
Timer 1 or general-purpose output
Timer 1 or general-purpose input
Timer 0 or general-purpose output
Timer 0 or general-purpose input
DMA ACTION COMPLETE
I
O/Z
I
M18
J18
DMAC3
DMAC2
DMAC1
DMAC0
E18
F19
E20
G16
O
I
DMA action complete
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)
CLKS1
CLKR1
CLKX1
DR1
F4
H4
J4
External clock source (as opposed to internal)
Receive clock
I/O/Z
I/O/Z
I
Transmit clock
E2
G4
F3
F2
Receive data
DX1
O/Z
I/O/Z
I/O/Z
Transmit data
FSR1
FSX1
Receive frame sync
Transmit frame sync
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
12
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢅ ꢉ
ꢊ ꢋꢌ ꢍꢎ ꢏꢐꢑ ꢒꢓ ꢌꢏ ꢐꢎ ꢔꢏ ꢑꢏ ꢎꢍꢋ ꢀꢏ ꢑ ꢐꢍꢋ ꢓꢕ ꢌ ꢆꢖ ꢀ ꢀꢌ ꢕ
SGUS030B – APRIL 2000 – REVISED MAY 2001
Signal Descriptions (Continued)
SIGNAL
NAME
†
TYPE
DESCRIPTION
NO.
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)
External clock source (as opposed to internal)
Receive clock
CLKS0
K18
L21
K20
J21
I
CLKR0
CLKX0
DR0
I/O/Z
I/O/Z
I
Transmit clock
Receive data
DX0
M21
P16
N16
O/Z
I/O/Z
I/O/Z
Transmit data
FSR0
FSX0
Receive frame sync
Transmit frame sync
RESERVED FOR TEST
RSV0
RSV1
RSV2
RSV3
RSV4
RSV5
RSV6
RSV7
RSV8
RSV9
N21
K16
B13
B14
F13
C15
F7
I
I
Reserved for testing, pull-up with a dedicated 20-kΩ resistor
Reserved for testing, pull-up with a dedicated 20-kΩ resistor
Reserved for testing, pull-up with a dedicated 20-kΩ resistor
Reserved for testing, pull-up with a dedicated 20-kΩ resistor
Reserved for testing, pull-down with a dedicated 20-kΩ resistor
Reserved (leave unconnected, do not connect to power or ground)
Reserved for testing, pull-up with a dedicated 20-kW resistor
Reserved for testing, pull-up with a dedicated 20-kW resistor
Reserved for testing, pull-up with a dedicated 20-kW resistor
Reserved (leave unconnected, do not connect to power or ground)
SUPPLY VOLTAGE PINS
I
I
I
O
I
D7
I
B5
I
F16
O
C14
C8
E19
E3
H11
H13
H9
J10
J12
J14
J19
J3
DV
S
3.3-V supply voltage
DD
J8
K11
K13
K15
K7
K9
L10
L12
L14
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
13
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢅꢉ
ꢊ ꢋ ꢌꢍꢎ ꢏ ꢐ ꢑꢒꢓꢌꢏ ꢐ ꢎ ꢔꢏ ꢑ ꢏ ꢎꢍꢋ ꢀ ꢏ ꢑꢐ ꢍꢋ ꢓ ꢕꢌ ꢆꢖꢀ ꢀꢌ ꢕ
SGUS030B – APRIL 2000 – REVISED MAY 2001
Signal Descriptions (Continued)
SIGNAL
†
TYPE
DESCRIPTION
SUPPLY VOLTAGE PINS (CONTINUED)
NAME
NO.
L8
M11
M13
M15
M7
M9
N10
N12
N14
N19
N3
DV
S
3.3-V supply voltage
DD
N8
P11
P13
P9
U19
U3
W14
W8
A12
A13
B10
B12
B6
D15
D16
F10
F14
F8
CV
S
1.9-V supply voltage
DD
G13
G7
G8
K4
M3
M4
A3
A5
A7
A16
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
14
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢅ ꢉ
ꢊ ꢋꢌ ꢍꢎ ꢏꢐꢑ ꢒꢓ ꢌꢏ ꢐꢎ ꢔꢏ ꢑꢏ ꢎꢍꢋ ꢀꢏ ꢑ ꢐꢍꢋ ꢓꢕ ꢌ ꢆꢖ ꢀ ꢀꢌ ꢕ
SGUS030B – APRIL 2000 – REVISED MAY 2001
Signal Descriptions (Continued)
SIGNAL
NAME
†
TYPE
DESCRIPTION
SUPPLY VOLTAGE PINS (CONTINUED)
NO.
A18
AA4
AA6
AA15
AA17
AA19
B2
B4
B19
C1
C3
C20
D2
D21
E1
E6
E8
CV
S
1.9-V supply voltage
DD
E10
E12
E14
E16
F5
F17
F21
G1
H5
H17
K5
K17
M5
M17
P5
P17
R21
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
15
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢅꢉ
ꢊ ꢋ ꢌꢍꢎ ꢏ ꢐ ꢑꢒꢓꢌꢏ ꢐ ꢎ ꢔꢏ ꢑ ꢏ ꢎꢍꢋ ꢀ ꢏ ꢑꢐ ꢍꢋ ꢓ ꢕꢌ ꢆꢖꢀ ꢀꢌ ꢕ
SGUS030B – APRIL 2000 – REVISED MAY 2001
Signal Descriptions (Continued)
SIGNAL
†
TYPE
DESCRIPTION
SUPPLY VOLTAGE PINS (CONTINUED)
NAME
NO.
T1
T5
T17
U6
U8
U10
U12
U14
U16
U21
V1
V20
W2
W19
W21
Y3
Y18
Y20
AA11
AA12
F20
G18
H16
H18
L18
L19
L20
N20
P18
P19
R10
R14
U4
CV
S
1.9-V supply voltage
DD
V11
V12
V15
W13
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
16
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢅ ꢉ
ꢊ ꢋꢌ ꢍꢎ ꢏꢐꢑ ꢒꢓ ꢌꢏ ꢐꢎ ꢔꢏ ꢑꢏ ꢎꢍꢋ ꢀꢏ ꢑ ꢐꢍꢋ ꢓꢕ ꢌ ꢆꢖ ꢀ ꢀꢌ ꢕ
SGUS030B – APRIL 2000 – REVISED MAY 2001
Signal Descriptions (Continued)
SIGNAL
NAME
†
TYPE
DESCRIPTION
NO.
GROUND PINS
C11
C16
C6
D5
G3
H10
H12
H14
H7
H8
J11
J13
J7
J9
K8
L7
L9
M8
N7
R3
V
SS
GND
Ground pins
A4
A6
A8
A15
A17
A19
AA3
AA5
AA7
AA14
AA16
AA18
B3
B18
B20
C2
C19
C21
D1
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
17
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢅꢉ
ꢊ ꢋ ꢌꢍꢎ ꢏ ꢐ ꢑꢒꢓꢌꢏ ꢐ ꢎ ꢔꢏ ꢑ ꢏ ꢎꢍꢋ ꢀ ꢏ ꢑꢐ ꢍꢋ ꢓ ꢕꢌ ꢆꢖꢀ ꢀꢌ ꢕ
SGUS030B – APRIL 2000 – REVISED MAY 2001
Signal Descriptions (Continued)
SIGNAL
†
TYPE
DESCRIPTION
GROUND PINS (CONTINUED)
NAME
NO.
D20
E5
E7
E9
E11
E13
E15
E17
E21
F1
G5
G17
G21
H1
J5
J17
L5
L17
N5
V
GND
Ground pins
SS
N17
P21
R1
R5
R17
T21
U1
U5
U7
U9
U11
U13
U15
U17
V2
V21
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
18
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢅ ꢉ
ꢊ ꢋꢌ ꢍꢎ ꢏꢐꢑ ꢒꢓ ꢌꢏ ꢐꢎ ꢔꢏ ꢑꢏ ꢎꢍꢋ ꢀꢏ ꢑ ꢐꢍꢋ ꢓꢕ ꢌ ꢆꢖ ꢀ ꢀꢌ ꢕ
SGUS030B – APRIL 2000 – REVISED MAY 2001
Signal Descriptions (Continued)
SIGNAL
NAME
†
TYPE
DESCRIPTION
GROUND PINS (CONTINUED)
NO.
W1
W3
W20
Y2
Y4
Y19
F18
G19
H15
J15
J16
K10
K12
K14
L11
L13
L15
M10
M12
M14
N11
N13
N15
N9
V
GND
Ground pins
SS
P10
P12
P14
P15
P7
P8
R19
T4
W11
W16
W6
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
19
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢅꢉ
ꢊ ꢋ ꢌꢍꢎ ꢏ ꢐ ꢑꢒꢓꢌꢏ ꢐ ꢎ ꢔꢏ ꢑ ꢏ ꢎꢍꢋ ꢀ ꢏ ꢑꢐ ꢍꢋ ꢓ ꢕꢌ ꢆꢖꢀ ꢀꢌ ꢕ
SGUS030B – APRIL 2000 – REVISED MAY 2001
Signal Descriptions (Continued)
SIGNAL
†
TYPE
DESCRIPTION
REMAINING UNCONNECTED PINS
NAME
NO.
D13
D14
D18
D3
D6
F12
G12
G15
H19
H20
H21
L16
M16
M19
V19
V4
NC
Unconnected pins
W18
W4
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
20
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢅ ꢉ
ꢊ ꢋꢌ ꢍꢎ ꢏꢐꢑ ꢒꢓ ꢌꢏ ꢐꢎ ꢔꢏ ꢑꢏ ꢎꢍꢋ ꢀꢏ ꢑ ꢐꢍꢋ ꢓꢕ ꢌ ꢆꢖ ꢀ ꢀꢌ ꢕ
SGUS030B – APRIL 2000 – REVISED MAY 2001
development support
Texas Instruments (TI) offers an extensive line of development tools for the ’C6x generation of DSPs, including
tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and
fully integrate and debug software and hardware modules.
The following products support development of ’C6x-based applications:
Software-Development Tools:
Assembly optimizer
Assembler/Linker
Simulator
Optimizing ANSI C compiler
Application algorithms
C/Assembly debugger and code profiler
Hardware-Development Tools:
Extended development system (XDS ) emulator (supports ’C6x multiprocessor system debug)
EVM (Evaluation Module)
The TMS320 DSP Development Support Reference Guide (SPRU011) contains information about
development-support products for all TMS320 family member devices, including documentation. See this
document for further information on TMS320 documentation or any TMS320 support products from Texas
Instruments. An additional document, the TMS320 Third-Party Support Reference Guide (SPRU052), contains
information about TMS320-related products from other companies in the industry. To receive TMS320 literature,
contact the Literature Response Center at 800/477-8924.
See Table 2 for a complete listing of development-support tools for the ’C6x. For information on pricing and
availability, contact the nearest TI field sales office or authorized distributor.
Table 2. SMJ320C6x Development-Support Tools
DEVELOPMENT TOOL
PLATFORM
Software
PART NUMBER
AD0345AS8500RF - Single User
AD0345BS8500RF - Multi-user
†
‡
Ada 95 Compiler
Sun Solaris 2.3
C Compiler/Assembler/Linker/Assembly Optimizer
C Compiler/Assembler/Linker/Assembly Optimizer
Simulator
Win32
SPARC Solaris
Win32
TMDX3246855-07
TMDX3246555-07
TMDS3246851-07
TMDS3246551-07
TMDX324016X-07
Simulator
SPARC Solaris
XDS510 Debugger/Emulation Software
Win32, Windows NT
Hardware
§
XDS510 Emulator
PC
TMDS00510
¶
XDS510WS Emulator
SCSI
TMDS00510WS
Software/Hardware
PC/Win95/Windows NT
PC/Win95/Windows NT
EVM Evaluation Kit
TMDX3260A6201
TMDX326006201
EVM Evaluation Kit (including TMDX3246855–07)
†
Contact IRVINE Compiler Corporation (949) 250-1366 to order.
NT support estimated availability 1Q00.
Includes XDS510 board and JTAG emulation cable. TMDX324016X-07 C-source Debugger/Emulation software is not included.
Includes XDS510WS box, SCSI cable, power supply, and JTAG emulation cable.
‡
§
¶
XDS, XDS510, and XDS510WS are trademarks of Texas Instruments Incorporated.
Win32 and Windows NT are trademarks of Microsoft Corporation.
SPARC is a trademark of SPARC International, Inc.
Solaris is a trademark of Sun Microsystems, Inc.
21
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢅꢉ
ꢊ ꢋ ꢌꢍꢎ ꢏ ꢐ ꢑꢒꢓꢌꢏ ꢐ ꢎ ꢔꢏ ꢑ ꢏ ꢎꢍꢋ ꢀ ꢏ ꢑꢐ ꢍꢋ ꢓ ꢕꢌ ꢆꢖꢀ ꢀꢌ ꢕ
SGUS030B – APRIL 2000 – REVISED MAY 2001
device and development-support tool nomenclature
To designate the stages in the product-development cycle, TI assigns prefixes to the part numbers of all SMJ320
devices and support tools. Each SMJ320 member has one of three prefixes: SMX, SM, or SMJ. Texas
Instruments recommends two of three possible prefix designators for support tools: TMDX and TMDS. These
prefixes represent evolutionary stages of product development from engineering prototypes (SMX/TMDX)
through fully qualified production devices/tools (SMJ/TMDS).
Device development evolutionary flow:
SMX
SM
Experimental device that is not necessarily representative of the final device’s electrical
specifications
Final silicon die that conforms to the device’s electrical specifications but has not completed
quality and reliability verification
SMJ
Fully qualified production device processed to MIL-PRF-38535
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal qualification
testing.
TMDS
Fully qualified development-support product
SMX devices and TMDX development-support tools are shipped against the following disclaimer:
“Developmental product is intended for internal evaluation purposes.”
SMJ devices and TMDS development-support tools have been characterized fully, and the quality and reliability
of the device have been demonstrated fully. TI’s standard warranty applies.
Predictions show that prototype devices (SMX or SM) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, GLP), the temperature range, and the device speed range in megahertz (for example, 16 is
167 MHz). Figure 4 provides a legend for reading the complete device name for any SMJ320 family member.
22
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SGUS030B – APRIL 2000 – REVISED MAY 2001
device and development-support tool nomenclature (continued)
W
SMJ 320
C
6701 GLP
14
PREFIX
DEVICE SPEED RANGE
14 = 140 MHz
16 = 167 MHz
SMX= Experimental device
SMJ = MIL-PRF-38535, QML
SM = Commercial
processing
TEMPERATURE RANGE (DEFAULT: 0°C TO 90°C)
DEVICE FAMILY
320 = SMJ320 family
S
=
=
–40°C to 90°C, extended temperature
–55°C to 115°C, extended temperature
W
TECHNOLOGY
†
PACKAGE TYPE
GLP = 429-pin ceramic BGA
C
=
CMOS
DEVICE
’6x DSP:
6201B
6203
6701
†
BGA
=
Ball Grid Array
Figure 4. SMJ320 Device Nomenclature (Including SMJ320C6701)
documentation support
Extensive documentation supports all SMJ320 family generations of devices from product announcement
through applications development. The types of documentation available include: data sheets, such as this
document, with design specifications; complete user’s reference guides for all devices; technical briefs;
development-support tools; and hardware and software applications. The following is a brief, descriptive list of
support documentation specific to the ’C6x devices:
The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the
’C6000 CPU architecture, instruction set, pipeline, and associated interrupts.
The TMS320C6000 Peripherals Reference Guide (literature number SPRU190) describes the functionality of
the peripherals available on ’C6x devices, such as the external memory interface (EMIF), host-port interface
(HPI), multichannel buffered serial ports (McBSPs), direct-memory-access (DMA), enhanced
direct-memory-access (EDMA) controller, expansion bus (XB), clocking and phase-locked loop (PLL); and
power-down modes. This guide also includes information on internal data and program memories.
The TMS320C6000 Programmer’s Guide (literature number SPRU198) describes ways to optimize C and
assembly code for ’C6x devices and includes application program examples.
The TMS320C6x C Source Debugger User’s Guide (literature number SPRU188) describes how to invoke the
’C6x simulator and emulator versions of the C source debugger interface and discusses various aspects of the
debugger, including: command entry, code execution, data management, breakpoints, profiling, and analysis.
The TMS320C6x Peripheral Support Library Programmer’s Reference (literature number SPRU273) describes
the contents of the ’C6x peripheral support library of functions and macros. It lists functions and macros both
by header file and alphabetically, provides a complete description of each, and gives code examples to show
how they are used.
23
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SGUS030B – APRIL 2000 – REVISED MAY 2001
documentation support (continued)
TMS320C6000 Assembly Language Tools User’s Guide (literature number SPRU186) describes the assembly
language tools (assembler, linker, and other tools used to develop assembly language code), assembler
directives, macros, common object file format, and symbolic debugging directives for the ’C6000 generation of
devices.
The TMS320C6x Evaluation Module Reference Guide (literature number SPRU269) provides instructions for
installing and operating the ’C6x evaluation module. It also includes support software documentation,
application programming interfaces, and technical reference material.
TMS320C6000 DSP/BIOS User’s Guide (literature number SPRU303) describes how to use DSP/BIOS tools
and APIs to analyze embedded real-time DSP applications.
Code Composer User’s Guide (literature number SPRU296) explains how to use the Code Composer
development environment to build and debug embedded real-time DSP applications.
Code Composer Studio Tutorial (literature number SPRU301) introduces the Code Composer Studio integrated
development environment and software tools.
The TMS320C6000 Technical Brief (literature number SPRU197) gives an introduction to the ’C62x/C67x
devices, associated development tools, and third-party support.
A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support DSP research and
education. The TMS320 newsletter, Details on Signal Processing, is published quarterly and distributed to
update SMJ320 customers on product information. The TMS320 DSP bulletin board service (BBS) provides
access to information pertaining to the SMJ320 family, including documentation, source code, and object code
for many DSP algorithms and utilities. The BBS can be reached at 281/274-2323.
Information regarding TI DSP products is also available on the Worldwide Web at http://www.ti.com uniform
resource locator (URL).
clock PLL
All of the internal ’C67x clocks are generated from a single source through the CLKIN pin. This source clock
either drives the PLL, which multiplies the source clock in frequency to generate the internal CPU clock, or
bypasses the PLL to become the internal CPU clock.
To use the PLL to generate the CPU clock, the external PLL filter circuit must be properly designed. Table 3,
Table 4, and Figure 5 show the external PLL circuitry for either x1 (PLL bypass) or x4 PLL multiply modes.
Table 3 and Figure 6 show the external PLL circuitry for a system with ONLY x1 (PLL bypass) mode.
To minimize the clock jitter, a single clean power supply should power both the ’C67x device and the external
clock oscillator circuit. Noise coupling into PLLF will directly impact PLL clock jitter. The minimum CLKIN rise
and fall times should also be observed. For the input clock timing requirements, see the input and output clocks
electricals section. Guidelines for EMI filter selection are as follows: maximum attenuation frequency =
20-30 MHz, maximum dB attenuation = 45-50 dB, and minimum dB attenuation above 30 MHz = 20 dB.
†
Table 3. CLKOUT1 Frequency Ranges
PLLFREQ3
(C13)
PLLFREQ2
(G11)
PLLFREQ1
(F11)
CLKOUT1 Frequency Range
(MHz)
0
0
0
0
0
1
0
1
0
50–140
65–167
130–167
†
Due to overlap of frequency ranges when choosing the PLLFREQ, more than one frequency range can contain
the CLKOUT1 frequency. Choose the lowest frequency range that includes the desired frequency. For example,
for CLKOUT1 = 133 MHz, choose PLLFREQ value of 000b. For CLKOUT1 = 167 MHz, choose PLLFREQ value
of 001b. PLLFREQ values other than 000b, 001b, and 010b are reserved.
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SGUS030B – APRIL 2000 – REVISED MAY 2001
clock PLL (continued)
Table 4. ’C6701 PLL Component Selection Table
CPU CLOCK
CLKOUT2
CLKIN
RANGE
(MHz)
TYPICAL
R1
(Ω)
C1
(nF)
C2
(pF)
FREQUENCY
(CLKOUT1)
CLKMODE
RANGE
(MHz)
LOCK TIME
‡
(µs)
RANGE (MHz)
x4
12.5–41.7
50–167
25–83.5
60.4
27
560
75
‡
Under some operating conditions, the maximum PLL lock time may vary as much as 150% from the specified typical value. For example, if the
typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs.
PLLFREQ3
PLLFREQ2
PLLFREQ1
(see Table 3)
3.3V
PLLV
Internal to ’C6701
PLL
CLKMODE0
PLLMULT
CLKIN
CLKMODE1
C4
C3
PLLCLK
0.1 mF
10 mF
CLKIN
1
0
CPU
CLOCK
LOOP FILTER
Available Multiply Factors
PLL Multiply
C2
CPU Clock
Frequency
f(CPUCLOCK)
CLKMODE1
CLKMODE0
Factors
C1
R1
0
0
1
1
0
1
0
1
x1(BYPASS)
Reserved
Reserved
x4
1 x f(CLKIN)
Reserved
Reserved
4 x f(CLKIN)
NOTES: A. Keep the lead length and the number of vias between the PLLF pin, the PLLG pin, and R1, C1, and C2 to a minimum. In addition,
place all PLL external components (R1, C1, C2, C3, C4, and the EMI Filter) as close to the ’C6000 device as possible. For the best
performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or
components other than the ones shown.
B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (R1, C1, C2, C3, C4,
and the EMI Filter).
C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DV
.
DD
Figure 5. External PLL Circuitry for Either PLL x4 Mode or x1 (Bypass) Mode
25
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SGUS030B – APRIL 2000 – REVISED MAY 2001
clock PLL (continued)
PLLFREQ3
PLLFREQ2
PLLFREQ1
(see Table 3)
3.3V
PLLV
Internal to ’C6701
CLKMODE0
CLKMODE1
PLL
PLLMULT
CLKIN
PLLCLK
CLKIN
1
0
LOOP FILTER
CPU
CLOCK
NOTES: A. For a system with ONLY PLL x1 (bypass) mode, short the PLLF terminal to the PLLG terminal.
B. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DV
.
DD
Figure 6. External PLL Circuitry for x1 (Bypass) Mode Only
power-supply sequencing
TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However,
systems should be designed to ensure that neither supply is powered up for extended periods of time if the other
supply is below the proper operating voltage.
system-level design considerations
System-level design considerations, such as bus contention, may require supply sequencing to be
implemented. In this case, the core supply should be powered up at the same time as, or prior to (and powered
down after), the I/O buffers. This is to ensure that the I/O buffers receive valid inputs from the core before the
output buffers are powered up, thus, preventing bus contention with other chips on the board.
power-supply design considerations
For systems using the C6000 DSP platform of devices, the core supply may be required to provide in excess
of 2 A per DSP until the I/O supply is powered up. This extra current condition is a result of uninitialized logic
within the DSP(s) and is corrected once the CPU sees an internal clock pulse. With the PLL enabled, as the
I/O supply is powered on, a clock pulse is produced stopping the extra current draw from the supply. With the
PLL disabled, an external clock pulse may be required to stop this extra current draw. A normal current state
returns once the I/O power supply is turned on and the CPU sees a clock pulse. Decreasing the amount of time
between the core supply power up and the I/O supply power up can minimize the effects of this current draw.
A dual-power supply with simultaneous sequencing, such as available with TPS563xx controllers or PT69xx
plug-in power modules, can be used to eliminate the delay between core and I/O power up [see the Using the
TPS56300 to Power DSPs application report (literature number SLVA088)]. A Schottky diode can also be used
to tie the core rail to the I/O rail, effectively pulling up the I/O power supply to a level that can help initialize the
logic within the DSP.
Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize
inductance and resistance in the power delivery path. Additionally, when designing for high-performance
applications utilizing the C6000 platform of DSPs, the PC board should include separate power planes for
core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors.
26
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SGUS030B – APRIL 2000 – REVISED MAY 2001
†
absolute maximum ratings over operating case temperature range (unless otherwise noted)
Supply voltage range, CV
Supply voltage range, DV
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 2.3 V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V
DD
DD
Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V
Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V
Operating case temperature range, T S suffix device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40_C to 90_C
C
W suffix device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55_C to 115_C
Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55_C to 150_C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to V
SS
.
recommended operating conditions
MIN NOM
MAX UNIT
CV
DV
Supply voltage
1.81
3.14
0
1.9
3.30
0
1.99
3.46
0
V
V
DD
DD
Supply voltage
V
V
V
Supply ground
V
SS
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
2.0
V
IH
IL
0.8
–12
12
V
I
mA
mA
OH
OL
I
S suffix device
W suffix device
–40
–55
90
T
C
Case temperature
_C
115
27
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SGUS030B – APRIL 2000 – REVISED MAY 2001
electrical characteristics over recommended ranges of supply voltage and operating case
temperature (unless otherwise noted)
PARAMETER
High-level output voltage
Low-level output voltage
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
V
V
DV
DV
= MIN,
= MIN,
I
I
= MAX
= MAX
2.4
OH
DD
DD
OH
0.6
±10
±10
V
OL
OL
†
I
I
Input current
V = V
I SS
to DV
DD
uA
uA
I
Off-state output current
V
= DV
or 0 V
= NOM,
OZ
O DD
CV
DD
CPU clock = 150 MHz
‡
I
I
I
Supply current, CPU + CPU memory access
470
250
85
mA
mA
mA
DD2V
CV = NOM,
DD
CPU clock = 150 MHz
§
Supply current, peripherals
DD2V
DD3V
DV = NOM,
DD
CPU clock = 150 MHz
¶
Supply current, I/O pins
C
C
Input capacitance
Output capacitance
*15
*15
pF
pF
i
o
* This parameter is not tested.
†
TMS and TDI are not included due to internal pullups.
TRST is not included due to internal pulldown.
Measured with average CPU activity:
‡
50% of time:
50% of time:
Measured with average peripheral activity:
50% of time:
50% of time:
8 instructions per cycle, 32-bit DMEM access per cycle
2 instructions per cycle, 16-bit DMEM access per cycle
§
¶
Timers at max rate, McBSPs at E1 rate, and DMA burst transfer between DMEM and SDRAM
Timers at max rate, McBSPs at E1 rate, and DMA servicing McBSPs
Measured with average I/O activity (30-pF load, SDCLK on):
25% of time:
25% of time:
50% of time:
Reads from external SDRAM
Writes to external SDRAM
No activity
28
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SGUS030B – APRIL 2000 – REVISED MAY 2001
PARAMETER MEASUREMENT INFORMATION
I
OL
Tester Pin
Electronics
Output
Under
Test
50 Ω
V
ref
†
= 30 pF
C
T
I
OH
†
Typical distributed load circuit capacitance.
signal-transition levels
All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels.
V
ref
= 1.5 V
Figure 7. Input and Output Voltage Reference Levels for ac Timing Measurements
29
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ꢐ
ꢊ
ꢋ
ꢌ
ꢍ
ꢎ
ꢏ
ꢑ
ꢒ
ꢓ
ꢌ
ꢏ
ꢐ
ꢎ
ꢔ
ꢏ
ꢑ
ꢏ
ꢎ
ꢍ
ꢋ
ꢀ
ꢏ
ꢑ
ꢐ
ꢍ
ꢋ
ꢓ
ꢕ
ꢌ
ꢆ
ꢖ
ꢀ
ꢀ
ꢌ
ꢕ
SGUS030B – APRIL 2000 – REVISED MAY 2001
INPUT AND OUTPUT CLOCKS
†
timing requirements for CLKIN (see Figure 8)
’C6701-14
CLKMODE = x4 CLKMODE = x1
’C6701-16
CLKMODE = x4 CLKMODE = x1
NO.
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
1
2
t
t
Cycle time, CLKIN
28.4
7.1
24
6
ns
ns
c(CLKIN)
Pulse duration,
CLKIN high
‡
‡
‡
‡
*0.4C
*0.4C
*0.45C
*0.45C
*0.4C
*0.4C
*0.45C
*0.45C
w(CLKINH)
Pulse duration,
CLKIN low
‡
‡
‡
‡
3
4
t
t
ns
ns
w(CLKINL)
Transition time, CLKIN
*5
*0.6
*5
.
*0.6
t(CLKIN)
†
‡
The reference points for the rise and fall transitions are measured at 20% and 80%, respectively, of V
C = CLKIN cycle time in ns. For example, when CLKIN frequency is 10 MHz, use C = 100 ns.
IH
*This parameter is not tested.
1
4
2
CLKIN
3
4
Figure 8. CLKIN Timings
‡§
switching characteristics for CLKOUT1 (see Figure 9)
’C6701-14
’C6701-16
NO.
PARAMETER
UNIT
CLKMODE = x4
MIN
CLKMODE = x1
MIN MAX
MAX
1
2
3
4
t
t
t
t
Cycle time, CLKOUT1
*P – 0.7
*P + 0.7
*P – 0.7
*PH – 0.5
*PL – 0.5
*P + 0.7
*PH + 0.5
*PL + 0.5
*0.6
ns
ns
ns
ns
c(CKO1)
w(CKO1H)
w(CKO1L)
t(CKO1)
Pulse duration, CLKOUT1 high
Pulse duration, CLKOUT1 low
Transition time, CLKOUT1
*(P/2) – 0.5 *(P/2) + 0.5
*(P/2) – 0.5 *(P/2) + 0.5
*0.6
‡
§
P = 1/CPU clock frequency in nanoseconds (ns).
PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns.
*This parameter is not tested.
1
4
2
CLKOUT1
3
4
Figure 9. CLKOUT1 Timings
30
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SGUS030B – APRIL 2000 – REVISED MAY 2001
INPUT AND OUTPUT CLOCKS (CONTINUED)
†
switching characteristics for CLKOUT2 (see Figure 10)
’C6701-14
’C6701-16
NO.
PARAMETER
UNIT
MIN
MAX
1
2
3
4
t
t
t
t
Cycle time, CLKOUT2
*2P – 0.7
*P – 0.7
*P – 0.7
*2P + 0.7
*P + 0.7
*P + 0.7
*0.6
ns
ns
ns
ns
c(CKO2)
w(CKO2H)
w(CKO2L)
t(CKO2)
Pulse duration, CLKOUT2 high
Pulse duration, CLKOUT2 low
Transition time, CLKOUT2
†
P = 1/CPU clock frequency in ns.
*This parameter is not tested.
1
4
2
CLKOUT2
3
4
Figure 10. CLKOUT2 Timings
SDCLK, SSCLK timing parameters
SDCLK timing parameters are the same as CLKOUT2 parameters.
SSCLK timing parameters are the same as CLKOUT1 or CLKOUT2 parameters, depending on SSCLK
configuration.
switching characteristics for the relation of SSCLK, SDCLK, and CLKOUT2 to CLKOUT1
(see Figure 11)
’C6701-14
’C6701-16
NO.
PARAMETER
UNIT
MIN
–0.8
–1.0
–1.5
MAX
3.4
1
2
3
t
t
t
Delay time, CLKOUT1 edge to SSCLK edge
ns
ns
ns
d(CKO1-SSCLK)
d(CKO1-SSCLK1/2)
d(CKO1-CKO2)
Delay time, CLKOUT1 edge to SSCLK edge (1/2 clock rate)
Delay time, CLKOUT1 edge to CLKOUT2 edge
3.0
2.5
4
t
Delay time, CLKOUT1 edge to SDCLK edge
–1.5
1.9
ns
d(CKO1-SDCLK)
CLKOUT1
1
2
3
4
SSCLK
SSCLK (1/2rate)
CLKOUT2
SDCLK
Figure 11. Relation of CLKOUT2, SDCLK, and SSCLK to CLKOUT1
31
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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SGUS030B – APRIL 2000 – REVISED MAY 2001
ASYNCHRONOUS MEMORY TIMING
†
timing requirements for asynchronous memory cycles (see Figure 12 and Figure 13)
’C6701-14
’C6701-16
NO.
UNIT
MIN MAX
6
7
t
t
t
t
Setup time, read EDx valid before CLKOUT1 high
Hold time, read EDx valid after CLKOUT1 high
Setup time, ARDY valid before CLKOUT1 high
Hold time, ARDY valid after CLKOUT1 high
4.8
1.5
3.5
1.5
ns
ns
ns
ns
su(EDV-CKO1H)
h(CKO1H-EDV)
su(ARDY-CKO1H)
h(CKO1H-ARDY)
10
11
†
To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. If ARDY does meet setup or hold
time, it may be recognized in the current cycle or the next cycle. Thus, ARDY can be an asynchronous input.
‡
switching characteristics for asynchronous memory cycles (see Figure 12 and Figure 13)
’C6701-14
’C6701-16
NO.
PARAMETER
UNIT
MIN
MAX
4.5
1
2
t
t
t
t
t
t
t
t
t
t
Delay time, CLKOUT1 high to CEx valid
Delay time, CLKOUT1 high to BEx valid
Delay time, CLKOUT1 high to BEx invalid
Delay time, CLKOUT1 high to EAx valid
Delay time, CLKOUT1 high to EAx invalid
Delay time, CLKOUT1 high to AOE valid
Delay time, CLKOUT1 high to ARE valid
Delay time, CLKOUT1 high to EDx valid
Delay time, CLKOUT1 high to EDx invalid
Delay time, CLKOUT1 high to AWE valid
–1.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
d(CKO1H-CEV)
d(CKO1H-BEV)
d(CKO1H-BEIV)
d(CKO1H-EAV)
d(CKO1H-EAIV)
d(CKO1H-AOEV)
d(CKO1H-AREV)
d(CKO1H-EDV)
d(CKO1H-EDIV)
d(CKO1H-AWEV)
4.5
3
–1.0
4
4.5
5
–1.0
–1.0
–1.0
8
4.5
4.5
4.5
9
12
13
14
–1.0
–1.0
4.5
‡
The minimum delay is also the minimum output hold after CLKOUT1 high.
32
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SGUS030B – APRIL 2000 – REVISED MAY 2001
ASYNCHRONOUS MEMORY TIMING (CONTINUED)
Not ready = 2
Setup = 2
Strobe = 5
HOLD = 1
CLKOUT1
CEx
1
2
4
1
3
BE[3:0]
EA[21:2]
ED[31:0]
AOE
5
7
6
8
8
9
9
ARE
AWE
11
11
10
10
ARDY
Figure 12. Asynchronous Memory Read Timing
Not ready = 2
Setup = 2
Strobe = 5
HOLD = 1
CLKOUT1
1
2
4
1
3
5
CEx
BE[3:0]
EA[21:2]
12
13
14
ED[31:0]
AOE
ARE
14
AWE
11
11
10
10
ARDY
Figure 13. Asynchronous Memory Write Timing
33
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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SGUS030B – APRIL 2000 – REVISED MAY 2001
SYNCHRONOUS-BURST MEMORY TIMING
timing requirements for synchronous-burst SRAM cycles (full-rate SSCLK)
(see Figure 14)
’C6701-14
’C6701-16
NO.
UNIT
MIN
2.6
MAX
MIN
2.5
MAX
7
8
t
t
Setup time, read EDx valid before SSCLK high
Hold time, read EDx valid after SSCLK high
ns
ns
su(EDV-SSCLKH)
1.5
1.5
h(SSCLKH-EDV)
†
switching characteristics for synchronous-burst SRAM cycles (full-rate SSCLK)
(see Figure 14 and Figure 15)
’C6701-14
’C6701-16
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
1
2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Output setup time, CEx valid before SSCLK high
Output hold time, CEx valid after SSCLK high
Output setup time, BEx valid before SSCLK high
Output hold time, BEx invalid after SSCLK high
Output setup time, EAx valid before SSCLK high
Output hold time, EAx invalid after SSCLK high
Output setup time, SSADS valid before SSCLK high
Output hold time, SSADS valid after SSCLK high
Output setup time, SSOE valid before SSCLK high
Output hold time, SSOE valid after SSCLK high
Output setup time, EDx valid before SSCLK high
Output hold time, EDx invalid after SSCLK high
Output setup time, SSWE valid before SSCLK high
Output hold time, SSWE valid after SSCLK high
0.5P – 1.5
0.5P – 2.5
0.5P – 1.6
0.5P – 2.5
0.5P – 1.7
0.5P – 2.5
0.5P – 1.5
0.5P – 2.5
0.5P – 1.5
0.5P – 2.5
0.5P – 1.5
0.5P – 2.5
0.5P – 1.5
0.5P – 2.5
0.5P – 1.3
0.5P – 2.3
0.5P – 1.6
0.5P – 2.3
0.5P – 1.7
0.5P – 2.5
0.5P – 1.3
0.5P – 2.3
0.5P – 1.3
0.5P – 2.5
0.5P – 1.3
0.5P – 2.5
0.5P – 1.3
0.5P – 2.3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
osu(CEV-SSCLKH)
oh(SSCLKH-CEV)
osu(BEV-SSCLKH)
oh(SSCLKH-BEIV)
osu(EAV-SSCLKH)
oh(SSCLKH-EAIV)
osu(ADSV-SSCLKH)
oh(SSCLKH-ADSV)
osu(OEV-SSCLKH)
oh(SSCLKH-OEV)
osu(EDV-SSCLKH)
oh(SSCLKH-EDIV)
osu(WEV-SSCLKH)
oh(SSCLKH-WEV)
3
4
5
6
9
10
11
12
13
14
15
16
†
The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter.
When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.
For CLKMODE x1, 0.5P is defined as PH (pulse duration of CLKIN high) for all output setup times; 0.5P is defined as PL (pulse duration of CLKIN
low) for all output hold times.
34
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ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢅ ꢉ
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SGUS030B – APRIL 2000 – REVISED MAY 2001
SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)
SSCLK
CEx
1
2
3
5
4
BE[3:0]
BE1
A1
BE2
BE3
BE4
6
EA[21:2]
A2
7
A3
8
A4
Q1
Q2
Q3
Q4
ED[31:0]
SSADS
9
10
11
12
SSOE
SSWE
Figure 14. SBSRAM Read Timing (Full-Rate SSCLK)
SSCLK
1
3
2
CEx
BE[3:0]
4
BE1
A1
BE2
A2
BE3
A3
BE4
5
6
EA[21:2]
A4
13
14
D4
ED[31:0]
D1
D2
D3
9
10
SSADS
SSOE
15
16
SSWE
Figure 15. SBSRAM Write Timing (Full-Rate SSCLK)
35
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SGUS030B – APRIL 2000 – REVISED MAY 2001
SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)
timing requirements for synchronous-burst SRAM cycles (half-rate SSCLK) (see Figure 16)
’C6701-14
’C6701-16
NO.
UNIT
MIN
3.8
MAX
MIN
3.8
MAX
7
8
t
t
Setup time, read EDx valid before SSCLK high
Hold time, read EDx valid after SSCLK high
ns
ns
su(EDV-SSCLKH)
1.5
1.5
h(SSCLKH-EDV)
†
switching characteristics for synchronous-burst SRAM cycles (half-rate SSCLK)
(see Figure 16 and Figure 17)
’C6701-14
’C6701-16
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
1
2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Output setup time, CEx valid before SSCLK high
Output hold time, CEx valid after SSCLK high
Output setup time, BEx valid before SSCLK high
Output hold time, BEx invalid after SSCLK high
Output setup time, EAx valid before SSCLK high
Output hold time, EAx invalid after SSCLK high
Output setup time, SSADS valid before SSCLK high
Output hold time, SSADS valid after SSCLK high
Output setup time, SSOE valid before SSCLK high
Output hold time, SSOE valid after SSCLK high
Output setup time, EDx valid before SSCLK high
Output hold time, EDx invalid after SSCLK high
Output setup time, SSWE valid before SSCLK high
Output hold time, SSWE valid after SSCLK high
1.5P – 5.5
0.5P – 2.3
1.5P – 5.5
0.5P – 2.3
1.5P – 5.5
0.5P – 2.3
1.5P – 5.5
0.5P – 2.3
1.5P – 5.5
0.5P – 2.3
1.5P – 5.5
0.5P – 2.3
1.5P – 5.5
0.5P – 2.3
1.5P – 4.5
0.5P – 2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
osu(CEV-SSCLKH)
oh(SSCLKH-CEV)
osu(BEV-SSCLKH)
oh(SSCLKH-BEIV)
osu(EAV-SSCLKH)
oh(SSCLKH-EAIV)
osu(ADSV-SSCLKH)
oh(SSCLKH-ADSV)
osu(OEV-SSCLKH)
oh(SSCLKH-OEV)
osu(EDV-SSCLKH)
oh(SSCLKH-EDIV)
osu(WEV-SSCLKH)
oh(SSCLKH-WEV)
3
1.5P – 4.5
0.5P – 2
4
5
1.5P – 4.5
0.5P – 2
6
9
1.5P – 4.5
0.5P – 2
10
11
12
13
14
15
16
1.5P – 4.5
0.5P – 2
1.5P – 4.5
0.5P – 2.2
1.5P – 4.5
0.5P – 2
†
The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter.
When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.
For CLKMODE x1:
1.5P = P + PH, where P = 1/CPU clock frequency, and PH = pulse duration of CLKIN high.
0.5P = PL, where PL = pulse duration of CLKIN low.
36
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢅ ꢉ
ꢊ ꢋꢌ ꢍꢎ ꢏꢐꢑ ꢒꢓ ꢌꢏ ꢐꢎ ꢔꢏ ꢑꢏ ꢎꢍꢋ ꢀꢏ ꢑ ꢐꢍꢋ ꢓꢕ ꢌ ꢆꢖ ꢀ ꢀꢌ ꢕ
SGUS030B – APRIL 2000 – REVISED MAY 2001
SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)
SSCLK
CEx
1
2
3
4
6
BE[3:0]
BE1
BE2
A2
BE3
A3
BE4
5
A1
A4
8
EA[21:2]
ED[31:0]
SSADS
7
Q1
Q2
Q3
10
Q4
9
11
12
SSOE
SDWE
Figure 16. SBSRAM Read Timing (1/2 Rate SSCLK)
SSCLK
1
3
2
CEx
BE[3:0]
4
6
BE1
BE2
A2
BE3
A3
BE4
A4
5
EA[21:2]
A1
13
14
10
Q1
Q2
Q3
Q4
ED[31:0]
9
SSADS
SSOE
15
16
SSWE
Figure 17. SBSRAM Write Timing (1/2 Rate SSCLK)
37
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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SGUS030B – APRIL 2000 – REVISED MAY 2001
SYNCHRONOUS DRAM TIMING
timing requirements for synchronous DRAM cycles (see Figure 18)
’C6701-14
’C6701-16
NO.
UNIT
MIN MAX
MIN MAX
7
8
t
t
Setup time, read EDx valid before SDCLK high
Hold time, read EDx valid after SDCLK high
2
3
2
3
ns
ns
su(EDV-SDCLKH)
h(SDCLKH-EDV)
†
switching characteristics for synchronous DRAM cycles (see Figure 18–Figure 23)
’C6701-14
’C6701-16
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
1
2
3
4
5
6
t
t
t
t
t
t
Output setup time, CEx valid before SDCLK high
Output hold time, CEx valid after SDCLK high
Output setup time, BEx valid before SDCLK high
Output hold time, BEx invalid after SDCLK high
Output setup time, EAx valid before SDCLK high
Output hold time, EAx invalid after SDCLK high
1.5P – 5
0.5P – 1.9
1.5P – 5
0.5P – 1.9
1.5P – 5
0.5P – 1.9
1.5P – 4
0.5P – 1.5
1.5P – 4
0.5P – 1.5
1.5P – 4
0.5P – 1.5
ns
ns
ns
ns
ns
ns
osu(CEV-SDCLKH)
oh(SDCLKH-CEV)
osu(BEV-SDCLKH)
oh(SDCLKH-BEIV)
osu(EAV-SDCLKH)
oh(SDCLKH-EAIV)
Output setup time, SDCAS valid before SDCLK
high
9
t
1.5P – 5
1.5P – 4
ns
osu(SDCAS-SDCLKH)
10
11
12
t
t
t
Output hold time, SDCAS valid after SDCLK high
Output setup time, EDx valid before SDCLK high
Output hold time, EDx invalid after SDCLK high
0.5P – 1.9
1.5P – 5
0.5P – 1.5
1.5P – 4
ns
ns
ns
oh(SDCLKH-SDCAS)
osu(EDV-SDCLKH)
oh(SDCLKH-EDIV)
0.5P – 1.9
0.5P – 1.5
Output setup time, SDWE valid before SDCLK
high
13
14
15
t
t
t
1.5P – 5
0.5P – 1.9
1.5P – 5
1.5P – 4
0.5P – 1.5
1.5P – 4
ns
ns
ns
osu(SDWE-SDCLKH)
oh(SDCLKH-SDWE)
osu(SDA10V-SDCLKH)
Output hold time, SDWE valid after SDCLK high
Output setup time, SDA10 valid before SDCLK
high
Output hold time, SDA10 invalid after SDCLK
high
16
t
0.5P – 1.9
0.5P – 1.5
ns
oh(SDCLKH-SDA10IV)
Output setup time, SDRAS valid before SDCLK
high
17
18
t
t
1.5P – 5
1.5P – 4
ns
ns
osu(SDRAS-SDCLKH)
Output hold time, SDRAS valid after SDCLK high
0.5P – 1.9
0.5P – 1.5
oh(SDCLKH-SDRAS)
†
The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter.
When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.
For CLKMODE x1:
1.5P = P + PH, where P = 1/CPU clock frequency, and PH = pulse duration of CLKIN high.
0.5P = PL, where PL = pulse duration of CLKIN low.
38
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢅ ꢉ
ꢊ ꢋꢌ ꢍꢎ ꢏꢐꢑ ꢒꢓ ꢌꢏ ꢐꢎ ꢔꢏ ꢑꢏ ꢎꢍꢋ ꢀꢏ ꢑ ꢐꢍꢋ ꢓꢕ ꢌ ꢆꢖ ꢀ ꢀꢌ ꢕ
SGUS030B – APRIL 2000 – REVISED MAY 2001
SYNCHRONOUS DRAM TIMING (CONTINUED)
READ
READ
READ
SDCLK
1
5
2
CEx
3
4
BE[3:0]
BE1
BE2
CA3
BE3
7
6
CA1
CA2
EA[15:2]
ED[31:0]
8
D1
D2
D3
15
9
16
10
SDA10
SDRAS
SDCAS
SDWE
Figure 18. Three SDRAM Read Commands
WRITE
WRITE
WRITE
SDCLK
CEx
1
2
3
4
BE1
CA1
BE2
CA2
D2
BE3
CA3
D3
BE[3:0]
EA[15:2]
ED[31:0]
5
6
11
12
D1
15
16
SDA10
SDRAS
9
10
14
SDCAS
SDWE
13
Figure 19. Three SDRAM Write Commands
39
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢅꢉ
ꢊ ꢋ ꢌꢍꢎ ꢏ ꢐ ꢑꢒꢓꢌꢏ ꢐ ꢎ ꢔꢏ ꢑ ꢏ ꢎꢍꢋ ꢀ ꢏ ꢑꢐ ꢍꢋ ꢓ ꢕꢌ ꢆꢖꢀ ꢀꢌ ꢕ
SGUS030B – APRIL 2000 – REVISED MAY 2001
SYNCHRONOUS DRAM TIMING (CONTINUED)
ACTV
SDCLK
1
2
CEx
BE[3:0]
5
Bank Activate/Row Address
EA[15:2]
ED[31:0]
15
Row Address
SDA10
17
18
SDRAS
SDCAS
SDWE
Figure 20. SDRAM ACTV Command
DCAB
SDCLK
1
2
CEx
BE[3:0]
EA[15:2]
ED[31:0]
15
16
SDA10
17
18
SDRAS
SDCAS
13
14
SDWE
Figure 21. SDRAM DCAB Command
40
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢅ ꢉ
ꢊ ꢋꢌ ꢍꢎ ꢏꢐꢑ ꢒꢓ ꢌꢏ ꢐꢎ ꢔꢏ ꢑꢏ ꢎꢍꢋ ꢀꢏ ꢑ ꢐꢍꢋ ꢓꢕ ꢌ ꢆꢖ ꢀ ꢀꢌ ꢕ
SGUS030B – APRIL 2000 – REVISED MAY 2001
SYNCHRONOUS DRAM TIMING (CONTINUED)
REFR
SDCLK
1
2
CEx
BE[3:0]
EA[15:2]
ED[31:0]
SDA10
SDRAS
17
18
9
10
SDCAS
SDWE
Figure 22. SDRAM REFR Command
MRS
SDCLK
1
2
6
CEx
BE[3:0]
5
MRS Value
EA[15:2]
ED[31:0]
SDA10
SDRAS
17
18
10
14
9
SDCAS
SDWE
13
Figure 23. SDRAM MRS Command
41
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢅꢉ
ꢊ ꢋ ꢌꢍꢎ ꢏ ꢐ ꢑꢒꢓꢌꢏ ꢐ ꢎ ꢔꢏ ꢑ ꢏ ꢎꢍꢋ ꢀ ꢏ ꢑꢐ ꢍꢋ ꢓ ꢕꢌ ꢆꢖꢀ ꢀꢌ ꢕ
SGUS030B – APRIL 2000 – REVISED MAY 2001
HOLD/HOLDA TIMING
†
timing requirements for the hold/hold acknowledge cycles (see Figure 24)
’C6701-14
’C6701-16
NO.
UNIT
MIN MAX
1
2
t
t
Setup time, HOLD high before CLKOUT1 high
Hold time, HOLD low after CLKOUT1 high
5
2
ns
ns
su(HOLDH-CKO1H)
h(CKO1H-HOLDL)
†
HOLD is synchronized internally. Therefore, if setup and hold times are not met, it will either be recognized in the current cycle or in the next cycle.
Thus, HOLD can be an asynchronous input.
‡
switching characteristics for the hold/hold acknowledge cycles (see Figure 24)
’C6701-14
’C6701-16
NO.
PARAMETER
UNIT
MIN
MAX
§
3
4
5
6
7
8
9
t
t
t
t
t
t
t
Response time, HOLD low to EMIF high impedance
Response time, EMIF high impedance to HOLDA low
Response time, HOLD high to HOLDA high
4P
ns
ns
ns
ns
ns
ns
ns
R(HOLDL-EMHZ)
R(EMHZ-HOLDAL)
R(HOLDH-HOLDAH)
d(CKO1H-HOLDAL)
d(CKO1H-BHZ)
2P
7P
8
4P
1
Delay time, CLKOUT1 high to HOLDA valid
¶
Delay time, CLKOUT1 high to EMIF Bus high impedance
*1
*1
3P
*8
¶
Delay time, CLKOUT1 high to EMIF Bus low impedance
*12
6P
d(CKO1H-BLZ)
¶
Response time, HOLD high to EMIF Bus low impedance
R(HOLDH-BLZ)
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.
All pending EMIF transactions are allowed to complete before HOLDA is asserted. The worst cases for this is an asynchronous read or write
with external ARDY used or a minimum of eight consecutive SDRAM reads or writes when RBTR8 = 1. If no bus transactions are occurring, then
the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting the NOHOLD = 1.
¶
EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, and SDWE.
*This parameter is not tested.
DSP Owns Bus
External Requester
DSP Owns Bus
5
4
9
2
3
CLKOUT1
HOLD
2
1
1
6
6
HOLDA
7
8
†
EMIF Bus
’C6701
Ext Req
’C6701
†
EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, and SDWE.
Figure 24. HOLD/HOLDA Timing
42
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢅ ꢉ
ꢊ ꢋꢌ ꢍꢎ ꢏꢐꢑ ꢒꢓ ꢌꢏ ꢐꢎ ꢔꢏ ꢑꢏ ꢎꢍꢋ ꢀꢏ ꢑ ꢐꢍꢋ ꢓꢕ ꢌ ꢆꢖ ꢀ ꢀꢌ ꢕ
SGUS030B – APRIL 2000 – REVISED MAY 2001
RESET TIMING
timing requirements for reset (see Figure 25)
’C6701-14
’C6701-16
NO.
UNIT
MIN
*10
MAX
CLKOUT1
cycles
†
Width of the RESET pulse (PLL stable)
1
t
w(RESET)
‡
Width of the RESET pulse (PLL needs to sync up)
*250
µs
†
This parameter applies to CLKMODE x1 when CLKIN is stable and applies to CLKMODE x4 when CLKIN and PLL are stable.
*This parameter is not tested.
This parameter only applies to CLKMODE x4. The RESET signal is not connected internally to the clock PLL circuit. The PLL, however, may
need up to 250 µs to stabilize following device powerup or after PLL configuration has been changed. During that time, RESET must be asserted
to ensure proper device operation. See the clock PLL section for PLL lock times.
‡
§
switching characteristics during reset (see Figure 25)
’C6701-14
’C6701-16
NO.
PARAMETER
UNIT
MIN
*1
MAX
CLKOUT1
cycles
2
t
Response time to change of value in RESET signal
R(RESET)
3
4
t
t
t
t
t
t
t
t
t
t
t
t
Delay time, CLKOUT1 high to CLKOUT2 invalid
Delay time, CLKOUT1 high to CLKOUT2 valid
Delay time, CLKOUT1 high to SDCLK invalid
Delay time, CLKOUT1 high to SDCLK valid
Delay time, CLKOUT1 high to SSCLK invalid
Delay time, CLKOUT1 high to SSCLK valid
Delay time, CLKOUT1 high to low group invalid
Delay time, CLKOUT1 high to low group valid
Delay time, CLKOUT1 high to high group invalid
Delay time, CLKOUT1 high to high group valid
Delay time, CLKOUT1 high to Z group high impedance
Delay time, CLKOUT1 high to Z group valid
*–1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
d(CKO1H-CKO2IV)
d(CKO1H-CKO2V)
d(CKO1H-SDCLKIV)
d(CKO1H-SDCLKV)
d(CKO1H-SSCKIV)
d(CKO1H-SSCKV)
d(CKO1H-LOWIV)
d(CKO1H-LOWV)
d(CKO1H-HIGHIV)
d(CKO1H-HIGHV)
d(CKO1H-ZHZ)
*10
*10
*10
*10
*10
*10
5
*–1
*–1
*–1
*–1
*–1
6
7
8
9
10
11
12
13
14
d(CKO1H-ZV)
§
Low group consists of:
High group consists of:
Z group consists of:
IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1.
HRDY and HINT.
EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS,
SDWE, HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, and FSR1.
*This parameter is not tested.
43
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢅꢉ
ꢐ
ꢊ
ꢋ
ꢌ
ꢍ
ꢎ
ꢏ
ꢑ
ꢒ
ꢓ
ꢌ
ꢏ
ꢐ
ꢎ
ꢔ
ꢏ
ꢑ
ꢏ
ꢎꢍ
ꢋ
ꢀ
ꢏ
ꢑ
ꢐ
ꢍ
ꢋ
ꢓ
ꢕ
ꢌ
ꢆ
ꢖ
ꢀ
ꢀ
ꢌ
ꢕ
SGUS030B – APRIL 2000 – REVISED MAY 2001
RESET TIMING (CONTINUED)
CLKOUT1
1
2
2
RESET
3
5
7
9
4
6
CLKOUT2
SDCLK
8
SSCLK
10
12
14
†
†
†
LOW GROUP
HIGH GROUP
Z GROUP
11
13
†
Low group consists of:
High group consists of:
Z group consists of:
IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1.
HRDY and HINT.
EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS,
SDWE, HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, and FSR1.
Figure 25. Reset Timing
44
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢅ ꢉ
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SGUS030B – APRIL 2000 – REVISED MAY 2001
EXTERNAL INTERRUPT/RESET TIMING
†‡
timing requirements for interrupt response cycles (see Figure 26)
’C6701-14
’C6701-16
NO.
UNIT
MIN
*2P
*2P
MAX
2
3
t
t
Width of the interrupt pulse low
Width of the interrupt pulse high
ns
ns
w(ILOW)
w(IHIGH)
†
‡
Interrupt signals are synchronized internally and are potentially recognized one cycle later if setup and hold times are violated. Thus, they can
be connected to asynchronous inputs.
P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.
*This parameter is not tested.
§
switching characteristics during interrupt response cycles (see Figure 26)
’C6701-14
’C6701-16
NO.
PARAMETER
UNIT
MIN
MAX
1
4
5
6
t
t
t
t
Response time, EXT_INTx high to IACK high
Delay time, CLKOUT2 low to IACK valid
Delay time, CLKOUT2 low to INUMx valid
Delay time, CLKOUT2 low to INUMx invalid
9P
ns
ns
ns
ns
R(EINTH-IACKH)
d(CKO2L-IACKV)
d(CKO2L-INUMV)
d(CKO2L-INUMIV)
–0.5P 13 – 0.5P
10 – 0.5P
–0.5P
§
P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.
When the PLL is used (CLKMODE x4), 0.5P = 1/(2 × CPU clock frequency).
For CLKMODE x1: 0.5P = PH, where PH is the high period of CLKIN.
1
CLKOUT2
3
2
EXT_INTx, NMI
Intr Flag
4
4
IACK
6
5
Interrupt Number
INUMx
Figure 26. Interrupt Timing
45
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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SGUS030B – APRIL 2000 – REVISED MAY 2001
HOST-PORT INTERFACE TIMING
†‡
timing requirements for host-port interface cycles (see Figure 27, Figure 28, Figure 29, and
Figure 30)
’C6701-14
’C6701-16
NO.
UNIT
MIN
4
MAX
§
1
2
t
t
t
t
t
t
t
t
Setup time, select signals valid before HSTROBE low
ns
ns
ns
ns
ns
ns
ns
ns
su(SEL-HSTBL)
h(HSTBL-SEL)
w(HSTBL)
§
Hold time, select signals valid after HSTROBE low
2
3
Pulse duration, HSTROBE low
*2P
*2P
4
4
Pulse duration, HSTROBE high between consecutive accesses
w(HSTBH)
§
Setup time, select signals valid before HAS low
10
11
12
13
su(SEL-HASL)
h(HASL-SEL)
su(HDV-HSTBH)
h(HSTBH-HDV)
§
Hold time, select signals valid after HAS low
2
Setup time, host data valid before HSTROBE high
Hold time, host data valid after HSTROBE high
3
2
Hold time, HSTROBE low after HRDY low. HSTROBE should not be
inactivated until HRDY is active (low); otherwise, HPI writes will not
complete properly.
14
t
*1
ns
h(HRDYL-HSTBL)
18
19
t
t
Setup time, HAS low before HSTROBE low
Hold time, HAS low after HSTROBE low
*2
*2
ns
ns
su(HASL-HSTBL)
h(HSTBL-HASL)
*This parameter is not tested.
†
‡
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency
in ns. For example, when running parts at 167 MHz, use P = 6 ns.
§
Select signals include: HCNTRL[1:0], HR/W, and HHWIL.
†‡
switching characteristics during host-port interface cycles (see Figure 27, Figure 28, Figure 29,
and Figure 30)
’C6701-14
’C6701-16
NO.
PARAMETER
UNIT
MIN MAX
¶
5
6
t
t
t
t
t
t
t
t
Delay time, HCS to HRDY
1
1
12
12
ns
ns
ns
ns
ns
ns
ns
ns
d(HCS-HRDY)
#
Delay time, HSTROBE low to HRDY high
d(HSTBL-HRDYH)
oh(HSTBL-HDLZ)
d(HDV-HRDYL)
oh(HSTBH-HDV)
d(HSTBH-HDHZ)
d(HSTBL-HDV)
d(HSTBH-HRDYH)
7
Output hold time, HD low impedance after HSTROBE low for an HPI read
Delay time, HD valid to HRDY low
*4
8
*P – 3 *P + 3
9
Output hold time, HD valid after HSTROBE high
Delay time, HSTROBE high to HD high impedance
Delay time, HSTROBE low to HD valid
3
*3
3
12
*12
12
15
16
17
||
Delay time, HSTROBE high to HRDY high
1
12
*This parameter is not tested.
†
‡
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency
in ns. For example, when running parts at 167 MHz, use P = 6 ns.
¶
#
||
HCS enables HRDY, and HRDY is always low when HCS is high. The case where HRDY goes high when HCS falls indicates that HPI is busy
completing a previous HPID write or READ with autoincrement.
This parameter is used during an HPID read. At the beginning of the first half-word transfer on the falling edge of HSTROBE, the HPI sends the
request to the DMA auxiliary channel, and HRDY remains high until the DMA auxiliary channel loads the requested data into HPID.
This parameter is used after the second half-word of an HPID write or autoincrement read. HRDY remains low if the access is not an HPID write
or autoincrement read. Reading or writing to HPIC or HPIA does not affect the HRDY signal.
46
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢅ ꢉ
ꢊ ꢋꢌ ꢍꢎ ꢏꢐꢑ ꢒꢓ ꢌꢏ ꢐꢎ ꢔꢏ ꢑꢏ ꢎꢍꢋ ꢀꢏ ꢑ ꢐꢍꢋ ꢓꢕ ꢌ ꢆꢖ ꢀ ꢀꢌ ꢕ
SGUS030B – APRIL 2000 – REVISED MAY 2001
HOST-PORT INTERFACE TIMING (CONTINUED)
HAS
HCNTL[1:0]
HR/W
1
1
1
1
2
2
2
2
2
2
1
1
HHWIL
4
3
†
HSTROBE
HCS
15
9
15
9
7
16
HD[15:0] (output)
HRDY (case 1)
HRDY (case 2)
5
5
1st half-word
2nd half-word
5
8
8
17
17
6
†
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 27. HPI Read Timing (HAS Not Used, Tied High)
HAS
19
11
19
11
10
10
10
10
HCNTL[1:0]
HR/W
11
11
11
11
10
10
HHWIL
4
3
†
HSTROBE
18
18
HCS
15
15
7
9
16
9
17
17
HD[15:0] (output)
HRDY (case 1)
HRDY (case 2)
1st half-word
2nd half-word
5
8
8
5
5
6
†
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 28. HPI Read Timing (HAS Used)
47
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢅꢉ
ꢊ ꢋ ꢌꢍꢎ ꢏ ꢐ ꢑꢒꢓꢌꢏ ꢐ ꢎ ꢔꢏ ꢑ ꢏ ꢎꢍꢋ ꢀ ꢏ ꢑꢐ ꢍꢋ ꢓ ꢕꢌ ꢆꢖꢀ ꢀꢌ ꢕ
SGUS030B – APRIL 2000 – REVISED MAY 2001
HOST-PORT INTERFACE TIMING (CONTINUED)
HAS
1
1
2
2
HCNTL[1:0]
HBE[1:0]
12
12
13
13
1
1
1
1
2
2
2
2
HR/W
HHWIL
3
4
14
†
HSTROBE
HCS
HD[15:0] (input)
HRDY
12
12
13
2nd half-word
13
17
1st half-word
5
5
†
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 29. HPI Write Timing (HAS Not Used, Tied High)
HAS
HBE[1:0]
12
12
19
13
19
13
11
11
11
11
11
11
10
10
10
10
HCNTL[1:0]
10
10
HR/W
HHWIL
3
4
14
†
HSTROBE
18
12
18
HCS
HD[15:0] (input)
HRDY
12
13
13
1st half-word
2nd half-word
5
5
17
†
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 30. HPI Write Timing (HAS Used)
48
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢅ ꢉ
ꢊ ꢋꢌ ꢍꢎ ꢏꢐꢑ ꢒꢓ ꢌꢏ ꢐꢎ ꢔꢏ ꢑꢏ ꢎꢍꢋ ꢀꢏ ꢑ ꢐꢍꢋ ꢓꢕ ꢌ ꢆꢖ ꢀ ꢀꢌ ꢕ
SGUS030B – APRIL 2000 – REVISED MAY 2001
MULTICHANNEL BUFFERED SERIAL PORT TIMING
†‡
timing requirements for McBSP (see Figure 31)
’C6701-14
’C6701-16
NO.
UNIT
MIN
*2P
*P – 1
*13
4
MAX
2
3
t
t
Cycle time, CLKR/X
CLKR/X ext
CLKR/X ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
ns
ns
c(CKRX)
Pulse duration, CLKR/X high or CLKR/X low
w(CKRX)
5
6
t
t
t
t
t
t
Setup time, external FSR high before CLKR low
Hold time, external FSR high after CLKR low
Setup time, DR valid before CLKR low
ns
ns
ns
ns
ns
ns
su(FRH-CKRL)
h(CKRL-FRH)
su(DRV-CKRL)
h(CKRL-DRV)
su(FXH-CKXL)
h(CKXL-FXH)
*7
4
10
1
7
4
8
Hold time, DR valid after CLKR low
4
*13
4
10
11
Setup time, external FSX high before CLKX low
Hold time, external FSX high after CLKX low
*7
3
†
‡
P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.
CLKRP = CLKXP = FSRP = FSXP = 0 in the pin control register (PCR). If polarity of any of the signals is inverted, then the timing references
of that signal are also inverted.
*This parameter is not tested.
49
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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SGUS030B – APRIL 2000 – REVISED MAY 2001
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
†‡§
switching characteristics for McBSP
(see Figure 31)
’C6701-14
’C6701-16
NO.
PARAMETER
UNIT
MIN
3
MAX
15
Delay time, CLKS high to CLKR/X high for internal
CLKR/X generated from CLKS input
1
t
ns
d(CKSH-CKRXH)
2
3
4
t
t
t
Cycle time, CLKR/X
CLKR/X int
CLKR/X int
CLKR int
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
FSX int
2P
ns
ns
ns
c(CKRX)
¶
¶
Pulse duration, CLKR/X high or CLKR/X low
Delay time, CLKR high to internal FSR valid
C – 1
C + 1
w(CKRX)
–4
–4
*3
4
5
d(CKRH-FRV)
9
t
t
t
t
Delay time, CLKX high to internal FSX valid
ns
ns
ns
ns
d(CKXH-FXV)
dis(CKXH-DXHZ)
d(CKXH-DXV)
d(FXH-DXV)
*16
*2
*–3
*2
Disable time, DX high impedance following last data bit from
CLKX high
12
13
14
*9
–2
3
4
Delay time, CLKX high to DX valid.
16
*4
*–2
*2
Delay time, FSX high to DX valid.
ONLY applies when in data delay 0 (XDATDLY = 00b) mode.
FSX ext
*10
†
CLKRP = CLKXP = FSRP = FSXP = 0 in the pin control register (PCR). If polarity of any of the signals is inverted, then the timing references
of that signal are also inverted.
‡
§
¶
Minimum delay times also represent minimum output hold times.
P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.
C = H or L
S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
=
sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
*This parameter is not tested.
50
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢅ ꢉ
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SGUS030B – APRIL 2000 – REVISED MAY 2001
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
CLKS
1
2
3
3
CLKR
4
4
FSR (int)
5
6
FSR (ext)
7
8
DR
Bit(n-1)
(n-2)
(n-3)
2
3
3
CLKX
9
FSX (int)
11
10
FSX (ext)
FSX (XDATDLY=00b)
13
(n-2)
14
13
12
DX
Bit 0
Bit(n-1)
(n-3)
Figure 31. McBSP Timings
51
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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SGUS030B – APRIL 2000 – REVISED MAY 2001
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for FSR when GSYNC = 1 (see Figure 32)
’C6701-14
’C6701-16
NO.
UNIT
MIN
*4
MAX
1
2
t
t
Setup time, FSR high before CLKS high
Hold time, FSR high after CLKS high
ns
ns
su(FRH-CKSH)
*4
h(CKSH-FRH)
*This parameter is not tested.
CLKS
1
2
FSR external
CLKR/X (no need to resync)
CLKR/X(needs resync)
Figure 32. FSR Timing When GSYNC = 1
52
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢅ ꢉ
ꢊ ꢋꢌ ꢍꢎ ꢏꢐꢑ ꢒꢓ ꢌꢏ ꢐꢎ ꢔꢏ ꢑꢏ ꢎꢍꢋ ꢀꢏ ꢑ ꢐꢍꢋ ꢓꢕ ꢌ ꢆꢖ ꢀ ꢀꢌ ꢕ
SGUS030B – APRIL 2000 – REVISED MAY 2001
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
†‡
timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0 (see Figure 33)
’C6701-14
’C6701-16
NO.
UNIT
MASTER
SLAVE
MIN MAX
MIN
12
4
MAX
4
5
t
t
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
2 – 3P
ns
ns
su(DRV-CKXL)
5 + 6P
h(CKXL-DRV)
†
‡
The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency
in ns. For example, when running parts at 167 MHz, use P = 6 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
†‡
switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0
(see Figure 33)
’C6701-14
’C6701-16
NO.
PARAMETER
UNIT
§
MASTER
SLAVE
MIN
MIN MAX
MAX
¶
1
2
3
t
t
t
Hold time, FSX low after CLKX low
T – 4 T + 4
L – 4 L + 4
ns
ns
ns
h(CKXL-FXL)
d(FXL-CKXH)
d(CKXH-DXV)
#
Delay time, FSX low to CLKX high
Delay time, CLKX high to DX valid
–4
4
3P + 1
5P + 17
Disable time, DX high impedance following last data bit from
CLKX low
6
t
*L – 2 *L + 3
ns
dis(CKXL-DXHZ)
Disable time, DX high impedance following last data bit from
FSX high
7
8
t
t
*P + 4 *3P + 17
2P + 1 4P + 13
ns
ns
dis(FXH-DXHZ)
Delay time, FSX low to DX valid
d(FXL-DXV)
*This parameter is not tested.
†
The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency
in ns. For example, when running parts at 167 MHz, use P = 6 ns.
‡
§
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
=
sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
¶
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
#
53
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢅꢉ
ꢊ ꢋ ꢌꢍꢎ ꢏ ꢐ ꢑꢒꢓꢌꢏ ꢐ ꢎ ꢔꢏ ꢑ ꢏ ꢎꢍꢋ ꢀ ꢏ ꢑꢐ ꢍꢋ ꢓ ꢕꢌ ꢆꢖꢀ ꢀꢌ ꢕ
SGUS030B – APRIL 2000 – REVISED MAY 2001
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
CLKX
FSX
1
2
8
7
6
3
DX
DR
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
4
5
Bit 0
(n-2)
(n-3)
(n-4)
Figure 33. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
†‡
timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0 (see Figure 34)
’C6701-14
’C6701-16
NO.
UNIT
MASTER
SLAVE
MIN MAX
MIN
12
4
MAX
4
5
t
t
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
2 – 3P
ns
ns
su(DRV-CKXH)
5 + 6P
h(CKXH-DRV)
†
‡
The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency
in ns. For example, when running parts at 167 MHz, use P = 6 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
54
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢅ ꢉ
ꢊ ꢋꢌ ꢍꢎ ꢏꢐꢑ ꢒꢓ ꢌꢏ ꢐꢎ ꢔꢏ ꢑꢏ ꢎꢍꢋ ꢀꢏ ꢑ ꢐꢍꢋ ꢓꢕ ꢌ ꢆꢖ ꢀ ꢀꢌ ꢕ
SGUS030B – APRIL 2000 – REVISED MAY 2001
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
†‡
switching characteristics for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0
(see Figure 34)
’C6701-14
’C6701-16
NO.
PARAMETER
UNIT
§
MASTER
SLAVE
MIN
MIN
MAX
MAX
¶
1
2
3
t
t
t
Hold time, FSX low after CLKX low
L – 4
L + 4
ns
ns
ns
h(CKXL-FXL)
d(FXL-CKXH)
d(CKXL-DXV)
#
Delay time, FSX low to CLKX high
Delay time, CLKX low to DX valid
T – 4
–4
T + 4
4
3P + 1
5P + 17
Disable time, DX high impedance following last data bit
from CLKX low
6
t
*–2
*4 *3P + 4 *5P + 17
*H + 3 2P + 1 4P + 13
ns
ns
dis(CKXL-DXHZ)
7
t
Delay time, FSX low to DX valid
*H – 2
d(FXL-DXV)
*This parameter is not tested.
†
The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency
in ns. For example, when running parts at 167 MHz, use P = 6 ns.
‡
§
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
=
sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
¶
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
#
CLKX
1
2
7
FSX
DX
6
3
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-3)
(n-4)
4
5
DR
Bit 0
(n-2)
(n-4)
Figure 34. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
55
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢅꢉ
ꢊ ꢋ ꢌꢍꢎ ꢏ ꢐ ꢑꢒꢓꢌꢏ ꢐ ꢎ ꢔꢏ ꢑ ꢏ ꢎꢍꢋ ꢀ ꢏ ꢑꢐ ꢍꢋ ꢓ ꢕꢌ ꢆꢖꢀ ꢀꢌ ꢕ
SGUS030B – APRIL 2000 – REVISED MAY 2001
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
†‡
timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1 (see Figure 35)
’C6701-14
’C6701-16
NO.
UNIT
MASTER
SLAVE
MIN MAX
MIN
12
4
MAX
4
5
t
t
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
2 – 3P
ns
ns
su(DRV-CKXH)
5 + 6P
h(CKXH-DRV)
†
‡
The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency
in ns. For example, when running parts at 167 MHz, use P = 6 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
†‡
switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1
(see Figure 35)
’C6701-14
’C6701-16
NO.
PARAMETER
UNIT
§
MASTER
SLAVE
MIN
MIN
MAX
MAX
¶
1
2
3
t
t
t
Hold time, FSX low after CLKX high
T – 4
H – 4
–4
T + 4
H + 4
4
ns
ns
ns
h(CKXH-FXL)
d(FXL-CKXL)
d(CKXL-DXV)
#
Delay time, FSX low to CLKX low
Delay time, CLKX low to DX valid
3P + 1
5P + 17
Disable time, DX high impedance following last data bit
from CLKX high
6
t
*H – 2
*H + 3
ns
dis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit
from FSX high
7
8
t
t
*P + 4 *3P + 17
2P + 1 4P + 13
ns
ns
dis(FXH-DXHZ)
Delay time, FSX low to DX valid
d(FXL-DXV)
*This parameter is not tested.
†
The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency
in ns. For example, when running parts at 167 MHz, use P = 6 ns.
‡
§
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
=
sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
¶
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
#
56
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢅ ꢉ
ꢊ ꢋꢌ ꢍꢎ ꢏꢐꢑ ꢒꢓ ꢌꢏ ꢐꢎ ꢔꢏ ꢑꢏ ꢎꢍꢋ ꢀꢏ ꢑ ꢐꢍꢋ ꢓꢕ ꢌ ꢆꢖ ꢀ ꢀꢌ ꢕ
SGUS030B – APRIL 2000 – REVISED MAY 2001
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
CLKX
FSX
1
2
7
6
8
3
DX
DR
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
4
5
Bit 0
(n-2)
(n-3)
(n-4)
Figure 35. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
†‡
timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1 (see Figure 36)
’C6701-14
’C6701-16
NO.
UNIT
MASTER
SLAVE
MIN MAX
MIN
12
4
MAX
4
5
t
t
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
2 – 3P
ns
ns
su(DRV-CKXL)
5 + 6P
h(CKXL-DRV)
†
‡
The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency
in ns. For example, when running parts at 167 MHz, use P = 6 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
57
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢅꢉ
ꢊ ꢋ ꢌꢍꢎ ꢏ ꢐ ꢑꢒꢓꢌꢏ ꢐ ꢎ ꢔꢏ ꢑ ꢏ ꢎꢍꢋ ꢀ ꢏ ꢑꢐ ꢍꢋ ꢓ ꢕꢌ ꢆꢖꢀ ꢀꢌ ꢕ
SGUS030B – APRIL 2000 – REVISED MAY 2001
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
†‡
switching characteristics for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1
(see Figure 36)
’C6701-14
’C6701-16
NO.
PARAMETER
UNIT
§
MASTER
SLAVE
MIN
MIN MAX
MAX
¶
1
2
3
t
t
t
Hold time, FSX low after CLKX high
H – 4 H + 4
T – 4 T + 4
ns
ns
ns
h(CKXH-FXL)
d(FXL-CKXL)
d(CKXH-DXV)
#
Delay time, FSX low to CLKX low
Delay time, CLKX high to DX valid
–4
4
3P + 1
*4 *3P + 4 *5P + 17
*L – 2 *L + 3 2P + 1 4P + 13
5P + 17
Disable time, DX high impedance following last data bit from
CLKX high
6
t
*–2
ns
ns
dis(CKXH-DXHZ)
7
t
Delay time, FSX low to DX valid
d(FXL-DXV)
*This parameter is not tested.
†
The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency
in ns. For example, when running parts at 167 MHz, use P = 6 ns.
‡
§
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
=
sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
¶
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
#
CLKX
1
2
FSX
DX
7
6
3
Bit 0
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
4
5
DR
(n-2)
(n-3)
(n-4)
Figure 36. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
58
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢅ ꢉ
ꢊ ꢋꢌ ꢍꢎ ꢏꢐꢑ ꢒꢓ ꢌꢏ ꢐꢎ ꢔꢏ ꢑꢏ ꢎꢍꢋ ꢀꢏ ꢑ ꢐꢍꢋ ꢓꢕ ꢌ ꢆꢖ ꢀ ꢀꢌ ꢕ
SGUS030B – APRIL 2000 – REVISED MAY 2001
DMAC, TIMER, POWER-DOWN TIMING
switching characteristics for DMAC outputs (see Figure 37)
’C6701-14
’C6701-16
NO.
PARAMETER
UNIT
MIN
MAX
1
t
Delay time, CLKOUT1 high to DMAC valid
2
11
ns
d(CKO1H-DMACV)
CLKOUT1
DMAC[0:3]
1
1
Figure 37. DMAC Timing
†
timing requirements for timer inputs (see Figure 38)
’C6701-14
’C6701-16
NO.
UNIT
MIN
MAX
1
t
Pulse duration, TINP high
2P
ns
w(TINPH)
†
P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.
switching characteristics for timer outputs (see Figure 38)
’C6701-14
’C6701-16
NO.
PARAMETER
UNIT
MIN
MAX
10
2
t
Delay time, CLKOUT1 high to TOUT valid
1
ns
d(CKO1H-TOUTV)
CLKOUT1
TINP
1
2
2
TOUT
Figure 38. Timer Timing
switching characteristics for power-down outputs (see Figure 39)
’C6701-14
’C6701-16
NO.
PARAMETER
UNIT
MIN
MAX
1
t
Delay time, CLKOUT1 high to PD valid
1
9
ns
d(CKO1H-PDV)
CLKOUT1
PD
1
1
Figure 39. Power-Down Timing
59
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢅꢉ
ꢊ ꢋ ꢌꢍꢎ ꢏ ꢐ ꢑꢒꢓꢌꢏ ꢐ ꢎ ꢔꢏ ꢑ ꢏ ꢎꢍꢋ ꢀ ꢏ ꢑꢐ ꢍꢋ ꢓ ꢕꢌ ꢆꢖꢀ ꢀꢌ ꢕ
SGUS030B – APRIL 2000 – REVISED MAY 2001
JTAG TEST-PORT TIMING
timing requirements for JTAG test port (see Figure 40)
’C6701-14
’C6701-16
NO.
UNIT
MIN
35
10
9
MAX
1
3
4
t
t
t
Cycle time, TCK
ns
ns
ns
c(TCK)
Setup time, TDI/TMS/TRST valid before TCK high
Hold time, TDI/TMS/TRST valid after TCK high
su(TDIV-TCKH)
h(TCKH-TDIV)
switching characteristics for JTAG test port (see Figure 40)
’C6701-14
’C6701-16
NO.
PARAMETER
UNIT
MIN
MAX
*15
2
t
Delay time, TCK low to TDO valid
*–3
ns
d(TCKL-TDOV)
*This parameter is not tested.
1
TCK
TDO
2
2
4
3
TDI/TMS/TRST
Figure 40. JTAG Test-Port Timing
60
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢅ ꢉ
ꢀ
ꢊ
ꢋꢌ
ꢍꢎ
ꢏ
ꢐ
ꢑ
ꢒ
ꢓ
ꢌ
ꢏ
ꢐ
ꢎ
ꢔ
ꢏ
ꢑꢏ
ꢎ
ꢍ
ꢋ
ꢀ
ꢏ
ꢑ
ꢐ
ꢍ
ꢋ
ꢓ
ꢕ
ꢌ
ꢆ
ꢖ
ꢀ
ꢌ
ꢕ
SGUS030B – APRIL 2000 – REVISED MAY 2001
MECHANICAL DATA
GLP (S-CBGA-N429)
CERAMIC BALL GRID ARRAY
27,20
26,80
SQ
25,40 TYP
1,27
AA
Y
W
V
U
T
R
P
N
M
L
1,27
K
J
H
G
F
E
D
C
B
A
1
3
5
7
9
11 13 15 17 19 21
10 12 14 16 18 20
2
4
6
8
1,22
1,00
3,30 MAX
Seating Plane
0,15
0,90
0,60
M
0,10
0,70
0,50
4164732/A 08/98
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-156
D. Flip chip application only
thermal resistance characteristics (S-CBGA package)
NO
°C/W
3.0
Air Flow
N/A
1
2
3
4
5
6
RΘ
RΘ
RΘ
Junction-to-Case, measured to the bottom of solder ball
Junction-to-Case, measured to the top of the package lid
Junction-to-Ambient
JC
JC
JA
7.3
N/A
14.5
11.8
11.1
10.2
0
150 fpm
250 fpm
500 fpm
RΘ
RΘ
Junction-to-Moving-Air
JMA
JB
Junction-to-Board, measured by soldering a thermocouple to one of the middle
traces on the board at the edge of the package
7
6.2
N/A
61
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
PACKAGE OPTION ADDENDUM
www.ti.com
14-Aug-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
5962-9866101QXA
5962-9866101VXA
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FC/CSP
FC/CSP
FC/CSP
FC/CSP
FC/CSP
FC/CSP
GLP
429
429
429
429
429
429
1
1
1
1
1
1
TBD
TBD
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
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GLP
5962-9866102VXA
GLP
SM320C6701GLPS16
SM320C6701GLPW14
SMJ320C6701GLPW14
GLP
GLP
GLP
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MCBG004A – SEPTEMBER 1998 – REVISED JANUARY 2002
GLP (S-CBGA-N429)
CERAMIC BALL GRID ARRAY
27,20
26,80
SQ
25,40 TYP
1,27
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
3
5
7
9
11 13 15 17 19 21
10 12 14 16 18 20
A1 Corner
2
4
6
8
Bottom View
1,22
1,00
3,30 MAX
Seating Plane
0,15
0,90
0,60
M
0,10
0,70
0,50
4164732/B 11/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-156
D. Flip chip application only
1
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