SM320C6713BPYP300_技术文档

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

D

Highest-Performance Floating-Point Digital

Signal Processor (DSP): TMS320C6713B

− Eight 32-Bit Instructions/Cycle

D

16-Bit Host-Port Interface (HPI)

D

Two McASPs

− Two Independent Clock Zones Each

(1 TX and 1 RX)

− 32/64-Bit Data Word

− 300-, 225-, 200-MHz (GDP and ZDP), and

225-, 200-, 167-MHz (PYP) Clock Rates

− 3.3-, 4.4-, 5-, 6-Instruction Cycle Times

− 2400/1800, 1800/1350, 1600/1200, and

1336/1000 MIPS/MFLOPS

− Rich Peripheral Set, Optimized for Audio

− Highly Optimized C/C++ Compiler

− Extended Temperature Devices Available

− Eight Serial Data Pins Per Port:

Individually Assignable to any of the

Clock Zones

− Each Clock Zone Includes:

− Programmable Clock Generator

− Programmable Frame Sync Generator

− TDM Streams From 2-32 Time Slots

− Support for Slot Size:

8, 12, 16, 20, 24, 28, 32 Bits

− Data Formatter for Bit Manipulation

− Wide Variety of I2S and Similar Bit

Stream Formats

Advanced Very Long Instruction Word

(VLIW) TMS320C67x DSP Core

− Eight Independent Functional Units:

− 2 ALUs (Fixed-Point)

− 4 ALUs (Floating-/Fixed-Point)

− 2 Multipliers (Floating-/Fixed-Point)

− Load-Store Architecture With 32 32-Bit

General-Purpose Registers

− Integrated Digital Audio Interface

Transmitter (DIT) Supports:

− S/PDIF, IEC60958-1, AES-3, CP-430

Formats

− Instruction Packing Reduces Code Size

− All Instructions Conditional

− Up to 16 transmit pins

− Enhanced Channel Status/User Data

− Extensive Error Checking and Recovery

D

Instruction Set Features

2

− Native Instructions for IEEE 754

− Single- and Double-Precision

− Byte-Addressable (8-, 16-, 32-Bit Data)

− 8-Bit Overflow Protection

− Saturation; Bit-Field Extract, Set, Clear;

Bit-Counting; Normalization

D

Two Inter-Integrated Circuit Bus (I C Bus)

Multi-Master and Slave Interfaces

Two Multichannel Buffered Serial Ports:

− Serial-Peripheral-Interface (SPI)

− High-Speed TDM Interface

− AC97 Interface

L1/L2 Memory Architecture

− 4K-Byte L1P Program Cache

(Direct-Mapped)

− 4K-Byte L1D Data Cache (2-Way)

− 256K-Byte L2 Memory Total: 64K-Byte

L2 Unified Cache/Mapped RAM, and

192K-Byte Additional L2 Mapped RAM

D

Two 32-Bit General-Purpose Timers

Dedicated GPIO Module With 16 pins

(External Interrupt Capable)

Flexible Phase-Locked-Loop (PLL) Based

Clock Generator Module

†

IEEE-1149.1 (JTAG )

Boundary-Scan-Compatible

D

Device Configuration

− Boot Mode: HPI, 8-, 16-, 32-Bit ROM Boot

− Endianness: Little Endian, Big Endian

208-Pin PowerPAD PQFP (PYP)

272-BGA Packages (GDP and ZDP)

32-Bit External Memory Interface (EMIF)

− Glueless Interface to SRAM, EPROM,

Flash, SBSRAM, and SDRAM

− 512M-Byte Total Addressable External

Memory Space

0.13-µm/6-Level Copper Metal Process

− CMOS Technology

‡

D

3.3-V I/Os, 1.2 -V Internal (GDP/ZDP/ PYP)

D

3.3-V I/Os, 1.4-V Internal (GDP/ZDP) [300

MHz]

D

Enhanced Direct-Memory-Access (EDMA)

Controller (16 Independent Channels)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TMS320C67x and PowerPAD are trademarks of Texas Instruments.

2

I C Bus is a trademark of Philips Electronics N.V. Corporation

All trademarks are the property of their respective owners.

†

‡

IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

These values are compatible with existing 1.26-V designs.

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Copyright  2006, Texas Instruments Incorporated

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ꢟ ꢣ ꢠ ꢟꢘ ꢙꢭ ꢛꢚ ꢞ ꢦꢦ ꢤꢞ ꢜ ꢞ ꢝ ꢣ ꢟ ꢣ ꢜ ꢠ ꢨ

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1

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

Table of Contents

EMIF device speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

EMIF big endian mode correctness . . . . . . . . . . . . . . . . 97

bootmode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

GDP and ZDP 272-Ball BGA package (bottom view) . . . . . 5

PYP PowerPAD QFP package (top view) . . . . . . . . . . . . 10

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

functional block and CPU (DSP core) diagram . . . . . . . . . . 13

CPU (DSP core) description . . . . . . . . . . . . . . . . . . . . . . . . . 14

memory map summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

peripheral register descriptions . . . . . . . . . . . . . . . . . . . . . . . 18

signal groups description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

device configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

configuration examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

debugging considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

terminal functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

device support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

CPU CSR register description . . . . . . . . . . . . . . . . . . . . . . . . 68

cache configuration (CCFG) register description . . . . . . . . 70

interrupts and interrupt selector . . . . . . . . . . . . . . . . . . . . . . . 71

external interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

EDMA module and EDMA selector . . . . . . . . . . . . . . . . . . . . 74

PLL and PLL controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

multichannel audio serial port (McASP) peripherals . . . . . 84

I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

general-purpose input/output (GPIO) . . . . . . . . . . . . . . . . . . 90

absolute maximum ratings over operating case

temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . 99

recommended operating conditions . . . . . . . . . . . . . . . . 99

electrical characteristics over recommended ranges of

supply voltage and operating case temperature 100

parameter measurement information . . . . . . . . . . . . . . 101

signal transition levels . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

timing parameters and board routing analysis . . . . . . 103

input and output clocks . . . . . . . . . . . . . . . . . . . . . . . . . . 105

asynchronous memory timing . . . . . . . . . . . . . . . . . . . . 108

synchronous-burst memory timing . . . . . . . . . . . . . . . . . 111

synchronous DRAM timing . . . . . . . . . . . . . . . . . . . . . . . 113

HOLD/HOLDA timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

BUSREQ timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . 123

multichannel audio serial port (McASP) timing . . . . . . 124

inter-integrated circuits (I2C) timing . . . . . . . . . . . . . . . 127

host-port interface timing . . . . . . . . . . . . . . . . . . . . . . . . 129

multichannel buffered serial port timing . . . . . . . . . . . . 132

timer timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

general-purpose input/output (GPIO) port timing . . . . 143

JTAG test-port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

power-down mode logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

power-supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

IEEE 1149.1 JTAG compatibility statement . . . . . . . . . . . . . 95

power-supply decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

2

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

REVISION HISTORY

The TMS320C6713B device-specific documentation has been split from TMS320C6713, TMS320C6713B Float-

ing−Point Digital Signal Processors, literature number SPRS186K, into a separate Data Sheet, literature number

SPRS294. It also highlights technical changes made to SPRS294 to generate SPRS294A. These changes are

marked by “[Revision A].” Additionally, made changes to SPRS294A to generate SPRS294B. These changes

are marked by “[Revision B].” Both Revision A and B changes are noted in the Revision History table below.

Scope: Updated information on McASP, McBSP and JTAG for clarification. Changed Pin Description for A12 and

B11 (Revisions SPRS294 and SPRS294A). Updated Nomenclature figure by adding device−specific information

for the ZDP package. TI Recommends for new designs that the following pins be configured as such:

D

Pin A12 connected directly to CV

(core power)

DD

Pin B11 connected directly to V (ground)

ss

PAGE(S)

NO.

ADDITIONS/CHANGES/DELETIONS

6

Terminal Assignments for the 272-Ball GDP and ZDP Packages (in Order of Ball No.) table:

Updated Signal Name for Ball No. A12

Updated Signal Name for Ball No. B11

10

32

33

37

46

47

49

50

55

57

PYP PowerPAD QFP package (top view):

Updated drawing

Device Configurations, device configurations at device reset section:

Updated “For proper device operation...” paragraph [Revision B]

Device Configurations, Device Configurations Pins at Device Reset (HD[4:3], HD8, HD12, and CLKMODE0) section:

Removed “CE1 width 32−bit” from Functional Description for “00” in HD[4:3](BOOTMODE) Configuration Pin

Device Configurations, Device Configurations Pins at Device Reset (HD[4:3], HD8, HD12, and CLKMODE0) section:

Updated “All other HD pins...” footnote [Revision B]

Table 22 Peripheral Pin Selection Matrix:

Updated/changed MCBSP0DIS (DEVCFG bit) from “ACLKKO” to “ACLKXO”

Configuration Example F (1 McBSP + HPI + 1 McASP) figure:

Updated from McBSP1DIS = 1 to McBSP1DIS = 0

Device Configurations, debugging considerations section:

Updated “Internal pullup/pulldown resistors...” paragraph [Revision B]

Terminal Functions, Resets and Interrupts section:

Updated IPU/IPD for RESET Signal Name from “IPU” to “−−”

Terminal Functions table, Host Port Interface section:

Removed “CE1 width 32−bit” from Description for “00” in Bootmode HD[4:3]

Terminal Functions table, Host Port Interface section:

Updated “Other HD pins...” paragraph [Revision B]

Terminal Functions, Timer 1 section:

Updated Description for TINP1/AHCLKX0 Signal Name

Terminal Functions, Reserved for Test section:

Updated Description for RSV Signal Name, 181 PYP, A12 GDP/ZDP

Updated Description for RSV Signal Name, 180 PYP, B11 GDP/ZDP

3

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

PAGE(S)

NO.

ADDITIONS/CHANGES/DELETIONS

57

Terminal Functions, Reserved for Test section:

Updated/changed Description for RSV Signal Name, A12 GDP (to “recommended”) − [Revision A]

Updated/changed Description for RSV Signal Name, B11 GDP (to “recommended”) − [Revision A]

57

Terminal Functions, Reserved for Test section:

Updated/changed Description for RSV Signal Name D12 to include PYP 178 as follows:

“...the D12/178 pin must be externally pulled down with a 10−kΩ resistor.” [Revision B]

66

67

92

93

Device Support, device and development-support tool nomenclature section:

Updated figure for clarity

Device Support, document support section:

Updated paragraphs for clarity

Power−Down Mode Logic − Triggering, Wake−up and Effects section:

Updated paragraphs [Revision B]

Power−Down Mode Logic − Triggering, Wake−up and Effects section, Characteristics of the Power-Down Modes table:

Added “It is recommended to use the PLLPWDN bit (PLLCSR.1) as an alternative to PD3” to PRWD Field (BITS 15−10) −

011100 − Effect on Chip’s Operation [Revision B]

93

95

96

Power−Down Mode Logic − Triggering, Wake−up and Effects section, Characteristics of the Power-Down Modes table:

Deleted three paragraphs following table [Revision B]

IEEE 1149.1 JTAG Compatibility Statement section:

Updated/added paragraphs for clarity

EMIF Device Speed section, Example Boards and Maximum EMIF Speed table:

Type − 3−Loads Short Traces, EMIF Interface Components section:

Updated from “32−Bit SDRAMs” to “16−Bit SDRAMs” [Revision B]

95

99

IEEE 1149.1 JTAG Compatibility Statement section:

Updated/added paragraphs for clarity

Recommended Operating Conditions:

Added V

Maximum voltage during overshoot row and associated footnote

Maximum voltage during undershoot row and associated footnote

OS,

US,

102

124

Parameter Measurement Information, AC transient rise/fall time specifications section:

Added AC Transient Specification Rise Time figure

Added AC Transient Specification Fall Time figure

MULTICHANNEL AUDIO SERIAL PORT (McASP) TIMING:

timing requirements for McASP section:

Updated Parameter No. 3, t

from “33” to “greater of 2P or 33 ns” and added associated footnote

c(ACKRX),

MULTICHANNEL AUDIO SERIAL PORT (McASP) TIMING:

switching characteristics over recommended operating conditions for McASP section:

Updated Parameter No. 11, t

from “33” to “greater of 2P or 33 ns” and added associated footnote

c(ACKRX),

125, 126 MULTICHANNEL AUDIO SERIAL PORT (McASP) TIMING section:

Updated McASP Input and Output drawings

134

MULTICHANNEL BUFFERED SERIAL PORT TIMING section:

switching characteristics over recommended operating conditions for McBSP section:

Updated McBSP Timings figure

147

Mechanical Data section:

Added statement to the Packaging Information section

4

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

GDP and ZDP 272-Ball BGA package (bottom view)

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ꢖ ꢔ ꢈ

ꢖ ꢔ ꢰ

ꢖ ꢔ ꢺ

ꢖ ꢔ ꢱ

ꢆ ꢌ ꢯ ꢕ ꢉ ꢹ

ꢎ ꢶ ꢕ ꢅ ꢳ ꢇ ꢴ

ꢔ ꢕ ꢉ ꢹ

ꢂ ꢔ ꢎ ꢉ

ꢋ ꢂ ꢕ ꢉ ꢹ

ꢎ ꢶ ꢕ ꢅ ꢳ ꢈ ꢴ

ꢮ

ꢂꢂ

ꢮ

ꢂꢂ

ꢮ

ꢂꢂ

ꢮ

ꢂꢂ

ꢮ

ꢂꢂ

ꢮ

ꢂꢂ

ꢮ

ꢂꢂ

ꢮ

ꢂꢂ

ꢮ

ꢂꢂ

ꢔ ꢮ

ꢔ ꢔ

ꢔ ꢶ ꢉ ꢹ

ꢎ ꢶ ꢕ ꢅ ꢳ ꢱ ꢴ

ꢆ ꢌ ꢯ ꢶ ꢉ ꢹ

ꢎ ꢁ ꢗ ꢀ ꢖ ꢅ

ꢮ

ꢂ

ꢋ

ꢂ

ꢶ

ꢉ

ꢆ ꢮ

ꢖ ꢔ ꢄ

ꢖ ꢔ ꢅ

ꢖ ꢔ ꢃ

ꢖ ꢔ ꢉ

ꢆ ꢮ

ꢮ

ꢔ

ꢆ ꢌ ꢯ ꢂ ꢅ ꢹ

ꢎ ꢻ ꢆ ꢌ ꢯ ꢕ ꢅ

ꢆ ꢮ

ꢔ ꢔ

ꢮ

ꢂꢂ

ꢯ

ꢾ

ꢂꢂ

ꢔ

ꢂ

ꢔ ꢕ ꢅ ꢹ

ꢎ ꢶ ꢕ ꢅ ꢳ ꢅ ꢴ

ꢋ ꢂ ꢕ ꢅ ꢹ

ꢎ ꢋ ꢂ ꢕ ꢅ

ꢊ ꢗ ꢂ

ꢕ ꢖ ꢿ

ꢻ ꢏ ꢐ ꢀꢹ

ꢑ ꢓ ꢳ ꢉ ꢴ

ꢔ ꢮ

ꢔ ꢔ

ꢮ

ꢂꢂ

ꢻ

ꢍ

ꢌ

ꢔ

ꢻ

ꢍ

ꢌ

ꢔ

ꢎ

ꢔ ꢶ ꢅ ꢹ

ꢎ ꢶ ꢕ ꢅ ꢳ ꢉ ꢴ

ꢻ ꢕ ꢔ ꢼꢹ

ꢎ ꢆ ꢌ ꢯ ꢕ ꢉ

ꢻ ꢻ ꢽ ꢏ ꢌ ꢹ

ꢎ ꢋ ꢂ ꢕ ꢉ

ꢋ ꢂ ꢶ ꢅ ꢹ

ꢎ ꢋ ꢂ ꢶ ꢅ

ꢆ ꢌ ꢯ ꢕ ꢅ ꢹ

ꢎ ꢆ ꢌ ꢯ ꢕ ꢅ

ꢻ

ꢑ

ꢋ

ꢮ

ꢔ ꢮ

ꢔ ꢔ

ꢂ

ꢀꢍ ꢗ ꢀ ꢅ ꢹ

ꢎ ꢶ ꢕ ꢅ ꢳ ꢄ ꢴ

ꢀ ꢏ ꢐ ꢓ ꢅ ꢹ

ꢎ ꢶ ꢕ ꢅ ꢳ ꢃ ꢴ

ꢆ ꢌ ꢯ ꢶ ꢅ ꢹ

ꢎ ꢆ ꢌ ꢯ ꢶ ꢅ

ꢮ

ꢂꢂ

ꢻ ꢆ ꢐ ꢀ ꢌ ꢅ ꢹ ꢻ ꢆ ꢐ ꢀ ꢌ ꢉ ꢹ

ꢎ ꢶ ꢕ ꢉ ꢳ ꢉ ꢴ

ꢻ ꢕ ꢹ ꢽꢹ

ꢎ ꢶ ꢕ ꢉ ꢳ ꢅ ꢴ

ꢂ

ꢎ

ꢶ

ꢕ

ꢉ

ꢳ

ꢃ

ꢴ

ꢀꢍ ꢗ ꢀ ꢉ ꢹ

ꢎ ꢶ ꢕ ꢅ ꢳ ꢰ ꢴ

ꢀ ꢏ ꢐ ꢓ ꢉ ꢹ

ꢎ ꢻ ꢆ ꢌ ꢯ ꢶ ꢅ

ꢻ ꢔ ꢂ ꢄꢹ

ꢎ ꢶ ꢕ ꢉ ꢳ ꢱ ꢴ

ꢻ ꢆ ꢂꢹ

ꢎ ꢶ ꢕ ꢉ ꢳ ꢄ ꢴ

ꢔ ꢮ

ꢔ ꢔ

ꢆ ꢮ

ꢮ

ꢆ ꢮ

ꢔ ꢔ

ꢮ

ꢂꢂ

ꢔ

ꢻ ꢎ ꢂꢹ

ꢎ ꢆ ꢌ ꢯ ꢶ ꢉ

ꢻ ꢔ ꢂ ꢉꢹ

ꢎ ꢶ ꢕ ꢉ ꢳ ꢇ ꢴ

ꢻ ꢔ ꢅ ꢹ

ꢎ ꢶ ꢕ ꢉ ꢳ ꢰ ꢴ

ꢆ ꢌ ꢯ ꢂ ꢉ ꢹ

ꢂ ꢆ ꢌ ꢉ

ꢑ ꢓ ꢳ ꢈ ꢴ

ꢵ ꢖ ꢶ ꢀ ꢷ ꢏ ꢐ ꢀ ꢈ ꢸ

ꢮ

ꢂꢂ

ꢮ

ꢂꢂ

ꢖ

ꢔ

ꢆ

ꢊ

ꢎ

ꢂ

ꢑ ꢓ ꢳ ꢇ ꢴ

ꢵ ꢖ ꢶ ꢀ ꢷ ꢏ ꢐ ꢀ ꢇ ꢸ

ꢻ ꢔ ꢄ ꢹ

ꢎ ꢋ ꢂ ꢶ ꢉ

ꢻ ꢔ ꢉ ꢹ

ꢎ ꢶ ꢕ ꢉ ꢳ ꢈ ꢴ

ꢔ ꢮ

ꢔ ꢔ

ꢖ

ꢁ

ꢗ

ꢄ

ꢮ

ꢂꢂ

ꢆ ꢮ

ꢔ ꢔ

ꢆ ꢮ

ꢮ

ꢕ

ꢂ

ꢮ

ꢖ

ꢁ

ꢗ

ꢅ

ꢆ

ꢌ

ꢯ

ꢍ

ꢗ

ꢀ

ꢃ

ꢆ ꢮ

ꢔ ꢔ

ꢕ

ꢂ

ꢮ

ꢂꢂ

ꢆ ꢮ

ꢔ ꢔ

ꢆ ꢮ

ꢔ ꢔ

ꢔ ꢮ

ꢔ ꢔ

ꢮ

ꢂꢂ

ꢔ ꢮ

ꢔ ꢔ

ꢔ

ꢂ

ꢑ

ꢓ

ꢳ

ꢱ

ꢴ

ꢑ ꢓ ꢳ ꢰ ꢴ ꢹ

ꢵ ꢖ ꢶ ꢀ ꢷ ꢏ ꢐ ꢀ ꢱ ꢸ ꢹ ꢵ ꢖ ꢶ ꢀ ꢷ ꢏ ꢐ ꢀ ꢰ ꢸ ꢹ

ꢎ ꢁ ꢗ ꢀ ꢖ ꢏ ꢐ ꢅ ꢎ ꢁ ꢗ ꢀ ꢖ ꢏ ꢐ ꢉ

ꢆ

ꢌ

ꢯ

ꢻ ꢔ ꢉ ꢰ ꢹ

ꢑ ꢓ ꢳ ꢉ ꢰ ꢴ

ꢻ ꢔ ꢉ ꢄ ꢹ

ꢑ ꢓ ꢳ ꢉ ꢄ ꢴ

ꢻ ꢔ ꢲ ꢹ

ꢑ ꢓ ꢳ ꢲ ꢴ

ꢻ ꢔ ꢇ ꢹ

ꢎ ꢻ ꢆ ꢌ ꢯ ꢕ ꢉ

ꢻ ꢔ ꢰ ꢹ

ꢑ ꢓ ꢳ ꢅ ꢴ

ꢻ ꢔ ꢃ ꢹ

ꢎ ꢁ ꢗ ꢀ ꢖ ꢉ

ꢆ ꢮ

ꢔ ꢔ

ꢓ ꢌ ꢌ ꢻ ꢮ

ꢕ ꢂ ꢮ

ꢆ ꢮ

ꢔ ꢔ

ꢮ

ꢂꢂ

ꢔ ꢮ

ꢔ ꢔ

ꢖ ꢁ ꢗ ꢰ

ꢕ ꢂ ꢮ

ꢕ

ꢂ

ꢮ

ꢐ

ꢁ

ꢏ

ꢆ ꢮ

ꢔ ꢔ

ꢂ

ꢁ

ꢍ

ꢔ

ꢖ

ꢅ

ꢻ ꢔ ꢉ ꢅ ꢹ

ꢑ ꢓ ꢳ ꢉ ꢅ ꢴ

ꢻ ꢔ ꢺ ꢹ

ꢑ ꢓ ꢳ ꢺ ꢴ

ꢻ ꢔ ꢱ ꢹ

ꢎ ꢻ ꢆ ꢌ ꢯ ꢶ ꢉ

ꢻ ꢔ ꢉ ꢱ ꢹ

ꢑ ꢓ ꢳ ꢉ ꢱ ꢴ

ꢮ

ꢂꢂ

ꢮ

ꢆ ꢮ

ꢔ ꢔ

ꢔ ꢮ

ꢔ ꢔ

ꢀ

ꢕ

ꢂ

ꢀ

ꢁ

ꢂ

ꢔ ꢮ

ꢔ ꢔ

ꢖ

ꢁ

ꢗ

ꢱ

ꢮ

ꢂꢂ

ꢆ ꢮ

ꢔ ꢔ

ꢮ

ꢂ ꢂ

ꢖ

ꢁ

ꢗ

ꢉ

ꢔ ꢮ

ꢔ ꢔ

ꢂꢂ

ꢖ

ꢁ

ꢗ

ꢃ

ꢻ ꢔ ꢉ ꢃ ꢹ

ꢑ ꢓ ꢳ ꢉ ꢃ ꢴ

ꢻ ꢔ ꢉꢉ ꢹ

ꢑ ꢓ ꢳ ꢉꢉ ꢴ

ꢻ ꢔ ꢈ ꢹ

ꢑ ꢓ ꢳ ꢃ ꢴ

ꢆ ꢌ ꢯ ꢏ ꢐ

ꢃ

ꢆ ꢮ

ꢔ ꢔ

ꢮ

ꢂꢂ

ꢕ ꢂ ꢮ

ꢱ

ꢀ ꢆ ꢯ

ꢇ

ꢮ

ꢂꢂ

ꢮ

ꢂ ꢂ

ꢀ ꢔ ꢏ

ꢈ

ꢀ ꢔ ꢍ

ꢺ

ꢆ ꢮ

ꢲ

ꢆ ꢮ

ꢔ ꢔ

ꢮ

ꢂꢂ

ꢕ ꢂ ꢮ

ꢉ ꢄ

ꢕ ꢖ ꢂ ꢖ ꢀ

ꢉ ꢃ

ꢮ

ꢂꢂ

ꢔ ꢮ

ꢔ ꢔ

ꢔ

ꢉ

ꢄ

ꢰ

ꢉ

ꢅ

ꢉ

ꢰ

ꢉ

ꢱ

ꢉ

ꢇ

ꢉ

ꢈ

ꢉ

ꢺ

ꢉ

ꢲ

ꢄ

ꢅ

ꢀ

ꢁ

ꢂ

ꢃ

ꢄ

ꢅ

ꢆ

ꢃ

ꢇ

ꢅ

ꢈ

ꢉ

ꢇ

ꢊ

ꢉ

ꢁ

ꢇ

ꢋ

ꢌ

ꢍ

ꢎ

ꢂ

ꢏ

ꢐ

ꢂ

ꢆ

ꢇ

ꢎ

ꢄ

ꢅ

ꢑ

ꢒ

ꢅ

ꢏ

ꢉ

ꢄ

ꢈ

ꢅ

ꢊ

ꢉ

ꢁ

ꢂ

ꢉ

ꢃ

ꢓ

ꢈ

ꢎ

ꢈ

ꢒ

ꢉ

ꢈ

ꢅ

ꢉ

ꢁ

ꢇ

ꢍ

ꢔ

ꢍ

ꢎ

ꢂ

ꢏ

ꢐ

ꢂ

ꢆ

ꢇ

ꢕ

5

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢃꢊ

ꢋ ꢌ ꢍꢎꢀ ꢏ ꢐ ꢑꢒꢓꢍꢏ ꢐ ꢀ ꢔꢏ ꢑ ꢏ ꢀꢎꢌ ꢂ ꢏ ꢑꢐ ꢎꢌ ꢓ ꢕꢍ ꢆꢖꢂ ꢂꢍ ꢕ

SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

Table 1. Terminal Assignments for the 272-Ball GDP and ZDP Packages (in Order of Ball No.)

BALL NO.

A1

SIGNAL NAME

BALL NO.

C1

SIGNAL NAME

V

GP[5](EXT_INT5)/AMUTEIN0

GP[4](EXT_INT4)/AMUTEIN1

SS

A2

C2

SS

A3

CLKIN

CV

C3

CV

DD

A4

C4

CLKMODE0

PLLHV

DD

A5

RSV

TCK

TDI

C5

A6

C6

V

SS

CV

A7

C7

DD

A8

TDO

C8

V

SS

A9

CV

C9

DD

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

B1

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

D1

DV

DD

V

SS

EMU4

RSV [connect directly to CV

RESET

]

RSV

DD

NMI

V

SS

HD14/GP[14]

HD12/GP[12]

HD9/GP[9]

HD6/AHCLKR1

HD13/GP[13]

HD11/GP[11]

DV

DD

HD7/GP[3]

CV

DD

V

SS

V

SS

V

SS

HD4/GP[0]

HD3/AMUTE1

DV

DD

B2

CV

DV

D2

GP[6](EXT_INT6)

EMU2

DD

B3

D3

B4

V

SS

D4

V

SS

B5

RSV

TRST

TMS

D5

CV

DD

B6

D6

B7

D7

RSV

B8

DV

D8

V

SS

DD

B9

EMU1

D9

EMU0

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

EMU3

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

CLKOUT3

RSV [connect directly to V

EMU5

]

CV

DD

RSV

SS

DV

V

SS

DD

HD15/GP[15]

CV

DV

DD

V

SS

HD10/GP[10]

HD8/GP[8]

V

SS

HD2/AFSX1

DV

HD5/AHCLKX1

CV

DD

HD1/AXR1[7]

V

SS

Shading denotes the GDP and ZDP package pin functions that drop out on the PYP package.

6

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢈ ꢉꢃ ꢊ

ꢋ ꢌꢍ ꢎꢀ ꢏꢐꢑ ꢒꢓ ꢍꢏ ꢐꢀ ꢔꢏ ꢑꢏ ꢀꢎꢌ ꢂꢏ ꢑ ꢐꢎꢌ ꢓꢕ ꢍ ꢆꢖ ꢂ ꢂꢍ ꢕ

SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

Table 1. Terminal Assignments for the 272-Ball GDP and ZDP Package (in Order of Ball No.) (Continued)

BALL NO.

E1

SIGNAL NAME

CLKS1/SCL1

BALL NO.

J17

J18

J19

J20

K1

SIGNAL NAME

HOLD

E2

V

HOLDA

SS

GP[7](EXT_INT7)

E3

BUSREQ

E4

V

HINT/GP[1]

SS

E17

E18

E19

E20

F1

CV

DD

SS

HAS/ACLKX1

HDS1/AXR1[6]

HD0/AXR1[4]

K2

V

SS

CLKS0/AHCLKR0

CV

K3

K4

DD

TOUT1/AXR0[4]

TINP1/AHCLKX0

K9

V

SS

F2

K10

K11

K12

K17

K18

K19

K20

L1

SS

F3

DV

CV

DD

F4

F17

F18

F19

F20

G1

CV

DD

HDS2/AXR1[5]

ED0

ED1

V

SS

HCS/AXR1[2]

V

SS

TOUT0/AXR0[2]

TINP0/AXR0[3]

CLKX0/ACLKX0

FSX1

G2

L2

DX1/AXR0[5]

CLKX1/AMUTE0

G3

L3

G4

V

L4

CV

DD

SS

G17

G18

G19

G20

H1

L9

V

SS

HCNTL0/AXR1[3]

HCNTL1/AXR1[1]

HR/W/AXR1[0]

FSX0/AFSX0

L10

L11

L12

L17

L18

L19

L20

M1

SS

CV

DD

H2

DX0/AXR0[1]

ED2

ED3

H3

CLKR0/ACLKR0

H4

V

CV

DD

SS

H17

H18

H19

H20

J1

CLKR1/AXR0[6]

DR1/SDA1

SS

DV

M2

DD

HRDY/ACLKR1

HHWIL/AFSR1

DR0/AXR0[0]

M3

FSR1/AXR0[7]

M4

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

M9

J2

DV

M10

M11

M12

M17

M18

M19

M20

DD

FSR0/AFSR0

J3

J4

V

SS

V

SS

V

SS

V

SS

V

SS

J9

J10

J11

J12

DV

DD

ED4

ED5

Shading denotes the GDP and ZDP package pin functions that drop out on the PYP package.

7

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢃꢊ

ꢋ ꢌ ꢍꢎꢀ ꢏ ꢐ ꢑꢒꢓꢍꢏ ꢐ ꢀ ꢔꢏ ꢑ ꢏ ꢀꢎꢌ ꢂ ꢏ ꢑꢐ ꢎꢌ ꢓ ꢕꢍ ꢆꢖꢂ ꢂꢍ ꢕ

SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

Table 1. Terminal Assignments for the 272-Ball GDP and ZDP Package (in Order of Ball No.) (Continued)

BALL NO.

N1

SIGNAL NAME

BALL NO.

U9

SIGNAL NAME

SCL0

SDA0

ED31

V

SS

N2

U10

U11

U12

U13

U14

U15

U16

U17

U18

U19

U20

V1

CV

DV

DD

N3

N4

V

SS

N17

N18

N19

N20

P1

V

SS

ED6

CV

DV

DD

ED7

ED8

ED28

ED29

ED30

V

SS

P2

EA21

BE1

P3

P4

V

SS

P17

P18

P19

P20

R1

ED20

ED19

SS

ED9

V2

V

V3

CV

DD

SS

ED10

DV

V4

ED16

BE3

CE3

EA3

EA5

EA8

EA10

V5

DD

R2

ED27

ED26

V6

R3

V7

R4

CV

DV

V8

DD

R17

R18

R19

R20

T1

V9

V10

V11

V12

V13

V14

V15

V16

V17

V18

V19

V20

W1

ED11

ED12

ED24

ED25

ARE/SDCAS/SSADS

AWE/SDWE/SSWE

DV

DD

EA12

DV

T2

T3

DV

DD

T4

V

SS

V

SS

EA17

CE0

T17

T18

T19

T20

U1

ED13

ED15

ED14

ED22

ED21

ED23

CV

DV

DD

BE0

V

SS

U2

W2

CV

DV

DD

U3

W3

U4

V

SS

W4

ED17

U5

DV

CV

DV

W5

V

SS

DD

U6

W6

CE2

EA4

EA6

U7

W7

U8

V

SS

W8

Shading denotes the GDP and ZDP package pin functions that drop out on the PYP package.

8

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢈ ꢉꢃ ꢊ

ꢋ ꢌꢍ ꢎꢀ ꢏꢐꢑ ꢒꢓ ꢍꢏ ꢐꢀ ꢔꢏ ꢑꢏ ꢀꢎꢌ ꢂꢏ ꢑ ꢐꢎꢌ ꢓꢕ ꢍ ꢆꢖ ꢂ ꢂꢍ ꢕ

SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

Table 1. Terminal Assignments for the 272-Ball GDP and ZDP Package (in Order of Ball No.) (Continued)

BALL NO.

W9

SIGNAL NAME

BALL NO.

Y5

SIGNAL NAME

DV

ARDY

EA2

DD

AOE/SDRAS/SSOE

W10

W11

W12

W13

W14

W15

W16

W17

W18

W19

W20

Y1

Y6

V

SS

DV

Y7

DV

DD

Y8

EA7

EA9

DD

EA11

EA13

EA15

Y9

Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y17

Y18

Y19

Y20

ECLKOUT

ECLKIN

V

SS

CLKOUT2/GP[2]

EA19

CE1

V

SS

EA14

EA16

EA18

CV

DD

V

SS

DV

DD

EA20

SS

Y2

Y3

ED18

BE2

V

SS

Y4

SS

Shading denotes the GDP and ZDP package pin functions that drop out on the PYP package.

9

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢃꢊ

ꢋ ꢌ ꢍꢎꢀ ꢏ ꢐ ꢑꢒꢓꢍꢏ ꢐ ꢀ ꢔꢏ ꢑ ꢏ ꢀꢎꢌ ꢂ ꢏ ꢑꢐ ꢎꢌ ꢓ ꢕꢍ ꢆꢖꢂ ꢂꢍ ꢕ

SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

PYP PowerPAD QFP package (top view)

PYP 208-PIN PowerPAD PLASTIC QUAD FLATPACK (PQFP)

(TOP VIEW)

CV

DD

CE1

CE0

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

CV

104

103

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

DD

V

SS

HD5/AHCLKX1

HD8/GP[8]

EA20

EA19

EA17

HD6/AHCLKR1

DV

DD

V

DV

V

SS

DD

HD7/GP[3]

HD9/GP[9]

SS

CV

DD

EA18

EA15

EA12

EA16

EA13

EA14

HD10/GP[10]

HD11/GP[11]

HD12/GP[12]

CV

DD

V

SS

DD

CV

SS

HD13/GP[13]

HD14/GP[14]

HD15/GP[15]

DD

Exposed

Thermal

PAD

V

DV

DD

EA11

NMI

RESET

V

DV

SS

DD

CV

DD

AWE/SDWE/SSWE

CLKOUT2/GP[2]

RSV

V

CV

SS

DD

8,30

6,79

V

ARE/SDCAS/SSADS

ECLKIN

ECLKOUT

SS

DD

DV

CLKOUT3

EMU1

EA10

AOE/SDRAS/SSOE

EA9

EMU0

TDO

DV

V

DD

SS

DD

SS

V

DV

DD

CV

EA8

TDI

TMS

TCK

EA7

EA6

EA5

V

SS

CV

DD

CV

DD

CV

SS

DD

V

DV

DD

TRST

RSV

V

RSV

CV

EA4

EA3

EA2

CE2

8,30

6,79

SS

CV

DD

PLLHV

V

CLKIN

CLKMODE0

V

SS

DV

DD

SS

CE3

ARDY

DV

DD

V

CV

SS

CV

SS

DD

NOTE: All linear dimensions are in millimeters. This pad is electrically and thermally connected to the backside of the die.

For the TMS320C6713B 208-Pin PowerPAD plastic quad flatpack, the external thermal pad dimensions are: 7.2 x 7.2 mm and the thermal

pad is externally flush with the mold compound.

10

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ꢌ

ꢋ

ꢌꢍ

ꢎꢀ

ꢏ

ꢐ

ꢑ

ꢒ

ꢓ

ꢍꢏ

ꢐ

ꢀ

ꢔ

ꢏ

ꢑꢏ

ꢀꢎ

ꢌ

ꢂ

ꢏ

ꢑ

ꢐ

ꢎ

ꢓ

ꢕ

ꢍ

ꢆ

ꢖ

ꢂ

ꢍ

ꢕ

SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

description

†

The TMS320C67xt DSPs (including the TMS320C6713B device ) compose the floating-point DSP generation

in the TMS320C6000t DSP platform. The C6713B device is based on the high-performance, advanced

very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an

excellent choice for multichannel and multifunction applications.

Operating at 225 MHz, the C6713B delivers up to 1350 million floating-point operations per second (MFLOPS),

1800 million instructions per second (MIPS), and with dual fixed-/floating-point multipliers up to 450 million

multiply-accumulate operations per second (MMACS).

Operating at 300 MHz, the C6713B delivers up to 1800 million floating-point operations per second (MFLOPS),

2400 million instructions per second (MIPS), and with dual fixed-/floating-point multipliers up to 600 million

multiply-accumulate operations per second (MMACS).

The C6713B uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The

Level 1 program cache (L1P) is a 4K-byte direct-mapped cache and the Level 1 data cache (L1D) is a 4K-byte

2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 256K-byte memory space that is

shared between program and data space. 64K bytes of the 256K bytes in L2 memory can be configured as

mapped memory, cache, or combinations of the two. The remaining 192K bytes in L2 serves as mapped SRAM.

The C6713B has a rich peripheral set that includes two Multichannel Audio Serial Ports (McASPs), two

Multichannel Buffered Serial Ports (McBSPs), two Inter-Integrated Circuit (I2C) buses, one dedicated

General-Purpose Input/Output (GPIO) module, two general-purpose timers, a host-port interface (HPI), and a

glueless external memory interface (EMIF) capable of interfacing to SDRAM, SBSRAM, and asynchronous

peripherals.

The two McASP interface modules each support one transmit and one receive clock zone. Each of the McASP

has eight serial data pins which can be individually allocated to any of the two zones. The serial port supports

time-division multiplexing on each pin from 2 to 32 time slots. The C6713B has sufficient bandwidth to support

all 16 serial data pins transmitting a 192 kHz stereo signal. Serial data in each zone may be transmitted and

received on multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips

Inter-IC Sound (I2S) format.

In addition, the McASP transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3, CP-430

encoded data channels simultaneously, with a single RAM containing the full implementation of user data and

channel status fields.

The McASP also provides extensive error-checking and recovery features, such as the bad clock detection

circuit for each high-frequency master clock which verifies that the master clock is within a programmed

frequency range.

The two I2C ports on the TMS320C6713B allow the DSP to easily control peripheral devices and communicate

with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to

communicate with serial peripheral interface (SPI) mode peripheral devices.

The TMS320C6713B device has two bootmodes: from the HPI or from external asynchronous ROM. For more

detailed information, see the bootmode section of this data sheet.

The TMS320C67x DSP generation is supported by the TI eXpressDSPt set of industry benchmark

development tools, including a highly optimizing C/C++ Compiler, the Code Composer Studiot Integrated

Development Environment (IDE), JTAG-based emulation and real-time debugging, and the DSP/BIOSt

kernel.

TMS320C6000, eXpressDSP, Code Composer Studio, and DSP/BIOS are trademarks of Texas Instruments.

†

Throughout the remainder of this document, TMS320C6713B shall be referred to as C6713B or 13B.

11

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

device characteristics

Table 2 provides an overview of the C6713B DSP. The table shows significant features of the device, including

the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count. For more

details on the C67x DSP device part numbers and part numbering, see Figure 12.

Table 2. Characteristics of the C6713B Processor

C6713B

INTERNAL CLOCK

(FLOATING-POINT DSP)

HARDWARE FEATURES

SOURCE

GDP/ZDP

PYP

EMIF

SYSCLK3 or ECLKIN

CPU clock frequency

SYSCLK2

1 (32 bit)

1 (16 bit)

Peripherals

EDMA

(16 Channels)

1

Not all peripheral pins are

available at the same

time. (For more details,

see the Device

HPI (16 bit)

McASPs

1

†

AUXCLK, SYSCLK2

SYSCLK2

2

I2Cs

2

Configurations section.)

McBSPs

SYSCLK2

2

Peripheral performance is

dependent on chip-level

configuration.

32-Bit Timers

GPIO Module

Size (Bytes)

1/2 of SYSCLK2

SYSCLK2

1

264K

4K-Byte (4KB) L1 Program (L1P) Cache

4KB L1 Data (L1D) Cache

64KB Unified L2 Cache/Mapped RAM

192KB L2 Mapped RAM

On-Chip Memory

Organization

CPU ID+CPU Rev ID

BSDL File

Control Status Register (CSR.[31:16])

For the C6713B BSDL file, contact your Field Sales Representative.

0x0203

Frequency

MHz

300, 225, 200

225, 200, 167

3.3 ns (GDP-300, ZDP-300)

4.4 ns (GDP-225, ZDP-225)

5 ns (GDPA-200,

5 ns (PYP-200)

4.4 ns (PYP-225)

6 ns (PYPA−167)

5 ns (PYPA-200)

Cycle Time

ns

ZDPA-200)

‡

1.20

V

Core (V)

I/O (V)

1.2 V

1.4 V (−300)

Voltage

3.3 V

Prescaler

Multiplier

Postscaler

/1, /2, /3, ..., /32

x4, x5, x6, ..., x25

/1, /2, /3, ..., /32

Clock Generator Options

272-Ball BGA (GDP)

272-Ball BGA (ZDP)

27 x 27 mm

−

Packages

208-Pin PowerPAD

28 x 28 mm

−

PQFP (PYP)

Process Technology

µm

0.13

Product Status

Product Preview (PP)

Advance Information (AI)

Production Data (PD)

§

PD

†

AUXCLK is the McASP internal high-frequency clock source for serial transfers. SYSCLK2 is the McASP system clock used for the clock

check (high-frequency) circuit.

This value is compatible with existing 1.26-V designs.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include testing of all parameters.

‡

§

C67x is a trademark of Texas Instruments.

12

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

functional block and CPU (DSP core) diagram

Digital Signal Processor

32

L1P Cache

Direct Mapped

4K Bytes Total

EMIF

L2 Cache/

Memory

4 Banks

64K Bytes

Total

McASP1

McASP0

McBSP1

McBSP0

I2C1

C67x CPU

(up to

4-Way)

Instruction Fetch

Instruction Dispatch

Instruction Decode

Control

Registers

Control

Logic

Data Path A

Data Path B

Test

A Register File

B Register File

In-Circuit

Emulation

Enhanced

DMA

Interrupt

Control

†

.L1 .S1 .M1 .D1

.D2 .M2 .S2 .L2

Controller

(16 channel)

I2C0

L1D Cache

2-Way

Set Associative

4K Bytes

L2

Memory

192K

Bytes

Timer 1

Timer 0

Clock Generator and PLL

x4 through x25 Multiplier

/1 through /32 Dividers

Power-Down

Logic

GPIO

HPI

16

†

In addition to fixed-point instructions, these functional units execute floating-point instructions.

EMIF interfaces to:

−SDRAM

−SBSRAM

McBSPs interface to:

−SPI Control Port

−High-Speed TDM Codecs

−AC97 Codecs

McASPs interface to:

−I2S Multichannel ADC, DAC, Codec, DIR

−DIT: Multiple Outputs

−SRAM,

−ROM/Flash, and

−I/O devices

−Serial EEPROM

13

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

CPU (DSP core) description

The TMS320C6713B floating-point digital signal processor is based on the C67x CPU. The CPU fetches

advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight 32-bit instructions to the eight

functional units during every clock cycle. The VLIW architecture features controls by which all eight units do not

have to be supplied with instructions if they are not ready to execute. The first bit of every 32-bit instruction

determines if the next instruction belongs to the same execute packet as the previous instruction, or whether

it should be executed in the following clock as a part of the next execute packet. Fetch packets are always 256

bits wide; however, the execute packets can vary in size. The variable-length execute packets are a key

memory-saving feature, distinguishing the C67x CPU from other VLIW architectures.

The CPU features two sets of functional units. Each set contains four units and a register file. One set contains

functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files

each contain 16 32-bit registers for a total of 32 general-purpose registers. The two sets of functional units, along

with two register files, compose sides A and B of the CPU (see the functional block and CPU diagram and

Figure 1). The four functional units on each side of the CPU can freely share the 16 registers belonging to that

side. Additionally, each side features a single data bus connected to all the registers on the other side, by which

the two sets of functional units can access data from the register files on the opposite side. While register access

by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle,

register access using the register file across the CPU supports one read and one write per cycle.

The C67x CPU executes all C62x instructions. In addition to C62x fixed-point instructions, the six out of eight

functional units (.L1, .S1, .M1, .M2, .S2, and .L2) also execute floating-point instructions. The remaining two

functional units (.D1 and .D2) also execute the new LDDW instruction which loads 64 bits per CPU side for a

total of 128 bits per cycle.

Another key feature of the C67x CPU is the load/store architecture, where all instructions operate on registers

(as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data

transfers between the register files and the memory. The data address driven by the .D units allows data

addresses generated from one register file to be used to load or store data to or from the other register file. The

C67x CPU supports a variety of indirect addressing modes using either linear- or circular-addressing modes

with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers. Some

registers, however, are singled out to support specific addressing or to hold the condition for conditional

instructions (if the condition is not automatically “true”). The two .M functional units are dedicated for multiplies.

The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results

available every clock cycle.

The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory.

The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least

significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous

execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain,

effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the

fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of

the current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet

can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one

per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch

packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units

for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit

registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store

instructions are byte-, half-word, or word-addressable.

14

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

CPU (DSP core) description (continued)

src1

†

.L1

src2

dst

8

long dst

long src

8

32

LD1 32 MSB

ST1

32

Register

File A

(A0−A15)

long src

long dst

dst

8

Data Path A

†

.S1

src1

src2

dst

†

.M1

src1

src2

LD1 32 LSB

DA1

dst

src1

src2

.D1

2X

1X

src2

src1

dst

DA2

.D2

.M2

LD2 32 LSB

src2

†

src1

dst

src2

Register

File B

(B0−B15)

src1

dst

†

.S2

Data Path B

8

long dst

long src

8

32

LD2 32 MSB

ST2

long src

long dst

dst

8

†

.L2

src2

src1

Control

Register File

†

In addition to fixed-point instructions, these functional units execute floating-point instructions.

Figure 1. TMS320C67x CPU (DSP Core) Data Paths

15

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

memory map summary

Table 3 shows the memory map address ranges of the device.

Table 3. Memory Map Summary

MEMORY BLOCK DESCRIPTION

Internal RAM (L2)

Internal RAM/Cache

Reserved

BLOCK SIZE (BYTES)

192K

64K

HEX ADDRESS RANGE

0000 0000 – 0002 FFFF

0003 0000 – 0003 FFFF

0004 0000 – 017F FFFF

0180 0000 – 0183 FFFF

0184 0000 – 0185 FFFF

0186 0000 – 0187 FFFF

0188 0000 – 018B FFFF

018C 0000 – 018F FFFF

0190 0000 – 0193 FFFF

0194 0000 – 0197 FFFF

0198 0000 – 019B FFFF

019C 0000 – 019C 01FF

019C 0200 – 019C 0203

019C 0204 – 019F FFFF

01A0 0000 – 01A3 FFFF

01A4 0000 – 01AF FFFF

01B0 0000 – 01B0 3FFF

01B0 4000 – 01B3 FFFF

01B4 0000 – 01B4 3FFF

01B4 4000 – 01B4 7FFF

01B4 8000 – 01B4 BFFF

01B4 C000 – 01B4 FFFF

01B5 0000 – 01B5 3FFF

01B5 4000 – 01B7 BFFF

01B7 C000 – 01B7 DFFF

01B7 E000 – 01BB FFFF

01BC 0000 – 01BF FFFF

01C0 0000 – 01FF FFFF

0200 0000 – 0200 0033

0200 0034 – 02FF FFFF

0300 0000 – 2FFF FFFF

3000 0000 – 33FF FFFF

3400 0000 – 37FF FFFF

3800 0000 – 3BFF FFFF

3C00 0000 – 3C0F FFFF

3C10 0000 – 3C1F FFFF

3C20 0000 – 7FFF FFFF

8000 0000 – 8FFF FFFF

9000 0000 – 9FFF FFFF

A000 0000 – AFFF FFFF

B000 0000 – BFFF FFFF

C000 0000 – FFFF FFFF

24M – 256K

256K

128K

256K

512

External Memory Interface (EMIF) Registers

L2 Registers

Reserved

HPI Registers

McBSP 0 Registers

McBSP 1 Registers

Timer 0 Registers

Timer 1 Registers

Interrupt Selector Registers

Device Configuration Registers

Reserved

4

256K − 516

256K

768K

16K

EDMA RAM and EDMA Registers

Reserved

GPIO Registers

Reserved

240K

16K

I2C0 Registers

I2C1 Registers

16K

Reserved

16K

McASP0 Registers

McASP1 Registers

Reserved

16K

160K

8K

PLL Registers

Reserved

264K

256K

4M

Emulation Registers

Reserved

QDMA Registers

Reserved

52

16M − 52

720M

64M

Reserved

McBSP0 Data Port

McBSP1 Data Port

Reserved

64M

McASP0 Data Port

McASP1 Data Port

Reserved

1M

1G + 62M

256M

1G

†

EMIF CE0

EMIF CE1

EMIF CE2

EMIF CE3

Reserved

†

The number of EMIF address pins (EA[21:2]) limits the maximum addressable memory (SDRAM) to 128MB per CE space.

16

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

L2 memory structure expanded

Figure 2 shows the detail of the L2 memory structure.

L2 Mode

L2 Memory

Block Base Address

0x0000 0000

000

001

010

011

111

192K-Byte RAM

0x0003 0000

16K-Byte RAM

0x0003 4000

0x0003 8000

16K-Byte RAM

0x0003 C000

0x0003 FFFF

Figure 2. L2 Memory Configuration

17

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

peripheral register descriptions

Table 4 through Table 17 identify the peripheral registers for the device by their register names, acronyms, and

hex address or hex address range. For more detailed information on the register contents, bit names and their

descriptions, see the specific peripheral reference guide listed in the TMS320C6000 DSP Peripherals Overview

Reference Guide (literature number SPRU190).

Table 4. EMIF Registers

HEX ADDRESS RANGE

0180 0000

ACRONYM

GBLCTL

CECTL1

CECTL0

−

REGISTER NAME

EMIF global control

EMIF CE1 space control

EMIF CE0 space control

Reserved

0180 0004

0180 0008

0180 000C

0180 0010

CECTL2

CECTL3

SDCTL

SDTIM

SDEXT

−

EMIF CE2 space control

EMIF CE3 space control

EMIF SDRAM control

EMIF SDRAM refresh control

EMIF SDRAM extension

Reserved

0180 0014

0180 0018

0180 001C

0180 0020

0180 0024 − 0183 FFFF

Table 5. L2 Cache Registers

HEX ADDRESS RANGE

0184 0000

ACRONYM

CCFG

REGISTER NAME

Cache configuration register

0184 4000

L2WBAR

L2WWC

L2WIBAR

L2WIWC

L1PIBAR

L1PIWC

L1DWIBAR

L1DWIWC

L2WB

L2 writeback base address register

0184 4004

L2 writeback word count register

0184 4010

L2 writeback-invalidate base address register

L2 writeback-invalidate word count register

L1P invalidate base address register

0184 4014

0184 4020

0184 4024

L1P invalidate word count register

0184 4030

L1D writeback-invalidate base address register

L1D writeback-invalidate word count register

L2 writeback all register

0184 4034

0184 5000

0184 5004

L2WBINV

MAR0

L2 writeback-invalidate all register

0184 8200

Controls CE0 range 8000 0000 − 80FF FFFF

Controls CE0 range 8100 0000 − 81FF FFFF

Controls CE0 range 8200 0000 − 82FF FFFF

Controls CE0 range 8300 0000 − 83FF FFFF

Controls CE1 range 9000 0000 − 90FF FFFF

Controls CE1 range 9100 0000 − 91FF FFFF

Controls CE1 range 9200 0000 − 92FF FFFF

Controls CE1 range 9300 0000 − 93FF FFFF

Controls CE2 range A000 0000 − A0FF FFFF

Controls CE2 range A100 0000 − A1FF FFFF

Controls CE2 range A200 0000 − A2FF FFFF

Controls CE2 range A300 0000 − A3FF FFFF

Controls CE3 range B000 0000 − B0FF FFFF

Controls CE3 range B100 0000 − B1FF FFFF

Controls CE3 range B200 0000 − B2FF FFFF

Controls CE3 range B300 0000 − B3FF FFFF

Reserved

0184 8204

MAR1

0184 8208

MAR2

0184 820C

0184 8240

MAR3

MAR4

0184 8244

MAR5

0184 8248

MAR6

0184 824C

0184 8280

MAR7

MAR8

0184 8284

MAR9

0184 8288

MAR10

MAR11

MAR12

MAR13

MAR14

MAR15

−

0184 828C

0184 82C0

0184 82C4

0184 82C8

0184 82CC

0184 82D0 − 0185 FFFF

18

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

peripheral register descriptions (continued)

Table 6. Interrupt Selector Registers

HEX ADDRESS RANGE

ACRONYM

REGISTER NAME

COMMENTS

Selects which interrupts drive CPU interrupts

10−15 (INT10−INT15)

019C 0000

MUXH

Interrupt multiplexer high

Interrupt multiplexer low

Selects which interrupts drive CPU interrupts 4−9

(INT04−INT09)

019C 0004

MUXL

Sets the polarity of the external interrupts

(EXT_INT4−EXT_INT7)

019C 0008

EXTPOL

−

External interrupt polarity

Reserved

019C 000C − 019F FFFF

Table 7. Device Registers

HEX ADDRESS RANGE

019C 0200

ACRONYM

DEVCFG

−

REGISTER DESCRIPTION

Allows the user to control peripheral selection.

This register also offers the user control of the

EMIF input clock source. For more detailed

information on the device configuration register, see

the Device Configurations section of this data

sheet.

Device Configuration

Reserved

019C 0204 − 019F FFFF

N/A

Identifies which CPU and defines the silicon

revision of the CPU. This register also offers the

user control of device operation.

For more detailed information on the CPU Control

Status Register, see the CPU CSR Register

Description section of this data sheet.

CSR

CPU Control Status Register

†

Table 8. EDMA Parameter RAM

HEX ADDRESS RANGE

01A0 0000 − 01A0 0017

01A0 0018 − 01A0 002F

01A0 0030 − 01A0 0047

01A0 0048 − 01A0 005F

01A0 0060 − 01A0 0077

01A0 0078 − 01A0 008F

01A0 0090 − 01A0 00A7

01A0 00A8 − 01A0 00BF

01A0 00C0 − 01A0 00D7

01A0 00D8 − 01A0 00EF

01A0 00F0 − 01A0 00107

01A0 0108 − 01A0 011F

01A0 0120 − 01A0 0137

01A0 0138 − 01A0 014F

01A0 0150 − 01A0 0167

01A0 0168 − 01A0 017F

01A0 0180 − 01A0 0197

01A0 0198 − 01A0 01AF

...

ACRONYM

REGISTER NAME

−

Parameters for Event 0 (6 words) or Reload/Link Parameters for other Event

Parameters for Event 1 (6 words) or Reload/Link Parameters for other Event

Parameters for Event 2 (6 words) or Reload/Link Parameters for other Event

Parameters for Event 3 (6 words) or Reload/Link Parameters for other Event

Parameters for Event 4 (6 words) or Reload/Link Parameters for other Event

Parameters for Event 5 (6 words) or Reload/Link Parameters for other Event

Parameters for Event 6 (6 words) or Reload/Link Parameters for other Event

Parameters for Event 7 (6 words) or Reload/Link Parameters for other Event

Parameters for Event 8 (6 words) or Reload/Link Parameters for other Event

Parameters for Event 9 (6 words) or Reload/Link Parameters for other Event

Parameters for Event 10 (6 words) or Reload/Link Parameters for other Event

Parameters for Event 11 (6 words) or Reload/Link Parameters for other Event

Parameters for Event 12 (6 words) or Reload/Link Parameters for other Event

Parameters for Event 13 (6 words) or Reload/Link Parameters for other Event

Parameters for Event 14 (6 words) or Reload/Link Parameters for other Event

Parameters for Event 15 (6 words) or Reload/Link Parameters for other Event

Reload/link parameters for Event 0−15

...

01A0 07E0 − 01A0 07F7

01A0 07F8 − 01A0 07FF

−

Reload/link parameters for Event 0−15

Scratch pad area (2 words)

†

The device has 85 EDMA parameters total: 16 Event/Reload parameters and 69 Reload-only parameters.

19

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

peripheral register descriptions (continued)

For more details on the EDMA parameter RAM 6-word parameter entry structure, see Figure 3.

31

0

EDMA Parameter

Word 0

Word 1

Word 2

Word 3

Word 4

Word 5

EDMA Channel Options Parameter (OPT)

EDMA Channel Source Address (SRC)

OPT

SRC

CNT

DST

IDX

Array/Frame Count (FRMCNT)

Element Count (ELECNT)

EDMA Channel Destination Address (DST)

Array/Frame Index (FRMIDX)

Element Count Reload (ELERLD)

Element Index (ELEIDX)

Link Address (LINK)

RLD

Figure 3. EDMA Channel Parameter Entries (6 Words) for Each EDMA Event

Table 9. EDMA Registers

HEX ADDRESS RANGE

01A0 0800 − 01A0 FEFC

01A0 FF00

ACRONYM

−

REGISTER NAME

Reserved

ESEL0

ESEL1

−

EDMA event selector 0

EDMA event selector 1

Reserved

01A0 FF04

01A0 FF08 − 01A0 FF0B

01A0 FF0C

ESEL3

−

EDMA event selector 3

Reserved

01A0 FF1F − 01A0 FFDC

01A0 FFE0

PQSR

CIPR

CIER

CCER

ER

Priority queue status register

Channel interrupt pending register

Channel interrupt enable register

Channel chain enable register

Event register

01A0 FFE4

01A0 FFE8

01A0 FFEC

01A0 FFF0

01A0 FFF4

EER

ECR

ESR

–

Event enable register

Event clear register

Event set register

01A0 FFF8

01A0 FFFC

01A1 0000 − 01A3 FFFF

Reserved

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

peripheral register descriptions (continued)

†

Table 10. Quick DMA (QDMA) and Pseudo Registers

HEX ADDRESS RANGE

0200 0000

ACRONYM

QOPT

QSRC

QCNT

QDST

QIDX

REGISTER NAME

QDMA options parameter register

QDMA source address register

QDMA frame count register

QDMA destination address register

QDMA index register

0200 0004

0200 0008

0200 000C

0200 0010

0200 0014 − 0200 001C

0200 0020

−

Reserved

QSOPT

QSSRC

QSCNT

QSDST

QSIDX

QDMA pseudo options register

0200 0024

QDMA pseudo source address register

QDMA pseudo frame count register

QDMA pseudo destination address register

QDMA pseudo index register

0200 0028

0200 002C

0200 0030

†

All the QDMA and Pseudo registers are write-accessible only

Table 11. PLL Controller Registers

HEX ADDRESS RANGE

01B7 C000

ACRONYM

PLLPID

−

REGISTER NAME

Peripheral identification register (PID) [0x00010801 for PLL Controller]

Reserved

01B7 C004 − 01B7 C0FF

01B7 C100

PLLCSR

−

PLL control/status register

Reserved

01B7 C104 − 01B7 C10F

01B7 C110

PLLM

PLL multiplier control register

PLL controller divider 0 register

PLL controller divider 1 register

PLL controller divider 2 register

PLL controller divider 3 register

Oscillator divider 1 register

Reserved

01B7 C114

PLLDIV0

PLLDIV1

PLLDIV2

PLLDIV3

OSCDIV1

−

01B7 C118

01B7 C11C

01B7 C120

01B7 C124

01B7 C128 − 01B7 DFFF

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

peripheral register descriptions (continued)

Table 12. McASP0 and McASP1 Registers

HEX ADDRESS RANGE

ACRONYM

REGISTER NAME

McASP0

McASP1

McASPx receive buffer or McASPx transmit buffer via the

Peripheral Data Bus.

(Used when RSEL or XSEL bits = 0 [these bits are located

in the RFMT or XFMT registers, respectively].)

3C00 0000 − 3C00 FFFF

3C10 0000 − 3C10 FFFF

RBUF/XBUFx

MCASPPIDx

Peripheral Identification register

[0x00100101 for McASP0 and for McASP1]

01B4 C000

01B5 0000

01B4 C004

01B4 C008

01B4 C00C

01B4 C010

01B4 C014

01B4 C018

01B5 0004

01B5 0008

01B5 000C

01B5 0010

01B5 0014

01B5 0018

PWRDEMUx

−

Power down and emulation management register

Reserved

−

Reserved

PFUNCx

PDIRx

PDOUTx

Pin function register

Pin direction register

Pin data out register

Pin data in / data set register

Read returns: PDIN

Writes affect: PDSET

01B4 C01C

01B5 001C

PDIN/PDSETx

01B4 C020

01B4 C024 − 01B4 C040

01B4 C044

01B5 0020

01B5 0024 − 01B5 0040

01B5 0044

PDCLRx

−

Pin data clear register

Reserved

GBLCTLx

AMUTEx

DLBCTLx

DITCTLx

−

Global control register

Mute control register

Digital Loop-back control register

DIT mode control register

Reserved

01B4 C048

01B5 0048

01B4 C04C

01B5 004C

01B4 C050

01B5 0050

01B4 C054 − 01B4 C05C

01B5 0054 − 01B5 005C

Alias of GBLCTL containing only Receiver Reset bits,

allows transmit to be reset independently from receive.

01B4 C060

01B5 0060

RGBLCTLx

01B4 C064

01B4 C068

01B5 0064

01B5 0068

RMASKx

RFMTx

Receiver format unit bit mask register

Receive bit stream format register

Receive frame sync control register

Receive clock control register

01B4 C06C

01B5 006C

AFSRCTLx

ACLKRCTLx

01B4 C070

01B5 0070

01B4 C074

01B5 0074

AHCLKRCTLx High-frequency receive clock control register

01B4 C078

01B5 0078

RTDMx

RINTCTLx

RSTATx

RSLOTx

RCLKCHKx

−

Receive TDM slot 0−31 register

Receiver interrupt control register

Status register − Receiver

Current receive TDM slot register

Receiver clock check control register

Reserved

01B4 C07C

01B5 007C

01B4 C080

01B5 0080

01B4 C084

01B5 0084

01B4 C088

01B5 0088

01B4 C08C − 01B4 C09C

01B5 008C − 01B5 009C

Alias of GBLCTL containing only Transmitter Reset bits,

allows transmit to be reset independently from receive.

01B4 C0A0

01B5 00A0

XGBLCTLx

01B4 C0A4

01B4 C0A8

01B4 C0AC

01B4 C0B0

01B4 C0B4

01B5 00A4

01B5 00A8

01B5 00AC

01B5 00B0

01B5 00B4

XMASKx

XFMTx

Transmit format unit bit mask register

Transmit bit stream format register

Transmit frame sync control register

Transmit clock control register

AFSXCTLx

ACLKXCTLx

AHCLKXCTLx High-frequency Transmit clock control register

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

peripheral register descriptions (continued)

Table 12. McASP0 and McASP1 Registers (Continued)

HEX ADDRESS RANGE

ACRONYM

REGISTER NAME

Transmit TDM slot 0−31 register

McASP0

01B4 C0B8

01B4 C0BC

01B4 C0C0

01B4 C0C4

01B4 C0C8

01B4 C0D0 − 01B4 C0FC

01B4 C100

McASP1

01B5 00B8

01B5 00BC

01B5 00C0

01B5 00C4

01B5 00C8

01B5 00CC − 01B5 00FC

01B5 0100

XTDMx

XINTCTLx

XSTATx

Transmit interrupt control register

Status register − Transmitter

XSLOTx

Current transmit TDM slot

XCLKCHKx

−

Transmit clock check control register

Reserved

DITCSRA0x

DITCSRA1x

DITCSRA2x

DITCSRA3x

DITCSRA4x

DITCSRA5x

DITCSRB0x

DITCSRB1x

DITCSRB2x

DITCSRB3x

DITCSRB4x

DITCSRB5x

DITUDRA0x

DITUDRA1x

DITUDRA2x

DITUDRA3x

DITUDRA4x

DITUDRA5x

DITUDRB0x

DITUDRB1x

DITUDRB2x

DITUDRB3x

DITUDRB4x

DITUDRB5x

−

Left (even TDM slot) channel status register file

Right (odd TDM slot) channel status register file

Left (even TDM slot) user data register file

Right (odd TDM slot) user data register file

Reserved

01B4 C104

01B5 0104

01B4 C108

01B5 0108

01B4 C10C

01B4 C110

01B5 010C

01B5 0110

01B4 C114

01B5 0114

01B4 C118

01B5 0118

01B4 C11C

01B4 C120

01B5 011C

01B5 0120

01B4 C124

01B5 0124

01B4 C128

01B5 0128

01B4 C12C

01B4 C130

01B5 012C

01B5 0130

01B4 C134

01B5 0134

01B4 C138

01B5 0138

01B4 C13C

01B4 C140

01B5 013C

01B5 0140

01B4 C144

01B5 0144

01B4 C148

01B5 0148

01B4 C14C

01B4 C150

01B5 014C

01B5 0150

01B4 C154

01B5 0154

01B4 C158

01B5 0158

01B4 C15C

01B4 C160 − 01B4 C17C

01B4 C180

01B5 015C

01B5 0160 − 01B5 017C

01B5 0180

SRCTL0x

SRCTL1x

SRCTL2x

SRCTL3x

SRCTL4x

SRCTL5x

SRCTL6x

SRCTL7x

−

Serializer 0 control register

01B4 C184

01B5 0184

Serializer 1 control register

01B4 C188

01B5 0188

Serializer 2 control register

01B4 C18C

01B4 C190

01B5 018C

01B5 0190

Serializer 3 control register

Serializer 4 control register

01B4 C194

01B5 0194

Serializer 5 control register

01B4 C198

01B5 0198

Serializer 6 control register

01B4 C19C

01B4 C1A0 − 01B4 C1FC

01B5 019C

01B5 01A0 − 01B5 01FC

Serializer 7 control register

Reserved

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

peripheral register descriptions (continued)

Table 12. McASP0 and McASP1 Registers (Continued)

HEX ADDRESS RANGE

ACRONYM

REGISTER NAME

McASP0

01B4 C200

McASP1

01B5 0200

†

XBUF0x

XBUF1x

XBUF2x

XBUF3x

XBUF4x

XBUF5x

XBUF6x

XBUF7x

−

Transmit Buffer for Serializer 0 through configuration bus

Transmit Buffer for Serializer 1 through configuration bus

Transmit Buffer for Serializer 2 through configuration bus

Transmit Buffer for Serializer 3 through configuration bus

Transmit Buffer for Serializer 4 through configuration bus

Transmit Buffer for Serializer 5 through configuration bus

Transmit Buffer for Serializer 6 through configuration bus

Transmit Buffer for Serializer 7 through configuration bus

Reserved

01B4 C204

01B5 0204

01B4 C208

01B5 0208

01B4 C20C

01B5 020C

01B4 C210

01B5 0210

01B4 C214

01B5 0214

01B4 C218

01B5 0218

01B4 C21C

01B5 021C

01B4 C220 − 01B4 C27C

01B4 C280

01B5 C220 − 01B5 027C

01B5 0280

‡

RBUF0x

RBUF1x

RBUF2x

RBUF3x

RBUF4x

RBUF5x

RBUF6x

RBUF7x

−

Receive Buffer for Serializer 0 through configuration bus

Receive Buffer for Serializer 1 through configuration bus

Receive Buffer for Serializer 2 through configuration bus

Receive Buffer for Serializer 3 through configuration bus

Receive Buffer for Serializer 4 through configuration bus

Receive Buffer for Serializer 5 through configuration bus

Receive Buffer for Serializer 6 through configuration bus

Receive Buffer for Serializer 7 through configuration bus

Reserved

‡

01B4 C284

01B5 0284

‡

01B4 C288

01B5 0288

01B4 C28C

01B5 028C

01B4 C290

01B5 0290

01B4 C294

01B5 0294

01B4 C298

01B5 0298

01B4 C29C

01B5 029C

01B4 C2A0 − 01B4 FFFF

01B5 02A0 − 01B5 3FFF

†

‡

The transmit buffers for serializers 0 − 7 are accessible to the CPU via the peripheral bus if the XSEL bit = 1 (XFMT register).

The receive buffers for serializers 0 − 7 are accessible to the CPU via the peripheral bus if the RSEL bit = 1 (RFMT register).

Table 13. I2C0 and I2C1 Registers

HEX ADDRESS RANGE

ACRONYM

REGISTER DESCRIPTION

I2Cx own address register

I2C0

I2C1

01B4 0000

01B4 0004

01B4 0008

01B4 000C

01B4 0010

01B4 0014

01B4 0018

01B4 001C

01B4 0020

01B4 0024

01B4 0028

01B4 002C

01B4 0030

01B4 4000

01B4 4004

01B4 4008

01B4 400C

01B4 4010

01B4 4014

01B4 4018

01B4 401C

01B4 4020

01B4 4024

01B4 4028

01B4 402C

01B4 4030

I2COARx

I2CIERx

I2CSTRx

I2CCLKLx

I2CCLKHx

I2CCNTx

I2CDRRx

I2CSARx

I2CDXRx

I2CMDRx

I2CISRCx

−

I2Cx interrupt enable register

I2Cx interrupt status register

I2Cx clock low-time divider register

I2Cx clock high-time divider register

I2Cx data count register

I2Cx data receive register

I2Cx slave address register

I2Cx data transmit register

I2Cx mode register

I2Cx interrupt source register

Reserved

I2CPSCx

I2Cx prescaler register

I2CPID10

I2CPID11

I2Cx Peripheral Identification register 1

[0x0000 0103]

01B4 0034

01B4 4034

I2CPID20

I2CPID21

I2Cx Peripheral Identification register 2

[0x0000 0005]

01B4 0038

01B4 4038

01B4 003C − 01B4 3FFF

01B4 403C − 01B4 7FFF

−

Reserved

24

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

peripheral register descriptions (continued)

Table 14. HPI Registers

HEX ADDRESS RANGE

ACRONYM

HPID

HPIA

REGISTER NAME

COMMENTS

−

HPI data register

Host read/write access only

Both Host/CPU read/write access

−

HPI address register

HPI control register

Reserved

0188 0000

HPIC

−

0188 0004 − 018B FFFF

Table 15. Timer 0 and Timer 1 Registers

HEX ADDRESS RANGE

ACRONYM

REGISTER NAME

COMMENTS

TIMER 0

TIMER 1

Determines the operating

mode of the timer, monitors the

timer status, and controls the

function of the TOUT pin.

0194 0000

0194 0004

0198 0000

CTLx

Timer x control register

Timer x period register

Contains the number of timer

input clock cycles to count.

This number controls the

TSTAT signal frequency.

0198 0004

PRDx

Contains the current value of

the incrementing counter.

0194 0008

0198 0008

CNTx

−

Timer x counter register

Reserved

0194 000C − 0197 FFFF

0198 000C − 019B FFFF

−

Table 16. McBSP0 and McBSP1 Registers

HEX ADDRESS RANGE

ACRONYM

REGISTER DESCRIPTION

McBSP0

McBSP1

McBSPx data receive register via Configuration Bus

018C 0000

0190 0000

DRRx

The CPU and EDMA controller can only read this register;

they cannot write to it.

3000 0000 − 33FF FFFF

018C 0004

3400 0000 − 37FF FFFF

0190 0004

DRRx

DXRx

SPCRx

RCRx

XCRx

SRGRx

MCRx

RCERx

XCERx

PCRx

−

McBSPx data receive register via Peripheral Data Bus

McBSPx data transmit register via Configuration Bus

McBSPx data transmit register via Peripheral Data Bus

McBSPx serial port control register

McBSPx receive control register

3000 0000 − 33FF FFFF

018C 0008

3400 0000 − 37FF FFFF

0190 0008

018C 000C

0190 000C

018C 0010

0190 0010

McBSPx transmit control register

018C 0014

0190 0014

McBSPx sample rate generator register

McBSPx multichannel control register

McBSPx receive channel enable register

McBSPx transmit channel enable register

McBSPx pin control register

018C 0018

0190 0018

018C 001C

0190 001C

018C 0020

0190 0020

018C 0024

0190 0024

018C 0028 − 018F FFFF

0190 0028 − 0193 FFFF

Reserved

25

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

peripheral register descriptions (continued)

Table 17. GPIO Registers

HEX ADDRESS RANGE

01B0 0000

ACRONYM

GPEN

GPDIR

GPVAL

−

REGISTER NAME

GPIO enable register

01B0 0004

GPIO direction register

GPIO value register

Reserved

01B0 0008

01B0 000C

01B0 0010

GPDH

GPHM

GPDL

GPLM

GPGC

GPPOL

−

GPIO delta high register

GPIO high mask register

GPIO delta low register

GPIO low mask register

GPIO global control register

GPIO interrupt polarity register

Reserved

01B0 0014

01B0 0018

01B0 001C

01B0 0020

01B0 0024

01B0 0028 − 01B0 3FFF

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

signal groups description

CLKIN

CLKOUT2/GP[2]

Clock/PLL

Oscillator

CLKOUT3

CLKMODE0

PLLHV

RESET

NMI

‡§

GP[7](EXT_INT7)

GP[6](EXT_INT6)

Reset and

Interrupts

TMS

TDO

‡§

GP[5](EXT_INT5)/AMUTEIN0

GP[4](EXT_INT4)/AMUTEIN1

TDI

‡

HD4/GP[0]

TCK

IEEE Standard

1149.1

(JTAG)

Emulation

TRST

EMU0

EMU1

†

EMU2

EMU3

†

EMU4

EMU5

Control/Status

HPI

(Host-Port Interface)

HD15/GP[15]

HD14/GP[14]

HAS/ACLKX1

HR/W/AXR1[0]

HCS/AXR1[2]

HDS1/AXR1[6]

HDS2/AXR1[5]

HRDY/ACLKR1

HINT/GP[1]

HD13/GP[13]

HD12/GP[12]

HD11/GP[11]

HD10/GP[10]

Control

HD9/GP[9]

HD8/GP[8]

HD7/GP[3]

Data

HD6/AHCLKR1

HD5/AHCLKX1

HD4/GP[0]

HD3/AMUTE1

HD2/AFSX1

HCNTL0/AXR1[3]

HCNTL1/AXR1[1]

Register Select

HD1/AXR1[7]

HD0/AXR1[4]

Half-Word

Select

HHWIL/AFSR1

†

‡

These external pins are applicable to the GDP and ZDP packages only.

The GP[15:0] pins, through interrupt sharing, are external interrupt capable via GPINT0. For more details, see the External

Interrupt Sources section of this data sheet. For more details on interrupt sharing, see the TMS320C6000 DSP Interrupt Selector

Reference Guide (literature number SPRU646).

§

All of these pins are external interrupt sources. For more details, see the External Interrupt Sources section of this data sheet.

NOTE A: On multiplexed pins, bolded text denotes the active function of the pin for that particular peripheral module.

Figure 4. CPU (DSP Core) and Peripheral Signals

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

signal groups description (continued)

GP[7](EXT_INT7)

GP[6](EXT_INT6)

GP[5](EXT_INT5)/AMUTEIN0

GP[4](EXT_INT4)/AMUTEIN1

HD7/GP[3]

HD15/GP[15]

HD14/GP[14]

HD13/GP[13]

HD12/GP[12]

HD11/GP[11]

HD10/GP[10]

HD9/GP[9]

†

GPIO

CLKOUT2/GP[2]

HINT/GP[1]

HD4/GP[0]

HD8/GP[8]

General-Purpose Input/Output (GPIO) Port

TOUT1/AXR0[4]

TINP1/AHCLKX0

TOUT0/AXR0[2]

TINP0/AXR0[3]

Timer 1

Timer 0

Timers

CLKS1/SCL1

DR1/SDA1

SCL0

SDA0

I2C1

I2C0

I2Cs

†

The GP[15:0] pins, through interrupt sharing, are external interrupt capable via GPINT0. GP[15:0] are also external EDMA event

source capable. For more details, see the External Interrupt Sources and External EDMA Event Sources sections of this data sheet.

NOTE A: On multiplexed pins, bolded text denotes the active function of the pin for that particular peripheral module.

Figure 5. Peripheral Signals

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

signal groups description (continued)

ECLKIN

ECLKOUT

16

†

ED[31:16]

Data

Memory

Control

ARE/SDCAS/SSADS

16

AOE/SDRAS/SSOE

AWE/SDWE/SSWE

ARDY

ED[15:0]

CE3

CE2

CE1

CE0

Memory Map

Space Select

HOLD

HOLDA

Bus

Arbitration

20

EA[21:2]

Address

BUSREQ

†

BE3

BE2

Byte Enables

BE1

BE0

EMIF

(External Memory Interface)

McBSP1

Transmit

McBSP0

Transmit

CLKX1/AMUTE0

FSX1

CLKX0/ACLKX0

FSX0/AFSX0

DX0/AXR0[1]

DX1/AXR0[5]

CLKR1/AXR0[6]

FSR1/AXR0[7]

DR1/SDA1

CLKR0/ACLKR0

FSR0/AFSR0

DR0/AXR0[0]

Receive

Clock

Receive

Clock

CLKS1/SCL1

CLKS0/AHCLKR0

McBSPs

(Multichannel Buffered Serial Ports)

†

These external pins are applicable to the GDP and ZDP packages only.

NOTE A: On multiplexed pins, bolded text denotes the active function of the pin for that particular peripheral module.

Figure 5. Peripheral Signals (Continued)

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

signal groups description (continued)

(Transmit/Receive Data Pins)

FSR1/AXR0[7]

CLKR1/AXR0[6]

DX1/AXR0[5]

TOUT1/AXR0[4]

TINP0/AXR0[3]

TOUT0/AXR0[2]

DX0/AXR0[1]

8-Serial Ports

Flexible

Partitioning

Tx, Rx, OFF

DR0/AXR0[0]

(Receive Bit Clock)

(Transmit Bit Clock)

CLKX0/ACLKX0

Transmit

Clock

Generator

Receive Clock

Generator

CLKR0/ACLKR0

CLKS0/AHCLKR0

TINP1/AHCLKX0

(Receive Master Clock)

(Transmit Master Clock)

Transmit

Clock Check

Circuit

Receive Clock

Check Circuit

Receive

Frame Sync

Transmit

Frame Sync

FSR0/AFSR0

FSX0/AFSX0

(Receive Frame Sync or

Left/Right Clock)

(Transmit Frame Sync or

Left/Right Clock)

CLKX1/AMUTE0

GP[5](EXT_INT5)/AMUTEIN0

Error Detect

(see Note A)

Auto Mute

Logic

McASP0

(Multichannel Audio Serial Port 0)

NOTES: A. The McASPs’ Error Detect function detects underruns, overruns, early/late frame syncs, DMA errors, and external mute input.

B. On multiplexed pins, bolded text denotes the active function of the pin for that particular peripheral module.

C. Bolded and italicized text within parentheses denotes the function of the pins in an audio system.

Figure 5. Peripheral Signals (Continued)

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

signal groups description (continued)

(Transmit/Receive Data Pins)

HD1/AXR1[7]

HDS1/AXR1[6]

HDS2/AXR1[5]

HD0/AXR1[4]

8-Serial Ports

Flexible

Partitioning

Tx, Rx, OFF

HCNTL0/AXR1[3]

HCS/AXR1[2]

HCNTL1/AXR1[1]

HR/W/AXR1[0]

(Receive Bit Clock)

(Transmit Bit Clock)

HAS/ACLKX1

Transmit

Clock

Generator

Receive Clock

Generator

HRDY/ACLKR1

HD6/AHCLKR1

HD5/AHCLKX1

(Receive Master Clock)

(Transmit Master Clock)

Transmit

Clock Check

Circuit

Receive Clock

Check Circuit

Receive

Frame Sync

Transmit

Frame Sync

HHWIL/AFSR1

HD2/AFSX1

(Receive Frame Sync or

Left/Right Clock)

(Transmit Frame Sync or

Left/Right Clock)

HD3/AMUTE1

Error Detect

(see Note A)

Auto Mute

Logic

GP[4](EXT_INT4)/AMUTEIN1

McASP1

(Multichannel Audio Serial Port 1)

NOTES: A. The McASPs’ Error Detect function detects underruns, overruns, early/late frame syncs, DMA errors, and external mute input.

B. On multiplexed pins, bolded text denotes the active function of the pin for that particular peripheral module.

C. Bolded and italicized text within parentheses denotes the function of the pins in an audio system.

Figure 5. Peripheral Signals (Continued)

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

DEVICE CONFIGURATIONS

On the C6713B device, bootmode and certain device configurations/peripheral selections are determined at

device reset, while other device configurations/peripheral selections are software-configurable via the device

configurations register (DEVCFG) [address location 0x019C0200] after device reset.

device configurations at device reset

Table 18 describes the device configuration pins, which are set up via internal or external pullup/pulldown

resistors through the HPI data pins (HD[4:3], HD8, HD12), and CLKMODE0 pin. These configuration pins must

be in the desired state until reset is released.

For proper device operation, do not oppose the HD [13, 11:9, 7, 1, 0] pins with external pull−ups/pulldowns at

reset.

For more details on these device configuration pins, see the Terminal Functions table and the Debugging

Considerations section of this data sheet.

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

†

Table 18. Device Configurations Pins at Device Reset (HD[4:3], HD8, HD12, and CLKMODE0)

CONFIGURATION

PYP

GDP/ZDP

FUNCTIONAL DESCRIPTION

EMIF Big Endian mode correctness (EMIFBE)

For a C6713BGDP or C6713BZDP:

0

–

The EMIF data will always be presented on the ED[7:0] side of the

bus, regardless of the endianess mode (Little/Big Endian).

In Little Endian mode (HD8 =1), the 8-bit or 16-bit EMIF data will

be present on the ED[7:0] side of the bus.

1

−

In Big Endian mode (HD8 =0), the 8-bit or 16-bit EMIF data will be

present on the ED[31:24] side of the bus [default].

‡

HD12

168

C15

For a C6713BPYP, when Big Endian mode is selected (LENDIAN = 0), for

proper device operation the EMIFBE pin must be externally pulled low.

This new functionality does not affect systems using the current default value

of HD12=1. For more detailed information on the big endian mode

correctness, see the EMIF Big Endian Mode Correctness portion of this data

sheet.

Device Endian mode (LEND)

‡

HD8

160

B17

0

1

–

−

System operates in Big Endian mode

System operates in Little Endian mode (default)

Bootmode Configuration Pins (BOOTMODE)

00 – HPI boot/Emulation boot

01 – CE1 width 8-bit, Asynchronous external ROM boot with default

timings (default mode)

HD[4:3]

(BOOTMODE)

10 − CE1 width 16-bit, Asynchronous external ROM boot with default

timings

156, 154

C19, C20

‡

11 − CE1 width 32-bit, Asynchronous external ROM boot with default

timings

For more detailed information on these bootmode configurations, see the

bootmode section of this data sheet.

Clock generator input clock source select

0

1

–

−

Reserved. Do not use.

CLKIN square wave [default]

CLKMODE0

205

C4

This pin must be pulled to the correct level even after reset.

†

‡

All other HD pins (HD [15, 13, 11:9, 7:5, 2:0]) have pullups/pulldowns (IPUs or IPDs). For proper device operation, do not oppose the HD [13,

11:9, 7, 1, 0] pins with external pull−ups/pulldowns at reset; however, the HD[15, 6, 5, 2] pins can be opposed and driven during reset.

IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors

no greater than 4.4 kΩ and 2.0 kΩ, respectively.]

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

DEVICE CONFIGURATIONS (CONTINUED)

peripheral pin selection at device reset

Some peripherals share the same pins (internally muxed) and are mutually exclusive (i.e., HPI, general-purpose

input/output pins GP[15:8, 3, 1, 0] and McASP1).

D

HPI, McASP1, and GPIO peripherals

The HPI_EN (HD14 pin) is latched at reset. This pin selects whether the HPI peripheral pins or McASP1

peripheral pins and GP[15:8, 3, 1, 0] pins are functionally enabled (see Table 19).

†

Table 19. HPI_EN (HD14 Pin) Peripheral Selection (HPI or McASP1, and Select GPIO Pins)

PERIPHERAL PIN

SELECTION

PERIPHERAL

PINS SELECTED

DESCRIPTION

HPI_EN

(HD14 Pin) [173, C14]

McASP1 and

GP[15:8,3,1,0]

HPI

HPI_EN = 0

HPI pins are disabled; McASP1 peripheral pins and GP[15:8, 3, 1,0] pins

are enabled. All multiplexed HPI/McASP1 and HPI/GPIO pins function as

McASP1 and GPIO pins, respectively. To use the GPIO pins, the

appropriate bits in the GPEN and GPDIR registers need to be

configured.

0

√

HPI_EN = 1

HPI pins are enabled; McASP1 peripheral pins and GP[15:8, 3, 1,0] pins

are disabled [default]. All multiplexed HPI/McASP1 and HPI/GPIO pins

function as HPI pins.

1

√

†

The HPI_EN (HD[14]) pin cannot be controlled via software.

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

DEVICE CONFIGURATIONS (CONTINUED)

peripheral selection/device configurations via the DEVCFG control register

The device configuration register (DEVCFG) allows the user to control the pin availability of the McBSP0,

McBSP1, McASP0, I2C1, and Timer peripherals. The DEVCFG register also offers the user control of the EMIF

input clock source and the timer output pins. For more detailed information on the DEVCFG register control bits,

see Table 20 and Table 21.

Table 20. Device Configuration Register (DEVCFG) [Address location: 0x019C0200 − 0x019C02FF]

31

15

16

†

Reserved

RW-0

4

5

3

2

1

0

†

Reserved

EKSRC

R/W-0

TOUT1SEL

R/W-0

TOUT0SEL

R/W-0

MCBSP0DIS MCBSP1DIS

R/W-0 R/W-0

RW-0

Legend: R/W = Read/Write; -n = value after reset

†

Do not write non-zero values to these bit locations.

Table 21. Device Configuration (DEVCFG) Register Selection Bit Descriptions

BIT #

NAME

DESCRIPTION

31:5

Reserved

Reserved. Do not write non-zero values to these bit locations.

EMIF input clock source bit.

Determines which clock signal is used as the EMIF input clock.

4

3

EKSRC

0

1

=

SYSCLK3 (from the clock generator) is the EMIF input clock source (default)

ECLKIN external pin is the EMIF input clock source

Timer 1 output (TOUT1) pin function select bit.

Selects the pin function of the TOUT1/AXR0[4] external pin independent of the rest of the peripheral

selection bits in the DEVCFG register.

TOUT1SEL

0

1

=

The pin functions as a Timer 1 output (TOUT1) pin (default)

The pin functions as the McASP0 transmit/receive data pin 4 (AXR0[4]).

The Timer 1 module is still active.

Timer 0 output (TOUT0) pin function select bit.

Selects the pin function of the TOUT0/AXR0[2] external pin independent of the rest of the peripheral

selection bits in the DEVCFG register.

2

1

0

TOUT0SEL

MCBSP0DIS

MCBSP1DIS

0

1

=

The pin functions as a Timer 0 output (TOUT0) pin (default)

The pin functions as the McASP0 transmit/receive data pin 2 (AXR0[2]).

The Timer 0 module is still active.

Multichannel Buffered Serial Port 0 (McBSP0) disable bit.

Selects whether McBSP0 or the McASP0 multiplexed peripheral pins are enabled or disabled.

0

=

McBSP0 peripheral pins are enabled, McASP0 peripheral pins (AHCLKR0, ACLKR0,

ACLKX0, AXR0[0], AXR0[1], AFSR0, and AFSX0) are disabled (default).

[If the McASP0 data pins are available, the McASP0 peripheral is functional for DIT

mode only.]

1

=

McBSP0 peripheral pins are disabled, McASP0 peripheral pins (AHCLKR0, ACLKR0,

ACLKX0, AXR0[0], AXR0[1], AFSR0, and AFSX0) are enabled.

Multichannel Buffered Serial Port 1 (McBSP1) disable bit.

Selects whether McBSP1 or I2C1 and McASP0 multiplexed peripheral pins are enabled or disabled.

0

1

=

McBSP1 peripheral pins are enabled, I2C1 peripheral pins (SCL1 and SDA1) and McASP0

peripheral pins (AXR0[7:5] and AMUTE0) are disabled (default)

McBSP1 peripheral pins are disabled, I2C1 peripheral pins (SCL1 and SDA1) and McASP0

peripheral pins (AXR0[7:5] and AMUTE0) are enabled.

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

DEVICE CONFIGURATIONS (CONTINUED)

multiplexed pins

Multiplexed pins are pins that are shared by more than one peripheral and are internally multiplexed. Most of

these pins are configured by software via the device configuration register (DEVCFG), and the others

(specifically, the HPI pins) are configured by external pullup/pulldown resistors only at reset. The muxed pins

that are configured by software can be programmed to switch functionalities at any time. The muxed pins that

are configured by external pullup/pulldown resistors are mutually exclusive; only one peripheral has primary

control of the function of these pins after reset. Table 22 summarizes the peripheral pins affected by the HPI_EN

(HD14 pin) and DEVCFG register. Table 23 identifies the multiplexed pins on the device; shows the default

(primary) function and the default settings after reset; and describes the pins, registers, etc. necessary to

configure the specific multiplexed functions.

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

DEVICE CONFIGURATIONS (CONTINUED)

†

Table 22. Peripheral Pin Selection Matrix

SELECTION BITS

PERIPHERAL PINS AVAILABILITY

B

I

T

G

P

I

B

I

T

I

M

E

R

T

I

M

E

R

M

c

M

c

A

S

P

1

M

c

B

S

P

0

M

c

B

S

P

1

I

E

M

I

H

P

I

O

A

S

P

2

C

0

2

C

1

V

N

A

L

P

I

N

S

F

‡

M

U

E

0

1

AHCLKX1

AHCLKR1

ACLKX1

ACLKR1

AFSX1

GP[0:1],

GP[3],

GP[8:15]

Plus:

0

None

AFSR1

GP[2]

ctrl’d by

GP2EN

bit

HPI_EN

(boot config

pin)

AMUTE1

AXR1[0] to

AXR1[7]

NO

GP[0:1],

GP[3],

GP[8:15]

1

0

None

All

None

All

ACLKX0

ACLKR0

AFSX0

MCBSP0DIS

(DEVCFG bit)

1

AFSR0

None

AHCLKR0

AXR0[0]

AXR0[1]

NO

AMUTE0

AXR0[5]

AXR0[6]

AXR0[7]

0

1

None

All

MCBSP1DIS

(DEVCFG bit)

AMUTE0

AXR0[5]

AXR0[6]

AXR0[7]

None

NO

AXR0[2]

0

1

0

1

0

TOUT0

TOUT0SEL

(DEVCFG bit)

NO

TOUT0

AXR0[2]

NO

AXR0[4]

TOUT1

TOUT1SEL

(DEVCFG bit)

NO

AXR0[4]

TOUT1

ED[7:0];

HD8 = 1/0

HD12 (boot

config pin)

ED[7:0] side

§

[HD8 = 1 (Little)]

ED[31:24] side

[HD8 = 0 (Big)]

1

†

‡

Gray blocks indicate that the peripheral is not affected by the selection bit.

The McASP0 pins AXR0[3] and AHCLKX0 are shared with the timer input pins TINP0 and TINP1, respectively. See Table 23 for more detailed

information.

§

For more detailed information on endianness correction, see the EMIF Big Endian Mode Correctness portion of this data sheet.

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

DEVICE CONFIGURATIONS (CONTINUED)

Table 23. C6713B Device Multiplexed/Shared Pins

MULTIPLEXED PINS

DEFAULT

FUNCTION

DEFAULT SETTING

DESCRIPTION

GDP/

ZDP

NAME

PYP

When the CLKOUT2 pin is enabled,

the CLK2EN bit in the EMIF global

control register (GBLCTL) controls the

CLKOUT2 pin.

GP2EN = 0

CLK2EN = 0: CLKOUT2 held high

CLK2EN = 1: CLKOUT2 enabled

to clock [default]

(GPEN register bit)

GP[2] function disabled,

CLKOUT2 enabled

CLKOUT2/GP[2]

82

Y12 CLKOUT2

To use these software-configurable

GPIO pins, the GPxEN bits in the GP

Enable Register and the GPxDIR bits

in the GP Direction Register must be

properly configured.

GPxEN = 1:

GP[x] pin enabled

No Function

GPxDIR = 0: GP[x] pin is an input

GPxDIR = 1: GP[x] pin is an

output

GPxDIR = 0 (input)

GP5EN = 0 (disabled)

GP4EN = 0 (disabled)

[(GPEN register bits)

GP[x] function disabled]

GP[5](EXT_INT5)/AMUTEIN0

GP[4](EXT_INT4)/AMUTEIN1

6

1

C1

C2

GP[5](EXT_INT5)

GP[4](EXT_INT4)

To use AMUTEIN0/1 pin function, the

GP[5]/GP[4] pins must be configured

as an input, the INEN bit set to 1, and

the polarity through the INPOL bit

selected in the associated McASP

AMUTE register.

CLKS0/AHCLKR0

DR0/AXR0[0]

DX0/AXR0[1]

FSR0/AFSR0

FSX0/AFSX0

CLKR0/ACLKR0

CLKX0/ACLKX0

CLKS1/SCL1

DR1/SDA1

28

27

20

24

21

19

16

8

K3

J1

By default, McBSP0 peripheral pins are

enabled upon reset (McASP0 pins are

disabled).

MCBSP0DIS = 0

H2

J3

(DEVCFG register bit)

McASP0 pins disabled,

McBSP0 pins enabled

McBSP0 pin function

To enable the McASP0 peripheral pins,

the MCBSP0DIS bit in the DEVCFG

register must be set to 1 (disabling the

McBSP0 peripheral pins).

H1

H3

G3

E1

M2

L2

By default, McBSP1 peripheral pins are

enabled upon reset (I2C1 and McASP0

pins are disabled).

37

32

38

36

33

MCBSP1DIS = 0

(DEVCFG register bit)

I2C1 and McASP0 pins

disabled, McBSP1 pins

enabled

DX1/AXR0[5]

FSR1/AXR0[7]

CLKR1/AXR0[6]

CLKX1/AMUTE0

McBSP1 pin function

To enable the I2C1 and McASP0

peripheral pins, the MCBSP1DIS bit in

the DEVCFG register must be set to 1

(disabling the McBSP1 peripheral pins).

M3

M1

L3

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

DEVICE CONFIGURATIONS (CONTINUED)

Table 23. C6713B Device Multiplexed/Shared Pins (Continued)

MULTIPLEXED PINS

DEFAULT

FUNCTION

DEFAULT SETTING

DESCRIPTION

GDP/

ZDP

NAME

PYP

HINT/GP[1]

135

174

173

172

168

167

166

165

160

164

156

152

147

144

146

143

151

150

145

161

159

154

155

139

140

153

J20

B14

C14

A15

C15

A16

B16

C16

B17

A18

C19

D20

E20

G19

G18

G20

E19

F18

F20

C17

B18

C20

D18

H20

H19

E18

HD15/GP[15]

HD14/GP[14]

HD13/GP[13]

HD12/GP[12]

HD11/GP[11]

HD10/GP[10]

HD9/GP[9]

By default, the HPI peripheral pins are

enabled at reset. McASP1 peripheral

pins and eleven GPIO pins are

disabled.

To enable the McASP1 peripheral pins

and the eleven GPIO pins, an external

pulldown resistor must be provided on

the HD14 pin setting HPI_EN = 0 at

reset.

HD8/GP[8]

HD7/GP[3]

HD4/GP[0]

HD1/AXR1[7]

HD0/AXR1[4]

HCNTL1/AXR1[1]

HCNTL0/AXR1[3]

HR/W/AXR1[0]

HDS1/AXR1[6]

HDS2/AXR1[5]

HCS/AXR1[2]

HD6/AHCLKR1

HD5/AHCLKX1

HD3/AMUTE1

HD2/AFSX1

HPI_EN (HD14 pin) = 1

(HPI enabled)

To use these software-configurable

GPIO pins, the GPxEN bits in the GP

Enable Register and the GPxDIR bits in

the GP Direction Register must be

properly configured.

HPI pin function

McASP1 pins and eleven

GPIO pins are disabled.

GPxEN = 1:

GP[x] pin enabled

GPxDIR = 0: GP[x] pin is an input

GPxDIR = 1: GP[x] pin is an

output

McASP1 pin direction is controlled by

the PDIR[x] bits in the McASP1PDIR

register.

HHWIL/AFSR1

HRDY/ACLKR1

HAS/ACLKX1

By default, the Timer 0 input pin is

enabled (and a shared input until the

McASP0 peripheral forces an output).

McASP0PDIR = 0 input, = 1 output

Timer 0 input

function

McASP0PDIR = 0 (input)

[specifically AXR0[3] bit]

TINP0/AXR0[3]

17

G2

By default, the Timer 0 output pin is

enabled.

To enable the McASP0 AXR0[2] pin, the

TOUT0SEL bit in the DEVCFG register

must be set to 1 (disabling the Timer 0

peripheral output pin function).

TOUT0SEL = 0

(DEVCFG register bit)

[TOUT0 pin enabled and

McASP0 AXR0[2] pin

disabled]

Timer 0 output

function

TOUT0/AXR0[2]

18

G1

The AXR2 bit in the McASP0PDIR

register

controls

the

direction

(input/output) of the AXR0[2] pin

McASP0PDIR = 0 input, = 1 output

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

DEVICE CONFIGURATIONS (CONTINUED)

Table 23. C6713B Device Multiplexed/Shared Pins (Continued)

MULTIPLEXED PINS

DEFAULT

FUNCTION

DEFAULT SETTING

DESCRIPTION

GDP/

ZDP

NAME

PYP

By default, the Timer 1 input and

McASP0 clock function are enabled as

inputs.

For the McASP0 clock to function as an

output:

Timer 1 input

function

McASP0PDIR = 0 (input)

[specifically AHCLKX bit]

TINP1/AHCLKX0

12

F2

McASP0PDIR = 1 (specifically the

AHCLKX bit]

By default, the Timer 1 output pin is

enabled.

To enable the McASP0 AXR0[4] pin, the

TOUT1SEL bit in the DEVCFG register

must be set to 1 (disabling the Timer 1

peripheral output pin function).

TOUT1SEL = 0

(DEVCFG register bit)

[TOUT1 pin enabled and

McASP0 AXR0[4] pin

disabled]

Timer 1 output

function

TOUT1/AXR0[4]

13

F1

The AXR4 bit in the McASP0PDIR

register

controls

the

direction

(input/output) of the AXR0[4] pin

McASP0PDIR = 0 input, = 1 output

configuration examples

Figure 6 through Figure 11 illustrate examples of peripheral selections that are configurable on this device.

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

DEVICE CONFIGURATIONS (CONTINUED)

configuration examples (continued)

ED [31:16],

ED[15:0]

32

20

CLKIN, CLKOUT3, CLKMODE0,

PLLHV, TMS, TDO, TDI, TCK,

TRST, EMU[5:3,1,0], RESET,

NMI

Clock,

System,

EMU, and

Reset

EMIF

EA[21:2]

CE[3:0], BE[3:0],

HOLDA, HOLD,

BUSREQ, ECLKIN,

ECLKOUT,

ARE/SDCAS/SSADS,

AWE/SDWE/SSWE,

AOE/SDRAS/SSOE,

ARDY

GP[15:8, 3:1]

GPIO

and

EXT_INT

GP[0],

GP[4](EXT_INT4)/AMUTEIN1,

GP[5](EXT_INT5)/AMUTEIN0,

GP[6](EXT_INT6),

GP[7](EXT_INT7)

HPI

I2C0

SCL0, SDA0

AFSX1, AFSR1, ACLKX1,

ACLKR1, AHCLKR1,

AHCLKX1, AMUTE1

SCL1, SDA1

I2C1

McASP1

McASP0

8

AXR1[7:0]

AXR0[7:0]

{TINP0/AXR0[3]}

McBSP1

AMUTE0,

TINP1/AHCLKX0,

AHCLKR0,

ACLKR0,

ACLKX0, AFSR0,

AFSX0

TIMER0

TIMER1

McBSP0

Shading denotes a peripheral module not available for this configuration.

DEVCFG Register Value:

0x0000 000F

HPI_EN(HD14) = 0

GP2EN BIT = 1 (enabling GPEN.[2])

MCBSP0DIS = 1

MCBSP1DIS = 1

TOUT0SEL = 1

TOUT1SEL = 1

EKSRC = 0

Figure 6. Configuration Example A (2 I2C + 2 McASP + GPIO)

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

DEVICE CONFIGURATIONS (CONTINUED)

configuration examples (continued)

32

20

ED [31:16],

ED[15:0]

CLKIN, CLKOUT3, CLKMODE0,

PLLHV, TMS, TDO, TDI, TCK,

TRST, EMU[5:3,1,0], RESET,

NMI

Clock,

System,

EMU, and

Reset

EA[21:2]

EMIF

CE[3:0], BE[3:0],

HOLDA, HOLD,

BUSREQ, ECLKIN,

ECLKOUT,

GP[15:8, 3:1]

ARE/SDCAS/SSADS,

AWE/SDWE/SSWE,

AOE/SDRAS/SSOE,

ARDY

GPIO

and

EXT_INT

GP[0],

GP[4](EXT_INT4)/AMUTEIN1,

GP[5](EXT_INT5)/AMUTEIN0,

GP[6](EXT_INT6),

GP[7](EXT_INT7)

HPI

I2C0

SCL0, SDA0

AFSX1, AFSR1, ACLKX1,

ACLKR1, AHCLKR1,

AHCLKX1, AMUTE1

I2C1

McASP1

McASP0

8

5

AXR1[7:0]

AXR0[4:0]

{TINP0/AXR0[3]}

DR1, CLKS1,

CLKR1, CLKX1,

FSR1, DX1,

FSX1

McBSP1

TINP1/AHCLKX0,

AHCLKR0,

ACLKR0,

ACLKX0, AFSR0,

AFSX0

TIMER0

TIMER1

McBSP0

Shading denotes a peripheral module not available for this configuration.

DEVCFG Register Value:

0x0000 000E

HPI_EN(HD14) = 0

GP2EN BIT = 1 (enabling GPEN.[2])

MCBSP0DIS = 1

MCBSP1DIS = 0

TOUT0SEL = 1

TOUT1SEL = 1

EKSRC = 0

Figure 7. Configuration Example B (1 I2C + 1 McBSP + 2 McASP + GPIO)

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

DEVICE CONFIGURATIONS (CONTINUED)

configuration examples (continued)

32

20

ED [31:16],

ED[15:0]

CLKIN, CLKOUT3, CLKMODE0,

PLLHV, TMS, TDO, TDI, TCK,

TRST, EMU[5:3,1,0], RESET,

NMI

Clock,

System,

EMU, and

Reset

EA[21:2]

EMIF

CE[3:0], BE[3:0],

HOLDA, HOLD,

BUSREQ, ECLKIN,

ECLKOUT,

GP[15:8, 3:1]

ARE/SDCAS/SSADS,

AWE/SDWE/SSWE,

AOE/SDRAS/SSOE,

ARDY

GPIO

and

EXT_INT

GP[0],

GP[4](EXT_INT4)/AMUTEIN1,

GP[5](EXT_INT5)/AMUTEIN0,

GP[6](EXT_INT6),

GP[7](EXT_INT7)

HPI

I2C0

SCL0, SDA0

AFSX1, AFSR1, ACLKX1,

ACLKR1, AHCLKR1,

AHCLKX1, AMUTE1

SCL1, SDA1

I2C1

McASP1

8

6

AXR1[7:0]

AXR0[7:2]

{TINP0/AXR0[3]}

McASP0

McBSP1

(DIT Mode)

AMUTE0,

TINP1/AHCLKX0

TIMER0

TIMER1

McBSP0

DR0, CLKS0,

CLKR0, CLKX0,

FSR0, DX0,

FSX0

Shading denotes a peripheral module not available for this configuration.

DEVCFG Register Value:

0x0000 000D

HPI_EN(HD14) = 0

GP2EN BIT = 1 (enabling GPEN.[2])

MCBSP0DIS = 0

MCBSP1DIS = 1

TOUT0SEL = 1

TOUT1SEL = 1

EKSRC = 0

Figure 8. Configuration Example C [2 I2C + 1 McBSP + 1 McASP + 1 McASP (DIT) + GPIO]

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

DEVICE CONFIGURATIONS (CONTINUED)

configuration examples (continued)

32

20

ED [31:16],

ED[15:0]

CLKIN, CLKOUT3, CLKMODE0,

PLLHV, TMS, TDO, TDI, TCK,

TRST, EMU[5:3,1,0], RESET,

NMI

Clock,

System,

EMU, and

Reset

EA[21:2]

EMIF

CE[3:0], BE[3:0],

HOLDA, HOLD,

BUSREQ, ECLKIN,

ECLKOUT,

ARE/SDCAS/SSADS,

AWE/SDWE/SSWE,

AOE/SDRAS/SSOE,

ARDY

GP[15:8, 3:1]

GPIO

and

EXT_INT

GP[0],

GP[4](EXT_INT4)/AMUTEIN1,

GP[5](EXT_INT5)/AMUTEIN0,

GP[6](EXT_INT6),

GP[7](EXT_INT7)

HPI

I2C0

SCL0, SDA0

AFSX1, AFSR1, ACLKX1,

ACLKR1, AHCLKR1,

AHCLKX1, AMUTE1

I2C1

McASP1

8

3

AXR1[7:0]

AXR0[4:2]

{TINP0/AXR0[3]}

McASP0

McBSP1

(DIT Mode)

DR1, CLKS1,

CLKR1, CLKX1,

FSR1, DX1,

FSX1

TINP1/AHCLKX0

TOUT0/AXR0[2]

TIMER0

TIMER1

McBSP0

DR0, CLKS0,

CLKR0, CLKX0,

FSR0, DX0,

FSX0

TOUT1/AXR0[4]

Shading denotes a peripheral module not available for this configuration.

DEVCFG Register Value:

0x0000 000C

HPI_EN(HD14) = 0

GP2EN BIT = 1 (enabling GPEN.[2])

MCBSP0DIS = 0

MCBSP1DIS = 0

TOUT0SEL = 1

TOUT1SEL = 1

EKSRC = 0

Figure 9. Configuration Example D [1 I2C + 2 McBSP + 1 McASP + 1 McASP (DIT) + GPIO + Timers]

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

DEVICE CONFIGURATIONS (CONTINUED)

configuration examples (continued)

32

20

CLKIN, CLKOUT3, CLKMODE0,

PLLHV, TMS, TDO, TDI, TCK,

TRST, EMU[5:3,1,0], RESET,

NMI

ED [31:16],

ED[15:0]

Clock,

System,

EMU, and

Reset

EA[21:2]

EMIF

CE[3:0], BE[3:0],

HOLDA, HOLD,

BUSREQ, ECLKIN,

ECLKOUT,

CLKOUT2

ARE/SDCAS/SSADS,

AWE/SDWE/SSWE,

AOE/SDRAS/SSOE,

ARDY

GPIO

and

EXT_INT

GP[4](EXT_INT4)/AMUTEIN1,

GP[5](EXT_INT5)/AMUTEIN0,

GP[6](EXT_INT6),

GP[7](EXT_INT7)

16

HD[15:0]

HPI

I2C0

SCL0, SDA0

HINT, HHWIL,

HRDY, HR/W,

HCNTRL1,

HCNTRL0, HCS,

HDS2, HDS1,

HAS

I2C1

McASP1

McASP0

SCL1, SDA1

8

AXR0[7:0],

{TINP0/AXR0[3]}

McBSP1

AMUTE0,

TINP1/AHCLKX0,

AHCLKR0,

ACLKR0,

ACLKX0, AFSR0,

AFSX0

TIMER0

TIMER1

McBSP0

Shading denotes a peripheral module not available for this configuration.

DEVCFG Register Value:

0x0000 000F

HPI_EN(HD14) = 1

GP2EN BIT = 0 (enabling GPEN.[2])

MCBSP0DIS = 1

MCBSP1DIS = 1

TOUT0SEL = 1

TOUT1SEL = 1

EKSRC = 0

Figure 10. Configuration Example E (1 I2C + HPI + 1 McASP)

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

DEVICE CONFIGURATIONS (CONTINUED)

configuration examples (continued)

32

20

CLKIN, CLKOUT3, CLKMODE0,

PLLHV, TMS, TDO, TDI, TCK,

TRST, EMU[5:3,1,0], RESET,

NMI

ED [31:16],

ED[15:0]

Clock,

System,

EMU, and

Reset

EA[21:2]

EMIF

CE[3:0], BE[3:0],

HOLDA, HOLD,

BUSREQ, ECLKIN,

ECLKOUT,

CLKOUT2

ARE/SDCAS/SSADS,

AWE/SDWE/SSWE,

AOE/SDRAS/SSOE,

ARDY

GPIO

and

EXT_INT

GP[4](EXT_INT4)/AMUTEIN1,

GP[5](EXT_INT5)/AMUTEIN0,

GP[6](EXT_INT6),

GP[7](EXT_INT7)

16

HD[15:0]

I2C0

HPI

SCL0, SDA0

HINT, HHWIL,

HRDY, HR/W,

HCNTRL1,

HCNTRL0, HCS,

HDS2, HDS1,

HAS

I2C1

McASP1

McASP0

5

AXR0[4:0]

{TINP0/AXR0[3]}

DR1, CLKS1,

CLKR1, CLKX1,

FSR1, DX1,

FSX1

McBSP1

TINP1/AHCLKX0,

AHCLKR0,

ACLKR0,

ACLKX0, AFSR0,

AFSX0

TIMER0

TIMER1

McBSP0

Shading denotes a peripheral module not available for this configuration.

DEVCFG Register Value:

0x0000 000E

HPI_EN(HD14) = 1

GP2EN BIT = 0 (enabling GPEN.[2])

MCBSP0DIS = 1

MCBSP1DIS = 0

TOUT0SEL = 1

TOUT1SEL = 1

EKSRC = 0

Figure 11. Configuration Example F (1 McBSP + HPI + 1 McASP)

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

DEVICE CONFIGURATIONS (CONTINUED)

debugging considerations

It is recommended that external connections be provided to peripheral selection/device configuration pins,

including HD[14, 8, 12, 4, 3], and CLKMODE0. Although internal pullup resistors exist on these pins, providing

external connectivity adds convenience to the user in debugging and flexibility in switching operating modes.

Internal pullup/pulldown resistors also exist on the non-configuration pins on the HPI data bus and HD[15, 13,

11:9, 7:5, 2:0]. For proper device operation, do not oppose the HD [13, 11:9, 7, 1, 0] pins with external

pull−ups/pulldowns at reset. If an external controller provides signals to these HD[13, 11:9, 7, 1, 0]

non-configuration pins, these signals must be driven to the default state of the pins at reset, or not be driven

at all. For a list of routed out, 3-stated, or not-driven pins recommended for external pullup/pulldown resistors,

and internal pullup/pulldown resistors for all device pins, etc., see the Terminal Functions table. However, the

HD[15, 6, 5, 2] non-configuration pins can be opposed and driven during reset.

47

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

TERMINAL FUNCTIONS

The terminal functions table identifies the external signal names, the associated pin (ball) numbers along with

the mechanical package designator, the pin type (I, O/Z, or I/O/Z), whether the pin has any internal

pullup/pulldown resistors and a functional pin description. For more detailed information on device

configuration, peripheral selection, multiplexed/shared pins, and debugging considerations, see the Device

Configurations section of this data sheet.

Terminal Functions

SIGNAL

NAME

PIN NO.

IPD/

IPU‡

†

DESCRIPTION

GDP/

TYPE

PYP

ZDP

CLOCK/PLL CONFIGURATION

CLKIN

204

82

A3

I

IPD

Clock Input

Clock output at half of device speed (O/Z) [default] (SYSCLK2 internal signal

from the clock generator) or this pin can be programmed as GP[2] pin (I/O/Z)

CLKOUT2/GP[2]

CLKOUT3

Y12

D10

O/Z

O

184

Clock output programmable by OSCDIV1 register in the PLL controller.

Clock generator input clock source select

0

1

−

–

Reserved, do not use.

CLKIN square wave [default]

CLKMODE0

PLLHV

205

202

C4

C5

I

IPU

For proper device operation, this pin must be either left unconnected or

externally pulled up with a 1-kΩ resistor.

A

Analog power (3.3 V) for PLL (PLL Filter)

JTAG EMULATION

TMS

TDO

TDI

192

187

191

193

B7

A8

A7

A6

I

IPU

JTAG test-port mode select

JTAG test-port data out

O/Z

I

JTAG test-port data in

TCK

JTAG test-port clock

JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see the IEEE 1149.1

JTAG Compatibility Statement section of this data sheet.

§

TRST

197

B6

I

IPD

EMU5

EMU4

EMU3

EMU2

—

B12

C11

B10

D3

I/O/Z

IPU

Emulation pin 5. Reserved for future use, leave unconnected.

Emulation pin 4. Reserved for future use, leave unconnected.

Emulation pin 3. Reserved for future use, leave unconnected.

Emulation pin 2. Reserved for future use, leave unconnected.

Emulation [1:0] pins

•

Select the device functional mode of operation

EMU[1:0]

Operation

00

01

10

11

Boundary Scan/Functional Mode (see Note)

Reserved

Emulation/Functional Mode [default] (see the IEEE 1149.1

JTAG Compatibility Statement section of this data sheet)

EMU1

EMU0

185

186

B9

D9

I/O/Z

IPU

The DSP can be placed in Functional mode when the EMU[1:0] pins are

configured for either Boundary Scan or Emulation.

Note: When the EMU[1:0] pins are configured for Boundary Scan mode, the

internal pulldown (IPD) on the TRST signal must not be opposed in order to

operate in Functional mode.

For the Boundary Scan mode drive EMU[1:0] and RESET pins low.

†

‡

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal

IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors

no greater than 4.4 kΩ and 2.0 kΩ, respectively.]

§

To ensure a proper logic level during reset when these pins are both routed out and 3−stated or not driven, it is recommended to include an

external 10 kΩ pullup/pulldown resistor to sustain the IPU/IPD, respectively.

48

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

Terminal Functions (Continued)

SIGNAL

NAME

PIN NO.

IPD/

IPU‡

†

DESCRIPTION

GDP/

TYPE

PYP

ZDP

RESETS AND INTERRUPTS

Device reset. When using Boundary Scan mode, drive the EMU[1:0] and

RESET pins low. For this device, this pin does not have an IPU.

RESET

176

A13

I

—

Nonmaskable interrupt

•

Edge-driven (rising edge)

Any noise on the NMI pin may trigger an NMI interrupt; therefore, if the NMI pin is

not used, it is recommended that the NMI pin be grounded versus relying on the

IPD.

NMI

175

C13

IPD

General-purpose input/output pins (I/O/Z) which also function as external

interrupts

GP[7](EXT_INT7)

GP[6](EXT_INT6)

7

2

E3

D2

•

Edge-driven

Polarity independently selected via the External Interrupt Polarity Register

bits (EXTPOL.[3:0]), in addition to the GPIO registers.

GP[5](EXT_INT5)/

AMUTEIN0

I/O/Z

IPU

6

1

C1

C2

GP[4] and GP[5] pins also function as AMUTEIN1 McASP1 mute input and

AMUTEIN0 McASP0 mute input, respectively, if enabled by the INEN bit in the

associated McASP AMUTE register.

GP[4](EXT_INT4)/

AMUTEIN1

HOST-PORT INTERFACE (HPI)

Host interrupt (from DSP to host) (O) [default] or this pin can be programmed as

a GP[1] pin (I/O/Z).

HINT/GP[1]

135

144

146

J20

G19

G18

O/Z

IPU

Host control − selects between control, address, or data registers (I) [default] or

McASP1 data pin 1 (I/O/Z).

HCNTL1/AXR1[1]

HCNTL0/AXR1[3]

I

Host control − selects between control, address, or data registers (I) [default] or

McASP1 data pin 3 (I/O/Z).

Host half-word select − first or second half-word (not necessarily high or low

order) (I) [default] or McASP1 receive frame sync or left/right clock (LRCLK)

(I/O/Z).

HHWIL/AFSR1

HR/W/AXR1[0]

139

143

H20

G20

I

IPU

Host read or write select (I) [default] or McASP1 data pin 0 (I/O/Z).

†

‡

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal

IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors

no greater than 4.4 kΩ and 2.0 kΩ, respectively.]

49

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

Terminal Functions (Continued)

SIGNAL

NAME

PIN NO.

GDP/

IPD/

IPU‡

†

DESCRIPTION

TYPE

PYP

174

173

172

168

167

166

165

160

164

ZDP

HOST-PORT INTERFACE (HPI) (CONTINUED)

Host-port data pins (I/O/Z) [default] or general-purpose input/output pins

(I/O/Z)

HD15/GP[15]

B14

IPU

•

Used for transfer of data, address, and control

Also controls initialization of DSP modes at reset via pullup/pulldown

resistors

− Device Endian Mode (HD8)

§

HD14/GP[14]

HD13/GP[13]

HD12/GP[12]

HD11/GP[11]

HD10/GP[10]

HD9/GP[9]

C14

A15

C15

A16

B16

C16

B17

A18

0

1

–

−

Big Endian

Little Endian

For a C6713BGDP or C6713BZDP:

− Big Endian Mode Correctness EMIFBE (HD12)

§

0

–

The EMIF data will always be presented on the ED[7:0] side of the

bus, regardless of the endianess mode (Little/Big Endian).

In Little Endian mode (HD8 =1), the 8-bit or 16-bit EMIF data will be

present on the ED[7:0] side of the bus.

In Big Endian mode (HD8 =0), the 8-bit or 16-bit EMIF data will be

present on the ED[31:24] side of the bus [default].

1

−

For a C6713BPYP, when Big Endian mode is selected (LENDIAN = 0), for

proper device operation the EMIFBE pin must be externally pulled low.

This new functionality does not affect systems using the current default value of

HD12=1. For more detailed information on the big endian mode correctness,

see the EMIF Big Endian Mode Correctness portion of this data

sheet.

I/O/Z

− Bootmode (HD[4:3])

00 – HPI boot/Emulation boot

01 – CE1 width 8-bit, Asynchronous external ROM boot with default

timings (default mode)

10 − CE1 width 16-bit, Asynchronous external ROM boot with default

timings

11 − CE1 width 32-bit, Asynchronous external ROM boot with default

timings

− HPI_EN (HD14)

0

1

§

HD8/GP[8]

–

−

HPI disabled, McASP1 enabled

HPI enabled, McASP1 disabled (default)

Other HD pins HD [13, 11:9, 7:5, 2:0] have pullups/pulldowns (IPUs/IPDs). For

proper device operation, do not oppose the HD [13, 11:9, 7, 1, 0] pins with exter-

nal pull−ups/pulldowns at reset; however, the HD[15, 6, 5, 2] pins can be op-

posed and driven at reset. For more details, see the Device Configurations

section of this data sheet.

HD7/GP[3]

†

‡

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal

IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors

no greater than 4.4 kΩ and 2.0 kΩ, respectively.]

§

To ensure a proper logic level during reset when these pins are both routed out and 3−stated or not driven, it is recommended to include an

external 10 kΩ pullup/pulldown resistor to sustain the IPU/IPD, respectively.

50

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

Terminal Functions (Continued)

SIGNAL

NAME

PIN NO.

IPD/

IPU‡

†

DESCRIPTION

GDP/

TYPE

PYP

ZDP

HOST-PORT INTERFACE (HPI) (CONTINUED)

Host-port data pin 6 (I/O/Z) [ default] or McASP1 receive high-frequency master

clock (I/O/Z).

HD6/AHCLKR1

HD5/AHCLKX1

161

159

C17

B18

IPU

I/O/Z

Host-port data pin 5 (I/O/Z) [ default] or McASP1 transmit high-frequency master

clock (I/O/Z).

Host-port data pin 4 (I/O/Z) [ default] or this pin can be programmed as a GP[0]

pin (I/O/Z).

§

HD4/GP[0]

156

154

155

C19

C20

D18

IPD

IPU

§

HD3/AMUTE1

Host-port data pin 3 (I/O/Z) [ default] or McASP1 mute output (O/Z).

Host-port data pin 2 (I/O/Z) [ default] or McASP1 transmit frame sync or left/right

clock (LRCLK) (I/O/Z).

HD2/AFSX1

I/O/Z

HD1/AXR1[7]

HD0/AXR1[4]

HAS/ACLKX1

HCS/AXR1[2]

152

147

153

145

151

150

140

D20

E20

E18

F20

E19

F18

H19

IPU

IPD

Host-port data pin 1 (I/O/Z) [ default] or McASP1 data pin 7 (I/O/Z).

Host-port data pin 0 (I/O/Z) [ default] or McASP1 data pin 4 (I/O/Z).

Host address strobe (I) [default] or McASP1 transmit bit clock (I/O/Z).

Host chip select (I) [default] or McASP1 data pin 2 (I/O/Z).

I/O/Z

I

HDS1/AXR1[6]

HDS2/AXR1[5]

HRDY/ACLKR1

I

Host data strobe 1 (I) [default] or McASP1 data pin 6 (I/O/Z).

Host data strobe 2 (I) [default] or McASP1 data pin 5 (I/O/Z) .

Host ready (from DSP to host) (O) [default] or McASP1 receive bit clock (I/O/Z).

O/Z

¶

EMIF − COMMON SIGNALS TO ALL TYPES OF MEMORY

CE3

CE2

CE1

CE0

BE3

BE2

BE1

BE0

57

61

V6

W6

W18

V17

V5

O/Z

IPU

Memory space enables

•

Enabled by bits 28 through 31 of the word address

Only one asserted during any external data access

103

102

—

Byte-enable control

—

Y4

•

Decoded from the two lowest bits of the internal address

Byte-write enables for most types of memory

Can be directly connected to SDRAM read and write mask signal (SDQM)

108

110

U19

V20

¶

EMIF − BUS ARBITRATION

HOLDA

HOLD

137

138

136

J18

J17

J19

O/Z

I

IPU

Hold-request-acknowledge to the host

Hold request from the host

Bus request output

BUSREQ

O/Z

†

‡

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal

IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors

no greater than 4.4 kΩ and 2.0 kΩ, respectively.]

To ensure a proper logic level during reset when these pins are both routed out and 3−stated or not driven, it is recommended to include an

external 10 kΩ pullup/pulldown resistor to sustain the IPU/IPD, respectively.

§

¶

To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

Terminal Functions (Continued)

SIGNAL

NAME

PIN NO.

IPD/

†

TYPE

DESCRIPTION

GDP/

ZDP

‡

IPU

PYP

¶

EMIF − ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL

ECLKIN

78

Y11

I

IPD

External EMIF input clock source

EMIF output clock depends on the EKSRC bit (DEVCFG.[4]) and on EKEN bit

(GBLCTL.[5]).

EKSRC = 0

–

ECLKOUT is based on the internal SYSCLK3 signal

from the clock generator (default).

ECLKOUT

77

Y10

O/Z

IPD

EKSRC = 1

–

ECLKOUT is based on the the external EMIF input clock

source pin (ECLKIN)

EKEN = 0

EKEN = 1

–

ECLKOUT held low

ECLKOUT enabled to clock (default)

ARE/SDCAS/

SSADS

Asynchronous memory read enable/SDRAM column-address strobe/SBSRAM

address strobe

79

75

V11

O/Z

IPU

AOE/SDRAS/

SSOE

Asynchronous memory output enable/SDRAM row-address strobe/SBSRAM

output enable

W10

AWE/SDWE/

SSWE

Asynchronous memory write enable/SDRAM write enable/SBSRAM write

enable

83

56

V12

Y5

O/Z

I

IPU

ARDY

Asynchronous memory ready input

¶

EMIF − ADDRESS

EA21

EA20

EA19

EA18

EA17

109

101

100

95

U18

Y18

W17

Y16

V16

99

EA16

EA15

EA14

EA13

EA12

EA11

EA10

EA9

92

94

90

91

93

86

76

74

71

70

69

68

64

63

62

Y15

W15

Y14

W14

V14

W13

V10

Y9

EMIF external address

Note: EMIF address numbering for the C6713BPYP device

starts with EA2 to maintain signal name compatibility with other C671x devices

(e.g., C6711, C6713BGDP and C6713BZDP) [see the 32-bit EMIF addressing

scheme in the TMS320C6000 DSP External Memory Interface (EMIF)

Reference Guide (literature number SPRU266)].

O/Z

IPU

EA8

V9

EA7

Y8

EA6

W8

V8

EA5

EA4

W7

V7

EA3

EA2

Y6

†

‡

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal

IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors

no greater than 4.4 kΩ and 2.0 kΩ, respectively.]

¶

To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.

52

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

Terminal Functions (Continued)

SIGNAL

NAME

PIN NO.

IPD/

†

TYPE

DESCRIPTION

GDP/

IPU‡

PYP

ZDP

¶

EMIF − DATA

ED31

ED30

ED29

ED28

ED27

ED26

ED25

ED24

ED23

ED22

ED21

ED20

ED19

ED18

ED17

ED16

ED15

ED14

ED13

ED12

ED11

ED10

ED9

—

N3

P3

—

P2

—

P1

—

R2

—

R3

—

T2

—

T1

—

U3

—

U1

—

U2

—

V1

—

V2

—

Y3

—

W4

V4

—

I/O/Z

IPU

External data pins (ED[31:16] pins applicable to GDP and ZDP packages only)

112

113

111

118

117

120

119

123

122

121

128

127

129

130

131

132

T19

T20

T18

R20

R19

P20

P18

N20

N19

N18

M20

M19

L19

L18

K19

K18

ED8

ED7

ED6

ED5

ED4

ED3

ED2

ED1

ED0

†

‡

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal

IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors

no greater than 4.4 kΩ and 2.0 kΩ, respectively.]

¶

To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.

53

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

Terminal Functions (Continued)

IPD/

†

SIGNAL

PIN NO.

DESCRIPTION

TYPE

IPU‡

MULTICHANNEL AUDIO SERIAL PORT 1 (McASP1)

GP[4](EXT_INT4)/

AMUTEIN1

General-purpose input/output pin 4 and external interrupt 4 (I/O/Z) [default] or

McASP1 mute input (I/O/Z).

1

C2

I/O/Z

IPU

HD3/AMUTE1

154

140

C20

H19

I/O/Z

IPU

IPD

Host-port data pin 3 (I/O/Z) [ default] or McASP1 mute output (O/Z).

HRDY/ACLKR1

Host ready (from DSP to host) (O) [default] or McASP1 receive bit clock (I/O/Z).

Host-port data pin 6 (I/O/Z) [ default] or McASP1 receive high-frequency master

clock (I/O/Z).

HD6/AHCLKR1

HAS/ACLKX1

HD5/AHCLKX1

161

153

159

C17

E18

B18

I/O/Z

IPU

Host address strobe (I) [default] or McASP 1 transmit bit clock (I/O/Z).

Host-port data pin 5 (I/O/Z) [ default] or McASP1 transmit high-frequency

master clock (I/O/Z).

Host half-word select − first or second half-word (not necessarily high or low

order) (I) [default] or McASP1 receive frame sync or left/right clock (LRCLK)

(I/O/Z).

HHWIL/AFSR1

139

H20

I/O/Z

IPU

Host-port data pin 2 (I/O/Z) [ default] or McASP1 transmit frame sync or left/

right clock (LRCLK) (I/O/Z).

HD2/AFSX1

155

D18

I/O/Z

IPU

HD1/AXR1[7]

HDS1/AXR1[6]

HDS2/AXR1[5]

HD0/AXR1[4]

152

151

150

147

D20

E19

F18

E20

I/O/Z

IPU

Host-port data pin 1 (I/O/Z) [ default] or McASP1 TX/RX data pin 7 (I/O/Z).

Host data strobe 1 (I) [default] or McASP1 TX/RX data pin 6 (I/O/Z).

Host data strobe 2 (I) [default] or McASP1 TX/RX data pin 5 (I/O/Z).

Host-port data pin 0 (I/O/Z) [ default] or McASP1 TX/RX data pin 4 (I/O/Z).

Host control − selects between control, address, or data registers (I) [default] or

McASP1 TX/RX data pin 3 (I/O/Z).

HCNTL0/AXR1[3]

HCS/AXR1[2]

146

145

144

143

G18

F20

G19

G20

I/O/Z

IPU

Host chip select (I) [default] or McASP1 TX/RX data pin 2 (I/O/Z).

Host control − selects between control, address, or data registers (I) [default] or

McASP1 TX/RX data pin 1 (I/O/Z).

HCNTL1/AXR1[1]

HR/W/AXR1[0]

Host read or write select (I) [default] or McASP1 TX/RX data pin 0 (I/O/Z).

MULTICHANNEL AUDIO SERIAL PORT 0 (McASP0)

GP[5](EXT_INT5)/

AMUTEIN0

General-purpose input/output pin 5 and external interrupt 5 (I/O/Z) [default] or

McASP0 mute input (I/O/Z).

6

C1

I/O/Z

IPU

CLKX1/AMUTE0

CLKR0/ACLKR0

33

19

L3

I/O/Z

IPD

McBSP1 transmit clock (I/O/Z) [default] or McASP0 mute output (O/Z).

McBSP0 receive clock (I/O/Z) [default] or McASP0 receive bit clock (I/O/Z).

H3

Timer 1 input (I) or McASP0 transmit high−frequency master clock (I/O/Z). This

pin defaults as Timer 1 input (I) and McASP transmit high−frequency master

clock input (I).

TINP1/AHCLKX0

12

F2

I/O/Z

IPD

CLKX0/ACLKX0

16

28

G3

K3

I/O/Z

IPD

McBSP0 transmit clock (I/O/Z) [default] or McASP0 transmit bit clock (I/O/Z).

McBSP0 external clock source (as opposed to internal) (I) [default] or McASP0

receive high-frequency master clock (I/O/Z).

CLKS0/AHCLKR0

McBSP0 receive frame sync (I/O/Z) [default] or McASP0 receive frame sync or

left/right clock (LRCLK) (I/O/Z).

FSR0/AFSR0

FSX0/AFSX0

FSR1/AXR0[7]

24

21

38

J3

H1

M3

I/O/Z

IPD

McBSP0 transmit frame sync (I/O/Z) [default] or McASP0 transmit frame sync

or left/right clock (LRCLK) (I/O/Z).

McBSP1 receive frame sync (I/O/Z) [default] or McASP0 TX/RX data pin 7

(I/O/Z).

†

‡

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal

IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors

no greater than 4.4 kΩ and 2.0 kΩ, respectively.]

54

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

Terminal Functions (Continued)

SIGNAL

NAME

PIN NO.

IPD/

†

TYPE

DESCRIPTION

GDP/

ZDP

IPU‡

PYP

MULTICHANNEL AUDIO SERIAL PORT 0 (McASP0) (CONTINUED)

CLKR1/AXR0[6]

DX1/AXR0[5]

36

32

13

17

18

20

27

M1

L2

I/O/Z

IPD

IPU

IPD

IPU

McBSP1 receive clock (I/O/Z) [default] or McASP0 TX/RX data pin 6 (I/O/Z).

McBSP1 transmit data (O/Z) [default] or McASP0 TX/RX data pin 5 (I/O/Z).

Timer 1 output (O) [default] or McASP0 TX/RX data pin 4 (I/O/Z).

Timer 0 input (I) [default] or McASP0 TX/RX data pin 3 (I/O/Z).

Timer 0 output (O) [default] or McASP0 TX/RX data pin 2 (I/O/Z).

McBSP0 transmit data (O/Z) [default] or McASP0 TX/RX data pin 1 (I/O/Z).

McBSP0 receive data (I) [default] or McASP0 TX/RX data pin 0 (I/O/Z).

TIMER 1

TOUT1/AXR0[4]

TINP0/AXR0[3]

TOUT0/AXR0[2]

DX0/AXR0[1]

F1

G2

G1

H2

J1

DR0/AXR0[0]

TOUT1/AXR0[4]

TINP1/AHCLKX0

13

12

F1

F2

O

I

IPD

Timer 1 output (O) [default] or McASP0 TX/RX data pin 4 (I/O/Z).

Timer 1 input (I) or McASP0 transmit high−frequency master clock (I/O/Z). This

pin defaults as Timer 1 input (I) and McASP transmit high−frequency master

clock input (I).

TIMER0

TOUT0/AXR0[2]

TINP0/AXR0[3]

18

17

G1

G2

O

I

IPD

Timer 0 output (O) [default] or McASP0 TX/RX data pin 2 (I/O/Z).

Timer 0 input (I) [default] or McASP0 TX/RX data pin 3 (I/O/Z).

MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)

McBSP1 external clock source (as opposed to internal) (I) [default] or I2C1

clock (I/O/Z).

This pin does not have an internal pullup or pulldown. When this pin is used as a

McBSP pin, this pin should either be driven externally at all times or be pulled up

with a 10-kΩ resistor to a valid logic level. Because it is common for some ICs to

3-state their outputs at times, a 10-kΩ pullup resistor may be desirable even

when an external device is driving the pin.

CLKS1/SCL1

8

E1

I

—

CLKR1/AXR0[6]

CLKX1/AMUTE0

36

33

M1

L3

I/O/Z

IPD

McBSP1 receive clock (I/O/Z) [default] or McASP0 TX/RX data pin 6 (I/O/Z).

McBSP1 transmit clock (I/O/Z) [default] or McASP0 mute output (O/Z).

McBSP1 receive data (I) [default] or I2C1 data (I/O/Z).

This pin does not have an internal pullup or pulldown. When this pin is used as a

McBSP pin, this pin should either be driven externally at all times or be pulled up

with a 10-kΩ resistor to a valid logic level. Because it is common for some ICs to

3-state their outputs at times, a 10-kΩ pullup resistor may be desirable even

when an external device is driving the pin.

DR1/SDA1

37

M2

I

—

DX1/AXR0[5]

FSR1/AXR0[7]

FSX1

32

38

31

L2

M3

L1

O/Z

I/O/Z

IPU

IPD

McBSP1 transmit data (O/Z) [default] or McASP0 TX/RX data pin 5 (I/O/Z).

McBSP1 receive frame sync (I/O/Z) [default] or McASP0 TX/RX data pin 7

(I/O/Z).

McBSP1 transmit frame sync

†

‡

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal

IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors

no greater than 4.4 kΩ and 2.0 kΩ, respectively.]

55

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

Terminal Functions (Continued)

SIGNAL

NAME

PIN NO.

IPD/

IPU‡

†

DESCRIPTION

GDP/

TYPE

PYP

ZDP

MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)

McBSP0 external clock source (as opposed to internal) (I) [default] or McASP0

receive high-frequency master clock (I/O/Z).

CLKS0/AHCLKR0

28

K3

I

IPD

CLKR0/ACLKR0

CLKX0/ACLKX0

DR0/AXR0[0]

19

16

27

20

H3

G3

J1

I/O/Z

I

IPD

IPU

McBSP0 receive clock (I/O/Z) [default] or McASP0 receive bit clock (I/O/Z).

McBSP0 transmit clock (I/O/Z) [default] or McASP0 transmit bit clock (I/O/Z).

McBSP0 receive data (I) [default] or McASP0 TX/RX data pin 0 (I/O/Z).

McBSP0 transmit data (O/Z) [default] or McASP0 TX/RX data pin 1 (I/O/Z).

DX0/AXR0[1]

H2

O/Z

McBSP0 receive frame sync (I/O/Z) [default] or McASP0 receive frame sync or

left/right clock (LRCLK) (I/O/Z).

FSR0/AFSR0

FSX0/AFSX0

24

21

J3

I/O/Z

IPD

McBSP0 transmit frame sync (I/O/Z) [default] or McASP0 transmit frame sync or

left/right clock (LRCLK) (I/O/Z).

H1

INTER-INTEGRATED CIRCUIT 1 (I2C1)

McBSP1 external clock source (as opposed to internal) (I) [default] or I2C1 clock

(I/O/Z).

This pin must be externally pulled up. When this pin is used as an I2C pin, the

value of the pullup resistor is dependent on the number of devices connected to

the I2C bus. For more details, see the Philips I C Specification Revision 2.1

CLKS1/SCL1

DR1/SDA1

8

E1

I/O/Z

—

2

(January 2000).

McBSP1 receive data (I) [default] or I2C1 data (I/O/Z).

This pin must be externally pulled up. When this pin is used as an I2C pin, the

value of the pullup resistor is dependent on the number of devices connected to

37

M2

—

2

the I2C bus. For more details, see the Philips I C Specification Revision 2.1

(January 2000).

INTER-INTEGRATED CIRCUIT 0 (I2C0)

I2C0 clock.

This pin must be externally pulled up. The value of the pullup resistor on this pin

SCL0

SDA0

41

42

N1

N2

I/O/Z

—

is dependent on the number of devices connected to the I2C bus. For more

2

details, see the Philips I C Specification Revision 2.1 (January 2000).

I2C0 data.

This pin must be externally pulled up. The value of the pullup resistor on this pin

is dependent on the number of devices connected to the I2C bus. For more

2

details, see the Philips I C Specification Revision 2.1 (January 2000).

†

‡

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal

IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors

no greater than 4.4 kΩ and 2.0 kΩ, respectively.]

56

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

Terminal Functions (Continued)

SIGNAL

NAME

PIN NO.

IPD/

IPU‡

†

DESCRIPTION

GDP/

TYPE

PYP

ZDP

GENERAL-PURPOSE INPUT/OUTPUT (GPIO)

Host-port data pins (I/O/Z) [default] or general-purpose input/output pins

(I/O/Z) and some function as boot configuration pins at reset.

HD15/GP[15]

HD14/GP[14]

HD13/GP[13]

HD12/GP[12]

HD11/GP[11]

HD10/GP[10]

HD9/GP[9]

174

173

172

168

167

166

165

160

B14

C14

A15

C15

A16

B16

C16

B17

IPU

•

Used for transfer of data, address, and control

Also controls initialization of DSP modes at reset via pullup/pulldown

resistors

As general-purpose input/output (GP[x]) functions, these pins are software-con-

figurable through registers. The “GPxEN” bits in the GP Enable register and the

GPxDIR bits in the GP Direction register must be properly configured:

I/O/Z

GPxEN = 1; GP[x] pin is enabled.

GPxDIR = 0; GP[x] pin is an input.

GPxDIR = 1; GP[x] pin is an output.

For the functionality description of the Host-port data pins or the boot configura-

tion pins, see the Host-Port Interface (HPI) portion of this table.

HD8/GP[8]

General-purpose input/output pins (I/O/Z) which also function as external

interrupts

GP[7](EXT_INT7)

GP[6](EXT_INT6)

7

2

E3

D2

•

Edge-driven

Polarity independently selected via the External Interrupt Polarity Register

bits (EXTPOL.[3:0])

GP[5](EXT_INT5)/

AMUTEIN0

I/O/Z

IPU

6

1

C1

C2

GP[4] and GP[5] pins also function as AMUTEIN1 McASP1 mute input and

AMUTEIN0 McASP0 mute input, respectively, if enabled by the INEN bit in the

associated McASP AMUTE register.

GP[4](EXT_INT4)/

AMUTEIN1

Host-port data pin 7 (I/O/Z) [default] or general-purpose input/output pin 3

(I/O/Z)

HD7/GP[3]

164

82

A18

Y12

J20

C19

I/O/Z

O

IPU

IPD

IPU

IPD

Clock output at half of device speed (O/Z) [default] or this pin can be

programmed as GP[2] pin.

CLKOUT2/GP[2]

HINT/GP[1]

HD4/GP[0]

Host interrupt (from DSP to host) (O) [default] or this pin can be programmed as

a GP[1] pin (I/O/Z).

135

156

Host-port data pin 4 (I/O/Z) [ default] or this pin can be programmed as a GP[0]

pin (I/O/Z).

I/O/Z

RESERVED FOR TEST

RSV

198

200

179

—

A5

B5

O/Z

IPU

Reserved. (Leave unconnected, do not connect to power or ground)

§

A

C12

D7

O

—

O/Z

IPD

Reserved. This pin does not have an IPU. For proper device

operation, the D12/178 pin must be externally pulled down with a 10-kΩresistor.

RSV

178

181

180

D12

A12

B11

I

—

Reserved. [For new designs, it is recommended that this pin be connected di-

rectly to CV

DD

(core power). For old designs, this can be left unconnected.

Reserved. [For new designs, it is recommended that this pin be connected di-

rectly to V (ground). For old designs, this pin can be left unconnected.

ss

†

‡

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal

IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors

no greater than 4.4 kΩ and 2.0 kΩ, respectively.]

57

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

Terminal Functions (Continued)

SIGNAL

NAME

PIN NO.

†

DESCRIPTION

GDP/

TYPE

PYP

ZDP

SUPPLY VOLTAGE PINS

—

5

A17

B3

B8

B13

C10

D1

D16

D19

F3

H18

J2

M18

R1

R18

T3

U5

U7

U12

U16

V13

V15

V19

W3

W9

W12

Y7

3.3-V supply voltage

(see the power-supply decoupling portion of this data sheet)

DV

S

DD

Y17

—

9

—

25

44

47

55

58

65

72

84

87

98

107

—

†

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal

58

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

Terminal Functions (Continued)

SIGNAL

NAME

PIN NO.

†

DESCRIPTION

GDP/

TYPE

PYP

ZDP

SUPPLY VOLTAGE PINS (CONTINUED)

114

126

141

162

183

188

206

—

3.3-V supply voltage

(see the power-supply decoupling portion of this data sheet)

—

DV

S

DD

—

A4

—

A9

—

A10

B2

—

B19

C3

—

C7

—

C18

D5

—

D6

—

D11

D14

D15

F4

—

F17

K1

1.2-V supply voltage [PYP package]

1.20-V supply voltage [GDP and ZDP packages] (See Note)

1.4-V supply voltage [GDP and ZDP packages C6711D-300 only]

(see the power-supply decoupling portion of this data sheet)

—

CV

S

DD

—

K4

—

K17

L4

—

L17

L20

R4

—

R17

U6

—

U10

U11

U14

U15

V3

—

V18

W2

W19

—

Note: This value is compatible with existing 1.26-V designs.

—

†

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal

59

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

Terminal Functions (Continued)

SIGNAL

NAME

PIN NO.

†

DESCRIPTION

GDP/

TYPE

PYP

ZDP

SUPPLY VOLTAGE PINS (CONTINUED)

3

—

11

14

22

29

35

40

43

46

50

51

53

60

67

80

1.2-V supply voltage [PYP package]

89

CV

S

1.20-V supply voltage [GDP and ZDP packages] (See Note)

1.4-V supply voltage [GDP and ZDP packages C6711D-300 only]

(see the power-supply decoupling portion of this data sheet)

DD

96

104

105

116

124

133

149

157

169

171

177

190

195

196

201

208

Note: This value is compatible with existing 1.26-V designs.

GROUND PINS

—

A1

A2

A11

A14

A19

A20

B1

V

SS

GND

Ground pins

B4

†

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal

60

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

Terminal Functions (Continued)

SIGNAL

NAME

PIN NO.

†

TYPE

DESCRIPTION

GDP/

PYP

ZDP

GROUND PINS (CONTINUED)

—

B15

B20

C6

C8

C9

D4

D8

D13

D17

E2

E4

E17

F19

G4

G17

H4

H17

J4

#

Ground pins

J9

The center thermal balls (J9−J12, K9−K12, L9−L12, M9−M12) [shaded] are all tied to ground

and act as both electrical grounds and thermal relief (thermal dissipation).

V

SS

GND

J10

J11

J12

K2

K9

K10

K11

K12

K20

L9

L10

L11

L12

M4

M9

M10

M11

M12

M17

†

#

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal

Shaded pin numbers denote the center thermal balls.

61

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

Terminal Functions (Continued)

SIGNAL

NAME

PIN NO.

†

TYPE

DESCRIPTION

GDP/

PYP

ZDP

GROUND PINS (CONTINUED)

—

4

N4

N17

P4

P17

P19

T4

T17

U4

U8

U9

U13

U17

U20

W1

W5

W11

W16

W20

Y1

Y2

V

SS

GND

Ground pins

Y13

Y19

Y20

—

10

15

23

26

30

34

39

45

48

49

52

54

59

66

73

81

—

†

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal

62

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

Terminal Functions (Continued)

SIGNAL

NAME

PIN NO.

†

TYPE

DESCRIPTION

GDP/

PYP

ZDP

GROUND PINS (CONTINUED)

85

—

88

97

106

115

125

134

142

148

158

163

170

182

189

194

199

203

207

V

SS

GND

Ground pins

†

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal

63

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

development support

TI offers an extensive line of development tools for the TMS320C6000 DSP platform, including tools to

evaluate the performance of the processors, generate code, develop algorithm implementations, and fully

integrate and debug software and hardware modules.

The following products support development of C6000 DSP-based applications:

Software Development Tools:

Code Composer Studio Integrated Development Environment (IDE): including Editor

C/C++/Assembly Code Generation, and Debug plus additional development tools

Scalable, Real-Time Foundation Software (DSP/BIOS), which provides the basic run-time target software

needed to support any DSP application.

Hardware Development Tools:

Extended Development System (XDS) Emulator (supports C6000 DSP multiprocessor system debug)

EVM (Evaluation Module)

For a complete listing of development-support tools for the TMS320C6000 DSP platform, visit the Texas

Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). For

information on pricing and availability, contact the nearest TI field sales office or authorized distributor.

TI offers an extensive line of development tools for the TMS320C6000 DSP platform, including tools to

evaluate the performance of the processors, generate code, develop algorithm implementations, and fully

integrate and debug software and hardware modules.

C6000 and XDS are trademarks of Texas Instruments.

64

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

device support

device and development-support tool nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all DSP

devices and support tools. Each DSP commercial family member has one of three prefixes: TMX, TMP, or TMS.

(e.g., TMS320C6713BGDP300). Texas Instruments recommends two of three possible prefix designators for

support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from

engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).

Device development evolutionary flow:

TMX

TMP

TMS

Experimental device that is not necessarily representative of the final device’s electrical

specifications.

Final silicon die that conforms to the device’s electrical specifications but has not completed

quality and reliability verification.

Fully qualified production device.

Support tool development evolutionary flow:

TMDX

Development-support product that has not yet completed Texas Instruments internal qualification

testing.

TMDS

Fully qualified development-support product.

TMX and TMP devices and TMDX development-support tools are shipped with the following disclaimer:

“Developmental product is intended for internal evaluation purposes.”

TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability

of the device have been demonstrated fully. TI’s standard warranty applies.

Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production

devices. Texas Instruments recommends that these devices not be used in any production system because their

expected end-use failure rate still is undefined. Only qualified production devices are to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type

(for example, GDP), the temperature range (for example, blank is the default commercial temperature range),

and the device speed range in megahertz (for example, -225 is 225 MHz).

The ZDP package, like the GDP package, is a 272-ball plastic BGA only with Pb-free balls. For device part

numbers and further ordering information for TMS320C6713B in the PYP, GDP and ZDP package types, see

the TI website (http://www.ti.com) or contact your TI sales representative.

TMS320 is a trademark of Texas Instruments.

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

device and development-support tool nomenclature (continued)

(

)

TMS 320

C 6713B GDP

300

DEVICE SPEED RANGE

167 MHz

200 MHz

225 MHz

300 MHz

PREFIX

TMX= Experimental device

TMP= Prototype device

TMS= Qualified device

SMJ = MIL-PRF-38535, QML

SM = High Rel (non-38535)

TEMPERATURE RANGE (DEFAULT: 0°C TO 90°C)

Blank = 0°C to 90°C, commercial temperature

A

= −40°C to 105°C, extended temperature

DEVICE FAMILY

320 = TMS320 DSP family

†‡§

PACKAGE TYPE

GDP = 272-pin plastic BGA

PYP = 208-pin PowerPADt plastic QFP

ZDP = 272-pin plastic BGA, with Pb-free soldered balls

TECHNOLOGY

C = CMOS

DEVICE

C6713B

†

‡

§

BGA

QFP

=

Ball Grid Array

Quad Flatpack

The ZDP mechanical package designator represents the version of the GDP with Pb−Free soldered balls. The ZDP package

devices are supported in the same speed grades as the GDP package devices (available upon request).

For actual device part numbers (P/Ns) and ordering information, see the Mechanical Data section of this

document or the TI website (www.ti.com).

Figure 12. TMS320C6000 DSP Device Nomenclature (Including the TMS320C6713B Device)

MicroStar BGA and PowerPAD are trademarks of Texas Instruments.

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

documentation support

Extensive documentation supports all TMS320 DSP family generations of devices from product

announcement through applications development. The types of documentation available include: data sheets,

such as this document, with design specifications; complete user’s reference guides for all devices and tools;

technical briefs; development-support tools; on-line help; and hardware and software applications. The

following is a brief, descriptive list of support documentation specific to the C6000 DSP devices:

The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the

C6000 CPU (DSP core) architecture, instruction set, pipeline, and associated interrupts.

The TMS320C6000 DSP Peripherals Overview Reference Guide [hereafter referred to as the C6000 PRG

Overview] (literature number SPRU190) provides an overview and briefly describes the functionality of the

peripherals available on the C6000 DSP platform of devices. This document also includes a table listing the

peripherals available on the C6000 devices along with literature numbers and hyperlinks to the associated

peripheral documents. These C6713B peripherals are similar to the peripherals on the TMS320C6711 and

TMS320C64x devices; therefore, see the TMS320C6711 (C6711 or C67x) peripheral information, and in some

cases, where indicated, see the TMS320C6711 (C6711 or C671x) peripheral information and in some cases,

where indicated, see the C64x information in the C6000 PRG Overview (literature number SPRU190).

The TMS320DA6000 DSP Multichannel Audio Serial Port (McASP) Reference Guide (literature number

SPRU041) describes the functionality of the McASP peripherals available on the C6713B device.

TMS320C6000 DSP Software-Programmable Phase-Locked Loop (PLL) Controller Reference Guide

(literature number SPRU233) describes the functionality of the PLL peripheral available on the C6713B device.

TMS320C6000 DSP Inter-Integrated Circuit (I2C) Module Reference Guide (literature number SPRU175)

describes the functionality of the I2C peripherals available on the C6713B device.

The PowerPAD Thermally Enhanced Package Technical Brief (literature number SLMA002) focuses on the

specifics of integrating a PowerPAD package into the printed circuit board design to make optimum use of the

thermal efficiencies designed into the PowerPAD package.

The TMS320C6000 Technical Brief (literature number SPRU197) gives an introduction to the C62x/C67x

devices, associated development tools, and third-party support.

The Migrating from TMS320C6211(B)/C6711(B) to TMS320C6713 application report (literature number

SPRA851) indicates the differences and describes the issues of interest related to the migration from the Texas

Instruments TMS320C6211(B)/C6711(B), GFN package, to the TMS320C6713, GDP and ZDP packages.

The TMS320C6713, TMS320C6713B Digital Signal Processors Silicon Errata (literature number SPRZ191)

describes the known exceptions to the functional specifications for particular silicon revisions of the

TMS320C6713B device.

The TMS320C6711D, C6712D, C6713B Power Consumption Summary application report (literature number

SPRA889A2 or later) discusses the power consumption for user applications with the TMS320C6713B,

TMS320C6712D, and TMS320C6711D DSP devices.

The Using IBIS Models for Timing Analysis application report (literature number SPRA839) describes how to

properly use IBIS models to attain accurate timing analysis for a given system.

The tools support documentation is electronically available within the Code Composer Studio Integrated

Development Environment (IDE). For a complete listing of C6000 DSP latest documentation, visit the Texas

Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL).

See the Worldwide Web URL for the application report How To Begin Development Today With the

TMS320C6713 Floating-Point DSP (literature number SPRA809), which describes in more detail the

similarities/differences between the C6713 and C6711 C6000 DSP devices.

C62x is a trademark of Texas Instruments.

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

CPU CSR register description

The CPU control status register (CSR) contains the CPU ID and CPU Revision ID (bits 16−31) as well as the

status of the device power-down modes [PWRD field (bits 15−10)], program and data cache control modes, the

endian bit (EN, bit 8) and the global interrupt enable (GIE, bit 0) and previous GIE (PGIE, bit 1). Figure 13 and

Table 24 identify the bit fields in the CPU CSR register.

For more detailed information on the bit fields in the CPU CSR register, see the TMS320C6000 DSP Peripherals

Overview Reference Guide (literature number SPRU190) and the TMS320C6000 CPU and Instruction Set

Reference Guide (literature number SPRU189).

31

24 23

16

CPU ID

R-0x02

REVISION ID

R-0x03

15

10

9

8

7

6

5 4

2

1

0

PWRD

R/W-0

SAT

R/C-0

EN

PCC

R/W-0

DCC

PGIE

GIE

R-1

R/W-0

R/W-0 R/W-0

Legend: R = Readable by the MVC instruction, R/W = Readable/Writeable by the MVC instruction; W = Read/write; -n = value after reset, -x = undefined value after

reset, C = Clearable by the MVC instruction

Figure 13. CPU Control Status Register (CPU CSR)

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

CPU CSR register description (continued)

Table 24. CPU CSR Register Bit Field Description

BIT #

NAME

DESCRIPTION

CPU ID + REV ID. Read only.

Identifies which CPU is used and defines the silicon revision of the CPU.

31:24

CPU ID

23:16

15:10

REVISION ID

PWRD

CPU ID + REVISION ID (31:16) are combined for a value of 0x0203

Control power-down modes. The values are always read as zero.

000000

001001

010001

011010

011100

Others

=

no power-down (default)

PD1, wake-up by an enabled interrupt

PD1, wake-up by an enabled or not enabled interrupt

PD2, wake-up by a device reset

PD3, wake-up by a device reset

Reserved

Saturate bit.

Set when any unit performs a saturate. This bit can be cleared only by the MVC instruction and can

be set only by a functional unit. The set by the a functional unit has priority over a clear (by the MVC

instruction) if they occur on the same cycle. The saturate bit is set one full cycle (one delay slot) after

a saturate occurs. This bit will not be modified by a conditional instruction whose condition is false.

9

SAT

Endian bit. This bit is read-only.

Depicts the device endian mode.

8

EN

0

1

=

Big Endian mode.

Little Endian mode [default].

Program Cache control mode.

L1D, Level 1 Program Cache

7:5

4:2

PCC

DCC

000/010

=

Cache Enabled / Cache accessed and updated on reads.

All other PCC values reserved.

Data Cache control mode.

L1D, Level 1 Data Cache

000/010

=

Cache Enabled / 2-Way Cache

All other DCC values reserved

Previous GIE (global interrupt enable); saves the Global Interrupt Enable (GIE) when an interrupt is

taken. Allows for proper nesting of interrupts.

1

0

PGIE

GIE

0

1

=

Previous GIE value is 0. (default)

Previous GIE value is 1.

Global interrupt enable bit.

Enables (1) or disables (0) all interrupts except the reset interrupt and NMI (nonmaskable interrupt).

0

1

=

Disables all interrupts (except the reset interrupt and NMI) [default]

Enables all interrupts (except the reset interrupt and NMI)

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

cache configuration (CCFG) register description

The C6713B device includes an enhancement to the cache configuration (CCFG) register. A “P” bit

(CCFG.31) allows the programmer to select the priority of accesses to L2 memory originating from the transfer

crossbar (TC) over accesses originating from the L1D memory system. An important class of TC accesses is

EDMA transfers, which move data to or from the L2 memory. While the EDMA normally has no issue accessing

L2 memory due to the high hit rates on the L1D memory system, there are pathological cases where certain

CPU behavior could block the EDMA from accessing the L2 memory for long enough to cause a missed deadline

when transferring data to a peripheral such as the McASP or McBSP. This can be avoided by setting the P bit

to “1” because the EDMA will assume a higher priority than the L1D memory system when accessing L2

memory.

For more detailed information on the P-bit function and for silicon advisories concerning EDMA L2 memory

accesses blocked, see the TMS320C6713, TMS320C6713B Digital Signal Processors Silicon Errata (literature

number SPRZ191).

7

31

30

10

9

8

3

2

0

†

P

Reserved

R-x

IP

ID

Reserved

R-0 0000

L2MODE

R/W-000

R/W-0

W-0

Legend: R = Readable; R/W = Readable/Writeable; -n = value after reset; -x = undefined value after reset

†

This device includes a P bit.

Figure 14. Cache Configuration Register (CCFG)

Table 25. CCFG Register Bit Field Description

BIT #

31

NAME

DESCRIPTION

L1D requestor priority to L2 bit.

P

Reserved

IP

P

=

0: L1D requests to L2 higher priority than TC requests

1: TC requests to L2 higher priority than L1D requests

30:10

9

Reserved. Read-only, writes have no effect.

Invalidate L1P bit.

0

1

=

Normal L1P operation

All L1P lines are invalidated

Invalidate L1D bit.

8

ID

0

1

=

Normal L1D operation

All L1D lines are invalidated

7:3

Reserved

Reserved. Read-only, writes have no effect.

L2 operation mode bits (L2MODE).

000b = L2 Cache disabled (All SRAM mode) [256K SRAM]

001b = 1-way Cache (16K L2 Cache) / [240K SRAM]

010b = 2-way Cache (32K L2 Cache) / [224K SRAM]

2:0

L2MODE

011b

111b

=

3-way Cache (48K L2 Cache) / [208K SRAM]

4-way Cache (64K L2 Cache) / [192K SRAM]

All others Reserved

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

interrupts and interrupt selector

The C67x DSP core supports 16 prioritized interrupts, which are listed in Table 26. The highest priority interrupt

is INT_00 (dedicated to RESET) while the lowest priority is INT_15. The first four interrupts are non-maskable

and fixed. The remaining interrupts (4−15) are maskable and default to the interrupt source listed in Table 26.

However, their interrupt source may be reprogrammed to any one of the sources listed in Table 27 (Interrupt

Selector). Table 27 lists the selector value corresponding to each of the alternate interrupt sources. The selector

choice for interrupts 4−15 is made by programming the corresponding fields (listed in Table 26) in the MUXH

(address 0x019C0000) and MUXL (address 0x019C0004) registers.

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

Table 26. DSP Interrupts

Table 27. Interrupt Selector

INTERRUPT

SELECTOR

CONTROL

REGISTER

DEFAULT

SELECTOR

VALUE

INTERRUPT

SELECTOR

VALUE

DSP

INTERRUPT

NUMBER

DEFAULT

INTERRUPT

EVENT

INTERRUPT

EVENT

MODULE

(BINARY)

INT_00

INT_01

INT_02

INT_03

INT_04

INT_05

INT_06

INT_07

INT_08

INT_09

INT_10

INT_11

INT_12

INT_13

INT_14

INT_15

−

RESET

NMI

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

DSPINT

TINT0

TINT1

SDINT

HPI

Timer 0

Timer 1

EMIF

GPIO

EDMA

Emulation

McBSP0

McBSP1

GPIO

−

Reserved

−

†

MUXL[4:0]

MUXL[9:5]

MUXL[14:10]

MUXL[20:16]

MUXL[25:21]

MUXL[30:26]

MUXH[4:0]

MUXH[9:5]

MUXH[14:10]

MUXH[20:16]

MUXH[25:21]

MUXH[30:26]

00100

00101

00110

00111

01000

01001

00011

01010

01011

00000

00001

00010

GPINT4

GPINT5

GPINT6

GPINT7

GPINT4

GPINT5

GPINT6

GPINT7

EDMAINT

EMUDTDMA

SDINT

EDMAINT

EMUDTDMA

EMURTDXRX

EMURTDXTX

XINT0

EMURTDXRX

EMURTDXTX

DSPINT

RINT0

TINT0

XINT1

TINT1

RINT1

GPINT0

Reserved

I2CINT0

−

I2C0

I2CINT1

I2C1

Reserved

AXINT0

−

McASP0

McASP1

ARINT0

AXINT1

ARINT1

†

Interrupt Events GPINT4, GPINT5, GPINT6, and GPINT7 are outputs from the GPIO module (GP). They originate from the device pins

GP[4](EXT_INT4)/AMUTEIN1, GP[5](EXT_INT5)/AMUTEIN0, GP[6](EXT_INT6), and GP[7](EXT_INT7). These pins can be used as

edge-sensitive EXT_INTx with polarity controlled by the External Interrupt Polarity Register (EXTPOL.[3:0]). The corresponding pins must

first be enabled in the GPIO module by setting the corresponding enable bits in the GP Enable Register (GPEN.[7:4]), and configuring them

as inputs in the GP Direction Register (GPDIR.[7:4]). These interrupts can be controlled through the GPIO module in addition to the simple

EXTPOL.[3:0] bits. For more information on interrupt control via the GPIO module, see the TMS320C6000 DSP General-Purpose

Input/Output (GPIO) Reference Guide (literature number SPRU584).

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

external interrupt sources

The device supports many external interrupt sources as indicated in Table 28. Control of the interrupt source

is done by the associated module and is made available by enabling the corresponding binary interrupt selector

value (see Table 27 Interrupt Selector shaded rows). Due to pin muxing and module usage, not all external

interrupt sources are available at the same time.

Table 28. External Interrupt Sources and Peripheral Module Control

NAME

INTERRUPT

EVENT

MODULE

GP[15]

GP[14]

GP[13]

GP[12]

GP[11]

GP[10]

GP[9]

GP[8]

GP[7]

GP[6]

GP[5]

GP[4]

GP[3]

GP[2]

GP[1]

GP[0]

GPINT0

GPIO

GPINT0

GPINT0 or GPINT7

GPINT0 or GPINT6

GPINT0 or GPINT5

GPINT0 or GPINT4

GPINT0

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

EDMA module and EDMA selector

The C67x EDMA supports up to 16 EDMA channels. Four of the sixteen channels (channels 8−11) are reserved

for EDMA chaining, leaving 12 EDMA channels available to service peripheral devices.

The EDMA selector registers that control the EDMA channels servicing peripheral devices are located at

addresses 0x01A0FF00 (ESEL0), 0x01A0FF04 (ESEL1), and 0x01A0FF0C (ESEL3). These EDMA selector

registers control the mapping of the EDMA events to the EDMA channels. Each EDMA event has an assigned

EDMA selector code (see Table 30). By loading each EVTSELx register field with an EDMA selector code, users

can map any desired EDMA event to any specified EDMA channel. Table 29 lists the default EDMA selector

value for each EDMA channel.

See Table 31 and Table 32 for the EDMA Event Selector registers and their associated bit descriptions.

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ꢋ

SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

EDMA module and EDMA selector (continued)

Table 29. EDMA Channels

Table 30. EDMA Selector

EDMA

DEFAULT

SELECTOR

VALUE

DEFAULT

EDMA

EVENT

EDMA

CHANNEL

SELECTOR

CONTROL

REGISTER

SELECTOR

MODULE

EVENT

CODE (BINARY)

(BINARY)

0

1

ESEL0[5:0]

ESEL0[13:8]

ESEL0[21:16]

ESEL0[29:24]

ESEL1[5:0]

ESEL1[13:8]

ESEL1[21:16]

ESEL1[29:24]

−

000000

000001

000010

000011

000100

000101

000110

000111

−

DSPINT

TINT0

000000

000001

000010

000011

000100

000101

000110

000111

001000

001001

001010

001011

001100

001101

001110

001111

DSPINT

TINT0

HPI

TIMER0

TIMER1

EMIF

2

TINT1

3

SDINT

4

GPINT4

GPINT5

GPINT6

GPINT7

GPINT4

GPINT5

GPINT6

GPINT7

GPINT0

GPINT1

GPINT2

GPINT3

XEVT0

REVT0

XEVT1

REVT1

GPIO

5

GPIO

6

GPIO

7

GPIO

8

TCC8 (Chaining)

TCC9 (Chaining)

TCC10 (Chaining)

TCC11 (Chaining)

XEVT0

GPIO

9

−

GPIO

10

11

12

13

14

15

−

GPIO

−

GPIO

ESEL3[5:0]

ESEL3[13:8]

ESEL3[21:16]

ESEL3[29:24]

001100

001101

001110

001111

McBSP0

McBSP1

REVT0

XEVT1

REVT1

010000−011111

100000

100001

100010

100011

100100

100101

100110

100111

101000

101001

101010

101011

101100

101101

101110

101111

Reserved

AXEVTE0

AXEVTO0

AXEVT0

McASP0

McASP1

I2C0

AREVTE0

AREVTO0

AREVT0

AXEVTE1

AXEVTO1

AXEVT1

AREVTE1

AREVTO1

AREVT1

I2CREVT0

I2CXEVT0

I2CREVT1

I2CXEVT1

GPINT8

I2C0

I2C1

110000

110001

110010

110011

110100

110101

110110

110111

GPIO

GPINT9

GPIO

GPINT10

GPINT11

GPINT12

GPINT13

GPINT14

GPINT15

GPIO

111000−111111

Reserved

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

EDMA module and EDMA selector (continued)

Table 31. EDMA Event Selector Registers (ESEL0, ESEL1, and ESEL3)

ESEL0 Register (0x01A0 FF00)

30

31

29

28 27

24 23

22 21

20 19

16

0

Reserved

R−0

EVTSEL3

R/W−00 0011b

Reserved

R−0

EVTSEL2

R/W−00 0010b

4 3

14

15

13

12 11

8

7

6

5

Reserved

R−0

EVTSEL1

Reserved

R−0

EVTSEL0

R/W−00 0000b

R/W−00 0001b

Legend: R = Read only, R/W = Read/Write; -n = value after reset

ESEL1 Register (0x01A0 FF04)

30

31

29

13

28 27

24 23

22 21

20 19

16

0

Reserved

R−0

EVTSEL7

R/W−00 0111b

Reserved

R−0

EVTSEL6

R/W−00 0110b

4 3

14

15

12 11

8

7

6

5

Reserved

R−0

EVTSEL5

Reserved

R−0

EVTSEL4

R/W−00 0100b

R/W−00 0101b

Legend: R = Read only, R/W = Read/Write; -n = value after reset

ESEL3 Register (0x01A0 FF0C)

30

31

29

13

28 27

24 23

22 21

20 19

16

0

Reserved

R−0

EVTSEL15

R/W−00 1111b

Reserved

R−0

EVTSEL14

R/W−00 1110b

4 3

14

15

12 11

8

7

6

5

Reserved

R−0

EVTSEL13

Reserved

R−0

EVTSEL12

R/W−00 1100b

R/W−00 1101b

Legend: R = Read only, R/W = Read/Write; -n = value after reset

Table 32. EDMA Event Selection Registers (ESEL0, ESEL1, and ESEL3) Description

BIT #

NAME

DESCRIPTION

31:30

23:22

15:14

7:6

Reserved

Reserved. Read-only, writes have no effect.

EDMA event selection bits for channel x. Allows mapping of the EDMA events to the EDMA channels.

The EVTSEL0 through EVTSEL15 bits correspond to the channels 0 to 15, respectively. These

EVTSELx fields are user−selectable. By configuring the EVTSELx fields to the EDMA selector value

of the desired EDMA sync event number (see Table 30), users can map any EDMA event to the

EDMA channel.

29:24

21:16

13:8

5:0

EVTSELx

For example, if EVTSEL15 is programmed to 00 0001b (the EDMA selector code for TINT0), then

channel 15 is triggered by Timer0 TINT0 events.

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

PLL and PLL controller

The TMS320C6713B includes a PLL and a flexible PLL Controller peripheral consisting of a prescaler (D0) and

four dividers (OSCDIV1, D1, D2, and D3). The PLL controller is able to generate different clocks for different

parts of the system (i.e., DSP core, Peripheral Data Bus, External Memory Interface, McASP, and other

peripherals). Figure 15 illustrates the PLL, the PLL controller, and the clock generator logic.

PLLHV

+3.3 V

EMI filter

C1

C2

10 µF 0.1 µF

CLKMODE0

CLKIN

PLLOUT

PLLREF

DIVIDER D0

/1, /2,

..., /32

PLLEN (PLL_CSR.[0])

1

0

PLL

x4 to x25

†

DIVIDER D1

1

0

ENA

Reserved

CLKOUT3

/1, /2,

SYSCLK1

(DSP Core)

..., /32

ENA

D1EN (PLLDIV1.[15])

D0EN (PLLDIV0.[15])

†

DIVIDER D2

/1, /2,

SYSCLK2

(Peripherals)

..., /32

OSCDIV1

D2EN (PLLDIV2.[15])

ENA

/1, /2,

..., /32

For Use

in System

AUXCLK

(Internal Clock Source

to McASP0 and McASP1)

DIVIDER D3

ENA

/1, /2,

..., /32

OD1EN (OSCDIV1.[15])

SYSCLK3

ENA

D3EN (PLLDIV3.[15])

ECLKIN

(EMIF Clock Input)

EKSRC Bit

1

0

(DEVCFG.[4])

EMIF

C6713B DSP

ECLKOUT

Dividers D1 and D2 must never be disabled. Never write a “0” to the D1EN or D2EN bits in the PLLDIV1 and PLLDIV2 registers.

†

NOTES: A. Place all PLL external components (C1, C2, and the EMI Filter) as close to the C67x DSP device as possible. For the best

performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or

components other than the ones shown.

B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (C1, C2, and the EMI

Filter).

C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DV

D. EMI filter manufacturer TDK part number ACF451832-333, -223, -153, -103. Panasonic part number EXCCET103U.

.

DD

Figure 15. PLL and Clock Generator Logic

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

PLL and PLL controller (continued)

The PLL Reset Time is the amount of wait time needed when resetting the PLL (writing PLLRST=1), in order

for the PLL to properly reset, before bringing the PLL out of reset (writing PLLRST = 0). For the PLL Reset Time

value, see Table 33. The PLL Lock Time is the amount of time from when PLLRST = 0 with PLLEN = 0 (PLL

out of reset, but still bypassed) to when the PLLEN bit can be safely changed to “1” (switching from bypass to

the PLL path), see Table 33 and Figure 15.

Under some operating conditions, the maximum PLL Lock Time may vary from the specified typical value. For

the PLL Lock Time values, see Table 33.

Table 33. PLL Lock and Reset Times

MIN

TYP

MAX

UNIT

µs

PLL Lock Time

PLL Reset Time

75

187.5

125

ns

Table 34 shows the device’s CLKOUT signals, how they are derived and by what register control bits, and what

is the default settings. For more details on the PLL, see the PLL and Clock Generator Logic diagram (Figure 15).

Table 34. CLKOUT Signals, Default Settings, and Control

CLOCK OUTPUT

SIGNAL NAME

DEFAULT SETTING

(ENABLED or DISABLED)

CONTROL

BIT(s) (Register)

DESCRIPTION

D2EN = 1 (PLLDIV2.[15])

CK2EN = 1 (EMIF GBLCTL.[3])

CLKOUT2

CLKOUT3

ON (ENABLED)

SYSCLK2 selected [default]

OD1EN = 1 (OSCDIV1.[15])

Derived from CLKIN

SYSCLK3 selected [default].

ON (ENABLED);

derived from SYSCLK3

EKSRC = 0 (DEVCFG.[4])

EKEN = 1 (EMIF GBLCTL.[5])

To select ECLKIN source:

EKSRC = 1 (DEVCFG.[4]) and

EKEN = 1 (EMIF GBLCTL.[5])

ECLKOUT

The input clock (CLKIN) is directly available to the McASP modules as AUXCLK for use as an internal

high-frequency clock source. The input clock (CLKIN) may also be divided down by a programmable divider

OSCDIV1 (/1, /2, /3, ..., /32) and output on the CLKOUT3 pin for other use in the system.

Figure 15 shows that the input clock source may be divided down by divider PLLDIV0 (/1, /2, ..., /32) and then

multiplied up by a factor of x4, x5, x6, and so on, up to x25.

Either the input clock (PLLEN = 0) or the PLL output (PLLEN = 1) then serves as the high-frequency reference

clock for the rest of the DSP system. The DSP core clock, the peripheral bus clock, and the EMIF clock may

be divided down from this high-frequency clock (each with a unique divider) . For example, with a 30 MHz input

if the PLL output is configured for 450 MHz, the DSP core may be operated at 225 MHz (/2) while the EMIF may

be configured to operate at a rate of 75 MHz (/6). Note that there is a specific minimum and maximum reference

clock (PLLREF) and output clock (PLLOUT) for the block labeled PLL in Figure 15, as well as for the DSP core,

peripheral bus, and EMIF. The clock generator must not be configured to exceed any of these constraints

(certain combinations of external clock input, internal dividers, and PLL multiply ratios might not be supported).

See Table 35 for the PLL clocks input and output frequency ranges.

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

PLL and PLL controller (continued)

†‡

Table 35. PLL Clock Frequency Ranges

PYP −200, -225

GDP/ZDP −225, -300

PYPA −167, -200

GDPA/ZDPA −200

CLOCK SIGNAL

UNIT

MIN

12

140

−

MAX

PLLREF (PLLEN = 1)

100

MHz

PLLOUT

SYSCLK1

600

Device Speed (DSP Core)

100

SYSCLK3 (EKSRC = 0)

−

§

50

AUXCLK

−

†

‡

SYSCLK2 rate must be exactly half of SYSCLK1.

Also see the electrical specification (timing requirements and switching characteristics parameters) in the input and output clocks section of this

data sheet.

§

When the McASP module is not used, the AUXCLK maximum frequency can be any frequency up to the CLKIN maximum frequency.

The EMIF itself may be clocked by an external reference clock via the ECLKIN pin or can be generated on-chip

as SYSCLK3. SYSCLK3 is derived from divider D3 off of PLLOUT (see Figure 15, PLL and Clock Generator

Logic). The EMIF clock selection is programmable via the EKSRC bit in the DEVCFG register.

The settings for the PLL multiplier and each of the dividers in the clock generation block may be reconfigured

via software at run time. If either the input to the PLL changes due to D0, CLKMODE0, or CLKIN, or if the PLL

multiplier is changed, then software must enter bypass first and stay in bypass until the PLL has had enough

time to lock (see electrical specifications). For the programming procedure, see the TMS320C6000 DSP

Software-Programmable Phase-Locked Loop (PLL) Controller Reference Guide (literature number SPRU233).

SYSCLK2 is the internal clock source for peripheral bus control. SYSCLK2 (Divider D2) must be programmed

to be half of the SYSCLK1 rate. For example, if D1 is configured to divide-by-2 mode (/2), then D2 must be

programmed to divide-by-4 mode (/4). SYSCLK2 is also tied directly to CLKOUT2 pin (see Figure 15).

During the programming transition of Divider D1 and Divider D2 (resulting in SYSCLK1 and SYSCLK2 output

clocks, see Figure 15), the order of programming the PLLDIV1 and PLLDIV2 registers must be observed to

ensure that SYSCLK2 always runs at half the SYSCLK1 rate or slower. For example, if the divider ratios of D1

and D2 are to be changed from /1, /2 (respectively) to /5, /10 (respectively) then, the PLLDIV2 register must be

programmed before the PLLDIV1 register. The transition ratios become /1, /2; /1, /10; and then /5, /10. If the

divider ratios of D1 and D2 are to be changed from /3, /6 to /1, /2 then, the PLLDIV1 register must be programmed

before the PLLDIV2 register. The transition ratios, for this case, become /3, /6; /1, /6; and then /1, /2. The final

SYSCLK2 rate must be exactly half of the SYSCLK1 rate.

Note that Divider D1 and Divider D2 must always be enabled (i. e., D1EN and D2EN bits are set to “1” in the

PLLDIV1 and PLLDIV2 registers).

The PLL Controller registers should be modified only by the CPU or via emulation. The HPI should not be used

to directly access the PLL Controller registers.

For detailed information on the clock generator (PLL Controller registers) and their associated software bit

descriptions, see Table 37 through Table 43.

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

PLL and PLL controller (continued)

Table 36. PLL Control/Status Register (PLLCSR) [0x01B7 C100]

28 27

24 23

20 19

31

15

16

0

Reserved

R−0

5

12 11

8

7

6

4

3

2

1

Reserved

R−0

STABLE

R−x

Reserved

R−0

PLLRST

RW−1

Reserved

R/W−0

PLLPWRDN

R/W−0b

PLLEN

RW−0

Legend: R = Read only, R/W = Read/Write; -n = value after reset

Table 37. PLL Control/Status Register (PLLCSR) Description

BIT #

NAME

DESCRIPTION

Reserved. Read-only, writes have no effect.

31:7

Reserved

Clock Input Stable. This bit indicates if the clock input has stabilized.

6

5:4

3

STABLE

Reserved

PLLRST

0

1

–

Clock input not yet stable. Clock counter is not finished counting (default).

Clock input stable.

Reserved. Read-only, writes have no effect.

Asserts RESET to PLL

0

1

–

PLL Reset Released.

PLL Reset Asserted (default).

2

Reserved

PLLPWRDN

Reserved. The user must write a “0” to this bit.

Select PLL Power Down

1

0

1

–

PLL Operational (default).

PLL Placed in Power-Down State.

PLL Mode Enable

0

–

Bypass Mode (default). PLL disabled.

Divider D0 and PLL are bypassed. SYSCLK1/SYSCLK2/SYSCLK3 are divided down

directly from input reference clock.

0

PLLEN

1

–

PLL Enabled.

Divider D0 and PLL are not bypassed. SYSCLK1/SYSCLK2/SYSCLK3 are divided down

from PLL output.

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

PLL and PLL controller (continued)

Table 38. PLL Multiplier Control Register (PLLM) [0x01B7 C110]

28 27

12 11

24 23

20 19

31

15

16

0

Reserved

R−0

8

7

6

5

4

3

2

1

Reserved

R−0

PLLM

R/W−0 0111

Legend: R = Read only, R/W = Read/Write; -n = value after reset

Table 39. PLL Multiplier Control Register (PLLM) Description

BIT #

NAME

DESCRIPTION

Reserved. Read-only, writes have no effect.

PLL multiply mode [default is x7 (0 0111)].

31:5

Reserved

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

=

Reserved

x4

x5

x6

x7

x8

x9

x10

x11

x12

x13

x14

x15

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

=

x16

x17

x18

x19

x20

x21

x22

x23

4:0

PLLM

x24

x25

Reserved

PLLM select values 00000 through 00011 and 11010 through 11111 are not supported.

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

PLL and PLL controller (continued)

Table 40. PLL Wrapper Divider x Registers (PLLDIV0, PLLDIV1, PLLDIV2, and PLLDIV3)

[0x01B7 C114, 0x01B7 C118, 0x01B7 C11C, and 0x01B7 C120, respectively]

28 27

24 23

20 19

31

16

0

Reserved

R−0

7

14

15

12 11

8

5

4

3

2

1

DxEN

R/W−1

Reserved

R−0

PLLDIVx

R/W−x xxxx

†

Legend: R = Read only, R/W = Read/Write; -n = value after reset

†

Default values for the PLLDIV0, PLLDIV1, PLLDIV2, and PLLDIV3 bits are /1 (0 0000), /1 (0 0000), /2 (0 0001), and /2 (0 0001), respectively.

CAUTION:

D1 and D2 should never be disabled. D3 should only be disabled if ECLKIN is used.

Table 41. PLL Wrapper Divider x Registers (Prescaler Divider D0 and Post-Scaler Dividers D1,

‡

D2, and D3) Description

BIT #

NAME

DESCRIPTION

Reserved. Read-only, writes have no effect.

Divider Dx Enable (where x denotes 0 through 3).

31:16

Reserved

0

1

–

−

Divider x Disabled. No clock output.

Divider x Enabled (default).

15

DxEN

These divider-enable bits are device-specific and must be set to 1 to enable.

14:5

Reserved

Reserved. Read-only, writes have no effect.

PLL Divider Ratio [Default values for the PLLDIV0, PLLDIV1, PLLDIV2, and PLLDIV3 bits are /1, /1,

/2, and /2, respectively].

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

=

/1

/2

/3

/4

/5

/6

/7

/8

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

=

/17

/18

/19

/20

/21

/22

/23

/24

/25

/26

/27

/28

/29

/30

/31

/32

4:0

PLLDIVx

/9

/10

/11

/12

/13

/14

/15

/16

‡

Note that SYSCLK2 must run at half the rate of SYSCLK1. Therefore, the divider ratio of D2 must be two times slower than D1. For example,

if D1 is set to /2, then D2 must be set to /4.

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

PLL and PLL controller (continued)

Table 42. Oscillator Divider 1 Register (OSCDIV1) [0x01B7 C124]

28 27

12 11

24 23

20 19

31

16

0

Reserved

R−0

7

14

15

8

5

4

3

2

1

OD1EN

R/W−1

Reserved

R−0

OSCDIV1

R/W−0 0111

Legend: R = Read only, R/W = Read/Write; -n = value after reset

The OSCDIV1 register controls the oscillator divider 1 for CLKOUT3. The CLKOUT3 signal does not go through

the PLL path.

Table 43. Oscillator Divider 1 Register (OSCDIV1) Description

BIT #

NAME

DESCRIPTION

Reserved. Read-only, writes have no effect.

Oscillator Divider 1 Enable.

31:16

Reserved

15

OD1EN

0

1

–

−

Oscillator Divider 1 Disabled.

Oscillator Divider 1 Enabled (default).

14:5

Reserved

Reserved. Read-only, writes have no effect.

Oscillator Divider 1 Ratio [default is /8 (0 0111)].

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

=

/1

/2

/3

/4

/5

/6

/7

/8

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

=

/17

/18

/19

/20

/21

/22

/23

/24

/25

/26

/27

/28

/29

/30

/31

/32

4:0

OSCDIV1

/9

/10

/11

/12

/13

/14

/15

/16

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

multichannel audio serial port (McASP) peripherals

The device includes two multi-channel audio serial port (McASP) interface peripherals (McASP1 and McASP0).

The McASP is a serial port optimized for the needs of multi-channel audio applications. With two McASP

peripherals, the device is capable of supporting two completely independent audio zones simultaneously.

Each McASP consists of a transmit and receive section. These sections can operate completely independently

with different data formats, separate master clocks, bit clocks, and frame syncs or alternatively, the transmit and

receive sections may be synchronized. Each McASP module also includes a pool of 16 shift registers that may

be configured to operate as either transmit data, receive data, or general-purpose I/O (GPIO).

The transmit section of the McASP can transmit data in either a time-division-multiplexed (TDM) synchronous

serial format or in a digital audio interface (DIT) format where the bit stream is encoded for S/PDIF, AES-3,

IEC-60958, CP-430 transmission. The receive section of the McASP supports the TDM synchronous serial

format.

Each McASP can support one transmit data format (either a TDM format or DIT format) and one receive format

at a time. All transmit shift registers use the same format and all receive shift registers use the same format.

However, the transmit and receive formats need not be the same.

Both the transmit and receive sections of the McASP also support burst mode which is useful for non-audio data

(for example, passing control information between two DSPs).

The McASP peripherals have additional capability for flexible clock generation, and error detection/handling,

as well as error management.

McASP block diagram

Figure 16 illustrates the major blocks along with external signals of the McASP1 and McASP0 peripherals; and

shows the 8 serial data [AXR] pins for each McASP. Each McASP also includes full general-purpose I/O (GPIO)

control, so any pins not needed for serial transfers can be used for general-purpose I/O.

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

multichannel audio serial port (McASP) peripherals (continued)

McASP0

McASP1

Transmit

DIT

RAM

DIT

RAM

Frame Sync

Generator

AFSX0

Frame Sync

Generator

AFSX1

Transmit

Clock Check

(High-

Transmit

Clock Check

(High-

Transmit

Clock

Generator

Transmit

Clock

Generator

AHCLKX0

ACLKX0

AHCLKX1

ACLKX1

Frequency)

AMUTE0

AMUTE1

Error

Detect

AMUTEIN0

AMUTEIN1

Receive

Clock Check

(High-

Receive

Clock Check

(High-

Receive

Clock

Generator

Receive

Clock

Generator

AHCLKR0

ACLKR0

AHCLKR1

ACLKR1

Frequency)

Transmit

Data

Formatter

Receive

Frame Sync

Generator

Transmit

Data

Formatter

Receive

Frame Sync

Generator

AFSR0

AFSR1

Serializer 0

AXR0[0]

AXR0[1]

AXR0[2]

AXR0[3]

AXR0[4]

AXR0[5]

AXR0[6]

AXR0[7]

AXR1[0]

AXR1[1]

AXR1[2]

AXR1[3]

AXR1[4]

AXR1[5]

AXR1[6]

AXR1[7]

Serializer 1

Serializer 2

Serializer 3

Serializer 4

Serializer 5

Serializer 6

Serializer 7

Serializer 1

Serializer 2

Serializer 3

Serializer 4

Serializer 5

Serializer 6

Serializer 7

Receive

Data

Formatter

Receive

Data

Formatter

GPIO

Control

GPIO

Control

Figure 16. McASP0 and McASP1 Configuration

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

multichannel audio serial port (McASP) peripherals (continued)

multichannel time division multiplexed (TDM) synchronous transfer mode

The McASP supports a multichannel, time-division-multiplexed (TDM) synchronous transfer mode for both

transmit and receive. Within this transfer mode, a wide variety of serial data formats are supported, including

formats compatible with devices using the Inter-Integrated Sound (IIS) protocol.

TDM synchronous transfer mode is typically used when communicating between integrated circuits such as

between a DSP and one or more ADC, DAC, CODEC, or S/PDIF receiver devices. In multichannel applications,

it is typical to find several devices operating synchronized with each other. For example, to provide six analog

outputs, three stereo DAC devices would be driven with the same bit clock and frame sync, but each stereo DAC

would use a different McASP serial data pin carrying stereo data (2 TDM time slots, left and right).

The TDM synchronous serial transfer mode utilizes several control signals and one or more serial data signals:

D

A bit clock signal (ACLKX for transmit, ACKLR for receive)

A frame sync signal (AFSX for transmit, AFSR for receive)

An (Optional) high frequency master clock (AHCLKX for transmit, AHCLKR for receive) from which the bit

clock is derived

One or more serial data pins (AXR for transmit and for receive).

Except for the optional high-frequency master clock, all of the signals in the TDM synchronous serial transfer

mode protocol are synchronous to the bit clocks (ACLKX and ACLKR).

In the TDM synchronous transfer mode, the McASP continually transmits and receives data periodically (since

audio ADCs and DACs operate at a fixed-data rate). The data is organized into frames, and the beginning of

a frame is marked by a frame sync pulse on the AFSX, AFSR pin.

In a typical audio system, one frame is transferred per sample period. To support multiple channels, the choices

are to either include more time slots per frame (and therefore operate with a higher bit clock) or to keep the bit

clock period constant and use additional data pins to transfer the same number of channels. For example, a

particular six-channel DAC might require three McASP serial data pins; transferring two channels of data on

each serial data pin during each sample period (frame). Another similar DAC may be designed to use only a

single McASP serial data pin, but clocked three times faster and transferring six channels of data per sample

period. The McASP is flexible enough to support either type of DAC but a transmitter cannot be configured to

do both at the same time.

For multiprocessor applications, the McASP supports any number of time slots per frame (between 2 and 32),

and includes the ability to “disable” transfers during specific time slots.

In addition, to support of S/PDIF, AES-3, IEC-60958, CP-430 receivers chips whose natural block (McASP

frame) size is 384 samples; the McASP receiver supports a 384 time slot mode. The advantage to using the

384 time slot mode is that interrupts may be generated synchronous to the S/PDIF, AES-3, IEC-60958, CP-430

receivers, for example the “last slot” interrupt.

burst transfer mode

The McASP also supports a burst transfer mode, which is useful for non-audio data (for example, passing

control information between two DSPs). Burst transfer mode uses a synchronous serial format similar to TDM,

except the frame sync is generated for each data word transferred. In addition, frame sync generation is not

periodic or time-driven as in TDM mode but rather data-driven.

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

multichannel audio serial port (McASP) peripherals (continued)

supported bit stream formats for TDM and burst transfer modes

The serial data pins support a wide variety of formats. In the TDM and burst synchronous modes, the data may

be transmitted / received with the following options:

D

Time slots per frame: 1 (Burst/Data Driven), or 2,3...32 (TDM/Time-Driven).

Time slot size: 8, 12, 16, 20, 24, 28, 32 bits per time slot

Data size: 8, 12, 16, 20, 24, 28, 32 bits (must be less than or equal to time slot)

Data alignment within time slot: Left- or Right-Justified

Bit order: MSB or LSB first.

Unused bits in time slot: Padded with 0, 1 or extended with value of another bit.

Time slot delay from frame sync: 0,1, or 2 bit delay

The data format can be programmed independently for transmit and receive, and for McASP0 vs. McASP1. In

addition, the McASP can automatically re-align the data as processed natively by the DSP (any format on a

nibble boundary) adjusting the data in hardware to any of the supported serial bit stream formats (TDM, Burst,

and DIT modes). This reduces the amount of bit manipulation that the DSP must perform and simplifies software

architecture.

digital audio interface transmitter (DIT) transfer mode (transmitter only)

The McASP transmit section may also be configured in digital audio interface transmitter (DIT) mode where it

outputs data formatted for transmission over an S/PDIF, AES-3, IEC-60958, or CP-430 standard link. These

standards encode the serial data such that the equivalent of ’clock’ and ’frame sync’ are embedded within the

data stream. DIT transfer mode is used as an interconnect between audio components and can transfer

multichannel digital audio data over a single optical or coaxial cable.

From an internal DSP standpoint, the McASP operation in DIT transfer mode is similar to the two time slot TDM

mode, but the data transmitted is output as a bi-phase mark encoded bit stream with preamble, channel status,

user data, validity, and parity automatically stuffed into the bit stream by the McASP module. The McASP

includes separate validity bits for even/odd subframes and two 384-bit register file modules to hold channel

status and user data bits.

DIT mode requires at minimum:

D

One serial data pin (if the AUXCLK is used as the reference [see the PLL and Clock Generator Logic

Figure 15]) or

One serial data pin plus either the AHCLKX or ACLKX pin (if an external clock is needed).

If additional serial data pins are used, each McASP may be used to transmit multiple encoded bit streams (one

per pin). However, the bit streams will all be synchronized to the same clock and the user data, channel status,

and validity information carried by each bit stream will be the same for all bit streams transmitted by the same

McASP module.

The McASP can also automatically re-align the data as processed by the DSP (any format on a nibble boundary)

in DIT mode; reducing the amount of bit manipulation that the DSP must perform and simplifies software

architecture.

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

multichannel audio serial port (McASP) peripherals (continued)

McASP flexible clock generators

The McASP transmit and receive clock generators are identical. Each clock generator can accept a

high-frequency master clock input (on the AHCLKX and AHCLKR pins).

The transmit and receive bit clocks (on the ACLKX and ACLKR pins) can also be sourced externally or can be

sourced internally by dividing down the high-frequency master clock input (programmable factor /1, /2, /3, ...

/4096). The polarity of each bit clock is individually programmable.

The frame sync pins are AFSX (transmit) and AFSR (receive). A typical usage for these pins is to carry the

left-right clock (LRCLK) signal when transmitting and receiving stereo data. The frame sync signals are

individually programmable for either internal or external generation, either bit or slot length, and either rising or

falling edge polarity.

Some examples of the things that a system designer can use the McASP clocking flexibility for are:

D

Input a high-frequency master clock (for example, 512f of the receiver), receive with an internally

s

generated bit clock ratio of /8, while transmitting with an internally generated bit clock ratio of /4 or /2. [An

example application would be to receive data from a DVD at 48 kHz but output up-sampled or decoded

audio at 96 kHz or 192 kHz.]

D

Transmit/receive data based one sample rate (for example, 44.1 kHz) using McASP0 while transmitting and

receiving at a different sample rate (for example, 48 kHz) on McASP1.

Use the DSP’s on-board AUXCLK to supply the system clock when the input source is an A/D converter.

McASP error handling and management

To support the design of a robust audio system, the McASP module includes error-checking capability for the

serial protocol, data underrun, and data overrun. In addition, each McASP includes a timer that continually

measures the high-frequency master clock every 32-SYSCLK2 clock cycles. The timer value can be read to

get a measurement of the high-frequency master clock frequency and has a min-max range setting that can

raise an error flag if the high-frequency master clock goes out of a specified range. The user would read the

high-frequency transmit master clock measurement (AHCLKX0 or AHCLKX1) by reading the XCNT field of the

XCLKCHK register and the user would read the high-frequency receive master clock measurement (AHCLKR0

or AHCLKR1) by reading the RCNT field of the RCLKCHK register.

Upon the detection of any one or more of the above errors (software selectable), or the assertion of the

AMUTE_IN pin, the AMUTE output pin may be asserted to a high or low level (selectable) to immediately mute

the audio output. In addition, an interrupt may be generated if enabled based on any one or more of the error

sources.

McASP interrupts and EDMA events

The McASP transmitter and receiver sections each generate an event on every time slot. This event can be

serviced by an interrupt or by the EDMA controller.

When using interrupts to service the McASP, each shift register buffer has a unique address in the McASP

Registers space (see Table 3).

When using the EDMA to service the McASP, the McASP DATA Port space in Table 3 is accessed. In this case,

the address least-significant bits are ignored. Writes to any address in this range access the transmitting buffers

in order from lowest (serializer 0) to highest (serializer 15), skipping over disabled and receiving serializers.

Likewise, reads from any address in this space access the receiving buffers in the same order but skip over

disabled and transmitting buffers.

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

I2C

Having two I2C modules on the TMS320C6713B simplifies system architecture, since one module may be used

by the DSP to control local peripherals ICs (DACs, ADCs, etc.) while the other may be used to communicate

with other controllers in a system or to implement a user interface.

The TMS320C6713B also includes two I2C serial ports for control purposes. Each I2C port supports:

2

D

Compatible with Philips I C Specification Revision 2.1 (January 2000)

Fast Mode up to 400 Kbps (no fail-safe I/O buffers)

Noise Filter to Remove Noise 50 ns or less

Seven- and Ten-Bit Device Addressing Modes

Master (Transmit/Receive) and Slave (Transmit/Receive) Functionality

Events: DMA, Interrupt, or Polling

Slew-Rate Limited Open-Drain Output Buffers

Figure 17 is a block diagram of the I2Cx module.

I2Cx Module

Clock

SYSCLK2

Prescale

From PLL

Clock Generator

I2CPSCx

Bit Clock

Control

Generator

SCL

Noise

Own

Address

I2C Clock

Filter

I2CCLKHx

I2CCLKLx

I2COARx

I2CSARx

I2CMDRx

I2CCNTx

Slave

Address

Mode

Transmit

I2CXSRx

Data

Count

Transmit

Shift

Transmit

Buffer

I2CDXRx

SDA

Interrupt/DMA

I2CIERx

Noise

Filter

I2C Data

Interrupt

Enable

Receive

Buffer

I2CDRRx

Interrupt

Status

I2CSTRx

Interrupt

Source

Receive

Shift

I2CRSRx

I2CISRCx

NOTE A: Shading denotes control/status registers.

Figure 17. I2Cx Module Block Diagram

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

general-purpose input/output (GPIO)

To use the GP[15:0] software-configurable GPIO pins, the GPxEN bits in the GP Enable (GPEN) Register and

the GPxDIR bits in the GP Direction (GPDIR) Register must be properly configured.

GPxEN =

GPxDIR =

1

0

1

GP[x] pin is enabled

GP[x] pin is an input

GP[x] pin is an output

where “x” represents one of the 15 through 0 GPIO pins

Figure 18 shows the GPIO enable bits in the GPEN register for the C6713B device. To use any of the GPx pins

as general-purpose input/output functions, the corresponding GPxEN bit must be set to “1” (enabled). Default

values are device-specific, so refer to Figure 18 for the C6713B default configuration.

31

24 23

Reserved

R-0

16

15

GP15 GP14 GP13 GP12 GP11 GP10

EN EN EN EN EN EN

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

GP9

EN

GP8

EN

GP7

EN

GP6

EN

GP5

EN

GP4

EN

GP3

EN

GP2

EN

GP1

EN

GP0

EN

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0

Legend: R/W = Readable/Writeable; -n = value after reset, -x = undefined value after reset

Figure 18. GPIO Enable Register (GPEN) [Hex Address: 01B0 0000]

Figure 19 shows the GPIO direction bits in the GPDIR register. This register determines if a given GPIO pin is

an input or an output providing the corresponding GPxEN bit is enabled (set to “1”) in the GPEN register. By

default, all the GPIO pins are configured as input pins.

31

24 23

Reserved

R-0

16

15

GP15 GP14 GP13 GP12 GP11 GP10

DIR DIR DIR DIR DIR DIR

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

GP9

DIR

GP8

DIR

GP7

DIR

GP6

DIR

GP5

DIR

GP4

DIR

GP3

DIR

GP2

DIR

GP1

DIR

GP0

DIR

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

Legend: R/W = Readable/Writeable; -n = value after reset, -x = undefined value after reset

Figure 19. GPIO Direction Register (GPDIR) [Hex Address: 01B0 0004]

For more detailed information on general-purpose inputs/outputs (GPIOs), see the TMS320C6000 DSP

General-Purpose Input/Output (GPIO) Reference Guide (literature number SPRU584).

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

power-down mode logic

Figure 20 shows the power-down mode logic on the C6713B.

CLKOUT2

Internal Clock Tree

Clock

Distribution

and Dividers

PD1

PD2

IFR

Power-

Down

Logic

Clock

PLL

Internal

Peripherals

IER

CSR

PWRD

CPU

PD3

TMS320C6713B

CLKIN

RESET

†

External input clocks, with the exception of CLKIN and CLKOUT3, are not gated by the power-down mode logic.

†

Figure 20. Power-Down Mode Logic

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

triggering, wake-up, and effects

The device includes a programmable PLL which allows software control of PLL bypass via the PLLEN bit in the

PLLCSR register. With this enhanced functionality come some additional considerations when entering

power−down modes.

The power−down modes (PD2 and PD3) function by disabling the PLL to stop clocks to the C6713 device.

However, if the PLL is bypassed (PLLEN = 0), the device will still receive clocks from the external clock input

(CLKIN). Therefore, bypassing the PLL makes the power−down modes PD2 and PD3 ineffective.

The PLL needs to be enabled by writing a “1” to PLLEN bit (PLLCSR.0) before being able to enter either PD3

(CSR.11) or PD2 (CSR.10) in order for these modes to have an effect.

For the TMS320C6713B device it is recommended to use the PLLPWDN bit (PLLCSR.1) to enter a deep

power−down state equivalent to PD3 since the PLLPWDN bit takes full advantage of the PLL power−down

feature.

The power−down modes (PD1, PD2, and PD3) and their wake−up methods are programmed by setting the

PWRD field (bits 15−10) of the control status register (CSR). The PWRD field of the CSR is shown in Figure 21

and described in Table 44. When writing to the CSR, all bits of the PWRD field should be set at the same time.

Logic 0 should be used when “writing” to the reserved bit (bit 15) of the PWRD field. The CSR is discussed in

detail in the TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189).

31

16

15

14

13

12

11

10

9

8

Enable or

Non-Enabled

Interrupt Wake

Enabled

Interrupt Wake

Reserved

R/W-0

PD3

PD2

PD1

R/W-0

7

0

Legend: R/W−x = Read/write reset value

NOTE: The shadowed bits are not part of the power-down logic discussion and therefore are not covered here. For information on these other

bit fields in the CSR register, see the TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189).

Figure 21. PWRD Field of the CSR Register

A delay of up to nine clock cycles may occur after the instruction that sets the PWRD bits in the CSR before the

PD mode takes effect. As best practice, NOPs should be padded after the PWRD bits are set in the CSR to account

for this delay.

If PD1 mode is terminated by a non-enabled interrupt, the program execution returns to the instruction where PD1

took effect. If PD1 mode is terminated by an enabled interrupt, the interrupt service routine will be executed first,

then the program execution returns to the instruction where PD1 took effect. In the case with an enabled interrupt,

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

the GIE bit in the CSR and the NMIE bit in the interrupt enable register (IER) must also be set in order for the

interrupt service routine to execute; otherwise, execution returns to the instruction where PD1 took effect upon

PD1 mode termination by an enabled interrupt.

PD2 and PD3 modes can only be aborted by device reset. Table 44 summarizes all the power-down modes.

Table 44. Characteristics of the Power-Down Modes

PRWD FIELD

(BITS 15−10)

POWER-DOWN

MODE

WAKE-UP METHOD

—

EFFECT ON CHIP’S OPERATION

000000

No power-down

PD1

—

CPU halted (except for the interrupt logic)

001001

Wake by an enabled interrupt

Power-down mode blocks the internal clock inputs at the

boundary of the CPU, preventing most of the CPU’s logic from

switching. During PD1, EDMA transactions can proceed

between peripherals and internal memory.

Wake by an enabled or

non-enabled interrupt

010001

PD1

Output clock from PLL is halted, stopping the internal clock

structure from switching and resulting in the entire chip being

halted. All register and internal RAM contents are preserved. All

functional I/O “freeze” in the last state when the PLL clock is

turned off.

†

PD2

011010

Wake by a device reset

Input clock to the PLL stops generating clocks. All register and

internal RAM contents are preserved. All functional I/O freeze in

the last state when the PLL clock is turned off. Following reset, the

PLL needs time to re−lock, just as it does following power−up.

Wake−up from PD3 takes longer than wake−up from PD2

because the PLL needs to be re−locked, just as it does following

power−up.

†

PD3

011100

Wake by a device reset

It is recommended to use the PLLPWDN bit (PLLCSR.1) as an

alternative to PD3.

All others

Reserved

—

†

When entering PD2 and PD3, all functional I/O remains in the previous state. However, for peripherals which are asynchronous in nature or

peripherals with an external clock source, output signals may transition in response to stimulus on the inputs. Under these conditions,

peripherals will not operate according to specifications.

power-supply sequencing

TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However,

systems should be designed to ensure that neither supply is powered up for extended periods of time

(>1 second) if the other supply is below the proper operating voltage.

system-level design considerations

System-level design considerations, such as bus contention, may require supply sequencing to be

implemented. In this case, the core supply should be powered up prior to (and powered down after), the I/O

buffers. This is to ensure that the I/O buffers receive valid inputs from the core before the output buffers are

powered up, thus, preventing bus contention with other chips on the board.

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

power-supply design considerations

A dual-power supply with simultaneous sequencing can be used to eliminate the delay between core and I/O

power up. A Schottky diode can also be used to tie the core rail to the I/O rail (see Figure 22).

I/O Supply

DV

DD

Schottky

Diode

C6000

DSP

Core Supply

CV

DD

V

SS

GND

Figure 22. Schottky Diode Diagram

Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize

inductance and resistance in the power delivery path. Additionally, when designing for high-performance

applications utilizing the C6000 platform of DSPs, the PC board should include separate power planes for

core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors.

power-supply decoupling

In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as possible

close to the DSP. Assuming 0603 caps, the user should be able to fit a total of 60 caps — 30 for the core supply

and 30 for the I/O supply. These caps need to be close (no more than 1.25 cm maximum distance) to the DSP

to be effective. Physically smaller caps are better, such as 0402, but the size needs to be evaluated from a

yield/manufacturing point-of-view. Parasitic inductance limits the effectiveness of the decoupling capacitors,

therefore physically smaller capacitors should be used while maintaining the largest available capacitance

value. As with the selection of any component, verification of capacitor availability over the product’s production

lifetime needs to be considered.

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

IEEE 1149.1 JTAG compatibility statement

The TMS320C6713B DSP requires that both TRST and RESET resets be asserted upon power up to be

properly initialized. While RESET initializes the DSP core, TRST initializes the DSP’s emulation logic. Both

resets are required for proper operation.

Note: TRST is synchronous and must be clocked by TCLK; otherwise, BSCAN may not respond as expected

after TRST is asserted.

While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for the

DSP to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG port interface

and DSP’s emulation logic in the reset state. TRST only needs to be released when it is necessary to use a JTAG

controller to debug the DSP or exercise the DSP’s boundary scan functionality.

The TMS320C6713B DSP includes an internal pulldown (IPD) on the TRST pin to ensure that TRST will always

be asserted upon power up and the DSP’s internal emulation logic will always be properly initialized when this

pin is not routed out. JTAG controllers from Texas Instruments actively drive TRST high. However, some

third-party JTAG controllers may not drive TRST high but expect the use of an external pullup resistor on TRST.

When using this type of JTAG controller, assert TRST to initialize the DSP after powerup and externally drive

TRST high before attempting any emulation or boundary scan operations.

Following the release of RESET, the low-to-high transition of TRST must be “seen” to latch the state of EMU1

and EMU0. The EMU[1:0] pins configure the device for either Boundary Scan mode or Emulation mode. For

more detailed information, see the terminal functions section of this data sheet.

Note: The DESIGN−WARNING section of the TMS320C6713B BSDL file contains information and constraints

regarding proper device operation while in Boundary Scan Mode.

For more detailed information on the C6713B JTAG emulation, see the TMS320C6000 DSP Designing for JTAG

Emulation Reference Guide (literature number SPRU641).

EMIF device speed

The maximum EMIF speed on the C6713B device is 100 MHz. TI recommends utilizing I/O buffer information

specification (IBIS) to analyze all AC timings to determine if the maximum EMIF speed is achievable for a given

board layout. To properly use IBIS models to attain accurate timing analysis for a given system, see the Using

IBIS Models for Timing Analysis application report (literature number SPRA839).

For ease of design evaluation, Table 45 contains IBIS simulation results showing the maximum EMIF-SDRAM

interface speeds for the given example boards (TYPE) and SDRAM speed grades. Timing analysis should be

performed to verify that all AC timings are met for the specified board layout. Other configurations are also

possible, but again, timing analysis must be done to verify proper AC timings.

To maintain signal integrity, serial termination resistors should be inserted into all EMIF output signal lines (see

the Terminal Functions table for the EMIF output signals).

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

Table 45. C6713B Example Boards and Maximum EMIF Speed

BOARD CONFIGURATION

MAXIMUM ACHIEVABLE

EMIF-SDRAM

SDRAM SPEED GRADE

EMIF INTERFACE

TYPE

BOARD TRACE

COMPONENTS

INTERFACE SPEED

143 MHz 32-bit SDRAM (−7)

166 MHz 32-bit SDRAM (−6)

100 MHz

For short traces, SDRAM data

output hold time on these

SDRAM speed grades cannot

meet EMIF input hold time

requirement (see NOTE 1).

1 to 3-inch traces with proper

termination resistors;

Trace impedance ~ 50 Ω

1-Load

Short Traces

One bank of one

32-Bit SDRAM

183 MHz 32-bit SDRAM (−55)

200 MHz 32-bit SDRAM (−5)

125 MHz 16-bit SDRAM (−8E)

133 MHz 16-bit SDRAM (−75)

143 MHz 16-bit SDRAM (−7E)

167 MHz 16-bit SDRAM (−6A)

167 MHz 16-bit SDRAM (−6)

100 MHz

1.2 to 3 inches from EMIF to

each load, with proper

termination resistors;

2-Loads

Short Traces

One bank of two

16-Bit SDRAMs

Trace impedance ~ 78 Ω

For short traces, EMIF cannot

meet SDRAM input hold

125 MHz 16-bit SDRAM (−8E)

requirement (see NOTE 1).

1.2 to 3 inches from EMIF to

each load, with proper

termination resistors;

133 MHz 16-bit SDRAM (−75)

143 MHz 16-bit SDRAM (−7E)

167 MHz 16-bit SDRAM (−6A)

100 MHz

One bank of two

16-Bit SDRAMs

One bank of buffer

3-Loads

Short Traces

Trace impedance ~ 78 Ω

For short traces, EMIF cannot

meet SDRAM input hold

167 MHz 16-bit SDRAM (−6)

requirement (see NOTE 1).

143 MHz 32-bit SDRAM (−7)

166 MHz 32-bit SDRAM (−6)

183 MHz 32-bit SDRAM (−55)

83 MHz

One bank of one

32-Bit SDRAM

One bank of one

32-Bit SBSRAM

One bank of buffer

3-Loads

Long Traces

4 to 7 inches from EMIF;

Trace impedance ~ 63 Ω

SDRAM data output hold time

cannot meet EMIF input hold

requirement (see NOTE 1).

200 MHz 32-bit SDRAM (−5)

NOTE 1: Results are based on IBIS simulations for the given example boards (TYPE). Timing analysis should be performed to determine if timing

requirements can be met for the particular system.

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

EMIF big endian mode correctness

The HD8 pin device endian mode (LENDIAN) selects the endian mode of operation (Little or Big Endian). For

the C6713B device Little Endian is the default setting.

The HD12 pin (EMIF Big Endian Mode Correctness) [EMIFBE] enhancement allows the flexibility to change the

EMIF data placement on the EMIF bus.

When using the default setting of HD12 = 1 for the C6713B, the EMIF will present 8-bit or 16-bit data on the

ED[7:0] side of the bus if using Little Endian mode (HD8 = 1) and to the ED[31:24] side of the bus if using Big

Endian mode. Figure 23 shows the mapping of 16-bit and 8-bit C6713B devices.

EMIF DATA LINES (PINS) WHERE DATA PRESENT

ED[31:24] (BE3)

ED[23:16] (BE2)

32-Bit Device in Any Endianness Mode

16-Bit Device in Big Endianness Mode 16-Bit Device in Little Endianness Mode

ED[15:8] (BE1)

ED[7:0] (BE0)

8-Bit Device in Big

Endianness Mode

8-Bit Device in Little Endianness Mode

Figure 23. 16/8-Bit EMIF Big Endian Mode Correctness Mapping (HD12 = 1)

When HD12 = 0, enabling EMIF endianness correction, the EMIF will present 8-bit or 16-bit data on the ED[7:0]

side of the bus, regardless of the endianess mode (see Figure 24).

EMIF DATA LINES (PINS) WHERE DATA PRESENT

ED[31:24] (BE3)

ED[23:16] (BE2)

32-Bit Device in Any Endianness Mode

16-Bit Device in Any Endianness Mode

8-Bit Device in Any Endianness Mode

ED[15:8] (BE1)

ED[7:0] (BE0)

Figure 24. 16/8-Bit EMIF Big Endian Mode Correctness Mapping (HD12 = 0)

This new endianness correction functionality does not affect systems using the default value of HD12 = 1.

This new feature does not affect systems operating in Little Endian mode.

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

bootmode

The device resets using the active-low signal RESET and the internal reset signal. While RESET is low, the

internal reset is also asserted and the device is held in reset and is initialized to the prescribed reset state. Refer

to reset timing for reset timing characteristics and states of device pins during reset. The release of the internal

reset signal (see the Reset Phase 3 discussion in the Reset Timing section of this data sheet) starts the

processor running with the prescribed device configuration and boot mode.

The C6713B has three types of boot modes:

D

Host boot

If host boot is selected, upon release of internal reset, the CPU is internally “stalled” while the remainder of

the device is released. During this period, an external host can initialize the CPU’s memory space as

necessary through the host interface, including internal configuration registers, such as those that control

the EMIF or other peripherals. Once the host is finished with all necessary initialization, it must set the

DSPINT bit in the HPIC register to complete the boot process. This transition causes the boot configuration

logic to bring the CPU out of the “stalled” state. The CPU then begins execution from address 0. The DSPINT

condition is not latched by the CPU, because it occurs while the CPU is still internally “stalled”. Also, DSPINT

brings the CPU out of the “stalled” state only if the host boot process is selected. All memory may be written

to and read by the host. This allows for the host to verify what it sends to the DSP if required. After the CPU is

out of the “stalled” state , the CPU needs to clear the DSPINT, otherwise, no more DSPINTs can be received.

D

Emulation boot

Emulation boot mode is a variation of host boot. In this mode, it is not necessary for a host to load code or to

set DSPINT to release the CPU from the “stalled” state. Instead, the emulator will set DSPINT if it has not

been previously set so that the CPU can begin executing code from address 0. Prior to beginning execution,

the emulator sets a breakpoint at address 0. This prevents the execution of invalid code by halting the CPU

prior to executing the first instruction. Emulation boot is a good tool in the debug phase of development.

EMIF boot (using default ROM timings)

Upon the release of internal reset, the 1K-Byte ROM code located in the beginning of CE1 is copied to

address 0 by the EDMA using the default ROM timings, while the CPU is internally “stalled”. The data should

be stored in the endian format that the system is using. The boot process also lets you choose the width of

the ROM. In this case, the EMIF automatically assembles consecutive 8-bit bytes or 16-bit half-words to

form the 32-bit instruction words to be copied. The transfer is automatically done by the EDMA as a

single-frame block transfer from the ROM to address 0. After completion of the block transfer, the CPU is

released from the “stalled” state and start running from address 0.

reset

A hardware reset (RESET) is required to place the DSP into a known good state out of power−up. The RESET

signal can be asserted (pulled low) prior to ramping the core and I/O voltages or after the core and I/O voltages

have reached their proper operating conditions. As a best practice, reset should be held low during power−up.

Prior to deasserting RESET (low−to−high transition), the core and I/O voltages should be at their proper

operating conditions and CLKIN should also be running at the correct frequency.

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

†

absolute maximum ratings over operating case temperature range (unless otherwise noted)

Supply voltage range, CV

Supply voltage range, DV

(see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 1.8 V

(see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V

DD

Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to DV

Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to DV

+ 0.5 V

DD

Operating case temperature ranges, T : (default) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0_C to 90_C

C

(A version) [GDPA/ZDPA-200, PYPA-167,-200] −40_C to105_C

Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65_C to 150_C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 2: All voltage values are with respect to V

SS

.

†

recommended operating conditions

MIN

NOM

MAX

1.32

1.47

3.47

UNIT

PYP packages only

1.14

1.20

V

‡

1.14

‡

1.20

GDP/ZDP packages for C6713B only

GDP/ZDP packages for C6713B−300 only

CV

DV

Supply voltage, Core referenced to V

SS

DD

1.33

3.13

1.4

3.3

Supply voltage, I/O referenced to V

SS

All signals except CLKS1/SCL1,

DR1/SDA1, SCL0, SDA0, and RESET

2

V

High-level input voltage (See Figure 28)

Low-level input voltage (See Figure 29)

IH

CLKS1/SCL1, DR1/SDA1, SCL0, SDA0,

and RESET

All signals except CLKS1/SCL1,

DR1/SDA1, SCL0, SDA0, and RESET

0.8

V

IL

CLKS1/SCL1, DR1/SDA1, SCL0, SDA0,

and RESET

0.3*DV

DD

All signals except ECLKOUT, CLKOUT2,

CLKS1/SCL1, DR1/SDA1, SCL0, and

SDA0

−8

mA

§

High-level output current

I

OH

ECLKOUT and CLKOUT2

−16

8

All signals except ECLKOUT, CLKOUT2,

CLKS1/SCL1, DR1/SDA1, SCL0, and

SDA0

§

Low-level output current

OL

ECLKOUT and CLKOUT2

16

3

mA

CLKS1/SCL1, DR1/SDA1, SCL0, and

SDA0

¶

V

Maximum voltage during overshoot (See Figure 28)

Maximum voltage during undershoot (See Figure 29)

Default

4

V

OS

¶

−0.7

US

0

90

105

T

C

Operating case temperature

_C

A version (GDPA/ZDPA -200,

PYPA-167,−200)

–40

†

The core supply should be powered up prior to (and powered down after), the I/O supply. Systems should be designed to ensure that neither

supply is powered up for an extended period of time if the other supply is below the proper operating voltage.

These values are compatible with existing 1.26-V designs.

Refers to DC (or steady state) currents only, actual switching currents are higher. For more details, see the device-specific IBIS models.

The absolute maximum ratings should not be exceeded for more than 30% of the cycle period.

‡

§

¶

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

electrical characteristics over recommended ranges of supply voltage and operating case

†

temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

High-level output

voltage

All signals except SCL1, SDA1,

SCL0, and SDA0

V

I

=MAX

2.4

V

OH

OL

OH

All signals except SCL1, SDA1,

SCL0, and SDA0

I

= MAX

0.4

170

10

V

Low-level output

voltage

OL

V

SCL1, SDA1, SCL0, and SDA0

OL

All signals except SCL1, SDA1,

SCL0, and SDA0

uA

mA

I

Input current

V = V

SS

to DV

DD

I

SCL1, SDA1, SCL0, and SDA0

All signals except SCL1, SDA1,

SCL0, and SDA0

170

10

Off-state output

current

V

= DV or 0 V

DD

OZ

O

SCL1, SDA1, SCL0, and SDA0

GDP/ZDP, CV

DD

CPU clock = 300 MHz

= 1.4 V,

945

625

560

565

GDP/ZDP/PYP, CV

1.26 V, CPU clock = 225

MHz

=

DD

mA

GDPA/ZDPA, CV

CPU clock = 200 MHz

=1.26V

DD

‡

I

DD2V

Core supply current

GDPA/ZDPA/PYP/ PYPA

CV

200 MHz

=1.2 V CPU clock =

DD

PYPA, CV

clock = 167 MHz

=1.2 V CPU

DD

480

75

mA

DV = 3.3 V, EMIF speed

DD

= 100 MHz

‡

I

DD3V

I/O supply current

C

Input capacitance

7

pF

i

Output capacitance

o

†

‡

For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table.

Measured with average activity (50% high/50% low power) at 25°C case temperature and 100-MHz EMIF. This model represents a device

performing high-DSP-activity operations 50% of the time, and the remainder performing low-DSP-activity operations. The high/low-DSP-activity

models are defined as follows:

High-DSP-Activity Model:

CPU: 8 instructions/cycle with 2 LDDW instructions [L1 Data Memory: 128 bits/cycle via LDDW instructions;

L1 Program Memory: 256 bits/cycle; L2/EMIF EDMA: 50% writes, 50% reads to/from SDRAM (50% bit-switching)]

McBSP: 2 channels at E1 rate

Timers: 2 timers at maximum rate

Low-DSP-Activity Model:

CPU: 2 instructions/cycle with 1 LDH instruction [L1 Data Memory: 16 bits/cycle; L1 Program Memory: 256 bits per 4 cycles;

L2/EMIF EDMA: None]

McBSP: 2 channels at E1 rate

Timers: 2 timers at maximum rate

The actual current draw is highly application-dependent. For more details on core and I/O activity, refer to the TMS320C6711D, C6712D, C6713B

Power Consumption Summary application report (literature number SPRA889A2 or later).

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

PARAMETER MEASUREMENT INFORMATION

Tester Pin Electronics

Data Sheet Timing Reference Point

42 W

3.5 nH

Output

Under

Test

Transmission Line

Z0 = 50 W

(see note)

Device Pin

(see note)

4.0 pF

1.85 pF

NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects

must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect.

The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from

the data sheet timings.

Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.

Figure 25. Test Load Circuit for AC Timing Measurements

signal transition levels

All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels.

V

ref

= 1.5 V

Figure 26. Input and Output Voltage Reference Levels for AC Timing Measurements

All rise and fall transition timing parameters are referenced to V MAX and V MIN for input clocks, V MAX

IL

IH

OL

and V

MIN for output clocks.

OH

V

= V MIN (or V

IH OH

MIN)

MAX)

ref

V

ref

= V MAX (or V

IL OL

Figure 27. Rise and Fall Transition Time Voltage Reference Levels

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

PARAMETER MEASUREMENT INFORMATION (CONTINUED)

AC transient rise/fall time specifications

Figure 28 and Figure 29 show the AC transient specifications for Rise and Fall Time. For device-specific

information on these values, refer to the Recommended Operating Conditions section of this Data Sheet.

†

t = 0.3 t (max)

c

V

OS

(max)

Minimum

Risetime

V

IH

(min)

Waveform

Valid Region

Ground

Figure 28. AC Transient Specification Rise Time

†

t = the peripheral cycle time.

c

†

t = 0.3 t (max)

c

V

IL

(max)

V

US

(max)

Ground

Figure 29. AC Transient Specification Fall Time

†

t = the peripheral cycle time.

c

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

PARAMETER MEASUREMENT INFORMATION (CONTINUED)

timing parameters and board routing analysis

The timing parameter values specified in this data sheet do not include delays by board routings. As a good

board design practice, such delays must always be taken into account. Timing values may be adjusted by

increasing/decreasing such delays. TI recommends utilizing the available I/O buffer information specification

(IBIS) models to analyze the timing characteristics correctly. To properly use IBIS models to attain accurate

timing analysis for a given system, see the Using IBIS Models for Timing Analysis application report (literature

number SPRA839). If needed, external logic hardware such as buffers may be used to compensate any timing

differences.

For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external device and

from the external device to the DSP. This round-trip delay tends to negatively impact the input setup time margin,

but also tends to improve the input hold time margins (see Table 46 and Figure 30).

Figure 30 represents a general transfer between the DSP and an external device. The figure also represents

board route delays and how they are perceived by the DSP and the external device.

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

PARAMETER MEASUREMENT INFORMATION (CONTINUED)

Table 46. Board-Level Timings Example (see Figure 30)

NO.

1

DESCRIPTION

Clock route delay

2

Minimum DSP hold time

3

Minimum DSP setup time

External device hold time requirement

External device setup time requirement

Control signal route delay

External device hold time

4

5

6

7

8

External device access time

DSP hold time requirement

DSP setup time requirement

Data route delay

9

10

11

ECLKOUT

(Output from DSP)

1

ECLKOUT

(Input to External Device)

2

3

†

Control Signals

(Output from DSP)

4

5

6

Control Signals

(Input to External Device)

7

8

‡

Data Signals

(Output from External Device)

9

10

11

‡

Data Signals

(Input to DSP)

† Control signals include data for Writes.

‡ Data signals are generated during Reads from an external device.

Figure 30. Board-Level Input/Output Timings

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

INPUT AND OUTPUT CLOCKS

†‡§

timing requirements for CLKIN for PYP-200 and GDP/ZDP-225

(see Figure 31)

PYP−200

GDP/ZDP−225

PLL MODE

(PLLEN = 1)

BYPASS MODE

(PLLEN = 0)

PLL MODE

(PLLEN = 1)

BYPASS MODE

(PLLEN = 0)

NO.

UNIT

MIN

5

MAX

MIN

6.7

MAX

MIN

4.4

MAX

MIN

6.7

MAX

1

2

3

4

t

Cycle time, CLKIN

83.3

ns

c(CLKIN)

w(CLKINH)

w(CLKINL)

t(CLKIN)

Pulse duration, CLKIN high

Pulse duration, CLKIN low

Transition time, CLKIN

0.4C

5

†

‡

§

The reference points for the rise and fall transitions are measured at V MAX and V MIN.

C = CLKIN cycle time in nanoseconds (ns). For example, when CLKIN frequency is 40 MHz, use C = 25 ns.

See the PLL and PLL controller section of this data sheet.

IL

IH

†‡§

timing requirements for CLKIN for PYP-225 and GDP/ZDP-300

(see Figure 31)

PYP−225

GDP/ZDP−300

PLL MODE

(PLLEN = 1)

BYPASS MODE

(PLLEN = 0)

PLL MODE

(PLLEN = 1)

BYPASS MODE

(PLLEN = 0)

NO.

UNIT

MIN

4.4

MAX

MIN

6.7

MAX

MIN

4

MAX

MIN

6.7

MAX

1

2

3

4

t

Cycle time, CLKIN

83.3

ns

c(CLKIN)

w(CLKINH)

w(CLKINL)

t(CLKIN)

Pulse duration, CLKIN high

Pulse duration, CLKIN low

Transition time, CLKIN

0.4C

5

†

‡

§

The reference points for the rise and fall transitions are measured at V MAX and V MIN.

C = CLKIN cycle time in nanoseconds (ns). For example, when CLKIN frequency is 40 MHz, use C = 25 ns.

See the PLL and PLL controller section of this data sheet.

IL

IH

†‡§

timing requirements for CLKIN for PYPA-167, GDPA/ZDPA-200 and PYPA-200

(see Figure 31)

PYPA−167

GDPA/ZDPA−200 AND PYPA−200

PLL MODE

(PLLEN = 1)

BYPASS MODE

(PLLEN = 0)

PLL MODE

(PLLEN = 1)

BYPASS MODE

(PLLEN = 0)

NO.

UNIT

MIN

6

MAX

MIN

6.7

MAX

MIN

5

MAX

MIN

6.7

MAX

1

2

3

4

t

Cycle time, CLKIN

83.3

ns

c(CLKIN)

w(CLKINH)

w(CLKINL)

t(CLKIN)

Pulse duration, CLKIN high

Pulse duration, CLKIN low

Transition time, CLKIN

0.4C

5

†

‡

§

The reference points for the rise and fall transitions are measured at V MAX and V MIN.

C = CLKIN cycle time in nanoseconds (ns). For example, when CLKIN frequency is 40 MHz, use C = 25 ns.

See the PLL and PLL controller section of this data sheet.

IL

IH

1

4

2

CLKIN

3

4

Figure 31. CLKIN Timings

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

INPUT AND OUTPUT CLOCKS (CONTINUED)

†‡

switching characteristics over recommended operating conditions for CLKOUT2

(see Figure 32)

PYP −200, −225

GDP/ZDP −225, -300

PYPA −167, -200

NO.

PARAMETER

UNIT

GDPA/ZDPA −200

MIN

MAX

C2 + 0.8

1

2

3

4

t

Cycle time, CLKOUT2

C2 − 0.8

ns

c(CKO2)

w(CKO2H)

w(CKO2L)

t(CKO2)

Pulse duration, CLKOUT2 high

Pulse duration, CLKOUT2 low

Transition time, CLKOUT2

(C2/2) − 0.8 (C2/2) + 0.8

2

†

‡

The reference points for the rise and fall transitions are measured at V

C2 = CLKOUT2 period in ns. CLKOUT2 period is determined by the PLL controller output SYSCLK2 period, which must be set to CPU period

MAX and V MIN.

OH

OL

divide-by-2.

1

4

2

CLKOUT2

3

4

Figure 32. CLKOUT2 Timings

†§

switching characteristics over recommended operating conditions for CLKOUT3

(see Figure 33)

PYP −200, −225

GDP/ZDP −225, -300

PYPA −167, -200

GDPA/ZDPA −200

NO.

PARAMETER

UNIT

MIN

MAX

C3 + 0.9

1

2

3

4

5

t

Cycle time, CLKOUT3

C3 − 0.9

ns

c(CKO3)

w(CKO3H)

w(CKO3L)

t(CKO3)

Pulse duration, CLKOUT3 high

Pulse duration, CLKOUT3 low

Transition time, CLKOUT3

(C3/2) − 0.9 (C3/2) + 0.9

3

t

Delay time, CLKIN high to CLKOUT3 valid

1.5

7.5

d(CLKINH-CKO3V)

†

§

The reference points for the rise and fall transitions are measured at V

C3 = CLKOUT3 period in ns. CLKOUT3 period is a divide-down of the CPU clock, configurable via the OSCDIV1 register. For more details, see

PLL and PLL controller.

MAX and V MIN.

OH

OL

CLKIN

5

1

5

4

3

CLKOUT3

2

4

NOTE A: For this example, the CLKOUT3 frequency is CLKIN divide-by-2.

Figure 33. CLKOUT3 Timings

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

INPUT AND OUTPUT CLOCKS (CONTINUED)

†

timing requirements for ECLKIN (see Figure 34)

PYP-200,-225

GDP/ZDP -225, -300

PYPA -167, -200

GDPA/ZDPA −200

NO.

UNIT

MIN

10

MAX

1

2

3

4

t

Cycle time, ECLKIN

ns

c(EKI)

Pulse duration, ECLKIN high

Pulse duration, ECLKIN low

Transition time, ECLKIN

4.5

w(EKIH)

w(EKIL)

t(EKI)

3

†

The reference points for the rise and fall transitions are measured at V MAX and V MIN.

IL IH

1

4

2

ECLKIN

3

4

Figure 34. ECLKIN Timings

‡§#

switching characteristics over recommended operating conditions for ECLKOUT

(see Figure 35)

PYP−200, -225

GDP/ZDP -225, -300

PYPA -167, -200

GDPA/ZDPA −200

NO.

PARAMETER

UNIT

MIN

MAX

1

2

3

4

5

6

t

Cycle time, ECLKOUT

E − 0.9

E + 0.9

ns

c(EKO)

Pulse duration, ECLKOUT high

EH − 0.9 EH + 0.9

EL − 0.9 EL + 0.9

2

w(EKOH)

w(EKOL)

Pulse duration, ECLKOUT low

Transition time, ECLKOUT

t(EKO)

Delay time, ECLKIN high to ECLKOUT high

Delay time, ECLKIN low to ECLKOUT low

1

6.5

d(EKIH-EKOH)

d(EKIL-EKOL)

‡

§

¶

The reference points for the rise and fall transitions are measured at V

E = ECLKIN period in ns

EH is the high period of ECLKIN in ns and EL is the low period of ECLKIN in ns.

MAX and V MIN.

OH

OL

ECLKIN

6

1

4

2

5

3

ECLKOUT

Figure 35. ECLKOUT Timings

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

ASYNCHRONOUS MEMORY TIMING

†‡§

timing requirements for asynchronous memory cycles

(see Figure 36−Figure 37)

PYP-200,-225

GDP/ZDP -225, -300

PYPA −167, -200

GDPA/ZDPA −200

NO.

UNIT

MIN

6.5

1

MAX

3

4

6

7

t

Setup time, EDx valid before ARE high

Hold time, EDx valid after ARE high

ns

su(EDV-AREH)

h(AREH-EDV)

su(ARDY-EKOH)

h(EKOH-ARDY)

Setup time, ARDY valid before ECLKOUT high

Hold time, ARDY valid after ECLKOUT high

3

2.3

†

To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. The ARDY signal is recognized in

the cycle for which the setup and hold time is met. To use ARDY as an asynchronous input, the pulse width of the ARDY signal should be wide

enough (e.g., pulse width = 2E) to ensure setup and hold time is met.

‡

§

RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are

programmed via the EMIF CE space control registers.

E = ECLKOUT period in ns

switching characteristics over recommended operating conditions for asynchronous memory

‡§¶

cycles

(see Figure 36−Figure 37)

PYP-200,-225

GDP/ZDP -225, -300

PYPA -167, -200

GDPA/ZDPA −200

NO.

PARAMETER

UNIT

MIN

RS*E − 1.7

RH*E − 1.7

1.5

MAX

1

2

t

Output setup time, select signals valid to ARE low

Output hold time, ARE high to select signals invalid

Delay time, ECLKOUT high to ARE valid

ns

osu(SELV-AREL)

oh(AREH-SELIV)

d(EKOH-AREV)

osu(SELV-AWEL)

oh(AWEH-SELIV)

d(EKOH-AWEV)

5

7

8

Output setup time, select signals valid to AWE low

Output hold time, AWE high to select signals and EDx invalid

Delay time, ECLKOUT high to AWE valid

WS*E − 1.7

WH*E − 1.7

1.5

9

10

(WS−1)*E −

1.7

11

t

Output setup time, ED valid to AWE low

ns

osu(EDV-AWEL)

‡

RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are

programmed via the EMIF CE space control registers.

E = ECLKOUT period in ns

§

¶

Select signals include: CEx, BE[3:0], EA[21:2], and AOE.

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

ASYNCHRONOUS MEMORY TIMING (CONTINUED)

Setup = 2

Strobe = 3

Not Ready

Hold = 2

ECLKOUT

CEx

1

2

BE[3:0]

EA[21:2]

BE

Address

3

4

ED[31:0]

1

5

2

5

Read Data

†

AOE/SDRAS/SSOE

†

ARE/SDCAS/SSADS

AWE/SDWE/SSWE

7

6

ARDY

†

AOE/SDRAS/SSOE, ARE/SDCAS/SSADS, and AWE/SDWE/SSWE operate as AOE (identified under select signals), ARE, and AWE,

respectively, during asynchronous memory accesses.

Figure 36. Asynchronous Memory Read Timing

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

ASYNCHRONOUS MEMORY TIMING (CONTINUED)

Setup = 2

Hold = 2

Strobe = 3

Not Ready

ECLKOUT

CEx

8

9

BE[3:0]

BE

EA[21:2]

ED[31:0]

Address

Write Data

11

†

AOE/SDRAS/SSOE

ARE/SDCAS/SSADS

10

†

AWE/SDWE/SSWE

7

6

ARDY

†

AOE/SDRAS/SSOE, ARE/SDCAS/SSADS, and AWE/SDWE/SSWE operate as AOE (identified under select signals), ARE, and AWE,

respectively, during asynchronous memory accesses.

Figure 37. Asynchronous Memory Write Timing

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

SYNCHRONOUS-BURST MEMORY TIMING

†

timing requirements for synchronous-burst SRAM cycles (see Figure 38)

PYP-200,-225

GDP/ZDP -225, -300

PYPA -167, -200

GDPA/ZDPA −200

NO.

UNIT

MIN

1.5

MAX

6

7

t

Setup time, read EDx valid before ECLKOUT high

Hold time, read EDx valid after ECLKOUT high

ns

su(EDV-EKOH)

2.5

h(EKOH-EDV)

†

The C6713B SBSRAM interface takes advantage of the internal burst counter in the SBSRAM. Accesses default to incrementing 4-word bursts,

but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow.

switching characteristics over recommended operating conditions for synchronous-burst SRAM

†‡

cycles (see Figure 38 and Figure 39)

PYP-200,-225

GDP/ZDP -225, -300

PYPA

NO.

PARAMETER

UNIT

-167, -200

GDPA/ZDPA −200

MIN

MAX

1

2

t

Delay time, ECLKOUT high to CEx valid

1.2

7

ns

d(EKOH-CEV)

d(EKOH-BEV)

d(EKOH-BEIV)

d(EKOH-EAV)

d(EKOH-EAIV)

d(EKOH-ADSV)

d(EKOH-OEV)

d(EKOH-EDV)

d(EKOH-EDIV)

d(EKOH-WEV)

Delay time, ECLKOUT high to BEx valid

3

Delay time, ECLKOUT high to BEx invalid

Delay time, ECLKOUT high to EAx valid

1.2

4

7

5

Delay time, ECLKOUT high to EAx invalid

Delay time, ECLKOUT high to ARE/SDCAS/SSADS valid

Delay time, ECLKOUT high to, AOE/SDRAS/SSOE valid

Delay time, ECLKOUT high to EDx valid

1.2

8

7

9

10

11

12

Delay time, ECLKOUT high to EDx invalid

Delay time, ECLKOUT high to AWE/SDWE/SSWE valid

1.2

7

†

‡

The C6713B SBSRAM interface takes advantage of the internal burst counter in the SBSRAM. Accesses default to incrementing 4-word bursts,

but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow.

ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM

accesses.

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)

ECLKOUT

1

CEx

2

3

BE1

BE2

BE3

EA

BE4

7

BE[3:0]

4

5

EA[21:2]

ED[31:0]

6

Q1

Q2

Q3

Q4

8

†

ARE/SDCAS/SSADS

9

†

AOE/SDRAS/SSOE

AWE/SDWE/SSWE

†

ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM

accesses.

Figure 38. SBSRAM Read Timing

ECLKOUT

1

2

1

3

CEx

BE[3:0]

BE1

BE2

Q2

BE3

5

BE4

Q4

4

EA[21:2]

ED[31:0]

EA

10

11

12

Q1

Q3

8

†

ARE/SDCAS/SSADS

AOE/SDRAS/SSOE

12

†

AWE/SDWE/SSWE

†

ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM

accesses.

Figure 39. SBSRAM Write Timing

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

SYNCHRONOUS DRAM TIMING

†

timing requirements for synchronous DRAM cycles (see Figure 40)

PYP-200,-225

GDP/ZDP -225, -300

PYPA -167, -200

GDPA/ZDPA −200

NO.

UNIT

MIN MAX

6

7

t

Setup time, read EDx valid before ECLKOUT high

Hold time, read EDx valid after ECLKOUT high

1.5

2.5

ns

su(EDV-EKOH)

h(EKOH-EDV)

†

The C6713B SDRAM interface takes advantage of the internal burst counter in the SDRAM. Accesses default to incrementing 4-word bursts,

but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow.

switching characteristics over recommended operating conditions for synchronous DRAM

†‡

cycles (see Figure 40−Figure 46)

PYP-200,-225

GDP/ZDP -225, -300

PYPA -167, -200

GDPA/ZDPA −200

NO.

PARAMETER

UNIT

MIN

MAX

1

2

t

Delay time, ECLKOUT high to CEx valid

1.5

7

ns

d(EKOH-CEV)

d(EKOH-BEV)

d(EKOH-BEIV)

d(EKOH-EAV)

d(EKOH-EAIV)

d(EKOH-CASV)

d(EKOH-EDV)

d(EKOH-EDIV)

d(EKOH-WEV)

d(EKOH-RAS)

Delay time, ECLKOUT high to BEx valid

3

Delay time, ECLKOUT high to BEx invalid

Delay time, ECLKOUT high to EAx valid

1.5

4

7

5

Delay time, ECLKOUT high to EAx invalid

Delay time, ECLKOUT high to ARE/SDCAS/SSADS valid

Delay time, ECLKOUT high to EDx valid

1.5

8

7

9

10

11

12

Delay time, ECLKOUT high to EDx invalid

Delay time, ECLKOUT high to AWE/SDWE/SSWE valid

Delay time, ECLKOUT high to, AOE/SDRAS/SSOE valid

1.5

7

†

‡

The C6713B SDRAM interface takes advantage of the internal burst counter in the SDRAM. Accesses default to incrementing 4-word bursts,

but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow.

ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM

accesses.

113

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

SYNCHRONOUS DRAM TIMING (CONTINUED)

READ

ECLKOUT

CEx

1

2

3

BE[3:0]

BE1

BE2

BE3

BE4

4

5

Bank

EA[21:13]

EA[11:2]

4

Column

4

EA12

6

7

D2

ED[31:0]

D1

D3

D4

†

AOE/SDRAS/SSOE

8

†

ARE/SDCAS/SSADS

AWE/SDWE/SSWE

†

ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM

accesses.

Figure 40. SDRAM Read Command (CAS Latency 3)

114

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

SYNCHRONOUS DRAM TIMING (CONTINUED)

WRITE

ECLKOUT

CEx

1

2

4

9

1

2

5

9

3

BE[3:0]

BE1

Bank

BE2

BE3

BE4

EA[21:13]

Column

EA[11:2]

EA12

10

ED[31:0]

D1

D2

D3

D4

†

AOE/SDRAS/SSOE

ARE/SDCAS/SSADS

8

†

11

†

AWE/SDWE/SSWE

†

ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM

accesses.

Figure 41. SDRAM Write Command

115

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

SYNCHRONOUS DRAM TIMING (CONTINUED)

ACTV

ECLKOUT

1

CEx

BE[3:0]

4

5

Bank Activate

EA[21:13]

EA[11:2]

4

Row Address

4

Row Address

EA12

ED[31:0]

12

†

AOE/SDRAS/SSOE

ARE/SDCAS/SSADS

†

AWE/SDWE/SSWE

†

ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM

accesses.

Figure 42. SDRAM ACTV Command

DCAB

ECLKOUT

1

CEx

BE[3:0]

EA[21:13, 11:2]

4

12

11

5

12

11

EA12

ED[31:0]

†

AOE/SDRAS/SSOE

ARE/SDCAS/SSADS

†

AWE/SDWE/SSWE

†

ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM

accesses.

Figure 43. SDRAM DCAB Command

116

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

SYNCHRONOUS DRAM TIMING (CONTINUED)

DEAC

ECLKOUT

1

CEx

BE[3:0]

4

5

EA[21:13]

EA[11:2]

Bank

4

5

EA12

ED[31:0]

12

11

12

11

†

AOE/SDRAS/SSOE

ARE/SDCAS/SSADS

†

AWE/SDWE/SSWE

†

ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM

accesses.

Figure 44. SDRAM DEAC Command

REFR

ECLKOUT

1

CEx

BE[3:0]

EA[21:2]

EA12

ED[31:0]

12

8

12

8

†

AOE/SDRAS/SSOE

†

ARE/SDCAS/SSADS

AWE/SDWE/SSWE

†

ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM

accesses.

Figure 45. SDRAM REFR Command

117

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

SYNCHRONOUS DRAM TIMING (CONTINUED)

MRS

ECLKOUT

1

5

CEx

BE[3:0]

4

EA[21:2]

ED[31:0]

MRS value

12

8

12

8

†

AOE/SDRAS/SSOE

ARE/SDCAS/SSADS

†

11

†

AWE/SDWE/SSWE

†

ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM

accesses.

Figure 46. SDRAM MRS Command

118

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

HOLD/HOLDA TIMING

†

timing requirements for the HOLD/HOLDA cycles (see Figure 47)

PYP-200,-225

GDP/ZDP -225, -300

PYPA -167, -200

GDPA/ZDPA −200

NO.

UNIT

MIN MAX

3

t

Hold time, HOLD low after HOLDA low

E

ns

h(HOLDAL-HOLDL)

E = ECLKOUT period in ns

†

†‡

switching characteristics over recommended operating conditions for the HOLD/HOLDA cycles

(see Figure 47)

PYP-200,-225

GDP/ZDP -225, -300

PYPA -167, -200

GDPA/ZDPA −200

NO.

PARAMETER

UNIT

MIN

2E

0

MAX

1

2

4

5

t

Delay time, HOLD low to EMIF Bus high impedance

Delay time, EMIF Bus high impedance to HOLDA low

Delay time, HOLD high to EMIF Bus low impedance

Delay time, EMIF Bus low impedance to HOLDA high

§

2E

7E

2E

ns

d(HOLDL-EMHZ)

d(EMHZ-HOLDAL)

d(HOLDH-EMLZ)

d(EMLZ-HOLDAH)

2E

0

†

‡

§

E = ECLKOUT period in ns

EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE.

All pending EMIF transactions are allowed to complete before HOLDA is asserted. If no bus transactions are occurring, then the minimum delay

time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.

External Requestor

DSP Owns Bus

Owns Bus

3

HOLD

2

5

HOLDA

1

4

†

EMIF Bus

C6713B

†

EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE.

Figure 47. HOLD/HOLDA Timing

119

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

BUSREQ TIMING

switching characteristics over recommended operating conditions for the BUSREQ cycles

(see Figure 48)

PYP-200,-225

GDP/ZDP -225, -300

PYPA

NO.

PARAMETER

UNIT

-167, -200

GDPA/ZDPA −200

MIN

MAX

7.2

1

t

Delay time, ECLKOUT high to BUSREQ valid

1.5

ns

d(EKOH-BUSRV)

ECLKOUT

BUSREQ

1

Figure 48. BUSREQ Timing

120

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

RESET TIMING

†‡

timing requirements for reset (see Figure 49)

PYP-200,-225

GDP/ZDP -225, -300

PYPA -167, -200

GDPA/ZDPA −200

NO.

UNIT

MIN

100

2P

MAX

1

t

Pulse duration, RESET

Setup time, HD boot configuration bits valid before RESET high

ns

w(RST)

su(HD)

h(HD)

§

13

14

§

Hold time, HD boot configuration bits valid after RESET high

2P

†

‡

P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.

For the C6713B device, the PLL is bypassed immediately after the device comes out of reset. The PLL Controller can be programmed to change

the PLL mode in software. For more detailed information on the PLL Controller, see the TMS320C6000 DSP Phase-Lock Loop (PLL) Controller

Peripheral Reference Guide (literature number SPRU233).

The Boot and device configurations bits are latched asynchronously when RESET is transitioning high. The Boot and device configurations bits

consist of: HD[14, 8, 4:3].

§

¶

switching characteristics over recommended operating conditions during reset (see Figure 49)

PYP-200,-225

GDP/ZDP -225, -300

PYPA-167, -200

GDPA/ZDPA −200

NO.

PARAMETER

UNIT

MIN

MAX

Delay time, external RESET high to internal reset high and

all signal groups valid

512 x CLKIN

period

2

t

CLKMODE0 = 1

ns

d(RSTH-ZV)

#||

3

4

t

Delay time, RESET low to ECLKOUT high impedance

Delay time, RESET high to ECLKOUT valid

0

ns

d(RSTL-ECKOL)

d(RSTH-ECKOV)

d(RSTL-CKO2IV)

d(RSTH-CKO2V)

d(RSTL-CKO3L)

d(RSTH-CKO3V)

6P

5

Delay time, RESET low to CLKOUT2 high impedance

Delay time, RESET high to CLKOUT2 valid

6

7

Delay time, RESET low to CLKOUT3 low

8

Delay time, RESET high to CLKOUT3 valid

||

9

t

Delay time, RESET low to EMIF Z group high impedance

0

d(RSTL-EMIFZHZ)

||

Delay time, RESET low to EMIF low group (BUSREQ) invalid

10

11

12

t

d(RSTL-EMIFLIV)

||

t

Delay time, RESET low to Z group 1 high impedance

Delay time, RESET low to Z group 2 high impedance

d(RSTL-Z1HZ)

||

t

d(RSTL-Z2HZ)

¶

P = 1/CPU clock frequency in ns.

Note that while internal reset is asserted low, the CPU clock (SYSCLK1) period is equal to the input clock (CLKIN) period multiplied by 8. For

example, if the CLKIN period is 20 ns, then the CPU clock (SYSCLK1) period is 20 ns x 8 = 160 ns. Therefore, P = SYSCLK1 = 160 ns while

internal reset is asserted.

#

||

The internal reset is stretched exactly 512 x CLKIN cycles if CLKIN is used (CLKMODE0 = 1). If the input clock (CLKIN) is not stable when RESET

is deasserted, the actual delay time may vary.

EMIF Z group consists of: EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE and

HOLDA

EMIF low group consists of: BUSREQ

Z group 1 consists of:

CLKR0/ACLKR0, CLKR1/AXR0[6], CLKX0/ACLKX0, CLKX1/AMUTE0, FSR0/AFSR0, FSR1/AXR0[7],

FSX0/AFSX0, FSX1, DX0/AXR0[1], DX1/AXR0[5], TOUT0/AXR0[2], TOUT1/AXR0[4], SDA0 and SCL0.

All other HPI, McASP0/1, GPIO, and I2C1 signals.

Z group 2 consists of:

121

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

RESET TIMING (CONTINUED)

Phase 1

Phase 2

Phase 3

CLKIN

ECLKIN

1

RESET

2

Internal Reset

Internal SYSCLK1

Internal SYSCLK2

Internal SYSCLK3

3

4

6

ECLKOUT

5

CLKOUT2

7

8

CLKOUT3

9

2

†

EMIF Z Group

10

11

12

†

EMIF Low Group

2

†

Z Group 1

Z Group 2

†

14

13

Boot and Device

Configuration Pins‡

†

‡

EMIF Z group consists of: EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE and

HOLDA

EMIF low group consists of: BUSREQ

Z group 1 consists of:

CLKR0/ACLKR0, CLKR1/AXR0[6], CLKX0/ACLKX0, CLKX1/AMUTE0, FSR0/AFSR0, FSR1/AXR0[7],

FSX0/AFSX0, FSX1, DX0/AXR0[1], DX1/AXR0[5], TOUT0/AXR0[2], TOUT1/AXR0[4], SDA0 and SCL0.

All other HPI, McASP0/1, GPIO, and I2C1 signals.

Z group 2 consists of:

Boot and device configurations consist of: HD[14, 8, 4:3].

Figure 49. Reset Timing

Reset Phase 1: The RESET pin is asserted. During this time, all internal clocks are running at the CLKIN

frequency divide-by-8. The CPU is also running at the CLKIN frequency divide-by-8.

Reset Phase 2: The RESET pin is deasserted but the internal reset is stretched. During this time, all internal

clocks are running at the CLKIN frequency divide-by-8. The CPU is also running at the CLKIN frequency

divide-by-8.

Reset Phase 3: Both the RESET pin and internal reset are deasserted. During this time, all internal clocks are

running at their default divide-down frequency of CLKIN. The CPU clock (SYSCLK1) is running at CLKIN

frequency. The peripheral clock (SYSCLK2) is running at CLKIN frequency divide-by-2. The EMIF internal clock

source (SYSCLK3) is running at CLKIN frequency divide-by-2. SYSCLK3 is reflected on the ECLKOUT pin

(when EKSRC bit = 0 [default]). CLKOUT3 is running at CLKIN frequency divide-by-8.

122

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

EXTERNAL INTERRUPT TIMING

†

timing requirements for external interrupts (see Figure 50)

PYP-200,-225

GDP/ZDP -225, -300

PYPA -167, -200

GDPA/ZDPA −200

NO.

UNIT

MIN

2P

4P

2P

4P

MAX

Width of the NMI interrupt pulse low

ns

1

2

t

w(ILOW)

Width of the EXT_INT interrupt pulse low

Width of the NMI interrupt pulse high

Width of the EXT_INT interrupt pulse high

w(IHIGH)

†

P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.

2

1

EXT_INT, NMI

Figure 50. External/NMI Interrupt Timing

123

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

MULTICHANNEL AUDIO SERIAL PORT (McASP) TIMING

timing requirements for McASP (see Figure 51 and Figure 52)

PYP-200,-225

GDP/ZDP -225, -300

PYPA -167, -200

GDPA/ZDPA −200

NO.

UNIT

MIN

20

MAX

1

2

t

Cycle time, AHCLKR/X

ns

c(AHCKRX)

Pulse duration, AHCLKR/X high or low

7.5

w(AHCKRX)

greater of 2P

3

4

t

Cycle time, ACLKR/X

ACLKR/X ext

ns

c(ACKRX)

w(ACKRX)

†

or 33 ns

t

Pulse duration, ACLKR/X high or low

ACLKR/X ext

ACLKR/X int

ACLKR/X ext

ACLKR/X int

ACLKR/X ext

ACLKR/X int

ACLKR/X ext

ACLKR/X int

ACLKR/X ext

14

6

ns

Setup time, AFSR/X input valid before ACLKR/X latches

data

5

6

7

8

t

su(AFRXC-ACKRX)

3

0

Hold time, AFSR/X input valid after ACLKR/X latches

data

t

h(ACKRX-AFRX)

su(AXR-ACKRX)

h(ACKRX-AXR)

3

8

Setup time, AXR input valid before ACLKR/X latches

data

t

3

1

Hold time, AXR input valid after ACLKR/X latches data

3

†

P = SYSCLK2 period.

‡

switching characteristics over recommended operating conditions for McASP (see Figure 51

and Figure 52)

PYP-200,-225

GDP/ZDP -225, -300

PYPA -167, -200

GDPA/ZDPA −200

NO.

PARAMETER

UNIT

MIN

20

MAX

9

t

Cycle time, AHCLKR/X

ns

c(AHCKRX)

10

Pulse duration, AHCLKR/X high or low

(AH/2) − 2.5

w(AHCKRX)

greater of 2P

11

12

t

Cycle time, ACLKR/X

ACLKR/X int

ns

c(ACKRX)

w(ACKRX)

†

or 33 ns

t

Pulse duration, ACLKR/X high or low

ACLKR/X int

ACLKR/X ext

ACLKR/X int

ACLKR/X ext

ACLKR/X int

ACLKR/X ext

(A/2) − 2.5

ns

−1

0

5

10

5

Delay time, ACLKR/X transmit edge to AFSX/R output

valid

13

14

15

t

d(ACKRX-AFRX)

−1

0

Delay time, ACLKX transmit edge to AXR output valid

d(ACKX-AXRV)

10

−1

Disable time, AXR high impedance following last data bit

from ACLKR/X transmit edge

dis(ACKRX−AXRHZ)

†

‡

P = SYSCLK2 period.

AH = AHCLKR/X period in ns.

A = ACLKR/X period in ns.

124

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

MULTICHANNEL AUDIO SERIAL PORT (McASP) TIMING (CONTINUED)

2

1

2

AHCLKR/X (Falling Edge Polarity)

AHCLKR/X (Rising Edge Polarity)

4

3

4

†

‡

ACLKR/X (CLKRP = CLKXP = 0)

ACLKR/X (CLKRP = CLKXP = 1)

6

5

AFSR/X (Bit Width, 0 Bit Delay)

AFSR/X (Bit Width, 1 Bit Delay)

AFSR/X (Bit Width, 2 Bit Delay)

AFSR/X (Slot Width, 0 Bit Delay)

AFSR/X (Slot Width, 1 Bit Delay)

AFSR/X (Slot Width, 2 Bit Delay)

8

7

AXR[n] (Data In/Receive)

A0 A1

A30 A31 B0 B1

B30 B31 C0 C1 C2 C3

C31

†

‡

For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP receiver is configured for falling

edge (to shift data in).

For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP receiver is configured for rising

edge (to shift data in).

Figure 51. McASP Input Timings

125

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

MULTICHANNEL AUDIO SERIAL PORT (McASP) TIMING (CONTINUED)

10

9

AHCLKR/X (Falling Edge Polarity)

AHCLKR/X (Rising Edge Polarity)

12

11

12

†

‡

ACLKR/X (CLKRP = CLKXP = 1)

ACLKR/X (CLKRP = CLKXP = 0)

13

AFSR/X (Bit Width, 0 Bit Delay)

AFSR/X (Bit Width, 1 Bit Delay)

AFSR/X (Bit Width, 2 Bit Delay)

AFSR/X (Slot Width, 0 Bit Delay)

AFSR/X (Slot Width, 1 Bit Delay)

AFSR/X (Slot Width, 2 Bit Delay)

AXR[n] (Data Out/Transmit)

13

14

15

A0 A1

A30 A31 B0 B1

B30 B31 C0 C1 C2 C3

C31

†

‡

For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP receiver is configured for rising

edge (to shift data in).

For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP receiver is configured for falling

edge (to shift data in).

Figure 52. McASP Output Timings

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

INTER-INTEGRATED CIRCUITS (I2C) TIMING

†

timing requirements for I2C timings (see Figure 53)

PYP-200,-225

GDP/ZDP -225, -300

PYPA -167, -200

GDPA/ZDPA −200

NO.

UNIT

STANDARD

FAST

MODE

MIN MAX

10

MODE

MIN MAX

1

2

t

Cycle time, SCL

2.5

µs

c(SCL)

Setup time, SCL high before SDA low (for a repeated START

condition)

t

4.7

4

0.6

su(SCLH-SDAL)

Hold time, SCL low after SDA low (for a START and a repeated

START condition)

3

t

µs

h(SCLL-SDAL)

4

5

t

Pulse duration, SCL low

4.7

4

1.3

0.6

µs

ns

µs

ns

µs

ns

pF

w(SCLL)

t

Pulse duration, SCL high

w(SCLH)

‡

6

t

Setup time, SDA valid before SCL high

250

100

0

su(SDAV-SDLH)

2

§

0

§

¶

0.9

7

t

Hold time, SDA valid after SCL low (For I C bus devices)

h(SDA-SDLL)

w(SDAH)

r(SDA)

8

t

Pulse duration, SDA high between STOP and START conditions

Rise time, SDA

4.7

1.3

#

9

1000 20 + 0.1C

300

b

10

11

12

13

14

15

Rise time, SCL

1000 20 + 0.1C

300 20 + 0.1C

r(SCL)

Fall time, SDA

f(SDA)

Fall time, SCL

f(SCL)

t

Setup time, SCL high before SDA high (for STOP condition)

Pulse duration, spike (must be suppressed)

Capacitive load for each bus line

4

0.6

0

su(SCLH-SDAH)

t

50

w(SP)

#

C

400

b

†

‡

2

The I C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down.

2

A Fast-mode I C-bus device can be used in a Standard-mode I C-bus system, but the requirement t

su(SDA−SCLH)

This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period

of the SCL signal, it must output the next data bit to the SDA line t max + t = 1000 + 250 = 1250 ns (according to the Standard-mode

I C-Bus Specification) before the SCL line is released.

A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V

region of the falling edge of SCL.

≥ 250 ns must then be met.

r

su(SDA−SCLH)

2

§

of the SCL signal) to bridge the undefined

IHmin

¶

#

The maximum t

h(SDA−SCLL)

has only to be met if the device does not stretch the low period [t

] of the SCL signal.

w(SCLL)

= total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.

C

b

11

9

SDA

SCL

6

8

14

4

13

5

10

1

12

3

2

7

3

Stop

Start

Repeated

Start

Stop

2

Figure 53. I C Receive Timings

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

INTER-INTEGRATED CIRCUITS (I2C) TIMING (CONTINUED)

†

switching characteristics for I2C timings (see Figure 54)

PYP-200,-225

GDP/ZDP -225, -300

PYPA -167, -200

GDPA/ZDPA −200

NO.

PARAMETER

UNIT

STANDARD

FAST

MODE

MIN MAX

10

MODE

MIN MAX

16

17

t

Cycle time, SCL

2.5

0.6

µs

c(SCL)

t

Delay time, SCL high to SDA low (for a repeated START condition)

4.7

d(SCLH-SDAL)

Delay time, SDA low to SCL low (for a START and a repeated

START condition)

18

t

4

0.6

µs

d(SDAL-SCLL)

19

20

21

22

23

24

25

26

27

28

29

t

Pulse duration, SCL low

4.7

4

1.3

0.6

µs

ns

µs

ns

µs

pF

w(SCLL)

t

Pulse duration, SCL high

w(SCLH)

t

Delay time, SDA valid to SCL high

250

0

100

d(SDAV-SDLH)

2

t

Valid time, SDA valid after SCL low (For I C bus devices)

0

0.9

v(SDLL-SDAV)

t

Pulse duration, SDA high between STOP and START conditions

4.7

1.3

w(SDAH)

r(SDA)

r(SCL)

f(SDA)

f(SCL)

†

t

Rise time, SDA

1000 20 + 0.1C

300

b

Rise time, SCL

1000 20 + 0.1C

300 20 + 0.1C

Fall time, SDA

Fall time, SCL

t

Delay time, SCL high to SDA high (for STOP condition)

Capacitance for each I2C pin

4

0.6

d(SCLH-SDAH)

C

10

p

†

C

= total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.

b

26

24

SDA

21

23

19

28

20

25

SCL

16

27

18

17

22

18

Stop

Start

Repeated

Start

Stop

2

Figure 54. I C Transmit Timings

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

HOST-PORT INTERFACE TIMING

†‡

timing requirements for host-port interface cycles (see Figure 55, Figure 56, Figure 57, and

Figure 58)

PYP-200,-225

GDP/ZDP -225, -300

PYPA -167, -200

GDPA/ZDPA −200

NO.

UNIT

MIN

MAX

§

1

2

t

Setup time, select signals valid before HSTROBE low

5

ns

su(SELV-HSTBL)

§

t

Hold time, select signals valid after HSTROBE low

4

4P

5

h(HSTBL-SELV)

Pulse duration, HSTROBE low (host read access)

Pulse duration, HSTROBE low (host write access)

Pulse duration, HSTROBE high between consecutive accesses

3

t

ns

w(HSTBL)

4

t

ns

w(HSTBH)

§

Setup time, select signals valid before HAS low

10

11

12

13

su(SELV-HASL)

h(HASL-SELV)

§

Hold time, select signals valid after HAS low

3

t

Setup time, host data valid before HSTROBE high

Hold time, host data valid after HSTROBE high

5

su(HDV-HSTBH)

t

3

h(HSTBH-HDV)

Hold time, HSTROBE low after HRDY low. HSTROBE should not be inactivated

until HRDY is active (low); otherwise, HPI writes will not complete properly.

14

t

2

ns

h(HRDYL-HSTBL)

18

19

t

Setup time, HAS low before HSTROBE low

Hold time, HAS low after HSTROBE low

2

ns

su(HASL-HSTBL)

t

h(HSTBL-HASL)

†

‡

§

HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.

Select signals include: HCNTL[1:0], HR/W, and HHWIL.

switching characteristics over recommended operating conditions during host-port interface

†‡

cycles (see Figure 55, Figure 56, Figure 57, and Figure 58)

PYP-200,-225

GDP/ZDP -225, -300

PYPA -167, -200

GDPA/ZDPA −200

NO.

PARAMETER

UNIT

MIN

MAX

12

¶

5

6

7

t

Delay time, HCS to HRDY

1

ns

d(HCS-HRDY)

#

t

Delay time, HSTROBE low to HRDY high

3

2

12

d(HSTBL-HRDYH)

t

Delay time, HSTROBE low to HD low impedance for an HPI read

d(HSTBL-HDLZ)

8

t

Delay time, HD valid to HRDY low

2P − 4

ns

d(HDV-HRDYL)

9

t

Output hold time, HD valid after HSTROBE high

Delay time, HSTROBE high to HD high impedance

Delay time, HSTROBE low to HD valid

3

12

oh(HSTBH-HDV)

15

16

17

t

d(HSTBH-HDHZ)

t

12.5

12

d(HSTBL-HDV)

||

Delay time, HSTROBE high to HRDY high

t

d(HSTBH-HRDYH)

†

‡

¶

HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.

HCS enables HRDY, and HRDY is always low when HCS is high. The case where HRDY goes high when HCS falls indicates that HPI is busy

completing a previous HPID write or READ with autoincrement.

#

||

This parameter is used during an HPID read. At the beginning of the first half-word transfer on the falling edge of HSTROBE, the HPI sends the

request to the EDMA internal address generation hardware, and HRDY remains high until the EDMA internal address generation hardware loads

the requested data into HPID.

This parameter is used after the second half-word of an HPID write or autoincrement read. HRDY remains low if the access is not an HPID write

or autoincrement read. Reading or writing to HPIC or HPIA does not affect the HRDY signal.

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

HOST-PORT INTERFACE TIMING (CONTINUED)

HAS

HCNTL[1:0]

HR/W

1

2

1

HHWIL

4

3

†

HSTROBE

HCS

15

9

15

9

7

16

HD[15:0] (output)

HRDY (case 1)

HRDY (case 2)

5

1st halfword

2nd halfword

5

8

17

6

†

HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

Figure 55. HPI Read Timing (HAS Not Used, Tied High)

†

HAS

19

11

19

11

10

HCNTL[1:0]

HR/W

11

10

HHWIL

4

3

‡

HSTROBE

18

HCS

15

7

9

16

9

17

HD[15:0] (output)

HRDY (case 1)

HRDY (case 2)

1st half-word

2nd half-word

5

8

5

†

‡

For correct operation, strobe the HAS signal only once per HSTROBE active cycle.

HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

Figure 56. HPI Read Timing (HAS Used)

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

HOST-PORT INTERFACE TIMING (CONTINUED)

HAS

HCNTL[1:0]

HR/W

1

2

3

1

2

HHWIL

3

4

14

†

HSTROBE

HCS

HD[15:0] (input)

HRDY

12

13

2nd halfword

13

17

1st halfword

5

†

HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

Figure 57. HPI Write Timing (HAS Not Used, Tied High)

†

HAS

19

11

19

11

10

HCNTL[1:0]

HR/W

11

HHWIL

3

4

14

‡

HSTROBE

18

12

18

HCS

HD[15:0] (input)

HRDY

12

13

1st half-word

2nd half-word

5

17

†

‡

For correct operation, strobe the HAS signal only once per HSTROBE active cycle.

HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

Figure 58. HPI Write Timing (HAS Used)

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

MULTICHANNEL BUFFERED SERIAL PORT TIMING

†‡

timing requirements for McBSP (see Figure 59)

PYP-200,-225

GDP/ZDP -225, -300

PYPA -167, -200

GDPA/ZDPA −200

NO.

UNIT

MIN

MAX

§

2

3

t

Cycle time, CLKR/X

CLKR/X ext

CLKR int

CLKR ext

CLKR int

CLKR ext

CLKR int

CLKR ext

CLKR int

CLKR ext

CLKX int

CLKX ext

CLKX int

CLKX ext

2P

ns

c(CKRX)

¶

0.5*t −1

c(CKRX)

Pulse duration, CLKR/X high or CLKR/X low

w(CKRX)

9

5

6

t

Setup time, external FSR high before CLKR low

Hold time, external FSR high after CLKR low

Setup time, DR valid before CLKR low

ns

su(FRH-CKRL)

h(CKRL-FRH)

su(DRV-CKRL)

h(CKRL-DRV)

su(FXH-CKXL)

h(CKXL-FXH)

1

6

3

8

0

3

4

9

1

6

3

7

8

Hold time, DR valid after CLKR low

10

11

Setup time, external FSX high before CLKX low

Hold time, external FSX high after CLKX low

†

‡

§

CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.

The minimum CLKR/X period is twice the CPU cycle time (2P) and not faster than 75 Mbps (13.3 ns). This means that the maximum bit rate for

communications between the McBSP and other devices is 75 Mbps for 167-MHz and 225-MHz CPU clocks or 50 Mbps for 100-MHz CPU clock;

where the McBSP is either the master or the slave. Care must be taken to ensure that the AC timings specified in this data sheet are met. The

maximum bit rate for McBSP-to-McBSP communications is 67 Mbps; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle

time (2P), or 15 ns (67 MHz), whichever value is larger. For example, when running parts at 150 MHz (P = 6.7 ns), use 15 ns as the minimum

CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 60 MHz (P = 16.67 ns), use 2P =

33 ns (30 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP communications applies when the serial port

is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM

= 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a slave.

¶

This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the resonable range of 40/60 duty cycle.

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SPRS294B − OCTOBER 2005 − REVISED JUNE 2006

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

†‡

switching characteristics over recommended operating conditions for McBSP (see Figure 59)

PYP-200,-225

GDP/ZDP -225, -300

PYPA -167, -200

GDPA/ZDPA −200

NO.

PARAMETER

UNIT

MIN

MAX

Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from

CLKS input

1

t

1.8

10

ns

d(CKSH-CKRXH)

§¶

2

3

4

t

Cycle time, CLKR/X

CLKR/X int

CLKR int

CLKX int

CLKX ext

CLKX int

CLKX ext

CLKX int

CLKX ext

2P

ns

c(CKRX)

#

Pulse duration, CLKR/X high or CLKR/X low

Delay time, CLKR high to internal FSR valid

C − 1

C + 1

w(CKRX)

−2

2

3

9

4

d(CKRH-FRV)

9

t

Delay time, CLKX high to internal FSX valid

ns

d(CKXH-FXV)

dis(CKXH-DXHZ)

d(CKXH-DXV)

−1

1.5

Disable time, DX high impedance following last data bit

from CLKX high

12

13

10

||

−3.2 + D1

0.5 + D1

4 + D2

10+ D2

Delay time, CLKX high to DX valid

Delay time, FSX high to DX valid

||

FSX int

FSX ext

−1

2

7.5

14

t

ns

d(FXH-DXV)

ONLY applies when in data delay 0 (XDATDLY = 00b)

mode

11.5

†

‡

§

¶

CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

Minimum delay times also represent minimum output hold times.