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SM320C6748-HIREL [TI]

高可靠性产品 C6748 浮点 DSP;
SM320C6748-HIREL
型号： SM320C6748-HIREL
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

高可靠性产品 C6748 浮点 DSP
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SM320C6748-HIREL  
ZHCSFA2 –JUNE 2016  
SM320C6748-HIREL 定点和浮点数字信号处理器  
1 器件概述  
1.1 特性  
1
–
–
–
每2个时钟2 SP x SP → DP  
每3个时钟2 SP x DP → DP  
每 4 个时钟 2 DP x DP → DP  
• 375MHz C674x 定点和浮点超长指令字 (VLIW) 数  
字信号处理器 (DSP)  
• C674x 指令集 特性  
– C67x+ 和 C64x+ ISA 的超集  
– 高达 3648 MIPS 和 2746 MFLOPS  
– 可按字节寻址（8 位、16 位、32 位和 64 位数  
据）  
•
定点乘法每个时钟周期支持 2 次 32 x 32 位乘  
法、4 次 16 x 16 位乘法或 8 次 8 x 8 位乘  
法，而且还支持复杂的乘法  
– 指令组合减少代码尺寸  
– 所有指令需满足如下条件  
– 取模循环运算的硬件支持  
– 受保护模式运行  
– 8 位溢出保护  
– 位域提取、设定、清空  
– 正常化、饱和、位计数  
– 额外支持错误检测和程序重定向  
• 软件支持  
– 紧凑 16 位指令  
• C674x 二级缓存架构  
– 德州仪器 (TI) DSP BIOS™  
– 芯片支持库和 DSP 库  
• 128KB 的 RAM 共享存储器  
• 1.8V 或 3.3V LVCMOS I/O（USB 和 DDR2 接口除  
外）  
– 32KB 的 L1P 程序 RAM/缓存  
– 32KB 的 L1D 数据 RAM/缓存  
– 256KB 的 L2 统一映射 RAM/缓存  
– 灵活 RAM/缓存分区（L1 和 L2）  
• 增强型直接存储器访问控制器 3 (EDMA3)：  
– 2 个通道控制器  
• 2 个外部存储器接口：  
– 扩展内存接口 A (EMIFA)  
– 3 个传输控制器  
– 64 个独立 DMA 通道  
– 16 个快速 DMA 通道  
– 可编程传输突发尺寸  
•
•
•
NOR（8 位宽或 16 位宽数据）  
NAND（8 位宽或 16 位宽数据）  
具有 128MB 地址空间的 16 位 SDRAM  
– DDR2/移动 DDR 存储器控制器，有以下两种：  
• TMS320C674x 浮点 VLIW DSP 核心  
– 具备非对齐支持的 Load-Store 架构  
– 64 个通用寄存器（32 位）  
– 6 个 ALU（32 位和 40 位）功能单元  
•
具有 256MB 地址空间的 16 位 DDR2  
SDRAM  
•
具有 256MB 地址空间的 16 位 mDDR  
SDRAM  
•
•
•
支持 32 位整型，SP（IEEE 单精度/32 位）  
和 DP（IEEE 双精度/64 位）浮点数  
每个时钟支持多达 4 次 SP 加法，每 2 个时  
钟支持多达 4 次 DP 加法  
每个周期支持多达 2 次浮点数（SP 或 DP）  
倒数逼近 (RCPxP) 和平方根倒数逼近  
(RSQRxP) 运算  
• 3 个可配置的 16550 型 UART 模块：  
– 含调制解调器控制信号  
– 16 字节 FIFO  
– 16x 或 13x 过采样选项  
• LCD 控制器  
• 2 个串行外设接口 (SPI)，均支持多片选  
– 2 个乘法功能单元：  
混合精度 IEEE 浮点乘法支持高达：  
每时钟 2 SP x SP → SP  
• 2 个多媒体卡 (MMC)/安全数字 (SD) 卡接口，具有  
安全数据 I/O (SDIO) 接口  
•
• 2 个主控和受控内部集成电路  
–
（ I2C 总线™）  
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. PRODUCTION DATA.  
English Data Sheet: SPRS947  
 
 
SM320C6748-HIREL  
ZHCSFA2 –JUNE 2016  
www.ti.com.cn  
• 1 个主机端口接口 (HPI)，通过 16 位宽的地址和数  
据复用总线实现高带宽  
• 通用并行端口 (uPP)：  
– 到现场可编门阵列 (FPGA) 和数据转换器的高速  
并行接口  
• 可编程实时单元子系统 (PRUSS)  
– 2 个独立的可编程实时单元 (PRU) 内核  
– 两个通道的数据宽度为 8 位至 16 位（包括 8 位  
和 16 位）  
– 单倍数据速率或双倍数据速率传输  
•
32 位 Load-Store 精简指令集计算机 (RISC)  
架构  
– 支持多个接口进行 START、ENABLE 和 WAIT  
控制  
•
•
•
•
每个内核 4KB 的指令 RAM  
每个内核 512 字节的数据 RAM  
可通过软件禁用 PRUSS 以实现节能  
除了 PRU 内核的正常 R31 输出，还会从子  
系统中导出每个 PRU 的寄存器 30。  
• 串行高级技术附件 (SATA) 控制器：  
– 支持 SATA I (1.5Gbps) 和 SATA II  
(3Gbps)  
– 支持全部 SATA 电源管理 特性  
– 标准的电源管理机制  
– 高达 32 条的硬件辅助本地命令序列 (NCQ)  
– 支持端口复用器和基于命令的开关  
• 具有 32kHz 振荡器和独立电源轨的实时时钟 (RTC)  
•
•
时钟选通  
在一个单一 PSC 时钟选通域下的完整子系统  
– 专用中断控制器  
• 3 个 64 位通用定时器（每一个可配置为 2 个 32 位  
定时器）  
– 专用开关中心源  
• 集成有 PHY 的 USB 1.1 OHCI（主机）(USB1)  
• 集成有 PHY 的 USB 2.0 OTG 端口 (USB0)  
– USB 2.0 高速和全速客户端  
– USB 2.0 高速、全速和低速主机  
– 端点 0（控制）  
• 1 个 64 位通用定时器或看门狗定时器（可配置为 2  
个 32 位定时器）  
• 2 个增强的高分辨率脉宽调制器 (eHRPWM)：  
– 具有周期和频率控制功能的 16 位专用时基计数  
器
– 端点 1、端点 2、端点 3、端点 4（控制、批量、  
中断或 ISOC）RX 和 TX  
– 6 个单边沿输出、6 个双边沿对称输出或 3 个双  
边沿非对称输出  
• 1 个多通道音频串行端口 (McASP)：  
– 2 个时钟域和 16 个串行数据引脚  
– 支持时分复用 (TDM)，I2S，和相似格式  
– 支持动态互联网技术 (DIT)  
– 用于发送和接收的 FIFO 缓冲器  
• 2 个多通道缓冲串行端口 (McBSP)：  
– 支持 TDM，I2S，和相似格式  
– AC97 音频编解码器接口  
– 死区生成  
– 高频载波实现的脉宽调制 (PWM) 斩波  
– 触发区输入  
• 3 个 32 位增强型捕捉 (eCAP) 模块：  
– 可配置为 3 个捕捉输入或 3 个辅助脉宽调制器  
(APWM) 输出  
– 多达 4 个事件时间戳的单脉冲捕捉  
• 封装：  
– 电信接口（ST 总线，H100）  
– 128 通道时分复用 (TDM)  
– 361 焊球 SnPb PBGA [GWT 后缀]、  
0.80mm 焊球间距  
– 用于发送和接收的 FIFO 缓冲器  
• 10/100Mbps 以太网 MAC (EMAC)：  
– 符合 IEEE 802.3 标准  
• 商业级、扩展级或工业级温度  
– MII 介质独立接口  
– RMII 简化的介质独立接口  
– 管理数据 I/O (MDIO) 模块  
• 视频端口接口 (VPIF)：  
– 2 个 8 位 SD (BT.656)、单个 16 位或单个原始  
（8 位、10 位和 12 位）视频捕捉通道  
– 2 个 8 位 SD (BT.656)、单个 16 位视频显示通道  
2
器件概述  
版权 © 2016, Texas Instruments Incorporated  
SM320C6748-HIREL  
www.ti.com.cn  
ZHCSFA2 –JUNE 2016  
1.2 应用  
•
•
验钞  
•
机器视觉（低端）  
生物特征识别  
1.3 说明  
SM320C6748-HIREL 定点和浮点 DSP 是一款低功耗 应用 处理器，该处理器基于 C674x DSP 内核。该  
DSP 与其他 TMS320C6000™ 平台 DSP 相比，功耗要小很多。  
凭借这款器件，原始设备制造商 (OEM) 和原始设计制造商 (ODM) 能够充分利用全集成混合处理器解决方案  
的灵活性，迅速将兼具稳健操作系统、丰富用户接口和高处理器性能的器件推向市场。  
该器件的 DSP 内核采用基于 2 级缓存的架构。第 1 级程序缓存 (L1P) 是一个  
32KB 的直接映射缓存，第 1 级数据缓存 (L1D) 是一个 32KB 的 2 路组相连缓存。第 2 级程序缓存 (L2P)  
包含 256KB 的存储空间，由程序空间和数据空间共享。L2 存储器可配置为映射存储器、缓存或二者的组  
合。尽管系统内的其他主机可访问 DSP L2，但还是额外提供了一个 128KB 的 RAM 共享存储器给其他主机  
使用，从而避免对 DSP 性能产生影响。  
对于支持安全功能的器件，TI 的基本安全启动可为用户保护自主知识产权并防止外部实体修改用户开发的算  
法。该安全启动流程从一个基于硬件的“信任根”开始，确保代码从一个已知安全的位置开始执行。默认情况  
下会锁定 JTAG 端口以防止仿真和调试攻击；不过，在应用开发期间的安全启动过程中可以使能 JTAG 端  
口。启动模块存储在外部非易失性存储器（例如，闪存或 EEPROM）中时处于加密状态，在安全启动期间  
被装载时会进行解密和验证。加密和解密程序会保护客户 IP，使客户能够安全地设置系统并使器件采用已知  
可信任的代码开始运行。  
基本安全启动使用 SHA-1 或 SHA-256 以及 AES-128 来验证启动映像。另外，基本安全启动使用 AES-128  
进行启动映像加密。安全启动流程采用多层加密机制，不但可以保护启动过程，而且能够安全地升级启动和  
应用软件代码。该器件使用 1 个 128 位的器件专用密钥来保护客户密钥，该 128 位密钥由经过 NIST-800-  
22 认证的随机数发生器生成，并且仅对该器件是已知的。当需要更新时，客户可使用密钥创建一个新的加  
密映像。之后，器件可通过外部接口（例如，以太网）来获取该映像并覆盖现有代码。有关支持的安全 特性  
或 TI 基本安全启动的更多详细信息，请参见《TMS320C674x/OMAP-L1x 处理器安全用户指南》（文献编  
号：SPRUGQ9）。  
外设集包括：1 个具有管理数据输入/输出模块 (MDIO) 的 10Mbps/100Mbps 以太网介质访问控制器  
(EMAC)；1 个 USB2.0 OTG 接口；1 个 USB1.1 OHCI 接口；2 个 I2C 总线接口；1 个具有 16 个串行器和  
FIFO 缓冲器的多通道音频串行端口 (McASP)；2 个具有 FIFO 缓冲器的多通道缓冲串行端口 (McBSP)；2  
个支持多片选的串行外设接口 (SPI)；4 个可配置的 64 位通用定时器（其中一个可配置为看门狗）；1 个可  
配置的 16 位主机端口接口 (HPI)；多达 9 组通用输入/输出 (GPIO) 引脚（每组包含 16 个引脚，每个引脚均  
支持可编程的中断和事件生成模式，并且支持与其他外设复用）；3 个 UART 接口（均支持 RTS 和  
CTS）；2 个增强型高分辨率脉宽调制器 (eHRPWM) 外设；3 个 32 位增强型捕捉 (eCAP) 模块外设（可配  
置为 3 个捕捉输入或 3 个 APWM 输出）；2 个外部存储器接口（一个是用于慢速存储器或外设的异步  
SDRAM 外部存储器接口 (EMIFA)，另一个是高速 DDR2/移动 DDR 控制器）。  
EMAC 为器件和网络之间提供了一个高效接口。无论是在半双工模式还是全双工模式下，EMAC 都支持  
10Base-T 和 100Base-TX 或者 10Mbps 和 100Mbps。此外，该器件还提供了一个针对 PHY 配置的 MDIO  
接口。EMAC 支持 MII 和 RMII 接口。  
SATA 控制器提供了一个至海量数据存储设备的高速接口。SATA 控制器支持 SATA I (1.5Gbps) 和 SATA II  
(3.0Gbps)。  
uPP 提供了一个高速接口，可连接多种数据转换器、FPGA 或其他并行器件。uPP 的两个通道均支持可编  
程的数据宽度，可编程范围为 8 位至 16 位。另外，还支持单倍数据速率或双倍数据速率传输以及  
START、ENABLE 和 WAIT 信号，用以控制各类数据转换器。  
该器件包含一个视频端口接口 (VPIF)，可实现灵活的视频 I/O 端口。  
丰富的外设集提供了控制外围设备以及与外部处理器进行通信的功能。如需了解每个外设的详细信息，请参  
见本文件中的有关章节以及相关联的外设参考指南。  
版权 © 2016, Texas Instruments Incorporated  
器件概述  
3
 
 
SM320C6748-HIREL  
ZHCSFA2 –JUNE 2016  
www.ti.com.cn  
该器件配有一套完整的 DSP 开发工具。这套工具包括 C 语言编译器，用于简化编程和调度过程的 DSP 汇  
编优化器以及用于查看源代码执行的 Windows®调试程序界面。  
器件信息(1)  
产品型号  
SM320C6748EGWTS3  
封装  
封装尺寸  
NFBGA (361)  
16.00mm x 16.00mm  
(1) 更多信息请参见 节 7，机械封装和可订购产品信息。  
4
器件概述  
版权 © 2016, Texas Instruments Incorporated  
SM320C6748-HIREL  
www.ti.com.cn  
ZHCSFA2 –JUNE 2016  
1.4 功能框图  
图 1-1可展示器件的功能框图  
DSP Subsystem  
JTAG Interface  
System Control  
C674x™  
DSP CPU  
PLL/Clock  
Generator  
w/OSC  
Input  
Clock(s)  
Memory  
Protection  
AET  
General-  
Purpose  
Timer (x3)  
32KB  
L1 Pgm  
32KB  
L1 RAM  
Power/Sleep  
Controller  
256KB L2 RAM  
BOOT ROM  
RTC/  
32-kHz  
OSC  
Pin  
Multiplexing  
Switched Central Resource (SCR)  
Peripherals  
Control Timers  
DMA  
Audio Ports  
Serial Interfaces  
Display  
Parallel Port  
uPP  
Internal Memory  
2
SPI  
(x2)  
UART  
(x3)  
EDMA3  
(x2)  
128KB  
RAM  
McASP  
w/FIFO  
LCD  
Ctlr  
McBSP  
(x2)  
I C  
(x2)  
ePWM  
(x2)  
eCAP  
(x3)  
Connectivity  
External Memory Interfaces  
Customizable Interface  
PRU Subsystem  
Video  
EMAC  
10/100  
(MII/RMII)  
MMC/SD  
(8b)  
(x2)  
USB2.0  
OTG Ctlr OHCI Ctlr  
PHY PHY  
USB1.1  
EMIFA(8b/16B)  
DDR2/MDDR  
NAND/Flash  
Controller  
MDIO  
HPI  
SATA  
VPIF  
16b SDRAM  
图 1-1. 功能方框图  
版权 © 2016, Texas Instruments Incorporated  
器件概述  
5
 
 
SM320C6748-HIREL  
ZHCSFA2 –JUNE 2016  
www.ti.com.cn  
内容  
1
器件概述.................................................... 1  
1.1 特性 ................................................... 1  
1.2 应用 ................................................... 3  
1.3 说明 ................................................... 3  
1.4 功能框图 .............................................. 5  
修订历史记录............................................... 7  
Terminal Configuration and Functions.............. 8  
3.1 Pin Diagram .......................................... 8  
3.2 Pin Attributes ........................................ 12  
3.3 Pin Multiplexing ..................................... 52  
3.4 Connections for Unused Pins ....................... 52  
Specifications ........................................... 54  
4.1 Absolute Maximum Ratings......................... 54  
4.2 ESD Ratings ........................................ 54  
4.3 Power-On-Hours (POH) Limits...................... 55  
4.4 Recommended Operating Conditions............... 56  
4.5 Electrical Characteristics ........................... 58  
4.6 Thermal Data for GWT Package.................... 59  
4.7 Timing and Switching Characteristics............... 59  
5
Detailed Description.................................. 236  
5.1 Device Overview................................... 236  
5.2 Device Compatibility ............................... 237  
5.3 DSP Subsystem.................................... 237  
5.4 Memory Map Summary............................ 248  
5.5 Boot Modes ....................................... 250  
5.6 SYSCFG Module .................................. 251  
5.7 Pullup/Pulldown Resistors ......................... 253  
5.8 Reset............................................... 254  
5.9 Interrupts ........................................... 255  
器件和文档支持......................................... 259  
6.1 器件命名规则....................................... 259  
6.2 工具与软件 ......................................... 259  
6.3 文档支持 ........................................... 260  
6.4 社区资源 ........................................... 260  
6.5 商标 ................................................ 260  
6.6 静电放电警告....................................... 261  
6.7 Glossary............................................ 261  
机械、封装和可订购信息 .............................. 262  
2
3
6
4
7
6
内容  
版权 © 2016, Texas Instruments Incorporated  
SM320C6748-HIREL  
www.ti.com.cn  
ZHCSFA2 –JUNE 2016  
2 修订历史记录  
注：之前版本的页码可能与当前版本有所不同。  
日期  
修订版本  
注释  
2016 年 6 月  
*
最初发布。  
Copyright © 2016, Texas Instruments Incorporated  
修订历史记录  
7
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Product Folder Links: SM320C6748-HIREL  
SM320C6748-HIREL  
ZHCSFA2 –JUNE 2016  
www.ti.com.cn  
3 Terminal Configuration and Functions  
Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in  
the smallest possible package. Pin multiplexing is controlled using a combination of hardware  
configuration at device reset and software programmable register settings. See Section 3.3 for details.  
3.1 Pin Diagram  
Figure 3-1, Figure 3-2, Figure 3-3, and Figure 3-4 show the bottom view of the GWT package pin  
assignments in four quadrants (A, B, C, and D).  
1
2
3
4
5
6
7
8
9
10  
VP_DOUT[0]/  
LCD_D[0]/  
VP_DOUT[1]/  
LCD_D[1]/  
VP_DOUT[2]/  
LCD_D[2]/  
UPP_XD[8]/  
GP7[8]/  
PRU1_R31[8]  
UPP_XD[9]/  
GP7[9]/  
PRU1_R31[9]  
UPP_XD[10]/  
GP7[10]/  
PRU1_R31[10]  
DDR_A[10]  
DDR_A[6]  
DDR_A[2]  
DDR_CLKP  
DDR_D[15]  
DDR_CLKN  
DDR_RAS  
W
V
U
T
W
V
U
T
VP_DOUT[3]/  
LCD_D[3]/  
UPP_XD[11]/  
GP7[11]/  
PRU1_R31[11]  
VP_DOUT[4]/  
LCD_D[4]/  
UPP_XD[12]/  
GP7[12]/  
PRU1_R31[12]  
VP_DOUT[5]/  
LCD_D[5]/  
UPP_XD[13]/  
GP7[13]/  
PRU1_R31[13]  
DDR_A[12]  
DDR_A[5]  
DDR_A[4]  
DDR_A[13]  
DDR_A[3]  
DDR_CKE  
DDR_BA[0]  
DDR_D[13]  
DDR_CS  
VP_DOUT[6]/  
LCD_D[6]/  
UPP_XD[14]/  
GP7[14]/  
PRU1_R31[14]  
VP_DOUT[7]/  
LCD_D[7]/  
UPP_XD[15]/  
GP7[15]/  
PRU1_R31[15]  
VP_DOUT[8]/  
LCD_D[8]/  
UPP_XD[0]/  
GP7[0]/  
DDR_A[8]  
DDR_A[7]  
DDR_A[0]  
DDR_BA[2]  
DDR_CAS  
DDR_D[12]  
BOOT[0]  
VP_DOUT[9]/  
LCD_D[9]/  
UPP_XD[1]/  
GP7[1]/  
VP_DOUT[10]/  
LCD_D[10]/  
UPP_XD[2]/  
GP7[2]/  
VP_DOUT[11]/  
LCD_D[11]/  
UPP_XD[3]/  
GP7[3]/  
DDR_A[11]  
DDR_A[9]  
DDR_A[1]  
DDR_BA[1]  
DDR_D[10]  
DDR_WE  
BOOT[1]  
BOOT[2]  
BOOT[3]  
VP_DOUT[12]/  
LCD_D[12]/  
UPP_XD[4]/  
GP7[4]/  
VP_DOUT[13]/  
LCD_D[13]/  
UPP_XD[5]/  
GP7[5]/  
VP_DOUT[14]/  
LCD_D[14]/  
UPP_XD[6]/  
GP7[6]/  
LCD_AC_ENB_CS/  
GP6[0]/  
PRU1_R31[28]  
DVDD3318_C  
DDR_VREF  
DVDD3318_C  
DDR_DVDD18  
DDR_DVDD18  
DDR_DVDD18  
DDR_DVDD18  
DDR_DVDD18  
DDR_DVDD18  
DDR_DQM[1]  
DDR_DVDD18  
DDR_DVDD18  
R
P
N
M
L
R
P
N
M
L
BOOT[4]  
BOOT[5]  
BOOT[6]  
VP_DOUT[15]/  
LCD_D[15]/  
UPP_XD[7]/  
GP7[7]/  
SATA_VDD  
SATA_REFCLKN  
SATA_VSS  
SATA_VDD  
SATA_REFCLKP  
SATA_VDD  
SATA_VDDR  
DVDD3318_C  
DDR_DVDD18  
DDR_DVDD18  
BOOT[7]  
SATA_REG  
SATA_VDD  
V
RV  
DD  
CV  
CV  
V
SS  
DD  
NC  
V
V
V
V
CV  
V
SS  
SS  
SS  
SS  
DD  
DD  
SS  
DV  
SATA_RXP  
SATA_VSS  
V
DV  
V
V
V
SATA_RXN  
DD3318_C  
SS  
DD18  
SS  
SS  
SS  
SS  
VP_CLKOUT2/  
MMCSD1_DAT[2]/  
PRU1_R30[2]/  
GP6[3]/  
VP_CLKOUT3/  
PRU1_R30[0]/  
GP6[1]/  
SATA_VSS  
SATA_VSS  
DV  
V
V
V
V
CV  
K
DD18  
DD  
SS  
SS  
SS  
SS  
K
PRU1_R31[1]  
PRU1_R31[3]  
1
2
3
4
5
6
7
8
9
10  
Figure 3-1. Pin Map (Quad A)  
8
Terminal Configuration and Functions  
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11  
12  
13  
14  
15  
16  
17  
18  
19  
VP_CLKIN0/  
UHPI_HCS/  
PRU1_R30[10]/  
GP6[7]/  
VP_DIN[4]/  
UHPI_HD[12]/  
UPP_D[12]/  
RMII_RXD[1]/  
PRU0_R31[26]  
VP_DIN[2]/  
UHPI_HD[10]/  
UPP_D[10]/  
RMII_RXER/  
PRU0_R31[24]  
VP_DIN[1]/  
UHPI_HD[9]/  
UPP_D[9]/  
RMII_MHZ_50_CLK/  
PRU0_R31[23]  
VP_DIN[0]/  
UHPI_HD[8]/  
UPP_D[8]/  
RMII_CRS_DV/  
PRU1_R31[29]  
PRU0_R30[28]/  
UHPI_HCNTL1/  
UPP_CHA_START/  
GP6[10]  
DDR_DQM[0]  
W
V
U
T
W
V
U
T
DDR_D[7]  
DDR_D[6]  
UPP_2xTXCLK  
VP_DIN[6]/  
UHPI_HD[14]/  
UPP_D[14]/  
RMII_TXD[0]/  
PRU0_R31[28]  
VP_DIN[3]/  
UHPI_HD[11]/  
UPP_D[11]/  
RMII_RXD[0]/  
PRU0_R31[25]  
VP_DIN[15]_  
VSYNC/  
UHPI_HD[7]/  
UPP_D[7]/  
PRU0_R30[15]/  
PRU0_R31[15]  
VP_DIN[14]_  
HSYNC/  
UHPI_HD[6]/  
UPP_D[6]/  
PRU0_R30[14]/  
PRU0_R31[14]  
VP_CLKIN1/  
UHPI_HDS1/  
PRU1_R30[9]/  
GP6[6]/  
DDR_DQS[1]  
DDR_D[5]  
DDR_D[2]  
DDR_D[4]  
PRU1_R31[16]  
VP_DIN[7]/  
UHPI_HD[15]/  
UPP_D[15]/  
RMII_TXD[1]/  
PRU0_R31[29]  
VP_DIN[13]_  
FIELD/  
UHPI_HD[5]/  
UPP_D[5]/  
PRU0_R30[13]/  
PRU0_R31[13]  
PRU0_R30[27]/ PRU0_R30[29]/  
UHPI_HHWIL/ UHPI_HCNTL0/  
UPP_CHA_ENABLE/ UPP_CHA_CLOCK/  
DDR_D[14]  
DDR_ZP  
DDR_D[3]  
DDR_D[1]  
DDR_D[0]  
GP6[9]  
GP6[11]  
VP_DIN[12]/  
UHPI_HD[4]/  
UPP_D[4]/  
PRU0_R30[12]/  
PRU0_R31[12]  
CLKOUT/  
UHPI_HDS2/  
PRU1_R30[13]/  
GP6[14]  
PRU0_R30[26]/  
UHPI_HRW/  
UPP_CHA_WAIT/  
GP6[8]/  
PRU1_R31[17]  
RESETOUT/  
UHPI_HAS/  
PRU1_R30[14]/  
GP6[15]  
DDR_D[9]  
DDR_D[11]  
DDR_D[8]  
DDR_DQS[0]  
RSV2  
VP_DIN[5]/  
UHPI_HD[13]/  
UPP_D[13]/  
RMII_TXEN/  
PRU0_R31[27]  
VP_DIN[9]/  
UHPI_HD[1]/  
UPP_D[1]/  
PRU0_R30[9]/  
PRU0_R31[9]  
VP_DIN[11]/  
UHPI_HD[3]/  
UPP_D[3]/  
PRU0_R30[11]/  
PRU0_R31[11]  
VP_DIN[10]/  
UHPI_HD[2]/  
UPP_D[2]/  
PRU0_R30[10]/  
PRU0_R31[10]  
PRU0_R30[30]/  
UHPI_HINT/  
PRU1_R30[11]/  
GP6[12]  
PRU0_R30[31]/  
UHPI_HRDY/  
PRU1_R30[12]/  
GP6[13]  
DDR_DQGATE0  
DDR_DQGATE1  
DVDD18  
R
P
N
M
L
R
P
N
M
L
VP_DIN[8]/  
UHPI_HD[0]/  
UPP_D[0]/  
GP6[5]/  
V
DVDD3318_C  
USB1_VDDA18  
USB1_VDDA33  
PLL1_VDDA  
PLL1_VSSA  
PLL0_VDDA  
USB0_ID  
USB1_DM  
USB0_VDDA33  
USB0_DM  
USB1_DP  
USB0_VBUS  
USB0_DP  
OSCIN  
DVDD18  
SS  
PRU1_R31[0]  
NC  
USB0_VDDA12  
V
SS  
V
SS  
V
SS  
V
SS  
V
SS  
DVDD3318_C  
DVDD3318_C  
DVDD3318_C  
USB0_VDDA18  
PLL0_VSSA  
USB_CVDD  
NC  
TDI  
RTC_CVDD  
CV  
DD  
TMS  
OSCVSS  
TRST  
GP8[0]  
DVDD3318_C  
DVDD3318_B  
USB0_DRVVBUS  
CV  
DD  
EMU1  
OSCOUT  
K
RESET  
K
11  
12  
13  
14  
15  
16  
17  
18  
19  
Figure 3-2. Pin Map (Quad B)  
Copyright © 2016, Texas Instruments Incorporated  
Terminal Configuration and Functions  
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11  
12  
13  
14  
15  
16  
17  
18  
19  
DV  
V
CV  
DV  
DD3318_B  
RTC_XI  
J
TCK  
EMU0  
TDO  
J
H
G
SS  
DD  
DD18  
NMI  
SPI1_SOMI/  
GP2[11]  
SPI1_ENA/  
GP2[12]  
CV  
CV  
CV  
RV  
DD  
V
SS  
RTC_VSS  
RTC_XO  
DD  
DD  
DD  
H
SPI1_SCS[7]/  
I2C0_SCL/  
TM64P2_OUT12/  
GP1[5]  
SPI1_SCS[6]/  
I2C0_SDA/  
TM64P3_OUT12/  
GP1[4]  
SPI1_SIMO/  
GP2[10]  
SPI1_CLK/  
GP2[13]  
DV  
DV  
DD3318_A  
DV  
DV  
CV  
DD3318_A  
DD18  
DD18  
DD  
G
SPI1_SCS[1]/  
EPWM1A/  
PRU0_R30[8]/  
GP2[15]/  
TM64P2_IN12  
SPI1_SCS[4]/  
UART2_TXD/  
I2C1_SDA/  
GP1[2]  
SPI1_SCS[5]/  
UART2_RXD/  
I2C1_SCL/  
GP1[3]  
SPI1_SCS[2]/  
UART1_TXD/  
SATA_CP_POD/  
GP1[0]  
DV  
DV  
DV  
DV  
DD3318_A  
DD3318_B  
DD3318_B  
DD3318_B  
DV  
F
E
D
C
B
A
DD18  
F
SPI0_SCS[1]/  
TM64P0_OUT12/  
GP1[7]/  
MDCLK/  
TM64P0_IN12  
SPI0_SCS[3]/  
UART0_CTS/  
GP8[2]/  
MII_RXD[1]/  
SATA_MP_SWITCH  
SPI1_SCS[0]/  
EPWM1B/  
PRU0_R30[7]/  
GP2[14]/  
TM64P3_IN12  
EMA_A[18]/  
MMCSD0_DAT[3]/  
PRU1_R30[26]/  
GP4[2]  
EMA_A[16]/  
MMCSD0_DAT[5]/  
PRU1_R30[24]/  
GP4[0]  
SPI1_SCS[3]/  
UART1_RXD/  
SATA_LED/  
GP1[1]  
EMA_A[6]/  
GP5[6]  
DV  
DD3318_B  
CV  
DD  
E
EMA_A[13]/  
PRU0_R30[21]/  
PRU1_R30[21] /  
GP5[13]/  
SPI0_SCS[2]/  
UART0_RTS/  
GP8[1]/  
MII_RXD[0]/  
SATA_CP_DET  
SPI0_SCS[0]/  
TM64P1_OUT12/  
GP1[6]/  
MDIO/  
TM64P1_IN12  
EMA_A[12]/  
PRU1_R30[20]/  
GP5[12]/  
SPI0_CLK/  
EPWM0A/  
GP1[8]/  
SPI0_SCS[4]/  
UART0_TXD/  
GP8[3]/  
EMA_A[9]/  
PRU1_R30[17]/  
GP5[9]  
EMA_A[3]/  
GP5[3]  
EMA_A[1]/  
GP5[1]  
D
PRU1_R31[20]  
MII_RXCLK  
MII_RXD[2]  
PRU1_R31[21]  
EMA_A[15]/  
MMCSD0_DAT[6]/  
PRU1_R30[23]/  
GP5[15]/  
EMA_A[10]/  
PRU1_R30[18]/  
GP5[10]/  
SPI0_SOMI/  
EPWMSYNCI/  
GP8[6]/  
SPI0_SIMO/  
EPWMSYNCO/  
GP8[5]/  
SPI0_ENA/  
EPWM0B/  
PRU0_R30[6]/  
MII_RXDV  
SPI0_SCS[5]/  
UART0_RXD/  
GP8[4]/  
EMA_A[5]/  
GP5[5]  
EMA_A[0]/  
GP5[0]  
EMA_BA[0]/  
GP2[8]  
C
PRU1_R31[18]  
MII_RXER  
MII_CRS  
MII_RXD[3]  
PRU1_R31[23]  
EMA_A[17]/  
MMCSD0_DAT[4]/  
PRU1_R30[25]  
GP4[1]  
EMA_A[11]/  
PRU1_R30[19]/  
GP5[11]/  
EMA_WAIT[0]/  
PRU0_R30[0]/  
GP3[8]/  
EMA_WAIT[1]/  
PRU0_R30[1]/  
GP2[1]/  
EMA_A[7]/  
PRU1_R30[15]/  
GP5[7]  
EMA_A[2]/  
GP5[2]  
EMA_OE/  
GP3[10]  
EMA_CS[5]/  
GP3[12]  
EMA_CS[2]/  
GP3[15]  
B
PRU1_R31[19]  
PRU0_R31[0]  
PRU0_R31[1]  
EMA_A[14]/  
MMCSD0_DAT[7]/  
PRU1_R30[22]/  
GP5[14]/  
EMA_A[20]/  
MMCSD0_DAT[1]/  
PRU1_R30[28]/  
GP4[4]  
EMA_RAS/  
PRU0_R30[3]/  
GP2[5]/  
EMA_A[8]/  
PRU1_R30[16]/  
GP5[8]  
EMA_A[4]/  
GP5[4]  
EMA_BA[1]/  
GP2[9]  
EMA_CS[3]/  
GP3[14]  
EMA_CS[0]/  
GP2[0]  
V
SS  
A
PRU0_R31[3]  
PRU1_R31[22]  
11  
12  
13  
14  
15  
16  
17  
18  
19  
Figure 3-3. Pin Map (Quad C)  
10  
Terminal Configuration and Functions  
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ZHCSFA2 –JUNE 2016  
1
2
3
4
5
6
7
8
9
10  
VP_CLKIN3/  
MMCSD1_DAT[1]/  
PRU1_R30[1]/  
GP6[2]/  
PRU0_R30[23]/  
MMCSD1_CMD/  
UPP_CHB_ENABLE/  
GP8[13]/  
DV  
DV  
DV  
DV  
SATA_TXP  
J
V
V
V
SS  
SATA_TXN  
DD3318_C  
CV  
DD  
SS  
V
SS  
J
SS  
PRU1_R31[2]  
PRU1_R31[25]  
VP_CLKIN2/  
MMCSD1_DAT[3]/  
PRU1_R30[3]/  
GP6[4]/  
MMCSD1_DAT[5]/  
LCD_HSYNC/  
PRU1_R30[5]/  
GP8[9]/  
SATA_VSS  
H
SATA_VSS  
V
V
SS  
DD3318_A  
DD3318_A  
DD3318_A  
CV  
CV  
CV  
DD  
DD  
DD  
SS  
H
G
F
PRU1_R31[4]  
PRU1_R31[6]  
PRU0_R30[25]/  
MMCSD1_DAT[0]/  
PRU0_R30[24]/  
MMCSD1_CLK/  
PRU0_R30[22]/  
PRU1_R30[8]/  
UPP_CHB_CLOCK/ UPP_CHB_START/ UPP_CHB_WAIT/  
MMCSD1_DAT[4]/  
LCD_VSYNC/  
PRU1_R30[4]/  
GP8[8]/  
DV  
DV  
DD3318_B  
DD18  
CV  
DV  
DD18  
CV  
G
DD  
DD  
GP8[15]/  
PRU1_R31[27]  
GP8[14]/  
PRU1_R31[26]  
GP8[12]/  
PRU1_R31[24]  
PRU1_R31[5]  
MMCSD1_DAT[6]/  
LCD_MCLK/  
PRU1_R30[6]/  
GP8[10]/  
AXR0/  
ECAP0_APWM0/  
GP8[7]/  
MII_TXD[0]/  
CLKS0  
RTC_ALARM/  
UART2_CTS/  
GP0[8]/  
MMCSD1_DAT[7]/  
LCD_PCLK/  
PRU1_R30[7]/  
GP8[11]  
EMA_CS[4]/  
GP3[13]  
DV  
DV  
DV  
DV  
DD3318_B  
DD3318_B  
DD3318_B  
DD3318_B  
F
DEEPSLEEP  
PRU1_R31[7]  
AXR8/  
CLKS1/  
ECAP1_APWM1/  
GP0[0]/  
PRU0_R31[8]  
AXR1/  
DX0/  
GP1[9]/  
MII_TXD[1]  
AXR2/  
DR0/  
GP1[10]/  
MII_TXD[2]  
AXR3/  
FSX0/  
GP1[11]/  
MII_TXD[3]  
MMCSD0_CLK/  
PRU1_R30[31]/  
GP4[7]  
EMA_D[15]/  
GP3[7]  
EMA_D[5]/  
GP4[13]  
EMA_D[3]/  
GP4[11]  
EMA_D[8]/  
GP3[0]  
RV  
DD  
E
D
C
B
A
E
D
C
B
A
AXR7/  
AMUTE/  
PRU0_R30[16]/  
UART2_RTS/  
GP0[9]/  
AXR4/  
FSR0/  
GP1[12]/  
MII_COL  
AXR5/  
CLKX0/  
GP1[13]/  
MII_TXCLK  
EMA_SDCKE/  
PRU0_R30[4]/  
GP2[6]/  
EPWM1TZ[0]/  
PRU0_R30[17]  
GP1[15]/  
AXR10/  
DR1/  
GP0[2]  
EMA_D[11]/  
GP3[3]  
EMA_D[7]/  
GP4[15]  
EMA_D[9]/  
GP3[1]  
EMA_A_RW/  
GP3[9]  
PRU0_R31[4]  
PRU0_R31[7]  
PRU0_R31[16]  
AXR6/  
CLKR0/  
GP1[14]/  
MII_TXEN/  
PRU0_R31[6]  
EMA_A[19]/  
MMCSD0_DAT[2]/  
PRU1_R30[27]/  
GP4[3]  
AFSR/  
GP0[13]/  
PRU0_R31[20]  
AXR9/  
DX1/  
GP0[1]  
AXR12/  
FSR1/  
GP0[4]  
AXR11/  
FSX1/  
GP0[3]  
EMA_D[6]/  
GP4[14]  
EMA_D[14]/  
GP3[6]  
EMA_D[0]/  
GP4[8]  
EMA_WEN_DQM[0]/  
GP2[3]  
ACLKX/  
PRU0_R30[19]/  
GP0[14]/  
EMA_CLK/  
PRU0_R30[5]/  
GP2[7]/  
EMA_A[21]/  
MMCSD0_DAT[0]/  
PRU1_R30[29]/  
GP4[5]  
AFSX/  
GP0[12]/  
PRU0_R31[19]  
AXR13/  
CLKX1/  
GP0[5]  
AXR14/  
CLKR1/  
GP0[6]  
EMA_D[4]/  
GP4[12]  
EMA_D[13]/  
GP3[5]  
EMA_D[2]/  
GP4[10]  
EMA_WE/  
GP3[11]  
PRU0_R31[21]  
PRU0_R31[5]  
AHCLKR/  
PRU0_R30[18]/  
UART1_RTS/  
GP0[11]/  
AHCLKX/  
USB_REFCLKIN/  
UART1_CTS/  
GP0[10]/  
ACLKR/  
PRU0_R30[20]/  
GP0[15]/  
AXR15/  
EPWM0TZ[0]/  
ECAP2_APWM2/  
GP0[7]  
EMA_A[22]/  
MMCSD0_CMD/  
PRU1_R30[30]/  
GP4[6]  
EMA_CAS/  
PRU0_R30[2]/  
GP2[4]/  
EMA_D[12]/  
GP3[4]  
EMA_D[10]/  
GP3[2]  
EMA_D[1]/  
GP4[9]  
EMA_WEN_DQM[1]/  
GP2[2]  
PRU0_R31[22]  
PRU0_R31[2]  
PRU0_R31[18]  
PRU0_R31[17]  
1
2
3
4
5
6
7
8
9
10  
Figure 3-4. Pin Map (Quad D)  
Copyright © 2016, Texas Instruments Incorporated  
Terminal Configuration and Functions  
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3.2 Pin Attributes  
Table 3-1 to Table 3-27 identify the external signal names, the associated pin/ball numbers along with the  
mechanical package designator, the pin type (I, O, IO, OZ, or PWR), whether the pin/ball has any internal  
pullup/pulldown resistors, whether the pin/ball is configurable as an IO in GPIO mode, and a functional pin  
description.  
3.2.1 Device Reset, NMI and JTAG  
Table 3-1. Reset, NMI and JTAG Terminal Functions  
SIGNAL  
NAME  
POWER  
TYPE(1)  
PULL(2)  
DESCRIPTION  
GROUP(3)  
NO.  
RESET  
RESET  
NMI  
K14  
J17  
I
I
IPU  
IPU  
B
B
Device reset input  
Non-Maskable Interrupt  
RESETOUT / UHPI_HAS / PRU1_R30[14] /  
GP6[15]  
T17  
O(4)  
CP[21]  
C
Reset output  
JTAG  
TMS  
TDI  
L16  
M16  
J18  
J15  
L17  
J16  
K16  
I
I
IPU  
IPU  
IPU  
IPU  
IPD  
IPU  
IPU  
B
B
B
B
B
B
B
JTAG test mode select  
JTAG test data input  
JTAG test data output  
JTAG test clock  
TDO  
TCK  
O
I
TRST  
EMU0  
EMU1  
I
JTAG test reset  
I/O  
I/O  
Emulation pin  
Emulation pin  
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.  
Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for  
that particular peripheral.  
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor. CP[n] = configurable pull-up/pull-down (where n is the pin group) using  
the PUPDENA and PUPDSEL registers in the System Module. For more detailed information on pullup/pulldown resistors and situations  
where external pullup/pulldown resistors are required, see the Pullup/Pulldown Resistors section. For electrical specifications on pullup  
and internal pulldown circuits, see the Specifications section.  
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can  
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of  
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power  
supply DVDD3318_C.  
(4) Open drain mode for RESETOUT function.  
12  
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3.2.2 High-Frequency Oscillator and PLL  
Table 3-2. High-Frequency Oscillator and PLL Terminal Functions  
SIGNAL  
NAME  
POWER  
TYPE(1)  
PULL(2)  
DESCRIPTION  
PLL Observation Clock  
GROUP(3)  
NO.  
CLKOUT / UHPI_HDS2 /  
PRU1_R30[13] / GP6[14]  
T18  
O
CP[22]  
C
1.2-V OSCILLATOR  
OSCIN  
L19  
K19  
L18  
I
—
—
—
—
Oscillator input  
Oscillator output  
Oscillator ground  
OSCOUT  
OSCVSS  
O
—
GND  
—
1.2-V PLL0  
PLL0_VDDA  
PLL0_VSSA  
L15  
PWR  
GND  
—
—
—
PLL analog VDD (1.2-V filtered supply)  
PLL analog VSS (for filter)  
M17  
—
1.2-V PLL1  
PLL1_VDDA  
PLL1_VSSA  
N15  
M15  
PWR  
GND  
—
—
—
—
PLL analog VDD (1.2-V filtered supply)  
PLL analog VSS (for filter)  
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.  
Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for  
that particular peripheral.  
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using  
the PUPDENA and PUPDSEL registers in the System Module. For more detailed information on pullup/pulldown resistors and situations  
where external pullup/pulldown resistors are required, see the Pullup/Pulldown Resistors section. For electrical specifications on pullup  
and internal pulldown circuits, see the Specifications section.  
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can  
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of  
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power  
supply DVDD3318_C.  
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3.2.3 Real-Time Clock and 32-kHz Oscillator  
Table 3-3. Real-Time Clock (RTC) and 1.2-V, 32-kHz Oscillator Terminal Functions  
SIGNAL  
NAME  
POWER  
TYPE(1)  
PULL(2)  
DESCRIPTION  
GROUP(3)  
NO.  
J19  
H19  
F4  
RTC_XI  
I
—
—
—
—
A
RTC 32-kHz oscillator input  
RTC 32-kHz oscillator output  
RTC Alarm  
RTC_XO  
O
O
RTC_ALARM / UART2_CTS / GP0[8] / DEEPSLEEP  
CP[0]  
RTC module core power  
(isolated from chip CVDD  
RTC_CVDD  
RTC_Vss  
L14  
H18  
PWR  
GND  
—
—
—
—
)
Oscillator ground  
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.  
Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for  
that particular peripheral.  
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using  
the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the  
device is out of reset. During reset, all of the pins associated with these registers are pulled down. If the application requires a pull-up,  
an external pull-up can be used. For more detailed information on pullup/pulldown resistors and situations where external  
pullup/pulldown resistors are required, see the Pullup/Pulldown Resistors section. For electrical specifications on pullup and internal  
pulldown circuits, see the Specifications section.  
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can  
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of  
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power  
supply DVDD3318_C.  
3.2.4 DEEPSLEEP Power Control  
Table 3-4. DEEPSLEEP Power Control Terminal Functions  
SIGNAL  
NAME  
POWER  
TYPE(1)  
PULL(2)  
DESCRIPTION  
GROUP(3)  
NO.  
RTC_ALARM / UART2_CTS / GP0[8] / DEEPSLEEP  
F4  
I
CP[0]  
A
DEEPSLEEP power control output  
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.  
Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for  
that particular peripheral.  
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using  
the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the  
device is out of reset. During reset, all of the pins associated with these registers are pulled down. If the application requires a pull-up,  
an external pull-up can be used. For more detailed information on pullup/pulldown resistors and situations where external  
pullup/pulldown resistors are required, see the Pullup/Pulldown Resistors section. For electrical specifications on pullup and internal  
pulldown circuits, see the Specifications section.  
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can  
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of  
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power  
supply DVDD3318_C.  
14  
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3.2.5 External Memory Interface A (EMIFA)  
Table 3-5. External Memory Interface A (EMIFA) Terminal Functions  
SIGNAL  
NAME  
POWER  
TYPE(1)  
PULL(2)  
DESCRIPTION  
GROUP(3)  
NO.  
E6  
C7  
B6  
A6  
D6  
A7  
D9  
E10  
D7  
C6  
E7  
B5  
E8  
B8  
A8  
C9  
EMA_D[15] / GP3[7]  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
CP[17]  
CP[17]  
CP[17]  
CP[17]  
CP[17]  
CP[17]  
CP[17]  
CP[17]  
CP[17]  
CP[17]  
CP[17]  
CP[17]  
CP[17]  
CP[17]  
CP[17]  
CP[17]  
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
EMA_D[14] / GP3[6]  
EMA_D[13] / GP3[5]  
EMA_D[12] / GP3[4]  
EMA_D[11] / GP3[3]  
EMA_D[10] / GP3[2]  
EMA_D[9] / GP3[1]  
EMA_D[8] / GP3[0]  
EMA_D[7] / GP4[15]  
EMA_D[6] / GP4[14]  
EMA_D[5] / GP4[13]  
EMA_D[4] / GP4[12]  
EMA_D[3] / GP4[11]  
EMA_D[2] / GP4[10]  
EMA_D[1] / GP4[9]  
EMA_D[0] / GP4[8]  
EMIFA data bus  
EMA_A[22] / MMCSD0_CMD /  
PRU1_R30[30] / GP4[6]  
A10  
B10  
A11  
C10  
E11  
B11  
E12  
C11  
A12  
D11  
D13  
O
O
O
O
O
O
O
O
O
O
O
CP[18]  
CP[18]  
CP[18]  
CP[18]  
CP[18]  
CP[18]  
CP[18]  
CP[19]  
CP[19]  
CP[19]  
CP[19]  
B
B
B
B
B
B
B
B
B
B
B
EMA_A[21] / MMCSD0_DAT[0] /  
PRU1_R30[29] / GP4[5]  
EMA_A[20] / MMCSD0_DAT[1] /  
PRU1_R30[28] / GP4[4]  
EMA_A[19] / MMCSD0_DAT[2] /  
PRU1_R30[27] / GP4[3]  
EMA_A[18] / MMCSD0_DAT[3] /  
PRU1_R30[26] / GP4[2]  
EMA_A[17] / MMCSD0_DAT[4] /  
PRU1_R30[25] / GP4[1]  
EMIFA address bus  
EMA_A[16] / MMCSD0_DAT[5] /  
PRU1_R30[24] / GP4[0]  
EMA_A[15] / MMCSD0_DAT[6] /  
PRU1_R30[23] / GP5[15] / PRU1_R31[23]  
EMA_A[14] / MMCSD0_DAT[7] /  
PRU1_R30[22] / GP5[14] / PRU1_R31[22]  
EMA_A[13] / PRU0_R30[21] / PRU1_R30[21]  
/ GP5[13] / PRU1_R31[21]  
EMA_A[12] / PRU1_R30[20] / GP5[12] /  
PRU1_R31[20]  
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.  
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name  
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured  
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different  
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.  
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using  
the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the  
device is out of reset. During reset, all of the pins associated with these registers are pulled down. If the application requires a pull-up,  
an external pull-up can be used. For more detailed information on pullup/pulldown resistors and situations where external  
pullup/pulldown resistors are required, see the Pullup/Pulldown Resistors section. For electrical specifications on pullup and internal  
pulldown circuits, see the Specifications section.  
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can  
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of  
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power  
supply DVDD3318_C.  
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Table 3-5. External Memory Interface A (EMIFA) Terminal Functions (continued)  
SIGNAL  
NAME  
POWER  
TYPE(1)  
PULL(2)  
DESCRIPTION  
GROUP(3)  
NO.  
EMA_A[11] / PRU1_R30[19] / GP5[11] /  
PRU1_R31[19]  
B12  
O
O
CP[19]  
CP[19]  
B
B
EMA_A[10] / PRU1_R30[18] / GP5[10] /  
PRU1_R31[18]  
C12  
EMA_A[9] / PRU1_R30[17] / GP5[9]  
EMA_A[8] / PRU1_R30[16] / GP5[8]  
EMA_A[7] / PRU1_R30[15] / GP5[7]  
EMA_A[6] / GP5[6]  
D12  
A13  
B13  
E13  
C13  
A14  
D14  
B14  
D15  
C14  
C15  
A15  
O
O
O
O
O
O
O
O
O
O
O
O
CP[19]  
CP[19]  
CP[20]  
CP[20]  
CP[20]  
CP[20]  
CP[20]  
CP[20]  
CP[20]  
CP[20]  
CP[16]  
CP[16]  
B
B
B
B
B
B
B
B
B
B
B
B
EMIFA address bus  
EMA_A[5] / GP5[5]  
EMA_A[4] / GP5[4]  
EMA_A[3] / GP5[3]  
EMA_A[2] / GP5[2]  
EMA_A[1] / GP5[1]  
EMA_A[0] / GP5[0]  
EMA_BA[0] / GP2[8]  
EMIFA bank address  
EMA_BA[1] / GP2[9]  
EMA_CLK / PRU0_R30[5] / GP2[7] /  
PRU0_R31[5]  
B7  
D8  
O
O
O
O
CP[16]  
CP[16]  
CP[16]  
CP[16]  
B
B
B
B
EMIFA clock  
EMA_SDCKE / PRU0_R30[4] / GP2[6] /  
PRU0_R31[4]  
EMIFA SDRAM clock enable  
EMA_RAS / PRU0_R30[3] / GP2[5] /  
PRU0_R31[3]  
A16  
A9  
EMIFA SDRAM row address strobe  
EMA_CAS / PRU0_R30[2] / GP2[4] /  
PRU0_R31[2]  
EMIFA SDRAM column address strobe  
EMIFA SDRAM Chip Select  
EMA_CS[0] / GP2[0]  
EMA_CS[2] / GP3[15]  
EMA_CS[3] / GP3[14]  
EMA_CS[4] / GP3[13]  
EMA_CS[5] / GP3[12]  
EMA_A_RW / GP3[9]  
EMA_WE / GP3[11]  
A18  
B17  
A17  
F9  
O
O
O
O
O
O
O
CP[16]  
CP[16]  
CP[16]  
CP[16]  
CP[16]  
CP[16]  
CP[16]  
B
B
B
B
B
B
B
EMIFA Async chip select  
B16  
D10  
B9  
EMIFA Async Read/Write control  
EMIFA SDRAM write enable  
EMIFA write enable/data mask for  
EMA_D[15:8]  
EMA_WEN_DQM[1] / GP2[2]  
A5  
O
CP[16]  
B
EMA_WEN_DQM[0] / GP2[3]  
EMA_OE / GP3[10]  
C8  
O
O
CP[16]  
CP[16]  
B
B
EMIFA write enable/data mask for EMA_D[7:0]  
EMIFA output enable  
B15  
EMA_WAIT[0] / PRU0_R30[0] / GP3[8] /  
PRU0_R31[0]  
B18  
B19  
I
I
CP[16]  
CP[16]  
B
B
EMIFA wait input/interrupt  
EMA_WAIT[1] / PRU0_R30[1] / GP2[1] /  
PRU0_R31[1]  
16  
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3.2.6 DDR2/mDDR Controller  
Table 3-6. DDR2/mDDR Terminal Functions  
SIGNAL  
NAME  
TYPE(1)  
PULL(2)  
DESCRIPTION  
NO.  
W10  
U11  
V10  
U10  
T12  
T10  
T11  
T13  
W11  
W12  
V12  
V13  
U13  
V14  
U14  
U15  
T5  
DDR_D[15]  
DDR_D[14]  
DDR_D[13]  
DDR_D[12]  
DDR_D[11]  
DDR_D[10]  
DDR_D[9]  
DDR_D[8]  
DDR_D[7]  
DDR_D[6]  
DDR_D[5]  
DDR_D[4]  
DDR_D[3]  
DDR_D[2]  
DDR_D[1]  
DDR_D[0]  
DDR_A[13]  
DDR_A[12]  
DDR_A[11]  
DDR_A[10]  
DDR_A[9]  
DDR_A[8]  
DDR_A[7]  
DDR_A[6]  
DDR_A[5]  
DDR_A[4]  
DDR_A[3]  
DDR_A[2]  
DDR_A[1]  
DDR_A[0]  
DDR_CLKP  
DDR_CLKN  
DDR_CKE  
DDR_WE  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
O
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
DDR2 SDRAM data bus  
V4  
O
T4  
O
W4  
T6  
O
O
U4  
O
U6  
O
DDR2 row/column address  
W5  
V5  
O
O
U5  
O
V6  
O
W6  
T7  
O
O
U7  
O
W8  
W7  
V7  
O
DDR2 clock (positive)  
DDR2 clock (negative)  
DDR2 clock enable  
O
O
T8  
O
DDR2 write enable  
DDR_RAS  
DDR_CAS  
DDR_CS  
W9  
U9  
O
DDR2 row address strobe  
O
DDR2 column address strobe  
DDR2 chip select  
V9  
O
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.  
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name  
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured  
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different  
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.  
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using  
the PUPDENA and PUPDSEL registers in the System Module. For more detailed information on pullup/pulldown resistors and situations  
where external pullup/pulldown resistors are required, see the Pullup/Pulldown Resistors section. For electrical specifications on pullup  
and internal pulldown circuits, see the Specifications section.  
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Table 3-6. DDR2/mDDR Terminal Functions (continued)  
SIGNAL  
NAME  
TYPE(1)  
PULL(2)  
DESCRIPTION  
NO.  
W13  
R10  
T14  
V11  
U8  
DDR_DQM[0]  
DDR_DQM[1]  
DDR_DQS[0]  
DDR_DQS[1]  
DDR_BA[2]  
O
O
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
IPD  
DDR2 data mask outputs  
I/O  
I/O  
O
DDR2 data strobe inputs/outputs  
DDR2 SDRAM bank address  
DDR_BA[1]  
T9  
O
DDR_BA[0]  
V8  
O
DDR2 loopback signal for external DQS gating.  
Route to DDR and back to DDR_DQGATE1 with  
same constraints as used for DDR clock and data.  
DDR_DQGATE0  
DDR_DQGATE1  
DDR_ZP  
R11  
R12  
U12  
R6  
O
I
IPD  
IPD  
—
DDR2 loopback signal for external DQS gating.  
Route to DDR and back to DDR_DQGATE0 with  
same constraints as used for DDR clock and data.  
DDR2 reference output for drive strength calibration  
of N and P channel outputs. Tie to ground via 50  
ohm resistor @ 5% tolerance.  
O
I
DDR voltage input for the DDR2/mDDR I/O buffers.  
Note even in the case of mDDR an external resistor  
divider connected to this pin is necessary.  
DDR_VREF  
—
N6, N9, N10,  
P7, P8, P9,  
P10, R7, R8,  
R9  
DDR_DVDD18  
PWR  
—
DDR PHY 1.8V power supply pins  
18  
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3.2.7 Serial Peripheral Interface Modules (SPI)  
Table 3-7. Serial Peripheral Interface (SPI) Terminal Functions  
SIGNAL  
NAME  
POWER  
TYPE(1)  
PULL(2)  
DESCRIPTION  
GROUP(3)  
NO.  
SPI0  
SPI0_CLK / EPWM0A / GP1[8] / MII_RXCLK  
D19  
C17  
D17  
E16  
I/O  
I/O  
I/O  
I/O  
I/O  
CP[7]  
CP[7]  
A
A
A
A
A
SPI0 clock  
SPI0_ENA / EPWM0B / PRU0_R30[6] / MII_RXDV  
SPI0 enable  
SPI0_SCS[0] / TM64P1_OUT12 / GP1[6] / MDIO / TM64P1_IN12  
SPI0_SCS[1] / TM64P0_OUT12 / GP1[7] / MDCLK / TM64P0_IN12  
CP[10]  
CP[10]  
CP[9]  
SPI0_SCS[2] / UART0_RTS / GP8[1] / MII_RXD[0] /SATA_CP_DET D16  
SPI0 chip selects  
SPI0_SCS[3] / UART0_CTS / GP8[2] / MII_RXD[1] /  
SATA_MP_SWITCH  
E17  
I/O  
CP[9]  
A
SPI0_SCS[4] / UART0_TXD / GP8[3] / MII_RXD[2]  
SPI0_SCS[5] / UART0_RXD / GP8[4] / MII_RXD[3]  
D18  
C19  
I/O  
I/O  
CP[8]  
CP[8]  
A
A
SPI0 data slave-in-  
master-out  
SPI0_SIMO / EPWMSYNCO / GP8[5] / MII_CRS  
SPI0_SOMI / EPWMSYNCI / GP8[6] / MII_RXER  
C18  
C16  
I/O  
I/O  
CP[7]  
CP[7]  
A
A
SPI0 data slave-out-  
master-in  
SPI1  
SPI1_CLK / GP2[13]  
G19  
H16  
E19  
F18  
F19  
E18  
F16  
F17  
G18  
G16  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
CP[15]  
CP[15]  
CP[14]  
CP[14]  
CP[13]  
CP[13]  
CP[12]  
CP[12]  
CP[11]  
CP[11]  
A
A
A
A
A
A
A
A
A
A
SPI1 clock  
SPI1_ENA / GP2[12]  
SPI1 enable  
SPI1_SCS[0] / EPWM1B / PRU0_R30[7] / GP2[14] / TM64P3_IN12  
SPI1_SCS[1] / EPWM1A / PRU0_R30[8] / GP2[15] / TM64P2_IN12  
SPI1_SCS[2] / UART1_TXD / SATA_CP_POD / GP1[0]  
SPI1_SCS[3] / UART1_RXD / SATA_LED / GP1[1]  
SPI1_SCS[4] / UART2_TXD / I2C1_SDA / GP1[2]  
SPI1_SCS[5] / UART2_RXD / I2C1_SCL / GP1[3]  
SPI1_SCS[6] / I2C0_SDA / TM64P3_OUT12 / GP1[4]  
SPI1_SCS[7] / I2C0_SCL / TM64P2_OUT12 / GP1[5]  
SPI1 chip selects  
SPI1 data slave-in-  
master-out  
SPI1_SIMO / GP2[10]  
SPI1_SOMI / GP2[11]  
G17  
H17  
I/O  
I/O  
CP[15]  
CP[15]  
A
A
SPI1 data slave-out-  
master-in  
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.  
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name  
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured  
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different  
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.  
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using  
the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the  
device is out of reset. During reset, all of the pins associated with these registers are pulled down. If the application requires a pull-up,  
an external pull-up can be used. For more detailed information on pullup/pulldown resistors and situations where external  
pullup/pulldown resistors are required, see the Pullup/Pulldown Resistors section. For electrical specifications on pullup and internal  
pulldown circuits, see the Specifications section.  
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can  
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of  
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power  
supply DVDD3318_C.  
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Terminal Configuration and Functions  
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3.2.8 Programmable Real-Time Unit (PRU)  
Table 3-8. Programmable Real-Time Unit (PRU) Terminal Functions  
SIGNAL  
POWER  
TYPE(1)  
PULL(2)  
DESCRIPTION  
GROUP(3)  
NAME  
NO.  
R17  
R16  
U17  
W15  
U16  
PRU0_R30[31] / UHPI_HRDY / PRU1_R30[12] / GP6[13]  
PRU0_R30[30] / UHPI_HINT / PRU1_R30[11] / GP6[12]  
PRU0_R30[29]/ UHPI_HCNTL0 / UPP_CHA_CLOCK / GP6[11]  
PRU0_R30[28] / UHPI_HCNTL1 / UPP_CHA_START / GP6[10]  
PRU0_R30[27] / UHPI_HHWIL / UPP_CHA_ENABLE / GP6[9]  
O
O
O
O
O
O
CP[23]  
CP[23]  
CP[24]  
CP[24]  
CP[24]  
CP[24]  
C
C
C
C
C
C
PRU0_R30[26] / UHPI_HRW / UPP_CHA_WAIT / GP6[8] / PRU1_R31[17] T15  
PRU0_R30[25] / MMCSD1_DAT[0] / UPP_CHB_CLOCK / GP8[15] /  
PRU1_R31[27]  
G1  
O
O
O
O
CP30]  
CP[30]  
CP[30]  
CP[30]  
C
C
C
C
PRU0_R30[24] / MMCSD1_CLK / UPP_CHB_START / GP8[14] /  
PRU1_R31[26]  
G2  
PRU0 Output  
Signals  
PRU0_R30[23] / MMCSD1_CMD / UPP_CHB_ENABLE / GP8[13] /  
PRU1_R31[25]  
J4  
PRU0_R30[22] / PRU1_R30[8]UPP_CHB_WAIT / / GP8[12] /  
PRU1_R31[24]  
G3  
EMA_A[13] / PRU0_R30[21] / PRU1_R30[21] / GP5[13] / PRU1_R31[21]  
ACLKR / PRU0_R30[20] / GP0[15] / PRU0_R31[22]  
D11  
A1  
O
O
O
O
O
CP[19]  
CP[0]  
CP[0]  
CP[0]  
CP[4]  
B
A
A
A
A
ACLKX / PRU0_R30[19] / GP0[14] / PRU0_R31[21]  
B1  
AHCLKR / PRU0_R30[18] / UART1_RTS / GP0[11] / PRU0_R31[18]  
AXR7 / EPWM1TZ[0] / PRU0_R30[17] / GP1[15] / PRU0_R31[7]  
A2  
D2  
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.  
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name  
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured  
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different  
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.  
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using  
the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the  
device is out of reset. During reset, all of the pins associated with these registers are pulled down. If the application requires a pull-up,  
an external pull-up can be used. For more detailed information on pullup/pulldown resistors and situations where external  
pullup/pulldown resistors are required, see the Pullup/Pulldown Resistors section. For electrical specifications on pullup and internal  
pulldown circuits, see the Specifications section.  
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can  
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of  
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power  
supply DVDD3318_C.  
20  
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Table 3-8. Programmable Real-Time Unit (PRU) Terminal Functions (continued)  
SIGNAL  
NAME  
POWER  
TYPE(1)  
PULL(2)  
DESCRIPTION  
GROUP(3)  
NO.  
AMUTE / PRU0_R30[16] / UART2_RTS / GP0[9] / PRU0_R31[16]  
D5  
O
O
CP[0]  
A
C
VP_DIN[15]_VSYNC / UHPI_HD[7] / UPP_D[7] / PRU0_R30[15] /  
PRU0_R31[15]  
V18  
V19  
U19  
CP[27]  
VP_DIN[14]_HSYNC / UHPI_HD[6] / UPP_D[6] / PRU0_R30[14] /  
PRU0_R31[14]  
O
O
CP[27]  
CP[27]  
C
C
VP_DIN[13]_FIELD / UHPI_HD[5] / UPP_D[5] / PRU0_R30[13] /  
PRU0_R31[13]  
VP_DIN[12] / UHPI_HD[4] / UPP_D[4] / PRU0_R30[12] / PRU0_R31[12]  
VP_DIN[11] / UHPI_HD[3] / UPP_D[3] / PRU0_R30[11] / PRU0_R31[11]  
VP_DIN[10] / UHPI_HD[2] / UPP_D[2] / PRU0_R30[10] / PRU0_R31[10]  
VP_DIN[9] / UHPI_HD[1] / UPP_D[1] / PRU0_R30[9] / PRU0_R31[9]  
SPI1_SCS[1] / EPWM1A / PRU0_R30[8] / GP2[15] / TM64P2_IN12  
SPI1_SCS[0] / EPWM1B / PRU0_R30[7] / GP2[14] / TM64P3_IN12  
SPI0_ENA / EPWM0B / PRU0_R30[6] / MII_RXDV  
T16  
R18  
R19  
R15  
F18  
E19  
C17  
B7  
O
O
O
O
O
O
O
O
O
O
O
O
O
CP[27]  
CP[27]  
CP[27]  
CP[27]  
CP[14]  
CP[14]  
CP[7]  
C
C
C
C
A
A
A
B
B
B
B
B
B
PRU0 Output  
Signals  
EMA_CLK / PRU0_R30[5] / GP2[7] / PRU0_R31[5]  
CP[16]  
CP[16]  
CP[16]  
CP[16]  
CP[16]  
CP[16]  
EMA_SDCKE / PRU0_R30[4] / GP2[6] / PRU0_R31[4]  
D8  
EMA_RAS / PRU0_R30[3] / GP2[5] / PRU0_R31[3]  
A16  
A9  
EMA_CAS / PRU0_R30[2] / GP2[4] / PRU0_R31[2]  
EMA_WAIT[1] / PRU0_R30[1] / GP2[1] / PRU0_R31[1]  
B19  
B18  
EMA_WAIT[0] / PRU0_R30[0] / GP3[8] / PRU0_R31[0]  
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DESCRIPTION  
Table 3-8. Programmable Real-Time Unit (PRU) Terminal Functions (continued)  
SIGNAL  
POWER  
TYPE(1)  
PULL(2)  
GROUP(3)  
NAME  
NO.  
U18  
V16  
R14  
W16  
V17  
W17  
VP_DIN[7] / UHPI_HD[15] / UPP_D[15] / RMII_TXD[1] / PRU0_R31[29]  
VP_DIN[6] / UHPI_HD[14] / UPP_D[14] / RMII_TXD[0] / PRU0_R31[28]  
VP_DIN[5] / UHPI_HD[13] / UPP_D[13] / RMII_TXEN / PRU0_R31[27]  
VP_DIN[4] / UHPI_HD[12] / UPP_D[12] / RMII_RXD[1] / PRU0_R31[26]  
VP_DIN[3] / UHPI_HD[11] / UPP_D[11] / RMII_RXD[0] / PRU0_R31[25]  
VP_DIN[2] / UHPI_HD[10] / UPP_D[10] / RMII_RXER / PRU0_R31[24]  
I
I
I
I
I
I
CP[26]  
CP[26]  
CP[26]  
CP[26]  
CP[26]  
CP[26]  
C
C
C
C
C
C
VP_DIN[1] / UHPI_HD[9] / UPP_D[9] / RMII_MHZ_50_CLK /  
PRU0_R31[23]  
W18  
I
CP[26]  
C
ACLKR / PRU0_R30[20] / GP0[15] / PRU0_R31[22]  
ACLKX / PRU0_R30[19] / GP0[14] / PRU0_R31[21]  
AFSR / GP0[13] / PRU0_R31[20]  
A1  
B1  
C2  
B2  
A2  
A3  
D5  
I
I
I
I
I
I
I
CP[0]  
CP[0]  
CP[0]  
CP[0]  
CP[0]  
CP[0]  
CP[0]  
A
A
A
A
A
A
A
AFSX / GP0[12] / PRU0_R31[19]  
AHCLKR / PRU0_R30[18] / UART1_RTS / GP0[11] / PRU0_R31[18]  
AHCLKX / USB_REFCLKIN / UART1_CTS / GP0[10] / PRU0_R31[17]  
AMUTE / PRU0_R30[16] / UART2_RTS / GP0[9] / PRU0_R31[16]  
VP_DIN[15]_VSYNC / UHPI_HD[7] / UPP_D[7] / PRU0_R30[15] /  
PRU0_R31[15]  
V18  
V19  
U19  
I
I
I
CP[27]  
CP[27]  
CP[27]  
C
C
C
PRU0 Input  
Signals  
VP_DIN[14]_HSYNC / UHPI_HD[6] / UPP_D[6] / PRU0_R30[14] /  
PRU0_R31[14]  
VP_DIN[13]_FIELD / UHPI_HD[5] / UPP_D[5] / PRU0_R30[13] /  
PRU0_R31[13]  
VP_DIN[12] / UHPI_HD[4] / UPP_D[4] / PRU0_R30[12] / PRU0_R31[12]  
VP_DIN[11] / UHPI_HD[3] / UPP_D[3] / PRU0_R30[11] / PRU0_R31[11]  
VP_DIN[10] / UHPI_HD[2] / UPP_D[2] / PRU0_R30[10] / PRU0_R31[10]  
VP_DIN[9] / UHPI_HD[1] / UPP_D[1] / PRU0_R30[9] / PRU0_R31[9]  
AXR8 / CLKS1 / ECAP1_APWM1 / GP0[0] / PRU0_R31[8]  
AXR7 / EPWM1TZ[0] / PRU0_R30[17] / GP1[15] / PRU0_R31[7]  
AXR6 / CLKR0 / GP1[14] / MII_TXEN / PRU0_R31[6]  
T16  
R18  
R19  
R15  
E4  
I
I
I
I
I
I
I
I
I
I
I
I
I
CP[27]  
CP[27]  
CP[27]  
CP[27]  
CP[3]  
C
C
C
C
A
A
A
B
B
B
B
B
B
D2  
CP[4]  
C1  
CP[5]  
EMA_CLK / PRU0_R30[5] / GP2[7] / PRU0_R31[5]  
B7  
CP[16]  
CP[16]  
CP[16]  
CP[16]  
CP[16]  
CP[16]  
EMA_SDCKE / PRU0_R30[4] / GP2[6] / PRU0_R31[4]  
D8  
EMA_RAS / PRU0_R30[3] / GP2[5] / PRU0_R31[3]  
A16  
A9  
EMA_CAS / PRU0_R30[2] / GP2[4] / PRU0_R31[2]  
EMA_WAIT[1] / PRU0_R30[1] / GP2[1] / PRU0_R31[1]  
EMA_WAIT[0] / PRU0_R30[0] / GP3[8] / PRU0_R31[0]  
B19  
B18  
22  
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Table 3-8. Programmable Real-Time Unit (PRU) Terminal Functions (continued)  
SIGNAL  
NAME  
POWER  
TYPE(1)  
PULL(2)  
DESCRIPTION  
GROUP(3)  
NO.  
E9  
MMCSD0_CLK / PRU1_R30[31] /GP4[7]  
O
O
O
O
O
O
O
O
CP[18]  
CP[18]  
CP[18]  
CP[18]  
CP[18]  
CP[18]  
CP[18]  
CP[18]  
B
B
B
B
B
B
B
B
EMA_A[22] / MMCSD0_CMD / PRU1_R30[30] / GP4[6]  
EMA_A[21] / MMCSD0_DAT[0] / PRU1_R30[29] / GP4[5]  
EMA_A[20] / MMCSD0_DAT[1] / PRU1_R30[28] / GP4[4]  
EMA_A[19] / MMCSD0_DAT[2] / PRU1_R30[27] / GP4[3]  
EMA_A[18] / MMCSD0_DAT[3] / PRU1_R30[26] / GP4[2]  
EMA_A[17] / MMCSD0_DAT[4] / PRU1_R30[25] / GP4[1]  
EMA_A[16] / MMCSD0_DAT[5] / PRU1_R30[24] / GP4[0]  
A10  
B10  
A11  
C10  
E11  
B11  
E12  
EMA_A[15] / MMCSD0_DAT[6] / PRU1_R30[23] / GP5[15] /  
PRU1_R31[23]  
C11  
A12  
O
O
CP[19]  
CP[19]  
B
B
EMA_A[14] / MMCSD0_DAT[7] / PRU1_R30[22] / GP5[14] /  
PRU1_R31[22]  
EMA_A[13] / PRU0_R30[21] / PRU1_R30[21] / GP5[13] / PRU1_R31[21]  
EMA_A[12] / PRU1_R30[20] / GP5[12] / PRU1_R31[20]  
EMA_A[11] / PRU1_R30[19] / GP5[11] / PRU1_R31[19]  
EMA_A[10] / PRU1_R30[18] / GP5[10] / PRU1_R31[18]  
EMA_A[9] / PRU1_R30[17] / GP5[9]  
D11  
D13  
B12  
C12  
D12  
A13  
B13  
T17  
T18  
R17  
R16  
W14  
V15  
O
O
O
O
O
O
O
O
O
O
O
O
O
CP[19]  
CP[19]  
CP[19]  
CP[19]  
CP[19]  
CP[19]  
CP[20]  
CP[21]  
CP[22]  
CP[23]  
CP[23]  
CP[25]  
CP[25]  
B
B
B
B
B
B
B
C
C
C
C
C
C
EMA_A[8] / PRU1_R30[16] / GP5[8]  
PRU1 Output  
Signals  
EMA_A[7] / PRU1_R30[15] / GP5[7]  
RESETOUT / UHPI_HAS / PRU1_R30[14] / GP6[15]  
CLKOUT / UHPI_HDS2 / PRU1_R30[13] / GP6[14]  
PRU0_R30[31] / UHPI_HRDY / PRU1_R30[12] / GP6[13]  
PRU0_R30[30] / UHPI_HINT / PRU1_R30[11] / GP6[12]  
VP_CLKIN0 / UHPI_HCS / PRU1_R30[10] / GP6[7] / UPP_2xTXCLK  
VP_CLKIN1 / UHPI_HDS1 / PRU1_R30[9] / GP6[6] / PRU1_R31[16]  
PRU0_R30[22] / PRU1_R30[8] / UPP_CHB_WAIT / GP8[12] /  
PRU1_R31[24]  
G3  
O
CP[30]  
C
MMCSD1_DAT[7] / LCD_PCLK / PRU1_R30[7] / GP8[11]  
F1  
F2  
O
O
O
O
O
CP[31]  
CP[31]  
CP[31]  
CP[31]  
CP[30]  
C
C
C
C
C
MMCSD1_DAT[6] / LCD_MCLK / PRU1_R30[6] / GP8[10] / PRU1_R31[7]  
MMCSD1_DAT[5] / LCD_HSYNC / PRU1_R30[5] / GP8[9] / PRU1_R31[6] H4  
MMCSD1_DAT[4] / LCD_VSYNC / PRU1_R30[4] / GP8[8] / PRU1_R31[5] G4  
VP_CLKIN2 / MMCSD1_DAT[3] / PRU1_R30[3] / GP6[4] / PRU1_R31[4]  
H3  
VP_CLKOUT2 / MMCSD1_DAT[2] / PRU1_R30[2] / GP6[3] /  
PRU1_R31[3]  
K3  
O
CP[30]  
C
VP_CLKIN3 / MMCSD1_DAT[1] / PRU1_R30[1] / GP6[2] / PRU1_R31[2]  
VP_CLKOUT3 / PRU1_R30[0] / GP6[1] / PRU1_R31[1]  
J3  
O
O
CP[30]  
CP[30]  
C
C
K4  
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DESCRIPTION  
Table 3-8. Programmable Real-Time Unit (PRU) Terminal Functions (continued)  
SIGNAL  
NAME  
POWER  
TYPE(1)  
PULL(2)  
GROUP(3)  
NO.  
W19  
R5  
VP_DIN[0] / UHPI_HD[8] / UPP_D[8] / RMII_CRS_DV / PRU1_R31[29]  
LCD_AC_ENB_CS / GP6[0] / PRU1_R31[28]  
I
I
CP[26]  
CP[31]  
C
C
PRU0_R30[25] / MMCSD1_DAT[0] / UPP_CHB_CLOCK / GP8[15] /  
PRU1_R31[27]  
G1  
G2  
J4  
I
I
I
I
CP[30]  
CP[30]  
CP[30]  
CP[30]  
C
C
C
C
PRU0_R30[24] / MMCSD1_CLK / UPP_CHB_START / GP8[14] /  
PRU1_R31[26]  
PRU0_R30[23] / MMCSD1_CMD / UPP_CHB_ENABLE / GP8[13] /  
PRU1_R31[25]  
PRU0_R30[22] / PRU1_R30[8] / UPP_CHB_WAIT / GP8[12] /  
PRU1_R31[24]  
G3  
EMA_A[15]/MMCSD0_DAT[6]/PRU1_R30[23]/GP5[15]/PRU1_R31[23]  
EMA_A[14]/MMCSD0_DAT[7]/PRU1_R30[22]/GP5[14]/PRU1_R31[22]  
EMA_A[13]/PRU0_R30[21]/PRU1_R30[21]/GP5[13]/PRU1_R31[21]  
EMA_A[12]/PRU1_R30[20]/GP5[12]/PRU1_R31[20]  
C11  
A12  
D11  
D13  
B12  
C12  
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
CP[19]  
CP[19]  
CP[19]  
CP[19]  
CP[19]  
CP[19]  
CP[24]  
CP[25]  
CP[28]  
CP[28]  
CP[28]  
CP[28]  
CP[28]  
CP[28]  
CP[28]  
CP[28]  
CP[31]  
CP[31]  
CP[31]  
CP[30]  
B
B
B
B
B
B
C
C
C
C
C
C
C
C
C
C
C
C
C
C
EMA_A[11]/PRU1_R30[19]/GP5[11]/PRU1_R31[19]  
EMA_A[10]/PRU1_R30[18]/GP5[10]/PRU1_R31[18]  
PRU0_R30[26] / UHPI_HRW / UPP_CHA_WAIT / GP6[8] / PRU1_R31[17] T15  
VP_CLKIN1 / UHPI_HDS1 / PRU1_R30[9] / GP6[6] / PRU1_R31[16]  
VP_DOUT[7] / LCD_D[7] / UPP_XD[15] / GP7[15] / PRU1_R31[15]  
VP_DOUT[6] / LCD_D[6] / UPP_XD[14] / GP7[14] / PRU1_R31[14]  
VP_DOUT[5] / LCD_D[5] / UPP_XD[13] / GP7[13] / PRU1_R31[13]  
VP_DOUT[4] / LCD_D[4] / UPP_XD[12] / GP7[12] / PRU1_R31[12]  
VP_DOUT[3] / LCD_D[3] / UPP_XD[11] / GP7[11] / PRU1_R31[11]  
VP_DOUT[2] / LCD_D[2] / UPP_XD[10] / GP7[10] / PRU1_R31[10]  
VP_DOUT[1] / LCD_D[1] / UPP_XD[9] / GP7[9] / PRU1_R31[9]  
VP_DOUT[0] / LCD_D[0] / UPP_XD[8] / GP7[8] / PRU1_R31[8]  
MMCSD1_DAT[6] / LCD_MCLK / PRU1_R30[6] / GP8[10] / PRU1_R31[7]  
V15  
U2  
U1  
V3  
PRU1 Input  
Signals  
V2  
V1  
W3  
W2  
W1  
F2  
MMCSD1_DAT[5] / LCD_HSYNC / PRU1_R30[5] / GP8[9] / PRU1_R31[6] H4  
MMCSD1_DAT[4] / LCD_VSYNC / PRU1_R30[4] / GP8[8] / PRU1_R31[5] G4  
VP_CLKIN2 / MMCSD1_DAT[3] / PRU1_R30[3] / GP6[4] / PRU1_R31[4]  
H3  
VP_CLKOUT2 / MMCSD1_DAT[2] / PRU1_R30[2] / GP6[3] /  
PRU1_R31[3]  
K3  
I
CP[30]  
C
VP_CLKIN3 / MMCSD1_DAT[1] / PRU1_R30[1] / GP6[2] / PRU1_R31[2]  
VP_CLKOUT3 / PRU1_R30[0] / GP6[1] / PRU1_R31[1]  
J3  
K4  
I
I
I
CP[30]  
CP[30]  
CP[27]  
C
C
C
VP_DIN[8] / UHPI_HD[0] / UPP_D[0] / GP6[5] / PRU1_R31[0]  
P17  
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3.2.9 Enhanced Capture/Auxiliary PWM Modules (eCAP0)  
The eCAP Module pins function as either input captures or auxiliary PWM 32-bit outputs, depending upon  
how the eCAP module is programmed.  
Table 3-9. Enhanced Capture Module (eCAP) Terminal Functions  
SIGNAL  
NAME  
POWER  
TYPE(1)  
eCAP0  
PULL(2)  
DESCRIPTION  
GROUP(3)  
NO.  
enhanced capture 0 input or  
auxiliary PWM 0 output  
AXR0 / ECAP0_APWM0 / GP8[7] / MII_TXD[0] / CLKS0  
AXR8 / CLKS1 / ECAP1_APWM1 / GP0[0] / PRU0_R31[8]  
AXR15 / EPWM0TZ[0] / ECAP2_APWM2 / GP0[7]  
F3  
I/O  
eCAP1  
I/O  
CP[6]  
CP[3]  
CP[1]  
A
A
A
enhanced capture 1 input or  
auxiliary PWM 1 output  
E4  
A4  
eCAP2  
I/O  
enhanced capture 2 input or  
auxiliary PWM 2 output  
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.  
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name  
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured  
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different  
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.  
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using  
the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the  
device is out of reset. During reset, all of the pins associated with these registers are pulled down. If the application requires a pull-up,  
an external pull-up can be used. For more detailed information on pullup/pulldown resistors and situations where external  
pullup/pulldown resistors are required, see the Pullup/Pulldown Resistors section. For electrical specifications on pullup and internal  
pulldown circuits, see the Specifications section.  
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can  
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of  
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power  
supply DVDD3318_C.  
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3.2.10 Enhanced Pulse Width Modulators (eHRPWM)  
Table 3-10. Enhanced Pulse Width Modulator (eHRPWM) Terminal Functions  
SIGNAL  
NAME  
POWER  
TYPE(1)  
PULL(2)  
DESCRIPTION  
GROUP(3)  
NO.  
eHRPWM0  
eHRPWM0 A output  
(with high-resolution)  
SPI0_CLK / EPWM0A / GP1[8] / MII_RXCLK  
D19  
I/O  
CP[7]  
A
SPI0_ENA / EPWM0B / PRU0_R30[6] / MII_RXDV  
AXR15 / EPWM0TZ[0] / ECAP2_APWM2 / GP0[7]  
SPI0_SOMI / EPWMSYNCI / GP8[6] / MII_RXER  
SPI0_SIMO / EPWMSYNCO / GP8[5] / MII_CRS  
C17  
A4  
I/O  
CP[7]  
CP[1]  
CP[7]  
CP[7]  
A
A
A
A
eHRPWM0 B output  
I
eHRPWM0 trip zone input  
eHRPWM0 sync input  
eHRPWM0 sync output  
C16  
C18  
I
I/O  
eHRPWM1  
SPI1_SCS[1] / EPWM1A / PRU0_R30[8] / GP2[15] /  
TM64P2_IN12  
eHRPWM1 A output  
(with high-resolution)  
F18  
E19  
D2  
I/O  
I/O  
I
CP[14]  
CP[14]  
CP[4]  
A
A
A
SPI1_SCS[0] / EPWM1B / PRU0_R30[7] / GP2[14] /  
TM64P3_IN12  
eHRPWM1 B output  
AXR7 / EPWM1TZ[0] / PRU0_R30[17] / GP1[15] /  
PRU0_R31[7]  
eHRPWM1 trip zone input  
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.  
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name  
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured  
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different  
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.  
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using  
the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the  
device is out of reset. During reset, all of the pins associated with these registers are pulled down. If the application requires a pull-up,  
an external pull-up can be used. For more detailed information on pullup/pulldown resistors and situations where external  
pullup/pulldown resistors are required, see the Pullup/Pulldown Resistors section. For electrical specifications on pullup and internal  
pulldown circuits, see the Specifications section.  
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can  
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of  
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power  
supply DVDD3318_C.  
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3.2.11 Boot  
Table 3-11. Boot Mode Selection Terminal Functions(1)  
SIGNAL  
NAME  
POWER  
TYPE(2)  
PULL(3)  
DESCRIPTION  
GROUP(4)  
NO.  
P4  
R3  
R2  
R1  
T3  
VP_DOUT[15] / LCD_D[15] / UPP_XD[7] / GP7[7] / BOOT[7]  
VP_DOUT[14] / LCD_D[14] / UPP_XD[6] / GP7[6] / BOOT[6]  
VP_DOUT[13] / LCD_D[13] / UPP_XD[5] / GP7[5] / BOOT[5]  
VP_DOUT[12] / LCD_D[12] / UPP_XD[4] / GP7[4] / BOOT[4]  
VP_DOUT[11] / LCD_D[11] / UPP_XD[3] / GP7[3] / BOOT[3]  
VP_DOUT[10] / LCD_D[10] / UPP_XD[2] / GP7[2] / BOOT[2]  
VP_DOUT[9] / LCD_D[9] / UPP_XD[1] / GP7[1] / BOOT[1]  
VP_DOUT[8] / LCD_D[8] / UPP_XD[0] / GP7[0] / BOOT[0]  
I
I
I
I
I
I
I
I
CP[29]  
CP[29]  
CP[29]  
CP[29]  
CP[29]  
CP[29]  
CP[29]  
CP[29]  
C
C
C
C
C
C
C
C
Boot Mode Selection Pins  
T2  
T1  
U3  
(1) Boot decoding is defined in the bootloader application report.  
(2) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.  
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name  
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured  
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different  
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.  
(3) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using  
the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the  
device is out of reset. During reset, all of the pins associated with these registers are pulled down. If the application requires a pull-up,  
an external pull-up can be used. For more detailed information on pullup/pulldown resistors and situations where external  
pullup/pulldown resistors are required, see the Pullup/Pulldown Resistors section. For electrical specifications on pullup and internal  
pulldown circuits, see the Specifications section.  
(4) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can  
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of  
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power  
supply DVDD3318_C.  
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3.2.12 Universal Asynchronous Receiver/Transmitters (UART0, UART1, UART2)  
Table 3-12. Universal Asynchronous Receiver/Transmitter (UART) Terminal Functions  
SIGNAL  
NAME  
POWER  
TYPE(1)  
PULL(2)  
DESCRIPTION  
GROUP(3)  
NO.  
UART0  
SPI0_SCS[5] / UART0_RXD / GP8[4] / MII_RXD[3]  
SPI0_SCS[4] / UART0_TXD / GP8[3] / MII_RXD[2]  
C19  
D18  
I
CP[8]  
CP[8]  
A
A
UART0 receive data  
UART0 transmit data  
O
SPI0_SCS[2] / UART0_RTS / GP8[1] / MII_RXD[0] /  
SATA_CP_DET  
D16  
E17  
O
I
CP[9]  
CP[9]  
A
A
UART0 ready-to-send output  
UART0 clear-to-send input  
SPI0_SCS[3] / UART0_CTS / GP8[2] / MII_RXD[1] /  
SATA_MP_SWITCH  
UART1  
SPI1_SCS[3] / UART1_RXD / SATA_LED / GP1[1]  
SPI1_SCS[2] / UART1_TXD / SATA_CP_POD / GP1[0]  
E18  
F19  
I
CP[13]  
CP[13]  
A
A
UART1 receive data  
UART1 transmit data  
O
AHCLKR / PRU0_R30[18] / UART1_RTS /GP0[11] /  
PRU0_R31[18]  
A2  
A3  
O
I
CP[0]  
CP[0]  
A
A
UART1 ready-to-send output  
UART1 clear-to-send input  
AHCLKX / USB_REFCLKIN / UART1_CTS / GP0[10] /  
PRU0_R31[17]  
UART2  
SPI1_SCS[5] / UART2_RXD / I2C1_SCL /GP1[3]  
SPI1_SCS[4] / UART2_TXD / I2C1_SDA /GP1[2]  
F17  
F16  
I
CP[12]  
CP[12]  
A
A
UART2 receive data  
UART2 transmit data  
O
AMUTE / PRU0_R30[16] / UART2_RTS / GP0[9] /  
PRU0_R31[16]  
D5  
F4  
O
I
CP[0]  
CP[0]  
A
A
UART2 ready-to-send output  
UART2 clear-to-send input  
RTC_ALARM / UART2_CTS / GP0[8] / DEEPSLEEP  
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.  
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name  
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured  
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different  
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.  
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using  
the PUPDENA and PUPDSEL registers in the System Module.The pull-up and pull-down control of these pins is not active until the  
device is out of reset. During reset, all of the pins associated with these registers are pulled down. If the application requires a pull-up,  
an external pull-up can be used. For more detailed information on pullup/pulldown resistors and situations where external  
pullup/pulldown resistors are required, see the Pullup/Pulldown Resistors section. For electrical specifications on pullup and internal  
pulldown circuits, see the Specifications section.  
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can  
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of  
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power  
supply DVDD3318_C.  
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3.2.13 Inter-Integrated Circuit Modules (I2C0, I2C1)  
Table 3-13. Inter-Integrated Circuit (I2C) Terminal Functions  
SIGNAL  
NAME  
POWER  
TYPE(1)  
PULL(2)  
DESCRIPTION  
GROUP(3)  
NO.  
I2C0  
SPI1_SCS[6] / I2C0_SDA / TM64P3_OUT12 / GP1[4]  
SPI1_SCS[7] / I2C0_SCL / TM64P2_OUT12 / GP1[5]  
G18  
G16  
I/O  
I/O  
CP[11]  
CP[11]  
A
A
I2C0 serial data  
I2C0 serial clock  
I2C1  
SPI1_SCS[4] / UART2_TXD / I2C1_SDA / GP1[2]  
SPI1_SCS[5] / UART2_RXD / I2C1_SCL / GP1[3]  
F16  
F17  
I/O  
I/O  
CP[12]  
CP[12]  
A
A
I2C1 serial data  
I2C1 serial clock  
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.  
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name  
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured  
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different  
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.  
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using  
the PUPDENA and PUPDSEL registers in the System Module.The pull-up and pull-down control of these pins is not active until the  
device is out of reset. During reset, all of the pins associated with these registers are pulled down. If the application requires a pull-up,  
an external pull-up can be used. For more detailed information on pullup/pulldown resistors and situations where external  
pullup/pulldown resistors are required, see the Pullup/Pulldown Resistors section. For electrical specifications on pullup and internal  
pulldown circuits, see the Specifications section.  
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can  
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of  
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power  
supply DVDD3318_C.  
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3.2.14 Timers  
Table 3-14. Timers Terminal Functions  
SIGNAL  
NAME  
POWER  
TYPE(1)  
PULL(2)  
DESCRIPTION  
GROUP(3)  
NO.  
TIMER0  
SPI0_SCS[1] / TM64P0_OUT12 / GP1[7] / MDCLK /TM64P0_IN12  
E16  
E16  
I
CP[10]  
CP[10]  
A
A
Timer0 lower input  
Timer0 lower  
output  
SPI0_SCS[1] / TM64P0_OUT12 / GP1[7] / MDCLK / TM64P0_IN12  
O
TIMER1 (Watchdog)  
SPI0_SCS[0] / TM64P1_OUT12 / GP1[6] / MDIO / TM64P1_IN12  
D17  
I
CP[10]  
CP[10]  
A
A
Timer1 lower input  
Timer1 lower  
output  
SPI0_SCS[0] / TM64P1_OUT12 / GP1[6] / MDIO / TM64P1_IN12  
D17  
O
TIMER2  
SPI1_SCS[1] / EPWM1A / PRU0_R30[8] / GP2[15] / TM64P2_IN12  
F18  
G16  
I
CP[14]  
CP[11]  
A
A
Timer2 lower input  
Timer2 lower  
output  
SPI1_SCS[7] / I2C0_SCL / TM64P2_OUT12 / GP1[5]  
O
TIMER3  
SPI1_SCS[0] / EPWM1B / PRU0_R30[7] / GP2[14] / TM64P3_IN12  
E19  
G18  
I
CP[14]  
CP[11]  
A
A
Timer3 lower input  
Timer3 lower  
output  
SPI1_SCS[6] / I2C0_SDA / TM64P3_OUT12 / GP1[4]  
O
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.  
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name  
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured  
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different  
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.  
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using  
the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the  
device is out of reset. During reset, all of the pins associated with these registers are pulled down. If the application requires a pull-up,  
an external pull-up can be used. For more detailed information on pullup/pulldown resistors and situations where external  
pullup/pulldown resistors are required, see the Pullup/Pulldown Resistors section. For electrical specifications on pullup and internal  
pulldown circuits, see the Specifications section.  
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can  
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of  
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power  
supply DVDD3318_C.  
30  
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3.2.15 Multichannel Audio Serial Ports (McASP)  
Table 3-15. Multichannel Audio Serial Ports Terminal Functions  
SIGNAL  
NAME  
POWER  
TYPE(1)  
McASP0  
PULL(2)  
DESCRIPTION  
GROUP(3)  
NO.  
AXR15 / EPWM0TZ[0] / ECAP2_APWM2 / GP0[7]  
AXR14 / CLKR1 / GP0[6]  
A4  
B4  
B3  
C4  
C5  
D4  
C3  
E4  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
CP[1]  
CP[2]  
CP[2]  
CP[2]  
CP[2]  
CP[2]  
CP[2]  
CP[3]  
A
A
A
A
A
A
A
A
AXR13 / CLKX1 / GP0[5]  
AXR12 / FSR1 / GP0[4]  
AXR11 / FSX1 / GP0[3]  
AXR10 / DR1 / GP0[2]  
AXR9 / DX1 / GP0[1]  
AXR8 / CLKS1 / ECAP1_APWM1 / GP0[0] / PRU0_R31[8]  
McASP0 serial data  
AXR7 / EPWM1TZ[0] / PRU0_R30[17] / GP1[15] /  
PRU0_R31[7]  
D2  
I/O  
CP[4]  
A
AXR6 / CLKR0 / GP1[14] / MII_TXEN / PRU0_R31[6]  
AXR5 / CLKX0 / GP1[13] / MII_TXCLK  
AXR4 / FSR0 / GP1[12] / MII_COL  
C1  
D3  
D1  
E3  
E2  
E1  
F3  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
CP[5]  
CP[5]  
CP[5]  
CP[5]  
CP[5]  
CP[5]  
CP[6]  
A
A
A
A
A
A
A
AXR3 / FSX0 / GP1[11] / MII_TXD[3]  
AXR2 / DR0 / GP1[10] / MII_TXD[2]  
AXR1 / DX0 / GP1[9] / MII_TXD[1]  
AXR0 / ECAP0_APWM0 / GP8[7]/ MII_TXD[0] / CLKS0  
AHCLKX / USB_REFCLKIN / UART1_CTS / GP0[10] /  
PRU0_R31[17]  
A3  
I/O  
CP[0]  
A
McASP0 transmit master clock  
ACLKX / PRU0_R30[19] / GP0[14] / PRU0_R31[21]  
AFSX / GP0[12] / PRU0_R31[19]  
B1  
B2  
I/O  
I/O  
CP[0]  
CP[0]  
A
A
McASP0 transmit bit clock  
McASP0 transmit frame sync  
AHCLKR / PRU0_R30[18] / UART1_RTS / GP0[11] /  
PRU0_R31[18]  
A2  
I/O  
CP[0]  
A
McASP0 receive master clock  
ACLKR / PRU0_R30[20] / GP0[15] / PRU0_R31[22]  
AFSR / GP0[13] / PRU0_R31[20]  
A1  
C2  
I/O  
I/O  
CP[0]  
CP[0]  
A
A
McASP0 receive bit clock  
McASP0 receive frame sync  
AMUTE / PRU0_R30[16] / UART2_RTS / GP0[9] /  
PRU0_R31[16]  
D5  
I/O  
CP[0]  
A
McASP0 mute output  
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.  
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name  
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured  
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different  
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.  
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using  
the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the  
device is out of reset. During reset, all of the pins associated with these registers are pulled down. If the application requires a pull-up,  
an external pull-up can be used. For more detailed information on pullup/pulldown resistors and situations where external  
pullup/pulldown resistors are required, see the Pullup/Pulldown Resistors section. For electrical specifications on pullup and internal  
pulldown circuits, see the Specifications section.  
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can  
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of  
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power  
supply DVDD3318_C.  
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3.2.16 Multichannel Buffered Serial Ports (McBSP)  
Table 3-16. Multichannel Buffered Serial Ports (McBSPs) Terminal Functions  
SIGNAL  
NAME  
POWER  
TYPE(1)  
PULL(2)  
McBSP0  
DESCRIPTION  
GROUP(3)  
NO.  
AXR0 / ECAP0_APWM0 / GP8[7] / MII_TXD[0]  
/ CLKS0  
F3  
C1  
I
CP[6]  
CP[5]  
A
A
McBSP0 sample rate generator clock input  
McBSP0 receive clock  
AXR6 / CLKR0 / GP1[14] / MII_TXEN /  
PRU0_R31[6]  
I/O  
AXR4 / FSR0 / GP1[12] / MII_COL  
AXR2 / DR0 / GP1[10] / MII_TXD[2]  
AXR5 / CLKX0 / GP1[13] / MII_TXCLK  
AXR3 / FSX0 / GP1[11] / MII_TXD[3]  
AXR1 / DX0 / GP1[9] / MII_TXD[1]  
D1  
E2  
D3  
E3  
E1  
I/O  
I
CP[5]  
CP[5]  
A
A
A
A
A
McBSP0 receive frame sync  
McBSP0 receive data  
I/O  
I/O  
O
CP[5]  
McBSP0 transmit clock  
McBSP0 transmit frame sync  
McBSP0 transmit data  
CP[5]  
CP[5]  
McBSP1  
AXR8 / CLKS1 / ECAP1_APWM1 / GP0[0] /  
PRU0_R31[8]  
E4  
I
CP[3]  
A
McBSP1 sample rate generator clock input  
AXR14 / CLKR1 / GP0[6]  
AXR12 / FSR1 / GP0[4]  
AXR10 / DR1 / GP0[2]  
AXR13 / CLKX1 / GP0[5]  
AXR11 / FSX1 / GP0[3]  
AXR9 / DX1 / GP0[1]  
B4  
C4  
D4  
B3  
C5  
C3  
I/O  
I/O  
I
CP[2]  
CP[2]  
CP[2]  
CP[2]  
CP[2]  
CP[2]  
A
A
A
A
A
A
McBSP1 receive clock  
McBSP1 receive frame sync  
McBSP1 receive data  
I/O  
I/O  
O
McBSP1 transmit clock  
McBSP1 transmit frame sync  
McBSP1 transmit data  
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.  
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name  
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured  
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different  
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.  
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using  
the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the  
device is out of reset. During reset, all of the pins associated with these registers are pulled down. If the application requires a pull-up,  
an external pull-up can be used. For more detailed information on pullup/pulldown resistors and situations where external  
pullup/pulldown resistors are required, see the Pullup/Pulldown Resistors section. For electrical specifications on pullup and internal  
pulldown circuits, see the Specifications section.  
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can  
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of  
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power  
supply DVDD3318_C.  
32  
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3.2.17 Universal Serial Bus Modules (USB0, USB1)  
Table 3-17. Universal Serial Bus (USB) Terminal Functions  
SIGNAL  
NAME  
POWER  
TYPE(1)  
PULL(2)  
DESCRIPTION  
GROUP(3)  
NO.  
USB0 2.0 OTG (USB0)  
USB0_DM  
M18  
M19  
N18  
A
A
IPD  
IPD  
—
—
—
—
USB0 PHY data minus  
USB0_DP  
USB0 PHY data plus  
USB0_VDDA33  
PWR  
USB0 PHY 3.3-V supply  
USB0 PHY identification  
(mini-A or mini-B plug)  
USB0_ID  
P16  
A
—
—
USB0_VBUS  
N19  
K18  
A
0
—
—
B
USB0 bus voltage  
USB0_DRVVBUS  
IPD  
USB0 controller VBUS control output.  
AHCLKX / USB_REFCLKIN / UART1_CTS /  
GP0[10] / PRU0_R31[17]  
A3  
I
CP[0]  
—
A
USB_REFCLKIN. Optional clock input  
USB0 PHY 1.8-V supply input  
USB0_VDDA18  
N14  
PWR  
—
USB0 PHY 1.2-V LDO output for bypass cap  
For proper device operation, this pin must  
always be connected via a 0.22-μF capacitor  
to VSS (GND), even if USB0 is not being  
used.  
USB0_VDDA12  
N17  
M12  
A
—
—
—
—
USB0 and USB1 core logic 1.2-V supply  
input  
USB_CVDD  
PWR  
USB1 1.1 OHCI (USB1)  
USB1_DM  
USB1_DP  
P18  
P19  
A
A
—
—
—
—
USB1 PHY data minus  
USB1 PHY data plus  
AHCLKX / USB_REFCLKIN / UART1_CTS /  
GP0[10] / PRU0_R31[17]  
A3  
I
CP[0]  
A
USB_REFCLKIN. Optional clock input  
USB1_VDDA33  
USB1_VDDA18  
P15  
P14  
PWR  
PWR  
—
—
—
—
USB1 PHY 3.3-V supply  
USB1 PHY 1.8-V supply  
USB0 and USB1 core logic 1.2-V supply  
input  
USB_CVDD  
M12  
PWR  
—
—
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.  
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name  
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured  
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different  
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.  
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using  
the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the  
device is out of reset. During reset, all of the pins associated with these registers are pulled down. If the application requires a pull-up,  
an external pull-up can be used. For more detailed information on pullup/pulldown resistors and situations where external  
pullup/pulldown resistors are required, see the Pullup/Pulldown Resistors section. For electrical specifications on pullup and internal  
pulldown circuits, see the Specifications section.  
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can  
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of  
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power  
supply DVDD3318_C.  
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3.2.18 Ethernet Media Access Controller (EMAC)  
Table 3-18. Ethernet Media Access Controller (EMAC) Terminal Functions  
SIGNAL  
NAME  
POWER  
TYPE(1)  
PULL(2)  
DESCRIPTION  
GROUP(3)  
NO.  
MII  
O
I
AXR6 / CLKR0 / GP1[14] / MII_TXEN / PRU0_R31[6]  
AXR5 / CLKX0 / GP1[13] / MII_TXCLK  
AXR4 / FSR0 / GP1[12] / MII_COL  
C1  
D3  
D1  
E3  
E2  
E1  
CP[5]  
CP[5]  
CP[5]  
CP[5]  
CP[5]  
CP[5]  
A
A
A
A
A
A
EMAC MII Transmit enable output  
EMAC MII Transmit clock input  
EMAC MII Collision detect input  
I
AXR3 / FSX0 / GP1[11] / MII_TXD[3]  
AXR2 / DR0 / GP1[10] / MII_TXD[2]  
AXR1 / DX0 / GP1[9] / MII_TXD[1]  
O
O
O
EMAC MII transmit data  
AXR0 / ECAP0_APWM0 / GP8[7] / MII_TXD[0] /  
CLKS0  
F3  
O
CP[6]  
A
SPI0_SOMI / EPWMSYNCI / GP8[6] / MII_RXER  
SPI0_SIMO / EPWMSYNCO / GP8[5] / MII_CRS  
SPI0_CLK / EPWM0A / GP1[8] / MII_RXCLK  
SPI0_ENA / EPWM0B / PRU0_R30[6] / MII_RXDV  
SPI0_SCS[5] /UART0_RXD / GP8[4] / MII_RXD[3]  
SPI0_SCS[4] /UART0_TXD / GP8[3] / MII_RXD[2]  
C16  
C18  
D19  
C17  
C19  
D18  
I
I
I
I
I
I
CP[7]  
CP[7]  
CP[7]  
CP[7]  
CP[8]  
CP[8]  
A
A
A
A
A
A
EMAC MII receive error input  
EMAC MII carrier sense input  
EMAC MII receive clock input  
EMAC MII receive data valid input  
SPI0_SCS[3] / UART0_CTS / GP8[2] / MII_RXD[1] /  
SATA_MP_SWITCH  
EMAC MII receive data  
E17  
D16  
I
I
CP[9]  
CP[9]  
A
A
SPI0_SCS[2] / UART0_RTS / GP8[1] / MII_RXD[0] /  
SATA_CP_DET  
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.  
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name  
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured  
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different  
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.  
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using  
the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the  
device is out of reset. During reset, all of the pins associated with these registers are pulled down. If the application requires a pull-up,  
an external pull-up can be used. For more detailed information on pullup/pulldown resistors and situations where external  
pullup/pulldown resistors are required, see the Pullup/Pulldown Resistors section. For electrical specifications on pullup and internal  
pulldown circuits, see the Specifications section.  
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can  
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of  
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power  
supply DVDD3318_C.  
34  
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Table 3-18. Ethernet Media Access Controller (EMAC) Terminal Functions (continued)  
SIGNAL  
NAME  
POWER  
TYPE(1)  
PULL(2)  
DESCRIPTION  
GROUP(3)  
NO.  
RMII  
VP_DIN[1] / UHPI_HD[9] / UPP_D[9] /  
RMII_MHZ_50_CLK / PRU0_R31[23]  
W18  
W17  
V17  
W16  
W19  
R14  
V16  
U18  
I/O  
CP[26]  
CP[26]  
CP[26]  
CP[26]  
CP[26]  
CP[26]  
CP[26]  
CP[26]  
C
C
C
C
C
C
C
C
EMAC 50-MHz clock input or output  
EMAC RMII receiver error  
VP_DIN[2] / UHPI_HD[10] / UPP_D[10] / RMII_RXER /  
PRU0_R31[24]  
I
I
VP_DIN[3] / UHPI_HD[11] / UPP_D[11] / RMII_RXD[0]  
/ PRU0_R31[25]  
EMAC RMII receive data  
VP_DIN[4] / UHPI_HD[12] / UPP_D[12] / RMII_RXD[1]  
/PRU0_R31[26]  
I
VP_DIN[0] / UHPI_HD[8] / UPP_D[8] / RMII_CRS_DV /  
PRU1_R31[29]  
I
EMAC RMII carrier sense data valid  
EMAC RMII transmit enable  
VP_DIN[5] / UHPI_HD[13] / UPP_D[13] / RMII_TXEN /  
PRU0_R31[27]  
O
O
VP_DIN[6] / UHPI_HD[14] / UPP_D[14] / RMII_TXD[0]  
/ PRU0_R31[28]  
EMAC RMII transmit data  
VP_DIN[7] / UHPI_HD[15] / UPP_D[15] / RMII_TXD[1]  
/ PRU0_R31[29]  
O
MDIO  
I/O  
SPI0_SCS[0] / TM64P1_OUT12 / GP1[6] / MDIO /  
TM64P1_IN12  
D17  
E16  
CP[10]  
CP[10]  
A
A
MDIO serial data  
MDIO clock  
SPI0_SCS[1] / TM64P0_OUT12 / GP1[7] / MDCLK /  
TM64P0_IN12  
O
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3.2.19 Multimedia Card/Secure Digital (MMC/SD)  
Table 3-19. Multimedia Card/Secure Digital (MMC/SD) Terminal Functions  
SIGNAL  
NAME  
POWER  
TYPE(1)  
PULL(2)  
DESCRIPTION  
GROUP(3)  
NO.  
MMCSD0  
MMCSD0_CLK / PRU1_R30[31] /GP4[7]  
E9  
O
CP[18]  
CP[18]  
B
B
MMCSD0 Clock  
EMA_A[22] / MMCSD0_CMD / PRU1_R30[30] / GP4[6]  
A10  
I/O  
MMCSD0 Command  
EMA_A[14] / MMCSD0_DAT[7] / PRU1_R30[22] / GP5[14] /  
PRU1_R31[22]  
A12  
C11  
I/O  
I/O  
CP[19]  
CP[19]  
B
B
EMA_A[15] / MMCSD0_DAT[6] / PRU1_R30[23] / GP5[15] /  
PRU1_R31[23]  
EMA_A[16] / MMCSD0_DAT[5] / PRU1_R30[24] / GP4[0]  
EMA_A[17] / MMCSD0_DAT[4] / PRU1_R30[25] / GP4[1]  
EMA_A[18] / MMCSD0_DAT[3] / PRU1_R30[26] / GP4[2]  
EMA_A[19] / MMCSD0_DAT[2] / PRU1_R30[27] / GP4[3]  
EMA_A[20] / MMCSD0_DAT[1] / PRU1_R30[28] / GP4[4]  
EMA_A[21] / MMCSD0_DAT[0] / PRU1_R30[29] / GP4[5]  
E12  
B11  
E11  
C10  
A11  
B10  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
CP[18]  
CP[18]  
CP[18]  
CP[18]  
CP[18]  
CP[18]  
B
B
B
B
B
B
MMC/SD0 data  
MMCSD1  
PRU0_R30[24] / MMCSD1_CLK / UPP_CHB_START / GP8[14] /  
PRU1_R31[26]/  
G2  
O
CP[30]  
C
MMCSD1 Clock  
PRU0_R30[23] / MMCSD1_CMD / UPP_CHB_ENABLE / GP8[13] /  
PRU1_R31[25]  
J4  
F1  
F2  
I/O  
I/O  
I/O  
CP[30]  
CP[31]  
CP[31]  
C
C
C
MMCSD1 Command  
MMCSD1_DAT[7] / LCD_PCLK / PRU1_R30[7] / GP8[11]  
MMCSD1_DAT[6] / LCD_MCLK / PRU1_R30[6] / GP8[10] /  
PRU1_R31[7]  
MMCSD1_DAT[5] / LCD_HSYNC / PRU1_R30[5] / GP8[9] /  
PRU1_R31[6]  
H4  
G4  
H3  
K3  
J3  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
CP[31]  
CP[31]  
CP[30]  
CP[30]  
CP[30]  
CP[30]  
C
C
C
C
C
C
MMCSD1_DAT[4] / LCD_VSYNC / PRU1_R30[4] / GP8[8] /  
PRU1_R31[5]  
MMC/SD1 data  
VP_CLKIN2 / MMCSD1_DAT[3] / PRU1_R30[3] / GP6[4] /  
PRU1_R31[4]  
VP_CLKOUT2 / MMCSD1_DAT[2] / PRU1_R30[2] / GP6[3] /  
PRU1_R31[3]  
VP_CLKIN3 / MMCSD1_DAT[1]/ PRU1_R30[1] / GP6[2] /  
PRU1_R31[2]  
PRU0_R30[25] / MMCSD1_DAT[0] / UPP_CHB_CLOCK / GP8[15]/  
PRU1_R31[27]  
G1  
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.  
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name  
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured  
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different  
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.  
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using  
the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the  
device is out of reset. During reset, all of the pins associated with these registers are pulled down. If the application requires a pull-up,  
an external pull-up can be used. For more detailed information on pullup/pulldown resistors and situations where external  
pullup/pulldown resistors are required, see the Pullup/Pulldown Resistors section. For electrical specifications on pullup and internal  
pulldown circuits, see the Specifications section.  
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can  
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of  
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power  
supply DVDD3318_C.  
36  
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3.2.20 Liquid Crystal Display Controller (LCDC)  
Table 3-20. Liquid Crystal Display Controller (LCDC) Terminal Functions  
SIGNAL  
POWER  
TYPE(1)  
PULL(2)  
DESCRIPTION  
GROUP(3)  
NAME  
NO.  
P4  
R3  
R2  
R1  
T3  
VP_DOUT[15] / LCD_D[15] / UPP_XD[7] / GP7[7] / BOOT[7]  
VP_DOUT[14] / LCD_D[14] / UPP_XD[6] / GP7[6] / BOOT[6]  
VP_DOUT[13] / LCD_D[13] / UPP_XD[5] / GP7[5] / BOOT[5]  
VP_DOUT[12] / LCD_D[12] / UPP_XD[4] / GP7[4] / BOOT[4]  
VP_DOUT[11] / LCD_D[11] / UPP_XD[3] / GP7[3] / BOOT[3]  
VP_DOUT[10] / LCD_D[10] / UPP_XD[2] / GP7[2] / BOOT[2]  
VP_DOUT[9] / LCD_D[9] / UPP_XD[1] / GP7[1] / BOOT[1]  
VP_DOUT[8] / LCD_D[8] / UPP_XD[0] / GP7[0] / BOOT[0]  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
CP[29]  
CP[29]  
CP[29]  
CP[29]  
CP[29]  
CP[29]  
CP[29]  
CP[29]  
C
C
C
C
C
C
C
C
T2  
T1  
U3  
VP_DOUT[7] / LCD_D[7] / UPP_XD[15] / GP7[15] /  
PRU1_R31[15]  
U2  
U1  
V3  
V2  
V1  
W3  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
CP[28]  
CP[28]  
CP[28]  
CP[28]  
CP[28]  
CP[28]  
C
C
C
C
C
C
LCD data bus  
VP_DOUT[6] / LCD_D[6] / UPP_XD[14] / GP7[14] /  
PRU1_R31[14]  
VP_DOUT[5] / LCD_D[5] / UPP_XD[13] / GP7[13] /  
PRU1_R31[13]  
VP_DOUT[4] / LCD_D[4] / UPP_XD[12] / GP7[12] /  
PRU1_R31[12]  
VP_DOUT[3] / LCD_D[3] / UPP_XD[11] / GP7[11] /  
PRU1_R31[11]  
VP_DOUT[2] / LCD_D[2] / UPP_XD[10] / GP7[10] /  
PRU1_R31[10]  
VP_DOUT[1] / LCD_D[1] / UPP_XD[9] / GP7[9] / PRU1_R31[9]  
VP_DOUT[0] / LCD_D[0] / UPP_XD[8] / GP7[8] / PRU1_R31[8]  
MMCSD1_DAT[7] / LCD_PCLK / PRU1_R30[7] / GP8[11]  
W2  
W1  
F1  
I/O  
I/O  
O
CP[28]  
CP[28]  
CP[31]  
C
C
C
LCD pixel clock  
MMCSD1_DAT[5] / LCD_HSYNC / PRU1_R30[5] / GP8[9] /  
PRU1_R31[6]  
H4  
G4  
R5  
F2  
O
O
O
O
CP[31]  
CP[31]  
CP[31]  
CP[31]  
C
C
C
C
LCD horizontal sync  
MMCSD1_DAT[4] / LCD_VSYNC / PRU1_R30[4] / GP8[8] /  
PRU1_R31[5]  
LCD vertical sync  
LCD AC bias enable chip  
select  
LCD_AC_ENB_CS / GP6[0] / PRU1_R31[28]  
MMCSD1_DAT[6] / LCD_MCLK / PRU1_R30[6] / GP8[10] /  
PRU1_R31[7]  
LCD memory clock  
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.  
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name  
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured  
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different  
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.  
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using  
the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the  
device is out of reset. During reset, all of the pins associated with these registers are pulled down. If the application requires a pull-up,  
an external pull-up can be used. For more detailed information on pullup/pulldown resistors and situations where external  
pullup/pulldown resistors are required, see the Pullup/Pulldown Resistors section. For electrical specifications on pullup and internal  
pulldown circuits, see the Specifications section.  
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can  
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of  
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power  
supply DVDD3318_C.  
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3.2.21 Serial ATA Controller (SATA)  
Table 3-21. Serial ATA Controller (SATA) Terminal Functions  
SIGNAL  
NAME  
POWER  
TYPE(1)  
PULL(2)  
DESCRIPTION  
GROUP(3)  
NO.  
L1  
SATA_RXP  
I
I
—
—
—
—
—
—
—
—
—
—
—
—
SATA receive data (positive)  
SATA receive data (negative)  
SATA transmit data (positive)  
SATA transmit data (negative)  
SATA_RXN  
L2  
SATA_TXP  
J1  
O
O
I
SATA_TXN  
J2  
SATA_REFCLKP  
SATA_REFCLKN  
N2  
N1  
SATA PHY reference clock (positive)  
SATA PHY reference clock (negative)  
I
SPI0_SCS[3] / UART0_CTS / GP8[2] /  
MII_RXD[1] / SATA_MP_SWITCH  
E17  
D16  
F19  
E18  
I
CP[9]  
CP[9]  
A
A
A
A
SATA mechanical presence switch input  
SATA cold presence detect input  
SATA cold presence power-on output  
SATA LED control output  
SPI0_SCS[2] / UART0_RTS / GP8[1] /  
MII_RXD[0] / SATA_CP_DET  
I
SPI1_SCS[2] / UART1_TXD /  
SATA_CP_POD / GP1[0]  
O
O
CP[13]  
CP[13]  
SPI1_SCS[3] / UART1_RXD / SATA_LED /  
GP1[1]  
SATA PHY PLL regulator output. Requires an  
external 0.1uF filter capacitor.  
SATA_REG  
N3  
P3  
A
—
—
—
—
SATA_VDDR  
PWR  
SATA PHY 1.8V internal regulator supply  
M2,  
P1,  
P2,  
N4  
SATA_VDD  
SATA_VSS  
PWR  
GND  
—
—
SATA PHY 1.2V logic supply  
H1,  
H2,  
K1,  
K2,  
L3,  
M1  
—
—
SATA PHY ground reference  
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.  
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name  
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured  
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different  
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.  
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using  
the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the  
device is out of reset. During reset, all of the pins associated with these registers are pulled down. If the application requires a pull-up,  
an external pull-up can be used. For more detailed information on pullup/pulldown resistors and situations where external  
pullup/pulldown resistors are required, see the Pullup/Pulldown Resistors section. For electrical specifications on pullup and internal  
pulldown circuits, see the Specifications section.  
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can  
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of  
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power  
supply DVDD3318_C.  
38  
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3.2.22 Universal Host-Port Interface (UHPI)  
Table 3-22. Universal Host-Port Interface (UHPI) Terminal Functions  
SIGNAL  
NAME  
POWER  
TYPE(1)  
PULL(2)  
DESCRIPTION  
GROUP(3)  
NO.  
VP_DIN[7] / UHPI_HD[15] / UPP_D[15] / RMII_TXD[1] /  
PRU0_R31[29]  
U18  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
CP[26]  
CP[26]  
CP[26]  
CP[26]  
CP[26]  
CP[26]  
CP[26]  
CP[26]  
CP[27]  
CP[27]  
CP[27]  
CP[27]  
CP[27]  
CP[27]  
C
C
C
C
C
C
C
C
C
C
C
C
C
C
VP_DIN[6] / UHPI_HD[14] / UPP_D[14] / RMII_TXD[0] /  
PRU0_R31[28]  
V16  
R14  
W16  
V17  
W17  
W18  
W19  
V18  
V19  
U19  
T16  
R18  
R19  
VP_DIN[5] / UHPI_HD[13] / UPP_D[13] / RMII_TXEN /  
PRU0_R31[27]  
VP_DIN[4] / UHPI_HD[12] / UPP_D[12] / RMII_RXD[1] /  
PRU0_R31[26]  
VP_DIN[3] / UHPI_HD[11] / UPP_D[11] / RMII_RXD[0] /  
PRU0_R31[25]  
VP_DIN[2] / UHPI_HD[10] / UPP_D[10] / RMII_RXER /  
PRU0_R31[24]  
VP_DIN[1] / UHPI_HD[9] / UPP_D[9] / RMII_MHZ_50_CLK /  
PRU0_R31[23]  
VP_DIN[0] / UHPI_HD[8] / UPP_D[8] / RMII_CRS_DV /  
PRU1_R31[29]  
UHPI data bus  
VP_DIN[15]_VSYNC / UHPI_HD[7] / UPP_D[7] / PRU0_R30[15] /  
PRU0_R31[15]  
VP_DIN[14]_HSYNC / UHPI_HD[6] / UPP_D[6] / PRU0_R30[14] /  
PRU0_R31[14]  
VP_DIN[13]_FIELD / UHPI_HD[5] / UPP_D[5] / PRU0_R30[13] /  
PRU0_R31[13]  
VP_DIN[12] / UHPI_HD[4] / UPP_D[4] / PRU0_R30[12] /  
PRU0_R31[12]  
VP_DIN[11] / UHPI_HD[3] / UPP_D[3] / PRU0_R30[11] /  
PRU0_R31[11]  
VP_DIN[10] / UHPI_HD[2] / UPP_D[2] / PRU0_R30[10] /  
PRU0_R31[10]  
VP_DIN[9] / UHPI_HD[1] / UPP_D[1] / PRU0_R30[9] / PRU0_R31[9] R15  
I/O  
CP[27]  
CP[27]  
CP[24]  
CP[24]  
C
C
C
C
VP_DIN[8] / UHPI_HD[0] / UPP_D[0] / GP6[5] / PRU1_R31[0]  
PRU0_R30[29] / UHPI_HCNTL0 / UPP_CHA_CLOCK / GP6[11]  
PRU0_R30[28] / UHPI_HCNTL1 / UPP_CHA_START / GP6[10]  
P17  
U17  
W15  
I/O  
I
I
UHPI access control  
UHPI half-word  
identification control  
PRU0_R30[27] / UHPI_HHWIL / UPP_CHA_ENABLE / GP6[9]  
U16  
T15  
I
I
CP[24]  
CP[24]  
C
C
PRU0_R30[26] / UHPI_HRW / UPP_CHA_WAIT /  
GP6[8]/PRU1_R31[17]  
UHPI read/write  
UHPI chip select  
VP_CLKIN0 / UHPI_HCS / PRU1_R30[10] / GP6[7] / UPP_2xTXCLK W14  
I
I
I
CP[25]  
CP[25]  
CP[22]  
C
C
C
VP_CLKIN1 / UHPI_HDS1 / PRU1_R30[9] / GP6[6] / PRU1_R31[16]  
CLKOUT / UHPI_HDS2 / PRU1_R30[13] / GP6[14]  
V15  
T18  
UHPI data strobe  
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.  
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name  
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured  
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different  
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.  
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using  
the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the  
device is out of reset. During reset, all of the pins associated with these registers are pulled down. If the application requires a pull-up,  
an external pull-up can be used. For more detailed information on pullup/pulldown resistors and situations where external  
pullup/pulldown resistors are required, see the Pullup/Pulldown Resistors section. For electrical specifications on pullup and internal  
pulldown circuits, see the Specifications section.  
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can  
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of  
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power  
supply DVDD3318_C.  
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Terminal Configuration and Functions  
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Table 3-22. Universal Host-Port Interface (UHPI) Terminal Functions (continued)  
SIGNAL  
NAME  
POWER  
TYPE(1)  
PULL(2)  
DESCRIPTION  
GROUP(3)  
NO.  
R16  
R17  
T17  
PRU0_R30[30] / UHPI_HINT / PRU1_R30[11] / GP6[12]  
PRU0_R30[31] / UHPI_HRDY / PRU1_R30[12] /GP6[13]  
RESETOUT / UHPI_HAS / PRU1_R30[14] / GP6[15]  
O
O
I
CP[23]  
CP[23]  
CP[21]  
C
C
C
UHPI host interrupt  
UHPI ready  
UHPI address strobe  
40  
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3.2.23 Universal Parallel Port (uPP)  
Table 3-23. Universal Parallel Port (uPP) Terminal Functions  
SIGNAL  
NAME  
POWER  
TYPE(1)  
PULL(2)  
DESCRIPTION  
GROUP(3)  
NO.  
VP_CLKIN0 / UHPI_HCS /PRU1_R30[10] / GP6[7] /  
UPP_2xTXCLK  
W14  
I
CP[25]  
CP[30]  
CP[30]  
CP[30]  
CP[30]  
C
C
C
C
C
uPP 2x transmit clock input  
uPP channel B clock  
uPP channel B start  
PRU0_R30[25] /MMCSD1_DAT[0] / UPP_CHB_CLOCK /  
GP8[15]/PRU1_R31[27]  
G1  
G2  
J4  
I/O  
I/O  
I/O  
I/O  
PRU0_R30[24]/ MMCSD1_CLK / UPP_CHB_START / GP8[14] /  
PRU1_R31[26]  
PRU0_R30[23] / MMCSD1_CMD / UPP_CHB_ENABLE /  
GP8[13]/PRU1_R31[25]  
uPP channel B enable  
uPP channel B wait  
PRU0_R30[22] / PRU1_R30[8] / UPP_CHB_WAIT / GP8[12]/  
PRU1_R31[24]  
G3  
PRU0_R30[29] /UHPI_HCNTL0 / UPP_CHA_CLOCK / GP6[11]  
PRU0_R30[28] / UHPI_HCNTL1 / UPP_CHA_START / GP6[10]  
PRU0_R30[27] / UHPI_HHWIL / UPP_CHA_ENABLE / GP6[9]  
U17  
W15  
U16  
I/O  
I/O  
I/O  
CP[24]  
CP[24]  
CP[24]  
C
C
C
uPP channel A clock  
uPP channel A start  
uPP channel A enable  
PRU0_R30[26] /UHPI_HRW / UPP_CHA_WAIT / GP6[8] /  
PRU1_R31[17]  
T15  
I/O  
CP[24]  
C
uPP channel A wait  
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.  
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name  
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured  
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different  
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.  
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using  
the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the  
device is out of reset. During reset, all of the pins associated with these registers are pulled down. If the application requires a pull-up,  
an external pull-up can be used. For more detailed information on pullup/pulldown resistors and situations where external  
pullup/pulldown resistors are required, see the Pullup/Pulldown Resistors section. For electrical specifications on pullup and internal  
pulldown circuits, see the Specifications section.  
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can  
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of  
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power  
supply DVDD3318_C.  
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Table 3-23. Universal Parallel Port (uPP) Terminal Functions (continued)  
SIGNAL  
NAME  
POWER  
TYPE(1)  
PULL(2)  
DESCRIPTION  
GROUP(3)  
NO.  
VP_DOUT[7] / LCD_D[7] / UPP_XD[15] / GP7[15] /  
PRU1_R31[15]  
U2  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
CP[28]  
CP[28]  
CP[28]  
CP[28]  
CP[28]  
CP[28]  
C
C
C
C
C
C
VP_DOUT[6] / LCD_D[6] / UPP_XD[14] / GP7[14] /  
PRU1_R31[14]  
U1  
V3  
V2  
V1  
W3  
VP_DOUT[5] / LCD_D[5] / UPP_XD[13] / GP7[13] /  
PRU1_R31[13]  
VP_DOUT[4] / LCD_D[4] / UPP_XD[12] / GP7[12] /  
PRU1_R31[12]  
VP_DOUT[3] / LCD_D[3] / UPP_XD[11] / GP7[11] /  
PRU1_R31[11]  
VP_DOUT[2] / LCD_D[2] / UPP_XD[10] / GP7[10] /  
PRU1_R31[10]  
VP_DOUT[1] / LCD_D[1] / UPP_XD[9] / GP7[9] / PRU1_R31[9]  
VP_DOUT[0] / LCD_D[0] / UPP_XD[8] / GP7[8] / PRU1_R31[8]  
VP_DOUT[15] / LCD_D[15] / UPP_XD[7] / GP7[7] / BOOT[7]  
VP_DOUT[14] / LCD_D[14] / UPP_XD[6] / GP7[6] / BOOT[6]  
VP_DOUT[13] / LCD_D[13] / UPP_XD[5] / GP7[5] / BOOT[5]  
VP_DOUT[12] / LCD_D[12] / UPP_XD[4] / GP7[4] / BOOT[4]  
VP_DOUT[11] / LCD_D[11] / UPP_XD[3] / GP7[3] / BOOT[3]  
VP_DOUT[10] / LCD_D[10] / UPP_XD[2] / GP7[2] / BOOT[2]  
VP_DOUT[9] / LCD_D[9] / UPP_XD[1] / GP7[1] / BOOT[1]  
VP_DOUT[8] / LCD_D[8] / UPP_XD[0] / GP7[0] / BOOT[0]  
W2  
W1  
P4  
R3  
R2  
R1  
T3  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
CP[28]  
CP[28]  
CP[29]  
CP[29]  
CP[29]  
CP[29]  
CP[29]  
CP[29]  
CP[29]  
CP[29]  
C
C
C
C
C
C
C
C
C
C
T2  
T1  
U3  
VP_DIN[7] / UHPI_HD[15] / UPP_D[15] / RMII_TXD[1] /  
PRU0_R31[29]  
U18  
V16  
R14  
W16  
V17  
W17  
W18  
W19  
V18  
V19  
U19  
T16  
R18  
R19  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
CP[26]  
CP[26]  
CP[26]  
CP[26]  
CP[26]  
CP[26]  
CP[26]  
CP[26]  
CP[27]  
CP[27]  
CP[27]  
CP[27]  
CP[27]  
CP[27]  
C
C
C
C
C
C
C
C
C
C
C
C
C
C
VP_DIN[6] / UHPI_HD[14] / UPP_D[14] / RMII_TXD[0] /  
PRU0_R31[28]  
uPP data bus  
VP_DIN[5] / UHPI_HD[13] / UPP_D[13] / RMII_TXEN /  
PRU0_R31[27]  
VP_DIN[4] / UHPI_HD[12] / UPP_D[12] / RMII_RXD[1] /  
PRU0_R31[26]  
VP_DIN[3] / UHPI_HD[11] / UPP_D[11] / RMII_RXD[0] /  
PRU0_R31[25]  
VP_DIN[2] / UHPI_HD[10] / UPP_D[10] / RMII_RXER /  
PRU0_R31[24]  
VP_DIN[1] / UHPI_HD[9] / UPP_D[9] / RMII_MHZ_50_CLK /  
PRU0_R31[23]  
VP_DIN[0] / UHPI_HD[8] / UPP_D[8] / RMII_CRS_DV /  
PRU1_R31[29]  
VP_DIN[15]_VSYNC / UHPI_HD[7] / UPP_D[7]/PRU0_R30[15] /  
PRU0_R31[15]  
VP_DIN[14]_HSYNC / UHPI_HD[6] / UPP_D[6]/ PRU0_R30[14] /  
PRU0_R31[14]  
VP_DIN[13]_FIELD / UHPI_HD[5] / UPP_D[5] /PRU0_R30[13] /  
PRU0_R31[13]  
VP_DIN[12] / UHPI_HD[4] / UPP_D[4]/ PRU0_R30[12] /  
PRU0_R31[12]  
VP_DIN[11] / UHPI_HD[3] / UPP_D[3]/ PRU0_R30[11] /  
PRU0_R31[11]  
VP_DIN[10] / UHPI_HD[2] / UPP_D[2]/ PRU0_R30[10] /  
PRU0_R31[10]  
VP_DIN[9] / UHPI_HD[1] / UPP_D[1]/ PRU0_R30[9] /  
PRU0_R31[9]  
R15  
P17  
I/O  
I/O  
CP[27]  
CP[27]  
C
C
VP_DIN[8] / UHPI_HD[0] / UPP_D[0] / GP6[5] / PRU1_R31[0]  
42  
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3.2.24 Video Port Interface (VPIF)  
Table 3-24. Video Port Interface (VPIF) Terminal Functions  
SIGNAL  
NAME  
POWER  
TYPE(1)  
PULL(2)  
DESCRIPTION  
GROUP(3)  
NO.  
VIDEO INPUT  
VP_CLKIN0 / UHPI_HCS / PRU1_R30[10] / GP6[7] /  
UPP_2xTXCLK  
VPIF capture channel 0  
input clock  
W14  
I
I
I
I
I
I
I
I
CP[25]  
CP[25]  
CP[27]  
CP[27]  
CP[27]  
CP[27]  
CP[27]  
CP[27]  
C
C
C
C
C
C
C
C
VPIF capture channel 1  
input clock  
VP_CLKIN1 / UHPI_HDS1/PRU1_R30[9] / GP6[6] / PRU1_R31[16] V15  
VP_DIN[15]_VSYNC / UHPI_HD[7] / UPP_D[7] / PRU0_R30[15] /  
PRU0_R31[15]  
V18  
VP_DIN[14]_HSYNC / UHPI_HD[6] / UPP_D[6] / RU0_R30[14] /  
PRU0_R31[14]  
V19  
VP_DIN[13]_FIELD / UHPI_HD[5] / UPP_D[5] / PRU0_R30[13] /  
PRU0_R31[13]  
U19  
VP_DIN[12] / UHPI_HD[4] / UPP_D[4] / PRU0_R30[12] /  
PRU0_R31[12]  
T16  
VP_DIN[11] / UHPI_HD[3] / UPP_D[3] / PRU0_R30[11] /  
PRU0_R31[11]  
R18  
VP_DIN[10] / UHPI_HD[2] / UPP_D[2] / PRU0_R30[10] /  
PRU0_R31[10]  
R19  
VP_DIN[9] / UHPI_HD[1] / UPP_D[1] / PRU0_R30[9] /  
PRU0_R31[9]  
R15  
I
I
I
CP[27]  
CP[27]  
CP[26]  
C
C
C
VP_DIN[8] / UHPI_HD[0] / UPP_D[0] / GP6[5] / PRU1_R31[0]  
P17  
U18  
VPIF capture data bus  
VP_DIN[7] / UHPI_HD[15] / UPP_D[15] / RMII_TXD[1] /  
PRU0_R31[29]  
VP_DIN[6] / UHPI_HD[14] / UPP_D[14] / RMII_TXD[0] /  
PRU0_R31[28]  
V16  
R14  
W16  
V17  
I
I
I
I
I
I
I
CP[26]  
CP[26]  
CP[26]  
CP[26]  
CP[26]  
CP[26]  
CP[26]  
C
C
C
C
C
C
C
VP_DIN[5] / UHPI_HD[13] / UPP_D[13] / RMII_TXEN /  
PRU0_R31[27]  
VP_DIN[4] / UHPI_HD[12] / UPP_D[12] / RMII_RXD[1] /  
PRU0_R31[26]  
VP_DIN[3] / UHPI_HD[11] / UPP_D[11] / MII_RXD[0] /  
PRU0_R31[25]  
VP_DIN[2] / UHPI_HD[10] / UPP_D[10] / RMII_RXER /  
PRU0_R31[24]  
W17  
W18  
W19  
VP_DIN[1] / UHPI_HD[9] / UPP_D[9] / RMII_MHZ_50_CLK /  
PRU0_R31[23]  
VP_DIN[0] / UHPI_HD[8] / UPP_D[8] / RMII_CRS_DV /  
PRU1_R31[29]  
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.  
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name  
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured  
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different  
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.  
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using  
the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the  
device is out of reset. During reset, all of the pins associated with these registers are pulled down. If the application requires a pull-up,  
an external pull-up can be used. or more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown  
resistors are required, see the Pullup/Pulldown Resistors section. For electrical specifications on pullup and internal pulldown circuits,  
see the Specifications section.  
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can  
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of  
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power  
supply DVDD3318_C.  
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Table 3-24. Video Port Interface (VPIF) Terminal Functions (continued)  
SIGNAL  
NAME  
POWER  
TYPE(1)  
PULL(2)  
DESCRIPTION  
GROUP(3)  
NO.  
VIDEO OUTPUT  
VP_CLKIN2 / MMCSD1_DAT[3] / PRU1_R30[3] / GP6[4] /  
PRU1_R31[4]  
VPIF display channel 2  
input clock  
H3  
I
CP[30]  
CP[30]  
CP[30]  
CP[30]  
C
C
C
C
VP_CLKOUT2 / MMCSD1_DAT[2] / PRU1_R30[2] / GP6[3] /  
PRU1_R31[3]  
VPIF display channel 2  
output clock  
K3  
J3  
O
I
VP_CLKIN3 / MMCSD1_DAT[1] / PRU1_R30[1] / GP6[2] /  
PRU1_R31[2]  
VPIF display channel 3  
input clock  
VPIF display channel 3  
output clock  
VP_CLKOUT3 / PRU1_R30[0] / GP6[1] / PRU1_R31[1]  
K4  
O
VP_DOUT[15] / LCD_D[15] / UPP_XD[7] / GP7[7] / BOOT[7]  
VP_DOUT[14] / LCD_D[14] / UPP_XD[6] / GP7[6] / BOOT[6]  
VP_DOUT[13] / LCD_D[13] / UPP_XD[5] / GP7[5] / BOOT[5]  
VP_DOUT[12] / LCD_D[12] / UPP_XD[4] / GP7[4] / BOOT[4]  
VP_DOUT[11] / LCD_D[11] / UPP_XD[3] / GP7[3] / BOOT[3]  
VP_DOUT[10] / LCD_D[10] / UPP_XD[2] / GP7[2] / BOOT[2]  
VP_DOUT[9] / LCD_D[9] / UPP_XD[1] / GP7[1] / BOOT[1]  
VP_DOUT[8] / LCD_D[8] / UPP_XD[0] / GP7[0] / BOOT[0]  
P4  
R3  
R2  
R1  
T3  
T2  
T1  
U3  
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
CP[29]  
CP[29]  
CP[29]  
CP[29]  
CP[29]  
CP[29]  
CP[29]  
CP[29]  
CP[28]  
CP[28]  
CP[28]  
CP[28]  
CP[28]  
CP[28]  
CP[28]  
CP[28]  
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
VPIF display data bus  
VP_DOUT[7] / LCD_D[7] / UPP_XD[15] / GP7[15] / PRU1_R31[15]  
VP_DOUT[6] / LCD_D[6] / UPP_XD[14] / GP7[14] / PRU1_R31[14]  
VP_DOUT[5] / LCD_D[5] / UPP_XD[13] / GP7[13] / PRU1_R31[13]  
VP_DOUT[4] / LCD_D[4] / UPP_XD[12] / GP7[12] / PRU1_R31[12]  
VP_DOUT[3] / LCD_D[3] / UPP_XD[11] / GP7[11] / PRU1_R31[11]  
U2  
U1  
V3  
V2  
V1  
VP_DOUT[2] / LCD_D[2] / UPP_XD[10] / GP7[10] / PRU1_R31[10] W3  
VP_DOUT[1] / LCD_D[1] / UPP_XD[9] / GP7[9] / PRU1_R31[9]  
VP_DOUT[0] / LCD_D[0] / UPP_XD[8] / GP7[8] / PRU1_R31[8]  
W2  
W1  
44  
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3.2.25 General Purpose Input Output  
Table 3-25. General Purpose Input Output Terminal Functions  
SIGNAL  
NAME  
POWER  
TYPE(1)  
PULL(2)  
DESCRIPTION  
GROUP(3)  
NO.  
GP0  
ACLKR / PRU0_R30[20] / GP0[15] / PRU0_R31[22]  
ACLKX / PRU0_R30[19] / GP0[14] / PRU0_R31[21]  
AFSR / GP0[13] / PRU0_R31[20]  
A1  
B1  
C2  
B2  
I/O  
I/O  
I/O  
I/O  
CP[0]  
CP[0]  
CP[0]  
CP[0]  
A
A
A
A
AFSX / GP0[12] / PRU0_R31[19]  
AHCLKR / PRU0_R30[18] / UART1_RTS / GP0[11] /  
PRU0_R31[18]  
A2  
A3  
I/O  
I/O  
CP[0]  
CP[0]  
A
A
AHCLKX / USB_REFCLKIN / UART1_CTS / GP0[10] /  
PRU0_R31[17]  
AMUTE / PRU0_R30[16] / UART2_RTS / GP0[9] / PRU0_R31[16]  
RTC_ALARM / UART2_CTS / GP0[8] / DEEPSLEEP  
AXR15 / EPWM0TZ[0] / ECAP2_APWM2 / GP0[7]  
AXR14 / CLKR1 / GP0[6]  
D5  
F4  
A4  
B4  
B3  
C4  
C5  
D4  
C3  
E4  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
CP[0]  
CP[0]  
CP[1]  
CP[2]  
CP[2]  
CP[2]  
CP[2]  
CP[2]  
CP[2]  
CP[3]  
A
A
A
A
A
A
A
A
A
A
GPIO Bank 0  
AXR13 / CLKX1 / GP0[5]  
AXR12 / FSR1 / GP0[4]  
AXR11 / FSX1 / GP0[3]  
AXR10 / DR1 / GP0[2]  
AXR9 / DX1 / GP0[1]  
AXR8 / CLKS1 / ECAP1_APWM1 /GP0[0] / PRU0_R31[8]  
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.  
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the signal name  
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured  
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different  
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.  
(2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using  
the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the  
device is out of reset. During reset, all of the pins associated with these registers are pulled down. If the application requires a pull-up,  
an external pull-up can be used. For more detailed information on pullup/pulldown resistors and situations where external  
pullup/pulldown resistors are required, see the Pullup/Pulldown Resistors section. For electrical specifications on pullup and internal  
pulldown circuits, see the Specifications section.  
(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can  
be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of  
power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power  
supply DVDD3318_C.  
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Table 3-25. General Purpose Input Output Terminal Functions (continued)  
SIGNAL  
NAME  
POWER  
TYPE(1)  
PULL(2)  
DESCRIPTION  
GROUP(3)  
NO.  
GP1  
AXR7 / EPWM1TZ[0] / PRU0_R30[17] / GP1[15] / PRU0_R31[7]  
AXR6 / CLKR0 / GP1[14] / MII_TXEN / PRU0_R31[6]  
AXR5 / CLKX0 / GP1[13] / MII_TXCLK  
D2  
C1  
D3  
D1  
E3  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
CP[4]  
CP[5]  
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
CP[5]  
AXR4 / FSR0 / GP1[12] / MII_COL  
CP[5]  
AXR3 / FSX0 / GP1[11] / MII_TXD[3]  
CP[5]  
AXR2 / DR0 / GP1[10] / MII_TXD[2]  
E2  
CP[5]  
AXR1 / DX0 / GP1[9] / MII_TXD[1]  
E1  
CP[5]  
SPI0_CLK / EPWM0A / GP1[8] / MII_RXCLK  
D19  
CP[7]  
GPIO Bank 1  
SPI0_SCS[1] / TM64P0_OUT12 / GP1[7] / MDCLK / TM64P0_IN12 E16  
CP[10]  
CP[10]  
CP[11]  
CP[11]  
CP[12]  
CP[12]  
CP[13]  
CP[13]  
SPI0_SCS[0] / TM64P1_OUT12 / GP1[6] / MDIO / TM64P1_IN12  
SPI1_SCS[7] / I2C0_SCL / TM64P2_OUT12 / GP1[5]  
SPI1_SCS[6] / I2C0_SDA / TM64P3_OUT12 / GP1[4]  
SPI1_SCS[5] / UART2_RXD / I2C1_SCL / GP1[3]  
SPI1_SCS[4] / UART2_TXD / I2C1_SDA / GP1[2]  
SPI1_SCS[3] / UART1_RXD / SATA_LED / GP1[1]  
SPI1_SCS[2] / UART1_TXD / SATA_CP_POD / GP1[0]  
D17  
G16  
G18  
F17  
F16  
E18  
F19  
46  
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Table 3-25. General Purpose Input Output Terminal Functions (continued)  
SIGNAL  
NAME  
POWER  
TYPE(1)  
PULL(2)  
DESCRIPTION  
GROUP(3)  
NO.  
GP2  
SPI1_SCS[1] / EPWM1A / PRU0_R30[8] / GP2[15] / TM64P2_IN12 F18  
SPI1_SCS[0] / EPWM1B / PRU0_R30[7] / GP2[14] / TM64P3_IN12 E19  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
CP[14]  
CP[14]  
CP[15]  
CP[15]  
CP[15]  
CP[15]  
CP[16]  
CP[16]  
CP[16]  
CP[16]  
CP[16]  
CP[16]  
CP[16]  
CP[16]  
CP[16]  
CP[16]  
A
A
A
A
A
A
B
B
B
B
B
B
B
B
B
B
SPI1_CLK / GP2[13]  
G19  
H16  
H17  
G17  
A15  
C15  
B7  
SPI1_ENA / GP2[12]  
SPI1_SOMI / GP2[11]  
SPI1_SIMO / GP2[10]  
EMA_BA[1] / GP2[9]  
EMA_BA[0] / GP2[8]  
GPIO Bank 2  
EMA_CLK / PRU0_R30[5] / GP2[7] / PRU0_R31[5]  
EMA_SDCKE / PRU0_R30[4] / GP2[6] / PRU0_R31[4]  
EMA_RAS / PRU0_R30[3] / GP2[5] / PRU0_R31[3]  
EMA_CAS / PRU0_R30[2] / GP2[4] / PRU0_R31[2]  
EMA_WEN_DQM[0] / GP2[3]  
D8  
A16  
A9  
C8  
EMA_WEN_DQM[1] / GP2[2]  
A5  
EMA_WAIT[1] / PRU0_R30[1] / GP2[1] / PRU0_R31[1]  
EMA_CS[0] / GP2[0]  
B19  
A18  
GP3  
EMA_CS[2] / GP3[15]  
EMA_CS[3] / GP3[14]  
EMA_CS[4] / GP3[13]  
EMA_CS[5] / GP3[12]  
EMA_WE / GP3[11]  
B17  
A17  
F9  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
CP[16]  
CP[16]  
CP[16]  
CP[16]  
CP[16]  
CP[16]  
CP[16]  
CP[16]  
CP[17]  
CP[17]  
CP[17]  
CP[17]  
CP[17]  
CP[17]  
CP[17]  
CP[17]  
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B16  
B9  
EMA_OE / GP3[10]  
B15  
D10  
B18  
E6  
EMA_A_RW / GP3[9]  
EMA_WAIT[0] / PRU0_R30[0] / GP3[8] / PRU0_R31[0]  
EMA_D[15] / GP3[7]  
GPIO Bank 3  
EMA_D[14] / GP3[6]  
C7  
EMA_D[13] / GP3[5]  
B6  
EMA_D[12] / GP3[4]  
A6  
EMA_D[11] / GP3[3]  
D6  
EMA_D[10] / GP3[2]  
A7  
EMA_D[9] / GP3[1]  
D9  
EMA_D[8] / GP3[0]  
E10  
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Table 3-25. General Purpose Input Output Terminal Functions (continued)  
SIGNAL  
NAME  
POWER  
TYPE(1)  
PULL(2)  
DESCRIPTION  
GROUP(3)  
NO.  
GP4  
EMA_D[7] / GP4[15]  
EMA_D[6] / GP4[14]  
EMA_D[5] / GP4[13]  
EMA_D[4] / GP4[12]  
EMA_D[3] / GP4[11]  
EMA_D[2] / GP4[10]  
EMA_D[1] / GP4[9]  
EMA_D[0] / GP4[8]  
D7  
C6  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
CP[17]  
CP[17]  
CP[17]  
CP[17]  
CP[17]  
CP[17]  
CP[17]  
CP[17]  
CP[18]  
CP[18]  
CP[18]  
CP[18]  
CP[18]  
CP[18]  
CP[18]  
CP[18]  
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
E7  
B5  
E8  
B8  
A8  
C9  
GPIO Bank 4  
MMCSD0_CLK / PRU1_R30[31] / GP4[7]  
E9  
EMA_A[22] / MMCSD0_CMD / PRU1_R30[30] / GP4[6]  
EMA_A[21] / MMCSD0_DAT[0] / PRU1_R30[29] / GP4[5]  
EMA_A[20] / MMCSD0_DAT[1] / PRU1_R30[28] / GP4[4]  
EMA_A[19] / MMCSD0_DAT[2] / PRU1_R30[27] / GP4[3]  
EMA_A[18] / MMCSD0_DAT[3] / PRU1_R30[26] / GP4[2]  
EMA_A[17] / MMCSD0_DAT[4] / PRU1_R30[25] / GP4[1]  
EMA_A[16] / MMCSD0_DAT[5] / PRU1_R30[24] / GP4[0]  
A10  
B10  
A11  
C10  
E11  
B11  
E12  
GP5  
EMA_A[15] / MMCSD0_DAT[6] / PRU1_R30[23] / GP5[15] /  
PRU1_R31[23]  
C11  
A12  
D11  
I/O  
I/O  
I/O  
CP[19]  
CP[19]  
CP[19]  
B
B
B
EMA_A[14] / MMCSD0_DAT[7] / PRU1_R30[22] / GP5[14] /  
PRU1_R31[22]  
EMA_A[13] / PRU0_R30[21] / PRU1_R30[21] / GP5[13] /  
PRU1_R31[21]  
EMA_A[12] / PRU1_R30[20] / GP5[12] / PRU1_R31[20]  
EMA_A[11] / PRU1_R30[19] / GP5[11] / PRU1_R31[19]  
EMA_A[10] / PRU1_R30[18] / GP5[10] / PRU1_R31[18]  
EMA_A[9] / PRU1_R30[17] / GP5[9]  
EMA_A[8] / PRU1_R30[16] / GP5[8]  
EMA_A[7] / PRU1_R30[15] / GP5[7]  
EMA_A[6] / GP5[6]  
D13  
B12  
C12  
D12  
A13  
B13  
E13  
C13  
A14  
D14  
B14  
D15  
C14  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
CP[19]  
CP[19]  
CP[19]  
CP[19]  
CP[19]  
CP[20]  
CP[20]  
CP[20]  
CP[20]  
CP[20]  
CP[20]  
CP[20]  
CP[20]  
B
B
B
B
B
B
B
B
B
B
B
B
B
GPIO Bank 5  
EMA_A[5] / GP5[5]  
EMA_A[4] / GP5[4]  
EMA_A[3] / GP5[3]  
EMA_A[2] / GP5[2]  
EMA_A[1] / GP5[1]  
EMA_A[0] / GP5[0]  
48  
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Table 3-25. General Purpose Input Output Terminal Functions (continued)  
SIGNAL  
NAME  
POWER  
TYPE(1)  
PULL(2)  
DESCRIPTION  
GROUP(3)  
NO.  
GP6  
RESETOUT / UHPI_HAS / PRU1_R30[14] / GP6[15]  
T17  
T18  
R17  
R16  
U17  
W15  
U16  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
CP[21]  
CP[22]  
CP[23]  
CP[23]  
CP[24]  
CP[24]  
CP[24]  
C
C
C
C
C
C
C
CLKOUT / UHPI_HDS2 / PRU1_R30[13] / GP6[14]  
PRU0_R30[31] / UHPI_HRDY / PRU1_R30[12] / GP6[13]  
PRU0_R30[30] / UHPI_HINT / PRU1_R30[11] / GP6[12]  
PRU0_R30[29] / UHPI_HCNTL0 / UPP_CHA_CLOCK / GP6[11]  
PRU0_R30[28] / UHPI_HCNTL1 / UPP_CHA_START / GP6[10]  
PRU0_R30[27] / UHPI_HHWIL / UPP_CHA_ENABLE / GP6[9]  
PRU0_R30[26] / UHPI_HRW / UPP_CHA_WAIT/GP6[8] /  
PRU1_R31[17]  
T15  
I/O  
I/O  
I/O  
I/O  
I/O  
CP[24]  
CP[25]  
CP[25]  
CP[27]  
CP[30]  
C
C
C
C
C
VP_CLKIN0 / UHPI_HCS / PRU1_R30[10] GP6[7] / UPP_2xTXCLK W14  
GPIO Bank 6  
VP_CLKIN1 / UHPI_HDS1 / PRU1_R30[9] / GP6[6] /  
PRU1_R31[16]  
V15  
VP_DIN[8] / UHPI_HD[0] / UPP_D[0] / GP6[5] / PRU1_R31[0]  
P17  
H3  
VP_CLKIN2 / MMCSD1_DAT[3] / PRU1_R30[3] / GP6[4] /  
PRU1_R31[4]  
VP_CLKOUT2 / MMCSD1_DAT[2] / PRU1_R30[2] / GP6[3] /  
PRU1_R31[3]  
K3  
J3  
I/O  
I/O  
CP[30]  
CP[30]  
C
C
VP_CLKIN3 / MMCSD1_DAT[1] / PRU1_R30[1] / GP6[2] /  
PRU1_R31[2]  
VP_CLKOUT3 / PRU1_R30[0] / GP6[1] / PRU1_R31[1]  
LCD_AC_ENB_CS / GP6[0] / PRU1_R31[28]  
K4  
R5  
I/O  
I/O  
CP[30]  
CP[31]  
C
C
GP7  
VP_DOUT[7] / LCD_D[7] / UPP_XD[15] / GP7[15] / PRU1_R31[15]  
VP_DOUT[6] / LCD_D[6] / UPP_XD[14] / GP7[14] / PRU1_R31[14]  
VP_DOUT[5] / LCD_D[5] / UPP_XD[13] / GP7[13] / PRU1_R31[13]  
VP_DOUT[4] / LCD_D[4] / UPP_XD[12] / GP7[12] / PRU1_R31[12]  
VP_DOUT[3] / LCD_D[3] / UPP_XD[11] / GP7[11] / PRU1_R31[11]  
U2  
U1  
V3  
V2  
V1  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
CP[28]  
CP[28]  
CP[28]  
CP[28]  
CP[28]  
CP[28]  
CP[28]  
CP[28]  
CP[29]  
CP[29]  
CP[29]  
CP[29]  
CP[29]  
CP[29]  
CP[29]  
CP[29]  
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
VP_DOUT[2] / LCD_D[2] / UPP_XD[10] / GP7[10] / PRU1_R31[10] W3  
VP_DOUT[1] / LCD_D[1] / UPP_XD[9] / GP7[9] / PRU1_R31[9]  
VP_DOUT[0] / LCD_D[0] / UPP_XD[8] / GP7[8] / PRU1_R31[8]  
VP_DOUT[15] / LCD_D[15] / UPP_XD[7] / GP7[7] / BOOT[7]  
VP_DOUT[14] / LCD_D[14] / UPP_XD[6] / GP7[6] / BOOT[6]  
VP_DOUT[13] / LCD_D[13] / UPP_XD[5] / GP7[5]/ BOOT[5]  
VP_DOUT[12] / LCD_D[12] / UPP_XD[4] / GP7[4] / BOOT[4]  
VP_DOUT[11] / LCD_D[11] / UPP_XD[3] / GP7[3] / BOOT[3]  
VP_DOUT[10] / LCD_D[10] / UPP_XD[2] / GP7[2] / BOOT[2]  
VP_DOUT[9] / LCD_D[9] / UPP_XD[1] / GP7[1] / BOOT[1]  
VP_DOUT[8] / LCD_D[8] / UPP_XD[0] / GP7[0] / BOOT[0]  
W2  
W1  
P4  
R3  
R2  
R1  
T3  
GPIO Bank 7  
T2  
T1  
U3  
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Table 3-25. General Purpose Input Output Terminal Functions (continued)  
SIGNAL  
NAME  
POWER  
TYPE(1)  
PULL(2)  
DESCRIPTION  
GROUP(3)  
NO.  
GP8  
PRU0_R30[25] / MMCSD1_DAT[0] / UPP_CHB_CLOCK / GP8[15]  
/ PRU1_R31[27]  
G1  
G2  
J4  
I/O  
I/O  
I/O  
CP30]  
CP[30]  
CP[30]  
C
C
C
PRU0_R30[24] / MMCSD1_CLK / UPP_CHB_START / GP8[14] /  
PRU1_R31[26]  
PRU0_R30[23] / MMCSD1_CMD / UPP_CHB_ENABLE / GP8[13] /  
PRU1_R31[25]  
PRU0_R30[22] / PRU1_R30[8] / UPP_CHB_WAIT / GP8[12] /  
PRU1_R31[24]  
G3  
F1  
F2  
I/O  
I/O  
I/O  
CP[30]  
CP[31]  
CP[31]  
C
C
C
MMCSD1_DAT[7] / LCD_PCLK / PRU1_R30[7] / GP8[11]  
MMCSD1_DAT[6] / LCD_MCLK / PRU1_R30[6] / GP8[10] /  
PRU1_R31[7]  
MMCSD1_DAT[5] / LCD_HSYNC / PRU1_R30[5] / GP8[9] /  
PRU1_R31[6]  
H4  
G4  
I/O  
I/O  
CP[31]  
CP[31]  
C
C
GPIO Bank 8  
MMCSD1_DAT[4] / LCD_VSYNC / PRU1_R30[4] / GP8[8] /  
PRU1_R31[5]  
AXR0 / ECAP0_APWM0 / GP8[7] / MII_TXD[0] / CLKS0  
SPI0_SOMI / EPWMSYNCI / GP8[6] / MII_RXER  
SPI0_SIMO / EPWMSYNCO / GP8[5] / MII_CRS  
SPI0_SCS[5] / UART0_RXD / GP8[4] / MII_RXD[3]  
SPI0_SCS[4] / UART0_TXD / GP8[3] / MII_RXD[2]  
F3  
I/O  
I/O  
I/O  
I/O  
I/O  
CP[6]  
CP[7]  
CP[7]  
CP[8]  
CP[8]  
A
A
A
A
A
C16  
C18  
C19  
D18  
SPI0_SCS[3] / UART0_CTS / GP8[2] / MII_RXD[1] /  
SATA_MP_SWITCH  
E17  
I/O  
CP[9]  
A
SPI0_SCS[2] / UART0_RTS / GP8[1] / MII_RXD[0] /  
SATA_CP_DET  
GP8[0](4)  
D16  
K17  
I/O  
I/O  
CP[9]  
IPD  
A
B
(4) GP8[0] is initially configured as a reserved function after reset and will not be in a predictable state. This signal will only be stable after  
the GPIO configuration for this pin has been completed. Users should carefully consider the system implications of this pin being in an  
unknown state after reset.  
50  
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3.2.26 Reserved and No Connect  
Table 3-26. Reserved and No Connect Terminal Functions  
SIGNAL  
NAME  
TYPE(1)  
DESCRIPTION  
NO.  
Reserved. For proper device operation, this pin must be tied either directly to  
CVDD or left unconnected (do not connect to ground).  
RSV2  
NC  
T19  
PWR  
Pin M3 should be left unconnected (do not connect to power or ground)  
Pins M14 and N16 may be left unconnected or connected to ground (VSS)  
M3, M14, N16  
(1) PWR = Supply voltage.  
3.2.27 Supply and Ground  
Table 3-27. Supply and Ground Terminal Functions  
SIGNAL  
NAME  
TYPE(1)  
DESCRIPTION  
NO.  
E15, G7, G8,  
G13, H6, H7,  
H10, H11,  
CVDD (Core supply)  
H12, H13, J6,  
J12, K6, K12,  
L12, M8, M9,  
N8  
PWR  
Variable (1.3 V - 1 V) core supply voltage pins  
RVDD (Internal RAM supply)  
DVDD18 (I/O supply)  
E5, H14, N7  
PWR  
PWR  
1.2-V internal ram supply voltage pins (for 375 MHz versions)  
F14, G6, G10,  
G11, G12,  
J13, K5, L6,  
P13, R13  
1.8-V I/O supply voltage pins. DVDD18 must be powered even if all of  
the DVDD3318_x supplies are operated at 3.3 V.  
F5, F15, G5,  
G14, G15, H5  
1.8-V or 3.3-V dual-voltage LVCMOS I/O supply voltage pins, Group  
A
DVDD3318_A (I/O supply)  
DVDD3318_B (I/O supply)  
PWR  
PWR  
E14, F6, F7,  
F8, F10, F11,  
F12, F13, G9,  
J14, K15  
1.8-V or 3.3-V dual-voltage LVCMOS I/O supply voltage pins, Group  
B
J5, K13, L4,  
L13, M13,  
N13, P5, P6,  
P12, R4  
1.8-V or 3.3-V dual-voltage LVCMOS I/O supply voltage pins, Group  
C
DVDD3318_C (I/O supply)  
PWR  
GND  
A19, H8, H9,  
H15, J7, J8,  
J9, J10, J11,  
K7, K8, K9,  
K10, K11, L5,  
L7, L8, L9,  
VSS (Ground)  
Ground pins.  
L10, L11, M4,  
M5, M6, M7,  
M10, M11, N5,  
N11, N12, P11  
USB0_VDDA33  
USB0_VDDA18  
USB0_VDDA12  
USB_CVDD  
N18  
N14  
N17  
M12  
P15  
P14  
PWR  
PWR  
A
USB0 PHY 3.3-V supply  
USB0 PHY 1.8-V supply input  
USB0 PHY 1.2-V LDO output for bypass cap  
USB0 core logic 1.2-V supply input  
USB1 PHY 3.3-V supply  
PWR  
PWR  
PWR  
USB1_VDDA33  
USB1_VDDA18  
USB1 PHY 1.8-V supply  
M2, N4, P1,  
P2  
SATA_VDD  
SATA_VSS  
PWR  
GND  
SATA PHY 1.2-V logic supply  
SATA PHY ground reference  
H1, H2, K1,  
K2, L3, M1  
(1) PWR = Supply voltage, GND - Ground.  
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Table 3-27. Supply and Ground Terminal Functions (continued)  
SIGNAL  
NAME  
TYPE(1)  
DESCRIPTION  
NO.  
N6, N9, N10,  
P7, P8, P9,  
P10, R7, R8,  
R9  
DDR_DVDD18  
PWR  
DDR PHY 1.8-V power supply pins  
3.3 Pin Multiplexing  
Device level pin multiplexing is controlled by registers PINMUX0 - PINMUX19 in the SYSCFG module.  
See Table 5-5 for .  
For the device family, pin multiplexing can be controlled on a pin-by-pin basis. Each pin that is multiplexed  
with several different functions has a corresponding 4-bit field in one of the PINMUX registers.  
Pin multiplexing selects which of several peripheral pin functions controls the pin's IO buffer output data  
and output enable values only. The default pin multiplexing control for almost every pin is to select 'none'  
of the peripheral functions in which case the pin's IO buffer is held tri-stated.  
Note that the input from each pin is always routed to all of the peripherals that share the pin; the PINMUX  
registers have no effect on input from a pin.  
3.4 Connections for Unused Pins  
All signals multiplexed with multiple functions may be used as an alternate function if a given peripheral is  
not used. Unused non-multiplexed signals and some other specific signals should be handled as specified  
in the tables below.  
If NMI is unused, it should be pulled-high externally through a 10-kΩ resistor to supply DVDD3318_B.  
Table 3-28. Unused USB0 and USB1 Signal Configurations  
Configuration (When USB0 and USB1 are not  
SIGNAL NAME  
Configuration (When only USB1 is not used)  
used)  
USB0_DM  
USB0_DP  
No Connect  
No Connect  
No Connect  
No Connect  
No Connect  
No Connect  
No Connect  
Use as USB0 function  
Use as USB0 function  
Use as USB0 function  
Use as USB0 function  
Use as USB0 function  
3.3V  
USB0_ID  
USB0_VBUS  
USB0_DRVVBUS  
USB0_VDDA33  
USB0_VDDA18  
USB0_VDDA12  
USB1_DM  
1.8V  
Internal USB PHY output connected to an external 0.22-μF filter capacitor  
No Connect  
VSS or No Connect  
VSS or No Connect  
No Connect  
USB1_DP  
No Connect  
USB1_VDDA33  
USB1_VDDA18  
USB_REFCLKIN  
USB_CVDD  
No Connect  
No Connect  
No Connect or other peripheral function  
1.2V  
No Connect  
Use for USB0 or other peripheral function  
1.2V  
Table 3-29. Unused SATA Signal Configuration  
SIGNAL NAME  
Configuration  
No Connect  
No Connect  
No Connect  
No Connect  
SATA_RXP  
SATA_RXN  
SATA_TXP  
SATA_TXN  
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Table 3-29. Unused SATA Signal Configuration (continued)  
SIGNAL NAME  
SATA_REFCLKP  
SATA_REFCLKN  
Configuration  
No Connect  
No Connect  
SATA_MP_SWITCH  
SATA_CP_DET  
SATA_CP_POD  
SATA_LED  
May be used as GPIO or other peripheral function  
May be used as GPIO or other peripheral function  
May be used as GPIO or other peripheral function  
May be used as GPIO or other peripheral function  
No Connect  
SATA_REG  
SATA_VDDR  
No Connect  
Prior to silicon revision 2.0, this supply must be connected to a static 1.2V nominal supply.  
For silicon revision 2.0 and later, this supply may be left unconnected for additional power  
conservation.  
SATA_VDD  
SATA_VSS  
VSS  
Table 3-30. Unused RTC Signal Configuration  
SIGNAL NAME  
RTC_XI  
Configuration  
May be held high (CVDD) or low  
No Connect  
RTC_XO  
RTC_ALARM  
RTC_CVDD  
RTC_VSS  
May be used as GPIO or other peripheral function  
Connect to CVDD  
VSS  
Table 3-31. Unused DDR2/mDDR Memory Controller Signal Configuration  
(1)  
SIGNAL NAME  
Configuration  
No Connect  
No Connect  
No Connect  
No Connect  
No Connect  
No Connect  
No Connect  
No Connect  
No Connect  
No Connect  
No Connect  
No Connect  
No Connect  
No Connect  
No Connect  
No Connect  
No Connect  
DDR_D[15:0]  
DDR_A[13:0]  
DDR_CLKP  
DDR_CLKN  
DDR_CKE  
DDR_WE  
DDR_RAS  
DDR_CAS  
DDS_CS  
DDR_DQM[1:0]  
DDR_DQS[1:0]  
DDR_BA[2:0]  
DDR_DQGATE0  
DDR_DQGATE1  
DDR_ZP  
DDR_VREF  
DDR_DVDD18  
(1) The DDR2/mDDR input buffers are enabled by default on device power up and a maximum current draw of 25mA can result on the 1.8V  
supply. To minimize power consumption, the DDR2/mDDR controller input receivers should be placed in power-down mode by setting  
VTPIO[14] = 1.  
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4 Specifications  
4.1 Absolute Maximum Ratings  
Over operating junction temperature range (unless otherwise noted)(1)  
MIN  
MAX  
UNIT  
Core logic, variable and fixed  
(CVDD, RVDD, RTC_CVDD, PLL0_VDDA ,  
–0.5  
1.4  
PLL1_VDDA , SATA_VDD, USB_CVDD)(2)  
I/O, 1.8 V  
Supply voltage  
(USB0_VDDA18, USB1_VDDA18,  
–0.5  
–0.5  
2
V
SATA_VDDR, DDR_DVDD18)(2)  
I/O, 3.3 V  
(DVDD3318_A, DVDD3318_B, DVDD3318_C,  
3.8  
USB0_VDDA33, USB1_VDDA33)(2)  
Oscillator inputs (OSCIN, RTC_XI), 1.2 V  
–0.3  
–0.3  
CVDD + 0.3  
DVDD + 0.3  
DVDD + 20%  
Dual-voltage LVCMOS inputs, 3.3 V or 1.8 V  
(steady state)  
Dual-voltage LVCMOS inputs, operated at 3.3 V  
(transient overshoot/undershoot)  
up to 20% of signal period  
Input voltage, VI  
V
Dual-voltage LVCMOS inputs, operated at 1.8 V  
(transient overshoot/undershoot)  
DVDD + 30%  
up to 30% of signal period  
USB 5-V tolerant IOs:  
5.25(3)  
(USB0_DM, USB0_DP, USB0_ID, USB1_DM,  
USB1_DP)  
USB0 VBUS Pin  
5.5(3)  
Dual-voltage LVCMOS outputs, 3.3 V or 1.8 V  
(steady state)  
–0.3  
DVDD + 0.3  
Dual-voltage LVCMOS outputs, operated at 3.3  
DVDD + 20%  
V
up to 20% of signal period  
Output voltage, VO  
V
(transient overshoot/undershoot)  
Dual-voltage LVCMOS outputs, operated at 1.8  
DVDD + 30%  
V
up to 30% of signal period  
(transient overshoot/undershoot)  
Input or output voltages 0.3 V above or below  
their respective power rails. Limit clamp current  
that flows through the I/O's internal diode  
protection cells.  
±20  
Clamp current  
mA  
Operating junction temperature, TJ  
Storage temperature, Tstg  
Extended (S suffix)  
–55  
–55  
125  
150  
°C  
°C  
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating  
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
(2) All voltage values are with respect to VSS, USB0_VSSA33, USB0_VSSA, PLL0_VSSA, OSCVSS, RTC_VSS.  
(3) Up to a maximum of 24 hours.  
4.2 ESD Ratings  
VALUE  
±1000  
±500  
UNIT  
Human-body model (HBM)(2)  
Charged-device model (CDM)(3)  
VESD  
ESD stress voltage(1)  
V
(1) Electrostatic discharge (ESD) to measure device sensitivity/immunity to damage caused by electrostatic discharges into the device.  
(2) Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001-2010. JEDEC document JEP 155 states that 500V HBM allows  
safe manufacturing with a standard ESD control process, and manufacturing with less than 500V HBM is possible if necessary  
precautions are taken. Pins listed as 1000V may actually have higher performance.  
(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101E. JEDEC document JEP 157 states that 250V CDM allows safe  
manufacturing with a standard ESD control process. Pins listed as 250V may actually have higher performance.  
54  
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4.3 Power-On-Hours (POH) Limits  
The information in the section below is provided solely for your convenience and does not extend  
or modify the warranty provided under TI’s standard terms and conditions for TI semiconductor  
products.  
To avoid significant degradation, the device power-on hours (POH) must be limited to the following:  
Table 4-1. Recommended Power-On Hours  
Silicon  
Revision  
Operating Junction  
Temperature (Tj)  
Power-On Hours [POH]  
(hours)  
Speed Grade  
Nominal CVDD Voltage (V)  
E
375 MHz  
–55 to 105°C  
1.2 V  
75,000(1)  
(1) 100,000 POH can be achieved at this temperature condition if the device operation is limited to 345 MHz  
Note: Logic functions and parameter values are not assured out of the range specified in the  
recommended operating conditions.  
The above notations cannot be deemed a warranty or deemed to extend or modify the warranty  
under TI’s standard terms and conditions for TI semiconductor products.  
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4.4 Recommended Operating Conditions  
MIN  
NOM  
MAX UNIT  
SUPPLY VOLTAGE  
1.3-V operating  
point  
1.25  
1.14  
1.05  
1.3  
1.2  
1.1  
1.35  
1.2-V operating  
point  
1.32  
V
CVDD  
Core Logic Supply Voltage (variable)  
1.1-V operating  
point  
1.16  
1.05  
1-V operating point  
375 MHz versions  
0.95  
1.14  
0.9  
1
1.2  
1.2  
1.2  
1.2  
1.2  
1.2  
1.8  
3.3  
1.8  
3.3  
1.8  
1.8  
1.8  
0.5 ×  
RVDD  
Internal RAM Supply Voltage  
RTC Core Logic Supply Voltage  
PLL0 Supply Voltage  
1.32  
1.32  
1.32  
1.32  
1.32  
1.32  
1.89  
3.45  
1.89  
3.45  
1.89  
1.89  
1.89  
V
V
V
V
V
V
V
V
V
V
V
V
V
(1)  
RTC_CVDD  
PLL0_VDDA  
PLL1_VDDA  
SATA_VDD  
USB_CVDD  
1.14  
1.14  
1.14  
1.14  
1.71  
3.15  
1.71  
3.15  
1.71  
1.71  
1.71  
0.49 ×  
PLL1 Supply Voltage  
SATA Core Logic Supply Voltage  
USB0, USB1 Core Logic Supply Voltage  
USB0 PHY Supply Voltage  
USB0_VDDA18  
USB0_VDDA33  
USB1_VDDA18  
USB1_VDDA33  
DVDD18(2)  
USB0 PHY Supply Voltage  
USB1 PHY Supply Voltage  
USB1 PHY Supply Voltage  
1.8-V Logic Supply  
SATA_VDDR  
DDR_DVDD18(2)  
SATA PHY Internal Regulator Supply Voltage  
DDR2 PHY Supply Voltage  
0.51 ×  
DDR_DVDD18  
DDR_VREF  
DDR_ZP  
DDR2/mDDR reference voltage  
V
V
DDR_DVDD18 DDR_DVDD18  
DDR2/mDDR impedance control,  
connected via 50-Ω resistor to Vss  
Vss  
1.8-V operating  
point  
1.71  
3.15  
1.71  
3.15  
1.71  
3.15  
1.8  
3.3  
1.8  
3.3  
1.8  
3.3  
1.89  
3.45  
1.89  
3.45  
1.89  
3.45  
Power Group A Dual-voltage IO  
Supply Voltage  
DVDD3318_A  
DVDD3318_B  
DVDD3318_C  
V
V
V
3.3-V operating  
point  
1.8-V operating  
point  
Power Group B Dual-voltage IO  
Supply Voltage  
3.3-V operating  
point  
1.8-V operating  
point  
Power Group C Dual-voltage IO  
Supply Voltage  
3.3-V operating  
point  
SUPPLY GROUND  
VSS  
Core Logic Digital Ground  
PLL0 Ground  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
V
V
V
V
V
V
V
V
PLL0_VSSA  
PLL1_VSSA  
SATA_VSS  
OSCVSS(3)  
RTC_VSS(3)  
USB0_VSSA  
USB0_VSSA33  
PLL1 Ground  
SATA PHY Ground  
Oscillator Ground  
RTC Oscillator Ground  
USB0 PHY Ground  
USB0 PHY Ground  
(1) The RTC provides an option for isolating the RTC_CVDD from the CVDD to reduce current leakage when the RTC is powered  
independently. If these power supplies are not isolated (CTRL.SPLITPOWER=0), RTC_CVDD must be equal to or greater than CVDD.  
If these power supplies are isolated (CTRL.SPLITPOWER=1), RTC_CVDD may be lower than CVDD.  
(2) DVDD18 must be powered even if all of the DVDD3318_x supplies are operated at 3.3 V.  
(3) When an external crystal is used oscillator (OSC_VSS, RTC_VSS) ground must be kept separate from other grounds and connected  
directly to the crystal load capacitor ground. These pins are shorted to VSS on the device itself and should not be connected to VSS on  
the circuit board. If a crystal is not used and the clock input is driven directly, then the oscillator VSS may be connected to board ground.  
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Recommended Operating Conditions (continued)  
MIN  
NOM  
MAX UNIT  
VOLTAGE INPUT HIGH  
High-level input voltage, Dual-voltage I/O, 3.3 V(4)  
2
(4)  
High-level input voltage, Dual-voltage I/O, 1.8 V  
High-level input voltage, RTC_XI  
0.65 × DVDD  
VIH  
V
0.8 ×  
RTC_CVDD  
High-level input voltage, OSCIN  
0.8 × CVDD  
VOLTAGE INPUT LOW  
Low-level input voltage, Dual-voltage I/O, 3.3 V(4)  
Low-level input voltage, Dual-voltage I/O, 1.8 V(4)  
0.8  
0.35 × DVDD  
VIL  
V
0.2 ×  
RTC_CVDD  
Low-level input voltage, RTC_XI  
Low-level input voltage, OSCIN  
0.2 × CVDD  
USB  
USB0_VBUS  
USB external charge pump input  
0
5.25  
V
DIFFERENTIAL CLOCK INPUT VOLTAGE  
Differential input voltage, SATA_REFCLKP and  
SATA_REFCLKN  
250  
2000  
mV  
TRANSITION TIME  
Transition time, 10%-90%, All Inputs (unless otherwise  
specified in the electrical data sections)  
tt  
0.25P or 10(5)  
ns  
OPERATING FREQUENCY  
CVDD = 1.2-V  
operating point  
0
0
0
375(6)  
200(7)  
100(7)  
Extended temperature grade  
(S suffix)  
CVDD = 1.1-V  
operating point  
FPLL0_SYSCLK1,6  
MHz  
CVDD = 1-V  
operating point  
(4) These IO specifications apply to the dual-voltage IOs only and do not apply to DDR2/mDDR or SATA interfaces. DDR2/mDDR IOs are  
1.8V IOs and adhere to the JESD79-2A standard.  
(5) Whichever is smaller. P = the period of the applied signal. Maintaining transition times as fast as possible is recommended to improve  
noise immunity on input signals.  
(6) This operating point is 300 MHz on revision 1.x silicon.  
(7) This operating point is not supported on revision 1.x silicon.  
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4.5 Electrical Characteristics  
Over recommended ranges of supply voltage and operating junction temperature (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
DVDD= 3.15V, IOH = -4 mA  
DVDD= 3.15V, IOH = -100 μA  
MIN  
TYP  
MAX  
UNIT  
V
2.4  
High-level output voltage  
(dual-voltage LVCMOS IOs at 3.3V)(1)  
2.95  
V
VOH  
High-level output voltage  
DVDD= 1.71V, IOH = -2 mA  
DVDD-0.45  
V
(dual-voltage LVCMOS IOs at 1.8V)(1)  
DVDD= 3.15V, IOL = 4mA  
0.4  
0.2  
V
V
Low-level output voltage  
(dual-voltage LVCMOS I/Os at 3.3V)  
DVDD= 3.15V, IOL = 100 μA  
VOL  
Low-level output voltage  
(dual-voltage LVCMOS I/Os at 1.8V)  
DVDD= 1.71V, IOL = 2mA  
0.45  
±9  
V
VI = VSS to DVDD without  
opposing internal resistor  
μA  
VI = VSS to DVDD with  
opposing internal pullup  
resistor  
Input current(1)  
(dual-voltage LVCMOS I/Os)  
70  
-75  
-77  
310  
-270  
-286  
μA  
μA  
μA  
(3)  
(2)  
II  
VI = VSS to DVDD with  
opposing internal pulldown  
(3)  
resistor  
VI = VSS to DVDD with  
Input current (DDR2/mDDR I/Os)  
opposing internal pulldown  
(3)  
resistor  
High-level output current(1)  
(dual-voltage LVCMOS I/Os)  
Low-level output current(1)  
(dual-voltage LVCMOS I/Os)  
IOH  
IOL  
-6  
6
mA  
mA  
Input capacitance (dual-voltage LVCMOS)  
Output capacitance (dual-voltage LVCMOS)  
3
3
pF  
pF  
Capacitance  
(1) These IO specifications apply to the dual-voltage IOs only and do not apply to DDR2/mDDR or SATA interfaces. DDR2/mDDR IOs are  
1.8V IOs and adhere to the JESD79-2A standard. USB0 I/Os adhere to the USB2.0 standard. USB1 I/Os adhere to the USB1.1  
standard. SATA I/Os adhere to the SATA-I and SATA-II standards.  
(2) II applies to input-only pins and bi-directional pins. For input-only pins, II indicates the input leakage current. For bi-directional pins, II  
indicates the input leakage current and off-state (Hi-Z) output leakage current.  
(3) Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor. The pull-up and pull-down strengths shown represent the  
minimum and maximum strength across process variation.  
100k  
10k  
1k  
95  
100  
105  
110  
115  
120  
125  
130  
135  
140  
145  
Continuous Junction Temperature, TJ (èC)  
D001  
(1) See data sheet for absolute maximum and minimum recommended operating conditions.  
(2) Silicon operating life design goal is approximately 9 years at 105°C junction temperature (does not include package interconnect life).  
(3) The predicted operating lifetime vs junction temperature is based on reliability modeling using electromigration as the dominant  
failure mechanism affecting device wear-out for the specific device process and design characteristics.  
Figure 4-1. Operating Life Derating Chart for SM320C6748-HIREL  
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4.6 Thermal Data for GWT Package  
The following table(s) show the thermal resistance characteristics for the PBGA–GWT mechanical  
package.  
Table 4-2. Thermal Resistance Characteristics for PBGA Package (GWT)  
NO.  
1
°C/W(1)  
7.3  
AIR FLOW (m/s)(2)  
RΘJC  
RΘJB  
RΘJA  
Junction-to-case  
Junction-to-board  
Junction-to-free air  
N/A  
N /A  
0.00  
0.50  
1.00  
2.00  
4.00  
0.00  
0.50  
1.00  
2.00  
4.00  
0.00  
0.50  
1.00  
2.00  
4.00  
2
12.4  
23.7  
21.0  
20.1  
19.3  
18.4  
0.2  
3
4
5
RΘJMA  
Junction-to-moving air  
6
7
8
9
0.3  
10  
11  
12  
13  
14  
15  
16  
17  
PsiJT  
Junction-to-package top  
0.3  
0.4  
0.5  
12.3  
12.2  
12.1  
12.0  
11.9  
PsiJB  
Junction-to-board  
(1) These measurements were conducted in a JEDEC defined 2S2P system and will change based on environment as well as application.  
For more information, see these EIA/JEDEC standards – EIA/JESD51-2, Integrated Circuits Thermal Test Method Environment  
Conditions - Natural Convection (Still Air) and JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount  
Packages. Power dissipation of 1 W and ambient temp of 70°C assumed. PCB with 2-oz (70-µm) top and bottom copper thickness and  
1.5-oz (50-µm) inner copper thickness.  
(2) m/s = meters per second  
4.7 Timing and Switching Characteristics  
4.7.1 Timing Parameters and Information  
Tester Pin Electronics  
Data Sheet Timing Reference Point  
42 Ω  
3.5 nH  
Output  
Under  
Test  
Transmission Line  
Z0 = 50 Ω  
(see note)  
Device Pin  
(see note)  
4.0 pF  
1.85 pF  
A. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its  
transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to  
produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to  
add or subtract the transmission line delay (2 ns or longer) from the data sheet timings.  
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the  
device pin and the input signals are driven between 0V and the appropriate IO supply rail for the signal.  
Figure 4-2. Test Load Circuit for AC Timing Measurements  
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The load capacitance value stated is only for characterization and measurement of AC timing signals. This  
load capacitance value does not indicate the maximum load the device is capable of driving.  
4.7.1.1 Signal Transition Levels  
All input and output timing parameters are referenced to Vref for both "0" and "1" logic levels.  
For 3.3-V I/O, Vref = 1.65 V.  
For 1.8-V I/O, Vref = 0.9 V.  
For 1.2-V I/O, Vref = 0.6 V.  
V
ref  
Figure 4-3. Input and Output Voltage Reference Levels for AC Timing Measurements  
All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks,  
VOLMAX and VOH MIN for output clocks  
V
ref  
= V MIN (or V MIN)  
IH OH  
V
ref  
= V MAX (or V MAX)  
IL OL  
Figure 4-4. Rise and Fall Transition Time Voltage Reference Levels  
4.7.2 Power Supply Sequencing  
4.7.2.1 Power-On Sequence  
The device should be powered-on in the following order:  
1. RTC (RTC_CVDD) may be powered from an external device (such as a battery) prior to all other  
supplies being applied or powered-up at the same time as CVDD. If the RTC is not used, RTC_CVDD  
should be connected to CVDD. RTC_CVDD should not be left unpowered while CVDD is powered.  
2. Core logic supplies:  
(a) All variable 1.3-V to 1-V core logic supplies (CVDD)  
(b) All static core logic supplies (RVDD, PLL0_VDDA, PLL1_VDDA, USB_CVDD, SATA_VDD). If  
voltage scaling is not used on the device, groups 2a) and 2b) can be controlled from the same  
power supply and powered up together.  
3. All static 1.8V IO supplies (DVDD18, DDR_DVDD18, USB0_VDDA18, USB1_VDDA18 and  
SATA_VDDR) and any of the LVCMOS IO supply groups used at 1.8V nominal (DVDD3318_A,  
DVDD3318_B, or DVDD3318_C).  
4. All analog 3.3V PHY supplies (USB0_VDDA33 and USB1_VDDA33; these are not required if both  
USB0 and USB1 are not used) and any of the LVCMOS IO supply groups used at 3.3V nominal  
(DVDD3318_A, DVDD3318_B, or DVDD3318_C).  
There is no specific required voltage ramp rate for any of the supplies as long as the LVCMOS supplies  
operated at 3.3V (DVDD3318_A, DVDD3318_B, or DVDD3318_C) never exceed the STATIC 1.8V  
supplies by more than 2 volts.  
RESET must be maintained active until all power supplies have reached their nominal values.  
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4.7.2.2 Power-Off Sequence  
The power supplies can be powered-off in any order as long as LVCMOS supplies operated at 3.3V  
(DVDD3318_A, DVDD3318_B, or DVDD3318_C) never exceed static 1.8V supplies by more than 2 volts.  
There is no specific required voltage ramp down rate for any of the supplies (except as required to meet  
the above mentioned voltage condition).  
4.7.3 Reset Timing  
4.7.3.1 Reset Electrical Data/Timing  
Table 4-3 assumes testing over the recommended operating conditions.  
Table 4-3. Reset Timing Requirements(1)(2)  
1.3V, 1.2V  
1.1V  
1.0V  
NO.  
UNIT  
MIN  
100  
20  
MAX  
MIN  
MAX  
MIN  
MAX  
1
2
3
tw(RSTL)  
Pulse width, RESET/TRST low  
100  
20  
100  
20  
ns  
ns  
tsu(BPV-RSTH)  
th(RSTH-BPV)  
Setup time, boot pins valid before RESET/TRST high  
Hold time, boot pins valid after RESET/TRST high  
RESET high to RESETOUT high; Warm reset  
RESET high to RESETOUT high; Power-on Reset  
20  
20  
20  
ns  
cycles(3)  
td(RSTH-  
RESETOUTH)  
4096  
6169  
4096  
6169  
4096  
6169  
4
5
td(RSTL-RESETOUTL) Delay time, RESET/TRST low to RESETOUT low  
14  
16  
20  
ns  
(1) RESETOUT is multiplexed with other pin functions. See the Terminal Functions table, Table 3-1 for details.  
(2) For power-on reset (POR), the reset timings in this table refer to RESET and TRST together. For warm reset, the reset timings in this  
table refer to RESET only (TRST is held high).  
(3) OSCIN cycles.  
Power  
Supplies  
Ramping  
Power Supplies Stable  
Clock Source Stable  
OSCIN  
RESET  
1
TRST  
4
RESETOUT  
3
2
Boot Pins  
Config  
Figure 4-5. Power-On Reset (RESET and TRST active) Timing  
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Power Supplies Stable  
OSCIN  
TRST  
1
RESET  
5
4
RESETOUT  
3
2
Config  
Boot Pins  
Driven or Hi-Z  
Figure 4-6. Warm Reset (RESET active, TRST high) Timing  
4.7.4 Clock Specifications  
4.7.4.1 Crystal Oscillator or External Clock Input  
The device includes two choices to provide an external clock input, which is fed to the on-chip PLLs to  
generate high-frequency system clocks. These options are illustrated in Figure 4-7 and Figure 4-8. For  
input clock frequencies between 12 and 20 MHz, a crystal with 80 ohm max ESR is recommended. For  
input clock frequencies between 20 and 30 MHz, a crystal with 60 ohm max ESR is recommended.  
Typical load capacitance values are 10-20 pF, where the load capacitance is the series combination of C1  
and C2.  
The CLKMODE bit in the PLLCTL register must be 0 to use the on-chip oscillator. If CLKMODE is set to 1,  
the internal oscillator is disabled.  
Figure 4-7 illustrates the option that uses on-chip 1.2V oscillator with external crystal circuit. Figure 4-8  
illustrates the option that uses an external 1.2V clock input.  
C2  
OSCIN  
Clock Input  
to PLL  
X1  
OSCOUT  
C1  
OSCVSS  
Figure 4-7. On-Chip Oscillator  
Table 4-4. Oscillator Timing Requirements  
PARAMETER  
MIN  
MAX  
UNIT  
fosc  
Oscillator frequency range (OSCIN/OSCOUT)  
12  
30  
MHz  
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Clock  
Input  
to PLL  
OSCIN  
OSCOUT  
NC  
OSCVSS  
Figure 4-8. External 1.2-V Clock Source  
Table 4-5. OSCIN Timing Requirements for an Externally Driven Clock  
PARAMETER  
OSCIN frequency range  
MIN  
12  
MAX  
UNIT  
MHz  
ns  
fOSCIN  
50  
tc(OSCIN)  
tw(OSCINH)  
tw(OSCINL)  
tt(OSCIN)  
tj(OSCIN)  
Cycle time, external clock driven on OSCIN  
Pulse width high, external clock on OSCIN  
Pulse width low, external clock on OSCIN  
Transition time, OSCIN  
20  
0.4 tc(OSCIN)  
0.4 tc(OSCIN)  
ns  
ns  
(1)  
0.25P or 10  
0.02P  
ns  
Period jitter, OSCIN  
ns  
(1) Whichever is smaller. P = the period of the applied signal. Maintaining transition times as fast as possible is recommended to improve  
noise immunity on input signals.  
4.7.4.2 Clock PLLs  
The device has two PLL controllers that provide clocks to different parts of the system. PLL0 provides  
clocks (though various dividers) to most of the components of the device. PLL1 provides clocks to the  
DDR2/mDDR Controller and provides an alternate clock source for the ASYNC3 clock domain. This allows  
the peripherals on the ASYNC3 clock domain to be immune to frequency scaling operation on PLL0.  
The PLL controller provides the following:  
•
•
•
•
Glitch-Free Transitions (on changing clock settings)  
Domain Clocks Alignment  
Clock Gating  
PLL power down  
The various clock outputs given by the controller are as follows:  
•
•
Domain Clocks: SYSCLK [1:n]  
Auxiliary Clock from reference clock source: AUXCLK  
Various dividers that can be used are as follows:  
•
•
Post-PLL Divider: POSTDIV  
SYSCLK Divider: D1, ¼, Dn  
Various other controls supported are as follows:  
•
•
PLL Multiplier Control: PLLM  
Software programmable PLL Bypass: PLLEN  
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4.7.4.2.1 PLL Device-Specific Information  
The device DSP generates the high-frequency internal clocks it requires through an on-chip PLL.  
The PLL requires some external filtering components to reduce power supply noise as shown in Figure 4-  
9.  
1.14V - 1.32V  
50R  
PLL0_VDDA  
0.1  
µF  
0.01  
µF  
VSS  
50R  
50R  
PLL0_VSSA  
PLL1_VDDA  
1.14V - 1.32V  
0.1  
µF  
0.01  
µF  
VSS  
50R  
PLL1_VSSA  
Ferrite Bead: Murata BLM31PG500SN1L or Equivalent  
Figure 4-9. PLL External Filtering Components  
The external filtering components shown above provide noise immunity for the PLLs. PLL0_VDDA and  
PLL1_VDDA should not be connected together to provide noise immunity between the two PLLs.  
Likewise, PLL0_VSSA and PLL1_VSSA should not be connected together.  
The input to the PLL is either from the on-chip oscillator or from an external clock on the OSCIN pin. PLL0  
outputs seven clocks that have programmable divider options. PLL1 outputs three clocks that have  
programmable divider options. Figure 4-10 illustrates the high-level view of the PLL Topology.  
The PLLs are disabled by default after a device reset. They must be configured by software according to  
the allowable operating conditions listed in Table 4-6 before enabling the device to run from the PLL by  
setting PLLEN = 1.  
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PLL Controller 0  
PLLCTL[EXTCLKSRC]  
PLL1_SYSCLK3  
1
0
PLLCTL[PLLEN]  
0
PLLCTL[CLKMODE]  
PLLDIV1 (/1)  
SYSCLK1  
SYSCLK2  
SYSCLK4  
SYSCLK5  
SYSCLK6  
SYSCLK7  
SYSCLK3  
Square  
Wave  
1
0
PLLDIV2 (/2)  
PLLDIV4 (/4)  
PLLDIV5 (/3)  
PLLDIV6 (/1)  
PLLDIV7 (/6)  
PLLDIV3 (/3)  
OSCIN  
PREDIV  
PLL  
POSTDIV  
1
Crystal  
PLLM  
EMIFA  
Internal  
Clock  
0
1
DIV4.5  
Source  
CFGCHIP3[EMA_CLKSRC]  
AUXCLK  
OSCDIV  
PLLC0 OBSCLK  
(CLKOUT Pin)  
14h  
17h  
18h  
19h  
1Ah  
1Bh  
1Ch  
1Dh  
1Eh  
SYSCLK1  
SYSCLK2  
SYSCLK3  
SYSCLK4  
SYSCLK5  
SYSCLK6  
SYSCLK7  
PLLC1 OBSCLK  
OCSEL[OCSRC]  
PLLCTL[PLLEN]  
PLL Controller 1  
PLLDIV2 (/2)  
0
1
SYSCLK2  
SYSCLK3  
SYSCLK1  
PLLDIV3 (/3)  
PLLDIV1 (/1)  
PLL  
POSTDIV  
PLLM  
DDR2/mDDR  
Internal  
Clock  
Source  
14h  
17h  
18h  
19h  
SYSCLK1  
SYSCLK2  
SYSCLK3  
OSCDIV  
PLLC1 OBSCLK  
OCSEL[OCSRC]  
Figure 4-10. PLL Topology  
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Table 4-6. Allowed PLL Operating Conditions (PLL0 and PLL1)  
Default  
Value  
NO.  
PARAMETER  
MIN  
MAX  
N/A  
UNIT  
1
PLLRST: Assertion time during initialization  
N/A  
1000  
ns  
2000 N  
m
Max PLL Lock Time =  
Lock time: The time that the application has to wait for  
the PLL to acquire lock before setting PLLEN, after  
changing PREDIV, PLLM, or OSCIN  
OSCIN  
cycles  
where N = Pre-Divider Ratio  
2
N/A  
/1  
N/A  
M = PLL Multiplier  
(1)  
3
4
PREDIV: Pre-divider value  
/1  
/32  
-
30 (if internal oscillator is used)  
50 (if external clock is used)  
PLLREF: PLL input frequency  
12  
MHz  
5
6
7
PLLM: PLL multiplier values  
PLLOUT: PLL output frequency  
POSTDIV: Post-divider value  
x20  
N/A  
/1  
x4  
300  
/1  
x32  
600  
/32  
MHz  
-
(1) The multiplier values must be chosen such that the PLL output frequency (at PLLOUT) is between 300 and 600 MHz, but the frequency  
going into the SYSCLK dividers (after the post divider) cannot exceed the maximum clock frequency defined for the device at a given  
voltage operating point.  
4.7.4.2.2 Device Clock Generation  
PLL0 is controlled by PLL Controller 0 and PLL1 is controlled by PLL Controller 1. PLLC0 and PLLC1  
manage the clock ratios, alignment, and gating for the system clocks to the chip. The PLLCs are  
responsible for controlling all modes of the PLL through software, in terms of pre-division of the clock  
inputs (PLLC0 only), multiply factors within the PLLs, and post-division for each of the chip-level clocks  
from the PLLs outputs. PLLC0 also controls reset propagation through the chip, clock alignment, and test  
points.  
PLLC0 provides clocks for the majority of the system but PLLC1 provides clocks to the DDR2/mDDR  
Controller and the ASYNC3 clock domain to provide frequency scaling immunity to a defined set or  
peripherals. The ASYNC3 clock domain can either derive its clock from PLL1_SYSCLK2 (for frequency  
scaling immunity from PLL0) or from PLL0_SYSCLK2 (for synchronous timing with PLL0) depending on  
the application requirements. In addition, some peripherals have specific clock options independent of the  
ASYNC clock domain.  
4.7.4.2.3 Dynamic Voltage and Frequency Scaling (DVFS)  
The processor supports multiple operating points by scaling voltage and frequency to minimize power  
consumption for a given level of processor performance.  
Frequency scaling is achieved by modifying the setting of the PLL controllers’ multipliers, post-dividers  
(POSTDIV), and system clock dividers (SYSCLKn). Modification of the POSTDIV and SYSCLK values  
does not require relocking the PLL and provides lower latency to switch between operating points, but at  
the expense of the frequencies being limited by the integer divide values (only the divide values are  
altered the PLL multiplier is left unmodified). Non integer divide frequency values can be achieved by  
changing both the multiplier and the divide values, but when the PLL multiplier is changed the PLL must  
relock, incurring additional latency to change between operating points. Detailed information on modifying  
the PLL Controller settings can be found in the SM320C6748-HIREL DSP System Reference Guide  
(SPRUGJ7).  
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Voltage scaling is enabled from outside the device by controlling an external voltage regulator. The  
processor may communicate with the regulator using GPIOs, I2C or some other interface. When switching  
between voltage-frequency operating points, the voltage must always support the desired frequency.  
When moving from a high-performance operating point to a lower performance operating point, the  
frequency should be lowered first followed by the voltage. When moving from a low-performance operating  
point to a higher performance operating point, the voltage should be raised first followed by the frequency.  
Voltage operating points refer to the CVdd voltage at that point. Other static supplies must be maintained  
at their nominal voltages at all operating points.  
The maximum voltage slew rate for CVdd supply changes is 1 mV/us.  
For additional information on power management solutions from TI for this processor, follow the Power  
Management link in the Product Folder on www.ti.com for this processor.  
The processor supports multiple clock domains some of which have clock ratio requirements to each  
other. SYSCLK1:SYSCLK2:SYSCLK4:SYSCLK6 are synchronous to each other and the SYSCLKn  
dividers must always be configured such that the ratio between these domains is 1:2:4:1. The ASYNC and  
ASYNC3 clock domains are asynchronous to the other clock domains and have no specific ratio  
requirement.  
Table 4-7 summarizes the maximum internal clock frequencies at each of the voltage operating points.  
Table 4-7. Maximum Internal Clock Frequencies at Each Voltage Operating Point  
CLOCK  
SOURCE  
CLOCK DOMAIN  
1.2V NOM  
375 MHz  
1.1V NOM  
200 MHz  
100 MHz  
1.0V NOM  
100 MHz  
50 MHz  
PLL0_SYSCLK1 DSP subsystem  
SYSCLK2 clock domain peripherals and optional clock  
source for ASYNC3 clock domain peripherals  
PLL0_SYSCLK2  
PLL0_SYSCLK3  
187.5 MHz  
Optional clock for ASYNC1 clock domain  
(See ASYNC1 row)  
PLL0_SYSCLK4 SYSCLK4 domain peripherals  
PLL0_SYSCLK5 Not used on this processor  
93.75 MHz  
50 MHz  
25 MHz  
-
-
-
-
-
-
-
PLL0_SYSCLK6 Not used on this processor  
-
PLL0_SYSCLK7 Optional 50 MHz clock source for EMAC RMII interface  
50 MHz  
DDR2/mDDR Interface clock source  
PLL1_SYSCLK1  
312 MHz  
150 MHz  
300 MHz  
100 MHz  
266 MHz  
75 MHz  
(memory interface clock is one-half of the value shown)  
Optional clock source for ASYNC3 clock domain  
PLL1_SYSCLK2  
peripherals  
PLL1_SYSCLK3 Alternate clock source input to PLL Controller 0  
McASP AUXCLK Bypass clock source for the McASP  
PLL0_AUXCLK Bypass clock source for the USB0 and USB1  
Async Mode  
75 MHz  
50 MHz  
48 MHz  
148 MHz  
100 MHz  
50 MHz  
75 MHz  
50 MHz  
48 MHz  
75 MHz  
66.6 MHz  
50 MHz  
75 MHz  
50 MHz  
48 MHz  
50 MHz  
50 MHz  
50 MHz  
ASYNC1  
ASYNC Clock Domain (EMIFA)  
SDRAM Mode  
ASYNC2 Clock Domain (multiple peripherals)  
ASYNC2  
Some interfaces have specific limitations on supported modes/speeds at each operating point. See the  
corresponding peripheral sections of this document for more information.  
TI provides software components (called the Power Manager) to perform DVFS and abstract the task from  
the user. The Power Manager controls changing operating points (both frequency and voltage) and  
handles the related tasks involved such as informing/controlling peripherals to provide graceful transitions  
between operating points. The Power Manager is bundled as a component of DSP/BIOS.  
4.7.5 Recommended Clock and Control Signal Transition Behavior  
All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic  
manner.  
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4.7.6 Peripherals  
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4.7.6.1 Power and Sleep Controller (PSC)  
The Power and Sleep Controllers (PSC) are responsible for managing transitions of system power on/off,  
clock on/off, resets (device level and module level). It is used primarily to provide granular power control  
for on chip modules (peripherals and CPU). A PSC module consists of a Global PSC (GPSC) and a set of  
Local PSCs (LPSCs). The GPSC contains memory mapped registers, PSC interrupts, a state machine for  
each peripheral/module it controls. An LPSC is associated with every module that is controlled by the PSC  
and provides clock and reset control.  
The PSC includes the following features:  
•
Provides a software interface to:  
–
–
–
Control module clock enable/disable  
Control module reset  
Control CPU local reset  
•
Supports IcePick emulation features: power, clock and reset  
PSC0 controls 16 local PSCs.  
PSC1 controls 32 local PSCs.  
Table 4-8. Power and Sleep Controller (PSC) Registers  
PSC0 BYTE  
ADDRESS  
PSC1 BYTE  
ACRONYM  
REGISTER DESCRIPTION  
ADDRESS  
0x01E2 7000  
0x01E2 7018  
0x01E2 7040  
0x01C1 0000  
0x01C1 0018  
0x01C1 0040  
REVID  
INTEVAL  
MERRPR0  
Peripheral Revision and Class Information Register  
Interrupt Evaluation Register  
Module Error Pending Register 0 (module 0-15) (PSC0)  
Module Error Pending Register 0 (module 0-31) (PSC1)  
Module Error Clear Register 0 (module 0-15) (PSC0)  
Module Error Clear Register 0 (module 0-31) (PSC1)  
Power Error Pending Register  
0x01C1 0050  
0x01E2 7050  
MERRCR0  
0x01C1 0060  
0x01C1 0068  
0x01C1 0120  
0x01C1 0128  
0x01C1 0200  
0x01C1 0204  
0x01C1 0300  
0x01C1 0304  
0x01C1 0400  
0x01C1 0404  
0x01C1 0800  
0x01C1 0804  
0x01C1 0808  
0x01C1 080C  
0x01C1 0810  
0x01C1 0814  
0x01C1 0818  
0x01C1 081C  
0x01C1 0820  
0x01C1 0824  
0x01C1 0828  
0x01C1 082C  
0x01C1 0830  
0x01C1 0834  
0x01E2 7060  
0x01E2 7068  
0x01E2 7120  
0x01E2 7128  
0x01E2 7200  
0x01E2 7204  
0x01E2 7300  
0x01E2 7304  
0x01E2 7400  
0x01E2 7404  
0x01E2 7800  
0x01E2 7804  
0x01E2 7808  
0x01E2 780C  
0x01E2 7810  
0x01E2 7814  
0x01E2 7818  
0x01E2 781C  
0x01E2 7820  
0x01E2 7824  
0x01E2 7828  
0x01E2 782C  
0x01E2 7830  
0x01E2 7834  
PERRPR  
PERRCR  
PTCMD  
Power Error Clear Register  
Power Domain Transition Command Register  
Power Domain Transition Status Register  
Power Domain 0 Status Register  
Power Domain 1 Status Register  
Power Domain 0 Control Register  
Power Domain 1 Control Register  
Power Domain 0 Configuration Register  
Power Domain 1 Configuration Register  
Module 0 Status Register  
PTSTAT  
PDSTAT0  
PDSTAT1  
PDCTL0  
PDCTL1  
PDCFG0  
PDCFG1  
MDSTAT0  
MDSTAT1  
MDSTAT2  
MDSTAT3  
MDSTAT4  
MDSTAT5  
MDSTAT6  
MDSTAT7  
MDSTAT8  
MDSTAT9  
MDSTAT10  
MDSTAT11  
MDSTAT12  
MDSTAT13  
Module 1 Status Register  
Module 2 Status Register  
Module 3 Status Register  
Module 4 Status Register  
Module 5 Status Register  
Module 6 Status Register  
Module 7 Status Register  
Module 8 Status Register  
Module 9 Status Register  
Module 10 Status Register  
Module 11 Status Register  
Module 12 Status Register  
Module 13 Status Register  
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Table 4-8. Power and Sleep Controller (PSC) Registers (continued)  
PSC0 BYTE  
ADDRESS  
PSC1 BYTE  
ACRONYM  
REGISTER DESCRIPTION  
ADDRESS  
0x01E2 7838  
0x01E2 783C  
0x01E2 7840  
0x01E2 7844  
0x01E2 7848  
0x01E2 784C  
0x01E2 7850  
0x01E2 7854  
0x01E2 7858  
0x01E2 785C  
0x01E2 7860  
0x01E2 7864  
0x01E2 7868  
0x01E2 786C  
0x01E2 7870  
0x01E2 7874  
0x01E2 7878  
0x01E2 787C  
0x01E2 7A00  
0x01E2 7A04  
0x01E2 7A08  
0x01E2 7A0C  
0x01E2 7A10  
0x01E2 7A14  
0x01E2 7A18  
0x01E2 7A1C  
0x01E2 7A20  
0x01E2 7A24  
0x01E2 7A28  
0x01E2 7A2C  
0x01E2 7A30  
0x01E2 7A34  
0x01E2 7A38  
0x01E2 7A3C  
0x01E2 7A40  
0x01E2 7A44  
0x01E2 7A48  
0x01E2 7A4C  
0x01E2 7A50  
0x01E2 7A54  
0x01E2 7A58  
0x01E2 7A5C  
0x01E2 7A60  
0x01E2 7A64  
0x01E2 7A68  
0x01E2 7A6C  
0x01E2 7A70  
0x01C1 0838  
MDSTAT14  
MDSTAT15  
MDSTAT16  
MDSTAT17  
MDSTAT18  
MDSTAT19  
MDSTAT20  
MDSTAT21  
MDSTAT22  
MDSTAT23  
MDSTAT24  
MDSTAT25  
MDSTAT26  
MDSTAT27  
MDSTAT28  
MDSTAT29  
MDSTAT30  
MDSTAT31  
MDCTL0  
Module 14 Status Register  
Module 15 Status Register  
Module 16 Status Register  
Module 17 Status Register  
Module 18 Status Register  
Module 19 Status Register  
Module 20 Status Register  
Module 21 Status Register  
Module 22 Status Register  
Module 23 Status Register  
Module 24 Status Register  
Module 25 Status Register  
Module 26 Status Register  
Module 27 Status Register  
Module 28 Status Register  
Module 29 Status Register  
Module 30 Status Register  
Module 31 Status Register  
Module 0 Control Register  
Module 1 Control Register  
Module 2 Control Register  
Module 3 Control Register  
Module 4 Control Register  
Module 5 Control Register  
Module 6 Control Register  
Module 7 Control Register  
Module 8 Control Register  
Module 9 Control Register  
Module 10 Control Register  
Module 11 Control Register  
Module 12 Control Register  
Module 13 Control Register  
Module 14 Control Register  
Module 15 Control Register  
Module 16 Control Register  
Module 17 Control Register  
Module 18 Control Register  
Module 19 Control Register  
Module 20 Control Register  
Module 21 Control Register  
Module 22 Control Register  
Module 23 Control Register  
Module 24 Control Register  
Module 25 Control Register  
Module 26 Control Register  
Module 27 Control Register  
Module 28 Control Register  
0x01C1 083C  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0x01C1 0A00  
0x01C1 0A04  
MDCTL1  
0x01C1 0A08  
MDCTL2  
0x01C1 0A0C  
MDCTL3  
0x01C1 0A10  
MDCTL4  
0x01C1 0A14  
MDCTL5  
0x01C1 0A18  
MDCTL6  
0x01C1 0A1C  
MDCTL7  
0x01C1 0A20  
MDCTL8  
0x01C1 0A24  
MDCTL9  
0x01C1 0A28  
MDCTL10  
MDCTL11  
MDCTL12  
MDCTL13  
MDCTL14  
MDCTL15  
MDCTL16  
MDCTL17  
MDCTL18  
MDCTL19  
MDCTL20  
MDCTL21  
MDCTL22  
MDCTL23  
MDCTL24  
MDCTL25  
MDCTL26  
MDCTL27  
MDCTL28  
0x01C1 0A2C  
0x01C1 0A30  
0x01C1 0A34  
0x01C1 0A38  
0x01C1 0A3C  
-
-
-
-
-
-
-
-
-
-
-
-
-
70  
Specifications  
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Table 4-8. Power and Sleep Controller (PSC) Registers (continued)  
PSC0 BYTE  
ADDRESS  
PSC1 BYTE  
ACRONYM  
REGISTER DESCRIPTION  
ADDRESS  
0x01E2 7A74  
0x01E2 7A78  
0x01E2 7A7C  
-
-
-
MDCTL29  
MDCTL30  
MDCTL31  
Module 29 Control Register  
Module 30 Control Register  
Module 31 Control Register  
4.7.6.1.1 Power Domain and Module Topology  
The device includes two PSC modules.  
Each PSC module controls clock states for several of the on chip modules, controllers and interconnect  
components. Table 4-9 and Table 4-10 lists the set of peripherals/modules that are controlled by the PSC,  
the power domain they are associated with, the LPSC assignment and the default (power-on reset)  
module states. The module states and terminology are defined in Section 4.7.6.1.1.2.  
Table 4-9. PSC0 Default Module Configuration  
LPSC  
Module Name  
Power Domain  
Default Module State  
Auto Sleep/Wake Only  
Number  
0
1
EDMA3 Channel Controller 0  
AlwaysON (PD0)  
AlwaysON (PD0)  
AlwaysON (PD0)  
AlwaysON (PD0)  
AlwaysON (PD0)  
AlwaysON (PD0)  
—
SwRstDisable  
SwRstDisable  
SwRstDisable  
SwRstDisable  
SwRstDisable  
SwRstDisable  
—
—
—
EDMA3 Transfer Controller 0  
2
EDMA3 Transfer Controller 1  
—
3
EMIFA (Br7)  
—
4
SPI 0  
—
5
MMC/SD 0  
—
6
—
—
7
—
—
—
—
8
—
—
—
—
9
UART 0  
AlwaysON (PD0)  
AlwaysON (PD0)  
AlwaysON (PD0)  
AlwaysON (PD0)  
AlwaysON (PD0)  
—
SwRstDisable  
Enable  
—
10  
11  
12  
13  
14  
15  
SCR0 (Br 0, Br 1, Br 2, Br 8)  
Yes  
Yes  
Yes  
—
SCR1 (Br 4)  
Enable  
SCR2 (Br 3, Br 5, Br 6)  
Enable  
PRUSS  
—
SwRstDisable  
—
—
DSP  
PD_DSP (PD1)  
Enable  
—
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Table 4-10. PSC1 Default Module Configuration  
LPSC  
Module Name  
Power Domain  
Default Module State  
Auto Sleep/Wake Only  
Number  
0
EDMA3 Channel Controller 1  
USB0 (USB2.0)  
USB1 (USB1.1)  
GPIO  
AlwaysON (PD0)  
AlwaysON (PD0)  
AlwaysON (PD0)  
AlwaysON (PD0)  
AlwaysON (PD0)  
AlwaysON (PD0)  
AlwaysON (PD0)  
AlwaysON (PD0)  
AlwaysON (PD0)  
AlwaysON (PD0)  
AlwaysON (PD0)  
AlwaysON (PD0)  
AlwaysON (PD0)  
AlwaysON (PD0)  
AlwaysON (PD0)  
AlwaysON (PD0)  
AlwaysON (PD0)  
AlwaysON (PD0)  
AlwaysON (PD0)  
AlwaysON (PD0)  
AlwaysON (PD0)  
AlwaysON (PD0)  
—
SwRstDisable  
SwRstDisable  
SwRstDisable  
SwRstDisable  
SwRstDisable  
SwRstDisable  
SwRstDisable  
SwRstDisable  
SwRstDisable  
SwRstDisable  
SwRstDisable  
SwRstDisable  
SwRstDisable  
SwRstDisable  
SwRstDisable  
SwRstDisable  
SwRstDisable  
SwRstDisable  
SwRstDisable  
SwRstDisable  
SwRstDisable  
SwRstDisable  
—
—
—
1
2
—
3
—
4
UHPI  
—
5
EMAC  
—
6
DDR2 (and SCR_F3)  
McASP0 ( + McASP0 FIFO)  
SATA  
—
7
—
8
—
9
VPIF  
—
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
SPI 1  
—
I2C 1  
—
UART 1  
—
UART 2  
—
McBSP0 ( + McBSP0 FIFO)  
McBSP1 ( + McBSP1 FIFO)  
LCDC  
—
—
—
eHRPWM0/1  
—
MMCSD1  
—
uPP  
—
ECAP0/1/2  
—
EDMA3 Transfer Controller 2  
—
—
—
—
—
—
—
SCR_F0 (and bridge F0)  
SCR_F1 (and bridge F1)  
SCR_F2 (and bridge F2)  
SCR_F6 (and bridge F3)  
SCR_F7 (and bridge F4)  
SCR_F8 (and bridge F5)  
Bridge F7 (DDR Controller path)  
AlwaysON (PD0)  
AlwaysON (PD0)  
AlwaysON (PD0)  
AlwaysON (PD0)  
AlwaysON (PD0)  
AlwaysON (PD0)  
AlwaysON (PD0)  
PD_SHRAM  
Enable  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
—
Enable  
Enable  
Enable  
Enable  
Enable  
Enable  
On-chip RAM (including SCR_F4  
and bridge F6)  
Enable  
72  
Specifications  
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4.7.6.1.1.1 Power Domain States  
A power domain can only be in one of the two states: ON or OFF, defined as follows:  
•
•
ON: power to the domain is on  
OFF: power to the domain is off  
For both PSC0 and PSC1, the Always ON domain, or PD0 power domain, is always in the ON state when  
the chip is powered-on. This domain is not programmable to OFF state.  
•
•
On PSC0 PD1/PD_DSP Domain: Controls the sleep state for DSP L1 and L2 Memories  
On PSC1 PD1/PD_SHRAM Domain: Controls the sleep state for the 128K on-chip RAM  
4.7.6.1.1.2 Module States  
The PSC defines several possible states for a module. This states are essentially a combination of the  
module reset asserted or de-asserted and module clock on/enabled or off/disabled. The module states are  
defined in Table 4-11.  
Table 4-11. Module States  
Module State  
Enable  
Module Reset  
De-asserted  
De-asserted  
Module  
Clock  
Module State Definition  
On  
A module in the enable state has its module reset de-asserted and it has its clock on.  
This is the normal operational state for a given module  
Disable  
Off  
A module in the disabled state has its module reset de-asserted and it has its module  
clock off. This state is typically used for disabling a module clock to save power. The  
device is designed in full static CMOS, so when you stop a module clock, it retains the  
module’s state. When the clock is restarted, the module resumes operating from the  
stopping point.  
SyncReset  
Asserted  
Asserted  
On  
Off  
A module state in the SyncReset state has its module reset asserted and it has its  
clock on. Generally, software is not expected to initiate this state  
SwRstDisable  
A module in the SwResetDisable state has its module reset asserted and it has its  
clock disabled. After initial power-on, several modules come up in the SwRstDisable  
state. Generally, software is not expected to initiate this state  
Auto Sleep  
De-asserted  
Off  
A module in the Auto Sleep state also has its module reset de-asserted and its module  
clock disabled, similar to the Disable state. However this is a special state, once a  
module is configured in this state by software, it can “automatically” transition to  
“Enable” state whenever there is an internal read/write request made to it, and after  
servicing the request it will “automatically” transition into the sleep state (with module  
reset re de-asserted and module clock disabled), without any software intervention.  
The transition from sleep to enabled and back to sleep state has some cycle latency  
associated with it. It is not envisioned to use this mode when peripherals are fully  
operational and moving data.  
Auto Wake  
De-asserted  
Off  
A module in the Auto Wake state also has its module reset de-asserted and its module  
clock disabled, similar to the Disable state. However this is a special state, once a  
module is configured in this state by software, it will “automatically” transition to  
“Enable” state whenever there is an internal read/write request made to it, and will  
remain in the “Enabled” state from then on (with module reset re de-asserted and  
module clock on), without any software intervention. The transition from sleep to  
enabled state has some cycle latency associated with it. It is not envisioned to use this  
mode when peripherals are fully operational and moving data.  
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4.7.6.2 Enhanced Direct Memory Access Controller (EDMA3)  
The EDMA3 controller handles all data transfers between memories and the device slave peripherals on  
the device. These data transfers include cache servicing, non-cacheable memory accesses, user-  
programmed data transfers, and host accesses.  
4.7.6.2.1 EDMA3 Channel Synchronization Events  
Each EDMA3 channel controller supports up to 32 channels which service peripherals and memory.  
Table 4-12 lists the source of the EDMA3 synchronization events associated with each of the  
programmable EDMA channels.  
Table 4-12. EDMA Synchronization Events  
EDMA3 Channel Controller 0  
Event  
0
Event Name / Source  
McASP0 Receive  
McASP0 Transmit  
McBSP0 Receive  
McBSP0 Transmit  
McBSP1 Receive  
McBSP1 Transmit  
GPIO Bank 0 Interrupt  
GPIO Bank 1 Interrupt  
UART0 Receive  
Event  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
Event Name / Source  
MMCSD0 Receive  
MMCSD0 Transmit  
SPI1 Receive  
1
2
3
SPI1 Transmit  
4
PRU_EVTOUT6  
PRU_EVTOUT7  
GPIO Bank 2 Interrupt  
GPIO Bank 3 Interrupt  
I2C0 Receive  
5
6
7
8
9
UART0 Transmit  
I2C0 Transmit  
10  
11  
12  
13  
14  
15  
Timer64P0 Event Out 12  
Timer64P0 Event Out 34  
UART1 Receive  
I2C1 Receive  
I2C1 Transmit  
GPIO Bank 4 Interrupt  
GPIO Bank 5 Interrupt  
UART2 Receive  
UART2 Transmit  
UART1 Transmit  
SPI0 Receive  
SPI0 Transmit  
EDMA3 Channel Controller 1  
Event Name / Source  
Event  
0
Event  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
Event Name / Source  
GPIO Bank 6 Interrupt  
GPIO Bank 7 Interrupt  
GPIO Bank 8 Interrupt  
Reserved  
Timer64P2 Compare Event 0  
Timer64P2 Compare Event 1  
Timer64P2 Compare Event 2  
Timer64P2 Compare Event 3  
Timer64P2 Compare Event 4  
Timer64P2 Compare Event 5  
Timer64P2 Compare Event 6  
Timer64P2 Compare Event 7  
Timer64P3 Compare Event 0  
Timer64P3 Compare Event 1  
Timer64P3 Compare Event 2  
Timer64P3 Compare Event 3  
Timer64P3 Compare Event 4  
Timer64P3 Compare Event 5  
Timer64P3 Compare Event 6  
Timer64P3 Compare Event 7  
1
2
3
4
Reserved  
5
Reserved  
6
Reserved  
7
Reserved  
8
Timer64P2 Event Out 12  
Timer64P2 Event Out 34  
Timer64P3 Event Out 12  
Timer64P3 Event Out 34  
MMCSD1 Receive  
MMCSD1 Transmit  
Reserved  
9
10  
11  
12  
13  
14  
15  
Reserved  
74  
Specifications  
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4.7.6.2.2 EDMA3 Peripheral Register Descriptions  
Table 4-13 is the list of EDMA3 Channel Controller Registers and Table 4-14 is the list of EDMA3 Transfer  
Controller registers.  
Table 4-13. EDMA3 Channel Controller (EDMA3CC) Registers  
EDMA3_0 Channel  
Controller 0  
EDMA3_1 Channel  
Controller 0  
ACRONYM  
REGISTER DESCRIPTION  
BYTE ADDRESS  
BYTE ADDRESS  
0x01C0 0000  
0x01C0 0004  
0x01E3 0000  
0x01E3 0004  
PID  
Peripheral Identification Register  
CCCFG  
EDMA3CC Configuration Register  
Global Registers  
0x01C0 0200  
0x01C0 0204  
0x01C0 0208  
0x01C0 020C  
0x01C0 0210  
0x01C0 0214  
0x01C0 0218  
0x01C0 021C  
0x01C0 0240  
0x01C0 0244  
0x01C0 0248  
0x01C0 024C  
0x01C0 0260  
0x01C0 0284  
0x01C0 0300  
0x01C0 0308  
0x01C0 0310  
0x01C0 0314  
0x01C0 0318  
0x01C0 031C  
0x01C0 0320  
0x01C0 0340  
0x01C0 0348  
0x01C0 0350  
0x01C0 0358  
0x01C0 0380  
0x01C0 0384  
0x01C0 0388  
0x01C0 038C  
0x01C0 0400 - 0x01C0 043C  
0x01C0 0440 - 0x01C0 047C  
0x01C0 0600  
0x01C0 0604  
0x01C0 0620  
0x01C0 0640  
0x01E3 0200  
0x01E3 0204  
0x01E3 0208  
0x01E3 020C  
0x01E3 0210  
0x01E3 0214  
0x01E3 0218  
0x01E3 021C  
0x01E3 0240  
0x01E3 0244  
0x01E3 0248  
0x01E3 024C  
0x01E3 0260  
0x01E3 0284  
0x01E3 0300  
0x01E3 0308  
0x01E3 0310  
0x01E3 0314  
0x01E3 0318  
0x01E3 031C  
0x01E3 0320  
0x01E3 0340  
0x01E3 0348  
0x01E3 0350  
0x01E3 0358  
0x01E3 0380  
0x01E3 0384  
0x01E3 0388  
0x01E3 038C  
0x01E3 0400 - 0x01E3 043C  
0x01E3 0440 - 0x01E3 047C  
0x01E3 0600  
0x01E3 0604  
0x01E3 0620  
0x01E3 0640  
QCHMAP0  
QCHMAP1  
QCHMAP2  
QCHMAP3  
QCHMAP4  
QCHMAP5  
QCHMAP6  
QCHMAP7  
QDMA Channel 0 Mapping Register  
QDMA Channel 1 Mapping Register  
QDMA Channel 2 Mapping Register  
QDMA Channel 3 Mapping Register  
QDMA Channel 4 Mapping Register  
QDMA Channel 5 Mapping Register  
QDMA Channel 6 Mapping Register  
QDMA Channel 7 Mapping Register  
DMAQNUM0 DMA Channel Queue Number Register 0  
DMAQNUM1 DMA Channel Queue Number Register 1  
DMAQNUM2 DMA Channel Queue Number Register 2  
DMAQNUM3 DMA Channel Queue Number Register 3  
QDMAQNUM QDMA Channel Queue Number Register  
QUEPRI  
EMR  
Queue Priority Register(1)  
Event Missed Register  
EMCR  
QEMR  
QEMCR  
CCERR  
Event Missed Clear Register  
QDMA Event Missed Register  
QDMA Event Missed Clear Register  
EDMA3CC Error Register  
CCERRCLR EDMA3CC Error Clear Register  
EEVAL  
DRAE0  
DRAE1  
DRAE2  
DRAE3  
QRAE0  
QRAE1  
QRAE2  
QRAE3  
Error Evaluate Register  
DMA Region Access Enable Register for Region 0  
DMA Region Access Enable Register for Region 1  
DMA Region Access Enable Register for Region 2  
DMA Region Access Enable Register for Region 3  
QDMA Region Access Enable Register for Region 0  
QDMA Region Access Enable Register for Region 1  
QDMA Region Access Enable Register for Region 2  
QDMA Region Access Enable Register for Region 3  
Q0E0-Q0E15 Event Queue Entry Registers Q0E0-Q0E15  
Q1E0-Q1E15 Event Queue Entry Registers Q1E0-Q1E15  
QSTAT0  
QSTAT1  
Queue 0 Status Register  
Queue 1 Status Register  
QWMTHRA  
CCSTAT  
Queue Watermark Threshold A Register  
EDMA3CC Status Register  
(1) On previous architectures, the EDMA3TC priority was controlled by the queue priority register (QUEPRI) in the EDMA3CC memory-  
map. However for this device, the priority control for the transfer controllers is controlled by the chip-level registers in the System  
Configuration Module. You should use the chip-level registers and not QUEPRI to configure the TC priority.  
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Table 4-13. EDMA3 Channel Controller (EDMA3CC) Registers (continued)  
EDMA3_0 Channel  
Controller 0  
EDMA3_1 Channel  
Controller 0  
ACRONYM  
REGISTER DESCRIPTION  
BYTE ADDRESS  
BYTE ADDRESS  
Global Channel Registers  
0x01C0 1000  
0x01C0 1008  
0x01C0 1010  
0x01C0 1018  
0x01C0 1020  
0x01C0 1028  
0x01C0 1030  
0x01C0 1038  
0x01C0 1040  
0x01C0 1050  
0x01C0 1058  
0x01C0 1060  
0x01C0 1068  
0x01C0 1070  
0x01C0 1078  
0x01C0 1080  
0x01C0 1084  
0x01C0 1088  
0x01C0 108C  
0x01C0 1090  
0x01C0 1094  
0x01E3 1000  
ER  
ECR  
Event Register  
0x01E3 1008  
0x01E3 1010  
0x01E3 1018  
0x01E3 1020  
0x01E3 1028  
0x01E3 1030  
0x01E3 1038  
0x01E3 1040  
0x01E3 1050  
0x01E3 1058  
0x01E3 1060  
0x01E3 1068  
0x01E3 1070  
0x01E3 1078  
0x01E3 1080  
0x01E3 1084  
0x01E3 1088  
0x01E3 108C  
0x01E3 1090  
0x01E3 1094  
Event Clear Register  
ESR  
Event Set Register  
CER  
Chained Event Register  
EER  
Event Enable Register  
EECR  
EESR  
SER  
Event Enable Clear Register  
Event Enable Set Register  
Secondary Event Register  
Secondary Event Clear Register  
Interrupt Enable Register  
SECR  
IER  
IECR  
IESR  
IPR  
Interrupt Enable Clear Register  
Interrupt Enable Set Register  
Interrupt Pending Register  
Interrupt Clear Register  
ICR  
IEVAL  
QER  
Interrupt Evaluate Register  
QDMA Event Register  
QEER  
QEECR  
QEESR  
QSER  
QSECR  
QDMA Event Enable Register  
QDMA Event Enable Clear Register  
QDMA Event Enable Set Register  
QDMA Secondary Event Register  
QDMA Secondary Event Clear Register  
Shadow Region 0 Channel Registers  
0x01C0 2000  
0x01C0 2008  
0x01C0 2010  
0x01C0 2018  
0x01C0 2020  
0x01C0 2028  
0x01C0 2030  
0x01C0 2038  
0x01C0 2040  
0x01C0 2050  
0x01C0 2058  
0x01C0 2060  
0x01C0 2068  
0x01C0 2070  
0x01C0 2078  
0x01C0 2080  
0x01C0 2084  
0x01C0 2088  
0x01C0 208C  
0x01C0 2090  
0x01C0 2094  
0x01E3 2000  
ER  
ECR  
Event Register  
0x01E3 2008  
0x01E3 2010  
0x01E3 2018  
0x01E3 2020  
0x01E3 2028  
0x01E3 2030  
0x01E3 2038  
0x01E3 2040  
0x01E3 2050  
0x01E3 2058  
0x01E3 2060  
0x01E3 2068  
0x01E3 2070  
0x01E3 2078  
0x01E3 2080  
0x01E3 2084  
0x01E3 2088  
0x01E3 208C  
0x01E3 2090  
0x01E3 2094  
Event Clear Register  
ESR  
Event Set Register  
CER  
Chained Event Register  
EER  
Event Enable Register  
EECR  
EESR  
SER  
Event Enable Clear Register  
Event Enable Set Register  
Secondary Event Register  
Secondary Event Clear Register  
Interrupt Enable Register  
SECR  
IER  
IECR  
IESR  
IPR  
Interrupt Enable Clear Register  
Interrupt Enable Set Register  
Interrupt Pending Register  
Interrupt Clear Register  
ICR  
IEVAL  
QER  
Interrupt Evaluate Register  
QDMA Event Register  
QEER  
QEECR  
QEESR  
QSER  
QSECR  
QDMA Event Enable Register  
QDMA Event Enable Clear Register  
QDMA Event Enable Set Register  
QDMA Secondary Event Register  
QDMA Secondary Event Clear Register  
76  
Specifications  
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Table 4-13. EDMA3 Channel Controller (EDMA3CC) Registers (continued)  
EDMA3_0 Channel  
EDMA3_1 Channel  
Controller 0  
ACRONYM  
REGISTER DESCRIPTION  
Controller 0  
BYTE ADDRESS  
BYTE ADDRESS  
Shadow Region 1 Channel Registers  
0x01C0 2200  
0x01C0 2208  
0x01C0 2210  
0x01C0 2218  
0x01C0 2220  
0x01C0 2228  
0x01C0 2230  
0x01C0 2238  
0x01C0 2240  
0x01C0 2250  
0x01C0 2258  
0x01C0 2260  
0x01C0 2268  
0x01C0 2270  
0x01C0 2278  
0x01C0 2280  
0x01C0 2284  
0x01C0 2288  
0x01C0 228C  
0x01C0 2290  
0x01C0 2294  
0x01C0 4000 - 0x01C0 4FFF  
0x01E3 2200  
ER  
ECR  
Event Register  
Event Clear Register  
0x01E3 2208  
0x01E3 2210  
0x01E3 2218  
0x01E3 2220  
0x01E3 2228  
0x01E3 2230  
0x01E3 2238  
0x01E3 2240  
0x01E3 2250  
0x01E3 2258  
0x01E3 2260  
0x01E3 2268  
0x01E3 2270  
0x01E3 2278  
0x01E3 2280  
0x01E3 2284  
0x01E3 2288  
0x01E3 228C  
0x01E3 2290  
0x01E3 2294  
0x01E3 4000 - 0x01E3 4FFF  
ESR  
Event Set Register  
CER  
Chained Event Register  
Event Enable Register  
Event Enable Clear Register  
Event Enable Set Register  
Secondary Event Register  
EER  
EECR  
EESR  
SER  
SECR  
IER  
Secondary Event Clear Register  
Interrupt Enable Register  
IECR  
IESR  
IPR  
Interrupt Enable Clear Register  
Interrupt Enable Set Register  
Interrupt Pending Register  
ICR  
Interrupt Clear Register  
IEVAL  
QER  
Interrupt Evaluate Register  
QDMA Event Register  
QEER  
QEECR  
QEESR  
QSER  
QSECR  
—
QDMA Event Enable Register  
QDMA Event Enable Clear Register  
QDMA Event Enable Set Register  
QDMA Secondary Event Register  
QDMA Secondary Event Clear Register  
Parameter RAM (PaRAM)  
Table 4-14. EDMA3 Transfer Controller (EDMA3TC) Registers  
EDMA3_0  
Transfer  
EDMA3_0  
Transfer  
EDMA3_1  
Transfer  
ACRONYM  
REGISTER DESCRIPTION  
Controller 0  
BYTE ADDRESS BYTE ADDRESS  
Controller 1  
Controller 0  
BYTE ADDRESS  
0x01C0 8000  
0x01C0 8004  
0x01C0 8100  
0x01C0 8120  
0x01C0 8124  
0x01C0 8128  
0x01C0 812C  
0x01C0 8130  
0x01C0 8140  
0x01C0 8240  
0x01C0 8244  
0x01C0 8248  
0x01C0 824C  
0x01C0 8250  
0x01C0 8254  
0x01C0 8258  
0x01C0 825C  
0x01C0 8260  
0x01C0 8400  
0x01C0 8404  
0x01C0 8500  
0x01C0 8520  
0x01C0 8524  
0x01C0 8528  
0x01C0 852C  
0x01C0 8530  
0x01C0 8540  
0x01C0 8640  
0x01C0 8644  
0x01C0 8648  
0x01C0 864C  
0x01C0 8650  
0x01C0 8654  
0x01C0 8658  
0x01C0 865C  
0x01C0 8660  
0x01E3 8000  
0x01E3 8004  
0x01E3 8100  
0x01E3 8120  
0x01E3 8124  
0x01E3 8128  
0x01E3 812C  
0x01E3 8130  
0x01E3 8140  
0x01E3 8240  
0x01E3 8244  
0x01E3 8248  
0x01E3 824C  
0x01E3 8250  
0x01E3 8254  
0x01E3 8258  
0x01E3 825C  
0x01E3 8260  
PID  
Peripheral Identification Register  
EDMA3TC Configuration Register  
EDMA3TC Channel Status Register  
Error Status Register  
TCCFG  
TCSTAT  
ERRSTAT  
ERREN  
Error Enable Register  
ERRCLR  
ERRDET  
ERRCMD  
RDRATE  
SAOPT  
Error Clear Register  
Error Details Register  
Error Interrupt Command Register  
Read Command Rate Register  
Source Active Options Register  
Source Active Source Address Register  
Source Active Count Register  
Source Active Destination Address Register  
Source Active B-Index Register  
Source Active Memory Protection Proxy Register  
Source Active Count Reload Register  
SASRC  
SACNT  
SADST  
SABIDX  
SAMPPRXY  
SACNTRLD  
SASRCBREF Source Active Source Address B-Reference Register  
SADSTBREF Source Active Destination Address B-Reference Register  
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Table 4-14. EDMA3 Transfer Controller (EDMA3TC) Registers (continued)  
EDMA3_0  
Transfer  
EDMA3_0  
Transfer  
EDMA3_1  
Transfer  
ACRONYM  
REGISTER DESCRIPTION  
Controller 0  
BYTE ADDRESS BYTE ADDRESS  
Controller 1  
Controller 0  
BYTE ADDRESS  
0x01C0 8280  
0x01C0 8284  
0x01C0 8680  
0x01C0 8684  
0x01E3 8280  
0x01E3 8284  
DFCNTRLD  
Destination FIFO Set Count Reload Register  
DFSRCBREF Destination FIFO Set Source Address B-Reference  
Register  
0x01C0 8288  
0x01C0 8688  
0x01E3 8288  
DFDSTBREF Destination FIFO Set Destination Address B-Reference  
Register  
0x01C0 8300  
0x01C0 8304  
0x01C0 8308  
0x01C0 830C  
0x01C0 8310  
0x01C0 8314  
0x01C0 8340  
0x01C0 8344  
0x01C0 8348  
0x01C0 834C  
0x01C0 8350  
0x01C0 8354  
0x01C0 8380  
0x01C0 8384  
0x01C0 8388  
0x01C0 838C  
0x01C0 8390  
0x01C0 8394  
0x01C0 83C0  
0x01C0 83C4  
0x01C0 83C8  
0x01C0 83CC  
0x01C0 83D0  
0x01C0 83D4  
0x01C0 8700  
0x01C0 8704  
0x01C0 8708  
0x01C0 870C  
0x01C0 8710  
0x01C0 8714  
0x01C0 8740  
0x01C0 8744  
0x01C0 8748  
0x01C0 874C  
0x01C0 8750  
0x01C0 8754  
0x01C0 8780  
0x01C0 8784  
0x01C0 8788  
0x01C0 878C  
0x01C0 8790  
0x01C0 8794  
0x01C0 87C0  
0x01C0 87C4  
0x01C0 87C8  
0x01C0 87CC  
0x01C0 87D0  
0x01C0 87D4  
0x01E3 8300  
0x01E3 8304  
0x01E3 8308  
0x01E3 830C  
0x01E3 8310  
0x01E3 8314  
0x01E3 8340  
0x01E3 8344  
0x01E3 8348  
0x01E3 834C  
0x01E3 8350  
0x01E3 8354  
0x01E3 8380  
0x01E3 8384  
0x01E3 8388  
0x01E3 838C  
0x01E3 8390  
0x01E3 8394  
0x01E3 83C0  
0x01E3 83C4  
0x01E3 83C8  
0x01E3 83CC  
0x01E3 83D0  
0x01E3 83D4  
DFOPT0  
DFSRC0  
DFCNT0  
DFDST0  
DFBIDX0  
Destination FIFO Options Register 0  
Destination FIFO Source Address Register 0  
Destination FIFO Count Register 0  
Destination FIFO Destination Address Register 0  
Destination FIFO B-Index Register 0  
DFMPPRXY0 Destination FIFO Memory Protection Proxy Register 0  
DFOPT1  
DFSRC1  
DFCNT1  
DFDST1  
DFBIDX1  
Destination FIFO Options Register 1  
Destination FIFO Source Address Register 1  
Destination FIFO Count Register 1  
Destination FIFO Destination Address Register 1  
Destination FIFO B-Index Register 1  
DFMPPRXY1 Destination FIFO Memory Protection Proxy Register 1  
DFOPT2  
DFSRC2  
DFCNT2  
DFDST2  
DFBIDX2  
Destination FIFO Options Register 2  
Destination FIFO Source Address Register 2  
Destination FIFO Count Register 2  
Destination FIFO Destination Address Register 2  
Destination FIFO B-Index Register 2  
DFMPPRXY2 Destination FIFO Memory Protection Proxy Register 2  
DFOPT3  
DFSRC3  
DFCNT3  
DFDST3  
DFBIDX3  
Destination FIFO Options Register 3  
Destination FIFO Source Address Register 3  
Destination FIFO Count Register 3  
Destination FIFO Destination Address Register 3  
Destination FIFO B-Index Register 3  
DFMPPRXY3 Destination FIFO Memory Protection Proxy Register 3  
Table 4-15 shows an abbreviation of the set of registers which make up the parameter set for each of 128  
EDMA3 events. Each of the parameter register sets consist of 8 32-bit word entries. Table 4-16 shows the  
parameter set entry registers with relative memory address locations within each of the parameter sets.  
Table 4-15. EDMA3 Parameter Set RAM  
EDMA3_0  
EDMA3_1  
Channel Controller 0  
BYTE ADDRESS RANGE  
Channel Controller 0  
BYTE ADDRESS RANGE  
DESCRIPTION  
0x01C0 4000 - 0x01C0 401F  
0x01C0 4020 - 0x01C0 403F  
0x01C0 4040 - 0x01CC0 405F  
0x01C0 4060 - 0x01C0 407F  
0x01C0 4080 - 0x01C0 409F  
0x01C0 40A0 - 0x01C0 40BF  
...  
0x01E3 4000 - 0x01E3 401F  
0x01E3 4020 - 0x01E3 403F  
0x01E3 4040 - 0x01CE3 405F  
0x01E3 4060 - 0x01E3 407F  
0x01E3 4080 - 0x01E3 409F  
0x01E3 40A0 - 0x01E3 40BF  
...  
Parameters Set 0 (8 32-bit words)  
Parameters Set 1 (8 32-bit words)  
Parameters Set 2 (8 32-bit words)  
Parameters Set 3 (8 32-bit words)  
Parameters Set 4 (8 32-bit words)  
Parameters Set 5 (8 32-bit words)  
...  
0x01C0 4FC0 - 0x01C0 4FDF  
0x01C0 4FE0 - 0x01C0 4FFF  
0x01E3 4FC0 - 0x01E3 4FDF  
0x01E3 4FE0 - 0x01E3 4FFF  
Parameters Set 126 (8 32-bit words)  
Parameters Set 127 (8 32-bit words)  
78  
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Table 4-16. Parameter Set Entries  
OFFSET BYTE ADDRESS  
WITHIN THE PARAMETER SET  
ACRONYM  
PARAMETER ENTRY  
0x0000  
0x0004  
0x0008  
0x000C  
0x0010  
0x0014  
0x0018  
0x001C  
OPT  
SRC  
Option  
Source Address  
A_B_CNT  
DST  
A Count, B Count  
Destination Address  
SRC_DST_BIDX  
LINK_BCNTRLD  
SRC_DST_CIDX  
CCNT  
Source B Index, Destination B Index  
Link Address, B Count Reload  
Source C Index, Destination C Index  
C Count  
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4.7.6.3 External Memory Interface A (EMIFA)  
EMIFA is one of two external memory interfaces supported on the device. It is primarily intended to  
support asynchronous memory types, such as NAND and NOR flash and Asynchronous SRAM. However  
on this device, EMIFA also provides a secondary interface to SDRAM.  
4.7.6.3.1 EMIFA Asynchronous Memory Support  
EMIFA supports asynchronous:  
•
•
•
SRAM memories  
NAND Flash memories  
NOR Flash memories  
The EMIFA data bus width is up to 16-bits.The device supports up to 23 address lines and two external  
wait/interrupt inputs. Up to four asynchronous chip selects are supported by EMIFA (EMA_CS[5:2]).  
Each chip select has the following individually programmable attributes:  
•
•
•
•
•
•
•
Data Bus Width  
Read cycle timings: setup, hold, strobe  
Write cycle timings: setup, hold, strobe  
Bus turn around time  
Extended Wait Option With Programmable Timeout  
Select Strobe Option  
NAND flash controller supports 1-bit and 4-bit ECC calculation on blocks of 512 bytes.  
4.7.6.3.2 EMIFA Synchronous DRAM Memory Support  
The device supports 16-bit SDRAM in addition to the asynchronous memories listed in Section 4.7.6.3.1. It  
has a single SDRAM chip select (EMA_CS[0]). SDRAM configurations that are supported are:  
•
•
•
•
One, Two, and Four Bank SDRAM devices  
Devices with Eight, Nine, Ten, and Eleven Column Address  
CAS Latency of two or three clock cycles  
Sixteen Bit Data Bus Width  
Additionally, the SDRAM interface of EMIFA supports placing the SDRAM in Self Refresh and Powerdown  
Modes. Self Refresh mode allows the SDRAM to be put into a low power state while still retaining memory  
contents; since the SDRAM will continue to refresh itself even without clocks from the device. Powerdown  
mode achieves even lower power, except the device must periodically wake the SDRAM up and issue  
refreshes if data retention is required.  
Finally, note that the EMIFA does not support Mobile SDRAM devices.  
Table 4-17 shows the supported SDRAM configurations for EMIFA.  
80  
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Table 4-17. EMIFA Supported SDRAM Configurations(1)  
SDRAM  
Memory  
Data Bus  
Width (bits)  
EMIFA Data  
Bus Size  
(bits)  
Total  
Memory  
(Mbits)  
Total  
Memory  
(Mbytes)  
Memory  
Density  
(Mbits)  
Number of  
Memories  
Rows  
Columns  
Banks  
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
15  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
15  
8
8
1
2
4
1
2
4
1
2
4
1
2
4
1
2
4
1
2
4
1
2
4
1
2
4
256  
512  
32  
256  
512  
64  
8
1024  
512  
128  
64  
1024  
512  
9
9
1024  
2048  
1024  
2048  
4096  
2048  
4096  
4096  
256  
128  
256  
128  
256  
512  
256  
512  
512  
32  
1024  
2048  
1024  
2048  
4096  
2048  
4096  
4096  
128  
16  
9
10  
10  
10  
11  
11  
11  
8
8
512  
64  
256  
8
1024  
512  
128  
64  
512  
9
256  
9
1024  
2048  
1024  
2048  
4096  
2048  
4096  
4096  
128  
256  
128  
256  
512  
256  
512  
512  
512  
8
9
1024  
512  
10  
10  
10  
11  
11  
11  
1024  
2048  
1024  
2048  
2048  
(1) The shaded cells indicate configurations that are possible on the EMIFA interface but as of this writing SDRAM memories capable of  
supporting these densities are not available in the market.  
4.7.6.3.3 EMIFA SDRAM Loading Limitations  
EMIFA supports SDRAM up to 100 MHz with up to two SDRAM or asynchronous memory loads.  
Additional loads will limit the SDRAM operation to lower speeds and the maximum speed should be  
confirmed by board simulation using IBIS models.  
4.7.6.3.4 EMIFA Connection Examples  
Figure 4-11 illustrates an example of how SDRAM, NOR, and NAND flash devices might be connected to  
EMIFA simultaneously. The SDRAM chip select must be EMA_CS[0]. Note that the NOR flash is  
connected to EMA_CS[2] and the NAND flash is connected to EMA_CS[3] in this example. Note that any  
type of asynchronous memory may be connected to EMA_CS[5:2].  
The on-chip bootloader makes some assumptions on which chip select the contains the boot image, and  
this depends on the boot mode. For NOR boot mode; the on-chip bootloader requires that the image be  
stored in NOR flash on EMA_CS[2]. For NAND boot mode, the bootloader requires that the boot image is  
stored in NAND flash on EMA_CS[3]. It is always possible to have the image span multiple chip selects,  
but this must be supported by second stage boot code stored in the external flash.  
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A likely use case with more than one EMIFA chip select used for NAND flash is illustrated in Figure 4-12.  
This figure shows how two multiplane NAND flash devices with two chip selects each would connect to the  
EMIFA. In this case if NAND is the boot memory, then the boot image needs to be stored in the NAND  
area selected by EMA_CS[3]. Part of the application image could spill over into the NAND regions  
selected by other EMIFA chip selects; but would rely on the code stored in the EMA_CS[3] area to  
bootload it.  
EMA_CS[0]  
EMA_CAS  
CE  
CAS  
EMIFA  
EMA_RAS  
RAS  
EMA_WE  
WE  
SDRAM  
2M x 16 x 4  
Bank  
EMA_CLK  
CLK  
EMA_SDCKE  
EMA_BA[1:0]  
EMA_A[12:0]  
CKE  
BA[1:0]  
A[11:0]  
LDQM  
UDQM  
DQ[15:0]  
EMA_WE_DQM[0]  
EMA_WE_DQM[1]  
EMA_D[15:0]  
EMA_CS[2]  
EMA_CS[3]  
EMA_WAIT  
EMA_OE  
A[0]  
A[12:1]  
DQ[15:0]  
CE  
GPIO  
(6 Pins)  
RESET  
NOR  
FLASH  
512K x 16  
WE  
RESET  
OE  
RESET  
A[18:13]  
...  
RY/BY  
EMA_A[1]  
EMA_A[2]  
ALE  
CLE  
DQ[15:0]  
CE  
NAND  
FLASH  
1Gb x 16  
DVDD  
WE  
RE  
RB  
Figure 4-11. Connection Diagram: SDRAM, NOR, NAND  
82  
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EMA_A[1]  
EMA_A[2]  
EMA_D[7:0]  
EMA_CS[2]  
EMA_CS[3]  
EMA_WE  
ALE  
CLE  
DQ[7:0]  
CE1  
CE2  
WE  
NAND  
FLASH  
x8,  
MultiPlane  
EMA_OE  
RE  
EMIFA  
R/B1  
R/B2  
EMA_WAIT  
DVDD  
ALE  
CLE  
DQ[7:0]  
CE1  
CE2  
WE  
NAND  
FLASH  
x8,  
EMA_CS[4]  
EMA_CS[5]  
MultiPlane  
RE  
R/B1  
R/B2  
Figure 4-12. EMIFA Connection Diagram: Multiple NAND Flash Planes  
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4.7.6.3.5 External Memory Interface Register Descriptions  
Table 4-18. External Memory Interface (EMIFA) Registers  
BYTE ADDRESS  
0x6800 0000  
0x6800 0004  
0x6800 0008  
0x6800 000C  
0x6800 0010  
0x6800 0014  
0x6800 0018  
0x6800 001C  
0x6800 0020  
0x6800 003C  
0x6800 0040  
0x6800 0044  
0x6800 0048  
0x6800 004C  
0x6800 0060  
0x6800 0064  
0x6800 0070  
0x6800 0074  
0x6800 0078  
0x6800 007C  
0x6800 00BC  
0x6800 00C0  
0x6800 00C4  
0x6800 00C8  
0x6800 00CC  
0x6800 00D0  
0x6800 00D4  
0x6800 00D8  
0x6800 00DC  
ACRONYM  
MIDR  
REGISTER DESCRIPTION  
Module ID Register  
AWCC  
Asynchronous Wait Cycle Configuration Register  
SDRAM Configuration Register  
SDCR  
SDRCR  
SDRAM Refresh Control Register  
CE2CFG  
Asynchronous 1 Configuration Register  
Asynchronous 2 Configuration Register  
Asynchronous 3 Configuration Register  
Asynchronous 4 Configuration Register  
SDRAM Timing Register  
CE3CFG  
CE4CFG  
CE5CFG  
SDTIMR  
SDSRETR  
SDRAM Self Refresh Exit Timing Register  
EMIFA Interrupt Raw Register  
INTRAW  
INTMSK  
EMIFA Interrupt Mask Register  
INTMSKSET  
INTMSKCLR  
NANDFCR  
EMIFA Interrupt Mask Set Register  
EMIFA Interrupt Mask Clear Register  
NAND Flash Control Register  
NANDFSR  
NAND Flash Status Register  
NANDF1ECC  
NANDF2ECC  
NANDF3ECC  
NANDF4ECC  
NAND4BITECCLOAD  
NAND4BITECC1  
NAND4BITECC2  
NAND4BITECC3  
NAND4BITECC4  
NANDERRADD1  
NANDERRADD2  
NANDERRVAL1  
NANDERRVAL2  
NAND Flash 1 ECC Register (CS2 Space)  
NAND Flash 2 ECC Register (CS3 Space)  
NAND Flash 3 ECC Register (CS4 Space)  
NAND Flash 4 ECC Register (CS5 Space)  
NAND Flash 4-Bit ECC Load Register  
NAND Flash 4-Bit ECC Register 1  
NAND Flash 4-Bit ECC Register 2  
NAND Flash 4-Bit ECC Register 3  
NAND Flash 4-Bit ECC Register 4  
NAND Flash 4-Bit ECC Error Address Register 1  
NAND Flash 4-Bit ECC Error Address Register 2  
NAND Flash 4-Bit ECC Error Value Register 1  
NAND Flash 4-Bit ECC Error Value Register 2  
84  
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4.7.6.3.6 EMIFA Electrical Data/Timing  
Table 4-19 through Table 4-22 assume testing over recommended operating conditions.  
Table 4-19. Timing Requirements for EMIFA SDRAM Interface  
1.3V, 1.2V  
1.1V  
1.0V  
NO.  
UNIT  
MIN MAX MIN MAX MIN MAX  
Input setup time, read data valid on EMA_D[15:0] before  
EMA_CLK rising  
19 tsu(EMA_DV-EM_CLKH)  
20 th(CLKH-DIV)  
2
3
3
ns  
ns  
Input hold time, read data valid on EMA_D[15:0] after  
EMA_CLK rising  
1.6  
1.6  
1.6  
Table 4-20. Switching Characteristics for EMIFA SDRAM Interface  
1.3V, 1.2V  
1.1V  
1.0V  
NO.  
PARAMETER  
UNIT  
MIN MAX MIN MAX MIN MAX  
1
2
3
4
5
tc(CLK)  
Cycle time, EMIF clock EMA_CLK  
10  
3
15  
5
20  
8
ns  
ns  
ns  
ns  
ns  
tw(CLK)  
Pulse width, EMIF clock EMA_CLK high or low  
Delay time, EMA_CLK rising to EMA_CS[0] valid  
Output hold time, EMA_CLK rising to EMA_CS[0] invalid  
Delay time, EMA_CLK rising to EMA_WE_DQM[1:0] valid  
td(CLKH-CSV)  
toh(CLKH-CSIV)  
td(CLKH-DQMV)  
7
7
9.5  
9.5  
13  
13  
1
1
1
1
1
1
Output hold time, EMA_CLK rising to EMA_WE_DQM[1:0]  
invalid  
6
7
toh(CLKH-DQMIV)  
td(CLKH-AV)  
toh(CLKH-AIV)  
td(CLKH-DV)  
ns  
ns  
ns  
Delay time, EMA_CLK rising to EMA_A[12:0] and  
EMA_BA[1:0] valid  
7
9.5  
13  
Output hold time, EMA_CLK rising to EMA_A[12:0] and  
EMA_BA[1:0] invalid  
8
9
1
1
1
Delay time, EMA_CLK rising to EMA_D[15:0] valid  
Output hold time, EMA_CLK rising to EMA_D[15:0] invalid  
Delay time, EMA_CLK rising to EMA_RAS valid  
7
7
7
7
7
9.5  
9.5  
9.5  
9.5  
9.5  
13  
13  
13  
13  
13  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
10 toh(CLKH-DIV)  
11 td(CLKH-RASV)  
12 toh(CLKH-RASIV)  
13 td(CLKH-CASV)  
14 toh(CLKH-CASIV)  
15 td(CLKH-WEV)  
16 toh(CLKH-WEIV)  
17 tdis(CLKH-DHZ)  
18 tena(CLKH-DLZ)  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Output hold time, EMA_CLK rising to EMA_RAS invalid  
Delay time, EMA_CLK rising to EMA_CAS valid  
Output hold time, EMA_CLK rising to EMA_CAS invalid  
Delay time, EMA_CLK rising to EMA_WE valid  
Output hold time, EMA_CLK rising to EMA_WE invalid  
Delay time, EMA_CLK rising to EMA_D[15:0] tri-stated  
Output hold time, EMA_CLK rising to EMA_D[15:0] driving  
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1
BASIC SDRAM  
WRITE OPERATION  
2
2
EMA_CLK  
EMA_CS[0]  
3
5
7
7
9
4
6
EMA_WE_DQM[1:0]  
EMA_BA[1:0]  
8
8
EMA_A[12:0]  
10  
EMA_D[15:0]  
EMA_RAS  
EMA_CAS  
EMA_WE  
11  
12  
13  
15  
16  
Figure 4-13. EMIFA Basic SDRAM Write Operation  
1
BASIC SDRAM  
READ OPERATION  
2
2
EMA_CLK  
EMA_CS[0]  
3
5
7
7
4
6
EMA_WE_DQM[1:0]  
EMA_BA[1:0]  
8
8
EMA_A[12:0]  
19  
20  
2 EM_CLK Delay  
17  
18  
EMA_D[15:0]  
EMA_RAS  
11  
12  
13  
14  
EMA_CAS  
EMA_WE  
Figure 4-14. EMIFA Basic SDRAM Read Operation  
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(1)  
Table 4-21. Timing Requirements for EMIFA Asynchronous Memory Interface  
1.3V, 1.2V  
1.1V  
MIN MAX  
1.0V  
MIN MAX  
NO.  
UNIT  
MIN  
MAX  
READS and WRITES  
Cycle time, EMIFA module clock  
E
2
tc(CLK)  
6.75  
2E  
13.33  
2E  
20  
2E  
ns  
ns  
tw(EM_WAIT)  
Pulse duration, EM_WAIT assertion and deassertion  
READS  
12 tsu(EMDV-EMOEH)  
13 th(EMOEH-EMDIV)  
tsu (EMOEL-  
Setup time, EM_D[15:0] valid before EM_OE high  
Hold time, EM_D[15:0] valid after EM_OE high  
3
0
5
0
7
0
ns  
ns  
Setup Time, EM_WAIT asserted before end of Strobe  
Phase(2)  
14  
4E+3  
4E+3  
4E+3  
ns  
EMWAIT)  
WRITES  
tsu (EMWEL-  
EMWAIT)  
Setup Time, EM_WAIT asserted before end of Strobe  
Phase(2)  
28  
4E+3  
4E+3  
4E+3  
ns  
(1) E = EMA_CLK period or in ns. EMA_CLK is selected either as SYSCLK3 or the PLL0 output clock divided by 4.5. As an example, when  
SYSCLK3 is selected and set to 100MHz, E=10ns  
(2) Setup before end of STROBE phase (if no extended wait states are inserted) by which EM_WAIT must be asserted to add extended  
wait states. Figure 4-17 and Figure 4-18 describe EMIF transactions that include extended wait states inserted during the STROBE  
phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where  
the HOLD phase would begin if there were no extended wait cycles.  
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(1) (2) (3)  
Table 4-22. Switching Characteristics for EMIFA Asynchronous Memory Interface  
1.3V, 1.2V, 1.1V, 1.0V  
Nom  
NO.  
PARAMETER  
UNIT  
MIN  
MAX  
READS and WRITES  
READS  
1
td(TURNAROUND)  
Turn around time  
(TA)*E - 3  
(TA)*E  
(TA)*E + 3  
ns  
EMIF read cycle time (EW = 0)  
(RS+RST+RH)*E - 3  
(RS+RST+RH)*E  
(RS+RST+RH)*E + 3  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
3
4
5
tc(EMRCYCLE)  
EMIF read cycle time (EW = 1)  
(RS+RST+RH+EWC)*E - 3  
(RS)*E-3  
-3  
(RS+RST+RH+EWC)*E (RS+RST+RH+EWC)*E + 3  
Output setup time, EMA_CE[5:2] low to EMA_OE low (SS = 0)  
Output setup time, EMA_CE[5:2] low to EMA_OE low (SS = 1)  
Output hold time, EMA_OE high to EMA_CE[5:2] high (SS = 0)  
Output hold time, EMA_OE high to EMA_CE[5:2] high (SS = 1)  
Output setup time, EMA_BA[1:0] valid to EMA_OE low  
Output hold time, EMA_OE high to EMA_BA[1:0] invalid  
Output setup time, EMA_A[13:0] valid to EMA_OE low  
Output hold time, EMA_OE high to EMA_A[13:0] invalid  
EMA_OE active low width (EW = 0)  
(RS)*E  
0
(RS)*E+3  
+3  
tsu(EMCEL-EMOEL)  
(RH)*E - 3  
-3  
(RH)*E  
0
(RH)*E + 3  
+3  
th(EMOEH-EMCEH)  
6
7
8
9
tsu(EMBAV-EMOEL)  
th(EMOEH-EMBAIV)  
tsu(EMBAV-EMOEL)  
th(EMOEH-EMAIV)  
(RS)*E-3  
(RH)*E-3  
(RS)*E-3  
(RH)*E-3  
(RST)*E-3  
(RST+EWC)*E-3  
3E-3  
(RS)*E  
(RH)*E  
(RS)*E  
(RH)*E  
(RST)*E  
(RST+EWC)*E  
4E  
(RS)*E+3  
(RH)*E+3  
(RS)*E+3  
(RH)*E+3  
(RST)*E+3  
(RST+EWC)*E+3  
4E+3  
10  
tw(EMOEL)  
EMA_OE active low width (EW = 1)  
11  
28  
29  
td(EMWAITH-EMOEH)  
tsu(EMARW-EMOEL)  
th(EMOEH-EMARW)  
Delay time from EMA_WAIT deasserted to EMA_OE high  
Output setup time, EMA_A_RW valid to EMA_OE low  
Output hold time, EMA_OE high to EMA_A_RW invalid  
(RS)*E-3  
(RH)*E-3  
(RS)*E  
(RH)*E  
(RS)*E+3  
(RH)*E+3  
WRITES  
EMIF write cycle time (EW = 0)  
EMIF write cycle time (EW = 1)  
(WS+WST+WH)*E-3  
(WS+WST+WH)*E  
(WS+WST+WH)*E+3  
ns  
ns  
15  
tc(EMWCYCLE)  
(WS+WST+WH+EWC)*E +  
3
(WS+WST+WH+EWC)*E - 3  
(WS+WST+WH+EWC)*E  
Output setup time, EMA_CE[5:2] low to EMA_WE low (SS = 0)  
Output setup time, EMA_CE[5:2] low to EMA_WE low (SS = 1)  
Output hold time, EMA_WE high to EMA_CE[5:2] high (SS = 0)  
Output hold time, EMA_WE high to EMA_CE[5:2] high (SS = 1)  
Output setup time, EMA_BA[1:0] valid to EMA_WE low  
Output hold time, EMA_WE high to EMA_BA[1:0] invalid  
Output setup time, EMA_BA[1:0] valid to EMA_WE low  
Output hold time, EMA_WE high to EMA_BA[1:0] invalid  
(WS)*E - 3  
-3  
(WS)*E  
0
(WS)*E + 3  
+3  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
16  
17  
tsu(EMCEL-EMWEL)  
(WH)*E-3  
-3  
(WH)*E  
0
(WH)*E+3  
+3  
th(EMWEH-EMCEH)  
18  
19  
20  
21  
tsu(EMDQMV-EMWEL)  
th(EMWEH-EMDQMIV)  
tsu(EMBAV-EMWEL)  
th(EMWEH-EMBAIV)  
(WS)*E-3  
(WH)*E-3  
(WS)*E-3  
(WH)*E-3  
(WS)*E  
(WH)*E  
(WS)*E  
(WH)*E  
(WS)*E+3  
(WH)*E+3  
(WS)*E+3  
(WH)*E+3  
(1) TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold, MEWC = Maximum external wait cycles. These  
parameters are programmed via the Asynchronous Bank and Asynchronous Wait Cycle Configuration Registers. These support the following range of values: TA[4-1], RS[16-1], RST[64-  
1], RH[8-1], WS[16-1], WST[64-1], WH[8-1], and MEW[1-256].  
(2) E = EMA_CLK period or in ns. EMA_CLK is selected either as SYSCLK3 or the PLL0 output clock divided by 4.5. As an example, when SYSCLK3 is selected and set to 100MHz,  
E=10ns.  
(3) EWC = external wait cycles determined by EMA_WAIT input signal. EWC supports the following range of values EWC[256-1]. Note that the maximum wait time before timeout is specified  
by bit field MEWC in the Asynchronous Wait Cycle Configuration Register.  
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Table 4-22. Switching Characteristics for EMIFA Asynchronous Memory Interface (1) (2) (3) (continued)  
1.3V, 1.2V, 1.1V, 1.0V  
Nom  
NO.  
PARAMETER  
UNIT  
MAX  
MIN  
22  
23  
tsu(EMAV-EMWEL)  
th(EMWEH-EMAIV)  
Output setup time, EMA_A[13:0] valid to EMA_WE low  
Output hold time, EMA_WE high to EMA_A[13:0] invalid  
EMA_WE active low width (EW = 0)  
(WS)*E-3  
(WH)*E-3  
(WST)*E-3  
(WS)*E  
(WH)*E  
(WS)*E+3  
(WH)*E+3  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
(WST)*E  
(WST)*E+3  
(WST+EWC)*E+3  
4E+3  
24  
tw(EMWEL)  
EMA_WE active low width (EW = 1)  
(WST+EWC)*E-3  
3E-3  
(WST+EWC)*E  
4E  
25  
26  
27  
30  
31  
td(EMWAITH-EMWEH)  
tsu(EMDV-EMWEL)  
th(EMWEH-EMDIV)  
tsu(EMARW-EMWEL)  
th(EMWEH-EMARW)  
Delay time from EMA_WAIT deasserted to EMA_WE high  
Output setup time, EMA_D[15:0] valid to EMA_WE low  
Output hold time, EMA_WE high to EMA_D[15:0] invalid  
Output setup time, EMA_A_RW valid to EMA_WE low  
Output hold time, EMA_WE high to EMA_A_RW invalid  
(WS)*E-3  
(WH)*E-3  
(WS)*E-3  
(WH)*E-3  
(WS)*E  
(WH)*E  
(WS)*E  
(WH)*E  
(WS)*E+3  
(WH)*E+3  
(WS)*E+3  
(WH)*E+3  
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STROBE  
3
SETUP  
HOLD  
1
EMA_CS[5:2]  
EMA_BA[1:0]  
EMA_A[22:0]  
EMA_WE_DQM[1:0]  
EMA_A_RW  
1
4
8
5
9
6
7
29  
28  
10  
EMA_OE  
13  
12  
EMA_D[15:0]  
EMA_WE  
Figure 4-15. Asynchronous Memory Read Timing for EMIFA  
SETUP  
STROBE  
15  
HOLD  
1
EMA_CS[5:2]  
EMA_BA[1:0]  
EMA_A[22:0]  
EMA_WE_DQM[1:0]  
EMA_A_RW  
16  
18  
20  
17  
19  
21  
1
22  
30  
23  
31  
24  
EMA_WE  
26  
27  
EMA_D[15:0]  
EMA_OE  
Figure 4-16. Asynchronous Memory Write Timing for EMIFA  
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SETUP  
STROBE  
Extended Due to EMA_WAIT  
STROBE HOLD  
EMA_CS[5:2]  
EMA_BA[1:0]  
EMA_A[22:0]  
EMA_D[15:0]  
EMA_A_RW  
14  
11  
EMA_OE  
2
2
EMA_WAIT  
Asserted  
Deasserted  
Figure 4-17. EMA_WAIT Read Timing Requirements  
EMA_CS[5:2]  
EMA_BA[1:0]  
EMA_A[22:0]  
EMA_D[15:0]  
EMA_A_RW  
EMA_WE  
EMA_WAIT  
Figure 4-18. EMA_WAIT Write Timing Requirements  
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4.7.6.4 DDR2/mDDR Memory Controller  
The DDR2/mDDR Memory Controller is a dedicated interface to DDR2/mDDR SDRAM. It supports  
JESD79-2A standard compliant DDR2 SDRAM devices and compliant Mobile DDR SDRAM devices.  
The DDR2/mDDR Memory Controller support the following features:  
•
•
•
•
•
JESD79-2A standard compliant DDR2 SDRAM  
Mobile DDR SDRAM  
256 MByte memory space for DDR2  
256 MByte memory space for mDDR  
CAS latencies:  
–
–
DDR2: 2, 3, 4 and 5  
mDDR: 2 and 3  
•
Internal banks:  
–
–
DDR2: 1, 2, 4 and 8  
mDDR:1, 2 and 4  
•
•
•
•
•
•
•
•
•
•
•
•
Burst length: 8  
Burst type: sequential  
1 chip select (CS) signal  
Page sizes: 256, 512, 1024, and 2048  
SDRAM autoinitialization  
Self-refresh mode  
Partial array self-refresh (for mDDR)  
Power down mode  
Prioritized refresh  
Programmable refresh rate and backlog counter  
Programmable timing parameters  
Little endian  
4.7.6.4.1 DDR2/mDDR Memory Controller Electrical Data/Timing  
Table 4-23. Switching Characteristics Over Recommended Operating Conditions for DDR2/mDDR  
Memory Controller  
No.  
PARAMETER  
1.3V, 1.2V  
1.1V  
1.0V  
UNIT  
MIN  
MAX  
156  
MIN  
125  
100  
MAX  
150  
MIN  
MAX  
(1)  
(1)  
DDR2  
125  
105  
—
—
Cycle time,  
DDR_CLKP / DDR_CLKN  
1
tc(DDR_CLK)  
MHz  
mDDR  
150  
133  
95  
133  
(1) DDR2 is not supported at this voltage operating point.  
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4.7.6.4.2 DDR2/mDDR Memory Controller Register Description(s)  
Table 4-24. DDR2/mDDR Memory Controller Registers  
BYTE ADDRESS  
0xB000 0000  
0xB000 0004  
0xB000 0008  
0xB000 000C  
0xB000 0010  
0xB000 0014  
0xB000 001C  
0xB000 0020  
0xB000 0040  
0xB000 0044  
0xB000 0048  
0xB000 004C  
0xB000 0050  
0xB000 00C0  
0xB000 00C4  
0xB000 00C8  
0xB000 00CC  
0xB000 00E4  
0x01E2 C000  
ACRONYM  
REVID  
REGISTER DESCRIPTION  
Revision ID Register  
SDRSTAT  
SDCR  
SDRAM Status Register  
SDRAM Configuration Register  
SDRAM Refresh Control Register  
SDRAM Timing Register 1  
SDRCR  
SDTIMR1  
SDTIMR2  
SDCR2  
PBBPR  
PC1  
SDRAM Timing Register 2  
SDRAM Configuration Register 2  
Peripheral Bus Burst Priority Register  
Performance Counter 1 Registers  
Performance Counter 2 Register  
Performance Counter Configuration Register  
Performance Counter Master Region Select Register  
Performance Counter Time Register  
Interrupt Raw Register  
PC2  
PCC  
PCMRS  
PCT  
IRR  
IMR  
Interrupt Mask Register  
IMSR  
Interrupt Mask Set Register  
IMCR  
Interrupt Mask Clear Register  
DDR PHY Control Register 1  
DRPYC1R  
VTPIO_CTL  
VTP IO Control Register  
4.7.6.4.3 DDR2/mDDR Interface  
This section provides the timing specification for the DDR2/mDDR interface as a PCB design and  
manufacturing specification. The design rules constrain PCB trace length, PCB trace skew, signal  
integrity, cross-talk, and signal timing. These rules, when followed, result in a reliable DDR2/mDDR  
memory system without the need for a complex timing closure process. For more information regarding  
guidelines for using this DDR2/mDDR specification, Understanding TI's PCB Routing Rule-Based DDR2  
Timing Specification (SPRAAV0).  
4.7.6.4.3.1 DDR2/mDDR Interface Schematic  
Figure 4-19 shows the DDR2/mDDR interface schematic for a single-memory DDR2/mDDR system. The  
dual-memory system shown in Figure 4-20. Pin numbers for the device can be obtained from the pin  
description section.  
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DDR2/mDDR Memory Controller  
DDR2/mDDR  
ODT  
DQ0  
DDR_D[0]  
DDR_D[7]  
T
T
DQ7  
DDR_DQM[0]  
DDR_DQS[0]  
T
T
LDM  
LDQS  
NC  
LDQS  
DQ8  
DDR_D[8]  
T
DDR_D[15]  
T
DQ15  
DDR_DQM[1]  
DDR_DQS[1]  
T
T
UDM  
UDQS  
UDQS  
BA0  
NC  
DDR_BA[0]  
T
DDR_BA[2]  
DDR_A[0]  
T
T
BA2  
A0  
DDR_A[13]  
DDR_CS  
T
T
T
T
T
T
T
T
A13  
CS  
DDR_CAS  
DDR_RAS  
DDR_WE  
CAS  
RAS  
WE  
CKE  
CK  
DDR_CKE  
DDR_CLKP  
DDR_CLKN  
CK  
DDR_ZP  
(1)  
DDR_DVDD18  
DDR_DQGATE0  
DDR_DQGATE1  
T
T
VREF(3)  
0.1 μF  
0.1 μF  
1 K Ω 1%  
DDR_VREF  
VREF  
0.1 μF(2)  
0.1 μF(2)  
0.1 μF(2)  
1 K Ω 1%  
T
Terminator, if desired. See terminator comments.  
(1) See Figure 4-26 for DQGATE routing specifications.  
(2) For DDR2, one of these capacitors can be eliminated if the divider and its capacitors are placed near a device VREF pin. For mDDR,  
these capacitors can be eliminated completely.  
(3) VREF applies in the case of DDR2 memories. For mDDR, the DDR_VREF pin still needs to be connected to the divider circuit.  
Figure 4-19. DDR2/mDDR Single-Memory High Level Schematic  
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DDR2/mDDR Memory Controller  
ODT  
DDR_D[0:7]  
T
DQ0 - DQ7  
BA0-BA2  
A0-A13  
DDR_DQM[0]  
DDR_DQS[0]  
T
T
DM  
DQS  
DQS  
NC  
CK  
CK  
CS  
CAS  
RAS  
WE  
CKE  
VREF  
DDR_BA[0:2]  
DDR_A[0:13]  
T
T
BA0-BA2  
A0-A13  
DDR_CLKP  
DDR_CLKN  
DDR_CS  
T
T
T
T
T
T
T
CK  
CK  
CS  
DDR_CAS  
DDR_RAS  
DDR_WE  
CAS  
RAS  
WE  
CKE  
DDR_CKE  
DDR_DQM1  
DDR_DQS1  
T
T
DM  
DQS  
DQS  
NC  
DDR_D[8:15]  
T
DQ0 - DQ7  
DDR_DVDD18  
DDR_ZP  
ODT  
(1)  
DDR_DQGATE0  
T
T
VREF(3)  
DDR_DQGATE1  
0.1 μF  
1 K Ω 1%  
DDR_VREF  
VREF  
0.1 μF(2)  
0.1 μF(2)  
0.1 μF(2)  
1 K Ω 1%  
0.1 μF  
T
Terminator, if desired. See terminator comments.  
(1) See Figure 4-26 for DQGATE routing specifications.  
(2) For DDR2, one of these capacitors can be eliminated if the divider and its capacitors are placed near a device VREF pin. For mDDR,  
these capacitors can be eliminated completely.  
(3) VREF applies in the case of DDR2 memories. For mDDR, the DDR_VREF pin still needs to be connected to the divider circuit.  
Figure 4-20. DDR2/mDDR Dual-Memory High Level Schematic  
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4.7.6.4.3.2 Compatible JEDEC DDR2/mDDR Devices  
Table 4-25 shows the parameters of the JEDEC DDR2/mDDR devices that are compatible with this  
interface. Generally, the DDR2/mDDR interface is compatible with x16 DDR2-400/mDDR-200 speed  
grade DDR2/mDDR devices.  
The device also supports JEDEC DDR2/mDDR x8 devices in the dual chip configuration. In this case, one  
chip supplies the upper byte and the second chip supplies the lower byte. Addresses and most control  
signals are shared just like regular dual chip memory configurations.  
Table 4-25. Compatible JEDEC DDR2/mDDR Devices  
NO. PARAMETER  
MIN  
MAX  
UNIT  
1
JEDEC DDR2/mDDR Device Speed Grade(1)  
DDR2-400/mDDR-  
200  
2
3
JEDEC DDR2/mDDR Device Bit Width  
JEDEC DDR2/mDDR Device Count(2)  
x8  
1
x16  
2
Bits  
Devices  
(1) Higher DDR2/mDDR speed grades are supported due to inherent JEDEC DDR2/mDDR backwards compatibility.  
(2) Supported configurations are one 16-bit DDR2/mDDR memory or two 8-bit DDR2/mDDR memories  
4.7.6.4.3.3 PCB Stackup  
The minimum stackup required for routing the device is a six layer stack as shown in Table 4-26.  
Additional layers may be added to the PCB stack up to accommodate other circuitry or to reduce the size  
of the PCB footprint.Complete stack up specifications are provided in Table 4-27.  
Table 4-26. Device Minimum PCB Stack Up  
LAYER  
TYPE  
Signal  
Plane  
Plane  
Signal  
Plane  
Signal  
DESCRIPTION  
Top Routing Mostly Horizontal  
Ground  
1
2
3
4
5
6
Power  
Internal Routing  
Ground  
Bottom Routing Mostly Vertical  
Table 4-27. PCB Stack Up Specifications  
NO. PARAMETER  
MIN  
6
TYP  
MAX  
UNIT  
1
2
PCB Routing/Plane Layers  
Signal Routing Layers  
3
3
Full ground layers under DDR2/mDDR routing region  
Number of ground plane cuts allowed within DDR routing region  
Number of ground reference planes required for each DDR2/mDDR routing layer  
Number of layers between DDR2/mDDR routing layer and reference ground plane  
PCB Routing Feature Size  
2
4
0
0
5
1
6
7
4
4
Mils  
Mils  
Mils  
Mils  
8
PCB Trace Width w  
8
PCB BGA escape via pad size  
18  
8
9
PCB BGA escape via hole size  
10  
11  
12  
13  
Device BGA pad size(1)  
DDR2/mDDR Device BGA pad size(2)  
Single Ended Impedance, Zo  
Impedance Control(3)  
50  
75  
Ω
Ω
Z-5  
Z
Z+5  
(1) Please refer to the Flip Chip Ball Grid Array Package Reference Guide (SPRU811) for device BGA pad size.  
(2) Please refer to the DDR2/mDDR device manufacturer documentation for the DDR2/mDDR device BGA pad size.  
(3) Z is the nominal singled ended impedance selected for the PCB specified by item 12.  
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4.7.6.4.3.4 Placement  
Figure 4-20 shows the required placement for the device as well as the DDR2/mDDR devices. The  
dimensions for Figure 4-21 are defined in Table 4-28. The placement does not restrict the side of the PCB  
that the devices are mounted on. The ultimate purpose of the placement is to limit the maximum trace  
lengths and allow for proper routing space. For single-memory DDR2/mDDR systems, the second  
DDR2/mDDR device is omitted from the placement.  
X
A1  
Y
OFFSET  
DDR2/mDDR  
Y
Device  
Y
OFFSET  
A1  
Recommended DDR2/mDDR  
Device Orientation  
Figure 4-21. C6748 and DDR2/mDDR Device Placement  
Table 4-28. Placement Specifications(1)(2)  
NO. PARAMETER  
MIN  
MAX  
1750  
1280  
(3)650  
UNIT  
Mils  
Mils  
Mils  
w(5)  
1
2
3
4
X
Y
Y Offset  
Clearance from non-DDR2/mDDR signal to DDR2/mDDR Keepout Region(4)  
4
(1) See Figure 4-21 for dimension definitions.  
(2) Measurements from center of device to center of DDR2/mDDR device.  
(3) For single memory systems it is recommended that Y Offset be as small as possible.  
(4) Non-DDR2/mDDR signals allowed within DDR2/mDDR keepout region provided they are separated from DDR2/mDDR routing layers by  
a ground plane.  
(5) w = PCB trace width as defined in Table 4-27.  
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4.7.6.4.3.5 DDR2/mDDR Keep Out Region  
The region of the PCB used for the DDR2/mDDR circuitry must be isolated from other signals. The  
DDR2/mDDR keep out region is defined for this purpose and is shown in Figure 4-22. The size of this  
region varies with the placement and DDR routing. Additional clearances required for the keep out region  
are shown in Table 4-28.  
A1  
DDR2/mDDR  
Device  
A1  
Region should encompass all DDR2/mDDR circuitry and varies  
depending on placement. Non-DDR2/mDDR signals should not be  
routed on the DDR signal layers within the DDR2/mDDR keep out  
region. Non-DDR2/mDDR signals may be routed in the region  
provided they are routed on layers separated from DDR2/mDDR  
signal layers by a ground layer. No breaks should be allowed in the  
reference ground layers in this region. In addition, the 1.8 V power  
plane should cover the entire keep out region.  
Figure 4-22. DDR2/mDDR Keepout Region  
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4.7.6.4.3.6 Bulk Bypass Capacitors  
Bulk bypass capacitors are required for moderate speed bypassing of the DDR2/mDDR and other  
circuitry. Table 4-29 contains the minimum numbers and capacitance required for the bulk bypass  
capacitors. Note that this table only covers the bypass needs of the DSP and DDR2/mDDR interfaces.  
Additional bulk bypass capacitance may be needed for other circuitry.  
Table 4-29. Bulk Bypass Capacitors  
NO. PARAMETER  
MIN  
3
MAX  
UNIT  
Devices  
μF  
1
2
3
4
5
6
DDR_DVDD18 Supply Bulk Bypass Capacitor Count(1)  
DDR_DVDD18 Supply Bulk Bypass Total Capacitance  
DDR#1 Bulk Bypass Capacitor Count(1)  
DDR#1 Bulk Bypass Total Capacitance  
DDR#2 Bulk Bypass Capacitor Count(1)(2)  
DDR#2 Bulk Bypass Total Capacitance(2)  
30  
1
Devices  
μF  
22  
1
Devices  
μF  
22  
(1) These devices should be placed near the device they are bypassing, but preference should be given to the placement of the high-speed  
(HS) bypass caps.  
(2) Only used on dual-memory systems.  
4.7.6.4.3.7 High-Speed Bypass Capacitors  
High-speed (HS) bypass capacitors are critical for proper DDR2/mDDR interface operation. It is  
particularly important to minimize the parasitic series inductance of the HS bypass cap, DSP/DDR2/mDDR  
power, and DSP/DDR2/mDDR ground connections. Table 4-30 contains the specification for the HS  
bypass capacitors as well as for the power connections on the PCB.  
Table 4-30. High-Speed Bypass Capacitors  
NO. PARAMETER  
MIN  
MAX  
0402  
250  
UNIT  
10 Mils  
Mils  
1
2
HS Bypass Capacitor Package Size(1)  
Distance from HS bypass capacitor to device being bypassed  
Number of connection vias for each HS bypass capacitor  
Trace length from bypass capacitor contact to connection via  
Number of connection vias for each DDR2/mDDR device power or ground balls  
Trace length from DDR2/mDDR device power ball to connection via  
DDR_DVDD18 Supply HS Bypass Capacitor Count(3)  
DDR_DVDD18 Supply HS Bypass Capacitor Total Capacitance  
DDR#1 HS Bypass Capacitor Count(3)  
3
2(2)  
1
Vias  
4
30  
35  
Mils  
5
1
Vias  
6
Mils  
7
10  
0.6  
8
Devices  
μF  
8
9
Devices  
μF  
10  
11  
12  
DDR#1 HS Bypass Capacitor Total Capacitance  
DDR#2 HS Bypass Capacitor Count(3)(4)  
DDR#2 HS Bypass Capacitor Total Capacitance(4)  
0.4  
8
Devices  
μF  
0.4  
(1) LxW, 10 mil units, i.e., a 0402 is a 40x20 mil surface mount capacitor  
(2) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board.  
(3) These devices should be placed as close as possible to the device being bypassed.  
(4) Only used on dual-memory systems.  
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4.7.6.4.3.8 Net Classes  
Table 4-31 lists the clock net classes for the DDR2/mDDR interface. Table 4-32 lists the signal net  
classes, and associated clock net classes, for the signals in the DDR2/mDDR interface. These net classes  
are used for the termination and routing rules that follow.  
Table 4-31. Clock Net Class Definitions  
CLOCK NET CLASS  
DSP PIN NAMES  
DDR_CLKP / DDR_CLKN  
DDR_DQS[0]  
CK  
DQS0  
DQS1  
DDR_DQS[1]  
Table 4-32. Signal Net Class Definitions  
ASSOCIATED CLOCK  
SIGNAL NET CLASS  
NET CLASS  
DSP PIN NAMES  
ADDR_CTRL  
CK  
DDR_BA[2:0], DDR_A[13:0], DDR_CS, DDR_CAS, DDR_RAS, DDR_WE,  
DDR_CKE  
D0  
D1  
DQS0  
DQS1  
DDR_D[7:0], DDR_DQM0  
DDR_D[15:8], DDR_DQM1  
DDR_DQGATE0, DDR_DQGATE1  
DQGATE  
CK, DQS0, DQS1  
4.7.6.4.3.9 DDR2/mDDR Signal Termination  
No terminations of any kind are required in order to meet signal integrity and overshoot requirements.  
Serial terminators are permitted, if desired, to reduce EMI risk; however, serial terminations are the only  
type permitted. Table 4-33 shows the specifications for the series terminators.  
Table 4-33. DDR2/mDDR Signal Terminations(1)(2)(3)  
NO. PARAMETER  
MIN  
0
TYP  
MAX  
10  
UNIT  
Ω
1
2
3
4
CK Net Class  
ADDR_CTRL Net Class  
Data Byte Net Classes (DQS[0], DQS[1], D0, D1)(4)  
0
22  
22  
10  
Zo  
Ω
0
Zo  
Ω
DQGATE Net Class (DQGATE)  
0
Zo  
Ω
(1) Only series termination is permitted, parallel or SST specifically disallowed.  
(2) Terminator values larger than typical only recommended to address EMI issues.  
(3) Termination value should be uniform across net class.  
(4) When no termination is used on data lines (0 Ω), the DDR2/mDDR devices must be programmed to operate in 60% strength mode.  
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4.7.6.4.3.10 VREF Routing  
VREF is used as a reference by the input buffers of the DDR2/mDDR memories as well as the C6748.  
VREF is intended to be half the DDR2/mDDR power supply voltage and should be created using a  
resistive divider as shown in Figure 4-19. Other methods of creating VREF are not recommended.  
Figure 4-23 shows the layout guidelines for VREF.  
VREF Bypass Capacitor  
DDR2/mDDR Device  
A1  
VREF Nominal Minimum  
DDR2/mDDR  
Trace Width is 20 Mils  
A1  
Neck down to minimum in BGA escape  
regions is acceptable. Narrowing to  
accomodate via congestion for short  
distances is also acceptable. Best  
performance is obtained if the width  
of VREF is maximized.  
Figure 4-23. VREF Routing and Topology  
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4.7.6.4.3.11 DDR2/mDDR CK and ADDR_CTRL Routing  
Figure 4-24 shows the topology of the routing for the CK and ADDR_CTRL net classes. The route is a  
balanced T as it is intended that the length of segments B and C be equal. In addition, the length of A  
should be maximized.  
A1  
T
A
A1  
Figure 4-24. CK and ADDR_CTRL Routing and Topology  
Table 4-34. CK and ADDR_CTRL Routing Specification  
NO. PARAMETER  
MIN  
TYP  
MAX  
2w(2)  
25  
UNIT  
1
2
Center to Center CK-CKN Spacing(1)  
CK A to B/A to C Skew Length Mismatch(3)  
Mils  
Mils  
3
CK B to C Skew Length Mismatch  
25  
4
Center to center CK to other DDR2/mDDR trace spacing(1)  
CK/ADDR_CTRL nominal trace length(4)  
4w(2)  
5
CACLM-50  
CACLM  
CACLM+50  
100  
Mils  
Mils  
Mils  
6
ADDR_CTRL to CK Skew Length Mismatch  
7
ADDR_CTRL to ADDR_CTRL Skew Length Mismatch  
Center to center ADDR_CTRL to other DDR2/mDDR trace spacing(1)  
Center to center ADDR_CTRL to other ADDR_CTRL trace spacing(1)  
ADDR_CTRL A to B/A to C Skew Length Mismatch(3)  
ADDR_CTRL B to C Skew Length Mismatch  
100  
8
4w(2)  
(2)  
9
3w  
10  
11  
100  
100  
Mils  
Mils  
(1) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing  
congestion.  
(2) w = PCB trace width as defined in Table 4-27.  
(3) Series terminator, if used, should be located closest to device.  
(4) CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes.  
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Figure 4-25 shows the topology and routing for the DQS and D net class; the routes are point to point.  
Skew matching across bytes is not needed nor recommended.  
T
E0  
A1  
T
E1  
A1  
Figure 4-25. DQS and D Routing and Topology  
Table 4-35. DQS and D Routing Specification  
NO. PARAMETER  
MIN  
4w(2)  
TYP  
MAX  
UNIT  
1
2
3
4
5
6
Center to center DQS to other DDR2/mDDR trace spacing(1)  
DQS/D nominal trace length(3)(4)  
D to DQS Skew Length Mismatch(4)  
D to D Skew Length Mismatch(4)  
Center to center D to other DDR2/mDDR trace spacing(1)(5)  
Center to Center D to other D trace spacing(1)(6)  
DQLM-50  
DQLM  
DQLM+50  
100  
Mils  
Mils  
Mils  
100  
4w(2)  
3w(2)  
(1) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing  
congestion.  
(2) w = PCB trace width as defined in Table 4-27.  
(3) Series terminator, if used, should be located closest to DDR.  
(4) There is no need and it is not recommended to skew match across data bytes, i.e., from DQS0 and data byte 0 to DQS1 and data byte  
1.  
(5) D's from other DQS domains are considered other DDR2/mDDR trace.  
(6) DQLM is the longest Manhattan distance of each of the DQS and D net class.  
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Figure 4-26 shows the routing for the DQGATE net class. Table 4-36 contains the routing specification.  
A1  
T
T
F
A1  
Figure 4-26. DQGATE Routing  
Table 4-36. DQGATE Routing Specification  
NO. PARAMETER  
MIN  
TYP  
MAX  
UNIT  
1
2
3
4
DQGATE Length F  
Center to center DQGATE to any other trace spacing  
CKB0B(1)  
4w(2)  
DQS/D nominal trace length  
DQGATE Skew(3)  
DQLM-50  
DQLM  
DQLM+50  
100  
Mils  
Mils  
(1) CKB0B1 is the sum of the length of the CK net plus the average length of the DQS0 and DQS1 nets.  
(2) w = PCB trace width as defined in Table 4-27.  
(3) Skew from CKB0B1  
4.7.6.4.3.12 DDR2/mDDR Boundary Scan Limitations  
Due to DDR implementation and timing restrictions, it was not possible to place boundary scan cells  
between core logic and the IO like boundary scan cells for other IO. Instead, the boundary scan cells are  
tapped-off to the DDR PHY and there is the equivalent of a multiplexer inside the DDR PHY which selects  
between functional and boundary scan paths.  
The implication for boundary scan is that the DDR pins will not support the SAMPLE function of the output  
enable cells on the DDR pins and this is a violation of IEEE 1149.1. Full EXTEST and PRELOAD  
capability is still available.  
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4.7.6.5 Memory Protection Units  
The MPU performs memory protection checking. It receives requests from a bus master in the system and  
checks the address against the fixed and programmable regions to see if the access is allowed. If allowed,  
the transfer is passed unmodified to its output bus (to the targeted address). If the transfer is illegal (fails  
the protection check) then the MPU does not pass the transfer to the output bus but rather services the  
transfer internally back to the input bus (to prevent a hang) returning the fault status to the requestor as  
well as generating an interrupt about the fault. The following features are supported by the MPU:  
•
•
•
•
•
•
•
Provides memory protection for fixed and programmable address ranges.  
Supports multiple programmable address region.  
Supports secure and debug access privileges.  
Supports read, write, and execute access privileges.  
Supports privid(8) associations with ranges.  
Generates an interrupt when there is a protection violation, and saves violating transfer parameters.  
MMR access is also protected.  
Table 4-37. MPU1 Configuration Registers  
MPU1  
BYTE ADDRESS  
ACRONYM  
REGISTER DESCRIPTION  
0x01E1 4000  
REVID  
CONFIG  
Revision ID  
0x01E1 4004  
Configuration  
0x01E1 4010  
IRAWSTAT  
IENSTAT  
Interrupt raw status/set  
0x01E1 4014  
Interrupt enable status/clear  
0x01E1 4018  
IENSET  
Interrupt enable  
0x01E1 401C  
IENCLR  
Interrupt enable clear  
0x01E1 4020 - 0x01E1 41FF  
0x01E1 4200  
-
Reserved  
PROG1_MPSAR  
PROG1_MPEAR  
PROG1_MPPA  
-
Programmable range 1, start address  
Programmable range 1, end address  
Programmable range 1, memory page protection attributes  
Reserved  
0x01E1 4204  
0x01E1 4208  
0x01E1 420C - 0x01E1 420F  
0x01E1 4210  
PROG2_MPSAR  
PROG2_MPEAR  
PROG2_MPPA  
-
Programmable range 2, start address  
Programmable range 2, end address  
Programmable range 2, memory page protection attributes  
Reserved  
0x01E1 4214  
0x01E1 4218  
0x01E1 421C - 0x01E1 421F  
0x01E1 4220  
PROG3_MPSAR  
PROG3_MPEAR  
PROG3_MPPA  
-
Programmable range 3, start address  
Programmable range 3, end address  
Programmable range 3, memory page protection attributes  
Reserved  
0x01E1 4224  
0x01E1 4228  
0x01E1 422C - 0x01E1 422F  
0x01E1 4230  
PROG4_MPSAR  
PROG4_MPEAR  
PROG4_MPPA  
-
Programmable range 4, start address  
Programmable range 4, end address  
Programmable range 4, memory page protection attributes  
Reserved  
0x01E1 4234  
0x01E1 4238  
0x01E1 423C - 0x01E1 423F  
0x01E1 4240  
PROG5_MPSAR  
PROG5_MPEAR  
PROG5_MPPA  
-
Programmable range 5, start address  
Programmable range 5, end address  
Programmable range 5, memory page protection attributes  
Reserved  
0x01E1 4244  
0x01E1 4248  
0x01E1 424C - 0x01E1 424F  
0x01E1 4250  
PROG6_MPSAR  
PROG6_MPEAR  
PROG6_MPPA  
-
Programmable range 6, start address  
Programmable range 6, end address  
Programmable range 6, memory page protection attributes  
Reserved  
0x01E1 4254  
0x01E1 4258  
0x01E1 425C - 0x01E1 42FF  
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Table 4-37. MPU1 Configuration Registers (continued)  
MPU1  
BYTE ADDRESS  
ACRONYM  
REGISTER DESCRIPTION  
0x01E1 4300  
0x01E1 4304  
FLTADDRR  
FLTSTAT  
FLTCLR  
-
Fault address  
Fault status  
Fault clear  
Reserved  
0x01E1 4308  
0x01E1 430C - 0x01E1 4FFF  
Table 4-38. MPU2 Configuration Registers  
MPU2  
BYTE ADDRESS  
ACRONYM  
REGISTER DESCRIPTION  
0x01E1 5000  
0x01E1 5004  
REVID  
CONFIG  
Revision ID  
Configuration  
0x01E1 5010  
IRAWSTAT  
IENSTAT  
Interrupt raw status/set  
0x01E1 5014  
Interrupt enable status/clear  
0x01E1 5018  
IENSET  
Interrupt enable  
0x01E1 501C  
IENCLR  
Interrupt enable clear  
0x01E1 5020 - 0x01E1 51FF  
0x01E1 5200  
-
Reserved  
PROG1_MPSAR  
PROG1_MPEAR  
PROG1_MPPA  
-
Programmable range 1, start address  
Programmable range 1, end address  
Programmable range 1, memory page protection attributes  
Reserved  
0x01E1 5204  
0x01E1 5208  
0x01E1 520C - 0x01E1 520F  
0x01E1 5210  
PROG2_MPSAR  
PROG2_MPEAR  
PROG2_MPPA  
-
Programmable range 2, start address  
Programmable range 2, end address  
Programmable range 2, memory page protection attributes  
Reserved  
0x01E1 5214  
0x01E1 5218  
0x01E1 521C - 0x01E1 521F  
0x01E1 5220  
PROG3_MPSAR  
PROG3_MPEAR  
PROG3_MPPA  
-
Programmable range 3, start address  
Programmable range 3, end address  
Programmable range 3, memory page protection attributes  
Reserved  
0x01E1 5224  
0x01E1 5228  
0x01E1 522C - 0x01E1 522F  
0x01E1 5230  
PROG4_MPSAR  
PROG4_MPEAR  
PROG4_MPPA  
-
Programmable range 4, start address  
Programmable range 4, end address  
Programmable range 4, memory page protection attributes  
Reserved  
0x01E1 5234  
0x01E1 5238  
0x01E1 523C - 0x01E1 523F  
0x01E1 5240  
PROG5_MPSAR  
PROG5_MPEAR  
PROG5_MPPA  
-
Programmable range 5, start address  
Programmable range 5, end address  
Programmable range 5, memory page protection attributes  
Reserved  
0x01E1 5244  
0x01E1 5248  
0x01E1 524C - 0x01E1 524F  
0x01E1 5250  
PROG6_MPSAR  
PROG6_MPEAR  
PROG6_MPPA  
-
Programmable range 6, start address  
Programmable range 6, end address  
Programmable range 6, memory page protection attributes  
Reserved  
0x01E1 5254  
0x01E1 5258  
0x01E1 525C - 0x01E1 525F  
0x01E1 5260  
PROG7_MPSAR  
PROG7_MPEAR  
PROG7_MPPA  
-
Programmable range 7, start address  
Programmable range 7, end address  
Programmable range 7, memory page protection attributes  
Reserved  
0x01E1 5264  
0x01E1 5268  
0x01E1 526C - 0x01E1 526F  
0x01E1 5270  
PROG8_MPSAR  
PROG8_MPEAR  
PROG8_MPPA  
-
Programmable range 8, start address  
Programmable range 8, end address  
Programmable range 8, memory page protection attributes  
Reserved  
0x01E1 5274  
0x01E1 5278  
0x01E1 527C - 0x01E1 527F  
106  
Specifications  
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Table 4-38. MPU2 Configuration Registers (continued)  
MPU2  
BYTE ADDRESS  
ACRONYM  
REGISTER DESCRIPTION  
0x01E1 5280  
PROG9_MPSAR  
PROG9_MPEAR  
PROG9_MPPA  
-
Programmable range 9, start address  
Programmable range 9, end address  
0x01E1 5284  
0x01E1 5288  
Programmable range 9, memory page protection attributes  
Reserved  
0x01E1 528C - 0x01E1 528F  
0x01E1 5290  
PROG10_MPSAR  
PROG10_MPEAR  
PROG10_MPPA  
-
Programmable range 10, start address  
Programmable range 10, end address  
Programmable range 10, memory page protection attributes  
Reserved  
0x01E1 5294  
0x01E1 5298  
0x01E1 529C - 0x01E1 529F  
0x01E1 52A0  
PROG11_MPSAR  
PROG11_MPEAR  
PROG11_MPPA  
-
Programmable range 11, start address  
Programmable range 11, end address  
Programmable range 11, memory page protection attributes  
Reserved  
0x01E1 52A4  
0x01E1 52A8  
0x01E1 52AC - 0x01E1 52AF  
0x01E1 52B0  
PROG12_MPSAR  
PROG12_MPEAR  
PROG12_MPPA  
-
Programmable range 12, start address  
Programmable range 12, end address  
Programmable range 12, memory page protection attributes  
Reserved  
0x01E1 52B4  
0x01E1 52B8  
0x01E1 52BC - 0x01E1 52FF  
0x01E1 5300  
FLTADDRR  
FLTSTAT  
Fault address  
0x01E1 5304  
Fault status  
0x01E1 5308  
FLTCLR  
Fault clear  
0x01E1 530C - 0x01E1 5FFF  
-
Reserved  
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4.7.6.6 MMC / SD / SDIO (MMCSD0, MMCSD1)  
4.7.6.6.1 MMCSD Peripheral Description  
The device includes an two MMCSD controllers which are compliant with MMC V4.0, Secure Digital Part 1  
Physical Layer Specification V1.1 and Secure Digital Input Output (SDIO) V2.0 specifications.  
The MMC/SD Controller have following features:  
•
•
•
•
•
•
•
•
MultiMediaCard (MMC)  
Secure Digital (SD) Memory Card  
MMC/SD protocol support  
SD high capacity support  
SDIO protocol support  
Programmable clock frequency  
512 bit Read/Write FIFO to lower system overhead  
Slave EDMA transfer capability  
The device MMC/SD Controller does not support SPI mode.  
4.7.6.6.2 MMCSD Peripheral Register Description(s)  
Table 4-39. Multimedia Card/Secure Digital (MMC/SD) Card Controller Registers  
MMCSD0  
BYTE ADDRESS  
MMCSD1  
BYTE ADDRESS  
ACRONYM  
REGISTER DESCSRIPTION  
0x01C4 0000  
0x01C4 0004  
0x01C4 0008  
0x01C4 000C  
0x01C4 0010  
0x01C4 0014  
0x01C4 0018  
0x01C4 001C  
0x01C4 0020  
0x01C4 0024  
0x01C4 0028  
0x01C4 002C  
0x01C4 0030  
0x01C4 0034  
0x01C4 0038  
0x01C4 003C  
0x01C4 0040  
0x01C4 0044  
0x01C4 0048  
0x01C4 0050  
0x01C4 0064  
0x01C4 0068  
0x01C4 006C  
0x01C4 0070  
0x01C4 0074  
0x01E1 B000  
0x01E1 B004  
0x01E1 B008  
0x01E1 B00C  
0x01E1 B010  
0x01E1 B014  
0x01E1 B018  
0x01E1 B01C  
0x01E1 B020  
0x01E1 B024  
0x01E1 B028  
0x01E1 B02C  
0x01E1 B030  
0x01E1 B034  
0x01E1 B038  
0x01E1 B03C  
0x01E1 B040  
0x01E1 B044  
0x01E1 B048  
0x01E1 B050  
0x01E1 B064  
0x01E1 B068  
0x01E1 B06C  
0x01E1 B070  
0x01E1 B074  
MMCCTL  
MMCCLK  
MMC Control Register  
MMC Memory Clock Control Register  
MMC Status Register 0  
MMCST0  
MMCST1  
MMC Status Register 1  
MMCIM  
MMC Interrupt Mask Register  
MMC Response Time-Out Register  
MMC Data Read Time-Out Register  
MMC Block Length Register  
MMC Number of Blocks Register  
MMC Number of Blocks Counter Register  
MMC Data Receive Register  
MMC Data Transmit Register  
MMC Command Register  
MMCTOR  
MMCTOD  
MMCBLEN  
MMCNBLK  
MMCNBLC  
MMCDRR  
MMCDXR  
MMCCMD  
MMCARGHL  
MMCRSP01  
MMCRSP23  
MMCRSP45  
MMCRSP67  
MMCDRSP  
MMCCIDX  
SDIOCTL  
MMC Argument Register  
MMC Response Register 0 and 1  
MMC Response Register 2 and 3  
MMC Response Register 4 and 5  
MMC Response Register 6 and 7  
MMC Data Response Register  
MMC Command Index Register  
SDIO Control Register  
SDIOST0  
SDIO Status Register 0  
SDIOIEN  
SDIO Interrupt Enable Register  
SDIO Interrupt Status Register  
MMC FIFO Control Register  
SDIOIST  
MMCFIFOCTL  
108  
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4.7.6.6.3 MMC/SD Electrical Data/Timing  
Table 4-40 through Table 4-41 assume testing over recommended operating conditions.  
Table 4-40. Timing Requirements for MMC/SD  
(see Figure 4-28 and Figure 4-30)  
1.3V, 1.2V  
1.1V  
MIN MAX  
1.0V  
MIN MAX  
NO.  
UNIT  
MIN  
MAX  
tsu(CMDV-  
CLKH)  
1
Setup time, MMCSD_CMD valid before MMCSD_CLK high  
4
4
6
ns  
2
3
4
th(CLKH-CMDV) Hold time, MMCSD_CMD valid after MMCSD_CLK high  
tsu(DATV-CLKH) Setup time, MMCSD_DATx valid before MMCSD_CLK high  
th(CLKH-DATV) Hold time, MMCSD_DATx valid after MMCSD_CLK high  
2.5  
4.5  
2.5  
2.5  
5
2.5  
6
ns  
ns  
ns  
2.5  
2.5  
Table 4-41. Switching Characteristics for MMC/SD (see Figure 4-27 through Figure 4-30)  
1.3V, 1.2V  
1.1V  
1.0V  
NO.  
PARAMETER  
UNIT  
MIN  
0
MAX  
MIN  
MAX  
50  
MIN  
MAX  
25  
7
8
9
f(CLK)  
Operating frequency, MMCSD_CLK  
Identification mode frequency, MMCSD_CLK  
Pulse width, MMCSD_CLK low  
52  
0
0
0
MHz  
KHz  
ns  
f(CLK_ID)  
tW(CLKL)  
0
400  
0
400  
400  
6.5  
6.5  
6.5  
6.5  
10  
10  
10 tW(CLKH)  
11 tr(CLK)  
Pulse width, MMCSD_CLK high  
ns  
Rise time, MMCSD_CLK  
3
3
3
10  
10  
4
ns  
12 tf(CLK)  
Fall time, MMCSD_CLK  
3
ns  
13 td(CLKL-CMD)  
14 td(CLKL-DAT)  
Delay time, MMCSD_CLK low to MMCSD_CMD transition  
Delay time, MMCSD_CLK low to MMCSD_DATx transition  
-4  
-4  
2.5  
3.3  
-4  
-4  
3
-4  
-4  
ns  
3.5  
4
ns  
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10  
9
7
MMCSD_CLK  
13  
13  
13  
13  
START  
XMIT  
Valid  
Valid  
Valid  
END  
MMCSD_CMD  
Figure 4-27. MMC/SD Host Command Timing  
9
10  
7
MMCSD_CLK  
MMCSD_CMD  
1
2
Valid  
START  
XMIT  
Valid  
Valid  
END  
Figure 4-28. MMC/SD Card Response Timing  
10  
9
7
MMCSD_CLK  
MMCSD_DATx  
14  
14  
14  
Dx  
14  
START  
D0  
D1  
END  
Figure 4-29. MMC/SD Host Write Timing  
9
10  
7
MMCSD_CLK  
MMCSD_DATx  
4
4
3
3
Start  
D0  
D1  
Dx  
End  
Figure 4-30. MMC/SD Host Read and Card CRC Status Timing  
110  
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4.7.6.7 Serial ATA Controller (SATA)  
The Serial ATA Controller (SATA) provides a single HBA port operating in AHCI mode and is used to  
interface to data storage devices at both 1.5 Gbits/second and 3.0 Gbits/second line speeds. AHCI  
describes a system memory structure that contains a generic area for control and status, and a table of  
entries describing a command list where each command list entry contains information necessary to  
program an SATA device, and a pointer to a descriptor table for transferring data between system memory  
and the device.  
The SATA Controller supports the following features:  
•
•
•
•
•
•
•
•
•
•
•
•
Serial ATA 1.5 Gbps (Gen 1i) and 3 Gbps (Gen 2i) line speeds  
Support for the AHCI controller spec 1.1  
Integrated SERDES PHY  
Integrated Rx and Tx data buffers  
Supports all SATA power management features  
Internal DMA engine per port  
Hardware-assisted native command queuing (NCQ) for up to 32 entries  
32-bit addressing  
Supports port multiplier with command-based switching  
Activity LED support  
Mechanical presence switch  
Cold presence detect  
The SATA Controller support is dependent on the CPU voltage operating point:  
•
•
•
•
At CVDD = 1.3V, SATA Gen 2i (3.0 Gbps) and SATA Gen 1i (1.5 Gbps) are supported.  
At CVDD = 1.2V, SATA Gen 2i (3.0 Gbps) and SATA Gen 1i (1.5 Gbps) are supported.  
At CVDD = 1.1V, SATA Gen 1i (1.5 Gbps) only is supported.  
At CVDD = 1.0V, SATA is not supported.  
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4.7.6.7.1 SATA Register Descriptions  
Table 4-42 is a list of the SATA Controller registers.  
Table 4-42. SATA Controller Registers  
BYTE ADDRESS  
0x01E1 8000  
0x01E1 8004  
0x01E1 8008  
0x01E1 800C  
0x01E1 8010  
0x01E1 8014  
0x01E1 8018  
0x01E1 80A0  
0x01E1 80A4  
0x01E1 80A8  
0x01E1 80AC  
0x01E1 80B0  
0x01E1 80E0  
0x01E1 80E8  
0x01E1 80EC  
0x01E1 80F0  
0x01E1 80F4  
0x01E1 80F8  
0x01E1 80FC  
0x01E1 8100  
0x01E1 8108  
0x01E1 8110  
0x01E1 8114  
0x01E1 8118  
0x01E1 8120  
0x01E1 8124  
0x01E1 8128  
0x01E1 812C  
0x01E1 8130  
0x01E1 8134  
0x01E1 8138  
0x01E1 813C  
0x01E1 8170  
0x01E1 8178  
0x01E1 817C  
ACRONYM  
REGISTER DESCRIPTION  
CAP  
GHC  
HBA Capabilities Register  
Global HBA Control Register  
Interrupt Status Register  
IS  
PI  
Ports Implemented Register  
AHCI Version Register  
VS  
CCC_CTL  
CCC_PORTS  
BISTAFR  
BISTCR  
BISTFCTR  
BISTSR  
BISTDECR  
TIMER1MS  
GPARAM1R  
GPARAM2R  
PPARAMR  
TESTR  
Command Completion Coalescing Control Register  
Command Completion Coalescing Ports Register  
BIST Active FIS Register  
BIST Control Register  
BIST FIS Count Register  
BIST Status Register  
BIST DWORD Error Count Register  
BIST DWORD Error Count Register  
Global Parameter 1 Register  
Global Parameter 2 Register  
Port Parameter Register  
Test Register  
VERSIONR  
IDR  
Version Register  
ID Register  
P0CLB  
Port Command List Base Address Register  
Port FIS Base Address Register  
Port Interrupt Status Register  
Port Interrupt Enable Register  
Port Command Register  
P0FB  
P0IS  
P0IE  
P0CMD  
P0TFD  
Port Task File Data Register  
Port Signature Register  
P0SIG  
P0SSTS  
P0SCTL  
P0SERR  
P0SACT  
P0CI  
Port Serial ATA Status Register  
Port Serial ATA Control Register  
Port Serial ATA Error Register  
Port Serial ATA Active Register  
Port Command Issue Register  
Port Serial ATA Notification Register  
Port DMA Control Register  
Port PHY Control Register  
Port PHY Status Register  
P0SNTF  
P0DMACR  
P0PHYCR  
P0PHYSR  
112  
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4.7.6.7.2 1. SATA Interface  
This section provides the timing specification for the SATA interface as a PCB design and manufacturing  
specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk,  
and signal timing. TI has performed the simulation and system design work to ensure the SATA interface  
requirements are met.  
4.7.6.7.2.1 SATA Interface Schematic  
Figure 4-31 shows the SATA interface schematic.  
SATA Interface(Processor)  
SATA Connector  
10nF  
TX–  
TX+  
SATA_TXN  
SATA_TXP  
10nF  
10nF  
RX–  
RX+  
SATA_RXN  
SATA_RXP  
10nF  
LVDS  
Oscillator  
10nF  
10nF  
CLK–  
CLK+  
SATA_REFCLKN  
SATA_REFCLKP  
SATA_REG  
0.1uF  
Figure 4-31. SATA Interface High Level Schematic  
4.7.6.7.2.2 Compatible SATA Components and Modes  
Table 4-43 shows the compatible SATA components and supported modes. Note that the only supported  
configuration is an internal cable from the processor host to the SATA device.  
Table 4-43. SATA Supported Modes  
PARAMETER  
Transfer Rates  
eSATA  
MIN  
MAX  
UNIT  
SUPPORTED  
1.5  
3.0  
Gbps  
No  
No  
xSATA  
Backplane  
Internal Cable  
No  
Yes  
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4.7.6.7.2.3 PCB Stackup Specifications  
Table 4-44 shows the stackup and feature sizes required for SATA.  
Table 4-44. SATA PCB Stackup Specifications  
PARAMETER  
PCB Routing/Plane Layers  
MIN  
4
TYP  
6
MAX  
UNIT  
Layers  
Layers  
Layers  
Signal Routing Layers  
2
3
Number of ground plane cuts allowed within SATA routing region  
Number of layers between SATA routing region and reference ground plane  
PCB Routing Feature Size  
0
0
4
4
Mils  
Mils  
Mils  
Mils  
PCB Trace Width w  
PCB BGA escape via pad size  
18  
8
PCB BGA escape via hole size  
(1)  
Device BGA pad size  
(1) Please refer to the Flip Chip Ball Grid Array Package Reference Guide (SPRU811) for device BGA pad size.  
4.7.6.7.2.4 Routing Specifications  
The SATA data signal traces are edge-coupled and must be routed to achieve exactly 100 Ohms  
differential impedance. This is impacted by trace width, trace spacing, distance between planes, and  
dielectric material. Verify with a proper PCB manufacturing tool that the trace geometry for both data  
signal pairs results in exactly 100 ohms differential impedance traces. Table 4-45 shows the routing  
specifications for the data and REFCLK signals.  
Table 4-45. SATA Routing Specifications  
PARAMETER  
MIN  
TYP  
MAX  
7000  
2000  
0
UNIT  
Mils  
Device to SATA header trace length  
REFCLK trace length from oscillator to Device(1)  
Number of stubs allowed on SATA traces  
TX/RX pair differential impedance  
Mils  
Stubs  
Ohms  
100  
(2)  
Number of vias on each SATA trace  
SATA differential pair to any other trace spacing  
3
Vias  
(3)  
2*DS  
(1) The SATA_REFCLK(P/N) pins include an internal 100 Ohms differential termination  
(2) Vias must be used in pairs with their distance minimized.  
(3) DS is the differential spacing of the SATA traces.  
4.7.6.7.2.5 Coupling Capacitors  
AC coupling capacitors are required on the receive data pair as well as the REFCLK pair. Table 4-46  
shows the requirements for these capacitors.  
Table 4-46. SATA Bypass and Coupling Capacitors Requirements  
PARAMETER  
MIN  
TYP  
MAX  
12  
UNIT  
nF  
10 Mils(1)(2)  
SATA AC coupling capacitor value  
SATA AC coupling capacitor package size  
0.3  
10  
0603  
(1) LxW, 10 mil units, i.e., a 0402 is a 40x20 mil surface mount capacitor.  
(2) The physical size of the capacitor should be as small as possible.  
4.7.6.7.2.6 SATA Interface Clock Source requirements  
A high-quality, low-jitter differential clock source is required for the SATA PHY. The SATA interface  
requires LVDS differential clock source to be provided at signals SATA_REFCLKP and  
SATA_REFCLKN. The clock source should be placed physically as close to the processor as possible.  
a
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Table 4-47 shows the requirements for the clock source.  
Table 4-47. SATA Input Clock Source Requirements  
PARAMETER  
Clock Frequency  
Jitter  
MIN  
TYP  
MAX  
UNIT  
MHz  
ps pk-pk  
%
(1)  
75  
375  
50  
Duty Cycle  
40  
60  
Rise/Fall Time  
700  
ps  
(1) Discrete clock frequency points are supported based on the PLL multiplier used in the SATA PHY.  
4.7.6.7.3 SATA Unused Signal Configuration  
If the SATA interface is not used, the SATA signals should be configured as shown below.  
Table 4-48. Unused SATA Signal Configuration  
SATA Signal Name  
SATA_RXP  
Configuration if SATA peripheral is not used  
No Connect  
No Connect  
No Connect  
No Connect  
No Connect  
No Connect  
SATA_RXN  
SATA_TXP  
SATA_TXN  
SATA_REFCLKP  
SATA_REFCLKN  
SATA_MPSWITCH  
SATA_CP_DET  
SATA_CP_POD  
SATA_LED  
May be used as GPIO or other peripheral function  
May be used as GPIO or other peripheral function  
May be used as GPIO or other peripheral function  
May be used as GPIO or other peripheral function  
No Connect  
SATA_REG  
SATA_VDDR  
SATA_VDD  
No Connect  
Prior to silicon revision 2.0, this supply must be connected to a static 1.2V nominal supply. For silicon  
revision 2.0 and later, this supply may be left unconnected for additional power conservation.  
SATA_VSS  
Vss  
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4.7.6.8 Multichannel Audio Serial Port (McASP)  
The McASP serial port is specifically designed for multichannel audio applications. Its key features are:  
•
•
•
Flexible clock and frame sync generation logic and on-chip dividers  
Up to sixteen transmit or receive data pins and serializers  
Large number of serial data format options, including:  
–
–
–
–
–
TDM Frames with 2 to 32 time slots per frame (periodic) or 1 slot per frame (burst)  
Time slots of 8,12,16, 20, 24, 28, and 32 bits  
First bit delay 0, 1, or 2 clocks  
MSB or LSB first bit order  
Left- or right-aligned data words within time slots  
•
•
•
DIT Mode with 384-bit Channel Status and 384-bit User Data registers  
Extensive error checking and mute generation logic  
All unused pins GPIO-capable  
•
Transmit & Receive FIFO Buffers allow the McASP to operate at a higher sample rate by making it  
more tolerant to DMA latency.  
•
Dynamic Adjustment of Clock Dividers  
–
Clock Divider Value may be changed without resetting the McASP  
Pins  
Function  
AHCLKRx  
ACLKRx  
AFSRx  
Receive Master Clock  
Receive Logic  
Clock/Fram e Generator  
State Machine  
Peripheral  
Configuration  
Bus  
GIO  
Control  
Receive Bit Clock  
Receive Left/Right Clock or Fram e Sync  
The McASP DOES NOT have a  
dedicated AMUTEIN pin.  
AMUTEINx  
AMUTEx  
Clock Check and  
Error Detection  
DIT RAM  
384 C  
384 U  
AFSXx  
Transm it Left/Right Clock or Fram e Sync  
Transm it Bit Clock  
Transm it Logic  
Clock/Fram e Generator  
State Machine  
Optional  
ACLKXx  
AHCLKXx  
Transm it M aster Clock  
Transm it  
Form atter  
Serializer 0  
Serializer 1  
AXRx[0]  
AXRx[1]  
Transm it/Receive Serial Data Pin  
Transm it/Receive Serial Data Pin  
McASP  
DMA Bus  
(Dedicated)  
Receive  
Form atter  
Serializer y  
McASP  
AXRx[y]  
Transm it/Receive Serial Data Pin  
Figure 4-32. McASP Block Diagram  
116  
Specifications  
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4.7.6.8.1 McASP Peripheral Registers Description(s)  
Registers for the McASP are summarized in Table 4-49. The registers are accessed through the  
peripheral configuration port. The receive buffer registers (RBUF) and transmit buffer registers (XBUF) can  
also be accessed through the DMA port, as listed in Table 4-50  
Registers for the McASP Audio FIFO (AFIFO) are summarized in Table 4-51. Note that the AFIFO Write  
FIFO (WFIFO) and Read FIFO (RFIFO) have independent control and status registers. The AFIFO control  
registers are accessed through the peripheral configuration port.  
Table 4-49. McASP Registers Accessed Through Peripheral Configuration Port  
BYTE ADDRESS  
0x01D0 0000  
0x01D0 0010  
0x01D0 0014  
0x01D0 0018  
0x01D0 001C  
0x01D0 001C  
0x01D0 0020  
0x01D0 0044  
0x01D0 0048  
0x01D0 004C  
0x01D0 0050  
0x01D0 0060  
ACRONYM  
REV  
REGISTER DESCRIPTION  
Revision identification register  
Pin function register  
PFUNC  
PDIR  
Pin direction register  
PDOUT  
PDIN  
Pin data output register  
Read returns: Pin data input register  
Writes affect: Pin data set register (alternate write address: PDOUT)  
Pin data clear register (alternate write address: PDOUT)  
Global control register  
PDSET  
PDCLR  
GBLCTL  
AMUTE  
DLBCTL  
DITCTL  
Audio mute control register  
Digital loopback control register  
DIT mode control register  
Receiver global control register: Alias of GBLCTL, only receive bits are affected - allows  
receiver to be reset independently from transmitter  
RGBLCTL  
0x01D0 0064  
0x01D0 0068  
0x01D0 006C  
0x01D0 0070  
0x01D0 0074  
0x01D0 0078  
0x01D0 007C  
0x01D0 0080  
0x01D0 0084  
0x01D0 0088  
0x01D0 008C  
0x01D0 00A0  
RMASK  
RFMT  
Receive format unit bit mask register  
Receive bit stream format register  
Receive frame sync control register  
Receive clock control register  
AFSRCTL  
ACLKRCTL  
AHCLKRCTL  
RTDM  
Receive high-frequency clock control register  
Receive TDM time slot 0-31 register  
Receiver interrupt control register  
Receiver status register  
RINTCTL  
RSTAT  
RSLOT  
Current receive TDM time slot register  
Receive clock check control register  
Receiver DMA event control register  
RCLKCHK  
REVTCTL  
Transmitter global control register. Alias of GBLCTL, only transmit bits are affected - allows  
transmitter to be reset independently from receiver  
XGBLCTL  
0x01D0 00A4  
0x01D0 00A8  
0x01D0 00AC  
0x01D0 00B0  
0x01D0 00B4  
0x01D0 00B8  
0x01D0 00BC  
0x01D0 00C0  
0x01D0 00C4  
0x01D0 00C8  
0x01D0 00CC  
0x01D0 0100  
0x01D0 0104  
0x01D0 0108  
XMASK  
XFMT  
Transmit format unit bit mask register  
Transmit bit stream format register  
AFSXCTL  
ACLKXCTL  
AHCLKXCTL  
XTDM  
Transmit frame sync control register  
Transmit clock control register  
Transmit high-frequency clock control register  
Transmit TDM time slot 0-31 register  
XINTCTL  
XSTAT  
Transmitter interrupt control register  
Transmitter status register  
XSLOT  
Current transmit TDM time slot register  
Transmit clock check control register  
XCLKCHK  
XEVTCTL  
DITCSRA0  
DITCSRA1  
DITCSRA2  
Transmitter DMA event control register  
Left (even TDM time slot) channel status register (DIT mode) 0  
Left (even TDM time slot) channel status register (DIT mode) 1  
Left (even TDM time slot) channel status register (DIT mode) 2  
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Specifications  
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Table 4-49. McASP Registers Accessed Through Peripheral Configuration Port (continued)  
BYTE ADDRESS  
0x01D0 010C  
0x01D0 0110  
0x01D0 0114  
0x01D0 0118  
0x01D0 011C  
0x01D0 0120  
0x01D0 0124  
0x01D0 0128  
0x01D0 012C  
0x01D0 0130  
0x01D0 0134  
0x01D0 0138  
0x01D0 013C  
0x01D0 0140  
0x01D0 0144  
0x01D0 0148  
0x01D0 014C  
0x01D0 0150  
0x01D0 0154  
0x01D0 0158  
0x01D0 015C  
0x01D0 0180  
0x01D0 0184  
0x01D0 0188  
0x01D0 018C  
0x01D0 0190  
0x01D0 0194  
0x01D0 0198  
0x01D0 019C  
0x01D0 01A0  
0x01D0 01A4  
0x01D0 01A8  
0x01D0 01AC  
0x01D0 01B0  
0x01D0 01B4  
0x01D0 01B8  
0x01D0 01BC  
ACRONYM  
DITCSRA3  
DITCSRA4  
DITCSRA5  
DITCSRB0  
DITCSRB1  
DITCSRB2  
DITCSRB3  
DITCSRB4  
DITCSRB5  
DITUDRA0  
DITUDRA1  
DITUDRA2  
DITUDRA3  
DITUDRA4  
DITUDRA5  
DITUDRB0  
DITUDRB1  
DITUDRB2  
DITUDRB3  
DITUDRB4  
DITUDRB5  
SRCTL0  
REGISTER DESCRIPTION  
Left (even TDM time slot) channel status register (DIT mode) 3  
Left (even TDM time slot) channel status register (DIT mode) 4  
Left (even TDM time slot) channel status register (DIT mode) 5  
Right (odd TDM time slot) channel status register (DIT mode) 0  
Right (odd TDM time slot) channel status register (DIT mode) 1  
Right (odd TDM time slot) channel status register (DIT mode) 2  
Right (odd TDM time slot) channel status register (DIT mode) 3  
Right (odd TDM time slot) channel status register (DIT mode) 4  
Right (odd TDM time slot) channel status register (DIT mode) 5  
Left (even TDM time slot) channel user data register (DIT mode) 0  
Left (even TDM time slot) channel user data register (DIT mode) 1  
Left (even TDM time slot) channel user data register (DIT mode) 2  
Left (even TDM time slot) channel user data register (DIT mode) 3  
Left (even TDM time slot) channel user data register (DIT mode) 4  
Left (even TDM time slot) channel user data register (DIT mode) 5  
Right (odd TDM time slot) channel user data register (DIT mode) 0  
Right (odd TDM time slot) channel user data register (DIT mode) 1  
Right (odd TDM time slot) channel user data register (DIT mode) 2  
Right (odd TDM time slot) channel user data register (DIT mode) 3  
Right (odd TDM time slot) channel user data register (DIT mode) 4  
Right (odd TDM time slot) channel user data register (DIT mode) 5  
Serializer control register 0  
SRCTL1  
Serializer control register 1  
SRCTL2  
Serializer control register 2  
SRCTL3  
Serializer control register 3  
SRCTL4  
Serializer control register 4  
SRCTL5  
Serializer control register 5  
SRCTL6  
Serializer control register 6  
SRCTL7  
Serializer control register 7  
SRCTL8  
Serializer control register 8  
SRCTL9  
Serializer control register 9  
SRCTL10  
SRCTL11  
SRCTL12  
SRCTL13  
SRCTL14  
SRCTL15  
Serializer control register 10  
Serializer control register 11  
Serializer control register 12  
Serializer control register 13  
Serializer control register 14  
Serializer control register 15  
118  
Specifications  
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Table 4-49. McASP Registers Accessed Through Peripheral Configuration Port (continued)  
BYTE ADDRESS  
0x01D0 0200  
0x01D0 0204  
0x01D0 0208  
0x01D0 020C  
0x01D0 0210  
0x01D0 0214  
0x01D0 0218  
0x01D0 021C  
0x01D0 0220  
0x01D0 0224  
0x01D0 0228  
0x01D0 022C  
0x01D0 0230  
0x01D0 0234  
0x01D0 0238  
0x01D0 023C  
0x01D0 0280  
0x01D0 0284  
0x01D0 0288  
0x01D0 028C  
0x01D0 0290  
0x01D0 0294  
0x01D0 0298  
0x01D0 029C  
0x01D0 02A0  
0x01D0 02A4  
0x01D0 02A8  
0x01D0 02AC  
0x01D0 02B0  
0x01D0 02B4  
0x01D0 02B8  
0x01D0 02BC  
ACRONYM  
XBUF0(1)  
XBUF1(1)  
XBUF2(1)  
XBUF3(1)  
XBUF4(1)  
XBUF5(1)  
XBUF6(1)  
XBUF7(1)  
XBUF8(1)  
XBUF9(1)  
XBUF10(1)  
XBUF11(1)  
XBUF12(1)  
XBUF13(1)  
XBUF14(1)  
XBUF15(1)  
RBUF0(2)  
RBUF1(2)  
RBUF2(2)  
RBUF3(2)  
RBUF4(2)  
RBUF5(2)  
RBUF6(2)  
RBUF7(2)  
RBUF8(2)  
RBUF9(2)  
RBUF10(2)  
RBUF11(2)  
RBUF12(2)  
RBUF13(2)  
RBUF14(2)  
RBUF15(2)  
REGISTER DESCRIPTION  
Transmit buffer register for serializer 0  
Transmit buffer register for serializer 1  
Transmit buffer register for serializer 2  
Transmit buffer register for serializer 3  
Transmit buffer register for serializer 4  
Transmit buffer register for serializer 5  
Transmit buffer register for serializer 6  
Transmit buffer register for serializer 7  
Transmit buffer register for serializer 8  
Transmit buffer register for serializer 9  
Transmit buffer register for serializer 10  
Transmit buffer register for serializer 11  
Transmit buffer register for serializer 12  
Transmit buffer register for serializer 13  
Transmit buffer register for serializer 14  
Transmit buffer register for serializer 15  
Receive buffer register for serializer 0  
Receive buffer register for serializer 1  
Receive buffer register for serializer 2  
Receive buffer register for serializer 3  
Receive buffer register for serializer 4  
Receive buffer register for serializer 5  
Receive buffer register for serializer 6  
Receive buffer register for serializer 7  
Receive buffer register for serializer 8  
Receive buffer register for serializer 9  
Receive buffer register for serializer 10  
Receive buffer register for serializer 11  
Receive buffer register for serializer 12  
Receive buffer register for serializer 13  
Receive buffer register for serializer 14  
Receive buffer register for serializer 15  
(1) Writes to XRBUF originate from peripheral configuration port only when XBUSEL = 1 in XFMT.  
(2) Reads from XRBUF originate on peripheral configuration port only when RBUSEL = 1 in RFMT.  
Table 4-50. McASP Registers Accessed Through DMA Port  
ACCESS  
TYPE  
BYTE  
ADDRESS  
ACRONYM REGISTER DESCRIPTION  
Read  
Accesses  
0x01D0 2000  
RBUF  
XBUF  
Receive buffer DMA port address. Cycles through receive serializers, skipping over transmit  
serializers and inactive serializers. Starts at the lowest serializer at the beginning of each  
time slot. Reads from DMA port only if XBUSEL = 0 in XFMT.  
Write  
Accesses  
0x01D0 2000  
Transmit buffer DMA port address. Cycles through transmit serializers, skipping over receive  
and inactive serializers. Starts at the lowest serializer at the beginning of each time slot.  
Writes to DMA port only if RBUSEL = 0 in RFMT.  
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Specifications  
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Table 4-51. McASP AFIFO Registers Accessed Through Peripheral Configuration Port  
BYTE ADDRESS  
0x01D0 1000  
0x01D0 1010  
0x01D0 1014  
0x01D0 1018  
0x01D0 101C  
ACRONYM  
AFIFOREV  
WFIFOCTL  
WFIFOSTS  
RFIFOCTL  
RFIFOSTS  
REGISTER DESCRIPTION  
AFIFO revision identification register  
Write FIFO control register  
Write FIFO status register  
Read FIFO control register  
Read FIFO status register  
4.7.6.8.2 McASP Electrical Data/Timing  
4.7.6.8.2.1 Multichannel Audio Serial Port 0 (McASP0) Timing  
Table 4-52 and Table 4-54 assume testing over recommended operating conditions (see Figure 4-33 and  
Figure 4-34).  
Table 4-52. Timing Requirements for McASP0 (1.3V, 1.2V, 1.1V)(1)(2)  
1.3V, 1.2V  
MIN MAX  
1.1V  
NO.  
UNIT  
MIN  
28  
MAX  
1
2
3
4
tc(AHCLKRX)  
tw(AHCLKRX)  
tc(ACLKRX)  
tw(ACLKRX)  
Cycle time, AHCLKR/X  
25  
12.5  
25(3)  
12.5  
11.5  
4
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Pulse duration, AHCLKR/X high or low  
Cycle time, ACLKR/X  
14  
AHCLKR/X ext  
28(3)  
14  
12  
5
Pulse duration, ACLKR/W high or low AHCLKR/X ext  
AHCLKR/X int  
Setup time,  
5
tsu(AFSRX-ACLKRX)  
AHCLKR/X ext input  
AFSR/X input to ACLKR/X(4)  
AHCLKR/X ext output  
AHCLKR/X int  
4
5
-1  
-2  
1
Hold time,  
6
7
8
th(ACLKRX-AFSRX)  
tsu(AXR-ACLKRX)  
th(ACLKRX-AXR)  
AHCLKR/X ext input  
AHCLKR/X ext output  
AHCLKR/X int  
1
AFSR/X input after ACLKR/X(4)  
1
1
11.5  
4
12  
5
Setup time,  
AXR0[n] input to ACLKR/X(4)(5)  
AHCLKR/X ext  
AHCLKR/X int  
-1  
-2  
4
Hold time,  
AHCLKR/X ext input  
AHCLKR/X ext output  
3
AXR0[n] input after ACLKR/X(4)(5)  
3
4
(1) ACLKX0 internal – McASP0 ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1  
ACLKX0 external input – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0  
ACLKX0 external output – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1  
ACLKR0 internal – McASP0 ACLKRCTL.CLKRM = 1, PDIR.ACLKR =1  
ACLKR0 external input – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0  
ACLKR0 external output – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1  
(2) P = SYSCLK2 period  
(3) This timing is limited by the timing shown or 2P, whichever is greater.  
(4) McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0  
(5) McASP0 ACLKXCTL.ASYNC=0: Receiver is clocked by transmitter's ACLKX0  
120  
Specifications  
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Table 4-53. Timing Requirements for McASP0 (1.0V)(1)(2)  
1.0V  
NO.  
UNIT  
MIN  
35  
17.5  
35(3)  
17.5  
16  
5.5  
5.5  
-2  
MAX  
1
2
3
4
tc(AHCLKRX)  
Cycle time, AHCLKR/X  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tw(AHCLKRX)  
tc(ACLKRX)  
tw(ACLKRX)  
Pulse duration, AHCLKR/X high or low  
Cycle time, ACLKR/X  
AHCLKR/X ext  
Pulse duration, ACLKR/W high or low  
AHCLKR/X ext  
AHCLKR/X int  
Setup time,  
5
tsu(AFSRX-ACLKRX)  
AHCLKR/X ext input  
AHCLKR/X ext output  
AHCLKR/X int  
AFSR/X input to ACLKR/X(4)  
Hold time,  
6
7
8
th(ACLKRX-AFSRX)  
tsu(AXR-ACLKRX)  
th(ACLKRX-AXR)  
AHCLKR/X ext input  
AHCLKR/X ext output  
AHCLKR/X int  
1
AFSR/X input after ACLKR/X(4)  
1
16  
5.5  
-2  
Setup time,  
AXR0[n] input to ACLKR/X(4)(5)  
AHCLKR/X ext  
AHCLKR/X int  
Hold time,  
AHCLKR/X ext input  
AHCLKR/X ext output  
5
AXR0[n] input after ACLKR/X(4)(5)  
5
(1) ACLKX0 internal – McASP0 ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1  
ACLKX0 external input – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0  
ACLKX0 external output – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1  
ACLKR0 internal – McASP0 ACLKRCTL.CLKRM = 1, PDIR.ACLKR =1  
ACLKR0 external input – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0  
ACLKR0 external output – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1  
(2) P = SYSCLK2 period  
(3) This timing is limited by the timing shown or 2P, whichever is greater.  
(4) McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0  
(5) McASP0 ACLKXCTL.ASYNC=0: Receiver is clocked by transmitter's ACLKX0  
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Specifications  
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Table 4-54. Switching Characteristics for McASP0 (1.3V, 1.2V, 1.1V)(1)  
1.3V, 1.2V  
1.1V  
NO.  
PARAMETER  
UNIT  
MAX  
MIN  
MAX  
MIN  
9
tc(AHCLKRX)  
Cycle time, AHCLKR/X  
25  
28  
ns  
ns  
ns  
ns  
10 tw(AHCLKRX)  
11 tc(ACLKRX)  
12 tw(ACLKRX)  
Pulse duration, AHCLKR/X high or low  
Cycle time, ACLKR/X  
AH – 2.5(2)  
25(3)(4)  
A – 2.5(5)  
AH – 2.5(2)  
28(3)(4)  
A – 2.5(5)  
ACLKR/X int  
Pulse duration, ACLKR/X high or low ACLKR/X int  
ACLKR/X int  
-1  
2
6
-1  
2
8
14.5  
14.5  
8
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Delay time, ACLKR/X transmit edge  
13 td(ACLKRX-AFSRX)  
ACLKR/X ext input  
13.5  
13.5  
6
to AFSX/R output valid(6)  
ACLKR/X ext output  
ACLKR/X int  
2
2
-1  
2
-1  
2
Delay time, ACLKX transmit edge to  
AXR output valid  
14 td(ACLKX-AXRV)  
ACLKR/X ext input  
ACLKR/X ext output  
ACLKR/X int  
13.5  
13.5  
6
15  
15  
8
2
2
Disable time, ACLKR/X transmit  
edge to AXR high impedance  
following last data bit  
0
0
15 tdis(ACLKX-AXRHZ)  
ACLKR/X ext  
2
13.5  
2
15  
ns  
(1) McASP0 ACLKX0 internal – ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1  
ACLKX0 external input – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0  
ACLKX0 external output – McASP0ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1  
ACLKR0 internal – McASP0 ACLKR0CTL.CLKRM = 1, PDIR.ACLKR =1  
ACLKR0 external input – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0  
ACLKR0 external output – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1  
(2) AH = (AHCLKR/X period)/2 in ns. For example, when AHCLKR/X period is 25 ns, use AH = 12.5 ns.  
(3) P = SYSCLK2 period  
(4) This timing is limited by the timing shown or 2P, whichever is greater.  
(5) A = (ACLKR/X period)/2 in ns. For example, when AHCLKR/X period is 25 ns, use AH = 12.5 ns.  
(6) McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0  
Table 4-55. Switching Characteristics for McASP0 (1.0V)(1)  
1.0V  
NO.  
PARAMETER  
UNIT  
MIN  
MAX  
9
tc(AHCLKRX)  
Cycle time, AHCLKR/X  
35  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
10 tw(AHCLKRX)  
11 tc(ACLKRX)  
12 tw(ACLKRX)  
Pulse duration, AHCLKR/X high or low  
AH – 2.5(2)  
35(3)(4)  
A – 2.5(5)  
Cycle time, ACLKR/X  
ACLKR/X int  
Pulse duration, ACLKR/X high or low  
ACLKR/X int  
ACLKR/X int  
-0.5  
2
10  
19  
19  
10  
19  
19  
10  
19  
Delay time, ACLKR/X transmit edge to AFSX/R output  
valid(6)  
13 td(ACLKRX-AFSRX)  
ACLKR/X ext input  
ACLKR/X ext output  
ACLKR/X int  
2
-0.5  
2
14 td(ACLKX-AXRV)  
Delay time, ACLKX transmit edge to AXR output valid  
ACLKR/X ext input  
ACLKR/X ext output  
ACLKR/X int  
2
0
Disable time, ACLKR/X transmit edge to AXR high  
impedance following last data bit  
15 tdis(ACLKX-AXRHZ)  
ACLKR/X ext  
2
(1) McASP0 ACLKX0 internal – ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1  
ACLKX0 external input – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0  
ACLKX0 external output – McASP0ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1  
ACLKR0 internal – McASP0 ACLKR0CTL.CLKRM = 1, PDIR.ACLKR =1  
ACLKR0 external input – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0  
ACLKR0 external output – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1  
(2) AH = (AHCLKR/X period)/2 in ns. For example, when AHCLKR/X period is 25 ns, use AH = 12.5 ns.  
(3) P = SYSCLK2 period  
(4) This timing is limited by the timing shown or 2P, whichever is greater.  
(5) A = (ACLKR/X period)/2 in ns. For example, when AHCLKR/X period is 25 ns, use AH = 12.5 ns.  
(6) McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0  
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2
1
2
AHCLKR/X (Falling Edge Polarity)  
AHCLKR/X (Rising Edge Polarity)  
4
3
4
(A)  
ACLKR/X (CLKRP = CLKXP = 0)  
(B)  
ACLKR/X (CLKRP = CLKXP = 1)  
6
5
AFSR/X (Bit Width, 0 Bit Delay)  
AFSR/X (Bit Width, 1 Bit Delay)  
AFSR/X (Bit Width, 2 Bit Delay)  
AFSR/X (Slot Width, 0 Bit Delay)  
AFSR/X (Slot Width, 1 Bit Delay)  
AFSR/X (Slot Width, 2 Bit Delay)  
8
7
AXR[n] (Data In/Receive)  
A0 A1  
A30 A31 B0 B1  
B30 B31 C0 C1 C2 C3  
C31  
A. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP  
receiver is configured for falling edge (to shift data in).  
B. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP  
receiver is configured for rising edge (to shift data in).  
Figure 4-33. McASP Input Timings  
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10  
10  
9
AHCLKR/X (Falling Edge Polarity)  
AHCLKR/X (Rising Edge Polarity)  
12  
11  
12  
(A)  
ACLKR/X (CLKRP = CLKXP = 1)  
(B)  
ACLKR/X (CLKRP = CLKXP = 0)  
13  
13  
13  
13  
AFSR/X (Bit Width, 0 Bit Delay)  
AFSR/X (Bit Width, 1 Bit Delay)  
AFSR/X (Bit Width, 2 Bit Delay)  
AFSR/X (Slot Width, 0 Bit Delay)  
AFSR/X (Slot Width, 1 Bit Delay)  
AFSR/X (Slot Width, 2 Bit Delay)  
AXR[n] (Data Out/Transmit)  
13  
13  
13  
14  
15  
A0 A1  
A30 A31 B0 B1  
B30 B31 C0 C1 C2 C3  
C31  
A. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP  
receiver is configured for rising edge (to shift data in).  
B. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP  
receiver is configured for falling edge (to shift data in).  
Figure 4-34. McASP Output Timings  
124  
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4.7.6.9 Multichannel Buffered Serial Port (McBSP)  
The McBSP provides these functions:  
•
•
•
•
Full-duplex communication  
Double-buffered data registers, which allow a continuous data stream  
Independent framing and clocking for receive and transmit  
Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially  
connected analog-to-digital (A/D) and digital-to-analog (D/A) devices  
•
•
External shift clock or an internal, programmable frequency shift clock for data transfer  
Transmit & Receive FIFO Buffers allow the McBSP to operate at a higher sample rate by making it  
more tolerant to DMA latency  
If internal clock source is used, the CLKGDV field of the Sample Rate Generator Register (SRGR) must  
always be set to a value of 1 or greater.  
4.7.6.9.1 McBSP Peripheral Register Description(s)  
Table 4-56. McBSP/FIFO Registers  
McBSP0  
BYTE ADDRESS  
McBSP1  
BYTE ADDRESS  
ACRONYM  
REGISTER DESCRIPTION  
McBSP Registers  
McBSP Data Receive Register (read-only)  
0x01D1 0000  
0x01D1 0004  
0x01D1 0008  
0x01D1 000C  
0x01D1 0010  
0x01D1 0014  
0x01D1 0018  
0x01D1 001C  
0x01D1 0020  
0x01D1 0024  
0x01D1 0028  
0x01D1 002C  
0x01D1 0030  
0x01D1 0034  
0x01D1 0038  
0x01D1 003C  
0x01D1 1000  
0x01D1 1004  
0x01D1 1008  
0x01D1 100C  
0x01D1 1010  
0x01D1 1014  
0x01D1 1018  
0x01D1 101C  
0x01D1 1020  
0x01D1 1024  
0x01D1 1028  
0x01D1 102C  
0x01D1 1030  
0x01D1 1034  
0x01D1 1038  
0x01D1 103C  
DRR  
DXR  
McBSP Data Transmit Register  
SPCR  
McBSP Serial Port Control Register  
RCR  
McBSP Receive Control Register  
XCR  
McBSP Transmit Control Register  
SRGR  
McBSP Sample Rate Generator register  
MCR  
McBSP Multichannel Control Register  
RCERE0  
XCERE0  
PCR  
McBSP Enhanced Receive Channel Enable Register 0 Partition A/B  
McBSP Enhanced Transmit Channel Enable Register 0 Partition A/B  
McBSP Pin Control Register  
RCERE1  
XCERE1  
RCERE2  
XCERE2  
RCERE3  
XCERE3  
McBSP Enhanced Receive Channel Enable Register 1 Partition C/D  
McBSP Enhanced Transmit Channel Enable Register 1 Partition C/D  
McBSP Enhanced Receive Channel Enable Register 2 Partition E/F  
McBSP Enhanced Transmit Channel Enable Register 2 Partition E/F  
McBSP Enhanced Receive Channel Enable Register 3 Partition G/H  
McBSP Enhanced Transmit Channel Enable Register 3 Partition G/H  
McBSP FIFO Control and Status Registers  
0x01D1 0800  
0x01D1 0810  
0x01D1 0814  
0x01D1 0818  
0x01D1 081C  
0x01D1 1800  
0x01D1 1810  
0x01D1 1814  
0x01D1 1818  
0x01D1 181C  
BFIFOREV  
WFIFOCTL  
WFIFOSTS  
RFIFOCTL  
RFIFOSTS  
BFIFO Revision Identification Register  
Write FIFO Control Register  
Write FIFO Status Register  
Read FIFO Control Register  
Read FIFO Status Register  
McBSP FIFO Data Registers  
0x01F1 0000  
0x01F1 0000  
0x01F1 1000  
0x01F1 1000  
RBUF  
XBUF  
McBSP FIFO Receive Buffer  
McBSP FIFO Transmit Buffer  
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4.7.6.9.2 McBSP Electrical Data/Timing  
The following assume testing over recommended operating conditions.  
4.7.6.9.2.1 Multichannel Buffered Serial Port (McBSP) Timing  
Table 4-57. Timing Requirements for McBSP0 [1.3V, 1.2V, 1.1V](1) (see Figure 4-35)  
1.3V, 1.2V  
1.1V  
NO.  
UNIT  
MAX  
MIN  
MAX  
MIN  
2
3
tc(CKRX)  
tw(CKRX)  
Cycle time, CLKR/X  
CLKR/X ext 2P or 20(2)(3)  
2P or 25(2)(3)  
ns  
ns  
Pulse duration, CLKR/X high or CLKR/X low  
CLKR/X ext  
CLKR int  
CLKR ext  
CLKR int  
CLKR ext  
CLKR int  
CLKR ext  
CLKR int  
CLKR ext  
CLKX int  
CLKX ext  
CLKX int  
CLKX ext  
P - 1(4)  
P - 1(4)  
14  
4
15.5  
Setup time, external FSR high before CLKR  
low  
5
6
7
8
tsu(FRH-CKRL)  
ns  
ns  
ns  
ns  
ns  
ns  
5
6
6
th(CKRL-FRH) Hold time, external FSR high after CLKR low  
tsu(DRV-CKRL) Setup time, DR valid before CLKR low  
3
3
14  
4
15.5  
5
3
3
th(CKRL-DRV) Hold time, DR valid after CLKR low  
Setup time, external FSX high before CLKX  
3
3
14  
4
15.5  
5
10 tsu(FXH-CKXL)  
low  
6
6
11 th(CKXL-FXH) Hold time, external FSX high after CLKX low  
3
3
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also  
inverted.  
(2) P = ASYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns.  
(3) Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock  
source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA  
limitations and AC timing requirements.  
(4) This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.  
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Table 4-58. Timing Requirements for McBSP0 [1.0V](1) (see Figure 4-35)  
1.0V  
NO.  
UNIT  
MIN  
MAX  
2
3
tc(CKRX)  
tw(CKRX)  
Cycle time, CLKR/X  
CLKR/X ext  
CLKR/X ext  
CLKR int  
CLKR ext  
CLKR int  
CLKR ext  
CLKR int  
CLKR ext  
CLKR int  
CLKR ext  
CLKX int  
CLKX ext  
CLKX int  
CLKX ext  
2P or 26.6(2)(3)  
ns  
ns  
Pulse duration, CLKR/X high or CLKR/X low  
P - 1(4)  
20  
5
5
6
7
8
tsu(FRH-CKRL) Setup time, external FSR high before CLKR low  
th(CKRL-FRH) Hold time, external FSR high after CLKR low  
tsu(DRV-CKRL) Setup time, DR valid before CLKR low  
th(CKRL-DRV) Hold time, DR valid after CLKR low  
ns  
ns  
ns  
ns  
ns  
ns  
6
3
20  
5
3
3
20  
5
10 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low  
11 th(CKXL-FXH) Hold time, external FSX high after CLKX low  
6
3
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also  
inverted.  
(2) P = ASYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns.  
(3) Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock  
source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA  
limitations and AC timing requirements.  
(4) This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.  
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Table 4-59. Switching Characteristics for McBSP0 [1.3V, 1.2V, 1.1V](1)(2)  
(see Figure 4-35)  
1.3V, 1.2V  
1.1V  
NO.  
PARAMETER  
UNIT  
MIN  
2
MAX  
MIN  
MAX  
td(CKSH-  
Delay time, CLKS high to CLKR/X high for internal  
CLKR/X generated from CLKS input  
1
2
3
14.5  
2
16  
ns  
ns  
ns  
CKRXH)  
tc(CKRX)  
tw(CKRX)  
Cycle time, CLKR/X  
CLKR/X int  
CLKR/X int  
2P or 20(3)(4)(5)  
C - 2(6)  
2P or 25(3)(4)(5)  
C - 2(6)  
Pulse duration, CLKR/X high or  
CLKR/X low  
C + 2(6)  
C + 2(6)  
CLKR int  
CLKR ext  
CLKX int  
CLKX ext  
CLKX int  
CLKX ext  
CLKX int  
CLKX ext  
FSX int  
-4  
5.5  
14.5  
-4  
5.5  
16  
Delay time, CLKR high to internal FSR  
valid  
4
9
td(CKRH-FRV)  
ns  
ns  
ns  
ns  
2
2
-4  
-4  
5.5  
5.5  
Delay time, CLKX high to internal FSX  
valid  
td(CKXH-FXV)  
2
-4  
14.5  
2
16  
7.5  
-5.5  
7.5  
tdis(CKXH-  
Disable time, DX high impedance  
following last data bit from CLKX high  
12  
13  
DXHZ)  
-2  
16  
-22  
16  
-4 + D1(7)  
2 + D1(7)  
-4(8)  
5.5 + D2(7)  
14.5 + D2(7)  
5(8)  
-4 + D1(7)  
2 + D1(7)  
-4(8)  
5.5 + D2(7)  
16 + D2(7)  
5(8)  
td(CKXH-DXV)  
Delay time, CLKX high to DX valid  
Delay time, FSX high to DX valid  
14  
td(FXH-DXV)  
ns  
ONLY applies when in data  
delay 0 (XDATDLY = 00b) mode  
FSX ext  
-2(8)  
14.5(8)  
-2(8)  
16(8)  
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also  
inverted.  
(2) Minimum delay times also represent minimum output hold times.  
(3) Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times  
are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements.  
(4) P = ASYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns.  
(5) Use whichever value is greater.  
(6) C = H or L  
S = sample rate generator input clock = P if CLKSM = 1 (P = ASYNC period)  
S = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)  
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even  
H = (CLKGDV + 1)/2 * S if CLKGDV is odd  
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even  
L = (CLKGDV + 1)/2 * S if CLKGDV is odd  
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see (4) above).  
(7) Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.  
if DXENA = 0, then D1 = D2 = 0  
if DXENA = 1, then D1 = 6P, D2 = 12P  
(8) Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.  
if DXENA = 0, then D1 = D2 = 0  
if DXENA = 1, then D1 = 6P, D2 = 12P  
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Table 4-60. Switching Characteristics for McBSP0 [1.0V](1) (2)  
(see Figure 4-35)  
1.0V  
NO.  
PARAMETER  
UNIT  
MAX  
MIN  
Delay time, CLKS high to CLKR/X high for internal CLKR/X  
generated from CLKS input  
1
td(CKSH-CKRXH)  
3
21.5  
ns  
2
3
tc(CKRX)  
tw(CKRX)  
Cycle time, CLKR/X  
CLKR/X int  
2P or 26.6(3)(4)(5)  
ns  
ns  
Pulse duration, CLKR/X high or CLKR/X low  
CLKR/X int  
CLKR int  
CLKR ext  
CLKX int  
CLKX ext  
CLKX int  
CLKX ext  
CLKX int  
CLKX ext  
FSX int  
C - 2(6)  
C + 2(6)  
10  
-4  
4
9
td(CKRH-FRV)  
Delay time, CLKR high to internal FSR valid  
Delay time, CLKX high to internal FSX valid  
ns  
ns  
ns  
ns  
2.5  
21.5  
-4  
2.5  
10  
td(CKXH-FXV)  
21.5  
-4  
10  
Disable time, DX high impedance following last data  
bit from CLKX high  
12 tdis(CKXH-DXHZ)  
-2  
21.5  
-4 + D1(7)  
2.5 + D1(7)  
-4(8)  
10 + D2(7)  
21.5 + D2(7)  
5(8)  
13 td(CKXH-DXV)  
Delay time, CLKX high to DX valid  
Delay time, FSX high to DX valid  
14 td(FXH-DXV)  
ns  
ONLY applies when in data  
delay 0 (XDATDLY = 00b) mode  
FSX ext  
-2(8)  
21.5(8)  
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also  
inverted.  
(2) Minimum delay times also represent minimum output hold times.  
(3) Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times  
are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements.  
(4) P = ASYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns.  
(5) Use whichever value is greater.  
(6) C = H or L  
S = sample rate generator input clock = P if CLKSM = 1 (P = ASYNC period)  
S = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)  
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even  
H = (CLKGDV + 1)/2 * S if CLKGDV is odd  
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even  
L = (CLKGDV + 1)/2 * S if CLKGDV is odd  
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see (4) above).  
(7) Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.  
if DXENA = 0, then D1 = D2 = 0  
if DXENA = 1, then D1 = 6P, D2 = 12P  
(8) Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.  
if DXENA = 0, then D1 = D2 = 0  
if DXENA = 1, then D1 = 6P, D2 = 12P  
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Table 4-61. Timing Requirements for McBSP1 [1.3V, 1.2V, 1.1V](1) (see Figure 4-35)  
1.3V, 1.2V  
1.1V  
NO.  
UNIT  
MIN  
MAX  
MIN  
MAX  
2
3
tc(CKRX)  
tw(CKRX)  
Cycle time, CLKR/X  
CLKR/X ext  
CLKR/X ext  
2P or 20(2)(3)  
P - 1(5)  
2P or 25(2) (4)  
ns  
ns  
Pulse duration, CLKR/X high or  
CLKR/X low  
P - 1(6)  
CLKR int  
CLKR ext  
CLKR int  
CLKR ext  
CLKR int  
CLKR ext  
CLKR int  
CLKR ext  
CLKX int  
CLKX ext  
CLKX int  
CLKX ext  
15  
5
18  
5
Setup time, external FSR high before  
CLKR low  
5
6
7
8
tsu(FRH-CKRL)  
th(CKRL-FRH)  
tsu(DRV-CKRL)  
th(CKRL-DRV)  
ns  
ns  
ns  
ns  
ns  
ns  
6
6
Hold time, external FSR high after  
CLKR low  
3
3
15  
5
18  
5
Setup time, DR valid before CLKR low  
Hold time, DR valid after CLKR low  
3
3
3
3
15  
5
18  
5
Setup time, external FSX high before  
CLKX low  
10 tsu(FXH-CKXL)  
6
6
Hold time, external FSX high after  
CLKX low  
11 th(CKXL-FXH)  
3
3
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also  
inverted.  
(2) P = ASYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns.  
(3) Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock  
source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA  
limitations and AC timing requirements.  
(4) Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock  
source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA  
limitations and AC timing requirements.  
(5) This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.  
(6) This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.  
Table 4-62. Timing Requirements for McBSP1 [1.0V](1) (see Figure 4-35)  
1.0V  
NO.  
UNIT  
MIN  
MAX  
2
3
tc(CKRX)  
tw(CKRX)  
Cycle time, CLKR/X  
CLKR/X ext  
CLKR/X ext  
CLKR int  
CLKR ext  
CLKR int  
CLKR ext  
CLKR int  
CLKR ext  
CLKR int  
CLKR ext  
CLKX int  
CLKX ext  
CLKX int  
CLKX ext  
2P or 26.6(2)(3)  
ns  
ns  
Pulse duration, CLKR/X high or CLKR/X low  
P - 1(4)  
21  
10  
6
5
6
7
8
tsu(FRH-CKRL)  
th(CKRL-FRH)  
tsu(DRV-CKRL)  
th(CKRL-DRV)  
Setup time, external FSR high before CLKR low  
Hold time, external FSR high after CLKR low  
Setup time, DR valid before CLKR low  
ns  
ns  
ns  
ns  
ns  
ns  
3
21  
10  
3
Hold time, DR valid after CLKR low  
3
21  
10  
6
10 tsu(FXH-CKXL)  
Setup time, external FSX high before CLKX low  
Hold time, external FSX high after CLKX low  
11 th(CKXL-FXH)  
3
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also  
inverted.  
(2) P = ASYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns.  
(3) Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock  
source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA  
limitations and AC timing requirements.  
(4) This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.  
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Table 4-63. Switching Characteristics for McBSP1 [1.3V, 1.2V, 1.1V](1) (2)  
(see Figure 4-35)  
1.3V, 1.2V  
1.1V  
NO.  
PARAMETER  
UNIT  
MIN  
MAX  
MIN  
1.5  
MAX  
Delay time, CLKS high to CLKR/X high for internal  
CLKR/X generated from CLKS input  
1
2
3
td(CKSH-CKRXH)  
tc(CKRX)  
tw(CKRX)  
0.5  
16.5  
18  
ns  
ns  
ns  
(5)  
Cycle time, CLKR/X  
CLKR/X int  
CLKR/X int  
2P or 20(3)(4)(5)  
C - 2(6)  
2P or 25(3)(4)  
C - 2(6)  
Pulse duration, CLKR/X high or  
CLKR/X low  
C + 2(6)  
C + 2(6)  
CLKR int  
CLKR ext  
CLKX int  
CLKX ext  
CLKX int  
-4  
1
6.5  
16.5  
6.5  
-4  
1
13  
18  
13  
18  
13  
Delay time, CLKR high to internal  
FSR valid  
4
9
td(CKRH-FRV)  
ns  
ns  
-4  
1
-4  
1
Delay time, CLKX high to internal  
FSX valid  
td(CKXH-FXV)  
16.5  
6.5  
Disable time, DX high impedance  
following last data bit from CLKX  
high  
-4  
-4  
12  
13  
tdis(CKXH-DXHZ)  
ns  
ns  
CLKX ext  
-2  
16.5  
-2  
18  
CLKX int  
CLKX ext  
FSX int  
-4 + D1(7)  
1 + D1(7)  
-4(8)  
6.5 + D2(7)  
16.5 + D2(7)  
6.5(8)  
-4 + D1(7)  
1 + D1(7)  
-4(8)  
13 + D2(7)  
18 + D2(7)  
13(8)  
td(CKXH-DXV)  
Delay time, CLKX high to DX valid  
Delay time, FSX high to DX valid  
14  
td(FXH-DXV)  
ns  
ONLY applies when in data  
delay 0 (XDATDLY = 00b) mode  
FSX ext  
-2(8)  
16.5(8)  
-2(8)  
18(9)  
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also  
inverted.  
(2) Minimum delay times also represent minimum output hold times.  
(3) Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times  
are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements.  
(4) P = ASYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns.  
(5) Use whichever value is greater.  
(6) C = H or L  
S = sample rate generator input clock = P if CLKSM = 1 (P = ASYNC period)  
S = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)  
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even  
H = (CLKGDV + 1)/2 * S if CLKGDV is odd  
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even  
L = (CLKGDV + 1)/2 * S if CLKGDV is odd  
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see (4) above).  
(7) Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.  
if DXENA = 0, then D1 = D2 = 0  
if DXENA = 1, then D1 = 6P, D2 = 12P  
(8) Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.  
if DXENA = 0, then D1 = D2 = 0  
if DXENA = 1, then D1 = 6P, D2 = 12P  
(9) Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.  
if DXENA = 0, then D1 = D2 = 0  
if DXENA = 1, then D1 = 6P, D2 = 12P  
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Table 4-64. Switching Characteristics for McBSP1 [1.0V](1) (2)  
(see Figure 4-35)  
1.0V  
NO.  
PARAMETER  
UNIT  
MIN  
MAX  
Delay time, CLKS high to CLKR/X high for internal CLKR/X  
generated from CLKS input  
1
td(CKSH-CKRXH)  
1.5  
23  
ns  
ns  
2
3
tc(CKRX)  
tw(CKRX)  
Cycle time, CLKR/X  
CLKR/X int  
2P or 26.6(3)(4)(5)  
Pulse duration, CLKR/X high or CLKR/X low  
CLKR/X int  
CLKR int  
CLKR ext  
CLKX int  
CLKX ext  
CLKX int  
CLKX ext  
CLKX int  
CLKX ext  
FSX int  
C - 2(6)  
C + 2(6)  
ns  
-4  
13  
23  
4
9
td(CKRH-FRV)  
Delay time, CLKR high to internal FSR valid  
Delay time, CLKX high to internal FSX valid  
ns  
2.5  
-4  
13  
td(CKXH-FXV)  
ns  
ns  
ns  
1
-4  
23  
13  
Disable time, DX high impedance following last data  
bit from CLKX high  
12 tdis(CKXH-DXHZ)  
-2  
23  
-4 + D1(7)  
1 + D1(8)  
-4(9)  
13 + D2(8)  
23 + D2(8)  
13(9)  
13 td(CKXH-DXV)  
Delay time, CLKX high to DX valid  
Delay time, FSX high to DX valid  
14 td(FXH-DXV)  
ns  
ONLY applies when in data  
delay 0 (XDATDLY = 00b) mode  
FSX ext  
-2(9)  
23(9)  
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also  
inverted.  
(2) Minimum delay times also represent minimum output hold times.  
(3) Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times  
are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements.  
(4) P = ASYNC3 period in ns. For example, when the ASYNC clock domain is running at 100 MHz, use 10 ns.  
(5) Use whichever value is greater.  
(6) C = H or L  
S = sample rate generator input clock = P if CLKSM = 1 (P = ASYNC period)  
S = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)  
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even  
H = (CLKGDV + 1)/2 * S if CLKGDV is odd  
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even  
L = (CLKGDV + 1)/2 * S if CLKGDV is odd  
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see (4) above).  
(7) Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.  
if DXENA = 0, then D1 = D2 = 0  
if DXENA = 1, then D1 = 6P, D2 = 12P  
(8) Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.  
if DXENA = 0, then D1 = D2 = 0  
if DXENA = 1, then D1 = 6P, D2 = 12P  
(9) Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.  
if DXENA = 0, then D1 = D2 = 0  
if DXENA = 1, then D1 = 6P, D2 = 12P  
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CLKS  
1
2
3
3
CLKR  
FSR (int)  
FSR (ext)  
DR  
4
4
5
6
7
3
8
Bit(n1)  
(n2)  
(n3)  
2
3
CLKX  
9
FSX (int)  
11  
10  
FSX (ext)  
FSX (XDATDLY=00b)  
13 (A)  
14  
12  
13 (A)  
DX  
Bit 0  
Bit(n1)  
(n2)  
(n3)  
A. No. 13 applies to the first data bit only when XDATDLY ≠ 0.  
Figure 4-35. McBSP Timing  
Table 4-65. Timing Requirements for McBSP0 FSR When GSYNC = 1 (see Figure 4-36)  
1.3V, 1.2V  
MIN MAX  
1.1V  
1.0V  
NO.  
UNIT  
MIN  
4.5  
4
MAX  
MIN  
5
MAX  
1
2
tsu(FRH-CKSH)  
th(CKSH-FRH)  
Setup time, FSR high before CLKS high  
Hold time, FSR high after CLKS high  
4
4
ns  
ns  
4
Table 4-66. Timing Requirements for McBSP1 FSR When GSYNC = 1 (see Figure 4-36)  
1.3V, 1.2V  
MIN MAX  
1.1V  
1.0V  
NO.  
UNIT  
MIN  
5
MAX  
MIN  
10  
4
MAX  
1
2
tsu(FRH-CKSH)  
th(CKSH-FRH)  
Setup time, FSR high before CLKS high  
Hold time, FSR high after CLKS high  
5
4
ns  
ns  
4
CLKS  
1
2
FSR external  
CLKR/X (no need to resync)  
CLKR/X (needs resync)  
Figure 4-36. FSR Timing When GSYNC = 1  
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4.7.6.10 Serial Peripheral Interface Ports (SPI0, SPI1)  
Figure 4-37 is a block diagram of the SPI module, which is a simple shift register and buffer plus control  
logic. Data is written to the shift register before transmission occurs and is read from the buffer at the end  
of transmission. The SPI can operate either as a master, in which case, it initiates a transfer and drives  
the SPIx_CLK pin, or as a slave. Four clock phase and polarity options are supported as well as many  
data formatting options.  
SPIx_SIMO  
SPIx_SOMI  
Peripheral  
Configuration Bus  
16-Bit Shift Register  
16-Bit Buffer  
SPIx_ENA  
SPIx_SCS  
SPIx_CLK  
State  
Machine  
GPIO  
Control  
(all pins)  
Interrupt and  
DMA Requests  
Clock  
Control  
Figure 4-37. Block Diagram of SPI Module  
The SPI supports 3-, 4-, and 5-pin operation with three basic pins (SPIx_CLK, SPIx_SIMO, and  
SPIx_SOMI) and two optional pins (SPIx_SCS, SPIx_ENA).  
The optional SPIx_SCS (Slave Chip Select) pin is most useful to enable in slave mode when there are  
other slave devices on the same SPI port. The device will only shift data and drive the SPIx_SOMI pin  
when SPIx_SCS is held low.  
In slave mode, SPIx_ENA is an optional output. The SPIx_ENA output provides the status of the internal  
transmit buffer (SPIDAT0/1 registers). In four-pin mode with the enable option, SPIx_ENA is asserted only  
when the transmit buffer is full, indicating that the slave is ready to begin another transfer. In five-pin  
mode, the SPIx_ENA is additionally qualified by SPIx_SCS being asserted. This allows a single  
handshake line to be shared by multiple slaves on the same SPI bus.  
In master mode, the SPIx_ENA pin is an optional input and the master can be configured to delay the start  
of the next transfer until the slave asserts SPIx_ENA. The addition of this handshake signal simplifies SPI  
communications and, on average, increases SPI bus throughput since the master does not need to delay  
each transfer long enough to allow for the worst-case latency of the slave device. Instead, each transfer  
can begin as soon as both the master and slave have actually serviced the previous SPI transfer.  
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Optional − Slave Chip Select  
Optional Enable (Ready)  
SPIx_SCS  
SPIx_ENA  
SPIx_CLK  
SPIx_SOMI  
SPIx_SIMO  
SPIx_SCS  
SPIx_ENA  
SPIx_CLK  
SPIx_SOMI  
SPIx_SIMO  
MASTER SPI  
SLAVE SPI  
Figure 4-38. Illustration of SPI Master-to-SPI Slave Connection  
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4.7.6.10.1 SPI Peripheral Registers Description(s)  
Table 4-67 is a list of the SPI registers.  
Table 4-67. SPIx Configuration Registers  
SPI0  
BYTE ADDRESS  
SPI1  
ACRONYM  
DESCRIPTION  
Global Control Register 0  
BYTE ADDRESS  
0x01F0 E000  
0x01F0 E004  
0x01F0 E008  
0x01F0 E00C  
0x01F0 E010  
0x01F0 E014  
0x01F0 E018  
0x01F0 E01C  
0x01F0 E020  
0x01F0 E024  
0x01F0 E028  
0x01F0 E02C  
0x01F0 E030  
0x01F0 E034  
0x01F0 E038  
0x01F0 E03C  
0x01F0 E040  
0x01F0 E044  
0x01F0 E048  
0x01F0 E04C  
0x01F0 E050  
0x01F0 E054  
0x01F0 E058  
0x01F0 E05C  
0x01F0 E060  
0x01F0 E064  
0x01C4 1000  
0x01C4 1004  
0x01C4 1008  
0x01C4 100C  
0x01C4 1010  
0x01C4 1014  
0x01C4 1018  
0x01C4 101C  
0x01C4 1020  
0x01C4 1024  
0x01C4 1028  
0x01C4 102C  
0x01C4 1030  
0x01C4 1034  
0x01C4 1038  
0x01C4 103C  
0x01C4 1040  
0x01C4 1044  
0x01C4 1048  
0x01C4 104C  
0x01C4 1050  
0x01C4 1054  
0x01C4 1058  
0x01C4 105C  
0x01C4 1060  
0x01C4 1064  
SPIGCR0  
SPIGCR1  
SPIINT0  
SPILVL  
Global Control Register 1  
Interrupt Register  
Interrupt Level Register  
SPIFLG  
Flag Register  
SPIPC0  
Pin Control Register 0 (Pin Function)  
Pin Control Register 1 (Pin Direction)  
Pin Control Register 2 (Pin Data In)  
Pin Control Register 3 (Pin Data Out)  
Pin Control Register 4 (Pin Data Set)  
Pin Control Register 5 (Pin Data Clear)  
Reserved - Do not write to this register  
Reserved - Do not write to this register  
Reserved - Do not write to this register  
Shift Register 0 (without format select)  
Shift Register 1 (with format select)  
Buffer Register  
SPIPC1  
SPIPC2  
SPIPC3  
SPIPC4  
SPIPC5  
Reserved  
Reserved  
Reserved  
SPIDAT0  
SPIDAT1  
SPIBUF  
SPIEMU  
SPIDELAY  
SPIDEF  
Emulation Register  
Delay Register  
Default Chip Select Register  
Format Register 0  
SPIFMT0  
SPIFMT1  
SPIFMT2  
SPIFMT3  
INTVEC0  
INTVEC1  
Format Register 1  
Format Register 2  
Format Register 3  
Interrupt Vector for SPI INT0  
Interrupt Vector for SPI INT1  
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4.7.6.10.2 SPI Electrical Data/Timing  
4.7.6.10.2.1 Serial Peripheral Interface (SPI) Timing  
Table 4-68 through Table 4-83 assume testing over recommended operating conditions (see Figure 4-39  
through Figure 4-42).  
Table 4-68. General Timing Requirements for SPI0 Master Modes(1)  
1.3V, 1.2V  
1.1V  
1.0V  
NO.  
UNIT  
MIN  
MAX  
MIN  
30(2)  
MAX  
MIN  
40(2)  
MAX  
1
2
3
tc(SPC)M  
Cycle Time, SPI0_CLK, All Master Modes  
Pulse Width High, SPI0_CLK, All Master Modes  
Pulse Width Low, SPI0_CLK, All Master Modes  
20(2)  
256P  
256P  
256P  
ns  
ns  
ns  
tw(SPCH)M  
tw(SPCL)M  
0.5M-1  
0.5M-1  
0.5M-1  
0.5M-1  
0.5M-1  
0.5M-1  
Polarity = 0, Phase = 0,  
to SPI0_CLK rising  
5
5
6
Polarity = 0, Phase = 1,  
to SPI0_CLK rising  
-0.5M+5  
-0.5M+5  
-0.5M+6  
Delay, initial data bit valid on  
SPI0_SIMO after initial edge  
on SPI0_CLK(3)  
4
5
6
7
8
td(SIMO_SPC)M  
td(SPC_SIMO)M  
toh(SPC_SIMO)M  
tsu(SOMI_SPC)M  
tih(SPC_SOMI)M  
ns  
ns  
ns  
ns  
ns  
Polarity = 1, Phase = 0,  
to SPI0_CLK falling  
5
5
6
Polarity = 1, Phase = 1,  
to SPI0_CLK falling  
-0.5M+5  
-0.5M+5  
-0.5M+6  
Polarity = 0, Phase = 0,  
from SPI0_CLK rising  
5
5
5
5
5
5
5
5
6
6
6
6
Polarity = 0, Phase = 1,  
from SPI0_CLK falling  
Delay, subsequent bits valid  
on SPI0_SIMO after transmit  
edge of SPI0_CLK  
Polarity = 1, Phase = 0,  
from SPI0_CLK falling  
Polarity = 1, Phase = 1,  
from SPI0_CLK rising  
Polarity = 0, Phase = 0,  
from SPI0_CLK falling  
0.5M-3  
0.5M-3  
0.5M-3  
0.5M-3  
1.5  
0.5M-3  
0.5M-3  
0.5M-3  
0.5M-3  
1.5  
0.5M-3  
0.5M-3  
0.5M-3  
0.5M-3  
1.5  
Polarity = 0, Phase = 1,  
from SPI0_CLK rising  
Output hold time, SPI0_SIMO  
valid after receive edge of  
SPI0_CLK  
Polarity = 1, Phase = 0,  
from SPI0_CLK rising  
Polarity = 1, Phase = 1,  
from SPI0_CLK falling  
Polarity = 0, Phase = 0,  
to SPI0_CLK falling  
Polarity = 0, Phase = 1,  
to SPI0_CLK rising  
1.5  
1.5  
1.5  
Input Setup Time, SPI0_SOMI  
valid before receive edge of  
SPI0_CLK  
Polarity = 1, Phase = 0,  
to SPI0_CLK rising  
1.5  
1.5  
1.5  
Polarity = 1, Phase = 1,  
to SPI0_CLK falling  
1.5  
1.5  
1.5  
Polarity = 0, Phase = 0,  
from SPI0_CLK falling  
4
4
5
Polarity = 0, Phase = 1,  
from SPI0_CLK rising  
4
4
5
Input Hold Time, SPI0_SOMI  
valid after receive edge of  
SPI0_CLK  
Polarity = 1, Phase = 0,  
from SPI0_CLK rising  
4
4
5
Polarity = 1, Phase = 1,  
from SPI0_CLK falling  
4
4
5
(1) P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)  
(2) This timing is limited by the timing shown or 3P, whichever is greater.  
(3) First bit may be MSB or LSB depending upon SPI configuration. MO(0) refers to first bit and MO(n) refers to last bit output on  
SPI0_SIMO. MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPI0_SOMI.  
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Table 4-69. General Timing Requirements for SPI0 Slave Modes(1)  
1.3V, 1.2V  
1.1V  
1.0V  
NO.  
UNIT  
MIN  
40(2)  
18  
MAX  
MIN  
MAX  
MIN  
60(2)  
27  
MAX  
9
tc(SPC)S  
10 tw(SPCH)S  
11 tw(SPCL)S  
Cycle Time, SPI0_CLK, All Slave Modes  
Pulse Width High, SPI0_CLK, All Slave Modes  
Pulse Width Low, SPI0_CLK, All Slave Modes  
50(2)  
22  
ns  
ns  
ns  
18  
22  
27  
Polarity = 0, Phase = 0,  
to SPI0_CLK rising  
2P  
2P  
2P  
2P  
2P  
2P  
2P  
2P  
2P  
2P  
2P  
2P  
Polarity = 0, Phase = 1,  
to SPI0_CLK rising  
Setup time, transmit data  
written to SPI before initial  
clock edge from  
12 tsu(SOMI_SPC)S  
ns  
ns  
ns  
ns  
ns  
Polarity = 1, Phase = 0,  
to SPI0_CLK falling  
master.(3) (4)  
Polarity = 1, Phase = 1,  
to SPI0_CLK falling  
Polarity = 0, Phase = 0,  
from SPI0_CLK rising  
17  
17  
17  
17  
20  
20  
20  
20  
27  
27  
27  
27  
Polarity = 0, Phase = 1,  
from SPI0_CLK falling  
Delay, subsequent bits valid  
13 td(SPC_SOMI)S on SPI0_SOMI after  
transmit edge of SPI0_CLK  
Polarity = 1, Phase = 0,  
from SPI0_CLK falling  
Polarity = 1, Phase = 1,  
from SPI0_CLK rising  
Polarity = 0, Phase = 0,  
from SPI0_CLK falling  
0.5S-6  
0.5S-6  
0.5S-6  
0.5S-6  
1.5  
0.5S-16  
0.5S-20  
Polarity = 0, Phase = 1,  
from SPI0_CLK rising  
0.5S-16  
0.5S-20  
Output hold time,  
14 toh(SPC_SOMI)S SPI0_SOMI valid after  
receive edge of SPI0_CLK  
Polarity = 1, Phase = 0,  
from SPI0_CLK rising  
0.5S-16  
0.5S-20  
Polarity = 1, Phase = 1,  
from SPI0_CLK falling  
0.5S-16  
0.5S-20  
Polarity = 0, Phase = 0,  
to SPI0_CLK falling  
1.5  
1.5  
1.5  
1.5  
4
1.5  
1.5  
1.5  
1.5  
5
Polarity = 0, Phase = 1,  
to SPI0_CLK rising  
1.5  
Input Setup Time,  
15 tsu(SIMO_SPC)S SPI0_SIMO valid before  
receive edge of SPI0_CLK  
Polarity = 1, Phase = 0,  
to SPI0_CLK rising  
1.5  
Polarity = 1, Phase = 1,  
to SPI0_CLK falling  
1.5  
Polarity = 0, Phase = 0,  
from SPI0_CLK falling  
4
Polarity = 0, Phase = 1,  
from SPI0_CLK rising  
4
4
5
Input Hold Time,  
16 tih(SPC_SIMO)S SPI0_SIMO valid after  
receive edge of SPI0_CLK  
Polarity = 1, Phase = 0,  
from SPI0_CLK rising  
4
4
5
Polarity = 1, Phase = 1,  
from SPI0_CLK falling  
4
4
5
(1) P = SYSCLK2 period; S = tc(SPC)S (SPI slave bit clock period)  
(2) This timing is limited by the timing shown or 3P, whichever is greater.  
(3) First bit may be MSB or LSB depending upon SPI configuration. SO(0) refers to first bit and SO(n) refers to last bit output on  
SPI0_SOMI. SI(0) refers to the first bit input and SI(n) refers to the last bit input on SPI0_SIMO.  
(4) Measured from the termination of the write of new data to the SPI module, In analyzing throughput requirements, additional internal bus  
cycles must be accounted for to allow data to be written to the SPI module by the CPU.  
138  
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(1)(2)(3)  
1.1V  
Table 4-70. Additional SPI0 Master Timings, 4-Pin Enable Option  
1.3V, 1.2V  
1.0V  
UNIT  
MAX  
NO.  
PARAMETER  
MIN  
MAX  
MIN  
MAX  
MIN  
Polarity = 0, Phase = 0,  
to SPI0_CLK rising  
3P+5  
3P+5  
0.5M+3P+5  
3P+5  
3P+6  
Polarity = 0, Phase = 1,  
to SPI0_CLK rising  
0.5M+3P+5  
3P+5  
0.5M+3P+6  
ns  
Delay from slave assertion of SPI0_ENA  
active to first SPI0_CLK from master.(4)  
17  
td(ENA_SPC)M  
Polarity = 1, Phase = 0,  
to SPI0_CLK falling  
3P+6  
Polarity = 1, Phase = 1,  
to SPI0_CLK falling  
0.5M+3P+5  
0.5M+P+5  
P+5  
0.5M+3P+5  
0.5M+P+5  
P+5  
0.5M+3P+6  
0.5M+P+6  
Polarity = 0, Phase = 0,  
from SPI0_CLK falling  
Polarity = 0, Phase = 1,  
from SPI0_CLK falling  
P+6  
Max delay for slave to deassert SPI0_ENA  
after final SPI0_CLK edge to ensure  
18  
td(SPC_ENA)M  
ns  
master does not begin the next transfer.(5)  
Polarity = 1, Phase = 0,  
from SPI0_CLK rising  
0.5M+P+5  
P+5  
0.5M+P+5  
P+5  
0.5M+P+6  
Polarity = 1, Phase = 1,  
from SPI0_CLK rising  
P+6  
(1) These parameters are in addition to the general timings for SPI master modes (Table 4-68).  
(2) P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)  
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.  
(4) In the case where the master SPI is ready with new data before SPI0_ENA assertion.  
(5) In the case where the master SPI is ready with new data before SPI0_EN A deassertion.  
(1)(2)(3)  
1.1V  
Table 4-71. Additional SPI0 Master Timings, 4-Pin Chip Select Option  
1.3V, 1.2V  
1.0V  
NO.  
PARAMETER  
UNIT  
MIN  
MAX  
MIN  
MAX  
MIN  
2P-3  
MAX  
Polarity = 0, Phase = 0,  
to SPI0_CLK rising  
2P-1  
2P-2  
Polarity = 0, Phase = 1,  
to SPI0_CLK rising  
0.5M+2P-1  
2P-1  
0.5M+2P-2  
2P-2  
0.5M+2P-3  
2P-3  
Delay from SPI0_SCS active to first  
SPI0_CLK(4) (5)  
19  
td(SCS_SPC)M  
ns  
Polarity = 1, Phase = 0,  
to SPI0_CLK falling  
Polarity = 1, Phase = 1,  
to SPI0_CLK falling  
0.5M+2P-1  
0.5M+2P-2  
0.5M+2P-3  
(1) These parameters are in addition to the general timings for SPI master modes (Table 4-68).  
(2) P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)  
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.  
(4) In the case where the master SPI is ready with new data before SPI0_SCS assertion.  
(5) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].  
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Table 4-71. Additional SPI0 Master Timings, 4-Pin Chip Select Option (1)(2)(3) (continued)  
1.3V, 1.2V  
MIN  
1.1V  
1.0V  
NO.  
PARAMETER  
UNIT  
MAX  
MIN  
MAX  
MIN  
MAX  
Polarity = 0, Phase = 0,  
from SPI0_CLK falling  
0.5M+P-1  
P-1  
0.5M+P-2  
P-2  
0.5M+P-3  
P-3  
Polarity = 0, Phase = 1,  
from SPI0_CLK falling  
Delay from final SPI0_CLK edge to master  
deasserting SPI0_SCS  
20  
td(SPC_SCS)M  
ns  
(6) (7)  
Polarity = 1, Phase = 0,  
from SPI0_CLK rising  
0.5M+P-1  
P-1  
0.5M+P-2  
P-2  
0.5M+P-3  
P-3  
Polarity = 1, Phase = 1,  
from SPI0_CLK rising  
(6) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI0_SCS will remain asserted.  
(7) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].  
(1)(2)(3)  
Table 4-72. Additional SPI0 Master Timings, 5-Pin Option  
1.3V, 1.2V  
MAX  
1.1V  
1.0V  
NO.  
PARAMETER  
UNIT  
MIN  
MIN  
MAX  
MIN  
MAX  
Polarity = 0, Phase = 0,  
from SPI0_CLK falling  
0.5M+P+5  
P+5  
0.5M+P+5  
P+5  
0.5M+P+6  
P+6  
Polarity = 0, Phase = 1,  
from SPI0_CLK falling  
Max delay for slave to deassert  
SPI0_ENA after final SPI0_CLK  
edge to ensure master does not  
begin the next transfer.(4)  
18  
td(SPC_ENA)M  
ns  
Polarity = 1, Phase = 0,  
from SPI0_CLK rising  
0.5M+P+5  
P+5  
0.5M+P+5  
P+5  
0.5M+P+6  
P+6  
Polarity = 1, Phase = 1,  
from SPI0_CLK rising  
Polarity = 0, Phase = 0,  
from SPI0_CLK falling  
0.5M+P-2  
P-2  
0.5M+P-2  
P-2  
0.5M+P-3  
P-3  
Polarity = 0, Phase = 1,  
from SPI0_CLK falling  
Delay from final SPI0_CLK edge to  
(5)  
20  
21  
td(SPC_SCS)M  
master deasserting SPI0_SCS  
ns  
ns  
(6)  
Polarity = 1, Phase = 0,  
from SPI0_CLK rising  
0.5M+P-2  
P-2  
0.5M+P-2  
P-2  
0.5M+P-3  
P-3  
Polarity = 1, Phase = 1,  
from SPI0_CLK rising  
Max delay for slave SPI to drive SPI0_ENA valid after master  
asserts SPI0_SCS to delay the master from beginning the  
next transfer,  
td(SCSL_ENAL)M  
C2TDELAY+P  
C2TDELAY+P  
C2TDELAY+P  
(1) These parameters are in addition to the general timings for SPI master modes (Table 4-69).  
(2) P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)  
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.  
(4) In the case where the master SPI is ready with new data before SPI0_ENA deassertion.  
(5) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI0_SCS will remain asserted.  
(6) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].  
140  
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Table 4-72. Additional SPI0 Master Timings, 5-Pin Option (1)(2)(3) (continued)  
1.3V, 1.2V  
1.1V  
1.0V  
UNIT  
MAX  
NO.  
PARAMETER  
MIN  
MAX  
MIN  
MAX  
MIN  
Polarity = 0, Phase = 0,  
to SPI0_CLK rising  
2P-2  
2P-2  
2P-3  
Polarity = 0, Phase = 1,  
to SPI0_CLK rising  
0.5M+2P-2  
2P-2  
0.5M+2P-2  
2P-2  
0.5M+2P-3  
2P-3  
Delay from SPI0_SCS active to  
first SPI0_CLK(7) (8) (9)  
22  
td(SCS_SPC)M  
ns  
Polarity = 1, Phase = 0,  
to SPI0_CLK falling  
Polarity = 1, Phase = 1,  
to SPI0_CLK falling  
0.5M+2P-2  
0.5M+2P-2  
0.5M+2P-3  
Polarity = 0, Phase = 0,  
to SPI0_CLK rising  
3P+5  
0.5M+3P+5  
3P+5  
3P+5  
3P+6  
Polarity = 0, Phase = 1,  
to SPI0_CLK rising  
0.5M+3P+5  
3P+5  
0.5M+3P+6  
ns  
Delay from assertion of SPI0_ENA  
low to first SPI0_CLK edge.(10)  
23  
td(ENA_SPC)M  
Polarity = 1, Phase = 0,  
to SPI0_CLK falling  
3P+6  
Polarity = 1, Phase = 1,  
to SPI0_CLK falling  
0.5M+3P+5  
0.5M+3P+5  
0.5M+3P+6  
(7) If SPI0_ENA is asserted immediately such that the transmission is not delayed by SPI0_ENA.  
(8) In the case where the master SPI is ready with new data before SPI0_SCS assertion.  
(9) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].  
(10) If SPI0_ENA was initially deasserted high and SPI0_CLK is delayed.  
(1)(2)(3)  
Table 4-73. Additional SPI0 Slave Timings, 4-Pin Enable Option  
1.3V, 1.2V  
1.1V  
1.0V  
UNIT  
MAX  
NO.  
PARAMETER  
MIN  
MAX  
MIN  
MAX  
MIN  
Polarity = 0, Phase = 0,  
from SPI0_CLK falling  
1.5P-3  
2.5P+17.5  
– 0.5M+2.5P+17.5  
2.5P+17.5  
1.5P-3  
2.5P+20  
1.5P-3  
2.5P+27  
Polarity = 0, Phase = 1,  
from SPI0_CLK falling  
– 0.5M+1.5P-3  
1.5P-3  
– 0.5M+1.5P-3  
1.5P-3  
– 0.5M+2.5P+20  
2.5P+20  
– 0.5M+1.5P-3  
1.5P-3  
– 0.5M+2.5P+27  
ns  
Delay from final SPI0_CLK edge  
to slave deasserting SPI0_ENA.  
24 td(SPC_ENAH)S  
Polarity = 1, Phase = 0,  
from SPI0_CLK rising  
2.5P+27  
Polarity = 1, Phase = 1,  
from SPI0_CLK rising  
– 0.5M+1.5P-3  
– 0.5+2.5P+17.5  
– 0.5M+1.5P-3  
– 0.5+2.5P+20  
– 0.5M+1.5P-3  
– 0.5+2.5P+27  
(1) These parameters are in addition to the general timings for SPI slave modes (Table 4-69).  
(2) P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)  
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.  
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(1)(2)(3)  
1.1V  
Table 4-74. Additional SPI0 Slave Timings, 4-Pin Chip Select Option  
1.3V, 1.2V  
1.0V  
NO.  
PARAMETER  
UNIT  
MIN  
MAX  
MIN  
MAX  
MIN  
MAX  
Required delay from SPI0_SCS asserted at slave to first SPI0_CLK edge  
at slave.  
25  
td(SCSL_SPC)S  
P + 1.5  
P + 1.5  
0.5M+P+4  
P+4  
P + 1.5  
ns  
Polarity = 0, Phase = 0,  
from SPI0_CLK falling  
0.5M+P+4  
P+4  
0.5M+P+5  
P+5  
Polarity = 0, Phase = 1,  
from SPI0_CLK falling  
Required delay from final SPI0_CLK edge  
before SPI0_SCS is deasserted.  
26  
td(SPC_SCSH)S  
ns  
Polarity = 1, Phase = 0,  
from SPI0_CLK rising  
0.5M+P+4  
P+4  
0.5M+P+4  
P+4  
0.5M+P+5  
P+5  
Polarity = 1, Phase = 1,  
from SPI0_CLK rising  
27  
28  
tena(SCSL_SOMI)S Delay from master asserting SPI0_SCS to slave driving SPI0_SOMI valid  
tdis(SCSH_SOMI)S Delay from master deasserting SPI0_SCS to slave 3-stating SPI0_SOMI  
P+17.5  
P+17.5  
P+20  
P+20  
P+27  
P+27  
ns  
ns  
(1) These parameters are in addition to the general timings for SPI slave modes (Table 4-69).  
(2) P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)  
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.  
(1)(2)(3)  
1.1V  
Table 4-75. Additional SPI0 Slave Timings, 5-Pin Option  
1.3V, 1.2V  
1.0V  
NO.  
PARAMETER  
UNIT  
MIN  
MAX  
MIN  
MAX  
MIN  
MAX  
Required delay from SPI0_SCS asserted at slave to first  
SPI0_CLK edge at slave.  
25  
td(SCSL_SPC)S  
P + 1.5  
P + 1.5  
0.5M+P+4  
P+4  
P + 1.5  
ns  
Polarity = 0, Phase = 0,  
from SPI0_CLK falling  
0.5M+P+4  
P+4  
0.5M+P+5  
P+5  
Polarity = 0, Phase = 1,  
Required delay from final  
from SPI0_CLK falling  
26  
td(SPC_SCSH)S  
SPI0_CLK edge before SPI0_SCS  
ns  
Polarity = 1, Phase = 0,  
is deasserted.  
0.5M+P+4  
P+4  
0.5M+P+4  
P+4  
0.5M+P+5  
P+5  
from SPI0_CLK rising  
Polarity = 1, Phase = 1,  
from SPI0_CLK rising  
Delay from master asserting SPI0_SCS to slave driving  
SPI0_SOMI valid  
27  
28  
29  
tena(SCSL_SOMI)S  
tdis(SCSH_SOMI)S  
tena(SCSL_ENA)S  
P+17.5  
P+17.5  
17.5  
P+20  
P+20  
20  
P+27  
P+27  
27  
ns  
ns  
ns  
Delay from master deasserting SPI0_SCS to slave 3-stating  
SPI0_SOMI  
Delay from master deasserting SPI0_SCS to slave driving  
SPI0_ENA valid  
(1) These parameters are in addition to the general timings for SPI slave modes (Table 4-69).  
(2) P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)  
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.  
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Table 4-75. Additional SPI0 Slave Timings, 5-Pin Option (1)(2)(3) (continued)  
1.3V, 1.2V  
MAX  
1.1V  
1.0V  
UNIT  
MAX  
NO.  
PARAMETER  
MIN  
MIN  
MAX  
MIN  
Polarity = 0, Phase = 0,  
from SPI0_CLK falling  
2.5P+17.5  
2.5P+17.5  
2.5P+17.5  
2.5P+17.5  
2.5P+20  
2.5P+27  
Polarity = 0, Phase = 1,  
from SPI0_CLK rising  
Delay from final clock receive  
edge on SPI0_CLK to slave 3-  
stating or driving high  
2.5P+20  
2.5P+20  
2.5P+20  
2.5P+27  
ns  
30  
tdis(SPC_ENA)S  
Polarity = 1, Phase = 0,  
from SPI0_CLK rising  
SPI0_ENA.(4)  
2.5P+27  
Polarity = 1, Phase = 1,  
from SPI0_CLK falling  
2.5P+27  
(4) SPI0_ENA is driven low after the transmission completes if the SPIINT0.ENABLE_HIGHZ bit is programmed to 0. Otherwise it is tri-stated. If tri-stated, an external pullup resistor should  
be used to provide a valid level to the master. This option is useful when tying several SPI slave devices to a single master.  
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Table 4-76. General Timing Requirements for SPI1 Master Modes(1)  
1.3V, 1.2V  
1.1V  
1.0V  
NO.  
UNIT  
MAX  
MIN  
MAX  
MIN  
30(2)  
MAX  
MIN  
40(2)  
1
2
3
tc(SPC)M  
Cycle Time, SPI1_CLK, All Master Modes  
Pulse Width High, SPI1_CLK, All Master Modes  
Pulse Width Low, SPI1_CLK, All Master Modes  
20(2)  
256P  
256P  
256P  
ns  
ns  
ns  
tw(SPCH)M  
tw(SPCL)M  
0.5M-1  
0.5M-1  
0.5M-1  
0.5M-1  
0.5M-1  
0.5M-1  
Polarity = 0, Phase = 0,  
to SPI1_CLK rising  
5
5
6
Polarity = 0, Phase = 1,  
to SPI1_CLK rising  
-0.5M+5  
-0.5M+5  
-0.5M+6  
Delay, initial data bit valid on  
SPI1_SIMO to initial edge on  
SPI1_CLK(3)  
4
5
6
7
8
td(SIMO_SPC)M  
td(SPC_SIMO)M  
toh(SPC_SIMO)M  
tsu(SOMI_SPC)M  
tih(SPC_SOMI)M  
ns  
ns  
ns  
ns  
ns  
Polarity = 1, Phase = 0,  
to SPI1_CLK falling  
5
5
6
Polarity = 1, Phase = 1,  
to SPI1_CLK falling  
-0.5M+5  
-0.5M+5  
-0.5M+6  
Polarity = 0, Phase = 0,  
from SPI1_CLK rising  
5
5
5
5
5
5
5
5
6
6
6
6
Polarity = 0, Phase = 1,  
from SPI1_CLK falling  
Delay, subsequent bits valid on  
SPI1_SIMO after transmit edge  
of SPI1_CLK  
Polarity = 1, Phase = 0,  
from SPI1_CLK falling  
Polarity = 1, Phase = 1,  
from SPI1_CLK rising  
Polarity = 0, Phase = 0,  
from SPI1_CLK falling  
0.5M-3  
0.5M-3  
0.5M-3  
0.5M-3  
1.5  
0.5M-3  
0.5M-3  
0.5M-3  
0.5M-3  
1.5  
0.5M-3  
0.5M-3  
0.5M-3  
0.5M-3  
1.5  
Polarity = 0, Phase = 1,  
from SPI1_CLK rising  
Output hold time, SPI1_SIMO  
valid after receive edge of  
SPI1_CLK  
Polarity = 1, Phase = 0,  
from SPI1_CLK rising  
Polarity = 1, Phase = 1,  
from SPI1_CLK falling  
Polarity = 0, Phase = 0,  
to SPI1_CLK falling  
Polarity = 0, Phase = 1,  
to SPI1_CLK rising  
1.5  
1.5  
1.5  
Input Setup Time, SPI1_SOMI  
valid before receive edge of  
SPI1_CLK  
Polarity = 1, Phase = 0,  
to SPI1_CLK rising  
1.5  
1.5  
1.5  
Polarity = 1, Phase = 1,  
to SPI1_CLK falling  
1.5  
1.5  
1.5  
Polarity = 0, Phase = 0,  
from SPI1_CLK falling  
4
5
6
Polarity = 0, Phase = 1,  
from SPI1_CLK rising  
4
5
6
Input Hold Time, SPI1_SOMI  
valid after receive edge of  
SPI1_CLK  
Polarity = 1, Phase = 0,  
from SPI1_CLK rising  
4
5
6
Polarity = 1, Phase = 1,  
from SPI1_CLK falling  
4
5
6
(1) P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)  
(2) This timing is limited by the timing shown or 3P, whichever is greater.  
(3) First bit may be MSB or LSB depending upon SPI configuration. MO(0) refers to first bit and MO(n) refers to last bit output on  
SPI1_SIMO. MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPI1_SOMI.  
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Table 4-77. General Timing Requirements for SPI1 Slave Modes(1)  
1.3V, 1.2V  
1.1V  
1.0V  
NO.  
UNIT  
MIN  
40(2)  
18  
MAX  
MIN  
MAX  
MIN  
60(2)  
27  
MAX  
9
tc(SPC)S  
10 tw(SPCH)S  
11 tw(SPCL)S  
Cycle Time, SPI1_CLK, All Slave Modes  
Pulse Width High, SPI1_CLK, All Slave Modes  
Pulse Width Low, SPI1_CLK, All Slave Modes  
50(2)  
22  
ns  
ns  
ns  
18  
22  
27  
Polarity = 0, Phase = 0,  
to SPI1_CLK rising  
2P  
2P  
2P  
2P  
2P  
2P  
2P  
2P  
2P  
2P  
2P  
2P  
Polarity = 0, Phase = 1,  
to SPI1_CLK rising  
Setup time, transmit data  
written to SPI before initial  
clock edge from  
12 tsu(SOMI_SPC)S  
ns  
ns  
ns  
ns  
ns  
Polarity = 1, Phase = 0,  
to SPI1_CLK falling  
master.(3)(4)  
Polarity = 1, Phase = 1,  
to SPI1_CLK falling  
Polarity = 0, Phase = 0,  
from SPI1_CLK rising  
15  
15  
15  
15  
17  
17  
17  
17  
19  
19  
19  
19  
Polarity = 0, Phase = 1,  
from SPI1_CLK falling  
Delay, subsequent bits valid  
on SPI1_SOMI after transmit  
edge of SPI1_CLK  
13 td(SPC_SOMI)S  
Polarity = 1, Phase = 0,  
from SPI1_CLK falling  
Polarity = 1, Phase = 1,  
from SPI1_CLK rising  
Polarity = 0, Phase = 0,  
from SPI1_CLK falling  
0.5S-4  
0.5S-4  
0.5S-4  
0.5S-4  
1.5  
0.5S-10  
0.5S-12  
Polarity = 0, Phase = 1,  
from SPI1_CLK rising  
0.5S-10  
0.5S-12  
Output hold time, SPI1_SOMI  
14 toh(SPC_SOMI)S valid after receive edge of  
SPI1_CLK  
Polarity = 1, Phase = 0,  
from SPI1_CLK rising  
0.5S-10  
0.5S-12  
Polarity = 1, Phase = 1,  
from SPI1_CLK falling  
0.5S-10  
0.5S-12  
Polarity = 0, Phase = 0,  
to SPI1_CLK falling  
1.5  
1.5  
1.5  
1.5  
5
1.5  
1.5  
1.5  
1.5  
6
Polarity = 0, Phase = 1,  
to SPI1_CLK rising  
1.5  
Input Setup Time, SPI1_SIMO  
15 tsu(SIMO_SPC)S valid before receive edge of  
SPI1_CLK  
Polarity = 1, Phase = 0,  
to SPI1_CLK rising  
1.5  
Polarity = 1, Phase = 1,  
to SPI1_CLK falling  
1.5  
Polarity = 0, Phase = 0,  
from SPI1_CLK falling  
4
Polarity = 0, Phase = 1,  
from SPI1_CLK rising  
4
5
6
Input Hold Time, SPI1_SIMO  
16 tih(SPC_SIMO)S valid after receive edge of  
SPI1_CLK  
Polarity = 1, Phase = 0,  
from SPI1_CLK rising  
4
5
6
Polarity = 1, Phase = 1,  
from SPI1_CLK falling  
4
5
6
(1) P = SYSCLK2 period; S = tc(SPC)S (SPI slave bit clock period)  
(2) This timing is limited by the timing shown or 3P, whichever is greater.  
(3) First bit may be MSB or LSB depending upon SPI configuration. SO(0) refers to first bit and SO(n) refers to last bit output on  
SPI1_SOMI. SI(0) refers to the first bit input and SI(n) refers to the last bit input on SPI1_SIMO.  
(4) Measured from the termination of the write of new data to the SPI module, In analyzing throughput requirements, additional internal bus  
cycles must be accounted for to allow data to be written to the SPI module by the CPU.  
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Table 4-78. Additional(1) SPI1 Master Timings, 4-Pin Enable Option(2)(3)  
1.3V, 1.2V  
1.1V  
MAX  
1.0V  
MAX  
NO.  
PARAMETER  
UNIT  
MIN  
MAX  
MIN  
MIN  
Polarity = 0, Phase = 0,  
to SPI1_CLK rising  
3P+5  
3P+5  
0.5M+3P+5  
3P+5  
3P+6  
0.5M+3P+6  
3P+6  
Delay from slave  
assertion of  
Polarity = 0, Phase = 1,  
to SPI1_CLK rising  
0.5M+3P+5  
3P+5  
17 td(EN A_SPC)M  
SPI1_ENA active to  
first SPI1_CLK from  
master.(4)  
ns  
Polarity = 1, Phase = 0,  
to SPI1_CLK falling  
Polarity = 1, Phase = 1,  
to SPI1_CLK falling  
0.5M+3P+5  
0.5M+P+5  
P+5  
0.5M+3P+5  
0.5M+P+5  
P+5  
0.5M+3P+6  
0.5M+P+6  
P+6  
Polarity = 0, Phase = 0,  
from SPI1_CLK falling  
Max delay for slave to  
deassert SPI1_ENA  
after final SPI1_CLK  
edge to ensure  
Polarity = 0, Phase = 1,  
from SPI1_CLK falling  
18 td(SPC_ENA)M  
ns  
Polarity = 1, Phase = 0,  
from SPI1_CLK rising  
0.5M+P+5  
P+5  
0.5M+P+5  
P+5  
0.5M+P+6  
P+6  
master does not begin  
the next transfer.(5)  
Polarity = 1, Phase = 1,  
from SPI1_CLK rising  
(1) These parameters are in addition to the general timings for SPI master modes (Table 4-76).  
(2) P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)  
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.  
(4) In the case where the master SPI is ready with new data before SPI1_ENA assertion.  
(5) In the case where the master SPI is ready with new data before SPI1_ENA deassertion.  
Table 4-79. Additional(1) SPI1 Master Timings, 4-Pin Chip Select Option(2) (3)  
1.3V, 1.2V  
1.1V  
MIN  
1.0V  
MIN MAX  
NO.  
PARAMETER  
UNIT  
MIN  
MAX  
MAX  
Polarity = 0, Phase = 0,  
to SPI1_CLK rising  
2P-1  
2P-5  
0.5M+2P-5  
2P-5  
2P-6  
0.5M+2P-6  
2P-6  
Polarity = 0, Phase = 1,  
to SPI1_CLK rising  
Delay from  
0.5M+2P-1  
2P-1  
SPI1_SCS active  
to first  
19 td(SCS_SPC)M  
ns  
Polarity = 1, Phase = 0,  
to SPI1_CLK falling  
SPI1_CLK(4) (5)  
Polarity = 1, Phase = 1,  
to SPI1_CLK falling  
0.5M+2P-1  
0.5M+P-1  
P-1  
0.5M+2P-5  
0.5M+P-5  
P-5  
0.5M+2P-6  
0.5M+P-6  
P-6  
Polarity = 0, Phase = 0,  
from SPI1_CLK falling  
Delay from final  
SPI1_CLK edge to  
master  
Polarity = 0, Phase = 1,  
from SPI1_CLK falling  
20 td(SPC_SCS)M  
ns  
Polarity = 1, Phase = 0,  
from SPI1_CLK rising  
deasserting  
0.5M+P-1  
P-1  
0.5M+P-5  
P-5  
0.5M+P-6  
P-6  
(6) (7)  
SPI1_SCS  
Polarity = 1, Phase = 1,  
from SPI1_CLK rising  
(1) These parameters are in addition to the general timings for SPI master modes (Table 4-76).  
(2) P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)  
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.  
(4) In the case where the master SPI is ready with new data before SPI1_SCS assertion.  
(5) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].  
(6) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI1_SCS will remain  
asserted.  
(7) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].  
146  
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Table 4-80. Additional(1) SPI1 Master Timings, 5-Pin Option(2)(3)  
1.3V, 1.2V  
MAX  
1.1V  
1.0V  
UNIT  
MAX  
NO.  
PARAMETER  
MIN  
MIN  
MAX  
MIN  
Polarity = 0, Phase = 0,  
from SPI1_CLK falling  
0.5M+P+5  
P+5  
0.5M+P+5  
0.5M+P+6  
Polarity = 0, Phase = 1,  
from SPI1_CLK falling  
Max delay for slave to deassert  
SPI1_ENA after final SPI1_CLK  
edge to ensure master does not  
begin the next transfer.(4)  
P+5  
0.5M+P+5  
P+5  
P+6  
18  
td(SPC_ENA)M  
ns  
Polarity = 1, Phase = 0,  
from SPI1_CLK rising  
0.5M+P+5  
P+5  
0.5M+P+6  
Polarity = 1, Phase = 1,  
from SPI1_CLK rising  
P+6  
Polarity = 0, Phase = 0,  
from SPI1_CLK falling  
0.5M+P-1  
P-1  
0.5M+P-5  
P-5  
0.5M+P-6  
P-6  
Polarity = 0, Phase = 1,  
from SPI1_CLK falling  
Delay from final SPI1_CLK edge to  
master deasserting SPI1_SCS  
20  
21  
22  
td(SPC_SCS)M  
td(SCSL_ENAL)M  
td(SCS_SPC)M  
ns  
(5)(6)  
Polarity = 1, Phase = 0,  
from SPI1_CLK rising  
0.5M+P-1  
P-1  
0.5M+P-5  
P-5  
0.5M+P-6  
P-6  
Polarity = 1, Phase = 1,  
from SPI1_CLK rising  
Max delay for slave SPI to drive SPI1_ENA valid after master  
asserts SPI1_SCS to delay the  
master from beginning the next transfer,  
C2TDELAY+P  
C2TDELAY+P  
C2TDELAY+P  
ns  
ns  
Polarity = 0, Phase = 0,  
to SPI1_CLK rising  
2P-1  
0.5M+2P-1  
2P-1  
2P-5  
0.5M+2P-5  
2P-5  
2P-6  
0.5M+2P-6  
2P-6  
Polarity = 0, Phase = 1,  
to SPI1_CLK rising  
Delay from SPI1_SCS active to first  
SPI1_CLK(7)(8)(9)  
Polarity = 1, Phase = 0,  
to SPI1_CLK falling  
Polarity = 1, Phase = 1,  
to SPI1_CLK falling  
0.5M+2P-1  
0.5M+2P-5  
0.5M+2P-6  
(1) These parameters are in addition to the general timings for SPI master modes (Table 4-77).  
(2) P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)  
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.  
(4) In the case where the master SPI is ready with new data before SPI1_ENA deassertion.  
(5) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI1_SCS will remain asserted.  
(6) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].  
(7) If SPI1_ENA is asserted immediately such that the transmission is not delayed by SPI1_ENA.  
(8) In the case where the master SPI is ready with new data before SPI1_SCS assertion.  
(9) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].  
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Table 4-80. Additional(1) SPI1 Master Timings, 5-Pin Option(2)(3) (continued)  
1.3V, 1.2V  
MAX  
1.1V  
1.0V  
NO.  
PARAMETER  
UNIT  
MIN  
MIN  
MAX  
MIN  
MAX  
Polarity = 0, Phase = 0,  
to SPI1_CLK rising  
3P+5  
3P+5  
3P+6  
Polarity = 0, Phase = 1,  
to SPI1_CLK rising  
0.5M+3P+5  
3P+5  
0.5M+3P+5  
3P+5  
0.5M+3P+6  
3P+6  
Delay from assertion of SPI1_ENA  
low to first SPI1_CLK edge.(10)  
23  
td(ENA_SPC)M  
ns  
Polarity = 1, Phase = 0,  
to SPI1_CLK falling  
Polarity = 1, Phase = 1,  
to SPI1_CLK falling  
0.5M+3P+5  
0.5M+3P+5  
0.5M+3P+6  
(10) If SPI1_ENA was initially deasserted high and SPI1_CLK is delayed.  
Table 4-81. Additional(1) SPI1 Slave Timings, 4-Pin Enable Option(2)(3)  
1.3V, 1.2V  
1.1V  
1.0V  
NO.  
PARAMETER  
UNIT  
MIN  
MAX  
MIN  
MAX  
MIN  
MAX  
Polarity = 0, Phase = 0,  
from SPI1_CLK falling  
1.5P-3  
2.5P+15  
1.5P-10  
2.5P+17  
1.5P-12  
–0.5M+1.5P-12  
1.5P-12  
2.5P+19  
Polarity = 0, Phase = 1,  
from SPI1_CLK falling  
–0.5M+1.5P-3  
1.5P-3  
–0.5M+2.5P+15  
2.5P+15  
–0.5M+1.5P-10  
1.5P-10  
–0.5M+2.5P+17  
2.5P+17  
–0.5M+2.5P+19  
2.5P+19  
Delay from final SPI1_CLK edge to  
slave deasserting SPI1_ENA.  
24  
td(SPC_ENAH)S  
ns  
Polarity = 1, Phase = 0,  
from SPI1_CLK rising  
Polarity = 1, Phase = 1,  
from SPI1_CLK rising  
–0.5M+1.5P-3  
–0.5M+2.5P+15  
–0.5M+1.5P-10  
–0.5M+2.5P+17  
–0.5M+1.5P-12  
–0.5M+2.5P+19  
(1) These parameters are in addition to the general timings for SPI slave modes (Table 4-77).  
(2) P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)  
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.  
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Table 4-82. Additional(1) SPI1 Slave Timings, 4-Pin Chip Select Option(2)(3)  
1.3V, 1.2V  
MIN  
1.1V  
1.0V  
UNIT  
MIN MAX  
NO.  
PARAMETER  
MAX  
MIN  
MAX  
Required delay from SPI1_SCS asserted at slave to first SPI1_CLK edge at  
slave.  
25  
td(SCSL_SPC)S  
P+1.5  
0.5M+P+4  
P+4  
P+1.5  
P+1.5  
0.5M+P+6  
P+6  
ns  
Polarity = 0, Phase = 0,  
from SPI1_CLK falling  
0.5M+P+5  
P+5  
Polarity = 0, Phase = 1,  
from SPI1_CLK falling  
Required delay from final SPI1_CLK edge  
26  
td(SPC_SCSH)S  
ns  
before SPI1_SCS is deasserted.  
Polarity = 1, Phase = 0,  
0.5M+P+4  
P+4  
0.5M+P+5  
P+5  
0.5M+P+6  
P+6  
from SPI1_CLK rising  
Polarity = 1, Phase = 1,  
from SPI1_CLK rising  
27  
28  
tena(SCSL_SOMI)S  
tdis(SCSH_SOMI)S  
Delay from master asserting SPI1_SCS to slave driving SPI1_SOMI valid  
Delay from master deasserting SPI1_SCS to slave 3-stating SPI1_SOMI  
P+15  
P+15  
P+17  
P+17  
P+19  
P+19  
ns  
ns  
(1) These parameters are in addition to the general timings for SPI slave modes (Table 4-77).  
(2) P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)  
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.  
Table 4-83. Additional(1) SPI1 Slave Timings, 5-Pin Option(2)(3)  
1.3V, 1.2V  
1.1V  
1.0V  
NO.  
PARAMETER  
UNIT  
MIN  
MAX  
MIN  
MAX  
MIN  
MAX  
Required delay from SPI1_SCS asserted at slave to first  
SPI1_CLK edge at slave.  
25  
td(SCSL_SPC)S  
P+1.5  
0.5M+P+4  
P+4  
P+1.5  
P+1.5  
ns  
Polarity = 0, Phase = 0,  
from SPI1_CLK falling  
0.5M+P+5  
P+5  
0.5M+P+6  
P+6  
Polarity = 0, Phase = 1,  
Required delay from final  
from SPI1_CLK falling  
26  
td(SPC_SCSH)S  
SPI1_CLK edge before SPI1_SCS  
ns  
Polarity = 1, Phase = 0,  
is deasserted.  
0.5M+P+4  
P+4  
0.5M+P+5  
P+5  
0.5M+P+6  
P+6  
from SPI1_CLK rising  
Polarity = 1, Phase = 1,  
from SPI1_CLK rising  
Delay from master asserting SPI1_SCS to slave driving  
SPI1_SOMI valid  
27  
28  
29  
tena(SCSL_SOMI)S  
tdis(SCSH_SOMI)S  
tena(SCSL_ENA)S  
P+15  
P+15  
15  
P+17  
P+17  
17  
P+19  
P+19  
19  
ns  
ns  
ns  
Delay from master deasserting SPI1_SCS to slave 3-stating  
SPI1_SOMI  
Delay from master deasserting SPI1_SCS to slave driving  
SPI1_ENA valid  
(1) These parameters are in addition to the general timings for SPI slave modes (Table 4-77).  
(2) P = SYSCLK2 period; M = tc(SPC)M (SPI master bit clock period)  
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.  
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Table 4-83. Additional(1) SPI1 Slave Timings, 5-Pin Option(2)(3) (continued)  
1.3V, 1.2V  
MAX  
1.1V  
1.0V  
NO.  
PARAMETER  
UNIT  
MIN  
MIN  
MAX  
MIN  
MAX  
Polarity = 0, Phase = 0,  
from SPI1_CLK falling  
2.5P+15  
2.5P+15  
2.5P+15  
2.5P+15  
2.5P+17  
2.5P+19  
2.5P+19  
2.5P+19  
2.5P+19  
Polarity = 0, Phase = 1,  
from SPI1_CLK rising  
2.5P+17  
2.5P+17  
2.5P+17  
Delay from final clock receive edge  
on SPI1_CLK to slave 3-stating or  
driving high SPI1_ENA.(4)  
30  
tdis(SPC_ENA)S  
ns  
Polarity = 1, Phase = 0,  
from SPI1_CLK rising  
Polarity = 1, Phase = 1,  
from SPI1_CLK falling  
(4) SPI1_ENA is driven low after the transmission completes if the SPIINT0.ENABLE_HIGHZ bit is programmed to 0. Otherwise it is tri-stated. If tri-stated, an external pullup resistor should  
be used to provide a valid level to the master. This option is useful when tying several SPI slave devices to a single master.  
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1
MASTER MODE  
POLARITY = 0 PHASE = 0  
2
3
SPIx_CLK  
SPIx_SIMO  
SPIx_SOMI  
5
4
6
MO(0)  
7
MO(1)  
MO(n−1)  
MO(n)  
MI(n)  
8
MI(0)  
MI(1)  
MI(n−1)  
MASTER MODE  
POLARITY = 0 PHASE = 1  
4
SPIx_CLK  
SPIx_SIMO  
SPIx_SOMI  
6
5
MO(0)  
7
MO(1)  
MI(1)  
MO(n−1)  
MI(n−1)  
MO(n)  
MI(n)  
8
MI(0)  
4
MASTER MODE  
POLARITY = 1 PHASE = 0  
SPIx_CLK  
SPIx_SIMO  
SPIx_SOMI  
5
6
MO(0)  
7
MO(1)  
MI(1)  
MO(n−1)  
MO(n)  
MI(n)  
8
MI(0)  
MI(n−1)  
MASTER MODE  
POLARITY = 1 PHASE = 1  
SPIx_CLK  
SPIx_SIMO  
SPIx_SOMI  
5
4
6
MO(0)  
7
MO(1)  
MI(1)  
MO(n−1)  
MI(n−1)  
MO(n)  
MI(n)  
8
MI(0)  
Figure 4-39. SPI Timings—Master Mode  
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9
SLAVE MODE  
POLARITY = 0 PHASE = 0  
12  
10  
15  
11  
SPIx_CLK  
SPIx_SIMO  
SPIx_SOMI  
16  
SI(0)  
SI(1)  
13  
SI(n−1)  
SI(n)  
14  
SO(0)  
SO(1)  
SO(n−1)  
SO(n)  
12  
SLAVE MODE  
POLARITY = 0 PHASE = 1  
SPIx_CLK  
SPIx_SIMO  
SPIx_SOMI  
15  
SI(0)  
16  
SI(1)  
SI(n−1)  
SI(n)  
13  
SO(1)  
14  
SO(0)  
SO(n−1)  
SO(n)  
SLAVE MODE  
POLARITY = 1 PHASE = 0  
12  
SPIx_CLK  
SPIx_SIMO  
SPIx_SOMI  
15  
16  
SI(0)  
SI(1)  
SI(n−1)  
SI(n)  
13  
SO(1)  
14  
SO(n−1)  
SO(0)  
SO(n)  
SLAVE MODE  
POLARITY = 1 PHASE = 1  
12  
SPIx_CLK  
SPIx_SIMO  
SPIx_SOMI  
15  
16  
SI(0)  
SI(1)  
SI(n−1)  
SI(n)  
13  
SO(1)  
14  
SO(0)  
SO(n−1)  
SO(n)  
Figure 4-40. SPI Timings—Slave Mode  
152  
Specifications  
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MASTER MODE 4 PIN WITH ENABLE  
17  
18  
SPIx_CLK  
SPIx_SIMO  
SPIx_SOMI  
SPIx_ENA  
MO(0)  
MI(0)  
MO(n)  
MI(n)  
MO(n−1)  
MI(n−1)  
MO(1)  
MI(1)  
MASTER MODE 4 PIN WITH CHIP SELECT  
19  
20  
SPIx_CLK  
SPIx_SIMO  
SPIx_SOMI  
SPIx_SCS  
MO(0)  
MO(n)  
MI(n)  
MO(n−1)  
MI(n−1)  
MO(1)  
MI(1)  
MI(0)  
MASTER MODE 5 PIN  
23  
22  
20  
MO(1)  
18  
SPIx_CLK  
SPIx_SIMO  
SPIx_SOMI  
MO(0)  
MO(n−1)  
MO(n)  
MI(0)  
MI(1)  
MI(n−1)  
MI(n)  
21  
(A)  
(A)  
SPIx_ENA  
SPIx_SCS  
DESEL  
DESEL  
A. DESELECTED IS PROGRAMMABLE EITHER HIGH OR  
3−STATE (REQUIRES EXTERNAL PULLUP)  
Figure 4-41. SPI Timings—Master Mode (4-Pin and 5-Pin)  
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SLAVE MODE 4 PIN WITH ENABLE  
24  
SPIx_CLK  
SPIx_SOMI  
SPIx_SIMO  
SPIx_ENA  
SO(0)  
SI(0)  
SO(1)  
SO(n−1) SO(n)  
SI(n−1) SI(n)  
SI(1)  
SLAVE MODE 4 PIN WITH CHIP SELECT  
25  
26  
SPIx_CLK  
27  
28  
SO(n−1)  
SPIx_SOMI  
SPIx_SIMO  
SPIx_SCS  
SO(0)  
SO(1)  
SO(n)  
SI(0)  
SI(1)  
SI(n−1)  
SI(n)  
SLAVE MODE 5 PIN  
25  
26  
30  
SPIx_CLK  
27  
29  
28  
SO(1)  
SPIx_SOMI  
SPIx_SIMO  
SO(0)  
SI(0)  
SO(n−1)  
SO(n)  
SI(1)  
SI(n−1) SI(n)  
SPIx_ENA  
SPIx_SCS  
(A)  
(A)  
DESEL  
DESEL  
A. DESELECTED IS PROGRAMMABLE EITHER HIGH OR  
3−STATE (REQUIRES EXTERNAL PULLUP)  
Figure 4-42. SPI Timings—Slave Mode (4-Pin and 5-Pin)  
154  
Specifications  
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4.7.6.11 Inter-Integrated Circuit Serial Ports (I2C)  
4.7.6.11.1 I2C Device-Specific Information  
Each I2C port supports:  
•
•
•
•
•
•
•
Compatible with Philips® I2C Specification Revision 2.1 (January 2000)  
Fast Mode up to 400 Kbps (no fail-safe I/O buffers)  
Noise Filter to Remove Noise 50 ns or less  
Seven- and Ten-Bit Device Addressing Modes  
Master (Transmit/Receive) and Slave (Transmit/Receive) Functionality  
Events: DMA, Interrupt, or Polling  
General-Purpose I/O Capability if not used as I2C  
Figure 4-43 is block diagram of the device I2C Module.  
Clock Prescaler  
Control  
I2CCOARx  
Prescaler  
Register  
Own Address  
Register  
I2CPSCx  
Slave Address  
Register  
I2CSARx  
Bit Clock Generator  
Noise  
I2Cx_SCL  
Clock Divide  
High Register  
I2CCLKHx  
Filter  
I2CCMDRx  
I2CEMDRx  
I2CCNTx  
I2CPID1  
Mode Register  
Extended Mode  
Register  
Clock Divide  
Low Register  
I2CCLKLx  
Data Count  
Register  
Peripheral  
Configuration  
Bus  
Transmit  
Peripheral ID  
Register 1  
Transmit Shift  
Register  
I2CXSRx  
I2CDXRx  
Peripheral ID  
Register 2  
I2CPID2  
Transmit Buffer  
Noise  
Filter  
I2Cx_SDA  
Interrupt/DMA  
Interrupt Enable  
Register  
Receive  
I2CIERx  
Interrupt DMA  
Requests  
Receive Buffer  
I2CDRRx  
I2CRSRx  
Interrupt Status  
Register  
I2CSTRx  
I2CSRCx  
Receive Shift  
Register  
Interrupt Source  
Register  
Control  
Pin Function  
Register  
Pin Data Out  
Register  
I2CPDOUT  
I2CPFUNC  
I2CPDIR  
I2CPDIN  
Pin Direction  
Register  
Pin Data In  
Register  
Pin Data Set  
Register  
Pin Data Clear  
Register  
I2CPDSET  
I2CPDCLR  
Figure 4-43. I2C Module Block Diagram  
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4.7.6.11.2 I2C Peripheral Registers Description(s)  
Table 4-84 is the list of the I2C registers.  
Table 4-84. Inter-Integrated Circuit (I2C) Registers  
I2C0  
BYTE ADDRESS  
I2C1  
ACRONYM  
REGISTER DESCRIPTION  
I2C Own Address Register  
BYTE ADDRESS  
0x01E2 8000  
0x01E2 8004  
0x01E2 8008  
0x01E2 800C  
0x01E2 8010  
0x01E2 8014  
0x01E2 8018  
0x01E2 801C  
0x01E2 8020  
0x01E2 8024  
0x01E2 8028  
0x01E2 802C  
0x01E2 8030  
0x01E2 8034  
0x01E2 8038  
0x01E2 8048  
0x01E2 804C  
0x01E2 8050  
0x01E2 8054  
0x01E2 8058  
0x01E2 805C  
0x01C2 2000  
0x01C2 2004  
0x01C2 2008  
0x01C2 200C  
0x01C2 2010  
0x01C2 2014  
0x01C2 2018  
0x01C2 201C  
0x01C2 2020  
0x01C2 2024  
0x01C2 2028  
0x01C2 202C  
0x01C2 2030  
0x01C2 2034  
0x01C2 2038  
0x01C2 2048  
0x01C2 204C  
0x01C2 2050  
0x01C2 2054  
0x01C2 2058  
0x01C2 205C  
ICOAR  
ICIMR  
I2C Interrupt Mask Register  
I2C Interrupt Status Register  
I2C Clock Low-Time Divider Register  
I2C Clock High-Time Divider Register  
I2C Data Count Register  
ICSTR  
ICCLKL  
ICCLKH  
ICCNT  
ICDRR  
I2C Data Receive Register  
I2C Slave Address Register  
I2C Data Transmit Register  
I2C Mode Register  
ICSAR  
ICDXR  
ICMDR  
ICIVR  
I2C Interrupt Vector Register  
I2C Extended Mode Register  
I2C Prescaler Register  
ICEMDR  
ICPSC  
REVID1  
REVID2  
ICPFUNC  
ICPDIR  
ICPDIN  
ICPDOUT  
ICPDSET  
ICPDCLR  
I2C Revision Identification Register 1  
I2C Revision Identification Register 2  
I2C Pin Function Register  
I2C Pin Direction Register  
I2C Pin Data In Register  
I2C Pin Data Out Register  
I2C Pin Data Set Register  
I2C Pin Data Clear Register  
156  
Specifications  
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4.7.6.11.3 I2C Electrical Data/Timing  
4.7.6.11.3.1 Inter-Integrated Circuit (I2C) Timing  
Table 4-85 and Table 4-86 assume testing over recommended operating conditions (see Figure 4-44 and  
Figure 4-45).  
Table 4-85. Timing Requirements for I2C Input  
1.3V, 1.2V, 1.1V, 1.0V  
NO.  
Standard Mode  
Fast Mode  
MIN  
UNIT  
MIN  
10  
4.7  
4
MAX  
MAX  
1
2
tc(SCL)  
Cycle time, I2Cx_SCL  
2.5  
μs  
μs  
μs  
μs  
μs  
ns  
μs  
μs  
ns  
ns  
ns  
ns  
μs  
ns  
pF  
tsu(SCLH-SDAL) Setup time, I2Cx_SCL high before I2Cx_SDA low  
0.6  
3
th(SCLL-SDAL)  
tw(SCLL)  
Hold time, I2Cx_SCL low after I2Cx_SDA low  
Pulse duration, I2Cx_SCL low  
Pulse duration, I2Cx_SCL high  
Setup time, I2Cx_SDA before I2Cx_SCL high  
Hold time, I2Cx_SDA after I2Cx_SCL low  
Pulse duration, I2Cx_SDA high  
Rise time, I2Cx_SDA  
0.6  
4
4.7  
4
1.3  
5
tw(SCLH)  
tsu(SDA-SCLH)  
th(SDA-SCLL)  
tw(SDAH)  
tr(SDA)  
0.6  
100  
6
250  
0
7
0
0.9  
8
4.7  
1.3  
9
1000  
1000  
300  
20 + 0.1Cb  
20 + 0.1Cb  
20 + 0.1Cb  
20 + 0.1Cb  
0.6  
300  
300  
300  
300  
10  
11  
12  
13  
14  
15  
tr(SCL)  
Rise time, I2Cx_SCL  
tf(SDA)  
Fall time, I2Cx_SDA  
tf(SCL)  
Fall time, I2Cx_SCL  
300  
tsu(SCLH-SDAH) Setup time, I2Cx_SCL high before I2Cx_SDA high  
4
tw(SP)  
Cb  
Pulse duration, spike (must be suppressed)  
Capacitive load for each bus line  
N/A  
0
50  
400  
400  
(1)  
Table 4-86. Switching Characteristics for I2C  
1.3V, 1.2V, 1.1V, 1.0V  
NO.  
PARAMETER  
Standard Mode  
Fast Mode  
UNIT  
MIN  
10  
4.7  
4
MAX  
MIN  
2.5  
0.6  
0.6  
1.3  
0.6  
100  
0
MAX  
16  
17  
18  
19  
20  
21  
22  
23  
28  
tc(SCL)  
Cycle time, I2Cx_SCL  
μs  
μs  
μs  
μs  
μs  
ns  
μs  
μs  
μs  
tsu(SCLH-SDAL) Setup time, I2Cx_SCL high before I2Cx_SDA low  
th(SDAL-SCLL)  
tw(SCLL)  
Hold time, I2Cx_SCL low after I2Cx_SDA low  
Pulse duration, I2Cx_SCL low  
4.7  
4
tw(SCLH)  
Pulse duration, I2Cx_SCL high  
tsu(SDAV-SCLH) Setup time, I2Cx_SDA valid before I2Cx_SCL high  
250  
0
th(SCLL-SDAV)  
tw(SDAH)  
Hold time, I2Cx_SDA valid after I2Cx_SCL low  
Pulse duration, I2Cx_SDA high  
0.9  
4.7  
4
1.3  
0.6  
tsu(SCLH-SDAH) Setup time, I2Cx_SCL high before I2Cx_SDA high  
(1) I2C must be configured correctly to meet the timings in Table 4-86.  
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11  
9
I2Cx_SDA  
I2Cx_SCL  
6
8
14  
4
13  
5
10  
1
12  
3
2
7
3
Stop  
Start  
Repeated  
Start  
Stop  
Figure 4-44. I2C Receive Timings  
26  
24  
I2Cx_SDA  
I2Cx_SCL  
21  
23  
19  
28  
20  
25  
16  
27  
18  
17  
22  
18  
Stop  
Start  
Repeated  
Start  
Stop  
Figure 4-45. I2C Transmit Timings  
158  
Specifications  
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4.7.6.12 Universal Asynchronous Receiver/Transmitter (UART)  
Each UART has the following features:  
•
•
•
•
•
•
•
•
•
16-byte storage space for both the transmitter and receiver FIFOs  
1, 4, 8, or 14 byte selectable receiver FIFO trigger level for autoflow control and DMA  
DMA signaling capability for both received and transmitted data  
Programmable auto-rts and auto-cts for autoflow control  
Programmable Baud Rate up to 12 MBaud  
Programmable Oversampling Options of x13 and x16  
Frequency pre-scale values from 1 to 65,535 to generate appropriate baud rates  
Prioritized interrupts  
Programmable serial data formats  
–
–
–
5, 6, 7, or 8-bit characters  
Even, odd, or no parity bit generation and detection  
1, 1.5, or 2 stop bit generation  
•
•
•
False start bit detection  
Line break generation and detection  
Internal diagnostic capabilities  
–
–
Loopback controls for communications link fault isolation  
Break, parity, overrun, and framing error simulation  
•
Modem control functions (CTS, RTS)  
The UART registers are listed in Section 4.7.6.12.1  
4.7.6.12.1 UART Peripheral Registers Description(s)  
Table 4-87 is the list of UART registers.  
Table 4-87. UART Registers  
UART0  
BYTE ADDRESS  
UART1  
BYTE ADDRESS  
UART2  
ACRONYM  
REGISTER DESCRIPTION  
BYTE ADDRESS  
0x01D0 D000  
0x01D0 D000  
0x01D0 D004  
0x01D0 D008  
0x01D0 D008  
0x01D0 D00C  
0x01D0 D010  
0x01D0 D014  
0x01D0 D018  
0x01D0 D01C  
0x01D0 D020  
0x01D0 D024  
0x01D0 D028  
0x01D0 D030  
0x01D0 D034  
0x01C4 2000  
0x01C4 2000  
0x01C4 2004  
0x01C4 2008  
0x01C4 2008  
0x01C4 200C  
0x01C4 2010  
0x01C4 2014  
0x01C4 2018  
0x01C4 201C  
0x01C4 2020  
0x01C4 2024  
0x01C4 2028  
0x01C4 2030  
0x01C4 2034  
0x01D0 C000  
0x01D0 C000  
0x01D0 C004  
0x01D0 C008  
0x01D0 C008  
0x01D0 C00C  
0x01D0 C010  
0x01D0 C014  
0x01D0 C018  
0x01D0 C01C  
0x01D0 C020  
0x01D0 C024  
0x01D0 C028  
0x01D0 C030  
0x01D0 C034  
RBR  
THR  
IER  
Receiver Buffer Register (read only)  
Transmitter Holding Register (write only)  
Interrupt Enable Register  
Interrupt Identification Register (read only)  
FIFO Control Register (write only)  
Line Control Register  
IIR  
FCR  
LCR  
MCR  
LSR  
Modem Control Register  
Line Status Register  
MSR  
SCR  
DLL  
Modem Status Register  
Scratchpad Register  
Divisor LSB Latch  
DLH  
REVID1  
Divisor MSB Latch  
Revision Identification Register 1  
PWREMU_MGMT Power and Emulation Management Register  
MDR Mode Definition Register  
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4.7.6.12.2 UART Electrical Data/Timing  
Table 4-88. Timing Requirements for UART Receive(1) (see Figure 4-46)  
1.3V, 1.2V, 1.1V, 1.0V  
NO.  
UNIT  
MIN  
MAX  
1.05U  
1.05U  
4
5
tw(URXDB)  
tw(URXSB)  
Pulse duration, receive data bit (RXDn)  
Pulse duration, receive start bit  
0.96U  
0.96U  
ns  
ns  
(1) U = UART baud time = 1/programmed baud rate.  
Table 4-89. Switching Characteristics Over Recommended Operating Conditions for UARTx Transmit(1)  
(see Figure 4-46)  
1.3V, 1.2V, 1.1V, 1.0V  
NO.  
PARAMETER  
UNIT  
MIN  
MAX  
(2) (3)  
(4)  
1
2
3
f(baud)  
Maximum programmable baud rate  
Pulse duration, transmit data bit (TXDn)  
Pulse duration, transmit start bit  
D/E  
MBaud  
ns  
tw(UTXDB)  
tw(UTXSB)  
U - 2  
U - 2  
U + 2  
U + 2  
ns  
(1) U = UART baud time = 1/programmed baud rate.  
(2) D = UART input clock in MHz.  
For UART0, the UART input clock is SYSCLK2.  
For UART1 or UART2, the UART input clock is ASYNC3 (either PLL0_SYCLK2 or PLL1_SYSCLK2).  
(3) E = UART divisor x UART sampling rate. The UART divisor is set through the UART divisor latch registers (DLL and DLH). The UART  
sampling rate is set through the over-sampling mode select bit (OSM_SEL) of the UART mode definition register (MDR).  
(4) Baud rate is not indicative of data rate. Actual data rate will be limited by system factors such as EDMA loading, EMIF/DDR loading,  
system frequency, etc.  
3
2
Start  
UART_TXDn  
Bit  
Data Bits  
5
4
Start  
Bit  
UART_RXDn  
Data Bits  
Figure 4-46. UART Transmit/Receive Timing  
160  
Specifications  
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4.7.6.13 Universal Serial Bus OTG Controller (USB0) [USB2.0 OTG]  
The USB2.0 peripheral supports the following features:  
•
•
•
•
•
USB 2.0 peripheral at speeds high speed (HS: 480 Mb/s) and full speed (FS: 12 Mb/s)  
USB 2.0 host at speeds HS, FS, and low speed (LS: 1.5 Mb/s)  
All transfer modes (control, bulk, interrupt, and isochronous)  
4 Transmit (TX) and 4 Receive (RX) endpoints in addition to endpoint 0  
FIFO RAM  
–
–
4K endpoint  
Programmable size  
•
•
•
Integrated USB 2.0 High Speed PHY  
Connects to a standard Charge Pump for VBUS 5 V generation  
RNDIS mode for accelerating RNDIS type protocols using short packet termination over USB  
Important Notice: The USB0 controller module clock (PLL0_SYSCLK2) must be greater than 30 MHz for  
proper operation of the USB controller. A clock rate of 60 MHz or greater is recommended to avoid data  
throughput reduction.  
Table 4-90 is the list of USB OTG registers.  
Table 4-90. Universal Serial Bus OTG (USB0) Registers  
BYTE ADDRESS  
0x01E0 0000  
0x01E0 0004  
0x01E0 0008  
0x01E0 000C  
0x01E0 0010  
0x01E0 0014  
0x01E0 0018  
0x01E0 001C  
0x01E0 0020  
0x01E0 0024  
0x01E0 0028  
0x01E0 002C  
0x01E0 0030  
0x01E0 0034  
0x01E0 0038  
0x01E0 003C  
0x01E0 0040  
0x01E0 0050  
0x01E0 0054  
0x01E0 0058  
0x01E0 005C  
0x01E0 0400  
0x01E0 0401  
0x01E0 0402  
0x01E0 0404  
0x01E0 0406  
0x01E0 0408  
0x01E0 040A  
0x01E0 040B  
ACRONYM  
REVID  
REGISTER DESCRIPTION  
Revision Register  
CTRLR  
Control Register  
STATR  
Status Register  
EMUR  
Emulation Register  
MODE  
Mode Register  
AUTOREQ  
SRPFIXTIME  
TEARDOWN  
INTSRCR  
INTSETR  
INTCLRR  
INTMSKR  
INTMSKSETR  
INTMSKCLRR  
INTMASKEDR  
EOIR  
Autorequest Register  
SRP Fix Time Register  
Teardown Register  
USB Interrupt Source Register  
USB Interrupt Source Set Register  
USB Interrupt Source Clear Register  
USB Interrupt Mask Register  
USB Interrupt Mask Set Register  
USB Interrupt Mask Clear Register  
USB Interrupt Source Masked Register  
USB End of Interrupt Register  
Reserved  
-
GENRNDISSZ1  
GENRNDISSZ2  
GENRNDISSZ3  
GENRNDISSZ4  
FADDR  
Generic RNDIS Size EP1  
Generic RNDIS Size EP2  
Generic RNDIS Size EP3  
Generic RNDIS Size EP4  
Function Address Register  
Power Management Register  
Interrupt Register for Endpoint 0 plus Transmit Endpoints 1 to 4  
Interrupt Register for Receive Endpoints 1 to 4  
Interrupt enable register for INTRTX  
Interrupt Enable Register for INTRRX  
Interrupt Register for Common USB Interrupts  
Interrupt Enable Register for INTRUSB  
POWER  
INTRTX  
INTRRX  
INTRTXE  
INTRRXE  
INTRUSB  
INTRUSBE  
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Table 4-90. Universal Serial Bus OTG (USB0) Registers (continued)  
BYTE ADDRESS  
0x01E0 040C  
0x01E0 040E  
0x01E0 040F  
ACRONYM  
FRAME  
REGISTER DESCRIPTION  
Frame Number Register  
INDEX  
Index Register for Selecting the Endpoint Status and Control Registers  
Register to Enable the USB 2.0 Test Modes  
Indexed Registers  
TESTMODE  
These registers operate on the endpoint selected by the INDEX register  
0x01E0 0410  
0x01E0 0412  
TXMAXP  
PERI_CSR0  
HOST_CSR0  
PERI_TXCSR  
HOST_TXCSR  
RXMAXP  
Maximum Packet Size for Peripheral/Host Transmit Endpoint  
(Index register set to select Endpoints 1-4 only)  
Control Status Register for Endpoint 0 in Peripheral Mode.  
(Index register set to select Endpoint 0)  
Control Status Register for Endpoint 0 in Host Mode.  
(Index register set to select Endpoint 0)  
Control Status Register for Peripheral Transmit Endpoint.  
(Index register set to select Endpoints 1-4)  
Control Status Register for Host Transmit Endpoint.  
(Index register set to select Endpoints 1-4)  
0x01E0 0414  
0x01E0 0416  
Maximum Packet Size for Peripheral/Host Receive Endpoint  
(Index register set to select Endpoints 1-4 only)  
PERI_RXCSR  
HOST_RXCSR  
COUNT0  
Control Status Register for Peripheral Receive Endpoint.  
(Index register set to select Endpoints 1-4)  
Control Status Register for Host Receive Endpoint.  
(Index register set to select Endpoints 1-4)  
0x01E0 0418  
Number of Received Bytes in Endpoint 0 FIFO.  
(Index register set to select Endpoint 0)  
RXCOUNT  
Number of Bytes in Host Receive Endpoint FIFO.  
(Index register set to select Endpoints 1- 4)  
0x01E0 041A  
0x01E0 041B  
HOST_TYPE0  
Defines the speed of Endpoint 0  
HOST_TXTYPE  
Sets the operating speed, transaction protocol and peripheral endpoint number for  
the host Transmit endpoint. (Index register set to select Endpoints 1-4 only)  
HOST_NAKLIMIT0  
Sets the NAK response timeout on Endpoint 0.  
(Index register set to select Endpoint 0)  
HOST_TXINTERVAL  
Sets the polling interval for Interrupt/ISOC transactions or the NAK response  
timeout on Bulk transactions for host Transmit endpoint. (Index register set to  
select Endpoints 1-4 only)  
0x01E0 041C  
0x01E0 041D  
HOST_RXTYPE  
Sets the operating speed, transaction protocol and peripheral endpoint number for  
the host Receive endpoint. (Index register set to select Endpoints 1-4 only)  
HOST_RXINTERVAL  
Sets the polling interval for Interrupt/ISOC transactions or the NAK response  
timeout on Bulk transactions for host Receive endpoint. (Index register set to select  
Endpoints 1-4 only)  
0x01E0 041F  
CONFIGDATA  
Returns details of core configuration. (Index register set to select Endpoint 0)  
FIFO  
0x01E0 0420  
0x01E0 0424  
0x01E0 0428  
0x01E0 042C  
0x01E0 0430  
FIFO0  
FIFO1  
FIFO2  
FIFO3  
FIFO4  
Transmit and Receive FIFO Register for Endpoint 0  
Transmit and Receive FIFO Register for Endpoint 1  
Transmit and Receive FIFO Register for Endpoint 2  
Transmit and Receive FIFO Register for Endpoint 3  
Transmit and Receive FIFO Register for Endpoint 4  
OTG Device Control  
0x01E0 0460  
DEVCTL  
Device Control Register  
Dynamic FIFO Control  
0x01E0 0462  
0x01E0 0463  
0x01E0 0464  
TXFIFOSZ  
RXFIFOSZ  
Transmit Endpoint FIFO Size  
(Index register set to select Endpoints 1-4 only)  
Receive Endpoint FIFO Size  
(Index register set to select Endpoints 1-4 only)  
TXFIFOADDR  
Transmit Endpoint FIFO Address  
(Index register set to select Endpoints 1-4 only)  
162  
Specifications  
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ZHCSFA2 –JUNE 2016  
Table 4-90. Universal Serial Bus OTG (USB0) Registers (continued)  
BYTE ADDRESS  
ACRONYM  
REGISTER DESCRIPTION  
0x01E0 0466  
RXFIFOADDR  
Receive Endpoint FIFO Address  
(Index register set to select Endpoints 1-4 only)  
0x01E0 046C  
HWVERS  
Hardware Version Register  
Target Endpoint 0 Control Registers, Valid Only in Host Mode  
0x01E0 0480  
0x01E0 0482  
TXFUNCADDR  
Address of the target function that has to be accessed through the associated  
Transmit Endpoint.  
TXHUBADDR  
Address of the hub that has to be accessed through the associated Transmit  
Endpoint. This is used only when full speed or low speed device is connected via a  
USB2.0 high-speed hub.  
0x01E0 0483  
TXHUBPORT  
Port of the hub that has to be accessed through the associated Transmit Endpoint.  
This is used only when full speed or low speed device is connected via a USB2.0  
high-speed hub.  
0x01E0 0484  
0x01E0 0486  
RXFUNCADDR  
RXHUBADDR  
Address of the target function that has to be accessed through the associated  
Receive Endpoint.  
Address of the hub that has to be accessed through the associated Receive  
Endpoint. This is used only when full speed or low speed device is connected via a  
USB2.0 high-speed hub.  
0x01E0 0487  
RXHUBPORT  
Port of the hub that has to be accessed through the associated Receive Endpoint.  
This is used only when full speed or low speed device is connected via a USB2.0  
high-speed hub.  
Target Endpoint 1 Control Registers, Valid Only in Host Mode  
0x01E0 0488  
0x01E0 048A  
TXFUNCADDR  
Address of the target function that has to be accessed through the associated  
Transmit Endpoint.  
TXHUBADDR  
Address of the hub that has to be accessed through the associated Transmit  
Endpoint. This is used only when full speed or low speed device is connected via a  
USB2.0 high-speed hub.  
0x01E0 048B  
TXHUBPORT  
Port of the hub that has to be accessed through the associated Transmit Endpoint.  
This is used only when full speed or low speed device is connected via a USB2.0  
high-speed hub.  
0x01E0 048C  
0x01E0 048E  
RXFUNCADDR  
RXHUBADDR  
Address of the target function that has to be accessed through the associated  
Receive Endpoint.  
Address of the hub that has to be accessed through the associated Receive  
Endpoint. This is used only when full speed or low speed device is connected via a  
USB2.0 high-speed hub.  
0x01E0 048F  
RXHUBPORT  
Port of the hub that has to be accessed through the associated Receive Endpoint.  
This is used only when full speed or low speed device is connected via a USB2.0  
high-speed hub.  
Target Endpoint 2 Control Registers, Valid Only in Host Mode  
0x01E0 0490  
0x01E0 0492  
TXFUNCADDR  
Address of the target function that has to be accessed through the associated  
Transmit Endpoint.  
TXHUBADDR  
Address of the hub that has to be accessed through the associated Transmit  
Endpoint. This is used only when full speed or low speed device is connected via a  
USB2.0 high-speed hub.  
0x01E0 0493  
TXHUBPORT  
Port of the hub that has to be accessed through the associated Transmit Endpoint.  
This is used only when full speed or low speed device is connected via a USB2.0  
high-speed hub.  
0x01E0 0494  
0x01E0 0496  
RXFUNCADDR  
RXHUBADDR  
Address of the target function that has to be accessed through the associated  
Receive Endpoint.  
Address of the hub that has to be accessed through the associated Receive  
Endpoint. This is used only when full speed or low speed device is connected via a  
USB2.0 high-speed hub.  
0x01E0 0497  
0x01E0 0498  
RXHUBPORT  
Port of the hub that has to be accessed through the associated Receive Endpoint.  
This is used only when full speed or low speed device is connected via a USB2.0  
high-speed hub.  
Target Endpoint 3 Control Registers, Valid Only in Host Mode  
TXFUNCADDR Address of the target function that has to be accessed through the associated  
Transmit Endpoint.  
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Specifications  
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Table 4-90. Universal Serial Bus OTG (USB0) Registers (continued)  
BYTE ADDRESS  
ACRONYM  
REGISTER DESCRIPTION  
0x01E0 049A  
TXHUBADDR  
Address of the hub that has to be accessed through the associated Transmit  
Endpoint. This is used only when full speed or low speed device is connected via a  
USB2.0 high-speed hub.  
0x01E0 049B  
TXHUBPORT  
Port of the hub that has to be accessed through the associated Transmit Endpoint.  
This is used only when full speed or low speed device is connected via a USB2.0  
high-speed hub.  
0x01E0 049C  
0x01E0 049E  
RXFUNCADDR  
RXHUBADDR  
Address of the target function that has to be accessed through the associated  
Receive Endpoint.  
Address of the hub that has to be accessed through the associated Receive  
Endpoint. This is used only when full speed or low speed device is connected via a  
USB2.0 high-speed hub.  
0x01E0 049F  
RXHUBPORT  
Port of the hub that has to be accessed through the associated Receive Endpoint.  
This is used only when full speed or low speed device is connected via a USB2.0  
high-speed hub.  
Target Endpoint 4 Control Registers, Valid Only in Host Mode  
0x01E0 04A0  
0x01E0 04A2  
TXFUNCADDR  
Address of the target function that has to be accessed through the associated  
Transmit Endpoint.  
TXHUBADDR  
Address of the hub that has to be accessed through the associated Transmit  
Endpoint. This is used only when full speed or low speed device is connected via a  
USB2.0 high-speed hub.  
0x01E0 04A3  
TXHUBPORT  
Port of the hub that has to be accessed through the associated Transmit Endpoint.  
This is used only when full speed or low speed device is connected via a USB2.0  
high-speed hub.  
0x01E0 04A4  
0x01E0 04A6  
RXFUNCADDR  
RXHUBADDR  
Address of the target function that has to be accessed through the associated  
Receive Endpoint.  
Address of the hub that has to be accessed through the associated Receive  
Endpoint. This is used only when full speed or low speed device is connected via a  
USB2.0 high-speed hub.  
0x01E0 04A7  
RXHUBPORT  
Port of the hub that has to be accessed through the associated Receive Endpoint.  
This is used only when full speed or low speed device is connected via a USB2.0  
high-speed hub.  
Control and Status Register for Endpoint 0  
0x01E0 0502  
PERI_CSR0  
Control Status Register for Endpoint 0 in Peripheral Mode  
Control Status Register for Endpoint 0 in Host Mode  
Number of Received Bytes in Endpoint 0 FIFO  
Defines the Speed of Endpoint 0  
HOST_CSR0  
COUNT0  
0x01E0 0508  
0x01E0 050A  
0x01E0 050B  
0x01E0 050F  
HOST_TYPE0  
HOST_NAKLIMIT0  
CONFIGDATA  
Sets the NAK Response Timeout on Endpoint 0  
Returns details of core configuration.  
Control and Status Register for Endpoint 1  
0x01E0 0510  
0x01E0 0512  
TXMAXP  
Maximum Packet Size for Peripheral/Host Transmit Endpoint  
PERI_TXCSR  
HOST_TXCSR  
RXMAXP  
Control Status Register for Peripheral Transmit Endpoint (peripheral mode)  
Control Status Register for Host Transmit Endpoint (host mode)  
Maximum Packet Size for Peripheral/Host Receive Endpoint  
Control Status Register for Peripheral Receive Endpoint (peripheral mode)  
Control Status Register for Host Receive Endpoint (host mode)  
Number of Bytes in Host Receive endpoint FIFO  
0x01E0 0514  
0x01E0 0516  
PERI_RXCSR  
HOST_RXCSR  
RXCOUNT  
0x01E0 0518  
0x01E0 051A  
HOST_TXTYPE  
Sets the operating speed, transaction protocol and peripheral endpoint number for  
the host Transmit endpoint.  
0x01E0 051B  
0x01E0 051C  
0x01E0 051D  
HOST_TXINTERVAL  
HOST_RXTYPE  
Sets the polling interval for Interrupt/ISOC transactions or the NAK response  
timeout on Bulk transactions for host Transmit endpoint.  
Sets the operating speed, transaction protocol and peripheral endpoint number for  
the host Receive endpoint.  
HOST_RXINTERVAL  
Sets the polling interval for Interrupt/ISOC transactions or the NAK response  
timeout on Bulk transactions for host Receive endpoint.  
Control and Status Register for Endpoint 2  
164  
Specifications  
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Table 4-90. Universal Serial Bus OTG (USB0) Registers (continued)  
BYTE ADDRESS  
ACRONYM  
TXMAXP  
REGISTER DESCRIPTION  
0x01E0 0520  
0x01E0 0522  
Maximum Packet Size for Peripheral/Host Transmit Endpoint  
Control Status Register for Peripheral Transmit Endpoint (peripheral mode)  
Control Status Register for Host Transmit Endpoint (host mode)  
Maximum Packet Size for Peripheral/Host Receive Endpoint  
Control Status Register for Peripheral Receive Endpoint (peripheral mode)  
Control Status Register for Host Receive Endpoint (host mode)  
Number of Bytes in Host Receive endpoint FIFO  
PERI_TXCSR  
HOST_TXCSR  
RXMAXP  
0x01E0 0524  
0x01E0 0526  
PERI_RXCSR  
HOST_RXCSR  
RXCOUNT  
0x01E0 0528  
0x01E0 052A  
HOST_TXTYPE  
Sets the operating speed, transaction protocol and peripheral endpoint number for  
the host Transmit endpoint.  
0x01E0 052B  
0x01E0 052C  
0x01E0 052D  
HOST_TXINTERVAL  
HOST_RXTYPE  
Sets the polling interval for Interrupt/ISOC transactions or the NAK response  
timeout on Bulk transactions for host Transmit endpoint.  
Sets the operating speed, transaction protocol and peripheral endpoint number for  
the host Receive endpoint.  
HOST_RXINTERVAL  
Sets the polling interval for Interrupt/ISOC transactions or the NAK response  
timeout on Bulk transactions for host Receive endpoint.  
Control and Status Register for Endpoint 3  
0x01E0 0530  
0x01E0 0532  
TXMAXP  
Maximum Packet Size for Peripheral/Host Transmit Endpoint  
PERI_TXCSR  
HOST_TXCSR  
RXMAXP  
Control Status Register for Peripheral Transmit Endpoint (peripheral mode)  
Control Status Register for Host Transmit Endpoint (host mode)  
Maximum Packet Size for Peripheral/Host Receive Endpoint  
Control Status Register for Peripheral Receive Endpoint (peripheral mode)  
Control Status Register for Host Receive Endpoint (host mode)  
Number of Bytes in Host Receive endpoint FIFO  
0x01E0 0534  
0x01E0 0536  
PERI_RXCSR  
HOST_RXCSR  
RXCOUNT  
0x01E0 0538  
0x01E0 053A  
HOST_TXTYPE  
Sets the operating speed, transaction protocol and peripheral endpoint number for  
the host Transmit endpoint.  
0x01E0 053B  
0x01E0 053C  
0x01E0 053D  
HOST_TXINTERVAL  
HOST_RXTYPE  
Sets the polling interval for Interrupt/ISOC transactions or the NAK response  
timeout on Bulk transactions for host Transmit endpoint.  
Sets the operating speed, transaction protocol and peripheral endpoint number for  
the host Receive endpoint.  
HOST_RXINTERVAL  
Sets the polling interval for Interrupt/ISOC transactions or the NAK response  
timeout on Bulk transactions for host Receive endpoint.  
Control and Status Register for Endpoint 4  
0x01E0 0540  
0x01E0 0542  
TXMAXP  
Maximum Packet Size for Peripheral/Host Transmit Endpoint  
PERI_TXCSR  
HOST_TXCSR  
RXMAXP  
Control Status Register for Peripheral Transmit Endpoint (peripheral mode)  
Control Status Register for Host Transmit Endpoint (host mode)  
Maximum Packet Size for Peripheral/Host Receive Endpoint  
Control Status Register for Peripheral Receive Endpoint (peripheral mode)  
Control Status Register for Host Receive Endpoint (host mode)  
Number of Bytes in Host Receive endpoint FIFO  
0x01E0 0544  
0x01E0 0546  
PERI_RXCSR  
HOST_RXCSR  
RXCOUNT  
0x01E0 0548  
0x01E0 054A  
HOST_TXTYPE  
Sets the operating speed, transaction protocol and peripheral endpoint number for  
the host Transmit endpoint.  
0x01E0 054B  
0x01E0 054C  
0x01E0 054D  
HOST_TXINTERVAL  
HOST_RXTYPE  
Sets the polling interval for Interrupt/ISOC transactions or the NAK response  
timeout on Bulk transactions for host Transmit endpoint.  
Sets the operating speed, transaction protocol and peripheral endpoint number for  
the host Receive endpoint.  
HOST_RXINTERVAL  
Sets the polling interval for Interrupt/ISOC transactions or the NAK response  
timeout on Bulk transactions for host Receive endpoint.  
DMA Registers  
0x01E0 1000  
0x01E0 1004  
0x01E0 1008  
DMAREVID  
TDFDQ  
DMA Revision Register  
DMA Teardown Free Descriptor Queue Control Register  
DMA Emulation Control Register  
DMAEMU  
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Specifications  
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Table 4-90. Universal Serial Bus OTG (USB0) Registers (continued)  
BYTE ADDRESS  
0x01E0 1800  
0x01E0 1808  
0x01E0 180C  
0x01E0 1810  
0x01E0 1820  
0x01E0 1828  
0x01E0 182C  
0x01E0 1830  
0x01E0 1840  
0x01E0 1848  
0x01E0 184C  
0x01E0 1850  
0x01E0 1860  
0x01E0 1868  
0x01E0 186C  
0x01E0 1870  
0x01E0 2000  
0x01E0 2800  
0x01E0 2804  
. . .  
ACRONYM  
TXGCR[0]  
REGISTER DESCRIPTION  
Transmit Channel 0 Global Configuration Register  
Receive Channel 0 Global Configuration Register  
Receive Channel 0 Host Packet Configuration Register A  
Receive Channel 0 Host Packet Configuration Register B  
Transmit Channel 1 Global Configuration Register  
Receive Channel 1 Global Configuration Register  
Receive Channel 1 Host Packet Configuration Register A  
Receive Channel 1 Host Packet Configuration Register B  
Transmit Channel 2 Global Configuration Register  
Receive Channel 2 Global Configuration Register  
Receive Channel 2 Host Packet Configuration Register A  
Receive Channel 2 Host Packet Configuration Register B  
Transmit Channel 3 Global Configuration Register  
Receive Channel 3 Global Configuration Register  
Receive Channel 3 Host Packet Configuration Register A  
Receive Channel 3 Host Packet Configuration Register B  
DMA Scheduler Control Register  
RXGCR[0]  
RXHPCRA[0]  
RXHPCRB[0]  
TXGCR[1]  
RXGCR[1]  
RXHPCRA[1]  
RXHPCRB[1]  
TXGCR[2]  
RXGCR[2]  
RXHPCRA[2]  
RXHPCRB[2]  
TXGCR[3]  
RXGCR[3]  
RXHPCRA[3]  
RXHPCRB[3]  
DMA_SCHED_CTRL  
WORD[0]  
DMA Scheduler Table Word 0  
WORD[1]  
DMA Scheduler Table Word 1  
. . .  
. . .  
0x01E0 28FC  
WORD[63]  
DMA Scheduler Table Word 63  
Queue Manager Registers  
0x01E0 4000  
0x01E0 4008  
0x01E0 4020  
0x01E0 4024  
0x01E0 4028  
0x01E0 402C  
0x01E0 4080  
0x01E0 4084  
0x01E0 4088  
0x01E0 4090  
0x01E0 4094  
0x01E0 5000  
0x01E0 5004  
0x01E0 5010  
0x01E0 5014  
. . .  
QMGRREVID  
DIVERSION  
FDBSC0  
Queue Manager Revision Register  
Queue Diversion Register  
Free Descriptor/Buffer Starvation Count Register 0  
Free Descriptor/Buffer Starvation Count Register 1  
Free Descriptor/Buffer Starvation Count Register 2  
Free Descriptor/Buffer Starvation Count Register 3  
Linking RAM Region 0 Base Address Register  
Linking RAM Region 0 Size Register  
FDBSC1  
FDBSC2  
FDBSC3  
LRAM0BASE  
LRAM0SIZE  
LRAM1BASE  
PEND0  
Linking RAM Region 1 Base Address Register  
Queue Pending Register 0  
PEND1  
Queue Pending Register 1  
QMEMRBASE[0]  
QMEMRCTRL[0]  
QMEMRBASE[1]  
QMEMRCTRL[1]  
. . .  
Memory Region 0 Base Address Register  
Memory Region 0 Control Register  
Memory Region 1 Base Address Register  
Memory Region 1 Control Register  
. . .  
0x01E0 50F0  
0x01E0 50F4  
0x01E0 600C  
0x01E0 601C  
. . .  
QMEMRBASE[15]  
QMEMRCTRL[15]  
CTRLD[0]  
Memory Region 15 Base Address Register  
Memory Region 15 Control Register  
Queue Manager Queue 0 Control Register D  
Queue Manager Queue 1 Control Register D  
. . .  
CTRLD[1]  
. . .  
0x01E0 63FC  
0x01E0 6800  
0x01E0 6804  
0x01E0 6808  
CTRLD[63]  
QSTATA[0]  
QSTATB[0]  
QSTATC[0]  
Queue Manager Queue 63 Status Register D  
Queue Manager Queue 0 Status Register A  
Queue Manager Queue 0 Status Register B  
Queue Manager Queue 0 Status Register C  
166  
Specifications  
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Table 4-90. Universal Serial Bus OTG (USB0) Registers (continued)  
BYTE ADDRESS  
ACRONYM  
QSTATA[1]  
QSTATB[1]  
QSTATC[1]  
. . .  
REGISTER DESCRIPTION  
0x01E0 6810  
0x01E0 6814  
0x01E0 6818  
. . .  
Queue Manager Queue 1 Status Register A  
Queue Manager Queue 1 Status Register B  
Queue Manager Queue 1 Status Register C  
. . .  
0x01E0 6BF0  
0x01E0 6BF4  
0x01E0 6BF8  
QSTATA[63]  
QSTATB[63]  
QSTATC[63]  
Queue Manager Queue 63 Status Register A  
Queue Manager Queue 63 Status Register B  
Queue Manager Queue 63 Status Register C  
4.7.6.13.1 USB0 [USB2.0] Electrical Data/Timing  
The USB PHY PLL can support input clock of the following frequencies: 12.0 MHz, 13.0 MHz, 19.2 MHz,  
20.0 MHz, 24.0 MHz, 26.0 MHz, 38.4 MHz, 40.0 MHz or 48.0 MHz. USB_REFCLKIN jitter tolerance is 50  
ppm (maximum).  
Table 4-91. Switching Characteristics Over Recommended Operating Conditions for USB0 [USB2.0] (see  
Figure 4-47)  
1.3V, 1.2V, 1.1V, 1.0V  
LOW SPEED  
1.5 Mbps  
FULL SPEED  
12 Mbps  
HIGH SPEED  
480 Mbps  
NO.  
PARAMETER  
UNIT  
MIN  
75  
MAX  
MIN  
4
MAX  
MIN  
0.5  
0.5  
–
MAX  
1
2
3
4
5
tr(D)  
Rise time, USB_DP and USB_DM signals(1)  
Fall time, USB_DP and USB_DM signals(1)  
Rise/Fall time, matching(2)  
Output signal cross-over voltage(1)  
Source (Host) Driver jitter, next transition  
Function Driver jitter, next transition  
Source (Host) Driver jitter, paired transition(4)  
Function Driver jitter, paired transition  
Pulse duration, EOP transmitter  
Pulse duration, EOP receiver  
300  
300  
120  
2
20  
20  
111  
2
ns  
ns  
%
tf(D)  
75  
4
trfM  
80  
90  
1.3  
–
–
VCRS  
1.3  
–
V
tjr(source)NT  
tjr(FUNC)NT  
tjr(source)PT  
tjr(FUNC)PT  
tw(EOPT)  
tw(EOPR)  
t(DRATE)  
2
2
(3)ns  
ns  
ns  
ns  
ns  
ns  
(3)  
(3)  
(3)  
25  
2
6
1
1
10  
1
7
8
9
1250  
670  
1500  
160  
82  
175  
–
–
–
Data Rate  
1.5  
–
12  
480 Mb/s  
10 ZDRV  
11 ZINP  
Driver Output Resistance  
–
40.5  
49.5  
40.5  
-
49.5  
-
Ω
Ω
Receiver Input Impedance  
100k  
100k  
(1) Low Speed: CL = 200 pF, Full Speed: CL = 50 pF, High Speed: CL = 50 pF  
(2) tRFM = (tr/tf) x 100. [Excluding the first transaction from the Idle state.]  
(3) For more detailed information, see the Universal Serial Bus Specification Revision 2.0, Chapter 7. Electrical.  
(4) tjr = tpx(1) - tpx(0)  
t
t
per − jr  
USB_DM  
90% V  
OH  
V
CRS  
10% V  
OL  
USB_DP  
t
f
t
r
Figure 4-47. USB2.0 Integrated Transceiver Interface Timing  
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Specifications  
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4.7.6.14 Universal Serial Bus Host Controller (USB1) [USB1.1 OHCI]  
All the USB interfaces for this device are compliant with Universal Serial Bus Specifications, Revision 1.1.  
Table 4-92 is the list of USB Host Controller registers.  
Table 4-92. USB Host Controller Registers  
USB1  
ACRONYM  
REGISTER DESCRIPTION  
OHCI Revision Number Register  
BYTE ADDRESS  
0x01E2 5000  
0x01E2 5004  
0x01E2 5008  
0x01E2 500C  
0x01E2 5010  
0x01E2 5014  
0x01E2 5018  
0x01E2 501C  
0x01E2 5020  
0x01E2 5024  
0x01E2 5028  
0x01E2 502C  
0x01E2 5030  
0x01E2 5034  
0x01E2 5038  
0x01E2 503C  
0x01E2 5040  
0x01E2 5044  
0x01E2 5048  
0x01E2 504C  
0x01E2 5050  
0x01E2 5054  
0x01E2 5058  
HCREVISION  
HCCONTROL  
HC Operating Mode Register  
HC Command and Status Register  
HC Interrupt and Status Register  
HC Interrupt Enable Register  
HC Interrupt Disable Register  
HC HCAA Address Register(1)  
HC Current Periodic Register(1)  
HC Head Control Register(1)  
HC Current Control Register(1)  
HC Head Bulk Register(1)  
HCCOMMANDSTATUS  
HCINTERRUPTSTATUS  
HCINTERRUPTENABLE  
HCINTERRUPTDISABLE  
HCHCCA  
HCPERIODCURRENTED  
HCCONTROLHEADED  
HCCONTROLCURRENTED  
HCBULKHEADED  
HCBULKCURRENTED  
HCDONEHEAD  
HC Current Bulk Register(1)  
HC Head Done Register(1)  
HCFMINTERVAL  
HC Frame Interval Register  
HC Frame Remaining Register  
HC Frame Number Register  
HC Periodic Start Register  
HCFMREMAINING  
HCFMNUMBER  
HCPERIODICSTART  
HCLSTHRESHOLD  
HCRHDESCRIPTORA  
HCRHDESCRIPTORB  
HCRHSTATUS  
HC Low-Speed Threshold Register  
HC Root Hub A Register  
HC Root Hub B Register  
HC Root Hub Status Register  
HC Port 1 Status and Control Register(2)  
HC Port 2 Status and Control Register(3)  
HCRHPORTSTATUS1  
HCRHPORTSTATUS2  
(1) Restrictions apply to the physical addresses used in these registers.  
(2) Connected to the integrated USB1.1 phy pins (USB1_DM, USB1_DP).  
(3) Although the controller implements two ports, the second port cannot be used.  
Table 4-93. Switching Characteristics Over Recommended Operating Conditions for USB1 [USB1.1]  
1.3V, 1.2V, 1.1V, 1.0V  
NO.  
PARAMETER  
LOW SPEED  
FULL SPEED  
UNIT  
MIN  
MAX  
300(1)  
300(1)  
120(2)  
2(1)  
MAX  
MAX  
20(1)  
20(1)  
110(2)  
2(1)  
U1 tr  
Rise time, USB.DP and USB.DM signals(1)  
Fall time, USB.DP and USB.DM signals(1)  
Rise/Fall time matching(2)  
Output signal cross-over voltage(1)  
Differential propagation jitter(3)  
Operating frequency(4)  
75(1)  
75(1)  
80(2)  
1.3(1)  
-25(3)  
4(1)  
4(1)  
90(2)  
1.3(1)  
-2(3)  
ns  
ns  
U2 tf  
U3 tRFM  
U4 VCRS  
U5 tj  
%
V
25(3)  
2(3)  
ns  
U6 fop  
1.5  
12  
MHz  
(1) Low Speed: CL = 200 pF. High Speed: CL = 50pF  
(2) tRFM =( tr/tf ) x 100  
(3) t jr = t px(1) - tpx(0)  
(4) fop = 1/tper  
168  
Specifications  
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4.7.6.15 Ethernet Media Access Controller (EMAC)  
The Ethernet Media Access Controller (EMAC) provides an efficient interface between device and the  
network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps  
in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support.  
The EMAC controls the flow of packet data from the device to the PHY. The MDIO module controls PHY  
configuration and status monitoring.  
Both the EMAC and the MDIO modules interface to the device through a custom interface that allows  
efficient data transmission and reception. This custom interface is referred to as the EMAC control  
module, and is considered integral to the EMAC/MDIO peripheral. The control module is also used to  
multiplex and control interrupts.  
4.7.6.15.1 EMAC Peripheral Register Description(s)  
Table 4-94. Ethernet Media Access Controller (EMAC) Registers  
BYTE ADDRESS  
0x01E2 3000  
0x01E2 3004  
0x01E2 3008  
0x01E2 3010  
0x01E2 3014  
0x01E2 3018  
0x01E2 3080  
0x01E2 3084  
0x01E2 3088  
0x01E2 308C  
0x01E2 3090  
0x01E2 3094  
0x01E2 30A0  
0x01E2 30A4  
0x01E2 30A8  
0x01E2 30AC  
0x01E2 30B0  
0x01E2 30B4  
0x01E2 30B8  
0x01E2 30BC  
0x01E2 3100  
0x01E2 3104  
0x01E2 3108  
0x01E2 310C  
0x01E2 3110  
0x01E2 3114  
0x01E2 3120  
0x01E2 3124  
0x01E2 3128  
0x01E2 312C  
0x01E2 3130  
0x01E2 3134  
0x01E2 3138  
0x01E2 313C  
ACRONYM  
TXREV  
REGISTER DESCRIPTION  
Transmit Revision Register  
Transmit Control Register  
TXCONTROL  
TXTEARDOWN  
RXREV  
Transmit Teardown Register  
Receive Revision Register  
RXCONTROL  
Receive Control Register  
RXTEARDOWN  
TXINTSTATRAW  
TXINTSTATMASKED  
TXINTMASKSET  
TXINTMASKCLEAR  
MACINVECTOR  
MACEOIVECTOR  
RXINTSTATRAW  
RXINTSTATMASKED  
RXINTMASKSET  
RXINTMASKCLEAR  
MACINTSTATRAW  
Receive Teardown Register  
Transmit Interrupt Status (Unmasked) Register  
Transmit Interrupt Status (Masked) Register  
Transmit Interrupt Mask Set Register  
Transmit Interrupt Clear Register  
MAC Input Vector Register  
MAC End Of Interrupt Vector Register  
Receive Interrupt Status (Unmasked) Register  
Receive Interrupt Status (Masked) Register  
Receive Interrupt Mask Set Register  
Receive Interrupt Mask Clear Register  
MAC Interrupt Status (Unmasked) Register  
MACINTSTATMASKED MAC Interrupt Status (Masked) Register  
MACINTMASKSET MAC Interrupt Mask Set Register  
MACINTMASKCLEAR MAC Interrupt Mask Clear Register  
RXMBPENABLE  
RXUNICASTSET  
RXUNICASTCLEAR  
RXMAXLEN  
Receive Multicast/Broadcast/Promiscuous Channel Enable Register  
Receive Unicast Enable Set Register  
Receive Unicast Clear Register  
Receive Maximum Length Register  
Receive Buffer Offset Register  
RXBUFFEROFFSET  
RXFILTERLOWTHRESH Receive Filter Low Priority Frame Threshold Register  
RX0FLOWTHRESH  
RX1FLOWTHRESH  
RX2FLOWTHRESH  
RX3FLOWTHRESH  
RX4FLOWTHRESH  
RX5FLOWTHRESH  
RX6FLOWTHRESH  
RX7FLOWTHRESH  
Receive Channel 0 Flow Control Threshold Register  
Receive Channel 1 Flow Control Threshold Register  
Receive Channel 2 Flow Control Threshold Register  
Receive Channel 3 Flow Control Threshold Register  
Receive Channel 4 Flow Control Threshold Register  
Receive Channel 5 Flow Control Threshold Register  
Receive Channel 6 Flow Control Threshold Register  
Receive Channel 7 Flow Control Threshold Register  
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Table 4-94. Ethernet Media Access Controller (EMAC) Registers (continued)  
BYTE ADDRESS  
0x01E2 3140  
0x01E2 3144  
0x01E2 3148  
0x01E2 314C  
0x01E2 3150  
0x01E2 3154  
0x01E2 3158  
0x01E2 315C  
0x01E2 3160  
0x01E2 3164  
0x01E2 3168  
0x01E2 316C  
0x01E2 3170  
0x01E2 3174  
0x01E2 31D0  
0x01E2 31D4  
0x01E2 31D8  
0x01E2 31DC  
0x01E2 31E0  
0x01E2 31E4  
0x01E2 31E8  
0x01E2 31EC  
0x01E2 3200 - 0x01E2 32FC  
0x01E2 3500  
0x01E2 3504  
0x01E2 3508  
0x01E2 3600  
0x01E2 3604  
0x01E2 3608  
0x01E2 360C  
0x01E2 3610  
0x01E2 3614  
0x01E2 3618  
0x01E2 361C  
0x01E2 3620  
0x01E2 3624  
0x01E2 3628  
0x01E2 362C  
0x01E2 3630  
0x01E2 3634  
0x01E2 3638  
0x01E2 363C  
0x01E2 3640  
0x01E2 3644  
0x01E2 3648  
0x01E2 364C  
0x01E2 3650  
ACRONYM  
RX0FREEBUFFER  
RX1FREEBUFFER  
RX2FREEBUFFER  
RX3FREEBUFFER  
RX4FREEBUFFER  
RX5FREEBUFFER  
RX6FREEBUFFER  
RX7FREEBUFFER  
MACCONTROL  
MACSTATUS  
EMCONTROL  
FIFOCONTROL  
MACCONFIG  
SOFTRESET  
MACSRCADDRLO  
MACSRCADDRHI  
MACHASH1  
MACHASH2  
BOFFTEST  
TPACETEST  
RXPAUSE  
REGISTER DESCRIPTION  
Receive Channel 0 Free Buffer Count Register  
Receive Channel 1 Free Buffer Count Register  
Receive Channel 2 Free Buffer Count Register  
Receive Channel 3 Free Buffer Count Register  
Receive Channel 4 Free Buffer Count Register  
Receive Channel 5 Free Buffer Count Register  
Receive Channel 6 Free Buffer Count Register  
Receive Channel 7 Free Buffer Count Register  
MAC Control Register  
MAC Status Register  
Emulation Control Register  
FIFO Control Register  
MAC Configuration Register  
Soft Reset Register  
MAC Source Address Low Bytes Register  
MAC Source Address High Bytes Register  
MAC Hash Address Register 1  
MAC Hash Address Register 2  
Back Off Test Register  
Transmit Pacing Algorithm Test Register  
Receive Pause Timer Register  
TXPAUSE  
Transmit Pause Timer Register  
(see Table 4-95)  
MACADDRLO  
MACADDRHI  
MACINDEX  
TX0HDP  
EMAC Statistics Registers  
MAC Address Low Bytes Register, Used in Receive Address Matching  
MAC Address High Bytes Register, Used in Receive Address Matching  
MAC Index Register  
Transmit Channel 0 DMA Head Descriptor Pointer Register  
Transmit Channel 1 DMA Head Descriptor Pointer Register  
Transmit Channel 2 DMA Head Descriptor Pointer Register  
Transmit Channel 3 DMA Head Descriptor Pointer Register  
Transmit Channel 4 DMA Head Descriptor Pointer Register  
Transmit Channel 5 DMA Head Descriptor Pointer Register  
Transmit Channel 6 DMA Head Descriptor Pointer Register  
Transmit Channel 7 DMA Head Descriptor Pointer Register  
Receive Channel 0 DMA Head Descriptor Pointer Register  
Receive Channel 1 DMA Head Descriptor Pointer Register  
Receive Channel 2 DMA Head Descriptor Pointer Register  
Receive Channel 3 DMA Head Descriptor Pointer Register  
Receive Channel 4 DMA Head Descriptor Pointer Register  
Receive Channel 5 DMA Head Descriptor Pointer Register  
Receive Channel 6 DMA Head Descriptor Pointer Register  
Receive Channel 7 DMA Head Descriptor Pointer Register  
Transmit Channel 0 Completion Pointer Register  
TX1HDP  
TX2HDP  
TX3HDP  
TX4HDP  
TX5HDP  
TX6HDP  
TX7HDP  
RX0HDP  
RX1HDP  
RX2HDP  
RX3HDP  
RX4HDP  
RX5HDP  
RX6HDP  
RX7HDP  
TX0CP  
TX1CP  
Transmit Channel 1 Completion Pointer Register  
TX2CP  
Transmit Channel 2 Completion Pointer Register  
TX3CP  
Transmit Channel 3 Completion Pointer Register  
TX4CP  
Transmit Channel 4 Completion Pointer Register  
170  
Specifications  
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Table 4-94. Ethernet Media Access Controller (EMAC) Registers (continued)  
BYTE ADDRESS  
ACRONYM  
TX5CP  
TX6CP  
TX7CP  
RX0CP  
RX1CP  
RX2CP  
RX3CP  
RX4CP  
RX5CP  
RX6CP  
RX7CP  
REGISTER DESCRIPTION  
Transmit Channel 5 Completion Pointer Register  
Transmit Channel 6 Completion Pointer Register  
Transmit Channel 7 Completion Pointer Register  
Receive Channel 0 Completion Pointer Register  
Receive Channel 1 Completion Pointer Register  
Receive Channel 2 Completion Pointer Register  
Receive Channel 3 Completion Pointer Register  
Receive Channel 4 Completion Pointer Register  
Receive Channel 5 Completion Pointer Register  
Receive Channel 6 Completion Pointer Register  
Receive Channel 7 Completion Pointer Register  
0x01E2 3654  
0x01E2 3658  
0x01E2 365C  
0x01E2 3660  
0x01E2 3664  
0x01E2 3668  
0x01E2 366C  
0x01E2 3670  
0x01E2 3674  
0x01E2 3678  
0x01E2 367C  
Table 4-95. EMAC Statistics Registers  
BYTE ADDRESS  
ACRONYM  
REGISTER DESCRIPTION  
Good Receive Frames Register  
0x01E2 3200  
RXGOODFRAMES  
Broadcast Receive Frames Register  
(Total number of good broadcast frames received)  
0x01E2 3204  
RXBCASTFRAMES  
Multicast Receive Frames Register  
(Total number of good multicast frames received)  
0x01E2 3208  
0x01E2 320C  
0x01E2 3210  
RXMCASTFRAMES  
RXPAUSEFRAMES  
RXCRCERRORS  
Pause Receive Frames Register  
Receive CRC Errors Register  
(Total number of frames received with CRC errors)  
Receive Alignment/Code Errors Register  
(Total number of frames received with alignment/code errors)  
0x01E2 3214  
0x01E2 3218  
0x01E2 321C  
0x01E2 3220  
RXALIGNCODEERRORS  
RXOVERSIZED  
Receive Oversized Frames Register  
(Total number of oversized frames received)  
Receive Jabber Frames Register  
(Total number of jabber frames received)  
RXJABBER  
Receive Undersized Frames Register  
(Total number of undersized frames received)  
RXUNDERSIZED  
0x01E2 3224  
0x01E2 3228  
0x01E2 322C  
RXFRAGMENTS  
RXFILTERED  
Receive Frame Fragments Register  
Filtered Receive Frames Register  
Received QOS Filtered Frames Register  
RXQOSFILTERED  
Receive Octet Frames Register  
(Total number of received bytes in good frames)  
0x01E2 3230  
0x01E2 3234  
RXOCTETS  
Good Transmit Frames Register  
(Total number of good frames transmitted)  
TXGOODFRAMES  
0x01E2 3238  
0x01E2 323C  
0x01E2 3240  
0x01E2 3244  
0x01E2 3248  
0x01E2 324C  
0x01E2 3250  
0x01E2 3254  
0x01E2 3258  
0x01E2 325C  
0x01E2 3260  
0x01E2 3264  
0x01E2 3268  
TXBCASTFRAMES  
TXMCASTFRAMES  
TXPAUSEFRAMES  
TXDEFERRED  
TXCOLLISION  
Broadcast Transmit Frames Register  
Multicast Transmit Frames Register  
Pause Transmit Frames Register  
Deferred Transmit Frames Register  
Transmit Collision Frames Register  
Transmit Single Collision Frames Register  
Transmit Multiple Collision Frames Register  
Transmit Excessive Collision Frames Register  
Transmit Late Collision Frames Register  
Transmit Underrun Error Register  
TXSINGLECOLL  
TXMULTICOLL  
TXEXCESSIVECOLL  
TXLATECOLL  
TXUNDERRUN  
TXCARRIERSENSE  
TXOCTETS  
Transmit Carrier Sense Errors Register  
Transmit Octet Frames Register  
FRAME64  
Transmit and Receive 64 Octet Frames Register  
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Table 4-95. EMAC Statistics Registers (continued)  
BYTE ADDRESS  
0x01E2 326C  
0x01E2 3270  
0x01E2 3274  
0x01E2 3278  
0x01E2 327C  
0x01E2 3280  
0x01E2 3284  
0x01E2 3288  
0x01E2 328C  
ACRONYM  
FRAME65T127  
REGISTER DESCRIPTION  
Transmit and Receive 65 to 127 Octet Frames Register  
Transmit and Receive 128 to 255 Octet Frames Register  
Transmit and Receive 256 to 511 Octet Frames Register  
Transmit and Receive 512 to 1023 Octet Frames Register  
FRAME128T255  
FRAME256T511  
FRAME512T1023  
FRAME1024TUP  
NETOCTETS  
Transmit and Receive 1024 to 1518 Octet Frames Register  
Network Octet Frames Register  
RXSOFOVERRUNS  
RXMOFOVERRUNS  
RXDMAOVERRUNS  
Receive FIFO or DMA Start of Frame Overruns Register  
Receive FIFO or DMA Middle of Frame Overruns Register  
Receive DMA Start of Frame and Middle of Frame Overruns Register  
Table 4-96. EMAC Control Module Registers  
BYTE ADDRESS  
0x01E2 2000  
0x01E2 2004  
0x01E2 200C  
0x01E2 2010  
0x01E2 2014  
0x01E2 2018  
0x01E2 201C  
0x01E2 2020  
0x01E2 2024  
0x01E2 2028  
0x01E2 202C  
0x01E2 2030  
0x01E2 2034  
0x01E2 2038  
0x01E2 203C  
0x01E2 2040  
0x01E2 2044  
0x01E2 2048  
0x01E2 204C  
0x01E2 2050  
0x01E2 2054  
0x01E2 2058  
0x01E2 205C  
0x01E2 2060  
0x01E2 2064  
0x01E2 2068  
0x01E2 206C  
0x01E2 2070  
0x01E2 2074  
0x01E2 2078  
0x01E2 207C  
0x01E2 2080  
0x01E2 2084  
ACRONYM  
REGISTER DESCRIPTION  
REV  
EMAC Control Module Revision Register  
SOFTRESET  
INTCONTROL  
C0RXTHRESHEN  
C0RXEN  
EMAC Control Module Software Reset Register  
EMAC Control Module Interrupt Control Register  
EMAC Control Module Interrupt Core 0 Receive Threshold Interrupt Enable Register  
EMAC Control Module Interrupt Core 0 Receive Interrupt Enable Register  
EMAC Control Module Interrupt Core 0 Transmit Interrupt Enable Register  
EMAC Control Module Interrupt Core 0 Miscellaneous Interrupt Enable Register  
EMAC Control Module Interrupt Core 1 Receive Threshold Interrupt Enable Register  
EMAC Control Module Interrupt Core 1 Receive Interrupt Enable Register  
EMAC Control Module Interrupt Core 1 Transmit Interrupt Enable Register  
EMAC Control Module Interrupt Core 1 Miscellaneous Interrupt Enable Register  
EMAC Control Module Interrupt Core 2 Receive Threshold Interrupt Enable Register  
EMAC Control Module Interrupt Core 2 Receive Interrupt Enable Register  
EMAC Control Module Interrupt Core 2 Transmit Interrupt Enable Register  
EMAC Control Module Interrupt Core 2 Miscellaneous Interrupt Enable Register  
C0TXEN  
C0MISCEN  
C1RXTHRESHEN  
C1RXEN  
C1TXEN  
C1MISCEN  
C2RXTHRESHEN  
C2RXEN  
C2TXEN  
C2MISCEN  
C0RXTHRESHSTAT EMAC Control Module Interrupt Core 0 Receive Threshold Interrupt Status Register  
C0RXSTAT  
C0TXSTAT  
EMAC Control Module Interrupt Core 0 Receive Interrupt Status Register  
EMAC Control Module Interrupt Core 0 Transmit Interrupt Status Register  
EMAC Control Module Interrupt Core 0 Miscellaneous Interrupt Status Register  
C0MISCSTAT  
C1RXTHRESHSTAT EMAC Control Module Interrupt Core 1 Receive Threshold Interrupt Status Register  
C1RXSTAT  
C1TXSTAT  
EMAC Control Module Interrupt Core 1 Receive Interrupt Status Register  
EMAC Control Module Interrupt Core 1 Transmit Interrupt Status Register  
EMAC Control Module Interrupt Core 1 Miscellaneous Interrupt Status Register  
C1MISCSTAT  
C2RXTHRESHSTAT EMAC Control Module Interrupt Core 2 Receive Threshold Interrupt Status Register  
C2RXSTAT  
C2TXSTAT  
C2MISCSTAT  
C0RXIMAX  
C0TXIMAX  
C1RXIMAX  
C1TXIMAX  
C2RXIMAX  
C2TXIMAX  
EMAC Control Module Interrupt Core 2 Receive Interrupt Status Register  
EMAC Control Module Interrupt Core 2 Transmit Interrupt Status Register  
EMAC Control Module Interrupt Core 2 Miscellaneous Interrupt Status Register  
EMAC Control Module Interrupt Core 0 Receive Interrupts Per Millisecond Register  
EMAC Control Module Interrupt Core 0 Transmit Interrupts Per Millisecond Register  
EMAC Control Module Interrupt Core 1 Receive Interrupts Per Millisecond Register  
EMAC Control Module Interrupt Core 1 Transmit Interrupts Per Millisecond Register  
EMAC Control Module Interrupt Core 2 Receive Interrupts Per Millisecond Register  
EMAC Control Module Interrupt Core 2 Transmit Interrupts Per Millisecond Register  
172  
Specifications  
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Table 4-97. EMAC Control Module RAM  
BYTE ADDRESS  
0x01E2 0000 - 0x01E2 1FFF  
DESCRIPTION  
EMAC Local Buffer Descriptor Memory  
4.7.6.15.1.1 EMAC Electrical Data/Timing  
Table 4-98. Timing Requirements for MII_RXCLK (see Figure 4-48)  
1.3V, 1.2V, 1.1V  
10 Mbps 100 Mbps  
MIN MAX MIN MAX  
1.0V  
NO.  
10 Mbps  
MIN MAX  
UNIT  
1
2
3
tc(MII_RXCLK)  
tw(MII_RXCLKH)  
tw(MII_RXCLKL)  
Cycle time, MII_RXCLK  
400  
140  
140  
40  
14  
14  
400  
140  
140  
ns  
ns  
ns  
Pulse duration, MII_RXCLK high  
Pulse duration, MII_RXCLK low  
1
2
3
MII_RXCLK  
Figure 4-48. MII_RXCLK Timing (EMAC - Receive)  
Table 4-99. Timing Requirements for MII_TXCLK (see Figure 4-49)  
1.3V, 1.2V, 1.1V  
1.0V  
10 Mbps  
MIN MAX  
NO.  
10 Mbps  
MIN MAX  
100 Mbps  
UNIT  
MIN  
40  
MAX  
1
2
3
tc(MII_TXCLK)  
tw(MII_TXCLKH)  
tw(MII_TXCLKL)  
Cycle time, MII_TXCLK  
400  
140  
140  
400  
140  
140  
ns  
ns  
ns  
Pulse duration, MII_TXCLK high  
Pulse duration, MII_TXCLK low  
14  
14  
1
2
3
MII_TXCLK  
Figure 4-49. MII_TXCLK Timing (EMAC - Transmit)  
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Table 4-100. Timing Requirements for EMAC MII Receive 10/100 Mbit/s(1) (see Figure 4-50)  
1.3V, 1.2V, 1.1V,  
1.0V  
NO.  
UNIT  
MIN  
8
MAX  
1
2
tsu(MRXD-MII_RXCLKH)  
th(MII_RXCLKH-MRXD)  
Setup time, receive selected signals valid before MII_RXCLK high  
Hold time, receive selected signals valid after MII_RXCLK high  
ns  
ns  
8
(1) Receive selected signals include: MII_RXD[3]-MII_RXD[0], MII_RXDV, and MII_RXER.  
1
2
MII_RXCLK (Input)  
MII_RXD[3]-MII_RXD[0],  
MII_RXDV, MII_RXER (Inputs)  
Figure 4-50. EMAC Receive Interface Timing  
Table 4-101. Switching Characteristics Over Recommended Operating Conditions for EMAC MII Transmit  
10/100 Mbit/s(1) (see Figure 4-51)  
1.3V, 1.2V,  
1.0V  
1.1V  
NO.  
PARAMETER  
UNIT  
MIN  
MAX  
MIN  
MAX  
td(MII_TXCLKH-  
MTXD)  
1
Delay time, MII_TXCLK high to transmit selected signals valid  
2
25  
2
32  
ns  
(1) Transmit selected signals include: MTXD3-MTXD0, and MII_TXEN.  
1
MII_TCLK (Input)  
MII_TXD[3]-MII_TXD[0],  
MII_TXEN (Outputs)  
Figure 4-51. EMAC Transmit Interface Timing  
174  
Specifications  
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Table 4-102. Timing Requirements for EMAC RMII  
1.3V, 1.2V, 1.1V(1)  
UNIT  
NO.  
MIN  
TYP MAX  
1
2
tc(REFCLK)  
Cycle Time, RMII_MHZ_50_CLK  
20  
13  
13  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tw(REFCLKH)  
Pulse Width, RMII_MHZ_50_CLK High  
7
7
4
2
4
2
4
2
3
tw(REFCLKL)  
Pulse Width, RMII_MHZ_50_CLK Low  
6
tsu(RXD-REFCLK)  
th(REFCLK-RXD)  
tsu(CRSDV-REFCLK)  
th(REFCLK-CRSDV)  
tsu(RXER-REFCLK)  
th(REFCLKR-RXER)  
Input Setup Time, RXD Valid before RMII_MHZ_50_CLK High  
Input Hold Time, RXD Valid after RMII_MHZ_50_CLK High  
Input Setup Time, CRSDV Valid before RMII_MHZ_50_CLK High  
Input Hold Time, CRSDV Valid after RMII_MHZ_50_CLK High  
Input Setup Time, RXER Valid before RMII_MHZ_50_CLK High  
Input Hold Time, RXER Valid after RMII_MHZ_50_CLK High  
7
8
9
10  
11  
(1) RMII is not supported at operating points below 1.1V nominal  
Note: Per the RMII industry specification, the RMII reference clock (RMII_MHZ_50_CLK) must have jitter  
tolerance of 50 ppm or less.  
Table 4-103. Switching Characteristics Over Recommended Operating Conditions for EMAC RMII  
1.3V, 1.2V, 1.1V(1)  
NO.  
PARAMETER  
UNIT  
MIN  
2.5  
TYP MAX  
4
5
td(REFCLK-TXD)  
td(REFCLK-TXEN)  
Output Delay Time, RMII_MHZ_50_CLK High to TXD Valid  
Output Delay Time, RMII_MHZ_50_CLK High to TXEN Valid  
13  
13  
ns  
ns  
2.5  
(1) RMII is not supported at operating points below 1.1V nominal.  
1
2
3
RMII_MHz_50_CLK  
5
5
RMII_TXEN  
4
RMII_TXD[1:0]  
6
7
RMII_RXD[1:0]  
RMII_CRS_DV  
8
9
10  
11  
RMII_RXER  
Figure 4-52. RMII Timing Diagram  
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4.7.6.16 Management Data Input/Output (MDIO)  
The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to  
enumerate all PHY devices in the system.  
The Management Data Input/Output (MDIO) module implements the 802.3 serial management interface to  
interrogate and control Ethernet PHY(s) using a shared two-wire bus. Host software uses the MDIO  
module to configure the auto-negotiation parameters of each PHY attached to the EMAC, retrieve the  
negotiation results, and configure required parameters in the EMAC module for correct operation. The  
module is designed to allow almost transparent operation of the MDIO interface, with very little  
maintenance from the core processor. Only one PHY may be connected at any given time.  
4.7.6.16.1 MDIO Register Description(s)  
Table 4-104. MDIO Register Memory Map  
BYTE ADDRESS  
0x01E2 4000  
ACRONYM  
REV  
REGISTER NAME  
Revision Identification Register  
0x01E2 4004  
CONTROL  
ALIVE  
MDIO Control Register  
0x01E2 4008  
MDIO PHY Alive Status Register  
0x01E2 400C  
LINK  
MDIO PHY Link Status Register  
0x01E2 4010  
LINKINTRAW  
LINKINTMASKED  
–
MDIO Link Status Change Interrupt (Unmasked) Register  
MDIO Link Status Change Interrupt (Masked) Register  
Reserved  
0x01E2 4014  
0x01E2 4018  
0x01E2 4020  
USERINTRAW  
USERINTMASKED  
USERINTMASKSET  
MDIO User Command Complete Interrupt (Unmasked) Register  
MDIO User Command Complete Interrupt (Masked) Register  
MDIO User Command Complete Interrupt Mask Set Register  
0x01E2 4024  
0x01E2 4028  
0x01E2 402C  
USERINTMASKCLEAR MDIO User Command Complete Interrupt Mask Clear Register  
0x01E2 4030 - 0x01E2 407C  
0x01E2 4080  
–
Reserved  
USERACCESS0  
USERPHYSEL0  
USERACCESS1  
USERPHYSEL1  
–
MDIO User Access Register 0  
MDIO User PHY Select Register 0  
MDIO User Access Register 1  
MDIO User PHY Select Register 1  
Reserved  
0x01E2 4084  
0x01E2 4088  
0x01E2 408C  
0x01E2 4090 - 0x01E2 47FF  
176  
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4.7.6.16.2 Management Data Input/Output (MDIO) Electrical Data/Timing  
Table 4-105. Timing Requirements for MDIO Input (see Figure 4-53 and Figure 4-54)  
1.3V, 1.2V, 1.1V  
1.0V  
NO.  
UNIT  
MIN  
400  
180  
MAX  
MIN  
400  
180  
MAX  
1
2
3
4
5
tc(MDCLK)  
Cycle time, MDCLK  
ns  
ns  
ns  
ns  
ns  
tw(MDCLK)  
Pulse duration, MDCLK high/low  
tt(MDCLK)  
Transition time, MDCLK  
5
5
tsu(MDIO-MDCLKH)  
th(MDCLKH-MDIO)  
Setup time, MDIO data input valid before MDCLK high  
Hold time, MDIO data input valid after MDCLK high  
16  
0
21  
0
1
3
3
MDCLK  
4
5
MDIO  
(input)  
Figure 4-53. MDIO Input Timing  
Table 4-106. Switching Characteristics Over Recommended Operating Conditions for MDIO Output  
(see Figure 4-54)  
1.3V, 1.2V, 1.1V,  
1.0V  
NO.  
PARAMETER  
UNIT  
MIN  
MAX  
7
td(MDCLKL-MDIO)  
Delay time, MDCLK low to MDIO data output valid  
0
100  
ns  
1
MDCLK  
7
MDIO  
(output)  
Figure 4-54. MDIO Output Timing  
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4.7.6.17 LCD Controller (LCDC)  
The LCD controller consists of two independent controllers, the Raster Controller and the LCD Interface  
Display Driver (LIDD) controller. Each controller operates independently from the other and only one of  
them is active at any given time.  
•
The Raster Controller handles the synchronous LCD interface. It provides timing and data for constant  
graphics refresh to a passive display. It supports a wide variety of monochrome and full-color display  
types and sizes by use of programmable timing controls, a built-in palette, and a gray-scale/serializer.  
Graphics data is processed and stored in frame buffers. A frame buffer is a contiguous memory block  
in the system. A built-in DMA engine supplies the graphics data to the Raster engine which, in turn,  
outputs to the external LCD device.  
•
The LIDD Controller supports the asynchronous LCD interface. It provides full-timing programmability  
of control signals (CS, WE, OE, ALE) and output data.  
The maximum resolution for the LCD controller is 1024 x 1024 pixels. The maximum frame rate is  
determined by the image size in combination with the pixel clock rate. For details, see SPRAB93.  
Table 4-107 lists the LCD Controller registers.  
Table 4-107. LCD Controller Registers  
BYTE ADDRESS  
0x01E1 3000  
0x01E1 3004  
0x01E1 3008  
0x01E1 300C  
0x01E1 3010  
0x01E1 3014  
0x01E1 3018  
0x01E1 301C  
0x01E1 3020  
0x01E1 3024  
0x01E1 3028  
0x01E1 302C  
0x01E1 3030  
0x01E1 3034  
0x01E1 3038  
0x01E1 3040  
0x01E1 3044  
0x01E1 3048  
0x01E1 304C  
0x01E1 3050  
ACRONYM  
REVID  
REGISTER DESCRIPTION  
LCD Revision Identification Register  
LCD_CTRL  
LCD Control Register  
LCD_STAT  
LCD Status Register  
LIDD_CTRL  
LCD LIDD Control Register  
LIDD_CS0_CONF  
LIDD_CS0_ADDR  
LIDD_CS0_DATA  
LIDD_CS1_CONF  
LIDD_CS1_ADDR  
LIDD_CS1_DATA  
RASTER_CTRL  
LCD LIDD CS0 Configuration Register  
LCD LIDD CS0 Address Read/Write Register  
LCD LIDD CS0 Data Read/Write Register  
LCD LIDD CS1 Configuration Register  
LCD LIDD CS1 Address Read/Write Register  
LCD LIDD CS1 Data Read/Write Register  
LCD Raster Control Register  
RASTER_TIMING_0  
RASTER_TIMING_1  
RASTER_TIMING_2  
RASTER_SUBPANEL  
LCDDMA_CTRL  
LCDDMA_FB0_BASE  
LCDDMA_FB0_CEILING  
LCDDMA_FB1_BASE  
LCDDMA_FB1_CEILING  
LCD Raster Timing 0 Register  
LCD Raster Timing 1 Register  
LCD Raster Timing 2 Register  
LCD Raster Subpanel Display Register  
LCD DMA Control Register  
LCD DMA Frame Buffer 0 Base Address Register  
LCD DMA Frame Buffer 0 Ceiling Address Register  
LCD DMA Frame Buffer 1 Base Address Register  
LCD DMA Frame Buffer 1 Ceiling Address Register  
178  
Specifications  
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4.7.6.17.1 LCD Interface Display Driver (LIDD Mode)  
Table 4-108. Timing Requirements for LCD LIDD Mode  
1.3V, 1.2V,  
1.1V  
1.0V  
NO.  
UNIT  
MIN MAX  
MIN  
8
MAX  
16 tsu(LCD_D)  
17 th(LCD_D)  
Setup time, LCD_D[15:0] valid before LCD_MCLK high  
Hold time, LCD_D[15:0] valid after LCD_MCLK high  
7
0
ns  
ns  
0
Table 4-109. Switching Characteristics Over Recommended Operating Conditions for LCD LIDD Mode  
1.3V, 1.2V,  
1.0V  
1.1V  
NO.  
PARAMETER  
UNIT  
MIN  
MAX  
7
MIN  
0
MAX  
9
4
5
6
7
8
9
td(LCD_D_V)  
td(LCD_D_I)  
td(LCD_E_A  
td(LCD_E_I)  
td(LCD_A_A)  
td(LCD_A_I)  
Delay time, LCD_MCLK high to LCD_D[15:0] valid (write)  
Delay time, LCD_MCLK high to LCD_D[15:0] invalid (write)  
Delay time, LCD_MCLK high to LCD_AC_ENB_CS low  
Delay time, LCD_MCLK high to LCD_AC_ENB_CS high  
Delay time, LCD_MCLK high to LCD_VSYNC low  
Delay time, LCD_MCLK high to LCD_VSYNC high  
Delay time, LCD_MCLK high to LCD_HSYNC low  
Delay time, LCD_MCLK high to LCD_HSYNC high  
0
0
0
0
0
0
0
0
0
0
0
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
7
0
9
)
7
0
9
7
0
9
7
0
9
7
0
9
10 td(LCD_W_A)  
11 td(LCD_W_I)  
7
0
9
7
0
9
12 td(LCD_STRB_A) Delay time, LCD_MCLK high to LCD_PCLK active  
13 td(LCD_STRB_I) Delay time, LCD_MCLK high to LCD_PCLK inactive  
7
0
9
7
0
9
14 td(LCD_D_Z)  
15 td(Z_LCD_D)  
Delay time, LCD_MCLK high to LCD_D[15:0] in 3-state  
7
0
9
Delay time, LCD_MCLK high to LCD_D[15:0] (valid from 3-state)  
7
0
9
CS_DELAY  
R_SU  
(0 to 31)  
1
R_HOLD  
(1 to 15)  
W_SU  
(0 to 31)  
2
W_STROBE  
CS_DELAY  
R_STROBE  
(1 to 63)  
W_HOLD  
(1 to 63)  
(1 to 15)  
3
LCD_MCLK  
4
5
14  
17  
16  
15  
LCD_D[15:0]  
LCD_PCLK  
Write Data  
Data[7:0]  
Read Status  
Not Used  
8
9
LCD_VSYNC  
LCD_HSYNC  
RS  
10  
11  
R/W  
12  
12  
13  
13  
E0  
E1  
LCD_AC_ENB_CS  
Figure 4-55. Character Display HD44780 Write  
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W_HOLD  
(1–15)  
R_SU  
(0–31)  
R_STROBE R_HOLD CS_DELAY  
(1–63) (1–5)  
W_SU  
(0–31)  
W_STROBE  
(1–63)  
CS_DELAY  
1
2
Not  
3
Used  
LCD_MCLK  
LCD_D[7:0]  
4
17  
15  
5
14  
16  
Data[7:0]  
Write Instruction  
Read  
Data  
LCD_PCLK  
Not  
Used  
8
9
RS  
LCD_VSYNC  
LCD_HSYNC  
10  
11  
R/W  
12  
13  
13  
12  
E0  
E1  
LCD_AC_ENB_CS  
Figure 4-56. Character Display HD44780 Read  
180  
Specifications  
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W_HOLD  
(1−15)  
W_HOLD  
(1−15)  
W_SU  
(0−31)  
W_STROBE  
(1−63)  
CS_DELAY  
W_SU  
(0−31)  
W_STROBE  
(1−63)  
CS_DELAY  
Clock  
1
2
3
LCD_MCLK  
4
6
5
7
5
4
LCD_D[15:0]  
Write Address  
Write Data  
Data[15:0]  
6
7
LCD_AC_ENB_CS  
(async mode)  
CS0  
CS1  
9
8
A0  
LCD_VSYNC  
10  
11  
10  
11  
R/W  
LCD_HSYNC  
LCD_PCLK  
12  
13  
12  
13  
E
Figure 4-57. Micro-Interface Graphic Display 6800 Write  
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W_HOLD  
(1−15)  
R_SU  
(0−31)  
W_SU  
(0−31)  
W_STROBE  
(1−63)  
CS_DELAY  
R_STROBE R_HOLD CS_DELAY  
(1−63  
1
2
(1−15)  
3
Clock  
LCD_MCLK  
LCD_D[15:0]  
4
14  
5
16  
15  
Data[15:0]  
17  
Write Address  
Read  
Data  
6
6
7
7
LCD_AC_ENB_CS  
(async mode)  
CS0  
CS1  
9
8
LCD_VSYNC  
LCD_HSYNC  
LCD_PCLK  
A0  
R/W  
E
11  
10  
13  
12  
13  
12  
Figure 4-58. Micro-Interface Graphic Display 6800 Read  
182  
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R_SU  
(0−31)  
R_SU  
(0−31)  
R_STROBE R_HOLD CS_DELAY  
(1−63) (1−15)  
R_HOLD CS_DELAY  
(1−15)  
R_STROBE  
(1−63)  
1
2
3
Clock  
LCD_MCLK  
17  
17  
14 16  
14  
15  
7
16  
15  
LCD_D[15:0]  
Data[15:0]  
Read  
Read  
Data  
Status  
6
7
6
LCD_AC_ENB_CS  
(async mode)  
CS0  
CS1  
8
9
LCD_VSYNC  
LCD_HSYNC  
A0  
R/W  
E
13  
12  
12  
13  
LCD_PCLK  
Figure 4-59. Micro-Interface Graphic Display 6800 Status  
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W_HOLD  
(1−15)  
W_HOLD  
(1−15)  
W_SU  
W_STROBE  
CS_DELAY  
W_SU  
(0−31)  
W_STROBE  
(1−63)  
CS_DELAY  
1
2
(0−31)  
3
(1−63)  
Clock  
LCD_MCLK  
4
5
4
5
LCD_D[15:0]  
Write Address  
Write Data  
7
6
6
7
LCD_AC_ENB_CS  
(async mode)  
CS0  
CS1  
8
9
LCD_VSYNC  
LCD_HSYNC  
LCD_PCLK  
A0  
WR  
RD  
11  
10  
10  
11  
Figure 4-60. Micro-Interface Graphic Display 8080 Write  
184  
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W_HOLD  
(1−15)  
R_SU  
(0−31)  
W_SU  
(0−31)  
W_STROBE  
(1−63)  
CS_DELAY  
R_STROBE  
(1−63)  
R_HOLD CS_DELAY  
(1−15)  
1
Clock  
2
3
LCD_MCLK  
4
5
16  
17  
15  
Data[15:0]  
14  
LCD_D[15:0]  
Write Address  
Read  
Data  
7
6
7
6
LCD_AC_ENB_CS  
(async mode)  
CS0  
CS1  
9
8
LCD_VSYNC  
LCD_HSYNC  
LCD_PCLK  
A0  
11  
10  
WR  
12  
13  
RD  
Figure 4-61. Micro-Interface Graphic Display 8080 Read  
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R_SU  
(0−31)  
R_SU  
(0−31)  
R_STROBE R_HOLD CS_DELAY  
R_STROBE R_HOLD  
CS_DELAY  
1
2
(1−15)  
(1−63)  
(1−63)  
(1−15)  
3
Clock  
LCD_MCLK  
17  
16  
17  
15  
Data[15:0]  
14  
6
16  
15  
14  
LCD_D[15:0]  
Read Data  
Read Status  
7
6
7
9
LCD_AC_ENB_CS  
CS0  
CS1  
8
A0  
WR  
RD  
LCD_VSYNC  
LCD_HSYNC  
12  
13  
13  
12  
LCD_PCLK  
Figure 4-62. Micro-Interface Graphic Display 8080 Status  
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4.7.6.17.2 LCD Raster Mode  
Table 4-110. Switching Characteristics Over Recommended Operating Conditions for LCD Raster Mode  
See Figure 4-63 through Figure 4-67  
1.3V, 1.2V, 1.1V  
1.0V  
NO.  
PARAMETER  
UNIT  
MIN  
26.66  
10  
MAX  
MIN  
33.33  
10  
MAX  
1
2
3
4
tc(PIXEL_CLK)  
tw(PIXEL_CLK_H)  
tw(PIXEL_CLK_L)  
td(LCD_D_V)  
Cycle time, pixel clock  
ns  
ns  
ns  
ns  
Pulse duration, pixel clock high  
Pulse duration, pixel clock low  
10  
10  
Delay time, LCD_PCLK high to LCD_D[15:0] valid (write)  
0
7
7
0
9
9
Delay time, LCD_PCLK high to LCD_D[15:0] invalid  
(write)  
5
td(LCD_D_IV)  
0
0
ns  
6
7
8
9
td(LCD_AC_ENB_CS_A)  
td(LCD_AC_ENB_CS_I)  
td(LCD_VSYNC_A)  
td(LCD_VSYNC_I)  
Delay time, LCD_PCLK low to LCD_AC_ENB_CS high  
Delay time, LCD_PCLK low to LCD_AC_ENB_CS low  
Delay time, LCD_PCLK low to LCD_VSYNC high  
Delay time, LCD_PCLK low to LCD_VSYNC low  
Delay time, LCD_PCLK high to LCD_HSYNC high  
Delay time, LCD_PCLK high to LCD_HSYNC low  
0
0
0
0
0
0
7
7
7
7
7
7
0
0
0
0
0
0
9
9
9
9
9
9
ns  
ns  
ns  
ns  
ns  
ns  
10 td(LCD_HSYNC_A)  
11 td(LCD_HSYNC_I)  
Frame-to-frame timing is derived through the following parameters in the LCD (RASTER_TIMING_1)  
register:  
•
•
•
•
Vertical front porch (VFP)  
Vertical sync pulse width (VSW)  
Vertical back porch (VBP)  
Lines per panel (LPP)  
Line-to-line timing is derived through the following parameters in the LCD (RASTER_TIMING_0) register:  
•
•
•
•
Horizontal front porch (HFP)  
Horizontal sync pulse width (HSW)  
Horizontal back porch (HBP)  
Pixels per panel (PPL)  
LCD_AC_ENB_CS timing is derived through the following parameter in the LCD (RASTER_TIMING_2)  
register:  
•
AC bias frequency (ACB)  
The display format produced in raster mode is shown in Figure 4-63. An entire frame is delivered one line  
at a time. The first line delivered starts at data pixel (1, 1) and ends at data pixel (P, 1). The last line  
delivered starts at data pixel (1, L) and ends at data pixel (P, L). The beginning of each new frame is  
denoted by the activation of I/O signal LCD_VSYNC. The beginning of each new line is denoted by the  
activation of I/O signal LCD_HSYNC.  
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Data Pixels (From 1 to P)  
P−2,  
1
P−1,  
1
1, 1  
1, 2  
1, 3  
2, 1  
2, 2  
3, 1  
P, 1  
P, 2  
P, 3  
P−1,  
2
LCD  
P,  
1,  
L−2  
L−2  
1,  
L−1  
2,  
L−1  
P,  
L−1  
P−1,  
L−1  
P−2,  
L
P−1,  
L
1, L  
2, L  
3, L  
P, L  
Figure 4-63. LCD Raster-Mode Display Format  
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Frame Time ~ 70 Hz  
Active TFT  
VSW  
VBP  
LPP  
(1 to 1024)  
VFP  
VSW  
(1 to 64)  
(0 to 255)  
(1 to 64)  
(0 to 255)  
Line  
Time  
Hsync  
LCD_HSYNC  
LCD_VSYNC  
Vsync  
Data  
LCD_D[15:0]  
1, L-1  
P, L-1  
1, L  
P, L  
1, 2  
P, 2  
1, 1  
P, 1  
LCD_AC_ENB_CS  
10  
11  
Hsync  
LCD_HSYNC  
CLK  
LCD_PCLK  
Data  
LCD_D[15:0]  
2, 1  
1, 2  
P, 2  
P, 1  
1, 1  
2, 2  
Enable  
LCD_AC_ENB_CS  
PLL  
HFP  
(1 to 256)  
HSW  
HBP  
PLL  
(1 to 256)  
(1 to 64)  
16 × (1 to 1024)  
Line 1  
16 × (1 to 1024)  
Line 2  
Figure 4-64. LCD Raster-Mode Active  
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Figure 4-65. LCD Raster-Mode Passive  
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LCD_AC_ENB_CS  
LCD_VSYNC  
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6
8
11  
10  
LCD_HSYNC  
1
3
2
LCD_PCLK  
(passive mode)  
5
4
LCD_D[7:0]  
2, L  
2, 1  
1, L  
P, L  
1, 1  
P, 1  
(passive mode)  
1
3
2
LCD_PCLK  
(active mode)  
4
5
LCD_D[15:0]  
(active mode)  
1, L  
P, L  
2, L  
VBP = 0  
VFP = 0  
VSW = 1  
PPL  
HSW  
HBP  
PPL  
(1 to 1024)  
×
HFP  
(1 to 256  
(1 to 1024)  
(1 to 64)  
(1 to 256)  
×
16  
16  
Line L  
Line 1 (Passive Only)  
Figure 4-66. LCD Raster-Mode Control Signal Activation  
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7
LCD_AC_ENB_CS  
LCD_VSYNC  
9
11  
10  
LCD_HSYNC  
1
3
4
LCD_PCLK  
(passive mode)  
5
4
LCD_D[7:0]  
2, 1  
2, 2  
1, 1  
P, 1  
1, 2  
P, 2  
(passive mode)  
1
3
2
LCD_PCLK  
(active mode)  
4
5
LCD_D[15:0]  
(active mode)  
1, 1  
P, 1  
2, 1  
VBP = 0  
VFP = 0  
VSW = 1  
PPL  
HSW  
HBP  
PPL  
(1 to 1024)  
×
HFP  
(1 to 1024)  
(1 to 256  
(1 to 64)  
(1 to 256)  
×
16  
16  
Line 1 for passive  
Line 1 for active  
Line 2 for passive  
Figure 4-67. LCD Raster-Mode Control Signal Deactivation  
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4.7.6.18 Host-Port Interface (UHPI)  
4.7.6.18.1 HPI Device-Specific Information  
The device includes a user-configurable 16-bit Host-port interface (HPI16).  
The host port interface (UHPI) provides a parallel port interface through which an external host processor  
can directly access the processor's resources (configuration and program/data memories). The external  
host device is asynchronous to the CPU clock and functions as a master to the HPI interface. The UHPI  
enables a host device and the processor to exchange information via internal or external memory.  
Dedicated address (HPIA) and data (HPID) registers within the UHPI provide the data path between the  
external host interface and the processor resources. A UHPI control register (HPIC) is available to the  
host and the CPU for various configuration and interrupt functions.  
4.7.6.18.2 HPI Peripheral Register Description(s)  
Table 4-111. HPI Control Registers  
BYTE ADDRESS  
ACRONYM  
REGISTER DESCRIPTION  
COMMENTS  
0x01E1 0000  
PID  
Peripheral Identification Register  
The CPU has read/write access to  
the PWREMU_MGMT register.  
0x01E1 0004  
PWREMU_MGMT  
HPI power and emulation management register  
0x01E1 0008  
0x01E1 000C  
0x01E1 0010  
0x01E1 0014  
0x01E1 0018  
0x01E1 001C  
0x01E1 0020  
0x01E1 0024  
01E1 0028  
-
Reserved  
GPIO_EN  
GPIO_DIR1  
GPIO_DAT1  
GPIO_DIR2  
GPIO_DAT2  
GPIO_DIR3  
GPIO_DAT3  
-
General Purpose IO Enable Register  
General Purpose IO Direction Register 1  
General Purpose IO Data Register 1  
General Purpose IO Direction Register 2  
General Purpose IO Data Register 2  
General Purpose IO Direction Register 3  
General Purpose IO Data Register 3  
Reserved  
01E1 002C  
-
Reserved  
The Host and the CPU both have  
read/write access to the HPIC  
register.  
01E1 0030  
01E1 0034  
HPIC  
HPI control register  
HPIA  
The Host has read/write access to  
the HPIA registers. The CPU has  
only read access to the HPIA  
registers.  
HPI address register (Write)  
(HPIAW)(1)  
HPIA  
01E1 0038  
HPI address register (Read)  
Reserved  
(HPIAR)(1)  
01E1 000C - 01E1 07FF  
-
(1) There are two 32-bit HPIA registers: HPIAR for read operations and HPIAW for write operations. The HPI can be configured such that  
HPIAR and HPIAW act as a single 32-bit HPIA (single-HPIA mode) or as two separate 32-bit HPIAs (dual-HPIA mode) from the  
perspective of the Host. The CPU can access HPIAW and HPIAR independently.  
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4.7.6.18.3 HPI Electrical Data/Timing  
Table 4-112. Timing Requirements for Host-Port Interface [1.2V, 1.1V](1) (2)  
1.3V, 1.2V, 1.1V,  
1.0V  
NO.  
UNIT  
MIN  
5
MAX  
1
2
3
4
9
tsu(SELV-HSTBL)  
th(HSTBL-SELV)  
tw(HSTBL)  
Setup time, select signals(3) valid before UHPI_HSTROBE low  
Hold time, select signals(3) valid after UHPI_HSTROBE low  
Pulse duration, UHPI_HSTROBE active low  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
2
15  
2M  
5
tw(HSTBH)  
Pulse duration, UHPI_HSTROBE inactive high between consecutive accesses  
Setup time, selects signals valid before UHPI_HAS low  
Hold time, select signals valid after UHPI_HAS low  
tsu(SELV-HASL)  
10 th(HASL-SELV)  
11 tsu(HDV-HSTBH)  
12 th(HSTBH-HDV)  
2
Setup time, host data valid before UHPI_HSTROBE high  
Hold time, host data valid after UHPI_HSTROBE high  
5
2
Hold time, UHPI_HSTROBE high after UHPI_HRDY low. UHPI_HSTROBE  
should not be inactivated until UHPI_HRDY is active (low); otherwise, HPI writes  
will not complete properly.  
13 th(HRDYL-HSTBH)  
2
ns  
16 tsu(HASL-HSTBL)  
17 th(HSTBL-HASH)  
Setup time, UHPI_HAS low before UHPI_HSTROBE low  
Hold time, UHPI_HAS low after UHPI_HSTROBE low  
5
2
ns  
ns  
(1) UHPI_HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2: [NOT(UHPI_HDS1 XOR  
UHPI_HDS2)] OR UHPI_HCS.  
(2) M=SYSCLK2 period in ns.  
(3) Select signals include: HCNTL[1:0], HR/W and HHWIL.  
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Table 4-113. Switching Characteristics Over Recommended Operating Conditions for Host-Port Interface  
[1.3V, 1.2V, 1.1V](1) (2) (3)  
1.3V, 1.2V  
1.1V  
NO.  
PARAMETER  
UNIT  
MIN  
MAX  
MIN  
MAX  
For HPI Write, HRDY can go high (not  
ready) for these HPI Write conditions;  
otherwise, HRDY stays low (ready):  
Case 1: Back-to-back HPIA writes (can  
be either first or second half-word)  
Case 2: HPIA write following a  
PREFETCH command (can be either  
first or second half-word)  
Case 3: HPID write when FIFO is full or  
flushing (can be either first or second  
half-word)  
Case 4: HPIA write and Write FIFO not  
empty  
For HPI Read, HRDY can go high (not  
ready) for these HPI Read conditions:  
Case 1: HPID read (with auto-  
increment) and data not in Read FIFO  
(can only happen to first half-word of  
HPID access)  
Delay time, HSTROBE low to  
HRDY valid  
5
td(HSTBL-HRDYV)  
15  
17  
ns  
Case 2: First half-word access of HPID  
Read without auto-increment  
For HPI Read, HRDY stays low (ready)  
for these HPI Read conditions:  
Case 1: HPID read with auto-increment  
and data is already in Read FIFO  
(applies to either half-word of HPID  
access)  
Case 2: HPID read without auto-  
increment and data is already in Read  
FIFO (always applies to second half-  
word of HPID access)  
Case 3: HPIC or HPIA read (applies to  
either half-word access)  
5a  
6
td(HASL-HRDYV)  
ten(HSTBL-HDLZ)  
td(HRDYL-HDV)  
toh(HSTBH-HDV)  
tdis(HSTBH-HDHZ)  
Delay time, HAS low to HRDY valid  
15  
0
17  
0
ns  
ns  
ns  
ns  
ns  
Enable time, HD driven from HSTROBE low  
Delay time, HRDY low to HD valid  
1.5  
1.5  
1.5  
1.5  
7
8
Output hold time, HD valid after HSTROBE high  
Disable time, HD high-impedance from HSTROBE high  
14  
15  
17  
For HPI Read. Applies to conditions  
where data is already residing in  
HPID/FIFO:  
Case 1: HPIC or HPIA read  
Case 2: First half-word of HPID read  
with auto-increment and data is already  
in Read FIFO  
Delay time, HSTROBE low to  
HD valid  
15  
td(HSTBL-HDV)  
15  
17  
ns  
Case 3: Second half-word of HPID  
read with or without auto-increment  
For HPI Write, HRDY can go high (not  
ready) for these HPI Write conditions;  
otherwise, HRDY stays low (ready):  
Case 1: HPID write when Write FIFO is  
Delay time, HSTROBE high to full (can happen to either half-word)  
18  
td(HSTBH-HRDYV)  
15  
17  
ns  
HRDY valid  
Case 2: HPIA write (can happen to  
either half-word)  
Case 3: HPID write without auto-  
increment (only happens to second  
half-word)  
(1) M=SYSCLK2 period in ns.  
(2) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.  
(3) By design, whenever HCS is driven inactive (high), HPI will drive HRDY active (low).  
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Table 4-114. Switching Characteristics Over Recommended Operating Conditions for Host-Port Interface  
[1.0V](1) (2) (3)  
1.0V  
NO.  
PARAMETER  
UNIT  
MIN  
MAX  
For HPI Write, HRDY can go high (not ready) for  
these HPI Write conditions; otherwise, HRDY  
stays low (ready):  
Case 1: Back-to-back HPIA writes (can be either  
first or second half-word)  
Case 2: HPIA write following a PREFETCH  
command (can be either first or second half-  
word)  
Case 3: HPID write when FIFO is full or flushing  
(can be either first or second half-word)  
Case 4: HPIA write and Write FIFO not empty  
For HPI Read, HRDY can go high (not ready)  
for these HPI Read conditions:  
Case 1: HPID read (with auto-increment) and  
data not in Read FIFO (can only happen to first  
half-word of HPID access)  
Delay time, HSTROBE low to HRDY  
valid  
5
td(HSTBL-HRDYV)  
22  
ns  
Case 2: First half-word access of HPID Read  
without auto-increment  
For HPI Read, HRDY stays low (ready) for  
these HPI Read conditions:  
Case 1: HPID read with auto-increment and  
data is already in Read FIFO (applies to either  
half-word of HPID access)  
Case 2: HPID read without auto-increment and  
data is already in Read FIFO (always applies to  
second half-word of HPID access)  
Case 3: HPIC or HPIA read (applies to either  
half-word access)  
5a  
6
td(HASL-HRDYV)  
ten(HSTBL-HDLZ)  
td(HRDYL-HDV)  
toh(HSTBH-HDV)  
tdis(HSTBH-HDHZ)  
Delay time, HAS low to HRDY valid  
22  
0
ns  
ns  
ns  
ns  
ns  
Enable time, HD driven from HSTROBE low  
Delay time, HRDY low to HD valid  
1.5  
1.5  
7
8
Output hold time, HD valid after HSTROBE high  
Disable time, HD high-impedance from HSTROBE high  
14  
22  
For HPI Read. Applies to conditions where data  
is already residing in HPID/FIFO:  
Case 1: HPIC or HPIA read  
Delay time, HSTROBE low to HD  
valid  
15  
18  
td(HSTBL-HDV)  
Case 2: First half-word of HPID read with auto-  
increment and data is already in Read FIFO  
Case 3: Second half-word of HPID read with or  
without auto-increment  
22  
22  
ns  
For HPI Write, HRDY can go high (not ready) for  
these HPI Write conditions; otherwise, HRDY  
stays low (ready):  
Case 1: HPID write when Write FIFO is full (can  
happen to either half-word)  
Delay time, HSTROBE high to HRDY  
valid  
td(HSTBH-HRDYV)  
ns  
Case 2: HPIA write (can happen to either half-  
word)  
Case 3: HPID write without auto-increment (only  
happens to second half-word)  
(1) M=SYSCLK2 period in ns.  
(2) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.  
(3) By design, whenever HCS is driven inactive (high), HPI will drive HRDY active (low).  
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UHPI_HCS  
(D)  
UHPI_HAS  
2
2
1
1
1
1
1
1
UHPI_HCNTL[1:0]  
UHPI_HR/W  
2
2
2
2
UHPI_HHWIL  
4
3
3
(A)(C)  
UHPI_HSTROBE  
15  
6
15  
14  
14  
8
6
8
UHPI_HD[15:0]  
(output)  
13  
7
1st Half-Word  
2nd Half-Word  
5
(B)  
UHPI_HRDY  
A. UHPI_HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2: [NOT(HDS1  
XOR HDS2)] OR UHPI_HCS.  
B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with  
auto-incrementing)and the state of the FIFO, transitions on UHPI_HRDY may or may not occur.  
C. UHPI_HCS reflects typical UHPI_HCS behavior when UHPI_HSTROBE assertion is caused by UHPI_HDS1 or  
UHPI_HDS2. UHPI_HCS timing requirements are reflected by parameters for UHPI_HSTROBE.  
D
The diagram above assumes UHPI_HAS has been pulled high.  
Figure 4-68. UHPI Read Timing (HAS Not Used, Tied High)  
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(A)  
UHPI_HAS  
17  
10  
17  
10  
9
9
9
9
UHPI_HCNTL[1:0]  
UHPI_HR/W  
10  
10  
10  
10  
9
9
UHPI_HHWIL  
4
3
(B)  
UHPI_HSTROBE  
16  
16  
UHPI_HCS  
14  
14  
6
8
15  
8
UHPI_HD[15:0]  
(output)  
1st half-word  
2nd half-word  
5a  
7
UHPI_HRDY  
A. For correct operation, strobe the UHPI_HAS signal only once per UHPI_HSTROBE active cycle.  
B. UHPI_HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2:  
[NOT(UHPI_HDS1 XOR UHPI_HDS2)] OR UHPI_HCS.  
Figure 4-69. UHPI Read Timing (HAS Used)  
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UHPI_HCS  
(D)  
UHPI_HAS  
1
1
1
1
1
1
2
2
2
2
2
UHPI_HCNTL[1:0]  
UHPI_HR/W  
2
3
UHPI_HHWIL  
3
4
(A)(C)  
UHPI_HSTROBE  
11  
11  
12  
12  
2nd Half-Word  
18  
UHPI_HD[15:0]  
(input)  
1st Half-Word  
18  
5
13  
13  
5
(B)  
UHPI_HRDY  
A. UHPI_HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2: [NOT(HDS1 XOR HDS2)] OR  
UHPI_HCS.  
B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-incrementing) and the  
state of the FIFO, transitions on UHPI_HRDY may or may not occur.  
C. UHPI_HCS reflects typical UHPI_HCS behavior when UHPI_HSTROBE assertion is caused by UHPI_HDS1 or UHPI_HDS2. UHPI_HCS  
timing requirements are reflected by parameters for UHPI_HSTROBE.  
D
The diagram above assumes UHPI_HAS has been pulled high.  
Figure 4-70. UHPI Write Timing (HAS Not Used, Tied High)  
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17  
10  
17  
†
UHPI_HAS  
10  
10  
10  
9
9
9
9
9
9
UHPI_HCNTL[1:0]  
10  
10  
UHPI_HR/W  
UHPI_HHWIL  
3
4
‡
UHPI_HSTROBE  
16  
11  
16  
UHPI_HCS  
11  
12  
12  
UHPI_HD[15:0]  
(input)  
1st half-word  
2nd half-word  
5a  
13  
UHPI_HRDY  
A. For correct operation, strobe the UHPI_HAS signal only once per UHPI_HSTROBE active cycle.  
B. UHPI_HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2:  
[NOT(UHPI_HDS1 XOR UHPI_HDS2)] OR UHPI_HCS.  
Figure 4-71. UHPI Write Timing (HAS Used)  
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4.7.6.19 Universal Parallel Port (uPP)  
The Universal Parallel Port (uPP) peripheral is a multichannel, high-speed parallel interface with dedicated  
data lines and minimal control signals. It is designed to interface cleanly with high-speed analog-to-digital  
converters (ADCs) or digital-to-analog converters (DACs) with up to 16-bit data width (per channel). It may  
also be interconnected with field-programmable gate arrays (FPGAs) or other uPP devices to achieve  
high-speed digital data transfer. It can operate in receive mode, transmit mode, or duplex mode, in which  
its individual channels operate in opposite directions.  
The uPP peripheral includes an internal DMA controller to maximize throughput and minimize CPU  
overhead during high-speed data transmission. All uPP transactions use the internal DMA to provide data  
to or retrieve data from the I/O channels. The DMA controller includes two DMA channels, which typically  
service separate I/O channels. The uPP peripheral also supports data interleave mode, in which all DMA  
resources service a single I/O channel. In this mode, only one I/O channel may be used.  
The features of the uPP include:  
•
•
Programmable data width per channel (from 8 to 16 bits inclusive)  
Programmable data justification  
–
–
–
Right-justify with zero extend  
Right-justify with sign extend  
Left-justify with zero fill  
•
•
•
•
•
Supports multiplexing of interleaved data during SDR transmit  
Optional frame START signal with programmable polarity  
Optional data ENABLE signal with programmable polarity  
Optional synchronization WAIT signal with programmable polarity  
Single Data Rate (SDR) or Double data Rate (DDR, interleaved) interface  
–
–
Supports multiplexing of interleaved data during SDR transmit  
Supports demultiplexing and multiplexing of interleaved data during DDR transfers  
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4.7.6.19.1 uPP Register Descriptions  
Table 4-115. Universal Parallel Port (uPP) Registers  
BYTE ADDRESS  
0x01E1 6000  
0x01E1 6004  
0x01E1 6008  
0x01E1 6010  
0x01E1 6014  
0x01E1 6018  
0x01E1 601C  
0x01E1 6020  
0x01E1 6024  
0x01E1 6028  
0x01E1 602C  
0x01E1 6030  
0x01E1 6040  
0x01E1 6044  
0x01E1 6048  
0x01E1 6050  
0x01E1 6054  
0x01E1 6058  
0x01E1 6060  
0x01E1 6064  
0x01E1 6068  
0x01E1 6070  
0x01E1 6074  
0x01E1 6078  
ACRONYM  
UPPID  
UPPCR  
UPDLB  
UPCTL  
UPICR  
UPIVR  
UPTCR  
UPISR  
UPIER  
UPIES  
UPIEC  
UPEOI  
UPID0  
REGISTER DESCRIPTION  
uPP Peripheral Identification Register  
uPP Peripheral Control Register  
uPP Digital Loopback Register  
uPP Channel Control Register  
uPP Interface Configuration Register  
uPP Interface Idle Value Register  
uPP Threshold Configuration Register  
uPP Interrupt Raw Status Register  
uPP Interrupt Enabled Status Register  
uPP Interrupt Enable Set Register  
uPP Interrupt Enable Clear Register  
uPP End-of-Interrupt Register  
uPP DMA Channel I Descriptor 0 Register  
uPP DMA Channel I Descriptor 1 Register  
uPP DMA Channel I Descriptor 2 Register  
uPP DMA Channel I Status 0 Register  
uPP DMA Channel I Status 1 Register  
uPP DMA Channel I Status 2 Register  
uPP DMA Channel Q Descriptor 0 Register  
uPP DMA Channel Q Descriptor 1 Register  
uPP DMA Channel Q Descriptor 2 Register  
uPP DMA Channel Q Status 0 Register  
uPP DMA Channel Q Status 1 Register  
uPP DMA Channel Q Status 2 Register  
UPID1  
UPID2  
UPIS0  
UPIS1  
UPIS2  
UPQD0  
UPQD1  
UPQD2  
UPQS0  
UPQS1  
UPQS2  
202  
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4.7.6.19.2 uPP Electrical Data/Timing  
Table 4-116. Timing Requirements for uPP (see Figure 4-72, Figure 4-73, Figure 4-74, Figure 4-75)  
1.3V, 1.2V  
1.1V  
MIN MAX  
1.0V  
MIN MAX  
NO.  
1
UNIT  
ns  
MIN  
13.33  
26.66  
5
MAX  
SDR mode  
DDR mode  
SDR mode  
DDR mode  
SDR mode  
DDR mode  
20  
40  
8
26.66  
53.33  
10  
tc(INCLK)  
Cycle time, CHn_CLK  
2
tw(INCLKH)  
Pulse width, CHn_CLK high  
Pulse width, CHn_CLK low  
ns  
10  
16  
8
20  
5
10  
3
tw(INCLKL)  
ns  
10  
16  
5.5  
0.8  
5.5  
0.8  
20  
4
5
6
7
tsu(STV-INCLKH)  
th(INCLKH-STV)  
tsu(ENV-INCLKH)  
th(INCLKH-ENV)  
Setup time, CHn_START valid before CHn_CLK high  
Hold time, CHn_START valid after CHn_CLK high  
Setup time, CHn_ENABLE valid before CHn_CLK high  
Hold time, CHn_ENABLE valid after CHn_CLK high  
4
6.5  
0.8  
6.5  
0.8  
ns  
ns  
ns  
ns  
0.8  
4
0.8  
Setup time,  
8
9
tsu(DV-INCLKH)  
th(INCLKH-DV)  
tsu(DV-INCLKL)  
4
0.8  
4
5.5  
0.8  
5.5  
6.5  
0.8  
6.5  
ns  
ns  
ns  
CHn_DATA/XDATA valid before CHn_CLK high  
Hold time, CHn_DATA/XDATA valid after CHn_CLK high  
Setup time, CHn_DATA/XDATA valid before CHn_CLK  
low  
10  
11  
19  
20  
21  
th(INCLKL-DV)  
tsu(WTV-INCLKL)  
th(INCLKL-WTV)  
tc(2xTXCLK)  
Hold time, CHn_DATA/XDATA valid after CHn_CLK low  
Setup time, CHn_WAIT valid before CHn_CLK high  
Hold time, CHn_WAIT valid after CHn_CLK high  
Cycle time, 2xTXCLK input clock(1)  
0.8  
10  
0.8  
12  
0.8  
14  
ns  
ns  
ns  
ns  
0.8  
6.66  
0.8  
10  
0.8  
13.33  
(1) 2xTXCLK is an alternate transmit clock source that must be at least 2 times the required uPP transmit clock rate (as it is is divided down  
by 2 inside the uPP). 2xTXCLK has no specified skew relationship to the CHn_CLOCK and therefore is not shown in the timing diagram.  
Table 4-117. Switching Characteristics Over Recommended Operating Conditions for uPP  
1.3V, 1.2V  
1.1V  
1.0V  
NO.  
12  
PARAMETER  
UNIT  
ns  
MIN  
MAX  
MIN  
MAX  
MIN  
MAX  
SDR mode  
DDR mode  
SDR mode  
DDR mode  
SDR mode  
DDR mode  
13.33  
20  
40  
8
26.66  
53.33  
10  
20  
10  
20  
2
tc(OUTCLK)  
Cycle time, CHn_CLK  
26.66  
5
10  
5
13  
tw(OUTCLKH)  
Pulse width, CHn_CLK high  
Pulse width, CHn_CLK low  
ns  
16  
8
14  
tw(OUTCLKL)  
ns  
10  
2
16  
2
15  
16  
17  
18  
td(OUTCLKH-STV) Delay time, CHn_START valid after CHn_CLK high  
td(OUTCLKH-ENV) Delay time, CHn_ENABLE valid after CHn_CLK high  
11  
11  
11  
11  
15  
15  
15  
15  
21  
21  
21  
21  
ns  
ns  
ns  
ns  
2
2
2
td(OUTCLKH-DV)  
td(OUTCLKL-DV)  
Delay time, CHn_DATA/XDATA valid after CHn_CLK high  
Delay time, CHn_DATA/XDATA valid after CHn_CLK low  
2
2
2
2
2
2
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1
2
3
CHx_CLK  
CHx_START  
CHx_ENABLE  
CHx_WAIT  
4
5
6
7
8
9
CHx_DATA[n:0]  
CHx_XDATA[n:0]  
Data1  
Data2  
Data3  
Data4  
Data5  
Data6  
Data7  
Data8  
Data9  
Figure 4-72. uPP Single Data Rate (SDR) Receive Timing  
1
2
3
CHx_CLK  
4
5
CHx_START  
6
7
CHx_ENABLE  
CHx_WAIT  
10  
8
11  
9
CHx_DATA[n:0]  
CHx_XDATA[n:0]  
I1 Q1 I2 Q2 I3 Q3  
I4 Q4  
I5 Q5 I6 Q6 I7 Q7 I8 Q8 I9 Q9  
Figure 4-73. uPP Double Data Rate (DDR) Receive Timing  
204  
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12  
13  
14  
CHx_CLK  
15  
16  
CHx_START  
CHx_ENABLE  
CHx_WAIT  
19  
20  
17  
CHx_DATA[n:0]  
CHx_XDATA[n:0]  
Data1  
Data2  
Data3  
Data4  
Data5  
Data6  
Data7  
Data8  
Data9  
Figure 4-74. uPP Single Data Rate (SDR) Transmit Timing  
12  
13  
14  
CHx_CLK  
CHx_START  
CHx_ENABLE  
CHx_WAIT  
15  
16  
19  
20  
17  
18  
I5 Q5 I6 Q6 I7 Q7 I8 Q8 I9 Q9  
CHx_DATA[n:0]  
CHx_XDATA[n:0]  
I1 Q1 I2 Q2 I3 Q3  
I4 Q4  
Figure 4-75. uPP Double Data Rate (DDR) Transmit Timing  
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4.7.6.20 Video Port Interface (VPIF)  
The Video Port Interface (VPIF) allows the capture and display of digital video streams. Features include:  
•
Up to 2 Video Capture Channels (Channel 0 and Channel 1)  
–
–
–
Two 8-bit Standard-Definition (SD) Video with embedded timing codes (BT.656)  
Single 16-bit High-Definition (HD) Video with embedded timing codes (BT.1120)  
Single Raw Video (8-/10-/12-bit)  
•
Up to 2 Video Display Channels (Channel 2 and Channel 3)  
–
–
Two 8-bit SD Video Display with embedded timing codes (BT.656)  
Single 16-bit HD Video Display with embedded timing codes (BT.1120)  
The VPIF capture channel input data format is selectable based on the settings of the specific Channel  
Control Register (Channels 0–3). The VPIF Raw Video data-bus width is selectable based on the settings  
of the Channel 0 Control Register.  
206  
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4.7.6.20.1 VPIF Register Descriptions  
Table 4-118 shows the VPIF registers.  
Table 4-118. Video Port Interface (VPIF) Registers  
BYTE ADDRESS  
0x01E1 7000  
ACRONYM  
PID  
REGISTER DESCRIPTION  
Peripheral identification register  
0x01E1 7004  
CH0_CTRL  
CH1_CTRL  
CH2_CTRL  
CH3_CTRL  
-
Channel 0 control register  
Channel 1 control register  
Channel 2 control register  
Channel 3 control register  
Reserved  
0x01E1 7008  
0x01E1 700C  
0x01E1 7010  
0x01E1 7014 - 0x01E1 701F  
0x01E1 7020  
INTEN  
Interrupt enable  
0x01E1 7024  
INTENSET  
INTENCLR  
INTSTAT  
INTSTATCLR  
EMU_CTRL  
DMA_SIZE  
-
Interrupt enable set  
Interrupt enable clear  
Interrupt status  
0x01E1 7028  
0x01E1 702C  
0x01E1 7030  
Interrupt status clear  
Emulation control  
0x01E1 7034  
0x01E1 7038  
DMA size control  
0x01E1 703C - 0x01E1 703F  
Reserved  
CAPTURE CHANNEL 0 REGISTERS  
0x01E1 7040  
0x01E1 7044  
0x01E1 7048  
0x01E1 704C  
0x01E1 7050  
0x01E1 7054  
0x01E1 7058  
0x01E1 705C  
0x01E1 7060  
0x01E1 7064  
0x01E1 7068  
0x01E1 706C  
0x01E1 7070  
0x01E1 7074  
0x01E1 7078  
0x01E1 707C  
CH0_TY_STRTADR  
Channel 0 Top Field luma buffer start address  
Channel 0 Bottom Field luma buffer start address  
Channel 0 Top Field chroma buffer start address  
CH0_BY_STRTADR  
CH0_TC_STRTADR  
CH0_BC_STRTADR  
CH0_THA_STRTADR  
CH0_BHA_STRTADR  
CH0_TVA_STRTADR  
CH0_BVA_STRTADR  
CH0_SUBPIC_CFG  
CH0_IMG_ADD_OFST  
CH0_HA_ADD_OFST  
CH0_HSIZE_CFG  
Channel 0 Bottom Field chroma buffer start address  
Channel 0 Top Field horizontal ancillary data buffer start address  
Channel 0 Bottom Field horizontal ancillary data buffer start address  
Channel 0 Top Field vertical ancillary data buffer start address  
Channel 0 Bottom Field vertical ancillary data buffer start address  
Channel 0 sub-picture configuration  
Channel 0 image data address offset  
Channel 0 horizontal ancillary data address offset  
Channel 0 horizontal data size configuration  
CH0_VSIZE_CFG0  
CH0_VSIZE_CFG1  
CH0_VSIZE_CFG2  
CH0_VSIZE  
Channel 0 vertical data size configuration (0)  
Channel 0 vertical data size configuration (1)  
Channel 0 vertical data size configuration (2)  
Channel 0 vertical image size  
CAPTURE CHANNEL 1 REGISTERS  
0x01E1 7080  
0x01E1 7084  
0x01E1 7088  
0x01E1 708C  
0x01E1 7090  
0x01E1 7094  
0x01E1 7098  
0x01E1 709C  
0x01E1 70A0  
0x01E1 70A4  
0x01E1 70A8  
0x01E1 70AC  
CH1_TY_STRTADR  
CH1_BY_STRTADR  
CH1_TC_STRTADR  
CH1_BC_STRTADR  
CH1_THA_STRTADR  
CH1_BHA_STRTADR  
CH1_TVA_STRTADR  
CH1_BVA_STRTADR  
CH1_SUBPIC_CFG  
CH1_IMG_ADD_OFST  
CH1_HA_ADD_OFST  
CH1_HSIZE_CFG  
Channel 1 Top Field luma buffer start address  
Channel 1 Bottom Field luma buffer start address  
Channel 1 Top Field chroma buffer start address  
Channel 1 Bottom Field chroma buffer start address  
Channel 1 Top Field horizontal ancillary data buffer start address  
Channel 1 Bottom Field horizontal ancillary data buffer start address  
Channel 1 Top Field vertical ancillary data buffer start address  
Channel 1 Bottom Field vertical ancillary data buffer start address  
Channel 1 sub-picture configuration  
Channel 1 image data address offset  
Channel 1 horizontal ancillary data address offset  
Channel 1 horizontal data size configuration  
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Table 4-118. Video Port Interface (VPIF) Registers (continued)  
BYTE ADDRESS  
0x01E1 70B0  
0x01E1 70B4  
0x01E1 70B8  
0x01E1 70BC  
ACRONYM  
REGISTER DESCRIPTION  
Channel 1 vertical data size configuration (0)  
CH1_VSIZE_CFG0  
CH1_VSIZE_CFG1  
CH1_VSIZE_CFG2  
CH1_VSIZE  
Channel 1 vertical data size configuration (1)  
Channel 1 vertical data size configuration (2)  
Channel 1 vertical image size  
DISPLAY CHANNEL 2 REGISTERS  
0x01E1 70C0  
0x01E1 70C4  
0x01E1 70C8  
0x01E1 70CC  
0x01E1 70D0  
0x01E1 70D4  
0x01E1 70D8  
0x01E1 70DC  
0x01E1 70E0  
0x01E1 70E4  
0x01E1 70E8  
0x01E1 70EC  
0x01E1 70F0  
0x01E1 70F4  
0x01E1 70F8  
0x01E1 70FC  
0x01E1 7100  
0x01E1 7104  
0x01E1 7108  
0x01E1 710C  
0x01E1 7110  
0x01E1 7114  
0x01E1 7118  
0x01E1 711C  
0x01E1 7120 - 0x01E1 713F  
CH2_TY_STRTADR  
CH2_BY_STRTADR  
CH2_TC_STRTADR  
CH2_BC_STRTADR  
CH2_THA_STRTADR  
CH2_BHA_STRTADR  
CH2_TVA_STRTADR  
CH2_BVA_STRTADR  
CH2_SUBPIC_CFG  
CH2_IMG_ADD_OFST  
CH2_HA_ADD_OFST  
CH2_HSIZE_CFG  
CH2_VSIZE_CFG0  
CH2_VSIZE_CFG1  
CH2_VSIZE_CFG2  
CH2_VSIZE  
Channel 2 Top Field luma buffer start address  
Channel 2 Bottom Field luma buffer start address  
Channel 2 Top Field chroma buffer start address  
Channel 2 Bottom Field chroma buffer start address  
Channel 2 Top Field horizontal ancillary data buffer start address  
Channel 2 Bottom Field horizontal ancillary data buffer start address  
Channel 2 Top Field vertical ancillary data buffer start address  
Channel 2 Bottom Field vertical ancillary data buffer start address  
Channel 2 sub-picture configuration  
Channel 2 image data address offset  
Channel 2 horizontal ancillary data address offset  
Channel 2 horizontal data size configuration  
Channel 2 vertical data size configuration (0)  
Channel 2 vertical data size configuration (1)  
Channel 2 vertical data size configuration (2)  
Channel 2 vertical image size  
CH2_THA_STRTPOS  
CH2_THA_SIZE  
Channel 2 Top Field horizontal ancillary data insertion start position  
Channel 2 Top Field horizontal ancillary data size  
Channel 2 Bottom Field horizontal ancillary data insertion start position  
Channel 2 Bottom Field horizontal ancillary data size  
Channel 2 Top Field vertical ancillary data insertion start position  
Channel 2 Top Field vertical ancillary data size  
Channel 2 Bottom Field vertical ancillary data insertion start position  
Channel 2 Bottom Field vertical ancillary data size  
Reserved  
CH2_BHA_STRTPOS  
CH2_BHA_SIZE  
CH2_TVA_STRTPOS  
CH2_TVA_SIZE  
CH2_BVA_STRTPOS  
CH2_BVA_SIZE  
-
DISPLAY CHANNEL 3 REGISTERS  
0x01E1 7140  
0x01E1 7144  
0x01E1 7148  
0x01E1 714C  
0x01E1 7150  
0x01E1 7154  
0x01E1 7158  
0x01E1 715C  
0x01E1 7160  
0x01E1 7164  
0x01E1 7168  
0x01E1 716C  
0x01E1 7170  
0x01E1 7174  
0x01E1 7178  
0x01E1 717C  
CH3_TY_STRTADR  
CH3_BY_STRTADR  
CH3_TC_STRTADR  
CH3_BC_STRTADR  
CH3_THA_STRTADR  
CH3_BHA_STRTADR  
CH3_TVA_STRTADR  
CH3_BVA_STRTADR  
CH3_SUBPIC_CFG  
CH3_IMG_ADD_OFST  
CH3_HA_ADD_OFST  
CH3_HSIZE_CFG  
Channel 3 Field 0 luma buffer start address  
Channel 3 Field 1 luma buffer start address  
Channel 3 Field 0 chroma buffer start address  
Channel 3 Field 1 chroma buffer start address  
Channel 3 Field 0 horizontal ancillary data buffer start address  
Channel 3 Field 1 horizontal ancillary data buffer start address  
Channel 3 Field 0 vertical ancillary data buffer start address  
Channel 3 Field 1 vertical ancillary data buffer start address  
Channel 3 sub-picture configuration  
Channel 3 image data address offset  
Channel 3 horizontal ancillary data address offset  
Channel 3 horizontal data size configuration  
Channel 3 vertical data size configuration (0)  
Channel 3 vertical data size configuration (1)  
Channel 3 vertical data size configuration (2)  
Channel 3 vertical image size  
CH3_VSIZE_CFG0  
CH3_VSIZE_CFG1  
CH3_VSIZE_CFG2  
CH3_VSIZE  
208  
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Table 4-118. Video Port Interface (VPIF) Registers (continued)  
BYTE ADDRESS  
ACRONYM  
CH3_THA_STRTPOS  
CH3_THA_SIZE  
CH3_BHA_STRTPOS  
CH3_BHA_SIZE  
CH3_TVA_STRTPOS  
CH3_TVA_SIZE  
CH3_BVA_STRTPOS  
CH3_BVA_SIZE  
-
REGISTER DESCRIPTION  
0x01E1 7180  
0x01E1 7184  
Channel 3 Top Field horizontal ancillary data insertion start position  
Channel 3 Top Field horizontal ancillary data size  
Channel 3 Bottom Field horizontal ancillary data insertion start position  
Channel 3 Bottom Field horizontal ancillary data size  
Channel 3 Top Field vertical ancillary data insertion start position  
Channel 3 Top Field vertical ancillary data size  
0x01E1 7188  
0x01E1 718C  
0x01E1 7190  
0x01E1 7194  
0x01E1 7198  
Channel 3 Bottom Field vertical ancillary data insertion start position  
Channel 3 Bottom Field vertical ancillary data size  
Reserved  
0x01E1 719C  
0x01E1 71A0 - 0x01E1 71FF  
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4.7.6.20.2 VPIF Electrical Data/Timing  
Table 4-119. Timing Requirements for VPIF VP_CLKINx Inputs(1) (see Figure 4-76)  
1.3V, 1.2V  
1.1V  
1.0V  
NO.  
UNIT  
MIN MAX MIN MAX MIN MAX  
Cycle time, VP_CLKIN0  
13.3  
13.3  
0.4C  
0.4C  
20  
20  
37  
37  
ns  
ns  
ns  
ns  
ns  
1
tc(VKI)  
Cycle time, VP_CLKIN1/2/3  
Pulse duration, VP_CLKINx high  
Pulse duration, VP_CLKINx low  
Transition time, VP_CLKINx  
2
3
4
tw(VKIH)  
tw(VKIL)  
tt(VKI)  
0.4C  
0.4C  
0.4C  
0.4C  
5
5
5
(1) C = VP_CLKINx period in ns.  
1
4
2
3
VP_CLKINx  
4
Figure 4-76. Video Port Capture VP_CLKINx Timing  
210  
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Table 4-120. Timing Requirements for VPIF Channels 0/1 Video Capture Data and Control Inputs  
(see Figure 4-77)  
1.3V  
1.2V  
1.1V  
1.0V  
NO.  
UNIT  
MIN MAX MIN MAX MIN MAX MIN MAX  
tsu(VDINV-  
VKIH)  
1
2
Setup time, VP_DINx valid before VP_OSCIN0/1 high  
4
4
0
6
0
7
0
ns  
ns  
th(VKIH-VDINV) Hold time, VP_DINx valid after VP_CLKIN0/1 high  
0.5  
VP_CLKIN0/1  
1
2
VP_DINx/FIELD/  
HSYNC/VSYNC  
Figure 4-77. VPIF Channels 0/1 Video Capture Data and Control Input Timing  
Table 4-121. Switching Characteristics Over Recommended Operating Conditions for Video Data Shown  
With Respect to VP_CLKOUT2/3(1)  
(see Figure 4-78)  
1.3V, 1.2V  
1.1V  
1.0V  
NO.  
PARAMETER  
UNIT  
MIN  
13.3  
0.4C  
0.4C  
MAX  
MIN  
MAX  
MIN  
MAX  
1
2
3
4
tc(VKO)  
Cycle time, VP_CLKOUT2/3  
20  
37  
ns  
ns  
ns  
ns  
tw(VKOH)  
tw(VKOL)  
tt(VKO)  
Pulse duration, VP_CLKOUT2/3 high  
Pulse duration, VP_CLKOUT2/3 low  
Transition time, VP_CLKOUT2/3  
0.4C  
0.4C  
0.4C  
0.4C  
5
5
5
Delay time,  
VP_CLKOUT2/3 high to VP_DOUTx valid  
11  
12  
td(VKOH-VPDOUTV)  
8.5  
12  
17  
ns  
ns  
Delay time,  
VP_CLKOUT2/3 high to VP_DOUTx invalid  
td(VCLKOH-VPDOUTIV)  
1.5  
1.5  
1.5  
(1) C = VP_CLKO2/3 period in ns.  
2
1
VP_CLKOUTx  
(Positive Edge  
Clocking)  
3
4
4
VP_CLKOUTx  
(Negative Edge  
Clocking)  
11  
12  
VP_DOUTx  
Figure 4-78. VPIF Channels 2/3 Video Display Data Output Timing With Respect to VP_CLKOUT2/3  
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4.7.6.21 Enhanced Capture (eCAP) Peripheral  
The device contains up to three enhanced capture (eCAP) modules. Figure 4-79 shows a functional block  
diagram of a module.  
Uses for ECAP include:  
•
•
•
•
Speed measurements of rotating machinery (e.g. toothed sprockets sensed via Hall sensors)  
Elapsed time measurements between position sensor triggers  
Period and duty cycle measurements of pulse train signals  
Decoding current or voltage amplitude derived from duty cycle encoded current/voltage sensors  
The ECAP module described in this specification includes the following features:  
•
•
•
•
•
•
•
•
•
32 bit time base  
4 event time-stamp registers (each 32 bits)  
Edge polarity selection for up to 4 sequenced time-stamp capture events  
Interrupt on either of the 4 events  
Single shot capture of up to 4 event time-stamps  
Continuous mode capture of time-stamps in a 4 deep circular buffer  
Absolute time-stamp capture  
Difference mode time-stamp capture  
All the above resources are dedicated to a single input pin  
The eCAP modules are clocked at the ASYNC3 clock domain rate.  
212  
Specifications  
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CTRPHS  
(phase register−32 bit)  
APWM mode  
SYNCIn  
CTR_OVF  
OVF  
CTR [0−31]  
PRD [0−31]  
CMP [0−31]  
TSCTR  
(counter−32 bit)  
SYNCOut  
PWM  
compare  
logic  
Delta−mode  
RST  
32  
CTR=PRD  
CTR=CMP  
CTR [0−31]  
PRD [0−31]  
32  
eCAPx  
32  
LD1  
CAP1  
(APRD active)  
Polarity  
select  
LD  
APRD  
shadow  
32  
CMP [0−31]  
32  
32  
LD2  
CAP2  
(ACMP active)  
Polarity  
select  
LD  
Event  
qualifier  
Event  
Pre-scale  
32  
ACMP  
shadow  
Polarity  
select  
32  
32  
LD3  
LD4  
CAP3  
(APRD shadow)  
LD  
CAP4  
(ACMP shadow)  
Polarity  
select  
LD  
4
Capture events  
4
CEVT[1:4]  
Interrupt  
Trigger  
and  
Flag  
Continuous /  
Oneshot  
Capture Control  
to Interrupt  
Controller  
CTR_OVF  
CTR=PRD  
CTR=CMP  
control  
Figure 4-79. eCAP Functional Block Diagram  
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Table 4-122 is the list of the ECAP registers.  
Table 4-122. ECAPx Configuration Registers  
ECAP0  
BYTE ADDRESS  
ECAP1  
BYTE ADDRESS  
ECAP2  
ACRONYM  
DESCRIPTION  
Time-Stamp Counter  
BYTE ADDRESS  
0x01F0 8000  
0x01F0 8004  
0x01F0 8008  
0x01F0 800C  
0x01F0 8010  
0x01F0 8014  
0x01F0 8028  
0x01F0 802A  
0x01F0 802C  
0x01F0 802E  
0x01F0 8030  
0x01F0 8032  
0x01F0 805C  
0x01F0 6000  
0x01F0 6004  
0x01F0 6008  
0x01F0 600C  
0x01F0 6010  
0x01F0 6014  
0x01F0 6028  
0x01F0 602A  
0x01F0 602C  
0x01F0 602E  
0x01F0 6030  
0x01F0 6032  
0x01F0 605C  
0x01F0 7000  
0x01F0 7004  
0x01F0 7008  
0x01F0 700C  
0x01F0 7010  
0x01F0 7014  
0x01F0 7028  
0x01F0 702A  
0x01F0 702C  
0x01F0 702E  
0x01F0 7030  
0x01F0 7032  
0x01F0 705C  
TSCTR  
CTRPHS  
CAP1  
Counter Phase Offset Value Register  
Capture 1 Register  
CAP2  
Capture 2 Register  
CAP3  
Capture 3 Register  
CAP4  
Capture 4 Register  
ECCTL1  
ECCTL2  
ECEINT  
ECFLG  
ECCLR  
ECFRC  
REVID  
Capture Control Register 1  
Capture Control Register 2  
Capture Interrupt Enable Register  
Capture Interrupt Flag Register  
Capture Interrupt Clear Register  
Capture Interrupt Force Register  
Revision ID  
Table 4-123 shows the eCAP timing requirement and Table 4-124 shows the eCAP switching  
characteristics.  
Table 4-123. Timing Requirements for Enhanced Capture (eCAP)  
1.3V, 1.2V, 1.1V, 1.0V  
TEST CONDITIONS  
UNIT  
MIN  
MAX  
tw(CAP)  
Capture input pulse width  
Asynchronous  
Synchronous  
2tc(SCO)  
2tc(SCO)  
cycles  
cycles  
Table 4-124. Switching Characteristics Over Recommended Operating Conditions for eCAP  
1.3V, 1.2V  
1.1V  
1.0V  
PARAMETER  
UNIT  
MIN  
MAX  
MIN  
MAX  
MIN  
MAX  
tw(APWM)  
Pulse duration, APWMx  
output high/low  
20  
20  
20  
ns  
214  
Specifications  
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4.7.6.22 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)  
The device contains two enhanced PWM Modules (eHRPWM). Figure 4-80 shows a block diagram of  
multiple eHRPWM modules. Figure 4-80 shows the signal interconnections with the eHRPWM.  
EPWMSYNCI  
EPWM0SYNCI  
EPWM0INT  
EPWM0A  
EPWM0B  
ePWM0 module  
TZ  
Interrupt  
Controllers  
EPWM0SYNCO  
GPIO  
MUX  
EPWM1SYNCI  
EPWM1INT  
EPWM1A  
EPWM1B  
ePWM1 module  
EPWM1SYNCO  
TZ  
To eCAP0  
module  
(sync in)  
EPWMSYNCO  
Peripheral Bus  
Figure 4-80. Multiple PWM Modules in a C6748 System  
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Time−base (TB)  
Sync  
in/out  
select  
Mux  
CTR=ZERO  
CTR=CMPB  
Disabled  
TBPRD shadow (16)  
EPWMSYNCO  
TBPRD active (16)  
CTR=PRD  
TBCTL[SYNCOSEL]  
TBCTL[CNTLDE]  
EPWMSYNCI  
Counter  
up/down  
(16 bit)  
TBCTL[SWFSYNC]  
(software forced sync)  
CTR=ZERO  
CTR_Dir  
TBCNT  
active (16)  
TBPHSHR (8)  
16  
8
CTR = PRD  
CTR = ZERO  
CTR = CMPA  
CTR = CMPB  
CTR_Dir  
Phase  
Event  
trigger  
and  
interrupt  
(ET)  
TBPHS active (24)  
control  
EPWMxINT  
Counter compare (CC)  
CTR=CMPA  
CMPAHR (8)  
Action  
qualifier  
(AQ)  
16  
8
HiRes PWM (HRPWM)  
CMPA active (24)  
EPWMA  
EPWMB  
EPWMxA  
CMPA shadow (24)  
CTR=CMPB  
Dead  
band  
(DB)  
PWM  
chopper  
(PC)  
Trip  
zone  
(TZ)  
16  
EPWMxB  
EPWMxTZINT  
TZ  
CMPB active (16)  
CMPB shadow (16)  
CTR = ZERO  
Figure 4-81. eHRPWM Sub-Modules Showing Critical Internal Signal Interconnections  
216  
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Table 4-125. eHRPWM Module Control and Status Registers Grouped by Submodule  
eHRPWM0  
eHRPWM1  
BYTE ADDRESS  
BYTE ADDRESS  
ACRONYM  
SHADOW  
REGISTER DESCRIPTION  
Time-Base Submodule Registers  
0x01F0 0000  
0x01F0 0002  
0x01F0 0004  
0x01F0 0006  
0x01F0 0008  
0x01F0 000A  
0x01F0 2000  
0x01F0 2002  
0x01F0 2004  
0x01F0 2006  
0x01F0 2008  
0x01F0 200A  
TBCTL  
TBSTS  
TBPHSHR  
No  
No  
No  
No  
No  
Yes  
Time-Base Control Register  
Time-Base Status Register  
Extension for HRPWM Phase Register(1)  
TBPHS  
TBCNT  
TBPRD  
Time-Base Phase Register  
Time-Base Counter Register  
Time-Base Period Register  
Counter-Compare Submodule Registers  
0x01F0 000E  
0x01F0 0010  
0x01F0 0012  
0x01F0 0014  
0x01F0 200E  
0x01F0 2010  
0x01F0 2012  
0x01F0 2014  
CMPCTL  
CMPAHR  
CMPA  
No  
No  
Counter-Compare Control Register  
Extension for HRPWM Counter-Compare A Register(1)  
Counter-Compare A Register  
Yes  
Yes  
CMPB  
Counter-Compare B Register  
Action-Qualifier Submodule Registers  
0x01F0 0016  
0x01F0 0018  
0x01F0 001A  
0x01F0 001C  
0x01F0 2016  
0x01F0 2018  
0x01F0 201A  
0x01F0 201C  
AQCTLA  
AQCTLB  
AQSFRC  
AQCSFRC  
No  
No  
Action-Qualifier Control Register for Output A (eHRPWMxA)  
Action-Qualifier Control Register for Output B (eHRPWMxB)  
Action-Qualifier Software Force Register  
No  
Yes  
Action-Qualifier Continuous S/W Force Register Set  
Dead-Band Generator Submodule Registers  
0x01F0 001E  
0x01F0 0020  
0x01F0 0022  
0x01F0 201E  
0x01F0 2020  
0x01F0 2022  
DBCTL  
DBRED  
DBFED  
No  
No  
No  
Dead-Band Generator Control Register  
Dead-Band Generator Rising Edge Delay Count Register  
Dead-Band Generator Falling Edge Delay Count Register  
PWM-Chopper Submodule Registers  
PCCTL No PWM-Chopper Control Register  
Trip-Zone Submodule Registers  
0x01F0 003C  
0x01F0 203C  
0x01F0 0024  
0x01F0 0028  
0x01F0 002A  
0x01F0 002C  
0x01F0 002E  
0x01F0 0030  
0x01F0 2024  
0x01F0 2028  
0x01F0 202A  
0x01F0 202C  
0x01F0 202E  
0x01F0 2030  
TZSEL  
No  
No  
No  
No  
No  
No  
Trip-Zone Select Register  
TZCTL  
TZEINT  
TZFLG  
TZCLR  
TZFRC  
Trip-Zone Control Register  
Trip-Zone Enable Interrupt Register  
Trip-Zone Flag Register  
Trip-Zone Clear Register  
Trip-Zone Force Register  
Event-Trigger Submodule Registers  
0x01F0 0032  
0x01F0 0034  
0x01F0 0036  
0x01F0 0038  
0x01F0 003A  
0x01F0 2032  
0x01F0 2034  
0x01F0 2036  
0x01F0 2038  
0x01F0 203A  
ETSEL  
No  
No  
No  
No  
No  
Event-Trigger Selection Register  
ETPS  
ETFLG  
ETCLR  
ETFRC  
Event-Trigger Pre-Scale Register  
Event-Trigger Flag Register  
Event-Trigger Clear Register  
Event-Trigger Force Register  
High-Resolution PWM (HRPWM) Submodule Registers  
HRCNFG No HRPWM Configuration Register  
(1)  
0x01F0 1040  
0x01F0 3040  
(1) These registers are only available on eHRPWM instances that include the high-resolution PWM (HRPWM) extension; otherwise, these  
locations are reserved.  
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4.7.6.22.1 Enhanced Pulse Width Modulator (eHRPWM) Timing  
PWM refers to PWM outputs on eHRPWM1-6. Table 4-126 shows the PWM timing requirements and  
Table 4-127, switching characteristics.  
Table 4-126. Timing Requirements for eHRPWM  
TEST CONDITIONS  
1.3V, 1.2V, 1.1V, 1.0V  
UNIT  
MIN  
MAX  
tw(SYNCIN)  
Sync input pulse width  
Asynchronous  
Synchronous  
2tc(SCO)  
2tc(SCO)  
cycles  
cycles  
Table 4-127. Switching Characteristics Over Recommended Operating Conditions for eHRPWM  
PARAMETER  
TEST  
CONDITIONS  
1.3V, 1.2V  
1.1V  
MIN  
1.0V  
MIN  
UNIT  
MIN  
MAX  
MAX  
MAX  
tw(PWM)  
Pulse duration, PWMx output  
high/low  
ns  
20  
20  
26.6  
tw(SYNCOUT)  
td(PWM)TZA  
Sync output pulse width  
8tc(SCO)  
8tc(SCO)  
8tc(SCO)  
cycles  
ns  
Delay time, trip input active to  
PWM forced high  
Delay time, trip input active to  
PWM forced low  
no pin load; no  
additional  
programmable  
delay  
25  
20  
25  
20  
25  
20  
td(TZ-PWM)HZ  
Delay time, trip input active to  
PWM Hi-Z  
no additional  
programmable  
delay  
ns  
218  
Specifications  
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4.7.6.22.2 Trip-Zone Input Timing  
t
w(TZ)  
TZ  
t
d(TZ-PWM)HZ  
(A)  
PWM  
A. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM  
recovery software.  
Figure 4-82. PWM Hi-Z Characteristics  
Table 4-128. Trip-Zone input Timing Requirements  
TEST CONDITIONS  
1.3V, 1.2V, 1.1V, 1.0V  
UNIT  
MIN  
MAX  
tw(TZ)  
Pulse duration, TZx input low  
Asynchronous  
Synchronous  
1tc(SCO)  
2tc(SCO)  
cycles  
cycles  
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4.7.6.23 Timers  
The timers support the following features:  
•
•
•
•
•
•
Configurable as single 64-bit timer or two 32-bit timers  
Period timeouts generate interrupts, DMA events or external pin events  
8 32-bit compare registers  
Compare matches generate interrupt events  
Capture capability  
64-bit Watchdog capability (Timer64P1 only)  
Table 4-129 lists the timer registers.  
Table 4-129. Timer Registers  
TIMER64P 0  
BYTE  
TIMER64P 1  
BYTE  
TIMER64P 2  
BYTE  
TIMER64P 3  
BYTE  
ACRONYM  
REGISTER DESCRIPTION  
ADDRESS  
ADDRESS  
ADDRESS  
ADDRESS  
0x01C2 0000  
0x01C2 0004  
0x01C2 0008  
0x01C2 000C  
0x01C2 0010  
0x01C2 0014  
0x01C2 0018  
0x01C2 001C  
0x01C2 0020  
0x01C2 0024  
0x01C2 0028  
0x01C2 0034  
0x01C2 0038  
0x01C2 003C  
0x01C2 0040  
0x01C2 0044  
0x01C2 0060  
0x01C2 0064  
0x01C2 0068  
0x01C2 006C  
0x01C2 0070  
0x01C2 0074  
0x01C2 0078  
0x01C2 007C  
0x01C2 1000  
0x01C2 1004  
0x01C2 1008  
0x01C2 100C  
0x01C2 1010  
0x01C2 1014  
0x01C2 1018  
0x01C2 101C  
0x01C2 1020  
0x01C2 1024  
0x01C2 1028  
0x01C2 1034  
0x01C2 1038  
0x01C2 103C  
0x01C2 1040  
0x01C2 1044  
0x01C2 1060  
0x01C2 1064  
0x01C2 1068  
0x01C2 106C  
0x01C2 1070  
0x01C2 1074  
0x01C2 1078  
0x01C2 107C  
0x01F0 C000  
0x01F0 C004  
0x01F0 C008  
0x01F0 C00C  
0x01F0 C010  
0x01F0 C014  
0x01F0 C018  
0x01F0 C01C  
0x01F0 C020  
0x01F0 C024  
0x01F0 C028  
0x01F0 C034  
0x01F0 C038  
0x01F0 C03C  
0x01F0 C040  
0x01F0 C044  
0x01F0 C060  
0x01F0 C064  
0x01F0 C068  
0x01F0 C06C  
0x01F0 C070  
0x01F0 C074  
0x01F0 C078  
0x01F0 C07C  
0x01F0 D000  
0x01F0 D004  
0x01F0 D008  
0x01F0 D00C  
0x01F0 D010  
0x01F0 D014  
0x01F0 D018  
0x01F0 D01C  
0x01F0 D020  
0x01F0 D024  
0x01F0 D028  
0x01F0 D034  
0x01F0 D038  
0x01F0 D03C  
0x01F0 D040  
0x01F0 D044  
0x01F0 D060  
0x01F0 D064  
0x01F0 D068  
0x01F0 D06C  
0x01F0 D070  
0x01F0 D074  
0x01F0 D078  
0x01F0 D07C  
REV  
Revision Register  
Emulation Management Register  
EMUMGT  
GPINTGPEN GPIO Interrupt and GPIO Enable Register  
GPDATGPDIR GPIO Data and GPIO Direction Register  
TIM12  
TIM34  
PRD12  
PRD34  
TCR  
Timer Counter Register 12  
Timer Counter Register 34  
Timer Period Register 12  
Timer Period Register 34  
Timer Control Register  
TGCR  
WDTCR  
REL12  
REL34  
CAP12  
CAP34  
Timer Global Control Register  
Watchdog Timer Control Register  
Timer Reload Register 12  
Timer Reload Register 34  
Timer Capture Register 12  
Timer Capture Register 34  
INTCTLSTAT Timer Interrupt Control and Status Register  
CMP0  
CMP1  
CMP2  
CMP3  
CMP4  
CMP5  
CMP6  
CMP7  
Compare Register 0  
Compare Register 1  
Compare Register 2  
Compare Register 3  
Compare Register 4  
Compare Register 5  
Compare Register 6  
Compare Register 7  
220  
Specifications  
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4.7.6.23.1 Timer Electrical Data/Timing  
Table 4-130. Timing Requirements for Timer Input(1) (2) (see Figure 4-83)  
1.3V, 1.2V, 1.1V, 1.0V  
NO.  
UNIT  
MIN  
4P  
MAX  
1
2
3
tc(TM64Px_IN12) Cycle time, TM64Px_IN12  
tw(TINPH) Pulse duration, TM64Px_IN12 high  
tw(TINPL) Pulse duration, TM64Px_IN12 low  
ns  
ns  
ns  
0.45C  
0.45C  
0.55C  
0.55C  
0.25P or 10  
4
tt(TM64Px_IN12) Transition time, TM64Px_IN12  
ns  
(3)  
(1) P = OSCIN cycle time in ns.  
(2) C = TM64P0_IN12 cycle time in ns.  
(3) Whichever is smaller. P = the period of the applied signal. Maintaining transition times as fast as possible is recommended to improve  
noise immunity on input signals.  
1
2
3
4
4
TM64P0_IN12  
Figure 4-83. Timer Timing  
(1)  
Table 4-131. Switching Characteristics Over Recommended Operating Conditions for Timer Output  
1.3V, 1.2V, 1.1V, 1.0V  
NO.  
PARAMETER  
UNIT  
MIN  
4P  
MAX  
5
6
tw(TOUTH)  
tw(TOUTL)  
Pulse duration, TM64P0_OUT12 high  
Pulse duration, TM64P0_OUT12 low  
ns  
ns  
4P  
(1) P = OSCIN cycle time in ns. For example, when OSCIN frequency is 27 MHz, use P = 37.037 ns.  
5
6
TM64P0_OUT12  
Figure 4-84. Timer Timing  
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4.7.6.24 Real Time Clock (RTC)  
The RTC provides a time reference to an application running on the device. The current date and time is  
tracked in a set of counter registers that update once per second. The time can be represented in 12-hour  
or 24-hour mode. The calendar and time registers are buffered during reads and writes so that updates do  
not interfere with the accuracy of the time and date.  
Alarms are available to interrupt the CPU at a particular time, or at periodic time intervals, such as once  
per minute or once per day. In addition, the RTC can interrupt the CPU every time the calendar and time  
registers are updated, or at programmable periodic intervals.  
The real-time clock (RTC) provides the following features:  
•
•
•
•
•
•
•
•
•
100-year calendar (xx00 to xx99)  
Counts seconds, minutes, hours, day of the week, date, month, and year with leap year compensation  
Binary-coded-decimal (BCD) representation of time, calendar, and alarm  
12-hour clock mode (with AM and PM) or 24-hour clock mode  
Alarm interrupt  
Periodic interrupt  
Single interrupt to the CPU  
Supports external 32.768-kHz crystal or external clock source of the same frequency  
Separate isolated power supply  
Figure 4-85 shows a block diagram of the RTC.  
Oscillator  
Compensation  
Week  
Days  
Counter  
32 kHz  
RTC_XI  
XTAL  
Hours  
Days  
Years  
Seconds  
Minutes  
Months  
RTC_XO  
Oscillator  
Alarm  
Interrupts  
Alarm  
Periodic  
Interrupts  
Timer  
Figure 4-85. Real-Time Clock Block Diagram  
222  
Specifications  
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4.7.6.24.1 Clock Source  
The clock reference for the RTC is an external 32.768-kHz crystal or an external clock source of the same  
frequency. The RTC also has a separate power supply that is isolated from the rest of the system. When  
the CPU and other peripherals are without power, the RTC can remain powered to preserve the current  
time and calendar information. Even if the RTC is not used, it must remain powered when the rest of the  
device is powered.  
The source for the RTC reference clock may be provided by a crystal or by an external clock source. The  
RTC has an internal oscillator buffer to support direct operation with a crystal. The crystal is connected  
between pins RTC_XI and RTC_XO. RTC_XI is the input to the on-chip oscillator and RTC_XO is the  
output from the oscillator back to the crystal.  
An external 32.768-kHz clock source may be used instead of a crystal. In such a case, the clock source is  
connected to RTC_XI, and RTC_XO is left unconnected.  
If the RTC is not used, the RTC_XI pin should be held either low or high, RTC_XO should be left  
unconnected, RTC_CVDD should be connected to the device CVDD and RTC_VSS should remain  
grounded.  
CVDD  
RTC  
Power  
Source  
RTC_CVDD  
C2  
RTC_XI  
XTAL  
32.768  
kHz  
Real  
Time  
Clock  
(RTC)  
Module  
RTC_XO  
32K  
OSC  
C1  
RTC_VSS  
Isolated RTC  
Power Domain  
Figure 4-86. Clock Source  
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4.7.6.24.2 Real-Time Clock Register Descriptions  
Table 4-132. Real-Time Clock (RTC) Registers  
BYTE ADDRESS  
0x01C2 3000  
0x01C2 3004  
0x01C2 3008  
0x01C2 300C  
0x01C2 3010  
0x01C2 3014  
0x01C2 3018  
0x01C2 3020  
0x01C2 3024  
0x01C2 3028  
0x01C2 302C  
0x01C2 3030  
0x01C2 3034  
0x01C2 3040  
0x01C2 3044  
0x01C2 3048  
0x01C2 304C  
0x01C2 3050  
0x01C2 3054  
0x01C2 3060  
0x01C2 3064  
0x01C2 3068  
0x01C2 306C  
0x01C2 3070  
ACRONYM  
REGISTER DESCRIPTION  
SECOND  
MINUTE  
Seconds Register  
Minutes Register  
HOUR  
Hours Register  
DAY  
Day of the Month Register  
Month Register  
MONTH  
YEAR  
Year Register  
DOTW  
Day of the Week Register  
Alarm Seconds Register  
Alarm Minutes Register  
Alarm Hours Register  
ALARMSECOND  
ALARMMINUTE  
ALARMHOUR  
ALARMDAY  
ALARMMONTH  
ALARMYEAR  
CTRL  
Alarm Days Register  
Alarm Months Register  
Alarm Years Register  
Control Register  
STATUS  
Status Register  
INTERRUPT  
COMPLSB  
COMPMSB  
OSC  
Interrupt Enable Register  
Compensation (LSB) Register  
Compensation (MSB) Register  
Oscillator Register  
SCRATCH0  
SCRATCH1  
SCRATCH2  
KICK0  
Scratch 0 (General-Purpose) Register  
Scratch 1 (General-Purpose) Register  
Scratch 2 (General-Purpose) Register  
Kick 0 (Write Protect) Register  
Kick 1 (Write Protect) Register  
KICK1  
224  
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4.7.6.25 General-Purpose Input/Output (GPIO)  
The GPIO peripheral provides general-purpose pins that can be configured as either inputs or outputs.  
When configured as an output, a write to an internal register can control the state driven on the output pin.  
When configured as an input, the state of the input is detectable by reading the state of an internal  
register. In addition, the GPIO peripheral can produce CPU interrupts and EDMA events in different  
interrupt/event generation modes. The GPIO peripheral provides generic connections to external devices.  
The GPIO pins are grouped into banks of 16 pins per bank (i.e., bank 0 consists of GPIO [0:15]).  
The device GPIO peripheral supports the following:  
•
•
Up to 144 Pins configurable as GPIO  
External Interrupt and DMA request Capability  
–
–
–
–
–
Every GPIO pin may be configured to generate an interrupt request on detection of rising and/or  
falling edges on the pin.  
The interrupt requests within each bank are combined (logical or) to create eight unique bank level  
interrupt requests.  
The bank level interrupt service routine may poll the INTSTATx register for its bank to determine  
which pin(s) have triggered the interrupt.  
GPIO Banks 0, 1, 2, 3, 4, 5, 6, 7, and 8 Interrupts assigned to DSP Events 65, 41, 49, 52, 54, 59,  
62, 72, and 75 respectively  
GPIO Banks 0, 1, 2, 3, 4, and 5 are assigned to EDMA events 6, 7, 22, 23, 28, 29, and 29  
respectively on Channel Controller 0 and GPIO Banks 6, 7, and 8 are assigned to EDMA events  
16, 17, and 18 respectively on Channel Controller 1.  
•
Set/clear functionality: Firmware writes 1 to corresponding bit position(s) to set or to clear GPIO  
signal(s). This allows multiple firmware processes to toggle GPIO output signals without critical section  
protection (disable interrupts, program GPIO, re-enable interrupts, to prevent context switching to  
anther process during GPIO programming).  
•
•
Separate Input/Output registers  
Output register in addition to set/clear so that, if preferred by firmware, some GPIO output signals can  
be toggled by direct write to the output register(s).  
•
Output register, when read, reflects output drive status. This, in addition to the input register reflecting  
pin status and open-drain I/O cell, allows wired logic be implemented.  
The memory map for the GPIO registers is shown in Table 4-133.  
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4.7.6.25.1 GPIO Register Description(s)  
Table 4-133. GPIO Registers  
BYTE ADDRESS  
0x01E2 6000  
0x01E2 6004  
0x01E2 6008  
ACRONYM  
REV  
REGISTER DESCRIPTION  
Peripheral Revision Register  
RESERVED  
BINTEN  
Reserved  
GPIO Interrupt Per-Bank Enable Register  
GPIO Banks 0 and 1  
0x01E2 6010  
0x01E2 6014  
0x01E2 6018  
0x01E2 601C  
0x01E2 6020  
0x01E2 6024  
0x01E2 6028  
0x01E2 602C  
0x01E2 6030  
0x01E2 6034  
DIR01  
GPIO Banks 0 and 1 Direction Register  
OUT_DATA01  
SET_DATA01  
CLR_DATA01  
IN_DATA01  
GPIO Banks 0 and 1 Output Data Register  
GPIO Banks 0 and 1 Set Data Register  
GPIO Banks 0 and 1 Clear Data Register  
GPIO Banks 0 and 1 Input Data Register  
GPIO Banks 0 and 1 Set Rising Edge Interrupt Register  
GPIO Banks 0 and 1 Clear Rising Edge Interrupt Register  
GPIO Banks 0 and 1 Set Falling Edge Interrupt Register  
GPIO Banks 0 and 1 Clear Falling Edge Interrupt Register  
GPIO Banks 0 and 1 Interrupt Status Register  
GPIO Banks 2 and 3  
SET_RIS_TRIG01  
CLR_RIS_TRIG01  
SET_FAL_TRIG01  
CLR_FAL_TRIG01  
INTSTAT01  
0x01E2 6038  
0x01E2 603C  
0x01E2 6040  
0x01E2 6044  
0x01E2 6048  
0x01E2 604C  
0x01E2 6050  
0x01E2 6054  
0x01E2 6058  
0x01E2 605C  
DIR23  
GPIO Banks 2 and 3 Direction Register  
OUT_DATA23  
SET_DATA23  
CLR_DATA23  
IN_DATA23  
GPIO Banks 2 and 3 Output Data Register  
GPIO Banks 2 and 3 Set Data Register  
GPIO Banks 2 and 3 Clear Data Register  
GPIO Banks 2 and 3 Input Data Register  
GPIO Banks 2 and 3 Set Rising Edge Interrupt Register  
GPIO Banks 2 and 3 Clear Rising Edge Interrupt Register  
GPIO Banks 2 and 3 Set Falling Edge Interrupt Register  
GPIO Banks 2 and 3 Clear Falling Edge Interrupt Register  
GPIO Banks 2 and 3 Interrupt Status Register  
GPIO Banks 4 and 5  
SET_RIS_TRIG23  
CLR_RIS_TRIG23  
SET_FAL_TRIG23  
CLR_FAL_TRIG23  
INTSTAT23  
0x01E2 6060  
0x01E2 6064  
0x01E2 6068  
0x01E2 606C  
0x01E2 6070  
0x01E2 6074  
0x01E2 6078  
0x01E2 607C  
0x01E2 6080  
0x01E2 6084  
DIR45  
GPIO Banks 4 and 5 Direction Register  
OUT_DATA45  
SET_DATA45  
CLR_DATA45  
IN_DATA45  
GPIO Banks 4 and 5 Output Data Register  
GPIO Banks 4 and 5 Set Data Register  
GPIO Banks 4 and 5 Clear Data Register  
GPIO Banks 4 and 5 Input Data Register  
GPIO Banks 4 and 5 Set Rising Edge Interrupt Register  
GPIO Banks 4 and 5 Clear Rising Edge Interrupt Register  
GPIO Banks 4 and 5 Set Falling Edge Interrupt Register  
GPIO Banks 4 and 5 Clear Falling Edge Interrupt Register  
GPIO Banks 4 and 5 Interrupt Status Register  
SET_RIS_TRIG45  
CLR_RIS_TRIG45  
SET_FAL_TRIG45  
CLR_FAL_TRIG45  
INTSTAT45  
226  
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Table 4-133. GPIO Registers (continued)  
BYTE ADDRESS  
ACRONYM  
REGISTER DESCRIPTION  
GPIO Banks 6 and 7  
0x01E2 6088  
0x01E2 608C  
0x01E2 6090  
0x01E2 6094  
0x01E2 6098  
0x01E2 609C  
0x01E2 60A0  
0x01E2 60A4  
0x01E2 60A8  
0x01E2 60AC  
DIR67  
GPIO Banks 6 and 7 Direction Register  
GPIO Banks 6 and 7 Output Data Register  
GPIO Banks 6 and 7 Set Data Register  
GPIO Banks 6 and 7 Clear Data Register  
GPIO Banks 6 and 7 Input Data Register  
GPIO Banks 6 and 7 Set Rising Edge Interrupt Register  
GPIO Banks 6 and 7 Clear Rising Edge Interrupt Register  
GPIO Banks 6 and 7 Set Falling Edge Interrupt Register  
GPIO Banks 6 and 7 Clear Falling Edge Interrupt Register  
GPIO Banks 6 and 7 Interrupt Status Register  
GPIO Bank 8  
OUT_DATA67  
SET_DATA67  
CLR_DATA67  
IN_DATA67  
SET_RIS_TRIG67  
CLR_RIS_TRIG67  
SET_FAL_TRIG67  
CLR_FAL_TRIG67  
INTSTAT67  
0x01E2 60B0  
0x01E2 60B4  
0x01E2 60B8  
0x01E2 60BC  
0x01E2 60C0  
0x01E2 60C4  
0x01E2 60C8  
0x01E2 60CC  
0x01E2 60D0  
0x01E2 60D4  
DIR8  
GPIO Bank 8 Direction Register  
OUT_DATA8  
SET_DATA8  
GPIO Bank 8 Output Data Register  
GPIO Bank 8 Set Data Register  
CLR_DATA8  
IN_DATA8  
GPIO Bank 8 Clear Data Register  
GPIO Bank 8 Input Data Register  
SET_RIS_TRIG8  
CLR_RIS_TRIG8  
SET_FAL_TRIG8  
CLR_FAL_TRIG8  
INTSTAT8  
GPIO Bank 8 Set Rising Edge Interrupt Register  
GPIO Bank 8 Clear Rising Edge Interrupt Register  
GPIO Bank 8 Set Falling Edge Interrupt Register  
GPIO Bank 8 Clear Falling Edge Interrupt Register  
GPIO Bank 8 Interrupt Status Register  
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4.7.6.25.2 GPIO Peripheral Input/Output Electrical Data/Timing  
Table 4-134. Timing Requirements for GPIO Inputs(1) (see Figure 4-87)  
1.3V, 1.2V, 1.1V, 1.0V  
NO.  
UNIT  
MIN  
MAX  
1
2
tw(GPIH)  
tw(GPIL)  
Pulse duration, GPn[m] as input high  
Pulse duration, GPn[m] as input low  
2C(1) (2)  
2C(1) (2)  
ns  
ns  
(1) The pulse width given is sufficient to generate a CPU interrupt or an EDMA event. However, if a user wants to have the device  
recognize the GPIx changes through software polling of the GPIO register, the GPIx duration must be extended to allow the device  
enough time to access the GPIO register through the internal bus.  
(2) C=SYSCLK4 period in ns.  
Table 4-135. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs  
(see Figure 4-87)  
1.3V, 1.2V, 1.1V, 1.0V  
NO.  
PARAMETER  
UNIT  
MIN  
MAX  
3
4
tw(GPOH)  
tw(GPOL)  
Pulse duration, GPn[m] as output high  
Pulse duration, GPn[m] as output low  
2C(1) (2)  
2C(1) (2)  
ns  
ns  
(1) This parameter value should not be used as a maximum performance specification. Actual performance of back-to-back accesses of the  
GPIO is dependent upon internal bus activity.  
(2) C=SYSCLK4 period in ns.  
2
1
GPn[m]  
as input  
4
3
GPn[m]  
as output  
Figure 4-87. GPIO Port Timing  
4.7.6.25.3 GPIO Peripheral External Interrupts Electrical Data/Timing  
Table 4-136. Timing Requirements for External Interrupts(1) (see Figure 4-88)  
1.3V, 1.2V, 1.1V, 1.0V  
NO.  
UNIT  
MIN  
MAX  
1
2
tw(ILOW)  
tw(IHIGH)  
Width of the external interrupt pulse low  
Width of the external interrupt pulse high  
2C(1) (2)  
2C(1) (2)  
ns  
ns  
(1) The pulse width given is sufficient to generate an interrupt or an EDMA event. However, if a user wants to have the device recognize the  
GPIO changes through software polling of the GPIO register, the GPIO duration must be extended to allow the device enough time to  
access the GPIO register through the internal bus.  
(2) C=SYSCLK4 period in ns.  
2
1
GPn[m]  
as input  
Figure 4-88. GPIO External Interrupt Timing  
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4.7.6.26 Programmable Real-Time Unit Subsystem (PRUSS)  
The Programmable Real-Time Unit Subsystem (PRUSS) consists of  
•
•
Two Programmable Real-Time Units (PRU0 and PRU1) and their associated memories  
An Interrupt Controller (INTC) for handling system interrupt events. The INTC also supports posting  
events back to the device level host CPU.  
•
A Switched Central Resource (SCR) for connecting the various internal and external masters to the  
resources inside the PRUSS.  
The two PRUs can operate completely independently or in coordination with each other. The PRUs can  
also work in coordination with the device level host CPU. This is determined by the nature of the program  
which is loaded into the PRUs instruction memory. Several different signaling mechanisms are available  
between the two PRUs and the device level host CPU.  
The PRUs are optimized for performing embedded tasks that require manipulation of packed memory  
mapped data structures, handling of system events that have tight realtime constraints and interfacing with  
systems external to the device.  
The PRUSS comprises various distinct addressable regions. Externally the subsystem presents a single  
64Kbyte range of addresses. The internal interconnect bus (also called switched central resource, or SCR)  
of the PRUSS decodes accesses for each of the individual regions. The PRUSS memory map is  
documented in Table 4-137 and in Table 4-138. Note that these two memory maps are implemented  
inside the PRUSS and are local to the components of the PRUSS.  
Table 4-137. Programmable Real-Time Unit Subsystem (PRUSS) Local Instruction Space Memory Map  
BYTE ADDRESS  
PRU0  
PRU1  
0x0000 0000 - 0x0000 0FFF  
PRU0 Instruction RAM  
PRU1 Instruction RAM  
Table 4-138. Programmable Real-Time Unit Subsystem (PRUSS) Local Data Space Memory Map  
BYTE ADDRESS  
PRU0  
Data RAM 0(1)  
Reserved  
PRU1  
Data RAM 1(1)  
Reserved  
0x0000 0000 - 0x0000 01FF  
0x0000 0200 - 0x0000 1FFF  
0x0000 2000 - 0x0000 21FF  
0x0000 2200 - 0x0000 3FFF  
0x0000 4000 - 0x0000 6FFF  
0x0000 7000 - 0x0000 73FF  
0x0000 7400 - 0x0000 77FF  
0x0000 7800 - 0x0000 7BFF  
0x0000 7C00 - 0xFFFF FFFF  
Data RAM 1(1)  
Data RAM 0(1)  
Reserved  
Reserved  
INTC Registers  
PRU0 Control Registers  
Reserved  
INTC Registers  
PRU0 Control Registers  
Reserved  
PRU1 Control Registers  
Reserved  
PRU1 Control Registers  
Reserved  
(1) Note that PRU0 accesses Data RAM0 at address 0x0000 0000, also PRU1 accesses Data RAM1 at address 0x0000 0000. Data RAM0  
is intended to be the primary data memory for PRU0 and Data RAM1 is intended to be the primary data memory for PRU1. However for  
passing information between PRUs, each PRU can access the data ram of the ‘other’ PRU through address 0x0000 2000.  
The global view of the PRUSS internal memories and control ports is documented in Table 4-139. The  
offset addresses of each region are implemented inside the PRUSS but the global device memory  
mapping places the PRUSS slave port in the address range 0x01C3 0000-0x01C3 FFFF. The PRU0 and  
PRU1 can use either the local or global addresses to access their internal memories, but using the local  
addresses will provide access time several cycles faster than using the global addresses. This is because  
when accessing via the global address the access needs to be routed through the switch fabric outside  
PRUSS and back in through the PRUSS slave port.  
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Table 4-139. Programmable Real-Time Unit Subsystem (PRUSS) Global Memory Map  
BYTE ADDRESS  
REGION  
Data RAM 0  
0x01C3 0000 - 0x01C3 01FF  
0x01C3 0200 - 0x01C3 1FFF  
0x01C3 2000 - 0x01C3 21FF  
0x01C3 2200 - 0x01C3 3FFF  
0x01C3 4000 - 0x01C3 6FFF  
0x01C3 7000 - 0x01C3 73FF  
0x01C3 7400 - 0x01C3 77FF  
0x01C3 7800 - 0x01C3 7BFF  
0x01C3 7C00 - 0x01C3 7FFF  
0x01C3 8000 - 0x01C3 8FFF  
0x01C3 9000 - 0x01C3 BFFF  
0x01C3 C000 - 0x01C3 CFFF  
0x01C3 D000 - 0x01C3 FFFF  
Reserved  
Data RAM 1  
Reserved  
INTC Registers  
PRU0 Control Registers  
PRU0 Debug Registers  
PRU1 Control Registers  
PRU1 Debug Registers  
PRU0 Instruction RAM  
Reserved  
PRU1 Instruction RAM  
Reserved  
Each of the PRUs can access the rest of the device memory (including memory mapped peripheral and  
configuration registers) using the global memory space addresses  
4.7.6.26.1 PRUSS Register Descriptions  
Table 4-140. Programmable Real-Time Unit Subsystem (PRUSS) Control / Status Registers  
PRU0 BYTE ADDRESS  
0x01C3 7000  
0x01C3 7004  
0x01C3 7008  
0x01C3 700C  
0x01C3 7010  
0x01C3 7020  
0x01C3 7028  
0x01C3 702C  
PRU1 BYTE ADDRESS  
0x01C3 7800  
0x01C3 7804  
0x01C3 7808  
0x01C3 780C  
0x01C3 7810  
0x01C3 7820  
0x01C3 7828  
0x01C3 782C  
ACRONYM  
CONTROL  
REGISTER DESCRIPTION  
PRU Control Register  
STATUS  
PRU Status Register  
WAKEUP  
PRU Wakeup Enable Register  
CYCLCNT  
PRU Cycle Count  
STALLCNT  
PRU Stall Count  
CONTABBLKIDX0  
CONTABPROPTR0  
CONTABPROPTR1  
PRU Constant Table Block Index Register 0  
PRU Constant Table Programmable Pointer Register 0  
PRU Constant Table Programmable Pointer Register 1  
0x01C37400 -  
0x01C3747C  
0x01C3 7C00 -  
0x01C3 7C7C  
INTGPR0 – INTGPR31  
PRU Internal General Purpose Register 0 (for Debug)  
0x01C37480 -  
0x01C374FC  
0x01C3 7C80 -  
0x01C3 7CFC  
INTCTER0 – INTCTER31 PRU Internal General Purpose Register 0 (for Debug)  
Table 4-141. Programmable Real-Time Unit Subsystem Interrupt Controller (PRUSS INTC) Registers  
BYTE ADDRESS  
0x01C3 4000  
0x01C3 4004  
0x01C3 4010  
0x01C3 401C  
0x01C3 4020  
0x01C3 4024  
0x01C3 4028  
0x01C3 402C  
0x01C3 4034  
0x01C3 4038  
0x01C3 4080  
0x01C3 4200  
ACRONYM  
REVID  
REGISTER DESCRIPTION  
Revision ID Register  
CONTROL  
Control Register  
GLBLEN  
Global Enable Register  
GLBLNSTLVL  
STATIDXSET  
STATIDXCLR  
ENIDXSET  
Global Nesting Level Register  
System Interrupt Status Indexed Set Register  
System Interrupt Status Indexed Clear Register  
System Interrupt Enable Indexed Set Register  
System Interrupt Enable Indexed Clear Register  
Host Interrupt Enable Indexed Set Register  
Host Interrupt Enable Indexed Clear Register  
Global Prioritized Index Register  
ENIDXCLR  
HSTINTENIDXSET  
HSTINTENIDXCLR  
GLBLPRIIDX  
STATSETINT0  
System Interrupt Status Raw/Set Register 0  
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Table 4-141. Programmable Real-Time Unit Subsystem Interrupt Controller (PRUSS INTC)  
Registers (continued)  
BYTE ADDRESS  
0x01C3 4204  
ACRONYM  
REGISTER DESCRIPTION  
System Interrupt Status Raw/Set Register 1  
System Interrupt Status Enabled/Clear Register 0  
System Interrupt Status Enabled/Clear Register 1  
System Interrupt Enable Set Register 0  
System Interrupt Enable Set Register 1  
System Interrupt Enable Clear Register 0  
System Interrupt Enable Clear Register 1  
Channel Map Registers 0-15  
STATSETINT1  
STATCLRINT0  
0x01C3 4280  
0x01C3 4284  
STATCLRINT1  
0x01C3 4300  
ENABLESET0  
0x01C3 4304  
ENABLESET1  
0x01C3 4380  
ENABLECLR0  
0x01C3 4384  
ENABLECLR1  
0x01C3 4400 - 0x01C3 4440  
0x01C3 4800 - 0x01C3 4808  
CHANMAP0 - CHANMAP15  
HOSTMAP0 - HOSTMAP2  
Host Map Register 0-2  
HOSTINTPRIIDX0 -  
HOSTINTPRIIDX9  
0x01C3 4900 - 0x01C3 4928  
Host Interrupt Prioritized Index Registers 0-9  
0x01C3 4D00  
0x01C3 4D04  
0x01C3 4D80  
0x01C3 4D84  
POLARITY0  
POLARITY1  
TYPE0  
System Interrupt Polarity Register 0  
System Interrupt Polarity Register 1  
System Interrupt Type Register 0  
System Interrupt Type Register 1  
TYPE1  
HOSTINTNSTLVL0-  
HOSTINTNSTLVL9  
0x01C3 5100 - 0x01C3 5128  
0x01C3 5500  
Host Interrupt Nesting Level Registers 0-9  
Host Interrupt Enable Register  
HOSTINTEN  
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4.7.7 Emulation and Debug  
The debug capabilities and features for DSP are as shown below.  
DSP:  
•
•
•
Basic Debug  
–
–
Execution Control  
System Visibility  
Real-Time Debug  
–
–
Interrupts serviced while halted  
Low/non-intrusive system visibility while running  
Advanced Debug  
–
–
–
–
Global Start  
Global Stop  
Specify targeted memory level(s) during memory accesses  
HSRTDX (High Speed Real Time Data eXchange)  
•
•
Advanced System Control  
–
–
–
Subsystem reset via debug  
Peripheral notification of debug events  
Cache-coherent debug accesses  
Analysis Actions  
–
–
–
–
–
–
Stop program execution  
Generate debug interrupt  
Benchmarking with counters  
External trigger generation  
Debug state machine state transition  
Combinational and Sequential event generation  
•
•
Analysis Events  
–
–
–
–
–
Program event detection  
Data event detection  
External trigger Detection  
System event detection (i.e. cache miss)  
Debug state machine state detection  
Analysis Configuration  
–
–
Application access  
Debugger access  
Table 4-142. DSP Debug Features  
Category  
Hardware Feature  
Availability  
Software breakpoint  
Unlimited  
Up to 10 HWBPs, including:  
Basic Debug  
4 precise(1) HWBPs inside DSP core and one of them is associated with a counter.  
2 imprecise(1) HWBPs from AET.  
Hardware breakpoint  
4 imprecise(1) HWBPs from AET which are shared for watch point.  
(1) Precise hardware breakpoints will halt the processor immediately prior to the execution of the selected instruction. Imprecise breakpoints  
will halt the processor some number of cycles after the selected instruction depending on device conditions.  
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Table 4-142. DSP Debug Features (continued)  
Hardware Feature  
Availability  
Up to 4 watch points, which are shared with HWBPs, and can also be used as 2 watch  
points with data (32 bits)  
Watch point  
Watch point with Data  
Counters/timers  
Up to 2, Which can also be used as 4 watch points.  
Analysis  
1x64-bits (cycle only) + 2x32-bits (water mark counters)  
External Event Trigger In  
External Event Trigger Out  
1
1
4.7.7.1 JTAG Port Description  
The device target debug interface uses the five standard IEEE 1149.1(JTAG) signals (TRST, TCK, TMS,  
TDI, and TDO).  
TRST holds the debug and boundary scan logic in reset (normal DSP operation) when pulled low (its  
default state). Since TRST has an internal pull-down resistor, this ensures that at power up the device  
functions in its normal (non-test) operation mode if TRST is not connected. Otherwise, TRST should be  
driven inactive by the emulator or boundary scan controller. Boundary scan test cannot be performed  
while the TRST pin is pulled low.  
Table 4-143. JTAG Port Description  
PIN  
TYPE  
NAME  
DESCRIPTION  
When asserted (active low) causes all test and debug logic in the device to be reset  
along with the IEEE 1149.1 interface  
TRST  
I
Test Logic Reset  
TCK  
TMS  
TDI  
I
I
Test Clock  
Test Mode Select  
Test Data Input  
Test Data Output  
Emulation 0  
This is the test clock used to drive an IEEE 1149.1 TAP state machine and logic.  
Directs the next state of the IEEE 1149.1 test access port state machine  
Scan data input to the device  
I
TDO  
EMU0  
EMU1  
O
I/O  
I/O  
Scan data output of the device  
Channel 0 trigger + HSRTDX  
Emulation 1  
Channel 1 trigger + HSRTDX  
4.7.7.2 Scan Chain Configuration Parameters  
Table 4-144 shows the TAP configuration details required to configure the router/emulator for this device.  
Table 4-144. JTAG Port Description  
Router Port ID  
Default TAP  
TAP Name  
C674x  
Tap IR Length  
17  
19  
No  
No  
38  
4
ETB  
The router is revision C and has a 6-bit IR length.  
4.7.7.3 Initial Scan Chain Configuration  
The first level of debug interface that sees the scan controller is the TAP router module. The debugger  
can configure the TAP router for serially linking up to 16 TAP controllers or individually scanning one of  
the TAP controllers without disrupting the IR state of the other TAPs.  
4.7.7.4 IEEE 1149.1 JTAG  
The JTAG (1) interface is used for BSDL testing and emulation of the device.  
The device requires that both TRST and RESET be asserted upon power up to be properly initialized.  
While RESET initializes the device, TRST initializes the device's emulation logic. Both resets are required  
for proper operation.  
(1) IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.  
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While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for  
the device to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG  
port interface and device's emulation logic in the reset state.  
TRST only needs to be released when it is necessary to use a JTAG controller to debug the device or  
exercise the device's boundary scan functionality. Note: TRST is synchronous and must be clocked by  
TCK; otherwise, the boundary scan logic may not respond as expected after TRST is asserted.  
RESET must be released only in order for boundary-scan JTAG to read the variant field of IDCODE  
correctly. Other boundary-scan instructions work correctly independent of current state of RESET.  
For maximum reliability, the device includes an internal pulldown (IPD) on the TRST pin to ensure that  
TRST will always be asserted upon power up and the device's internal emulation logic will always be  
properly initialized.  
JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG  
controllers may not drive TRST high but expect the use of a pullup resistor on TRST.  
When using this type of JTAG controller, assert TRST to initialize the device after powerup and externally  
drive TRST high before attempting any emulation or boundary scan operations.  
4.7.7.4.1 JTAG Peripheral Register Description(s) – JTAG ID Register (DEVIDR0)  
Table 4-145. DEVIDR0 Register  
BYTE ADDRESS  
ACRONYM  
REGISTER DESCRIPTION  
JTAG Identification Register  
COMMENTS  
Read-only. Provides 32-bit  
JTAG ID of the device.  
0x01C1 4018  
DEVIDR0  
The JTAG ID register is a read-only register that identifies the JTAG/Device ID. For the device, the JTAG  
ID register resides at address location 0x01C1 4018. The register hex value for each silicon revision is:  
•
•
0x0B7D 102F for silicon revision 1.x  
0x1B7D 102F for silicon revision 2.x  
For the actual register bit names and their associated bit field descriptions, see Figure 4-89 and Table 4-  
146.  
Figure 4-89. JTAG ID (DEVIDR0) Register Description - Register Value  
31-28  
VARIANT (4-Bit)  
R-xxxx  
27-12  
11-1  
0
PART NUMBER (16-Bit)  
R-1011 0111 1101 0001  
MANUFACTURER (11-Bit)  
R-0000 0010 111  
LSB  
R-1  
LEGEND: R = Read, W = Write, n = value at reset  
Table 4-146. JTAG ID Register Selection Bit Descriptions  
BIT  
31:28  
27:12  
11-1  
0
NAME  
VARIANT  
DESCRIPTION  
Variant (4-Bit) value  
PART NUMBER  
Part Number (16-Bit) value  
MANUFACTURER Manufacturer (11-Bit) value  
LSB LSB. This bit is read as a "1".  
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4.7.7.4.2 JTAG Test-Port Electrical Data/Timing  
Table 4-147. Timing Requirements for JTAG Test Port (see Figure 4-90)  
1.3V, 1.2V  
1.1V  
MIN MAX  
1.0V  
MIN MAX  
No.  
UNIT  
MIN  
40  
16  
16  
4
MAX  
1
2
3
4
5
tc(TCK)  
Cycle time, TCK  
50  
20  
20  
4
66.6  
26.6  
26.6  
4
ns  
ns  
ns  
ns  
ns  
tw(TCKH)  
Pulse duration, TCK high  
tw(TCKL)  
Pulse duration, TCK low  
tsu(TDIV-TCKH)  
Setup time, TDI/TMS/TRST valid before TCK high  
th(TCLKH-TDIV) Hold time, TDI/TMS/TRST valid after TCK high  
4
6
8
Table 4-148. Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port  
(see Figure 4-90)  
1.3V, 1.2V  
1.1V  
MIN MAX  
23  
1.0V  
MIN MAX  
31  
No.  
PARAMETER  
UNIT  
MIN  
MAX  
6
td(TCKL-TDOV)  
Delay time, TCK low to TDO valid  
18  
ns  
1
3
TCK  
2
6
6
TDO  
5
4
TDI/TMS/TRST  
Figure 4-90. JTAG Test-Port Timing  
4.7.7.5 JTAG 1149.1 Boundary Scan Considerations  
To use boundary scan, the following sequence should be followed:  
•
•
•
Execute a valid reset sequence and exit reset  
Wait at least 6000 OSCIN clock cycles  
Enter boundary scan mode using the JTAG pins  
No specific value is required on the EMU0 and EMU1 pins for boundary scan testing. If TRST is not driven  
by the boundary scan tool or tester, TRST should be externally pulled high during boundary scan testing.  
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5 Detailed Description  
5.1 Device Overview  
Table 5-1 provides an overview of the device. The table shows significant features of the device, including  
the capacity of on-chip RAM, peripherals, and the package type with pin count.  
Table 5-1. Characteristics of C6748  
HARDWARE FEATURES  
C6748  
DDR2, 16-bit bus width, up to 156 MHz  
Mobile DDR, 16-bit bus width, up to 150 MHz  
DDR2/mDDR Memory Controller  
Asynchronous (8/16-bit bus width) RAM, Flash,  
16-bit SDRAM, NOR, NAND  
EMIFA  
Flash Card Interface  
EDMA3  
2 MMC and SD cards supported  
64 independent channels, 16 QDMA channels,  
2 channel controllers, 3 transfer controllers  
4 64-Bit General Purpose (each configurable as 2 separate  
32-bit timers, one configurable as Watch Dog)  
Timers  
UART  
3 (each with RTS and CTS flow control)  
2 (Each with one hardware chip select)  
2 (both Master/Slave)  
SPI  
I2C  
Peripherals  
Multichannel Audio Serial Port [McASP]  
Multichannel Buffered Serial Port [McBSP]  
10/100 Ethernet MAC with Management Data I/O  
1 (each with transmit/receive, FIFO buffer, 16 serializers)  
2 (each with transmit/receive, FIFO buffer, 16)  
1 (MII or RMII Interface)  
Not all peripherals pins  
are available at the  
same time (for more  
detail, see the Device  
Configurations section).  
4 Single Edge, 4 Dual Edge Symmetric, or  
2 Dual Edge Asymmetric Outputs  
eHRPWM  
eCAP  
3 32-bit capture inputs or 3 32-bit auxiliary PWM outputs  
1 (16-bit multiplexed address/data)  
High-Speed OTG Controller with on-chip OTG PHY  
Full-Speed OHCI (as host) with on-chip PHY  
9 banks of 16-bit  
UHPI  
USB 2.0 (USB0)  
USB 1.1 (USB1)  
General-Purpose Input/Output Port  
LCD Controller  
1
SATA Controller  
1 (Supports both SATA I and SATAII)  
1
Universal Parallel Port (uPP)  
Video Port Interface (VPIF)  
PRU Subsystem (PRUSS)  
Size (Bytes)  
1 (video in and video out)  
2 Programmable PRU Cores  
448KB RAM  
DSP  
32KB L1 Program (L1P)/Cache (up to 32KB)  
32KB L1 Data (L1D)/Cache (up to 32KB)  
256KB Unified Mapped RAM/Cache (L2)  
DSP Memories can be made accessible to EDMA3 and  
other peripherals.  
On-Chip Memory  
Organization  
ADDITIONAL MEMORY  
128KB RAM  
Security  
Secure Boot  
TI Basic Secure Boot  
C674x CPU ID + CPU  
Rev ID  
Control Status Register (CSR.[31:16])  
0x1400  
C674x Megamodule  
Revision  
Revision ID Register (MM_REVID[15:0])  
0x0000  
JTAG BSDL_ID  
CPU Frequency  
DEVIDR0 Register  
MHz  
see Section 4.7.7.4.1, JTAG Peripheral Register Description  
674x DSP 375 MHz (1.2 V)  
Core (V)  
Variable (1.2 V - 1 V) for 375 MHz version  
1.8 V or 3.3 V  
Voltage  
I/O (V)  
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Table 5-1. Characteristics of C6748 (continued)  
HARDWARE FEATURES  
C6748  
Packages  
16 mm x 16 mm, 361-Ball 0.80 mm pitch, PBGA (GWT)  
Product Preview (PP),  
Advance Information (AI),  
or Production Data (PD)  
Product Status(1)  
375 MHz versions - PD  
(1) ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and  
other specifications are subject to change without notice. PRODUCTION DATA information is current as of publication date. Products  
conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include  
testing of all parameters.  
5.2 Device Compatibility  
The C674x DSP core is code-compatible with the C6000™ DSP platform and supports features of both  
the C64x+ and C67x+ DSP families.  
5.3 DSP Subsystem  
The DSP Subsystem includes the following features:  
•
•
•
•
•
•
C674x DSP CPU  
32KB L1 Program (L1P)/Cache (up to 32KB)  
32KB L1 Data (L1D)/Cache (up to 32KB)  
256KB Unified Mapped RAM/Cache (L2)  
Boot ROM (cannot be used for application code)  
Little endian  
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32K Bytes  
L1P RAM/  
Cache  
BOOT  
ROM  
256K Bytes  
L2 RAM  
256  
256  
256  
256  
Cache Control  
Memory Protect  
Bandwidth Mgmt  
Cache Control  
L1P  
Memory Protect  
Bandwidth Mgmt  
L2  
256  
256  
Power Down  
256  
256  
Instruction Fetch  
C674x  
Fixed/Floating Point CPU  
Interrupt  
Controller  
IDMA  
256  
Register  
File A  
Register  
File B  
64  
64  
CFG  
Bandwidth Mgmt  
Memory Protect  
Cache Control  
EMC  
Configuration  
Peripherals  
Bus  
32  
L1D  
MDMA  
SDMA  
8 x 32  
64  
64  
64  
64  
32K Bytes  
L1D RAM/  
Cache  
High  
Performance  
Switch Fabric  
Figure 5-1. C674x Megamodule Block Diagram  
5.3.1 C674x DSP CPU Description  
The C674x Central Processing Unit (CPU) consists of eight functional units, two register files, and two  
data paths as shown in Figure 5-2. The two general-purpose register files (A and B) each contain 32 32-  
bit registers for a total of 64 registers. The general-purpose registers can be used for data or can be data  
address pointers. The data types supported include packed 8-bit data, packed 16-bit data, 32-bit data, 40-  
bit data, and 64-bit data. Values larger than 32 bits, such as 40-bit-long or 64-bit-long values are stored in  
register pairs, with the 32 LSBs of data placed in an even register and the remaining 8 or 32 MSBs in the  
next upper register (which is always an odd-numbered register).  
The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one  
instruction every clock cycle. The .M functional units perform all multiply operations. The .S and .L units  
perform a general set of arithmetic, logical, and branch functions. The .D units primarily load data from  
memory to the register file and store results from the register file into memory.  
The C674x CPU combines the performance of the C64x+ core with the floating-point capabilities of the  
C67x+ core.  
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Each C674x .M unit can perform one of the following each clock cycle: one 32 x 32 bit multiply, one 16 x  
32 bit multiply, two 16 x 16 bit multiplies, two 16 x 32 bit multiplies, two 16 x 16 bit multiplies with  
add/subtract capabilities, four 8 x 8 bit multiplies, four 8 x 8 bit multiplies with add operations, and four  
16 x 16 multiplies with add/subtract capabilities (including a complex multiply). There is also support for  
Galois field multiplication for 8-bit and 32-bit data. Many communications algorithms such as FFTs and  
modems require complex multiplication. The complex multiply (CMPY) instruction takes for 16-bit inputs  
and produces a 32-bit real and a 32-bit imaginary output. There are also complex multiplies with rounding  
capability that produces one 32-bit packed output that contain 16-bit real and 16-bit imaginary values. The  
32 x 32 bit multiply instructions provide the extended precision necessary for high-precision algorithms on  
a variety of signed and unsigned 32-bit data types.  
The .L or (Arithmetic Logic Unit) now incorporates the ability to do parallel add/subtract operations on a  
pair of common inputs. Versions of this instruction exist to work on 32-bit data or on pairs of 16-bit data  
performing dual 16-bit add and subtracts in parallel. There are also saturated forms of these instructions.  
The C674x core enhances the .S unit in several ways. On the previous cores, dual 16-bit MIN2 and MAX2  
comparisons were only available on the .L units. On the C674x core they are also available on the .S unit  
which increases the performance of algorithms that do searching and sorting. Finally, to increase data  
packing and unpacking throughput, the .S unit allows sustained high performance for the quad 8-bit/16-bit  
and dual 16-bit instructions. Unpack instructions prepare 8-bit data for parallel 16-bit operations. Pack  
instructions return parallel results to output precision including saturation support.  
Other new features include:  
•
SPLOOP - A small instruction buffer in the CPU that aids in creation of software pipelining loops where  
multiple iterations of a loop are executed in parallel. The SPLOOP buffer reduces the code size  
associated with software pipelining. Furthermore, loops in the SPLOOP buffer are fully interruptible.  
•
Compact Instructions - The native instruction size for the C6000 devices is 32 bits. Many common  
instructions such as MPY, AND, OR, ADD, and SUB can be expressed as 16 bits if the C674x  
compiler can restrict the code to use certain registers in the register file. This compression is  
performed by the code generation tools.  
•
•
•
•
Instruction Set Enhancement - As noted above, there are new instructions such as 32-bit  
multiplications, complex multiplications, packing, sorting, bit manipulation, and 32-bit Galois field  
multiplication.  
Exceptions Handling - Intended to aid the programmer in isolating bugs. The C674x CPU is able to  
detect and respond to exceptions, both from internally detected sources (such as illegal op-codes) and  
from system events (such as a watchdog time expiration).  
Privilege - Defines user and supervisor modes of operation, allowing the operating system to give a  
basic level of protection to sensitive resources. Local memory is divided into multiple pages, each with  
read, write, and execute permissions.  
Time-Stamp Counter - Primarily targeted for Real-Time Operating System (RTOS) robustness, a free-  
running time-stamp counter is implemented in the CPU which is not sensitive to system stalls.  
For more details on the C674x CPU and its enhancements over the C64x architecture, see the following  
documents:  
•
•
TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRUFE8)  
TMS320C64x Technical Overview (literature number SPRU395)  
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Even  
register  
file A  
(A0, A2,  
A4...A30)  
src1  
src2  
Odd  
register  
file A  
(A1, A3,  
A5...A31)  
.L1  
odd dst  
even dst  
long src  
(D)  
8
32 MSB  
32 LSB  
ST1b  
ST1a  
8
long src  
even dst  
odd dst  
src1  
(D)  
Data path A  
.S1  
src2  
32  
32  
(A)  
(B)  
dst2  
dst1  
src1  
.M1  
src2  
(C)  
32 MSB  
32 LSB  
LD1b  
LD1a  
dst  
src1  
src2  
.D1  
.D2  
DA1  
2x  
1x  
Even  
register  
file B  
(B0, B2,  
B4...B30)  
Odd  
register  
file B  
(B1, B3,  
B5...B31)  
src2  
DA2  
src1  
dst  
32 LSB  
LD2a  
LD2b  
32 MSB  
src2  
(C)  
.M2  
src1  
dst2  
32  
32  
(B)  
(A)  
dst1  
src2  
src1  
.S2  
odd dst  
even dst  
long src  
(D)  
Data path B  
8
8
32 MSB  
32 LSB  
ST2a  
ST2b  
long src  
even dst  
(D)  
odd dst  
.L2  
src2  
src1  
Control Register  
A. On .M unit, dst2 is 32 MSB.  
B. On .M unit, dst1 is 32 LSB.  
C. On C64x CPU .M unit, src2 is 32 bits; on C64x+ CPU .M unit, src2 is 64 bits.  
D. On .L and .S units, odd dst connects to odd register files and even dst connects to even register files.  
Figure 5-2. TMS320C674x CPU (DSP Core) Data Paths  
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5.3.2 DSP Memory Mapping  
The DSP memory map is shown in Section 5.4.  
By default the DSP also has access to most on and off chip memory areas.  
Additionally, the DSP megamodule includes the capability to limit access to its internal memories through  
its SDMA port; without needing an external MPU unit.  
5.3.2.1 External Memories  
The DSP has access to the following External memories:  
•
•
Asynchronous EMIF / SDRAM / NAND / NOR Flash (EMIFA)  
SDRAM (DDR2)  
5.3.2.2 DSP Internal Memories  
The DSP has access to the following DSP memories:  
•
•
•
L2 RAM  
L1P RAM  
L1D RAM  
5.3.2.3 C674x CPU  
The C674x core uses a two-level cache-based architecture. The Level 1 Program cache (L1P) is 32 KB  
direct mapped cache and the Level 1 Data cache (L1D) is 32 KB 2-way set associated cache. The Level 2  
memory/cache (L2) consists of a 256 KB memory space that is shared between program and data space.  
L2 memory can be configured as mapped memory, cache, or a combination of both.  
Table 5-2 shows a memory map of the C674x CPU cache registers for the device.  
Table 5-2. C674x Cache Registers  
Byte Address  
0x0184 0000  
Register Name  
L2CFG  
Register Description  
L2 Cache configuration register  
0x0184 0020  
L1PCFG  
L1PCC  
L1P Size Cache configuration register  
L1P Freeze Mode Cache configuration register  
L1D Size Cache configuration register  
L1D Freeze Mode Cache configuration register  
Reserved  
0x0184 0024  
0x0184 0040  
L1DCFG  
L1DCC  
0x0184 0044  
0x0184 0048 - 0x0184 0FFC  
0x0184 1000  
-
EDMAWEIGHT  
-
L2 EDMA access control register  
Reserved  
0x0184 1004 - 0x0184 1FFC  
0x0184 2000  
L2ALLOC0  
L2ALLOC1  
L2ALLOC2  
L2ALLOC3  
-
L2 allocation register 0  
0x0184 2004  
L2 allocation register 1  
0x0184 2008  
L2 allocation register 2  
0x0184 200C  
L2 allocation register 3  
0x0184 2010 - 0x0184 3FFF  
0x0184 4000  
Reserved  
L2WBAR  
L2WWC  
L2WIBAR  
L2WIWC  
L2IBAR  
L2 writeback base address register  
L2 writeback word count register  
L2 writeback invalidate base address register  
L2 writeback invalidate word count register  
L2 invalidate base address register  
L2 invalidate word count register  
L1P invalidate base address register  
L1P invalidate word count register  
L1D writeback invalidate base address register  
0x0184 4004  
0x0184 4010  
0x0184 4014  
0x0184 4018  
0x0184 401C  
L2IWC  
0x0184 4020  
L1PIBAR  
L1PIWC  
L1DWIBAR  
0x0184 4024  
0x0184 4030  
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Table 5-2. C674x Cache Registers (continued)  
Byte Address  
0x0184 4034  
Register Name  
L1DWIWC  
-
Register Description  
L1D writeback invalidate word count register  
Reserved  
0x0184 4038  
0x0184 4040  
L1DWBAR  
L1DWWC  
L1DIBAR  
L1DIWC  
-
L1D Block Writeback  
0x0184 4044  
L1D Block Writeback  
0x0184 4048  
L1D invalidate base address register  
L1D invalidate word count register  
Reserved  
0x0184 404C  
0x0184 4050 - 0x0184 4FFF  
0x0184 5000  
L2WB  
L2 writeback all register  
0x0184 5004  
L2WBINV  
L2INV  
L2 writeback invalidate all register  
L2 Global Invalidate without writeback  
Reserved  
0x0184 5008  
0x0184 500C - 0x0184 5027  
0x0184 5028  
-
L1PINV  
-
L1P Global Invalidate  
0x0184 502C - 0x0184 5039  
0x0184 5040  
Reserved  
L1DWB  
L1DWBINV  
L1DINV  
MAR0 - MAR63  
L1D Global Writeback  
0x0184 5044  
L1D Global Writeback with Invalidate  
L1D Global Invalidate without writeback  
Reserved 0x0000 0000 – 0x3FFF FFFF  
0x0184 5048  
0x0184 8000 – 0x0184 80FF  
Memory Attribute Registers for EMIFA SDRAM Data (CS0)  
External memory addresses 0x4000 0000 – 0x5FFF FFFF  
0x0184 8100 – 0x0184 817F  
0x0184 8180 – 0x0184 8187  
0x0184 8188 – 0x0184 818F  
0x0184 8190 – 0x0184 8197  
MAR64 – MAR95  
MAR96 - MAR97  
MAR98 – MAR99  
MAR100 – MAR101  
Memory Attribute Registers for EMIFA Async Data (CS2)  
External memory addresses 0x6000 0000 – 0x61FF FFFF  
Memory Attribute Registers for EMIFA Async Data (CS3)  
External memory addresses 0x6200 0000 – 0x63FF FFFF  
Memory Attribute Registers for EMIFA Async Data (CS4)  
External memory addresses 0x6400 0000 – 0x65FF FFFF  
Memory Attribute Registers for EMIFA Async Data (CS5)  
External memory addresses 0x6600 0000 – 0x67FF FFFF  
0x0184 8198 – 0x0184 819F  
0x0184 81A0 – 0x0184 81FF  
MAR102 – MAR103  
MAR104 – MAR127  
Reserved 0x6800 0000 – 0x7FFF FFFF  
Memory Attribute Register for RAM  
External memory addresses 0x8000 0000 – 0x8001 FFFF  
0x0184 8200  
MAR128  
Reserved 0x8002 0000 – 0x81FF FFFF  
Reserved 0x8200 0000 – 0xBFFF FFFF  
0x0184 8204 – 0x0184 82FF  
0x0184 8300 – 0x0184 837F  
0x0184 8380 – 0x0184 83FF  
MAR129 – MAR191  
MAR192 – MAR223  
MAR224 – MAR255  
Memory Attribute Registers for DDR2 Data (CS2)  
External memory addresses 0xC000 0000 – 0xDFFF FFFF  
Reserved 0xE000 0000 – 0xFFFF FFFF  
Table 5-3. C674x L1/L2 Memory Protection Registers  
HEX ADDRESS RANGE  
0x0184 A000  
REGISTER ACRONYM  
L2MPFAR  
L2MPFSR  
L2MPFCR  
-
DESCRIPTION  
L2 memory protection fault address register  
L2 memory protection fault status register  
L2 memory protection fault command register  
Reserved  
0x0184 A004  
0x0184 A008  
0x0184 A00C - 0x0184 A0FF  
0x0184 A100  
L2MPLK0  
L2MPLK1  
L2MPLK2  
L2MPLK3  
L2MPLKCMD  
L2MPLKSTAT  
-
L2 memory protection lock key bits [31:0]  
L2 memory protection lock key bits [63:32]  
L2 memory protection lock key bits [95:64]  
L2 memory protection lock key bits [127:96]  
L2 memory protection lock key command register  
L2 memory protection lock key status register  
Reserved  
0x0184 A104  
0x0184 A108  
0x0184 A10C  
0x0184 A110  
0x0184 A114  
0x0184 A118 - 0x0184 A1FF  
242  
Detailed Description  
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Table 5-3. C674x L1/L2 Memory Protection Registers (continued)  
HEX ADDRESS RANGE  
REGISTER ACRONYM  
DESCRIPTION  
L2 memory protection page attribute register 0 (controls memory address  
0x0080 0000 - 0x0080 1FFF)  
0x0184 A200  
0x0184 A204  
0x0184 A208  
0x0184 A20C  
0x0184 A210  
0x0184 A214  
0x0184 A218  
0x0184 A21C  
0x0184 A220  
0x0184 A224  
0x0184 A228  
0x0184 A22C  
0x0184 A230  
0x0184 A234  
0x0184 A238  
0x0184 A23C  
0x0184 A240  
0x0184 A244  
0x0184 A248  
0x0184 A24C  
0x0184 A250  
0x0184 A254  
0x0184 A258  
0x0184 A25C  
0x0184 A260  
0x0184 A264  
0x0184 A268  
0x0184 A26C  
L2MPPA0  
L2 memory protection page attribute register 1 (controls memory address  
0x0080 2000 - 0x0080 3FFF)  
L2MPPA1  
L2MPPA2  
L2MPPA3  
L2MPPA4  
L2MPPA5  
L2MPPA6  
L2MPPA7  
L2MPPA8  
L2MPPA9  
L2MPPA10  
L2MPPA11  
L2MPPA12  
L2MPPA13  
L2MPPA14  
L2MPPA15  
L2MPPA16  
L2MPPA17  
L2MPPA18  
L2MPPA19  
L2MPPA20  
L2MPPA21  
L2MPPA22  
L2MPPA23  
L2MPPA24  
L2MPPA25  
L2MPPA26  
L2MPPA27  
L2 memory protection page attribute register 2 (controls memory address  
0x0080 4000 - 0x0080 5FFF)  
L2 memory protection page attribute register 3 (controls memory address  
0x0080 6000 - 0x0080 7FFF)  
L2 memory protection page attribute register 4 (controls memory address  
0x0080 8000 - 0x0080 9FFF)  
L2 memory protection page attribute register 5 (controls memory address  
0x0080 A000 - 0x0080 BFFF)  
L2 memory protection page attribute register 6 (controls memory address  
0x0080 C000 - 0x0080 DFFF)  
L2 memory protection page attribute register 7 (controls memory address  
0x0080 E000 - 0x0080 FFFF)  
L2 memory protection page attribute register 8 (controls memory address  
0x0081 0000 - 0x0081 1FFF)  
L2 memory protection page attribute register 9 (controls memory address  
0x0081 2000 - 0x0081 3FFF)  
L2 memory protection page attribute register 10 (controls memory address  
0x0081 4000 - 0x0081 5FFF)  
L2 memory protection page attribute register 11 (controls memory address  
0x0081 6000 - 0x0081 7FFF)  
L2 memory protection page attribute register 12 (controls memory address  
0x0081 8000 - 0x0081 9FFF)  
L2 memory protection page attribute register 13 (controls memory address  
0x0081 A000 - 0x0081 BFFF)  
L2 memory protection page attribute register 14 (controls memory address  
0x0081 C000 - 0x0081 DFFF)  
L2 memory protection page attribute register 15 (controls memory address  
0x0081 E000 - 0x0081 FFFF)  
L2 memory protection page attribute register 16 (controls memory address  
0x0082 0000 - 0x0082 1FFF)  
L2 memory protection page attribute register 17 (controls memory address  
0x0082 2000 - 0x0082 3FFF)  
L2 memory protection page attribute register 18 (controls memory address  
0x0082 4000 - 0x0082 5FFF)  
L2 memory protection page attribute register 19 (controls memory address  
0x0082 6000 - 0x0082 7FFF)  
L2 memory protection page attribute register 20 (controls memory address  
0x0082 8000 - 0x0082 9FFF)  
L2 memory protection page attribute register 21 (controls memory address  
0x0082 A000 - 0x0082 BFFF)  
L2 memory protection page attribute register 22 (controls memory address  
0x0082 C000 - 0x0082 DFFF)  
L2 memory protection page attribute register 23 (controls memory address  
0x0082 E000 - 0x0082 FFFF)  
L2 memory protection page attribute register 24 (controls memory address  
0x0083 0000 - 0x0083 1FFF)  
L2 memory protection page attribute register 25 (controls memory address  
0x0083 2000 - 0x0083 3FFF)  
L2 memory protection page attribute register 26 (controls memory address  
0x0083 4000 - 0x0083 5FFF)  
L2 memory protection page attribute register 27 (controls memory address  
0x0083 6000 - 0x0083 7FFF)  
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Table 5-3. C674x L1/L2 Memory Protection Registers (continued)  
HEX ADDRESS RANGE  
REGISTER ACRONYM  
DESCRIPTION  
L2 memory protection page attribute register 28 (controls memory address  
0x0083 8000 - 0x0083 9FFF)  
0x0184 A270  
L2MPPA28  
L2 memory protection page attribute register 29 (controls memory address  
0x0083 A000 - 0x0083 BFFF)  
0x0184 A274  
0x0184 A278  
0x0184 A27C  
0x0184 A280  
0x0184 A284  
0x0184 A288  
0x0184 A28C  
0x0184 A290  
0x0184 A294  
0x0184 A298  
0x0184 A29C  
0x0184 A2A0  
0x0184 A2A4  
0x0184 A2A8  
0x0184 A2AC  
0x0184 A2B0  
0x0184 A2B4  
0x0184 A2B8  
0x0184 A2BC  
0x0184 A2C0  
0x0184 A2C4  
0x0184 A2C8  
0x0184 A2CC  
0x0184 A2D0  
0x0184 A2D4  
0x0184 A2D8  
0x0184 A2DC  
L2MPPA29  
L2MPPA30  
L2MPPA31  
L2MPPA32  
L2MPPA33  
L2MPPA34  
L2MPPA35  
L2MPPA36  
L2MPPA37  
L2MPPA38  
L2MPPA39  
L2MPPA40  
L2MPPA41  
L2MPPA42  
L2MPPA43  
L2MPPA44  
L2MPPA45  
L2MPPA46  
L2MPPA47  
L2MPPA48  
L2MPPA49  
L2MPPA50  
L2MPPA51  
L2MPPA52  
L2MPPA53  
L2MPPA54  
L2MPPA55  
L2 memory protection page attribute register 30 (controls memory address  
0x0083 C000 - 0x0083 DFFF)  
L2 memory protection page attribute register 31 (controls memory address  
0x0083 E000 - 0x0083 FFFF)  
L2 memory protection page attribute register 32 (controls memory address  
0x0070 0000 - 0x0070 7FFF)  
L2 memory protection page attribute register 33 (controls memory address  
0x0070 8000 - 0x0070 FFFF)  
L2 memory protection page attribute register 34 (controls memory address  
0x0071 0000 - 0x0071 7FFF)  
L2 memory protection page attribute register 35 (controls memory address  
0x0071 8000 - 0x0071 FFFF)  
L2 memory protection page attribute register 36 (controls memory address  
0x0072 0000 - 0x0072 7FFF)  
L2 memory protection page attribute register 37 (controls memory address  
0x0072 8000 - 0x0072 FFFF)  
L2 memory protection page attribute register 38 (controls memory address  
0x0073 0000 - 0x0073 7FFF)  
L2 memory protection page attribute register 39 (controls memory address  
0x0073 8000 - 0x0073 FFFF)  
L2 memory protection page attribute register 40 (controls memory address  
0x0074 0000 - 0x0074 7FFF)  
L2 memory protection page attribute register 41 (controls memory address  
0x0074 8000 - 0x0074 FFFF)  
L2 memory protection page attribute register 42 (controls memory address  
0x0075 0000 - 0x0075 7FFF)  
L2 memory protection page attribute register 43 (controls memory address  
0x0075 8000 - 0x0075 FFFF)  
L2 memory protection page attribute register 44 (controls memory address  
0x0076 0000 - 0x0076 7FFF)  
L2 memory protection page attribute register 45 (controls memory address  
0x0076 8000 - 0x0076 FFFF)  
L2 memory protection page attribute register 46 (controls memory address  
0x0077 0000 - 0x0077 7FFF)  
L2 memory protection page attribute register 47 (controls memory address  
0x0077 8000 - 0x0077 FFFF)  
L2 memory protection page attribute register 48 (controls memory address  
0x0078 0000 - 0x0078 7FFF)  
L2 memory protection page attribute register 49 (controls memory address  
0x0078 8000 - 0x0078 FFFF)  
L2 memory protection page attribute register 50 (controls memory address  
0x0079 0000 - 0x0079 7FFF)  
L2 memory protection page attribute register 51 (controls memory address  
0x0079 8000 - 0x0079 FFFF)  
L2 memory protection page attribute register 52 (controls memory address  
0x007A 0000 - 0x007A 7FFF)  
L2 memory protection page attribute register 53 (controls memory address  
0x007A 8000 - 0x007A FFFF)  
L2 memory protection page attribute register 54 (controls memory address  
0x007B 0000 - 0x007B 7FFF)  
L2 memory protection page attribute register 55 (controls memory address  
0x007B 8000 - 0x007B FFFF)  
244  
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Table 5-3. C674x L1/L2 Memory Protection Registers (continued)  
HEX ADDRESS RANGE  
REGISTER ACRONYM  
DESCRIPTION  
L2 memory protection page attribute register 56 (controls memory address  
0x007C 0000 - 0x007C 7FFF)  
0x0184 A2E0  
0x0184 A2E4  
0x0184 A2E8  
0x0184 A2EC  
0x0184 A2F0  
0x0184 A2F4  
0x0184 A2F8  
0x0184 A2FC  
L2MPPA56  
L2 memory protection page attribute register 57 (controls memory address  
0x007C 8000 - 0x007C FFFF)  
L2MPPA57  
L2MPPA58  
L2MPPA59  
L2MPPA60  
L2MPPA61  
L2MPPA62  
L2MPPA63  
L2 memory protection page attribute register 58 (controls memory address  
0x007D 0000 - 0x007D 7FFF)  
L2 memory protection page attribute register 59 (controls memory address  
0x007D 8000 - 0x007D FFFF)  
L2 memory protection page attribute register 60 (controls memory address  
0x007E 0000 - 0x007E 7FFF)  
L2 memory protection page attribute register 61 (controls memory address  
0x007E 8000 - 0x007E FFFF)  
L2 memory protection page attribute register 62 (controls memory address  
0x007F 0000 - 0x007F 7FFF)  
L2 memory protection page attribute register 63 (controls memory address  
0x007F 8000 - 0x007F FFFF)  
0x0184 A300 - 0x0184 A3FF  
0x0184 A400  
-
Reserved  
L1PMPFAR  
L1PMPFSR  
L1PMPFCR  
-
L1P memory protection fault address register  
L1P memory protection fault status register  
L1P memory protection fault command register  
Reserved  
0x0184 A404  
0x0184 A408  
0x0184 A40C - 0x0184 A4FF  
0x0184 A500  
L1PMPLK0  
L1PMPLK1  
L1PMPLK2  
L1PMPLK3  
L1PMPLKCMD  
L1PMPLKSTAT  
-
L1P memory protection lock key bits [31:0]  
L1P memory protection lock key bits [63:32]  
L1P memory protection lock key bits [95:64]  
L1P memory protection lock key bits [127:96]  
L1P memory protection lock key command register  
L1P memory protection lock key status register  
Reserved  
0x0184 A504  
0x0184 A508  
0x0184 A50C  
0x0184 A510  
0x0184 A514  
0x0184 A518 - 0x0184 A5FF  
0x0184 A600 - 0x0184 A63F  
(1)  
-
Reserved  
L1P memory protection page attribute register 16 (controls memory address  
0x00E0 0000 - 0x00E0 07FF)  
0x0184 A640  
0x0184 A644  
0x0184 A648  
0x0184 A64C  
0x0184 A650  
0x0184 A654  
0x0184 A658  
0x0184 A65C  
0x0184 A660  
0x0184 A664  
0x0184 A668  
L1PMPPA16  
L1PMPPA17  
L1PMPPA18  
L1PMPPA19  
L1PMPPA20  
L1PMPPA21  
L1PMPPA22  
L1PMPPA23  
L1PMPPA24  
L1PMPPA25  
L1PMPPA26  
L1P memory protection page attribute register 17 (controls memory address  
0x00E0 0800 - 0x00E0 0FFF)  
L1P memory protection page attribute register 18 (controls memory address  
0x00E0 1000 - 0x00E0 17FF)  
L1P memory protection page attribute register 19 (controls memory address  
0x00E0 1800 - 0x00E0 1FFF)  
L1P memory protection page attribute register 20 (controls memory address  
0x00E0 2000 - 0x00E0 27FF)  
L1P memory protection page attribute register 21 (controls memory address  
0x00E0 2800 - 0x00E0 2FFF)  
L1P memory protection page attribute register 22 (controls memory address  
0x00E0 3000 - 0x00E0 37FF)  
L1P memory protection page attribute register 23 (controls memory address  
0x00E0 3800 - 0x00E0 3FFF)  
L1P memory protection page attribute register 24 (controls memory address  
0x00E0 4000 - 0x00E0 47FF)  
L1P memory protection page attribute register 25 (controls memory address  
0x00E0 4800 - 0x00E0 4FFF)  
L1P memory protection page attribute register 26 (controls memory address  
0x00E0 5000 - 0x00E0 57FF)  
(1) These addresses correspond to the L1P memory protection page attribute registers 0-15 (L1PMPPA0-L1PMPPA15) of the C674x  
megamaodule. These registers are not supported for this device.  
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Table 5-3. C674x L1/L2 Memory Protection Registers (continued)  
HEX ADDRESS RANGE  
REGISTER ACRONYM  
DESCRIPTION  
L1P memory protection page attribute register 27 (controls memory address  
0x00E0 5800 - 0x00E0 5FFF)  
0x0184 A66C  
L1PMPPA27  
L1P memory protection page attribute register 28 (controls memory address  
0x00E0 6000 - 0x00E0 67FF)  
0x0184 A670  
0x0184 A674  
0x0184 A678  
0x0184 A67C  
L1PMPPA28  
L1PMPPA29  
L1PMPPA30  
L1PMPPA31  
L1P memory protection page attribute register 29 (controls memory address  
0x00E0 6800 - 0x00E0 6FFF)  
L1P memory protection page attribute register 30 (controls memory address  
0x00E0 7000 - 0x00E0 77FF)  
L1P memory protection page attribute register 31 (controls memory address  
0x00E0 7800 - 0x00E0 7FFF)  
0x0184 A67F – 0x0184 ABFF  
0x0184 AC00  
-
Reserved  
L1DMPFAR  
L1DMPFSR  
L1DMPFCR  
-
L1D memory protection fault address register  
L1D memory protection fault status register  
L1D memory protection fault command register  
Reserved  
0x0184 AC04  
0x0184 AC08  
0x0184 AC0C - 0x0184 ACFF  
0x0184 AD00  
L1DMPLK0  
L1DMPLK1  
L1DMPLK2  
L1DMPLK3  
L1DMPLKCMD  
L1DMPLKSTAT  
-
L1D memory protection lock key bits [31:0]  
L1D memory protection lock key bits [63:32]  
L1D memory protection lock key bits [95:64]  
L1D memory protection lock key bits [127:96]  
L1D memory protection lock key command register  
L1D memory protection lock key status register  
Reserved  
0x0184 AD04  
0x0184 AD08  
0x0184 AD0C  
0x0184 AD10  
0x0184 AD14  
0x0184 AD18 - 0x0184 ADFF  
0x0184 AE00 - 0x0184 AE3F  
(2)  
-
Reserved  
L1D memory protection page attribute register 16 (controls memory address  
0x00F0 0000 - 0x00F0 07FF)  
0x0184 AE40  
0x0184 AE44  
0x0184 AE48  
0x0184 AE4C  
0x0184 AE50  
0x0184 AE54  
0x0184 AE58  
0x0184 AE5C  
0x0184 AE60  
0x0184 AE64  
0x0184 AE68  
0x0184 AE6C  
0x0184 AE70  
0x0184 AE74  
L1DMPPA16  
L1DMPPA17  
L1DMPPA18  
L1DMPPA19  
L1DMPPA20  
L1DMPPA21  
L1DMPPA22  
L1DMPPA23  
L1DMPPA24  
L1DMPPA25  
L1DMPPA26  
L1DMPPA27  
L1DMPPA28  
L1DMPPA29  
L1D memory protection page attribute register 17 (controls memory address  
0x00F0 0800 - 0x00F0 0FFF)  
L1D memory protection page attribute register 18 (controls memory address  
0x00F0 1000 - 0x00F0 17FF)  
L1D memory protection page attribute register 19 (controls memory address  
0x00F0 1800 - 0x00F0 1FFF)  
L1D memory protection page attribute register 20 (controls memory address  
0x00F0 2000 - 0x00F0 27FF)  
L1D memory protection page attribute register 21 (controls memory address  
0x00F0 2800 - 0x00F0 2FFF)  
L1D memory protection page attribute register 22 (controls memory address  
0x00F0 3000 - 0x00F0 37FF)  
L1D memory protection page attribute register 23 (controls memory address  
0x00F0 3800 - 0x00F0 3FFF)  
L1D memory protection page attribute register 24 (controls memory address  
0x00F0 4000 - 0x00F0 47FF)  
L1D memory protection page attribute register 25 (controls memory address  
0x00F0 4800 - 0x00F0 4FFF)  
L1D memory protection page attribute register 26 (controls memory address  
0x00F0 5000 - 0x00F0 57FF)  
L1D memory protection page attribute register 27 (controls memory address  
0x00F0 5800 - 0x00F0 5FFF)  
L1D memory protection page attribute register 28 (controls memory address  
0x00F0 6000 - 0x00F0 67FF)  
L1D memory protection page attribute register 29 (controls memory address  
0x00F0 6800 - 0x00F0 6FFF)  
(2) These addresses correspond to the L1D memory protection page attribute registers 0-15 (L1DMPPA0-L1DMPPA15) of the C674x  
megamaodule. These registers are not supported for this device.  
246  
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Table 5-3. C674x L1/L2 Memory Protection Registers (continued)  
HEX ADDRESS RANGE  
REGISTER ACRONYM  
DESCRIPTION  
L1D memory protection page attribute register 30 (controls memory address  
0x00F0 7000 - 0x00F0 77FF)  
0x0184 AE78  
L1DMPPA30  
L1D memory protection page attribute register 31 (controls memory address  
0x00F0 7800 - 0x00F0 7FFF)  
0x0184 AE7C  
L1DMPPA31  
-
0x0184 AE80 – 0x0185 FFFF  
Reserved  
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5.4 Memory Map Summary  
Note: Read/Write accesses to illegal or reserved addresses in the memory map may cause undefined  
behavior.  
Table 5-4. C6748 Top Level Memory Map  
Start Address End Address  
Size  
DSP Mem Map  
EDMA Mem Map  
PRUSS Mem Map  
Master  
LCDC  
Peripheral Mem Mem Map  
Map  
0x0000 0000  
0x0000 0FFF  
4K  
PRUSS Local  
Address Space  
0x0000 1000 0x006F FFFF  
0x0070 0000 0x007F FFFF  
0x0080 0000 0x0083 FFFF  
0x0084 0000 0x00DF FFFF  
0x00E0 0000 0x00E0 7FFF  
0x00E0 8000 0x00EF FFFF  
0x00F0 0000 0x00F0 7FFF  
0x00F0 8000 0x017F FFFF  
0x0180 0000 0x0180 FFFF  
(1)  
1024K  
256K  
DSP L2 ROM  
DSP L2 RAM  
32K  
32K  
DSP L1P RAM  
DSP L1D RAM  
64K  
4K  
DSP Interrupt  
Controller  
0x0181 0000  
0x0181 0FFF  
DSP Powerdown  
Controller  
0x0181 1000  
0x0181 2000  
0x0181 1FFF  
0x0181 2FFF  
4K  
4K  
DSP Security ID  
DSP Revision ID  
0x0181 3000 0x0181 FFFF  
0x0182 0000 0x0182 FFFF  
0x0183 0000 0x0183 FFFF  
52K  
64K  
64K  
DSP EMC  
DSP Internal  
Reserved  
0x0184 0000 0x0184 FFFF  
64K  
DSP Memory  
System  
0x0185 0000 0x01BF FFFF  
0x01C0 0000 0x01C0 7FFF  
0x01C0 8000 0x01C0 83FF  
0x01C0 8400 0x01C0 87FF  
0x01C0 8800 0x01C0 FFFF  
0x01C1 0000 0x01C1 0FFF  
0x01C1 1000 0x01C1 1FFF  
0x01C1 2000 0x01C1 3FFF  
0x01C1 4000 0x01C1 4FFF  
0x01C1 5000 0x01C1 FFFF  
0x01C2 0000 0x01C2 0FFF  
0x01C2 1000 0x01C2 1FFF  
0x01C2 2000 0x01C2 2FFF  
0x01C2 3000 0x01C2 3FFF  
0x01C2 4000 0x01C3 FFFF  
0x01C4 0000 0x01C4 0FFF  
0x01C4 1000 0x01C4 1FFF  
0x01C4 2000 0x01C4 2FFF  
0x01C4 3000 0x01CF FFFF  
0x01D0 0000 0x01D0 0FFF  
0x01D0 1000 0x01D0 1FFF  
32K  
1K  
EDMA3 CC  
EDMA3 TC0  
EDMA3 TC1  
1K  
4K  
4K  
PSC 0  
PLL Controller 0  
4K  
SYSCFG0  
4K  
4K  
4K  
4K  
Timer0  
Timer1  
I2C 0  
RTC  
4K  
4K  
4K  
MMC/SD 0  
SPI 0  
UART 0  
4K  
4K  
McASP 0 Control  
McASP 0 AFIFO Ctrl  
(1) The DSP L2 ROM is used for boot purposes and cannot be programmed with application code  
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Table 5-4. C6748 Top Level Memory Map (continued)  
Start Address End Address  
Size  
DSP Mem Map  
EDMA Mem Map  
PRUSS Mem Map  
Master  
LCDC  
Peripheral Mem Mem Map  
Map  
0x01D0 2000 0x01D0 2FFF  
0x01D0 3000 0x01D0 BFFF  
0x01D0 C000 0x01D0 CFFF  
0x01D0 D000 0x01D0 DFFF  
0x01D0 E000 0x01D0 FFFF  
0x01D1 0000 0x01D1 07FF  
0x01D1 0800 0x01D1 0FFF  
0x01D1 1000 0x01D1 17FF  
0x01D1 1800 0x01D1 1FFF  
0x01D1 2000 0x01DF FFFF  
0x01E0 0000 0x01E0 FFFF  
0x01E1 0000 0x01E1 0FFF  
0x01E1 1000 0x01E1 2FFF  
0x01E1 3000 0x01E1 3FFF  
0x01E1 4000 0x01E1 4FFF  
0x01E1 5000 0x01E1 5FFF  
0x01E1 6000 0x01E1 6FFF  
0x01E1 7000 0x01E1 7FFF  
0x01E1 8000 0x01E1 9FFF  
0x01E1 A000 0x01E1 AFFF  
0x01E1 B000 0x01E1 BFFF  
0x01E1 C000 0x01E1 FFFF  
0x01E2 0000 0x01E2 1FFF  
0x01E2 2000 0x01E2 2FFF  
0x01E2 3000 0x01E2 3FFF  
0x01E2 4000 0x01E2 4FFF  
0x01E2 5000 0x01E2 5FFF  
0x01E2 6000 0x01E2 6FFF  
0x01E2 7000 0x01E2 7FFF  
0x01E2 8000 0x01E2 8FFF  
0x01E2 9000 0x01E2 BFFF  
0x01E2 C000 0x01E2 CFFF  
0x01E2 D000 0x01E2 FFFF  
0x01E3 0000 0x01E3 7FFF  
0x01E3 8000 0x01E3 83FF  
0x01E3 8400 0x01EF FFFF  
0x01F0 0000 0x01F0 0FFF  
0x01F0 1000 0x01F0 1FFF  
0x01F0 2000 0x01F0 2FFF  
0x01F0 3000 0x01F0 3FFF  
0x01F0 4000 0x01F0 5FFF  
0x01F0 6000 0x01F0 6FFF  
0x01F0 7000 0x01F0 7FFF  
0x01F0 8000 0x01F0 8FFF  
0x01F0 9000 0x01F0 BFFF  
0x01F0 C000 0x01F0 CFFF  
4K  
McASP 0 Data  
4K  
4K  
UART 1  
UART 2  
2K  
2K  
2K  
2K  
McBSP0  
McBSP0 FIFO Ctrl  
McBSP1  
McBSP1 FIFO Ctrl  
64K  
4K  
USB0  
UHPI  
4K  
4K  
4K  
4K  
4K  
8K  
4K  
4K  
LCD Controller  
Memory Protection Unit 1 (MPU 1)  
Memory Protection Unit 2 (MPU 2)  
UPP  
VPIF  
SATA  
PLL Controller 1  
MMCSD1  
8K  
4K  
4K  
4K  
4K  
4K  
4K  
4K  
EMAC Control Module RAM  
EMAC Control Module Registers  
EMAC Control Registers  
EMAC MDIO port  
USB1  
GPIO  
PSC 1  
I2C 1  
4K  
SYSCFG1  
32K  
1K  
EDMA3 CC1  
EDMA3 TC2  
4K  
4K  
4K  
4K  
eHRPWM 0  
HRPWM 0  
eHRPWM 1  
HRPWM 1  
4K  
4K  
4K  
ECAP 0  
ECAP 1  
ECAP 2  
4K  
Timer2  
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LCDC  
Table 5-4. C6748 Top Level Memory Map (continued)  
Start Address End Address  
Size  
DSP Mem Map  
EDMA Mem Map  
PRUSS Mem Map  
Master  
Peripheral Mem Mem Map  
Map  
0x01F0 D000 0x01F0 DFFF  
0x01F0 E000 0x01F0 EFFF  
0x01F0 F000 0x01F0 FFFF  
0x01F1 0000 0x01F1 0FFF  
0x01F1 1000 0x01F1 1FFF  
0x01F1 2000 0x116F FFFF  
0x1170 0000 0x117F FFFF  
0x1180 0000 0x1183 FFFF  
0x1184 0000 0x11DF FFFF  
0x11E0 0000 0x11E0 7FFF  
0x11E0 8000 0x11EF FFFF  
0x11F0 0000 0x11F0 7FFF  
0x11F0 8000 0x3FFF FFFF  
0x4000 0000 0x5FFF FFFF  
0x6000 0000 0x61FF FFFF  
0x6200 0000 0x63FF FFFF  
0x6400 0000 0x65FF FFFF  
0x6600 0000 0x67FF FFFF  
4K  
4K  
Timer3  
SPI1  
4K  
4K  
McBSP0 FIFO Data  
McBSP1 FIFO Data  
(1)  
1024K  
256K  
DSP L2 ROM  
DSP L2 RAM  
DSP L1P RAM  
DSP L1D RAM  
32K  
32K  
512M  
32M  
32M  
32M  
32M  
32K  
EMIFA SDRAM data (CS0)  
EMIFA async data (CS2)  
EMIFA async data (CS3)  
EMIFA async data (CS4)  
EMIFA async data (CS5)  
EMIFA Control Regs  
0x6800 0000  
0x6800 7FFF  
0x6800 8000 0x7FFF FFFF  
0x8000 0000 0x8001 FFFF  
0x8002 0000 0xAFFF FFFF  
0xB000 0000 0xB000 7FFF  
0xB000 8000 0xBFFF FFFF  
0xC000 0000 0xCFFF FFFF  
0xD000 0000 0xFFFF FFFF  
128K  
32K  
On-chip RAM  
DDR2/mDDR Control Regs  
DDR2/mDDR Data  
256M  
5.5 Boot Modes  
This device supports a variety of boot modes through an internal DSP ROM bootloader. This device does  
not support dedicated hardware boot modes; therefore, all boot modes utilize the internal DSP ROM. The  
input states of the BOOT pins are sampled and latched into the BOOTCFG register, which is part of the  
system configuration (SYSCFG) module, when device reset is deasserted. Boot mode selection is  
determined by the values of the BOOT pins.  
See Using the SM320C6748-HIREL/C6746/C6742 Bootloader (SPRAAT2) for more details on the ROM  
Boot Loader.  
The following boot modes are supported:  
•
NAND Flash boot  
–
–
8-bit NAND  
16-bit NAND (supported on ROM revisions after d800k002 -- see the bootloader documents  
mentioned above to determine the ROM revision)  
•
NOR Flash boot  
–
–
–
NOR Direct boot (8-bit or 16-bit)  
NOR Legacy boot (8-bit or 16-bit)  
NOR AIS boot (8-bit or 16-bit)  
•
HPI Boot  
250  
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•
•
I2C0/I2C1 Boot  
–
–
EEPROM (Master Mode)  
External Host (Slave Mode)  
SPI0/SPI1 Boot  
–
–
–
Serial Flash (Master Mode)  
SERIAL EEPROM (Master Mode)  
External Host (Slave Mode)  
•
•
UART0/UART1/UART2 Boot  
External Host  
MMC/SD0 Boot  
–
5.6 SYSCFG Module  
The following system level features of the chip are controlled by the SYSCFG peripheral:  
•
•
•
•
•
•
•
Readable Device, Die, and Chip Revision ID  
Control of Pin Multiplexing  
Priority of bus accesses different bus masters in the system  
Capture at power on reset the chip BOOT pin values and make them available to software  
Control of the DeepSleep power management function  
Enable and selection of the programmable pin pullups and pulldowns  
Special case settings for peripherals:  
–
–
–
–
–
Locking of PLL controller settings  
Default burst sizes for EDMA3 transfer controllers  
Selection of the source for the eCAP module input capture (including on chip sources)  
McASP AMUTEIN selection and clearing of AMUTE status for the McASP  
Control of the reference clock source and other side-band signals for both of the integrated USB  
PHYs  
–
–
–
Clock source selection for EMIFA  
DDR2 Controller PHY settings  
SATA PHY power management controls  
•
Selects the source of emulation suspend signal (from DSP) of peripherals supporting this function.  
Many registers are accessible only by a host (DSP) when it is operating in its privileged mode (ex. from  
the kernel, but not from user space code).  
Table 5-5. System Configuration (SYSCFG) Module Register Access  
BYTE ADDRESS  
0x01C1 4000  
0x01C1 4008  
0x01C1 400C  
0x01C1 4010  
0x01C1 4014  
0x01C1 4020  
0x01C1 4038  
0x01C1 403C  
0x01C1 4044  
0x01C1 40E0  
0x01C1 40E4  
0x01C1 40E8  
ACRONYM  
REVID  
REGISTER DESCRIPTION  
Revision Identification Register  
REGISTER ACCESS  
—
DIEIDR0  
DIEIDR1  
DIEIDR2  
DIEIDR3  
BOOTCFG  
KICK0R  
Device Identification Register 0  
Device Identification Register 1  
Device Identification Register 2  
Device Identification Register 3  
Boot Configuration Register  
Kick 0 Register  
—
—
—
—
Privileged mode  
Privileged mode  
Privileged mode  
—
KICK1R  
Kick 1 Register  
HOST1CFG  
IRAWSTAT  
IENSTAT  
IENSET  
Host 1 Configuration Register  
Interrupt Raw Status/Set Register  
Interrupt Enable Status/Clear Register  
Interrupt Enable Register  
Privileged mode  
Privileged mode  
Privileged mode  
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Table 5-5. System Configuration (SYSCFG) Module Register Access (continued)  
BYTE ADDRESS  
0x01C1 40EC  
0x01C1 40F0  
0x01C1 40F4  
0x01C1 40F8  
0x01C1 4110  
0x01C1 4114  
0x01C1 4118  
0x01C1 4120  
0x01C1 4124  
0x01C1 4128  
0x01C1 412C  
0x01C1 4130  
0x01C1 4134  
0x01C1 4138  
0x01C1 413C  
0x01C1 4140  
0x01C1 4144  
0x01C1 4148  
0x01C1 414C  
0x01C1 4150  
0x01C1 4154  
0x01C1 4158  
0x01C1 415C  
0x01C1 4160  
0x01C1 4164  
0x01C1 4168  
0x01C1 416C  
0x01C1 4170  
0x01C1 4174  
0x01C1 4178  
0x01C1 417C  
0x01C1 4180  
0x01C1 4184  
0x01C1 4188  
0x01C1 418C  
0x01E2 C000  
0x01E2 C004  
0x01E2 C008  
0x01E2 C00C  
0x01E2 C010  
0x01E2 C014  
0x01E2 C018  
ACRONYM  
IENCLR  
REGISTER DESCRIPTION  
Interrupt Enable Clear Register  
REGISTER ACCESS  
Privileged mode  
Privileged mode  
Privileged mode  
—
EOI  
End of Interrupt Register  
FLTADDRR  
FLTSTAT  
MSTPRI0  
MSTPRI1  
MSTPRI2  
PINMUX0  
PINMUX1  
PINMUX2  
PINMUX3  
PINMUX4  
PINMUX5  
PINMUX6  
PINMUX7  
PINMUX8  
PINMUX9  
PINMUX10  
PINMUX11  
PINMUX12  
PINMUX13  
PINMUX14  
PINMUX15  
PINMUX16  
PINMUX17  
PINMUX18  
PINMUX19  
SUSPSRC  
CHIPSIG  
Fault Address Register  
Fault Status Register  
Master Priority 0 Registers  
Privileged mode  
Privileged mode  
Privileged mode  
Privileged mode  
Privileged mode  
Privileged mode  
Privileged mode  
Privileged mode  
Privileged mode  
Privileged mode  
Privileged mode  
Privileged mode  
Privileged mode  
Privileged mode  
Privileged mode  
Privileged mode  
Privileged mode  
Privileged mode  
Privileged mode  
Privileged mode  
Privileged mode  
Privileged mode  
Privileged mode  
Privileged mode  
—
Master Priority 1 Registers  
Master Priority 2 Registers  
Pin Multiplexing Control 0 Register  
Pin Multiplexing Control 1 Register  
Pin Multiplexing Control 2 Register  
Pin Multiplexing Control 3 Register  
Pin Multiplexing Control 4 Register  
Pin Multiplexing Control 5 Register  
Pin Multiplexing Control 6 Register  
Pin Multiplexing Control 7 Register  
Pin Multiplexing Control 8 Register  
Pin Multiplexing Control 9 Register  
Pin Multiplexing Control 10 Register  
Pin Multiplexing Control 11 Register  
Pin Multiplexing Control 12 Register  
Pin Multiplexing Control 13 Register  
Pin Multiplexing Control 14 Register  
Pin Multiplexing Control 15 Register  
Pin Multiplexing Control 16 Register  
Pin Multiplexing Control 17 Register  
Pin Multiplexing Control 18 Register  
Pin Multiplexing Control 19 Register  
Suspend Source Register  
Chip Signal Register  
CHIPSIG_CLR  
CFGCHIP0  
CFGCHIP1  
CFGCHIP2  
CFGCHIP3  
CFGCHIP4  
VTPIO_CTL  
DDR_SLEW  
DeepSleep  
PUPD_ENA  
PUPD_SEL  
RXACTIVE  
PWRDN  
Chip Signal Clear Register  
—
Chip Configuration 0 Register  
Chip Configuration 1 Register  
Chip Configuration 2 Register  
Chip Configuration 3 Register  
Chip Configuration 4 Register  
VTPIO COntrol Register  
Privileged mode  
Privileged mode  
Privileged mode  
Privileged mode  
Privileged mode  
Privileged mode  
Privileged mode  
Privileged mode  
Privileged mode  
Privileged mode  
Privileged mode  
Privileged mode  
DDR Slew Register  
DeepSleep Register  
Pullup / Pulldown Enable Register  
Pullup / Pulldown Selection Register  
RXACTIVE Control Register  
PWRDN Control Register  
252  
Detailed Description  
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5.7 Pullup/Pulldown Resistors  
Proper board design should ensure that input pins to the device always be at a valid logic level and not  
floating. This may be achieved via pullup/pulldown resistors. The device features internal pullup (IPU) and  
internal pulldown (IPD) resistors on most pins to eliminate the need, unless otherwise noted, for external  
pullup/pulldown resistors.  
An external pullup/pulldown resistor needs to be used in the following situations:  
•
Boot and Configuration Pins: If the pin is both routed out and 3-stated (not driven), an external  
pullup/pulldown resistor is strongly recommended, even if the IPU/IPD matches the desired value/state.  
•
Other Input Pins: If the IPU/IPD does not match the desired value/state, use an external  
pullup/pulldown resistor to pull the signal to the opposite rail.  
For the boot and configuration pins, if they are both routed out and 3-stated (not driven), it is strongly  
recommended that an external pullup/pulldown resistor be implemented. Although, internal  
pullup/pulldown resistors exist on these pins and they may match the desired configuration value,  
providing external connectivity can help ensure that valid logic levels are latched on these device boot and  
configuration pins. In addition, applying external pullup/pulldown resistors on the boot and configuration  
pins adds convenience to the user in debugging and flexibility in switching operating modes.  
Tips for choosing an external pullup/pulldown resistor:  
•
Consider the total amount of current that may pass through the pullup or pulldown resistor. Make sure  
to include the leakage currents of all the devices connected to the net, as well as any internal pullup or  
pulldown resistors.  
•
Decide a target value for the net. For a pulldown resistor, this should be below the lowest VIL level of  
all inputs connected to the net. For a pullup resistor, this should be above the highest VIH level of all  
inputs on the net. A reasonable choice would be to target the VOL or VOH levels for the logic family of  
the limiting device; which, by definition, have margin to the VIL and VIH levels.  
•
•
Select a pullup/pulldown resistor with the largest possible value; but, which can still ensure that the net  
will reach the target pulled value when maximum current from all devices on the net is flowing through  
the resistor. The current to be considered includes leakage current plus, any other internal and  
external pullup/pulldown resistors on the net.  
For bidirectional nets, there is an additional consideration which sets a lower limit on the resistance  
value of the external resistor. Verify that the resistance is small enough that the weakest output buffer  
can drive the net to the opposite logic level (including margin).  
•
•
•
Remember to include tolerances when selecting the resistor value.  
For pullup resistors, also remember to include tolerances on the IO supply rail.  
For most systems, a 1-kΩ resistor can be used to oppose the IPU/IPD while meeting the above  
criteria. Users should confirm this resistor value is correct for their specific application.  
•
For most systems, a 20-kΩ resistor can be used to compliment the IPU/IPD on the boot and  
configuration pins while meeting the above criteria. Users should confirm this resistor value is correct  
for their specific application.  
•
•
For more detailed information on input current (II), and the low-/high-level input voltages (VIL and VIH)  
for the device, see Section 4.4, Recommended Operating Conditions.  
For the internal pullup/pulldown resistors for all device pins, see the peripheral/system-specific terminal  
functions table.  
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5.8 Reset  
5.8.1 Power-On Reset (POR)  
A power-on reset (POR) is required to place the device in a known good state after power-up. Power-On  
Reset is initiated by bringing RESET and TRST low at the same time. POR sets all of the device internal  
logic to its default state. All pins are tri-stated with the exception of RESETOUT which remains active  
through the reset sequence, and RTCK/GP8[0]. During reset, GP8[0] is configured as a reserved function,  
and its behavior is not deterministic; the user should be aware that this pin will drive a level, and fact may  
toggle, during reset. RESETOUT in an output for use by other controllers in the system that indicates the  
device is currently in reset.  
While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for  
the device to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG  
port interface and device's emulation logic in the reset state.  
TRST only needs to be released when it is necessary to use a JTAG controller to debug the device or  
exercise the device's boundary scan functionality. Note: TRST is synchronous and must be clocked by  
TCK; otherwise, the boundary scan logic may not respond as expected after TRST is asserted.  
RESET must be released only in order for boundary-scan JTAG to read the variant field of IDCODE  
correctly. Other boundary-scan instructions work correctly independent of current state of RESET. For  
maximum reliability, the device includes an internal pulldown on the TRST pin to ensure that TRST will  
always be asserted upon power up and the device's internal emulation logic will always be properly  
initialized.  
JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG  
controllers may not drive TRST high but expect the use of a pullup resistor on TRST. When using this type  
of JTAG controller, assert TRST to intialize the device after powerup and externally drive TRST high  
before attempting any emulation or boundary scan operations.  
A summary of the effects of Power-On Reset is given below:  
•
•
•
•
•
All internal logic (including emulation logic and the PLL logic) is reset to its default state  
Internal memory is not maintained through a POR  
RESETOUT goes active  
All device pins go to a high-impedance state  
The RTC peripheral is not reset during a POR. A software sequence is required to reset the RTC  
CAUTION: A watchdog reset triggers a POR.  
5.8.2 Warm Reset  
A warm reset provides a limited reset to the device. Warm Reset is initiated by bringing only RESET low  
(TRST is maintained high through a warm reset). Warm reset sets certain portions of the device to their  
default state while leaving others unaltered. All pins are tri-stated with the exception of RESETOUT which  
remains active through the reset sequence, and RTCK/GP8[0]. During reset, GP8[0] is configured as a  
reserved function, and its behavior is not deterministic; the user should be aware that this pin will drive a  
level, and fact may toggle, during reset. RESETOUT is an output for use by other controllers in the system  
that indicates the device is currently in reset.  
During an emulation, the emulator will maintain TRST high and hence only warm reset (not POR) is  
available during emulation debug and development.  
A summary of the effects of Warm Reset is given below:  
•
•
•
•
All internal logic (except for the emulation logic and the PLL logic) is reset to its default state  
Internal memory is maintained through a warm reset  
RESETOUT goes active  
All device pins go to a high-impedance state  
254  
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•
The RTC peripheral is not reset during a warm reset. A software sequence is required to reset the  
RTC  
5.9 Interrupts  
The device has a large number of interrupts to service the needs of its many peripherals and subsystems.  
5.9.1 DSP Interrupts  
The C674x DSP interrupt controller combines device events into 12 prioritized interrupts. The source for  
each of the 12 CPU interrupts is user programmable and is listed in Table 5-6. Also, the interrupt  
controller controls the generation of the CPU exceptions, NMI, and emulation interrupts. Table 5-7  
summarizes the C674x interrupt controller registers and memory locations.  
Refer to the C674x DSP MegaModule Reference Guide (SPRUFK5) and the TMS320C674x DSP CPU  
and Instruction Set Reference Guide (SPRUFE8) for details of the C674x interrupts.  
Table 5-6. C6748 DSP Interrupts  
EVT#  
Interrupt Name  
EVT0  
Source  
0
1
2
3
4
5
6
7
8
C674x Int Ctl 0  
EVT1  
C674x Int Ctl 1  
EVT2  
C674x Int Ctl 2  
EVT3  
C674x Int Ctl 3  
T64P0_TINT12  
SYSCFG_CHIPINT2  
PRU_EVTOUT0  
EHRPWM0  
Timer64P0 - TINT12  
SYSCFG CHIPSIG Register  
PRUSS Interrupt  
HiResTimer/PWM0 Interrupt  
EDMA3_0_CC0_INT1  
EDMA3_0 Channel Controller 0 Shadow Region 1 Transfer  
Completion Interrupt  
9
EMU_DTDMA  
EHRPWM0TZ  
EMU_RTDXRX  
EMU_RTDXTX  
IDMAINT0  
C674x-ECM  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
HiResTimer/PWM0 Trip Zone Interrupt  
C674x-RTDX  
C674x-RTDX  
C674x-EMC  
IDMAINT1  
C674x-EMC  
MMCSD0_INT0  
MMCSD0_INT1  
PRU_EVTOUT1  
EHRPWM1  
MMCSD0 MMC/SD Interrupt  
MMCSD0 SDIO Interrupt  
PRUSS Interrupt  
HiResTimer/PWM1 Interrupt  
USB0 Interrupt  
USB0_INT  
USB1_HCINT  
USB1_RWAKEUP  
PRU_EVTOUT2  
EHRPWM1TZ  
SATA_INT  
USB1 OHCI Host Controller Interrupt  
USB1 Remote Wakeup Interrupt  
PRUSS Interrupt  
HiResTimer/PWM1 Trip Zone Interrupt  
SATA Controller  
T64P2_TINTALL  
EMAC_C0RXTHRESH  
EMAC_C0RX  
EMAC_C0TX  
Timer64P2 Combined TINT12 and TINT 34 Interrupt  
EMAC - Core 0 Receive Threshold Interrupt  
EMAC - Core 0 Receive Interrupt  
EMAC - Core 0 Transmit Interrupt  
EMAC - Core 0 Miscellaneous Interrupt  
EMAC - Core 1 Receive Threshold Interrupt  
EMAC - Core 1 Receive Interrupt  
EMAC - Core 1 Transmit Interrupt  
EMAC_C0MISC  
EMAC_C1RXTHRESH  
EMAC_C1RX  
EMAC_C1TX  
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Table 5-6. C6748 DSP Interrupts (continued)  
EVT#  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76 - 77  
78  
79  
80  
Interrupt Name  
Source  
EMAC_C1MISC  
UHPI_DSPINT  
PRU_EVTOUT3  
IIC0_INT  
EMAC - Core 1 Miscellaneous Interrupt  
UHPI DSP Interrupt  
PRUSS Interrupt  
I2C0  
SP0_INT  
SPI0  
UART0_INT  
UART0  
PRU_EVTOUT5  
T64P1_TINT12  
GPIO_B1INT  
IIC1_INT  
PRUSS Interrupt  
Timer64P1 Interrupt 12  
GPIO Bank 1 Interrupt  
I2C1  
SPI1_INT  
SPI1  
PRU_EVTOUT6  
ECAP0  
PRUSS Interrupt  
ECAP0  
UART_INT1  
UART1  
ECAP1  
ECAP1  
T64P1_TINT34  
GPIO_B2INT  
PRU_EVTOUT7  
ECAP2  
Timer64P1 Interrupt 34  
GPIO Bank 2 Interrupt  
PRUSS Interrupt  
ECAP2  
GPIO_B3INT  
MMCSD1_INT1  
GPIO_B4INT  
EMIFA_INT  
GPIO Bank 3 Interrupt  
MMCSD1 SDIO Interrupt  
GPIO Bank 4 Interrupt  
EMIFA  
EDMA3_0_CC0_ERRINT  
EDMA3_0_TC0_ERRINT  
EDMA3_0_TC1_ERRINT  
GPIO_B5INT  
DDR2_MEMERR  
MCASP0_INT  
GPIO_B6INT  
RTC_IRQS  
EDMA3_0 Channel Controller 0 Error Interrupt  
EDMA3_0 Transfer Controller 0 Error Interrupt  
EDMA3_0 Transfer Controller 1 Error Interrupt  
GPIO Bank 5 Interrupt  
DDR2 Memory Error Interrupt  
McASP0 Combined RX/TX Interrupts  
GPIO Bank 6 Interrupt  
RTC Combined  
T64P0_TINT34  
GPIO_B0INT  
PRU_EVTOUT4  
SYSCFG_CHIPINT3  
MMCSD1_INT0  
UART2_INT  
Timer64P0 Interrupt 34  
GPIO Bank 0 Interrupt  
PRUSS Interrupt  
SYSCFG_CHIPSIG Register  
MMCSD1 MMC/SD Interrupt  
UART2  
PSC0_ALLINT  
PSC1_ALLINT  
GPIO_B7INT  
LCDC_INT  
PSC0  
PSC1  
GPIO Bank 7 Interrupt  
LDC Controller  
PROTERR  
SYSCFG Protection Shared Interrupt  
GPIO Bank 8 Interrupt  
Reserved  
GPIO_B8INT  
-
T64P2_CMPINT0  
T64P2_CMPINT1  
T64P2_CMPINT2  
Timer64P2 - Compare Interrupt 0  
Timer64P2 - Compare Interrupt 1  
Timer64P2 - Compare Interrupt 2  
256  
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Table 5-6. C6748 DSP Interrupts (continued)  
EVT#  
81  
Interrupt Name  
Source  
T64P2_CMPINT3  
T64P2_CMPINT4  
T64P2_CMPINT5  
T64P2_CMPINT6  
T64P2_CMPINT7  
T64P3_TINTALL  
MCBSP0_RINT  
Timer64P2 - Compare Interrupt 3  
Timer64P2 - Compare Interrupt 4  
Timer64P2 - Compare Interrupt 5  
Timer64P2 - Compare Interrupt 6  
Timer64P2 - Compare Interrupt 7  
82  
83  
84  
85  
86  
Timer64P3 Combined TINT12 and TINT 34 Interrupt  
McBSP0 Receive Interrupt  
87  
88  
MCBSP0_XINT  
McBSP0 Transmit Interrupt  
89  
MCBSP1_RINT  
McBSP1 Receive Interrupt  
90  
MCBSP1_XINT  
McBSP1 Transmit Interrupt  
91  
EDMA3_1_CC0_INT1  
EDMA3_1 Channel Controller 0 Shadow Region 1 Transfer  
Completion Interrupt  
92  
93  
EDMA3_1_CC0_ERRINT  
EDMA3_1_TC0_ERRINT  
UPP_INT  
EDMA3_1 Channel Controller 0 Error Interrupt  
EDMA3_1 Transfer Controller 0 Error Interrupt  
uPP Combined Interrupt  
VPIF Combined Interrupt  
C674x-Int Ctl  
94  
95  
VPIF_INT  
96  
INTERR  
97  
EMC_IDMAERR  
-
C674x-EMC  
98 - 112  
113  
114 - 115  
116  
117  
118  
119  
120  
121  
122  
123  
124  
125  
126  
127  
Reserved  
PMC_ED  
C674x-PMC  
-
Reserved  
UMC_ED1  
C674x-UMC  
UMC_ED2  
C674x-UMC  
PDC_INT  
C674x-PDC  
SYS_CMPA  
PMC_CMPA  
PMC_CMPA  
DMC_CMPA  
DMC_CMPA  
UMC_CMPA  
UMC_CMPA  
EMC_CMPA  
EMC_BUSERR  
C674x-SYS  
C674x-PMC  
C674x-PMC  
C674x-DMC  
C674x-DMC  
C674x-UMC  
C674x-UMC  
C674x-EMC  
C674x-EMC  
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Table 5-7. C674x DSP Interrupt Controller Registers  
BYTE ADDRESS  
ACRONYM  
EVTFLAG0  
EVTFLAG1  
EVTFLAG2  
EVTFLAG3  
EVTSET0  
DESCRIPTION  
0x0180 0000  
0x0180 0004  
0x0180 0008  
0x0180 000C  
0x0180 0020  
0x0180 0024  
0x0180 0028  
0x0180 002C  
0x0180 0040  
0x0180 0044  
0x0180 0048  
0x0180 004C  
0x0180 0080  
0x0180 0084  
0x0180 0088  
0x0180 008C  
0x0180 00A0  
0x0180 00A4  
0x0180 00A8  
0x0180 00AC  
0x0180 00C0  
0x0180 00C4  
0x0180 00C8  
0x0180 00CC  
0x0180 00E0  
0x0180 00E4  
0x0180 00E8  
0x0180 00EC  
0x0180 0104  
0x0180 0108  
0x0180 010C  
0x0180 0140 - 0x0180 0144  
0x0180 0180  
0x0180 0184  
0x0180 0188  
0x0180 01C0  
Event flag register 0  
Event flag register 1  
Event flag register 2  
Event flag register 3  
Event set register 0  
EVTSET1  
Event set register 1  
EVTSET2  
Event set register 2  
EVTSET3  
Event set register 3  
EVTCLR0  
Event clear register 0  
Event clear register 1  
Event clear register 2  
Event clear register 3  
Event mask register 0  
Event mask register 1  
Event mask register 2  
Event mask register 3  
Masked event flag register 0  
Masked event flag register 1  
Masked event flag register 2  
Masked event flag register 3  
Exception mask register 0  
Exception mask register 1  
Exception mask register 2  
Exception mask register 3  
EVTCLR1  
EVTCLR2  
EVTCLR3  
EVTMASK0  
EVTMASK1  
EVTMASK2  
EVTMASK3  
MEVTFLAG0  
MEVTFLAG1  
MEVTFLAG2  
MEVTFLAG3  
EXPMASK0  
EXPMASK1  
EXPMASK2  
EXPMASK3  
MEXPFLAG0  
MEXPFLAG1  
MEXPFLAG2  
MEXPFLAG3  
INTMUX1  
Masked exception flag register 0  
Masked exception flag register 1  
Masked exception flag register 2  
Masked exception flag register 3  
Interrupt mux register 1  
INTMUX2  
Interrupt mux register 2  
INTMUX3  
Interrupt mux register 3  
-
Reserved  
INTXSTAT  
INTXCLR  
Interrupt exception status  
Interrupt exception clear  
Dropped interrupt mask register  
Event assert register  
INTDMASK  
EVTASRT  
258  
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6 器件和文档支持  
6.1 器件命名规则  
为了指出产品开发周期的阶段，TI 为所有数字信号处理 (DSP) 器件和支持工具的部件号指定了前缀。每个  
DSP 商用系列产品均具有以下三个前缀中的一个：TMX、TMP 或 TMS（例如，TMS320C6745）。 德州仪  
器 (TI) 建议为其支持的工具使用三个可能前缀指示符中的两个：TMDX 和 TMDS。这些前缀代表了产品开  
发的发展阶段，即从工程原型 (TMX/TMDX) 直到完全合格的生产器件/工具 (TMS/TMDS)。  
器件开发进化流程：  
TMX  
TMP  
TMS  
试验器件不一定代表最终器件的电气规范标准。  
最终的芯片模型符合器件的电气技术规范，但是未经完整的质量和可靠性验证。  
完全合格的生产器件。  
支持工具开发发展流程：  
TMDX  
TMDS  
还未经德州仪器 (TI) 完整内部质量测试的开发支持产品.  
完全合格的开发支持产品.  
TMX 和 TMP 器件和 TMDX 开发支持工具在供货时附带如下免责条款：  
“开发的产品用于内部评估用途。”  
TMS 器件和 TMDS 开发支持工具已进行完全特性描述，并且器件的质量和可靠性已经完全论证。TI 的标准  
保修证书适用。  
预测显示原型器件（TMX 或 TMP）的故障率大于标准生产器件。由于它们的预计的最终使用故障率仍未定  
义，德州仪器 (TI) 建议不要将这些器件用于任何生产系统。只有合格的生产器件将被使用。  
TI 器件的命名规则也包括一个带有器件系列名称的后缀。这个后缀表示封装类型（例如，GWT），温度范  
围（例如，“空白”是商业级温度范围），并以兆赫为单位的器件速度范围（例如，“空白”是默认值）。  
图 6-1 提供了一个解读完整器件名称的图例。  
( )  
( ) ( )  
SM  
320  
C6748  
GWT  
E
Basic Secure Boot Enabled  
PREFIX  
DEVICE SPEED RANGE  
SM = Qualified Device  
3 = 375 MHz (Revision 2.x)  
DEVICE FAMILY  
TEMPERATURE RANGE (JUNCTION)  
320 = TMS320™ DSP Family  
A = –55°C to 105°C, Extended Grade  
DEVICE  
C6748  
PACKAGE TYPE(A)  
SILICON REVISION(B)  
GWT = 361-Pin Plastic BGA, With Sn-Pb Solder  
Balls, 0.8-mm Ball Pitch  
E = Revision 2.3  
A. BGA = 球栅阵列  
图 6-1. 器件命名规则  
6.2 工具与软件  
德州仪器 (TI) 针对器件平台提供了大量的开发工具，其中包括评估处理器性能、生成代码、开发算法工具、  
以及完全集成和调试软件及硬件模块的工具。工具的电子支持文档可从 Code Composer Studio™ 集成开发  
环境 (IDE) 中获得。  
下列产品支持 器件的 应用的开发提供支持：  
软件开发工具:  
Code Composer Studio™ 集成开发环境 (IDE)：包括编辑器  
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C/C++/汇编代码生成工具、调试工具以及其他开发工具  
可扩展实时基础软件 (DSP/BIOS™)，提供支持所有应用所需的基本运行时目标软件。  
硬件开发工具:  
扩展开发系统 (XDS™) 仿真器  
要获取该器件的开发支持工具的完整列表，请访问德州仪器 (TI) 网站 http://www.ti.com。有关定价和购  
买信息，请联系最近的 TI 销售办事处或授权分销商。  
6.3 文档支持  
以下文档可在 www.ti.com 网站上获取。提示：请在搜索框中输入文献编号。  
DSP 参考指南  
SPRUG82 《TMS320C674x DSP 缓存用户指南》。 解释存储器缓存的基础知识并介绍如何在 DSP 应用  
中高效地使用 TMS320C674x 数字信号处理器 (DSP) 基于 2 级缓存的内部存储器 架构。展示  
如何与外部存储器保持一致性、如何通过 DMA 缩短延时以及如何优化您的代码来提高缓存效  
率。C674x DSP 的内部存储器架构采用 2 级结构，在第 1 级上包含一个专用的程序缓存  
(L1P) 和一个专用的数据缓存 (L1D)。CPU 可在其管线未暂停的情况下完成对这些第 1 级缓存  
的访问。如果 CPU 请求的数据不在缓存内，那么将从下一个低级存储器 (L2) 或外部存储器中  
获取。  
SPRUFE8 TMS320C674x DSP CPU 和指令集参考指南. 介绍 TMS320C674x 数字信号处理器 (DSP) 的  
CPU 架构、管线、指令集和中断。C674x DSP 是 C64x+ 和 C67x+ DSP 的增强版，增加了功  
能并扩展了指令集。  
SPRUFK5 《TMS320C674x DSP 超级模块参考指南》。介绍 TMS320C674x 数字信号处理器 (DSP) 超  
级模块。针对内部直接存储器访问 (IDMA) 控制器、中断控制器、掉电控制器、存储器保护、  
带宽管理以及存储器和缓存进行讨论。  
SPRUFK9 TMS320C674x/OMAP-L1x 处理器外设概览参考指南. 简要介绍器件上的可用外设。  
SPRUGJ7 《SM320C6748-HIREL DSP 系统参考指南》。介绍片上系统 (SoC)。SoC 系统包括 TI 的标  
准 TMS320C674x 超级模块和几个内部存储块（L1P、L1D 和 L2）。  
SPRUGQ9 《TMS320C674x/OMAP-L1x 处理器安全用户指南》。简要介绍在 TI 基本安全启动器件上实  
现的安全概念。  
6.3.1 接收文档更新通知  
如需接收文档更新通知，请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me)  
注册后，即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史  
记录。  
6.4 社区资源  
下列链接提供到 TI 社区资源的连接。 链接的内容由各个分销商“按照原样”提供。 这些内容并不构成 TI 技术  
规范和标准且不一定反映 TI 的观点；请见 TI 的使用条款。  
TI E2E™ 在线社区 TI 工程师对工程师 (E2E) 社区。 此社区的创建目的是为了促进工程师之间协作。 在  
e2e.ti.com 中，您可以咨询问题、共享知识、探索思路，在同领域工程师的帮助下解决问题。  
德州仪器 (TI) 嵌入式处理器维基网站 德州仪器 (TI) 嵌入式处理器维基网站。 此网站的建立是为了帮助开发  
人员从德州仪器 (TI) 的嵌入式处理器入门并且也为了促进与这些器件相关的硬件和软件的总体  
知识的创新和增长。  
6.5 商标  
BIOS, E2E are trademarks of Texas Instruments.  
Windows is a registered trademark of Microsoft.  
I2C 总线 is a trademark of Phillips.  
All other trademarks are the property of their respective owners.  
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6.6 静电放电警告  
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可  
能会损坏集成电路。  
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可  
能会导致器件与其发布的规格不相符。  
6.7 Glossary  
TI Glossary This glossary lists and explains terms, acronyms, and definitions.  
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7 机械、封装和可订购信息  
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知  
且不对本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。  
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PACKAGE OPTION ADDENDUM  
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25-Oct-2022  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
(6)  
SM320C6748EGWTS3  
ACTIVE  
NFBGA  
GWT  
361  
90  
Non-RoHS  
& Green  
SNPB  
Level-3-220C-168 HR  
-55 to 105  
SM320  
C6748EGWT  
A375  
Samples  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance  
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may  
reference these types of products as "Pb-Free".  
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.  
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based  
flame retardants must also meet the <=1000ppm threshold requirement.  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
(6)  
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two  
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