SM320F2808PZMEP [TI]
Digital Signal Processors; 数字信号处理器型号: | SM320F2808PZMEP |
厂家: | TEXAS INSTRUMENTS |
描述: | Digital Signal Processors |
文件: | 总118页 (文件大小:1000K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SM320F2808-EP, SM320F2806-EP
SM320F2801-EP
Digital Signal Processors
Data Manual
Literature Number: SGLS316A
March 2006–Revised February 2007
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SM320F2808-EP, SM320F2806-EP
SM320F2801-EP
Digital Signal Processors
www.ti.com
SGLS316A–MARCH 2006–REVISED FEBRUARY 2007
Contents
1
2
Features.............................................................................................................................. 9
Introduction....................................................................................................................... 10
ORDERING INFORMATION.............................................................................................. 10
2.1
2.2
Pin Assignments............................................................................................................ 11
Signal Descriptions......................................................................................................... 14
3
Functional Overview ........................................................................................................... 20
3.1
Memory Map ................................................................................................................ 21
Brief Descriptions........................................................................................................... 25
3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
3.2.7
3.2.8
3.2.9
C28x CPU ....................................................................................................... 25
Memory Bus (Harvard Bus Architecture) .................................................................... 26
Peripheral Bus .................................................................................................. 26
Real-Time JTAG and Analysis ................................................................................ 26
Flash .............................................................................................................. 26
M0, M1 SARAMs ............................................................................................... 27
L0, L1, H0 SARAMs ............................................................................................ 27
Boot ROM ........................................................................................................ 27
Security .......................................................................................................... 28
3.2.10 Peripheral Interrupt Expansion (PIE) Block .................................................................. 28
3.2.11 External Interrupts (XINT1, XINT2, XNMI) ................................................................... 29
3.2.12 Oscillator and PLL .............................................................................................. 29
3.2.13 Watchdog ........................................................................................................ 29
3.2.14 Peripheral Clocking ............................................................................................. 29
3.2.15 Low-Power Modes .............................................................................................. 29
3.2.16 Peripheral Frames 0, 1, 2 (PFn) .............................................................................. 29
3.2.17 General-Purpose Input/Output (GPIO) Multiplexer ......................................................... 30
3.2.18 32-Bit CPU-Timers (0, 1, 2) ................................................................................... 30
3.2.19 Control Peripherals ............................................................................................. 30
3.2.20 Serial Port Peripherals ......................................................................................... 30
Register Map................................................................................................................ 31
Device Emulation Registers............................................................................................... 33
Interrupts .................................................................................................................... 34
3.3
3.4
3.5
3.5.1
External Interrupts .............................................................................................. 36
3.6
System Control ............................................................................................................. 37
3.6.1
3.6.2
OSC and PLL Block ............................................................................................ 38
Watchdog Block ................................................................................................. 41
3.7
Low-Power Modes Block .................................................................................................. 42
4
Peripherals ........................................................................................................................ 43
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
32-Bit CPU-Timers 0/1/2 .................................................................................................. 43
Enhanced PWM Modules (ePWM1/2/3/4/5/6).......................................................................... 45
Hi-Resolution PWM (HRPWM) ........................................................................................... 47
Enhanced CAP Modules (eCAP1/2/3/4) ................................................................................ 48
Enhanced QEP Modules (eQEP1/2)..................................................................................... 49
Enhanced Analog-to-Digital Converter (ADC) Module ................................................................ 52
Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B)..................................... 57
Serial Communications Interface (SCI) Modules (SCI-A, SCI-B) .................................................... 62
Serial Peripheral Interface (SPI) Modules (SPI-A, SPI-B, SPI-C, SPI-D)........................................... 65
4.10 Inter-Integrated Circuit (I2C)............................................................................................... 69
4.11 GPIO MUX .................................................................................................................. 71
Device Support .................................................................................................................. 75
5
5.1
Device and Development Support Tool Nomenclature................................................................ 75
2
Contents
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SM320F2801-EP
Digital Signal Processors
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SGLS316A–MARCH 2006–REVISED FEBRUARY 2007
5.2
Documentation Support ................................................................................................... 76
6
Electrical Specifications...................................................................................................... 79
6.1
6.2
6.3
6.4
Absolute Maximum Ratings............................................................................................... 79
Recommended Operating Conditions ................................................................................... 79
Electrical Characteristics ................................................................................................. 80
Current Consumption ..................................................................................................... 80
6.4.1
Reducing Current Consumption .............................................................................. 83
Current Consumption Graphs.................................................................................. 84
6.4.2
6.5
Timing Parameter Symbology ............................................................................................ 84
6.5.1
6.5.2
6.5.3
General Notes on Timing Parameters ........................................................................ 85
Test Load Circuit ................................................................................................ 85
Device Clock Table ............................................................................................. 85
6.6
6.7
Clock Requirements and Characteristics ............................................................................... 86
Power Sequencing ......................................................................................................... 87
6.7.1
Power Management and Supervisory Circuit Solutions .................................................... 88
6.8
General-Purpose Input/Output (GPIO) .................................................................................. 91
6.8.1
6.8.2
6.8.3
6.8.4
GPIO - Output Timing........................................................................................... 91
GPIO - Input Timing............................................................................................. 92
Sampling Window Width for Input Signals ................................................................... 92
Low-Power Mode Wakeup Timing ............................................................................ 94
6.9
Enhanced Control Peripherals............................................................................................ 96
6.9.1
6.9.2
6.9.3
6.9.4
6.9.5
6.9.6
6.9.7
Enhanced Pulse Width Modulator (ePWM) Timing ......................................................... 96
Trip-Zone Input Timing.......................................................................................... 97
External Interrupt Timing ....................................................................................... 99
I2C Electrical Specification and Timing ..................................................................... 100
Serial Peripheral Interface (SPI) Master Mode Timing.................................................... 100
SPI Slave Mode Timing ....................................................................................... 104
On-Chip Analog-to-Digital Converter ........................................................................ 107
6.10 Detailed Descriptions .................................................................................................... 112
6.11 Flash Timing............................................................................................................... 113
Mechanical Data ............................................................................................................... 115
7
Contents
3
SM320F2808-EP, SM320F2806-EP
SM320F2801-EP
Digital Signal Processors
www.ti.com
SGLS316A–MARCH 2006–REVISED FEBRUARY 2007
List of Figures
2-1
SM320F2808 100-Pin PZ LQFP (Top View) .................................................................................. 11
2-2
F2806 100-Pin PZ LQFP (Top View)........................................................................................... 12
F2801/UCD9501 100-Pin PZ LQFP (Top View) .............................................................................. 13
SM320F280x 100-Ball GGM and ZGM MicroStar™ BGA (Bottom View) ................................................. 14
Functional Block Diagram........................................................................................................ 20
F2808 Memory Map .............................................................................................................. 21
F2806 Memory Map .............................................................................................................. 22
F2801/9501 Memory Map........................................................................................................ 23
External and PIE Interrupt Sources............................................................................................. 34
Multiplexing of Interrupts Using the PIE Block ................................................................................ 35
Clock and Reset Domains ....................................................................................................... 37
OSC and PLL Block Diagram ................................................................................................... 38
Using a 3.3-V External Oscillator ............................................................................................... 39
Using a 1.8-V External Oscillator ............................................................................................... 39
Using the Internal Oscillator ..................................................................................................... 39
Watchdog Module................................................................................................................. 41
CPU-Timers........................................................................................................................ 43
CPU-Timer Interrupt Signals and Output Signal .............................................................................. 44
Multiple PWM Modules in a 280x System ..................................................................................... 45
ePWM Sub-modules Showing Critical Internal Signal Interconects ........................................................ 47
eCAP Functional Block Diagram................................................................................................ 48
eQEP Functional Block Diagram................................................................................................ 50
Block Diagram of the ADC Module ............................................................................................. 53
ADC Pin Connections With Internal Reference ............................................................................... 54
ADC Pin Connections With External Reference .............................................................................. 55
eCAN Block Diagram and Interface Circuit .................................................................................... 58
eCAN-A Memory Map ............................................................................................................ 59
eCAN-B Memory Map ............................................................................................................ 60
Serial Communications Interface (SCI) Module Block Diagram ............................................................ 64
SPI Module Block Diagram (Slave Mode) ..................................................................................... 68
I2C Peripheral Module Interfaces ............................................................................................... 70
GPIO MUX Block Diagram....................................................................................................... 71
Qualification Using Sampling Window.......................................................................................... 74
Example of SM320x280x Device Nomenclature.............................................................................. 76
Example of UCD Device Nomenclature........................................................................................ 76
Wirebond / EM Life for SM320F280xPZMEP ................................................................................. 82
Typical Operational Current Versus Frequency (F2808) .................................................................... 84
Typical Operational Power Versus Frequency (F2808)...................................................................... 84
3.3-V Test Load Circuit........................................................................................................... 85
2-3
2-4
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
5-1
5-2
6-1
6-2
6-3
6-4
4
List of Figures
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SM320F2801-EP
Digital Signal Processors
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SGLS316A–MARCH 2006–REVISED FEBRUARY 2007
6-5
Clock Timing ....................................................................................................................... 87
Power-on Reset ................................................................................................................... 89
Warm Reset........................................................................................................................ 90
Example of Effect of Writing Into PLLCR Register ........................................................................... 91
General-Purpose Output Timing ................................................................................................ 91
Sampling Mode.................................................................................................................... 92
General-Purpose Input Timing .................................................................................................. 93
IDLE Entry and Exit Timing ...................................................................................................... 94
STANDBY Entry and Exit Timing Diagram .................................................................................... 95
HALT Wake Up Using GPIOn ................................................................................................... 96
PWM Hi-Z Characteristics ....................................................................................................... 97
ADCSOCAO or ADCSOCBO Timing........................................................................................... 99
External Interrupt Timing ......................................................................................................... 99
SPI Master Mode External Timing (Clock Phase = 0) ...................................................................... 102
SPI Master External Timing (Clock Phase = 1).............................................................................. 104
SPI Slave Mode External Timing (Clock Phase = 0)........................................................................ 105
SPI Slave Mode External Timing (Clock Phase = 1)........................................................................ 106
ADC Power-Up Control Bit Timing ............................................................................................ 108
ADC Analog Input Impedance Model ......................................................................................... 109
Sequential Sampling Mode (Single-Channel) Timing....................................................................... 110
Simultaneous Sampling Mode Timing ........................................................................................ 111
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16
6-17
6-18
6-19
6-20
6-21
6-22
6-23
6-24
6-25
List of Figures
5
SM320F2808-EP, SM320F2806-EP
SM320F2801-EP
Digital Signal Processors
www.ti.com
SGLS316A–MARCH 2006–REVISED FEBRUARY 2007
List of Tables
2-1
Hardware Features ............................................................................................................... 10
2-2
Signal Descriptions ............................................................................................................... 15
Addresses of Flash Sectors in F2808 .......................................................................................... 24
Addresses of Flash Sectors in F2806 .......................................................................................... 24
Addresses of Flash Sectors in F2801/9501 ................................................................................... 24
Wait States......................................................................................................................... 25
Boot Mode Selection.............................................................................................................. 27
Peripheral Frame 0 Registers ................................................................................................... 31
Peripheral Frame 1 Registers ................................................................................................... 32
Peripheral Frame 2 Registers ................................................................................................... 33
Device Emulation Registers ..................................................................................................... 33
PIE Peripheral Interrupts ......................................................................................................... 35
PIE Configuration and Control Registers ...................................................................................... 36
External Interrupt Registers...................................................................................................... 36
PLL, Clocking, Watchdog, and Low-Power Mode Registers ................................................................ 38
PLLCR Register Bit Definitions.................................................................................................. 40
Possible PLL Configuration Modes ............................................................................................. 40
Low-Power Modes ................................................................................................................ 42
CPU-Timers 0, 1, 2 Configuration and Control Registers ................................................................... 44
ePWM Control and Status Registers ........................................................................................... 46
eCAP Control and Status Registers ............................................................................................ 49
eQEP Control and Status Registers............................................................................................ 51
ADC Registers..................................................................................................................... 56
3.3-V eCAN Transceivers ....................................................................................................... 58
CAN Register Map ................................................................................................................ 61
SCI-A Registers ................................................................................................................... 63
SCI-B Registers ................................................................................................................... 63
SPI-A Registers ................................................................................................................... 66
SPI-B Registers ................................................................................................................... 66
SPI-C Registers ................................................................................................................... 67
SPI-D Registers ................................................................................................................... 67
I2C-A Registers .................................................................................................................... 70
GPIO Registers ................................................................................................................... 72
F2808 GPIO MUX Table ......................................................................................................... 73
SM320F2808 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT................................. 80
F2806 Current Consumption by Power-supply Pins at 100 MHz SYSCLKOUT ......................................... 81
F2801/UCD9501 Current Consumption by Power-supply Pins at 100-MHz SYSCLKOUT ............................. 82
Typical Current Consumption by Various Peripherals (at 100 MHz) ....................................................... 83
TMS320x280x Clock Table and Nomenclature ............................................................................... 86
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
6-1
6-2
6-3
6-4
6-5
6
List of Tables
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SM320F2808-EP, SM320F2806-EP
SM320F2801-EP
Digital Signal Processors
www.ti.com
SGLS316A–MARCH 2006–REVISED FEBRUARY 2007
6-6
Input Clock Frequency ........................................................................................................... 86
XCLKIN Timing Requirements - PLL Enabled ................................................................................ 86
XCLKIN Timing Requirements - PLL Disabled................................................................................ 86
XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)......................................................... 87
Power Management and Supervisory Circuit Solutions...................................................................... 88
Reset (XRS) Timing Requirements ............................................................................................ 90
General-Purpose Output Switching Characteristics .......................................................................... 91
General-Purpose Input Timing Requirements................................................................................. 92
IDLE Mode Timing Requirements............................................................................................... 94
IDLE Mode Switching Characteristics .......................................................................................... 94
STANDBY Mode Timing Requirements........................................................................................ 94
STANDBY Mode Switching Characteristics .................................................................................. 95
HALT Mode Timing Requirements.............................................................................................. 95
HALT Mode Switching Characteristics ........................................................................................ 96
ePWM Timing Requirements .................................................................................................... 97
ePWM Switching Characteristics................................................................................................ 97
Trip-Zone input Timing Requirements.......................................................................................... 97
High Resolution PWM Characteristics at SYSCLKOUT = (60 - 100 MHz)................................................ 98
Enhanced Capture (eCAP) Timing Requirement ............................................................................. 98
eCAP Switching Characteristics................................................................................................. 98
Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements ..................................................... 98
eQEP Switching Characteristics ................................................................................................ 98
External ADC Start-of-Conversion Switching Characteristics ............................................................... 98
External Interrupt Timing Requirements ....................................................................................... 99
External Interrupt Switching Characteristics................................................................................... 99
I2C Timing ....................................................................................................................... 100
SPI Master Mode External Timing (Clock Phase = 0) ...................................................................... 101
SPI Master Mode External Timing (Clock Phase = 1) ...................................................................... 103
SPI Slave Mode External Timing (Clock Phase = 0)........................................................................ 104
SPI Slave Mode External Timing (Clock Phase = 1)........................................................................ 105
ADC Electrical Characteristics (over recommended operating conditions) .............................................. 107
ADC Power-Up Delays.......................................................................................................... 108
Current Consumption for Different ADC Configurations (at 12.5-MHz ADCCLK)....................................... 108
Sequential Sampling Mode Timing............................................................................................ 110
Simultaneous Sampling Mode Timing ........................................................................................ 111
Flash Endurance................................................................................................................. 113
Flash Parameters at 100-MHz SYSCLKOUT................................................................................ 113
Flash/OTP Access Timing...................................................................................................... 113
Minimum Required Wait-States at Different Frequencies.................................................................. 114
F280x Thermal Model 100-pin GGM Results................................................................................ 115
F280x Thermal Model 100-pin PZ Results................................................................................... 115
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16
6-17
6-18
6-19
6-20
6-21
6-22
6-23
6-24
6-25
6-26
6-27
6-28
6-29
6-30
6-31
6-32
6-33
6-34
6-35
6-36
6-37
6-38
6-39
6-40
6-41
6-42
6-43
6-44
7-1
7-2
List of Tables
7
SM320F2808-EP, SM320F2806-EP
SM320F2801-EP
Digital Signal Processors
www.ti.com
SGLS316A–MARCH 2006–REVISED FEBRUARY 2007
8
List of Tables
Submit Documentation Feedback
SM320F2808-EP, SM320F2806-EP
SM320F2801-EP
Digital Signal Processors
www.ti.com
SGLS316A–MARCH 2006–REVISED FEBRUARY 2007
1
Features
•
•
Peripheral Interrupt Expansion (PIE) Block
That Supports All 43 Peripheral Interrupts
•
Controlled Baseline
–
One Assembly/Test/Fabrication Site
128-Bit Security Key/Lock
•
Enhanced Diminishing Manufacturing Sources
(DMS) Support
–
–
Protects Flash/OTP/L0/L1 Blocks
Prevents Firmware Reverse Engineering
•
•
•
Enhanced Product-Change Notification
Qualification Pedigree(1)
•
Enhanced Control Peripherals
–
–
Up to 16 PWM Outputs
Up to Four HRPWM Outputs With 150 ps
MEP Resolution
High-Performance Static CMOS Technology
–
–
–
100 MHz (10-ns Cycle Time)
Low-Power (1.8-V Core, 3.3-V I/O) Design
3.3-V Flash Voltage
–
–
–
–
Up to Four Capture Inputs
Up to Two Quadrature Encoder Interfaces
Up to Six 32-bit Timers
•
•
JTAG Boundary Scan Support
High-Performance 32-Bit CPU (TMS320C28x)
Up to Six 16-bit Timers
–
–
–
–
–
–
–
16 x 16 and 32 x 32 MAC Operations
16 x 16 Dual MAC
Harvard Bus Architecture
•
•
Three 32-Bit CPU Timers
Serial Port Peripherals
–
–
–
–
Up to Four Serial Peripheral Interface (SPI)
Modules
Up to Two Serial Communications Interface
(SCI), Standard UART Modules
Up to Two Enhanced Controller Area
Network (eCAN) Modules
One Inter-Integrated-Circuit (I2C) Bus
Atomic Operations
Fast Interrupt Response and Processing
Unified Memory Programming Model
Code-Efficient (in C/C++ and Assembly)
•
On-Chip Memory
–
F2808: 64K X 16 Flash, 18K X 16 SARAM
F2806: 32K X 16 Flash, 10K X 16 SARAM
F2801: 16K X 16 Flash, 6K X 16 SARAM
9501: 16K X 16 Flash, 6K X 16 SARAM
•
12-Bit ADC, 16 Channels
–
–
–
–
–
2 x 8 Channel Input Multiplexer
Two Sample-and-Hold
–
1K x 16 OTP ROM
Single/Simultaneous Conversions
Fast Conversion Rate: 160 ns/6.25 MSPS
Internal or External Reference
•
•
Boot ROM (4K x 16)
–
With Software Boot Modes (via SCI, SPI,
CAN, I2C, and Parallel I/O)
•
•
Up to 35 Individually Programmable,
Multiplexed General-Purpose Input/Output
(GPIO) Pins With Input Filtering
–
Standard Math Tables
Clock and System Control
–
–
–
–
Dynamic PLL Ratio Changes Supported
On-Chip Oscillator
Clock-Fail-Detect Mode
Advanced Emulation Features
–
–
Analysis and Breakpoint Functions
Real-Time Debug via Hardware
Watchdog Timer Module
•
•
•
Low-Power Modes and Power Savings
•
Any GPIO A Pin Can Be Connected to One of
the Three External Core Interrupts
–
–
IDLE, STANDBY, HALT Modes Supported
Disable Individual Peripheral Clocks
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
Package Options
–
–
Thin Quad Flatpack (PZ)
MicroStar BGA™ (GGM, ZGM)
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
Temperature Options:
M: -55°C to 125°C (PZ)
–
MicroStar BGA, TMS320C28x, MicroStar, C28x, TMS320C2000, DSP/BIOS, Code Composer Studio, TMS320 are trademarks of Texas
Instruments.
eZdsp, XDS510USB are trademarks of Spectrum Digital.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006–2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SM320F2808-EP, SM320F2806-EP
SM320F2801-EP
Digital Signal Processors
www.ti.com
SGLS316A–MARCH 2006–REVISED FEBRUARY 2007
2
Introduction
The SM320F2808, F2806, and F2801/UCD9501 devices, members of the TMS320C28x™ DSP
generation, are highly integrated, high-performance solutions for demanding control applications. The
UCD9501 is a 32-bit digital signal controller for power management.
Throughout this document, SM320F2808, F2806, and F2801/UCD9501 are abbreviated as F2808, F2806,
and F2801/9501, respectively. TMS320x280x device reference guides, flash tools, and other collateral are
applicable to the UCD9501 device as well. Table 2-1 provides a summary of each device's features.
Table 2-1. Hardware Features
FEATURE
Instruction cycle (at 100 MHz)
F2808
F2806(1)
F2801/9501(1)
10 ns
10 ns
10 ns
18K
10K
6K
Single-access RAM (SARAM) (16-bit word)
(L0, L1, M0, M1, H0)
(L0, L1, M0, M1)
(L0, M0, M1)
3.3-V on-chip flash (16-bit word)
Code security for on-chip flash/SARAM/OTP blocks
Boot ROM (4K X16)
64K
Yes
Yes
Yes
No
32K
Yes
Yes
Yes
No
16K
Yes
Yes
Yes
No
One-time programmable (OTP) ROM
External memory interface
ePWM1, ePWM2
ePWM3, ePWM4,
ePWM5, ePWM6
ePWM1, ePWM2
ePWM3, ePWM4,
ePWM5, ePWM6
ePWM1,
ePWM2,
ePWM3
Enhanced PWM outputs (16-bit timer-based modules with 2
PWM outputs/module)
ePWM1A, ePWM2A
ePWM3A, ePWM4A
ePWM1A, ePWM2A
ePWM3A, ePWM4A
ePWM1A, ePWM2A
ePWM3A
HRPWM channels
eCAP1, eCAP2
eCAP3, eCAP4
eCAP1, eCAP2
eCAP3, eCAP4
Enhanced 32-bit CAPTURE inputs or auxiliary PWM outputs
eCAP1, eCAP2
Enhanced 32-bit QEP channels (four inputs/channel)
Watchdog timer
eQEP1, eQEP2
eQEP1, eQEP2
eQEP1
Yes
16
Yes
16
3
Yes
16
3
12-Bit ADC channels
32-Bit CPU timers
3
SPI-A, SPI-B,
SPI-C, SPI-D
SPI-A, SPI-B,
SPI-C, SPI-D
Serial Peripheral Interface (SPI)
SPI-A, SPI-B
Serial Communications Interface (SCI)
Enhanced Controller Area Network (eCAN)
Inter-Integrated Circuit (I2C)
Digital I/O pins (shared)
SCI-A, SCI-B
SCI-A, SCI-B
SCI-A
eCAN-A, eCAN-B
eCAN-A
eCAN-A
I2C-A
I2C-A
I2C-A
35
35
35
External interrupts
3
3
3
Supply voltage
1.8-V Core, 3.3-V I/O
1.8-V Core, 3.3-V I/O
1.8-V Core, 3.3-V I/O
100-Pin PZ
100-Ball GGM, ZGM
100-Pin PZ
100-Ball GGM, ZGM
100-Pin PZ
100-Ball GGM, ZGM
Packaging
(PZ, GGM, ZGM)
(PZ, GGM, ZGM)
(PZ)
(PZ, GGM, ZGM)
(PZ, GGM, ZGM)
(PZ)
(PZ, GGM, ZGM)
(PZ, GGM, ZGM)
(PZ)
Temperature options
(1) Product Preview
M: -55°C to 125°C
ORDERING INFORMATION
TA
PACKAGE
LQFP-PZ
LQFP-PZ
ORDERABLE PART NUMBER
SM320F2801PZMEP
-55°C to 125°C
-55°C to 125°C
SM320F2808PZMEP
10
Introduction
Submit Documentation Feedback
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SM320F2801-EP
Digital Signal Processors
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SGLS316A–MARCH 2006–REVISED FEBRUARY 2007
2.1 Pin Assignments
The SM320F2808, F2806, and F2801/UCD9501 100-pin PZ low-profile quad flatpack (LQFP) pin
assignments are shown in Figure 2-1, Figure 2-2 and Figure 2-3. Table 2-2 describes the function(s) of
each pin.
GPIO16/SPISIMOA/CANTXB/TZ5
TDO
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
V
V
SS
SS
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
XRS
GPIO3/EPWM2B/SPISOMID
GPIO0/EPWM1A
GPIO27/ECAP4/EQEP2S/SPISTEB
EMU0
V
DDIO
EMU1
GPIO2/EPWM2A
GPIO1/EPWM1B/SPISIMOD
GPIO34
V
DDIO
GPIO24/ECAP1/EQEP2A/SPISIMOB
TRST
V
V
V
V
DD
V
DD
SS
X2
DD2A18
SS2AGND
V
SS
X1
ADCRESEXT
V
SS
ADCREFP
ADCREFM
XCLKIN
GPIO25/ECAP2/EQEP2B/SPISOMIB
GPIO28/SCIRXDA/TZ5
ADCREFIN
ADCINB7
V
DD
ADCINB6
ADCINB5
ADCINB4
V
SS
GPIO13/TZ2/CANRXB/SPISOMIB
V
DD3VFL
TEST1
TEST2
ADCINB3
ADCINB2
ADCINB1
ADCINB0
GPIO26/ECAP3/EQEP2I/SPICLKB
V
GPIO32/SDAA/EPWMSYNCI/ADCSOCAO
DDAIO
Figure 2-1. SM320F2808 100-Pin PZ LQFP (Top View)
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GPIO16/SPISIMOA/TZ5
76
50
49
TDO
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
V
V
SS
SS
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
XRS
GPIO3/EPWM2B/SPISOMID
GPIO0/EPWM1A
GPIO27/ECAP4/EQEP2S/SPISTEB
V
EMU0
EMU1
DDIO
GPIO2/EPWM2A
V
GPIO1/EPWM1B/SPISIMOD
GPIO34
DDIO
GPIO24/ECAP1/EQEP2A/SPISIMOB
TRST
V
DD
V
V
SS
DD
X2
V
DD2A18
V
SS2AGND
V
SS
X1
ADCRESEXT
ADCREFP
ADCREFM
ADCREFIN
ADCINB7
ADCINB6
ADCINB5
ADCINB4
ADCINB3
ADCINB2
ADCINB1
ADCINB0
V
SS
XCLKIN
GPIO25/ECAP2/EQEP2B/SPISOMIB
GPIO28/SCIRXDA/TZ5
V
DD
V
SS
GPIO13/TZ2/SPISOMIB
V
DD3VFL
TEST1
TEST2
99
GPIO26/ECAP3/EQEP2I/SPICLKB
GPIO32/SDAA/EPWMSYNCI/ADCSOCAO
100
V
DDAIO
Figure 2-2. F2806 100-Pin PZ LQFP (Top View)
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76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
TDO
GPIO16/SPISIMOA/TZ5
49
V
V
SS
SS
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
XRS
GPIO3/EPWM2B
GPIO0/EPWM1A
GPIO27
EMU0
EMU1
V
DDIO
GPIO2/EPWM2A
GPIO1/EPWM1B
GPIO34
V
DDIO
GPIO24/ECAP1
TRST
V
V
V
V
DD
V
DD
SS
X2
DD2A18
SS2AGND
V
SS
X1
ADCRESEXT
ADCREFP
ADCREFM
ADCREFIN
ADCINB7
ADCINB6
ADCINB5
ADCINB4
ADCINB3
ADCINB2
ADCINB1
ADCINB0
V
SS
XCLKIN
GPIO25/ECAP2/SPISIMIB
GPIO28/SCIRXDA/TZ5
V
DD
V
SS
GPIO13/TZ2
(A)
V
DD3VFL
TEST1
TEST2
GPIO26
GPIO32/SDAA/EPWMSYNCI/ADSOCAO
V
DDAIO
Figure 2-3. F2801/UCD9501 100-Pin PZ LQFP (Top View)
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K
ADCINB0
ADCINB3
ADCINB1
ADCINB2
V
SS2AGND
ADCINB7
GPIO1
GPIO2
ADCINB5
V
SS
GPIO16
VSSAIO
ADCLO
GPIO0
GPIO3
GPIO18
J
V
ADCINB4
ADCINB6
ADCINA5
V
ADCREFIN
ADCREFM
ADCREFP
DD2A18
GPIO4
GPIO5
GPIO6
GPIO17
DDAIO
H
G
F
ADCINA0
ADCINA3
V
V
V
SS
DDIO
SS
ADCINA1
V
GPIO34
GPIO7
GPIO19
ADCINA2
ADCINA7
DD
ADCINA4
VSSA2
V
ADCINA6
ADCRESEXT
GPIO20
VSS
GPIO9
GPIO8
V
DD
DDA2
E
D
C
B
A
V
V
GPIO15
V
V
X1
GPIO21
XCLKOUT
V
GPIO10
DD1A18
SS1AGND
DD
SS
DDIO
GPIO30
GPIO14
GPIO29
TEST2
GPIO28
GPIO25
XCLKIN
GPIO11
TDI
GPIO31
GPIO33
V
V
V
GPIO22
GPIO27
V
SS
DD
SS
DD
V
V
X2
GPIO24
EMU1
GPIO23
TMS
DDIO
DD3VFL
GPIO13
VSS
GPIO12
GPIO26
V
XRS
TDO
DD
GPIO32
V
V
TRST
V
EMU0
V
TCK
TEST1
SS
SS
DDIO
SS
1
2
3
4
5
6
7
8
9
10
Bottom View
Figure 2-4. SM320F280x 100-Ball GGM and ZGM MicroStar™ BGA (Bottom View)
2.2 Signal Descriptions
Table 2-2 describes the signals on the 280x devices. All digital inputs are TTL-compatible. All outputs are
3.3 V with CMOS levels. Inputs are not 5-V tolerant.
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Table 2-2. Signal Descriptions
PIN NO.
(1)
NAME
DESCRIPTION
PZ PIN
GGM
#
BALL #
JTAG
JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of
the operations of the device. If this signal is not connected or driven low, the device operates in its
functional mode, and the test reset signals are ignored.
NOTE: Do not use pullup resistors on TRST; it has an internal pull-down device. TRST is an active
high test pin and must be maintained low at all times during normal device operation. In a low-noise
environment, TRST may be left floating. In other instances, an external pulldown resistor is highly
recommended. The value of this resistor should be based on drive strength of the debugger pods
applicable to the design. A 2.2-kΩ resistor generally offers adequate protection. Since this is
application-specific, it is recommended that each target board is validated for proper operation of
the debugger and the application. (I, ↓)
TRST
84
A6
TCK
TMS
75
74
A10
B10
JTAG test clock with internal pullup (I, ↑)
JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP
controller on the rising edge of TCK. (I, ↑)
JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction
or data) on a rising edge of TCK. (I, ↑)
TDI
73
76
80
81
C9
B9
A8
B7
JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data)
are shifted out of TDO on the falling edge of TCK. (O/Z 8 mA drive)
TDO
EMU0
EMU1
Emulator pin 0. When TRST is driven high, this pin is used as an interrupt to or from the emulator
system and is defined as input/output through the JTAG scan. (I/O/Z, 8 mA drive ↑)
Emulator pin 1. When TRST is driven high, this pin is used as an interrupt to or from the emulator
system and is defined as input/output through the JTAG scan. (I/O/Z, 8 mA drive, ↑)
FLASH
VDD3VFL
TEST1
96
97
98
C4
A3
B3
3.3-V Flash Core Power Pin. This pin should be connected to 3.3 V at all times.
Test Pin. Reserved for Texas Instruments. Must be left unconnected. (I/O)
Test Pin. Reserved for Texas Instruments. Must be left unconnected. (I/O)
CLOCK
TEST2
Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the
frequency, or one-fourth the frequency of SYSCLKOUT. This is controlled by the bits 1, 0
(XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal
can be turned off by setting XCLKOUTDIV to 3. Unlike other GPIO pins, the XCLKOUT pin is not
placed in high-impedance state during a reset. (O/Z, 8 mA drive).
XCLKOUT
XCLKIN
66
90
E8
B5
External Oscillator Input. This pin is to feed a clock from an external 3.3-V oscillator. In this case,
the X1 pin must be tied to GND. If a crystal/resonator is used (or if an external 1.8-V oscillator is
used to feed clock to X1 pin), this pin must be tied to GND. (I)
Internal/External Oscillator Input. To use the internal oscillator, a quartz crystal or a ceramic
resonator may be connected across X1 and X2. The X1 pin is referenced to the 1.8-V core digital
power supply. A 1.8-V external oscillator may be connected to the X1 pin. In this case, the XCLKIN
pin must be connected to ground. If a 3.3-V external oscillator is used with the XCLKIN pin, X1 must
be tied to GND. (I)
X1
X2
88
86
E6
C6
Internal Oscillator Output. A quartz crystal or a ceramic resonator may be connected across X1 and
X2. If X2 is not used it must be left unconnected. (O)
RESET
Device Reset (in) and Watchdog Reset (out).
Device reset. XRS causes the device to terminate execution. The PC will point to the address
contained at the location 0x3FFFC0. When XRS is brought to a high level, execution begins at the
location pointed to by the PC. This pin is driven low by the DSP when a watchdog reset occurs.
During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK
cycles. (I/OD, ↑)
XRS
78
B8
The output buffer of this pin is an open-drain with an internal pullup (100 µA, typical). It is
recommended that this pin be driven by an open-drain device.
ADC SIGNALS
ADC Group A, Channel 7 input (I)
ADC Group A, Channel 6 input (I)
ADCINA7
ADCINA6
16
17
F3
F4
(1) I = Input, O = Output, Z = High impedance, OD = Open drain, ↑ = Pullup, ↓ = Pulldown
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Table 2-2. Signal Descriptions (continued)
PIN NO.
(1)
NAME
ADCINA5
DESCRIPTION
PZ PIN
GGM
#
BALL #
18
19
20
21
22
23
34
33
32
31
30
29
28
27
24
38
35
G4
G1
G2
G3
H1
H2
K5
H4
K4
J4
ADC Group A, Channel 5 input (I)
ADC Group A, Channel 4 input (I)
ADC Group A, Channel 3 input (I)
ADC Group A, Channel 2 input (I)
ADC Group A, Channel 1 input (I)
ADC Group A, Channel 0 input (I)
ADC Group B, Channel 7 input (I)
ADC Group B, Channel 6 input (I)
ADC Group B, Channel 5 input (I)
ADC Group B, Channel 4 input (I)
ADC Group B, Channel 3 input (I)
ADC Group B, Channel 2 input (I)
ADC Group B, Channel 1 input (I)
ADC Group B, Channel 0 input (I)
ADCINA4
ADCINA3
ADCINA2
ADCINA1
ADCINA0
ADCINB7
ADCINB6
ADCINB5
ADCINB4
ADCINB3
ADCINB2
ADCINB1
ADCINB0
ADCLO
K3
H3
J3
K2
J1
Low Reference (connect to analog ground) (I)
ADCRESEXT
ADCREFIN
F5
J5
ADC External Current Bias Resistor. Connect a 22-kΩ resistor to analog ground.
External reference input (I)
Internal Reference Positive Output. Requires a low ESR (50 mΩ - 1.5 Ω) ceramic bypass capacitor
of 2.2 µF to analog ground. (O)
ADCREFP
ADCREFM
37
36
G5
H5
Internal Reference Medium Output. Requires a low ESR (50 mΩ - 1.5 Ω) ceramic bypass capacitor
of 2.2 µF to analog ground. (O)
CPU AND I/O POWER PINS
ADC Analog Power Pin (3.3 V)
ADC Analog Ground Pin
VDDA2
VSSA2
VDDAIO
VSSAIO
VDD1A18
VSS1AGND
VDD2A18
VSS2AGND
VDD
15
14
26
25
12
13
40
39
10
42
59
68
85
93
3
F2
F1
J2
ADC Analog I/O Power Pin (3.3 V)
ADC Analog I/O Ground Pin
ADC Analog Power Pin (1.8 V)
ADC Analog Ground Pin
K1
E4
E5
J6
ADC Analog Power Pin (1.8 V)
ADC Analog Ground Pin
K6
E2
G6
F10
D7
B6
D4
C2
H7
E9
A7
VDD
VDD
CPU and Logic Digital Power Pins (1.8 V)
VDD
VDD
VDD
VDDIO
VDDIO
VDDIO
VDDIO
46
65
82
Digital I/O Power Pin (3.3 V)
16
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Table 2-2. Signal Descriptions (continued)
PIN NO.
(1)
NAME
DESCRIPTION
PZ PIN
GGM
#
BALL #
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
2
B1
E3
11
41
49
55
62
69
77
87
89
94
H6
K9
H10
F7
Digital Ground Pins
D10
A9
D6
A5
A4
GPIOA AND PERIPHERAL SIGNALS(2)
(3)
GPIO0
General purpose input/output 0 (I/O/Z)
EPWM1A
-
-
Enhanced PWM1 Output A and HRPWM channel (O)
-
-
General purpose input/output 1 (I/O/Z)(3)
Enhanced PWM1 Output B (O)
SPI-D slave in, master out (I/O) (not available on F2801/9501)
-
General purpose input/output 2 (I/O/Z)(3)
Enhanced PWM2 Output A and HRPWM channel (O)
-
-
General purpose input/output 3 (I/O/Z)(3)
Enhanced PWM2 Output B (O)
SPI-D slave out, master in (I/O) (not available on F2801/9501)
-
General purpose input/output 4 (I/O/Z)(3)
Enhanced PWM3 output A and HRPWM channel (O)
-
-
General purpose input/output 5 (I/O/Z)(3)
Enhanced PWM3 output B (O)
SPI-D clock (I/O) (not available on F2801/9501)
Enhanced capture input/output 1 (I/O)
General purpose input/output 6 (I/O/Z)(3)
Enhanced PWM4 output A and HRPWM channel (not available on F2801/9501) (O)
External ePWM sync pulse input (I)
External ePWM sync pulse output (O)
General purpose input/output 7 (I/O/Z)(3)
Enhanced PWM4 output B (not available on F2801/9501) (O)
SPI-D slave transmit enable (not available on F2801/9501 (I/O)
Enhanced capture input/output 2 (I/O)
General purpose input/output 8 (I/O/Z)(3)
Enhanced PWM5 output A (not available on F2801/9501) (O)
Enhanced CAN-B transmit (not available on F2806/F2801/9501) (O)
ADC start-of-conversion A (O)
General purpose input/output 9 (I/O/Z)(3)
47
44
45
48
51
53
56
58
60
61
K8
K7
J7
GPIO1
EPWM1B
SPISIMOD
-
GPIO2
EPWM2A
-
-
GPIO3
EPWM2B
SPISOMID
-
J8
GPIO4
EPWM3A
-
-
J9
GPIO5
EPWM3B
SPICLKD
ECAP1
H9
G9
G8
F9
F8
GPIO6
EPWM4A
EPWMSYNCI
EPWMSYNCO
GPIO7
EPWM4B
SPISTED
ECAP2
GPIO8
EPWM5A
CANTXB
ADCSOCAO
GPIO9
EPWM5B
SCITXDB
ECAP3
Enhanced PWM5 output B (not available on F2801/9501) (O)
SCI-B transmit data (not available on F2801/9501) (O)
Enhanced capture input/output 3 (not available on F2801/9501) (I/O)
(2) All GPIO pins are I/O/Z, 4-mA drive typical (unless otherwise indicated), and have an internal pullup, which can be selectively
enabled/disabled on a per-pin basis. This feature only applies to the GPIO pins. The GPIO function (shown in Italics) is the default at
reset. The peripheral signals that are listed under them are alternate functions.
(3) The pullups on GPIO0-GPIO11 pins are not enabled at reset.
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Table 2-2. Signal Descriptions (continued)
PIN NO.
(1)
NAME
GPIO10
DESCRIPTION
General purpose input/output 10 (I/O/Z)(3)
PZ PIN
GGM
#
BALL #
EPWM6A
CANRXB
ADCSOCBO
Enhanced PWM6 output A (not available on F2801/9501) (O)
Enhanced CAN-B receive (not available on F2806/F2801/9501) (I)
ADC start-of-conversion B (O)
General purpose input/output 11 (I/O/Z)(3)
Enhanced PWM6 output B (not available on F2801/9501) (O)
SCI-B receive data (not available on F2801/9501) (I)
Enhanced CAP Input/Output 4 (not available on F2801/9501) (I/O)
General purpose input/output 12 (I/O/Z)(4)
Trip Zone input 1 (I)
64
E10
D9
GPIO11
EPWM6B
SCIRXDB
ECAP4
70
1
GPIO12
TZ1
CANTXB
SPISIMOB
B2
Enhanced CAN-B transmit (not available on F2806/F2801/9501) (O)
SPI-B Slave in, Master out (I/O)
GPIO13
TZ2
CANRXB
SPISOMIB
General purpose input/output 13 (I/O/Z)(4)
Trip zone input 2 (I)
Enhanced CAN-B receive (not available on F2806/F2801/9501) (I)
SPI-B slave out, master in (I/O)
General purpose input/output 14 (I/O/Z)(4)
Trip zone input 3 (I)
SCI-B transmit (not available on F2801/9501) (O)
SPI-B clock input/output (I/O)
95
8
B4
GPIO14
TZ3
SCITXDB
SPICLKB
D3
GPIO15
TZ4
SCIRXDB
SPISTEB
General purpose input/output 15 (I/O/Z)(4)
Trip zone input (I)
SCI-B receive (not available on F2801/9501) (I)
SPI-B slave transmit enable (I/O)
9
E1
GPIO16
SPISIMOA
CANTXB
TZ5
General purpose input/output 16 (I/O/Z)(4)
SPI-A slave in, master out (I/O)
Enhanced CAN-B transmit (not available on F2806/F2801/9501) (O)
Trip zone input 5 (I)
General purpose input/output 17 (I/O/Z)(4)
SPI-A slave out, master in (I/O)
Enhanced CAN-B receive (not available on F2806/F2801/9501) (I)
Trip zone input 6(I)
50
52
K10
J10
GPIO17
SPISOMIA
CANRXB
TZ6
GPIO18
General purpose input/output 18 (I/O/Z)(4)
SPICLKA
SPI-A clock input/output (I/O)
SCITXDB
-
-
54
57
H8
SCI-B transmit (not available on F2801/9501) (O)
-
-
General purpose input/output 19 (I/O/Z)(4)
SPI-A slave transmit enable input/output (I/O)
GPIO19
SPISTEA
SCIRXDB
G10
SCI-B receive (not available on F2801/9501) (I)
-
-
-
-
GPIO20
General purpose input/output 20 (I/O/Z)(4)
EQEP1A
SPISIMOC
CANTXB
Enhanced QEP1 input A (I)
SPI-C slave in, master out (not available on F2801/9501) (I/O)
Enhanced CAN-B transmit (not available on F2806/F2801/9501) (O)
General purpose input/output 21 (I/O/Z)(4)
Enhanced QEP1 input A (I)
SPI-C master in, slave out (not available on F2801/9501) (I/O)
Enhanced CAN-B receive (not available on F2806/F2801/9501) (I)
General purpose input/output 22 (I/O/Z)(4)
Enhanced QEP1 strobe (I/O)
SPI-C clock (not available on F2801/9501) (I/O)
SCI-B transmit (not available on F2801/9501) (O)
General purpose input/output 23 (I/O/Z)(4)
Enhanced QEP1 index (I/O)
63
67
71
72
F6
E7
GPIO21
EQEP1B
SPISOMIC
CANRXB
GPIO22
EQEP1S
SPICLKC
SCITXDB
D8
GPIO23
EQEP1I
SPISTEC
SCIRXDB
C10
SPI-C slave transmit enable (not available on F2801/9501) (I/O)
SCI-B receive (I) (not available on F2801/9501)
(4) The pullups on GPIO12-GPIO34 are enabled upon reset.
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Table 2-2. Signal Descriptions (continued)
PIN NO.
(1)
NAME
DESCRIPTION
PZ PIN
GGM
#
BALL #
GPIO24
ECAP1
EQEP2A
SPISIMOB
General purpose input/output 24 (I/O/Z)(4)
Enhanced capture 1 (I/O)
Enhanced QEP2 input A (I) (not available on F2801/9501)
SPI-B slave in, master out (I/O)
General purpose input/output 25 (I/O/Z)(4)
Enhanced capture 2 (I/O)
Enhanced QEP2 input B (I) (not available on F2801/9501)
SPI-B master in, slave out (I/O)
General purpose input/output 26 (I/O/Z)(4)
Enhanced capture 3 (I/O) (not available on F2801/9501)
Enhanced QEP2 index (I/O) (not available on F2801/9501)
SPI-B clock (I/O)
General purpose input/output 27 (I/O/Z)(4)
Enhanced capture 4 (I/O) (not available on F2801/9501)
Enhanced QEP2 strobe (I/O) (not available on F2801)
SPI-B slave transmit enable (I/O)
83
C7
C5
A2
C8
D5
C3
D2
D1
A1
C1
G7
GPIO25
ECAP2
EQEP2B
SPISOMIB
91
99
79
92
4
GPIO26
ECAP3
EQEP2I
SPICLKB
GPIO27
ECAP4
EQEP2S
SPISTEB
GPIO28
SCIRXDA
-
General purpose input/output 28. This pin has an 8-mA (typical) output buffer. (I/O/Z)(4)
SCI receive data (I)
-
TZ5
Trip zone 5 (I)
GPIO29
SCITXDA
-
General purpose input/output 29. This pin has an 8-mA (typical) output buffer. (I/O/Z)(4)
SCI transmit data (O)
-
TZ6
Trip zone 6 (I)
GPIO30
CANRXA
-
-
General purpose input/output 30. This pin has an 8-mA (typical) output buffer. (I/O/Z)(4)
Enhanced CAN-A receive data (I)
-
-
General purpose input/output 31. This pin has an 8-mA (typical) output buffer. (I/O/Z)(4)
Enhanced CAN-A transmit data (O)
-
-
General purpose input/output 32 (I/O/Z)(4)
I2C data open-drain bidirectional port (I/OD)
Enhanced PWM external sync pulse input (I)
ADC start-of-conversion (O)
General-Purpose Input/Output 33 (I/O/Z)(4)
I2C clock open-drain bidirectional port (I/OD)
Enhanced PWM external synch pulse output (O)
ADC start-of-conversion (O)
General-Purpose Input/Output 34 (I/O/Z)(4)
-
-
-
6
GPIO31
CANTXA
-
-
7
GPIO32
SDAA
EPWMSYNCI
ADCSOCAO
100
5
GPIO33
SCLA
EPWMSYNCO
ADCSOCBO
GPIO34
-
-
-
43
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3
Functional Overview
Memory Bus
TINT0
TINT1
Real-Time JTAG
(TDI, TDO, TRST, TCK,
TMS, EMU0, EMU1)
32-bit CPU TIMER 0
7
32-bit CPU TIMER 1
32-bit CPU TIMER 2
TINT2
INT14
PIE
(A)
(96 Interrupts)
INT[12:1]
M0 SARAM
1 K y 16
NMI, INT13
M1 SARAM
1 K y 16
External Interrupt
Control
32
4
FIFO
SCI-A/B
L0 SARAM
4 K y 16
(0-wait)
16
2
FIFO
FIFO
SPI-A/B/C/D
2
(B)
I C-A
L1 SARAM
4 K y 16
4
8
(0-wait)
eCAN-A/B (32 mbox)
eQEP1/2
(C)
H0 SARAM
8 K y 16
(0-wait)
4
eCAP1/2/3/4
(4 timers 32-bit)
GPIOs
(35)
12
6
ROM
32K x 16 (C2802)
16K x 16 (C2801)
ePWM1/2/3/4/5/6
(12 PWM outputs,
6 trip zones,
C28x CPU
(100 MHz)
6 timers 16-bit)
FLASH
32
128K x 16 (F2809)
64K x 16 (F2808)
32K x 16 (F2806)
32K x 16 (F2802)
16K x 16 (F2801)
16K x 16 (9501)
16K x 16 (F2801x)
SYSCLKOUT
System Control
XCLKOUT
XRS
XCLKIN
RS
(Oscillator, PLL,
Peripheral Clocking,
Low Power Modes,
WatchDog)
CLKIN
X1
X2
(D)
OTP
1K y 16
ADCSOCA/B
SOCA/B
Boot ROM
4 K y 16
(1-wait state)
12-Bit ADC
16 Channels
Peripheral Bus
Protected by the code-security module.
A. 43 of the possible 96 interrupts are used on the devices.
B. Not available in F2801/9501
C. Not available in F2806 or F2801/9501
Figure 3-1. Functional Block Diagram
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3.1 Memory Map
Block Start
Address
Prog Space
Data Space
0x00 0000
M0 SARAM (1 K y 16)
0x00 0400
M1 SARAM (1 K y 16)
0x00 0800
0x00 0D00
Peripheral Frame 0
PIE Vector − RAM
(256 x 16)
(Enabled if ENPIE = 1)
0x00 0E00
0x00 6000
Peripheral Frame 1
(protected)
0x00 7000
0x00 8000
Peripheral Frame 2
(protected)
L0 SARAM (0-wait)
(4 k y 16, Secure Zone, Dual Mapped)
0x00 9000
0x00 A000
0x00 C000
L1 SARAM (0-wait)
(4 k y 16, Secure Zone, Dual Mapped)
H0 SARAM (0-wait)
(8 k y 16, Dual Mapped)
0x3D 7800
0x3D 7C00
0x3E 8000
OTP
(1 k y 16, Secure Zone)
FLASH
(64 k y 16, Secure Zone)
0x3F 7FF8
0x3F 8000
128-bit Password
L0 SARAM (0-wait)
(4 k y 16, Secure Zone, Dual Mapped)
0x3F 9000
0x3F A000
L1 SARAM (0-wait)
(4 k y 16, Secure Zone, Dual Mapped)
H0 SARAM (0-wait)
(8 k y 16, Dual Mapped)
0x3F C000
0x3F F000
Boot ROM (4 k y 16)
0x3F FFC0
Vectors (32 y 32)
(enabled if VMAP = 1, ENPIE = 0)
Reserved
A. Memory blocks are not to scale.
B. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only.
User program cannot access these memory maps in program space.
C. “ Protected” means the order of Write followed by Read operations is preserved rather than the pipeline order.
D. Certain memory ranges are EALLOW protected against spurious writes after configuration.
Figure 3-2. F2808 Memory Map
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Block Start
Address
Prog Space
Data Space
0x00 0000
M0 SARAM (1K y 16)
0x00 0400
0x00 0800
0x00 0D00
M1 SARAM (1K y 16)
Peripheral Frame 0
PIE Vector − RAM
(256 x 16)
(Enabled if ENPIE = 1)
0x00 0E00
0x00 6000
Peripheral Frame 1
(protected)
0x00 7000
0x00 8000
Peripheral Frame 2
(protected)
L0 SARAM (0-wait)
(4k y 16, Secure Zone, Dual Mapped)
0x00 9000
0x00 A000
L1 SARAM (0-wait)
(4k y 16, Secure Zone, Dual Mapped)
0x3D 7800
0x3D 7C00
OTP
(1 K y 16, Secure Zone)
0x3F 0000
FLASH
(32 K y 16, Secure Zone)
0x3F 7FF8
0x3F 8000
128-bit Password
L0 SARAM (0-wait) (4k y 16,
Secure Zone, Dual Mapped)
0x3F 9000
0x3F A000
L1 SARAM (0-wait) (4k y 16,
Secure Zone, Dual Mapped)
0x3F F000
0x3F FFC0
Boot ROM (4 K y 16)
Vectors (32 y 32)
(enabled if VMAP = 1, ENPIE = 0)
Reserved
A. Memory blocks are not to scale.
B. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only.
User program cannot access these memory maps in program space.
C. “ Protected” means the order of Write followed by Read operations is preserved rather than the pipeline order.
D. Certain memory ranges are EALLOW protected against spurious writes after configuration.
Figure 3-3. F2806 Memory Map
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Block Start
Address
Data Space
Prog Space
0x00 0000
M0 SARAM (1K y 16)
0x00 0400
M1 SARAM (1K y 16)
0x00 0800
0x00 0D00
Peripheral Frame 0
PIE Vector − RAM
(256 x 16)
(Enabled if ENPIE = 1)
0x00 0E00
0x00 6000
Peripheral Frame 1
(protected)
0x00 7000
0x00 8000
0x00 9000
Peripheral Frame 2
(protected)
L0 SARAM (0-wait)
(4K y 16, Secure Zone, Dual Mapped)
0x3D 7800
0x3D 7C00
(A)
OTP (F2801/9501 Only)
(1K y 16, Secure Zone)
0x3F 4000
FLASH (F2801/9501) or ROM (C2801)
(16K y 16, Secure Zone)
0x3F 7FF8
0x3F 8000
128-bit Password
L0 (0-wait)
(4K y 16, Secure Zone, Dual Mapped)
0x3F 9000
0x3F F000
0x3F FFC0
Boot ROM (4K y 16)
Vectors (32 y 32)
(enabled if VMAP = 1, ENPIE = 0)
Reserved
A. Memory blocks are not to scale.
B. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only.
User program cannot access these memory maps in program space.
C. “ Protected” means the order of Write followed by Read operations is preserved rather than the pipeline order.
D. Certain memory ranges are EALLOW protected against spurious writes after configuration.
Figure 3-4. F2801/9501 Memory Map
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Table 3-1. Addresses of Flash Sectors in F2808
ADDRESS RANGE
PROGRAM AND DATA SPACE
0x3E 8000
0x3E BFFF
Sector D (16K x 16)
Sector C (16K x 16)
Sector B (16K x 16)
Sector A (16K x 16)
0x3E C000
0x3E FFFF
0x3F 0000
0x3F 3FFF
0x3F 4000
0x3F 7F7F
0x3F 7F80
0x3F 7FF5
Program to 0x0000 when using the
Code Security Module
0x3F 7FF6
0x3F 7FF7
Boot-to-Flash Entry Point
(program branch instruction here)
0x3F 7FF8
0x3F 7FFF
Security Password (128-Bit)
(Do not program to all zeros)
Table 3-2. Addresses of Flash Sectors in F2806
ADDRESS RANGE
PROGRAM AND DATA SPACE
0x3F 0000
0x3F 1FFF
Sector D (8K x 16)
Sector C (8K x 16)
Sector B (8K x 16)
Sector A (8K x 16)
0x3F 2000
0x3F 3FFF
0x3F 4000
0x3F 5FFF
0x3F 6000
0x3F 7F7F
0x3F 7F80
0x3F 7FF5
Program to 0x0000 when using the
Code Security Module
0x3F 7FF6
0x3F 7FF7
Boot-to-Flash Entry Point
(program branch instruction here)
0x3F 7FF8
0x3F 7FFF
Security Password (128-Bit)
(Do not program to all zeros)
Table 3-3. Addresses of Flash Sectors in F2801/9501
ADDRESS RANGE
PROGRAM AND DATA SPACE
0x3F 4000
0x3F 4FFF
Sector D (4K x 16)
0x3F 5000
0x3F 5FFF
Sector C (4K x 16)
Sector B (4K x 16)
Sector A (4K x 16)
0x3F 6000
0x3F 6FFF
0x3F 7000
0x3F 7F7F
0x3F 7F80
0x3F 7FF5
Program to 0x0000 when using the
Code Security Module
0x3F 7FF6
0x3F 7FF7
Boot-to-Flash Entry Point
(program branch instruction here)
0x3F 7FF8
0x3F 7FFF
Security Password (128-Bit)
(Do not program to all zeros)
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NOTE
For code security operation, all addresses between 0x3F7F80 and 0x3F7FF5 cannot be
used as program code or data, but must be programmed to 0x0000 when the
code-security passwords are programmed. If security is not a concern, addresses
0x3F7F80 through 0x3F7FEF may be used for code or data. Addresses 0x3F7FF0 –
0x3F7FF5 are reserved for data variables and should not contain program code.
Peripheral Frame 1 and Peripheral Frame 2 are grouped together so as to enable these blocks to be
write/read peripheral block protected. The protected mode ensures that all accesses to these blocks
happen as written. Because of the C28x pipeline, a write immediately followed by a read, to different
memory locations, appears in reverse order on the memory bus of the CPU. This can cause problems in
certain peripheral applications where the user expected the write to occur first (as written). The C28x CPU
supports a block protection mode where a region of memory can be protected so as to make sure that
operations occur as written (the penalty is extra cycles are added to align the operations). This mode is
programmable and by default, it protects the selected zones.
The wait states for the various spaces in the memory map area are listed in Table 3-4.
Table 3-4. Wait States
AREA
WAIT-STATES COMMENTS
M0 and M1 SARAMs
Peripheral Frame 0
0-wait
0-wait
Fixed
Fixed
0-wait (writes)
2-wait (reads)
Peripheral Frame 1
Fixed. The eCAN peripheral can extend a cycle as needed.
Fixed
0-wait (writes)
2-wait (reads)
Peripheral Frame 2
L0 & L1 SARAMs
0-wait
Programmed via the Flash registers. 1-wait-state operation
is possible at a reduced CPU frequency. See Section
Section 3.2.5 for more information.
Programmable,
1-wait minimum
OTP
Programmed via the Flash registers. 0-wait-state operation
Programmable, is possible at reduced CPU frequency. The CSM password
0-wait minimum locations are hardwired for 16 wait-states. See Section
Section 3.2.5 for more information.
Flash
H0 SARAM
Boot-ROM
0-wait
1-wait
Fixed
Fixed
3.2 Brief Descriptions
3.2.1 C28x CPU
The C28x™ DSP generation is the newest member of the TMS320C2000™ DSP platform. The C28x is an
efficient C/C++ engine, hence enabling users to develop not only their system control software in a
high-level language, but also enables math algorithms to be developed using C/C++. The C28x is as
efficient in DSP math tasks as it is in system control tasks that typically are handled by microcontroller
devices. This efficiency removes the need for a second processor in many systems. The 32 x 32-bit MAC
capabilities of the C28x and its 64-bit processing capabilities, enable the C28x to efficiently handle higher
numerical resolution problems that would otherwise demand a more expensive floating-point processor
solution. Add to this the fast interrupt response with automatic context save of critical registers, resulting in
a device that is capable of servicing many asynchronous events with minimal latency. The C28x has an
8-level-deep protected pipeline with pipelined memory accesses. This pipelining enables the C28x to
execute at high speeds without resorting to expensive high-speed memories. Special branch-look-ahead
hardware minimizes the latency for conditional discontinuities. Special store conditional operations further
improve performance.
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3.2.2 Memory Bus (Harvard Bus Architecture)
As with many DSP type devices, multiple busses are used to move data between the memories and
peripherals and the CPU. The C28x memory bus architecture contains a program read bus, data read bus
and data write bus. The program read bus consists of 22 address lines and 32 data lines. The data read
and write busses consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable
single cycle 32-bit operations. The multiple bus architecture, commonly termed "Harvard Bus", enables the
C28x to fetch an instruction, read a data value and write a data value in a single cycle. All peripherals and
memories attached to the memory bus will prioritize memory accesses. Generally, the priority of memory
bus accesses can be summarized as follows:
Highest:
Data Writes
(Simultaneous data and program writes cannot occur on the memory bus.)
Program Writes (Simultaneous data and program writes cannot occur on the memory bus.)
Data Reads
Program Reads (Simultaneous program reads and fetches cannot occur on the memory bus.)
Lowest:
Fetches
(Simultaneous program reads and fetches cannot occur on the memory bus.)
3.2.3 Peripheral Bus
To enable migration of peripherals between various Texas Instruments DSP family of devices, the 280x
devices adopt a peripheral bus standard for peripheral interconnect. The peripheral bus bridge multiplexes
the various busses that make up the processor Memory Bus into a single bus consisting of 16 address
lines and 16 or 32 data lines and associated control signals. Two versions of the peripheral bus are
supported on the 280x. One version only supports 16-bit accesses (called peripheral frame 2). The other
version supports both 16- and 32-bit accesses (called peripheral frame 1).
3.2.4 Real-Time JTAG and Analysis
The 280x implements the standard IEEE 1149.1 JTAG interface. Additionally, the 280x supports real-time
mode of operation whereby the contents of memory, peripheral and register locations can be modified
while the processor is running and executing code and servicing interrupts. The user can also single step
through non-time critical code while enabling time-critical interrupts to be serviced without interference.
The 280x implements the real-time mode in hardware within the CPU. This is a unique feature to the
280x, no software monitor is required. Additionally, special analysis hardware is provided which allows the
user to set hardware breakpoint or data/address watch-points and generate various user-selectable break
events when a match occurs.
3.2.5 Flash
The F2808 contains 64K x 16 of embedded flash memory, segregated into four 16K X 16 sectors. The
F2806 has 32K X 16 of embedded flash, segregated into four 8K X 16 sectors. The F2801/UCD9501
devices contain 16K X 16 of embedded Flash (four 4K X 16 sectors). All three devices also contain a
single 1K x 16 of OTP memory at address range 0x3D 7800 - 0x3D 7BFF. The user can individually
erase, program, and validate a flash sector while leaving other sectors untouched. However, it is not
possible to use one sector of the flash or the OTP to execute flash algorithms that erase/program other
sectors. Special memory pipelining is provided to enable the flash module to achieve higher performance.
The flash/OTP is mapped to both program and data space; therefore, it can be used to execute code or
store data information. Note that addresses 0x3F7FF0 - 0x3F7FF5 are reserved for data variables and
should not contain program code.
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NOTE
The F2808/F2806/F2801 Flash and OTP wait states can be configured by the application.
This allows applications running at slower frequencies to configure the flash to use fewer
wait states.
Flash effective performance can be improved by enabling the flash pipeline mode in the
Flash options register. With this mode enabled, effective performance of linear code
execution will be much faster than the raw performance indicated by the wait state
configuration alone. The exact performance gain when using the Flash pipeline mode is
application-dependent.
For more information on the Flash options, Flash wait-state, and OTP wait-state registers,
see the TMS320x280x System Control and Interrupts Reference Guide (literature number
SPRU712).
3.2.6 M0, M1 SARAMs
All 280x devices contain these two blocks of single access memory, each 1K x 16 in size. The stack
pointer points to the beginning of block M1 on reset. The M0 and M1 blocks, like all other memory blocks
on C28x devices, are mapped to both program and data space. Hence, the user can use M0 and M1 to
execute code or for data variables. The partitioning is performed within the linker. The C28x device
presents a unified memory map to the programmer. This makes for easier programming in high-level
languages.
3.2.7 L0, L1, H0 SARAMs
The F2808 contains an additional 16K x 16 of single-access RAM, divided into 3 blocks (L0-4K, L1-4K,
H0-8K). The F2806 contains an additional 8K x 16 of single-access RAM, divided into 2 blocks (L0-4K,
L1-4K). The F2801/UCD9501 contain an additional 4K x 16 of single-access RAM (L0-4K). Each block
can be independently accessed to minimize CPU pipeline stalls. Each block is mapped to both program
and data space.
3.2.8 Boot ROM
The Boot ROM is factory-programmed with boot-loading software. Boot-mode signals are provided to tell
the bootloader software what boot mode to use on power up. The user can select to boot normally or to
download new software from an external connection or to select boot software that is programmed in the
internal Flash. The Boot ROM also contains standard tables, such as SIN/COS waveforms, for use in
math related algorithms.
Table 3-5. Boot Mode Selection
GPIO18
SPICLKA
SCITXDB
GPIO29
SCITXDA
GPIO34
MODE
Boot to Flash
DESCRIPTION
Jump to Flash address 0x3F 7FF6
1
1
1
You must have programmed a branch instruction here prior
to reset to redirect code execution as desired.
SCI-A Boot
SPI-A Boot
I2C Boot
Load a data stream from SCI-A
1
1
1
1
0
0
0
1
0
Load from an external serial SPI EEPROM on SPI-A
Load data from an external EEPROM at address 0x50 on
the I2C bus
eCAN-A Boot
Call CAN_Boot to load from eCAN-A mailbox 1.
Jump to M0 SARAM address 0x00 0000.
Jump to OTP address 0x3D 7800
0
0
0
0
1
1
0
0
1
0
1
0
Boot to M0 SARAM
Boot to OTP
Parallel I/O Boot
Load data from GPIO0 - GPIO15
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3.2.9 Security
The 280x devices support high levels of security to protect the user firmware from being reverse
engineered. The security features a 128-bit password (hardcoded for 16 wait states), which the user
programs into the flash. One code security module (CSM) is used to protect the flash/OTP and the L0/L1
SARAM blocks. The security feature prevents unauthorized users from examining the memory contents
via the JTAG port, executing code from external memory or trying to boot-load some undesirable software
that would export the secure memory contents. To enable access to the secure blocks, the user must
write the correct 128-bit "KEY" value, which matches the value stored in the password locations within the
Flash.
NOTE
For code security operation, all addresses between 0x3F7F80 and 0x3F7FF5 cannot be
used as program code or data, but must be programmed to 0x0000 when the Code
Security Password is programmed. If security is not a concern, addresses 0x3F7F80
through 0x3F7FEF may be used for code or data. Addresses 0x3F7FF0 – 0x3F7FF5 are
reserved for data variables and should not contain program code.
The 128-bit password (at 0x3F 7FF8 - 0x3F 7FFF) must not be programmed to zeros.
Doing so would permanently lock the device.
NOTE
Code Security Module Disclaimer
The Code Security Module ("CSM") included on this device was designed to password
protect the data stored in the associated memory (either ROM or Flash) and is warranted
by Texas Instruments (Texas Instruments), in accordance with its standard terms and
conditions, to conform to TI's published specifications for the warranty period applicable
for this device.
Texas Instruments DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE
CSM CANNOT BE COMPROMISED OR BREACHED OR THAT THE DATA STORED IN
THE ASSOCIATED MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS.
MOREOVER, EXCEPT AS SET FORTH ABOVE, Texas Instruments MAKES NO
WARRANTIES OR REPRESENTATIONS CONCERNING THE CSM OR OPERATION
OF THIS DEVICE, INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY
OR FITNESS FOR A PARTICULAR PURPOSE.
IN NO EVENT SHALL Texas Instruments BE LIABLE FOR ANY CONSEQUENTIAL,
SPECIAL, INDIRECT, INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED,
ARISING IN ANY WAY OUT OF YOUR USE OF THE CSM OR THIS DEVICE,
WHETHER OR NOT Texas Instruments HAS BEEN ADVISED OF THE POSSIBILITY OF
SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO
LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR INTERRUPTION OF
BUSINESS OR OTHER ECONOMIC LOSS.
3.2.10 Peripheral Interrupt Expansion (PIE) Block
The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The
PIE block can support up to 96 peripheral interrupts. On the 280x, 43 of the possible 96 interrupts are
used by peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12
CPU interrupt lines (INT1 to INT12). Each of the 96 interrupts is supported by its own vector stored in a
dedicated RAM block that can be overwritten by the user. The vector is automatically fetched by the CPU
on servicing the interrupt. It takes 8 CPU clock cycles to fetch the vector and save critical CPU registers.
Hence the CPU can quickly respond to interrupt events. Prioritization of interrupts is controlled in
hardware and software. Each individual interrupt can be enabled/disabled within the PIE block.
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3.2.11 External Interrupts (XINT1, XINT2, XNMI)
The 280x supports three masked external interrupts (XINT1, XINT2, XNMI). XNMI can be connected to
the INT13 or NMI interrupt of the CPU. Each of the interrupts can be selected for negative, positive, or
both negative and positive edge triggering and can also be enabled/disabled (including the XNMI). The
masked interrupts also contain a 16-bit free running up counter, which is reset to zero when a valid
interrupt edge is detected. This counter can be used to accurately time stamp the interrupt. Unlike the
281x devices, there are no dedicated pins for the external interrupts. Rather, any Port A GPIO pin can be
configured to trigger any external interrupt.
3.2.12 Oscillator and PLL
The 280x can be clocked by an external oscillator or by a crystal attached to the on-chip oscillator circuit.
A PLL is provided supporting up to 10 input-clock-scaling ratios. The PLL ratios can be changed on-the-fly
in software, enabling the user to scale back on operating frequency if lower power operation is desired.
Refer to the Electrical Specification section for timing details. The PLL block can be set in bypass mode.
3.2.13 Watchdog
The 280x devices contain a watchdog timer. The user software must regularly reset the watchdog counter
within a certain time frame; otherwise, the watchdog will generate a reset to the processor. The watchdog
can be disabled if necessary.
3.2.14 Peripheral Clocking
The clocks to each individual peripheral can be enabled/disabled so as to reduce power consumption
when a peripheral is not in use. Additionally, the system clock to the serial ports (except eCAN) and the
ADC blocks can be scaled relative to the CPU clock. This enables the timing of peripherals to be
decoupled from increasing CPU clock speeds.
3.2.15 Low-Power Modes
The 280x devices are full static CMOS devices. Three low-power modes are provided:
IDLE:
Place CPU into low-power mode. Peripheral clocks may be turned off selectively and only
those peripherals that need to function during IDLE are left operating. An enabled interrupt
from an active peripheral or the watchdog timer will wake the processor from IDLE mode.
STANDBY: Turn off clock to CPU and peripherals. This mode leaves the oscillator and PLL functional.
An external interrupt event will wake the processor and the peripherals. Execution begins
on the next valid cycle after detection of the interrupt event
HALT:
Turn off oscillator. This mode basically shuts down the device and places it in the lowest
possible power consumption mode. A reset or external signal can wake the device from
this mode.
3.2.16 Peripheral Frames 0, 1, 2 (PFn)
The 280x segregate peripherals into three sections. The mapping of peripherals is as follows:
PF0: PIE:
Flash:
PIE Interrupt Enable and Control Registers Plus PIE Vector Table
Flash Control, Programming, Erase, Verify Registers
CPU-Timers 0, 1, 2 Registers
Timers:
CSM:
Code Security Module KEY Registers
ADC:
ADC Result Registers (dual-mapped)
PF1: eCAN:
GPIO:
eCAN Mailbox and Control Registers
GPIO MUX Configuration and Control Registers
Enhanced Pulse Width Modulator Module and Registers
ePWM:
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eCAP:
eQEP:
Enhanced Capture Module and Registers
Enhanced Quadrature Encoder Pulse Module and Registers
System Control Registers
PF2: SYS:
SCI:
Serial Communications Interface (SCI) Control and RX/TX Registers
Serial Port Interface (SPI) Control and RX/TX Registers
ADC Status, Control, and Result Register
SPI:
ADC:
I2C:
Inter-Integrated Circuit Module and Registers
3.2.17 General-Purpose Input/Output (GPIO) Multiplexer
Most of the peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. This
enables the user to use a pin as GPIO if the peripheral signal or function is not used. On reset, GPIO pins
are configured as inputs. The user can individually program each pin for GPIO mode or peripheral signal
mode. For specific inputs, the user can also select the number of input qualification cycles. This is to filter
unwanted noise glitches. The GPIO signals can also be used to bring the device out of specific low-power
modes.
3.2.18 32-Bit CPU-Timers (0, 1, 2)
CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock
prescaling. The timers have a 32-bit count down register, which generates an interrupt when the counter
reaches zero. The counter is decremented at the CPU clock speed divided by the prescale value setting.
When the counter reaches zero, it is automatically reloaded with a 32-bit period value. CPU-Timer 2 is
reserved for Real-Time OS (RTOS)/BIOS applications. CPU-Timer 1 is also reserved for Texas
Instruments system functions. CPU-Timer 2 is connected to INT14 of the CPU. CPU-Timer 1 can be
connected to INT13 of the CPU. CPU-Timer 0 is for general use and is connected to the PIE block.
3.2.19 Control Peripherals
The 280x devices support the following peripherals which are used for embedded control and
communication:
ePWM:
eCAP:
eQEP:
The enhanced PWM peripheral supports independent/complementary PWM generation,
adjustable dead-band generation for leading/trailing edges, latched/cycle-by-cycle trip
mechanism. Some of the PWM pins support HRPWM features.
The enhanced capture peripheral uses a 32-bit time base and registers up to four
programmable events in continuous/one-shot capture modes.
This peripheral can also be configured to generate an auxiliary PWM signal.
The enhanced QEP peripheral uses a 32-bit position counter, supports low-speed
measurement using capture unit and high-speed measurement using a 32-bit unit timer.
This peripheral has a watchdog timer to detect motor stall and input error detection logic
to identify simultaneous edge transition in QEP signals.
ADC:
The ADC block is a 12-bit converter, single ended, 16-channels. It contains two
sample-and-hold units for simultaneous sampling.
3.2.20 Serial Port Peripherals
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The 280x devices support the following serial communication peripherals:
eCAN:
This is the enhanced version of the CAN peripheral. It supports 32 mailboxes, time
stamping of messages, and is CAN 2.0B-compliant.
SPI:
The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of
programmed length (one to sixteen bits) to be shifted into and out of the device at a
programmable bit-transfer rate. Normally, the SPI is used for communications between the
DSP controller and external peripherals or another processor. Typical applications include
external I/O or peripheral expansion through devices such as shift registers, display
drivers, and ADCs. Multi-device communications are supported by the master/slave
operation of the SPI. On the 280x, the SPI contains a 16-level receive and transmit FIFO
for reducing interrupt servicing overhead.
SCI:
I2C:
The serial communications interface is a two-wire asynchronous serial port, commonly
known as UART. On the 280x, the SCI contains a 16-level receive and transmit FIFO for
reducing interrupt servicing overhead.
The inter-integrated circuit (I2C) module provides an interface between a DSP and other
devices compliant with Philips Semiconductors Inter-IC bus (I2C-bus) specification version
2.1 and connected by way of an I2C-bus. External components attached to this 2-wire
serial bus can transmit/receive up to 8-bit data to/from the DSP through the I2C module.
On the 280x, the I2C contains a 16-level receive and transmit FIFO for reducing interrupt
servicing overhead.
3.3 Register Map
The 280x devices contain three peripheral register spaces. The spaces are categorized as follows:
Peripheral
Frame 0:
These are peripherals that are mapped directly to the CPU memory bus.
See Table 3-6
Peripheral
Frame 1
These are peripherals that are mapped to the 32-bit peripheral bus.
See Table 3-7
Peripheral
Frame 2:
These are peripherals that are mapped to the 16-bit peripheral bus.
See Table 3-8
Table 3-6. Peripheral Frame 0 Registers(1)(2)
NAME
ADDRESS RANGE
SIZE (x16) ACCESS TYPE(3)
0x0880
0x09FF
Device Emulation Registers
384
96
EALLOW protected
0x0A80
0x0ADF
EALLOW protected
CSM Protected
FLASH Registers(4)
0x0AE0
0x0AEF
Code Security Module Registers
16
EALLOW protected
ADC Result Registers
(dual-mapped)
0xB00
0xB0F
16
Not EALLOW protected
Not EALLOW protected
Not EALLOW protected
EALLOW protected
0x0C00
0x0C3F
CPU-TIMER0/1/2 Registers
PIE Registers
64
0x0CE0
0x0CFF
32
0x0D00
0x0DFF
PIE Vector Table
256
(1) Registers in Frame 0 support 16-bit and 32-bit accesses.
(2) Missing segments of memory space are reserved and should not be used in applications.
(3) If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction
disables writes to prevent stray code or pointers from corrupting register contents.
(4) The Flash Registers are also protected by the Code Security Module (CSM).
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Table 3-7. Peripheral Frame 1 Registers(1)(2)
NAME
ADDRESS RANGE
SIZE (x16)
ACCESS TYPE
0x6000
0x60FF
256
(128 x 32)
Some eCAN control registers (and selected bits in other eCAN
control registers) are EALLOW-protected.
eCANA Registers
0x6100
0x61FF
256
(128 x 32)
eCANA Mailbox RAM
eCANB Registers
eCANB Mailbox RAM
ePWM1 Registers
ePWM2 Registers
ePWM3 Registers
ePWM4 Registers
ePWM5 Registers
ePWM6 Registers
eCAP1 Registers
eCAP2 Registers
eCAP3 Registers
eCAP4 Registers
eQEP1 Registers
eQEP2 Registers
GPIO Control Registers
GPIO Data Registers
Not EALLOW-protected
0x6200
0x62FF
256
(128 x 32)
Some eCAN control registers (and selected bits in other eCAN
control registers) are EALLOW-protected.
0x6300
0x63FF
256
(128 x 32)
Not EALLOW-protected
0x6800
0x683F
64
(32 x 32)
Some ePWM registers are EALLOW protected.
See Table 4-2
0x6840
0x687F
64
(32 x 32)
Some ePWM registers are EALLOW protected.
See Table 4-2.
0x6880
0x68BF
64
(32 x 32)
Some ePWM registers are EALLOW protected.
See Table 4-2.
0x68C0
0x68FF
64
(32 x 32)
Some ePWM registers are EALLOW protected.
See Table 4-2.
0x6900
0x693F
64
(32 x 32)
Some ePWM registers are EALLOW protected.
See Table 4-2.
0x6940
0x697F
64
(32 x 32)
Some ePWM registers are EALLOW protected.
See Table 4-2.
0x6A00
0x6A1F
32
(16 x 32)
Not EALLOW protected
Not EALLOW protected
Not EALLOW protected
Not EALLOW protected
Not EALLOW protected
Not EALLOW protected
EALLOW protected
0x6A20
0x6A3F
32
(16 x 32)
0x6A40
0x6A5F
32
(16 x 32)
0x6A60
0x6A7F
32
(16 x 32)
0x6B00
0x6B3F
64
(32 x 32)
0x6B40
0x6B7F
64
(32 x 32)
0x6F80
0x6FBF
128
(64 x 32)
0x6FC0
0x6FDF
32
(16 x 32)
Not EALLOW protected
EALLOW protected
GPIO Interrupt and LPM
Select Registers
0x6FE0
0x6FFF
32
(16 x 32)
(1) The eCAN control registers only support 32-bit read/write operations. All 32-bit accesses are aligned to even address boundaries.
(2) Missing segments of memory space are reserved and should not be used in applications.
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Table 3-8. Peripheral Frame 2 Registers(1)(2)
NAME
ADDRESS RANGE
SIZE (x16)
ACCESS TYPE
0x7010
0x702F
System Control Registers
SPI-A Registers
32
EALLOW Protected
0x7040
0x704F
16
16
16
32
16
16
16
16
48
Not EALLOW Protected
Not EALLOW Protected
Not EALLOW Protected
Not EALLOW Protected
Not EALLOW Protected
Not EALLOW Protected
Not EALLOW Protected
Not EALLOW Protected
Not EALLOW Protected
0x7050
0x705F
SCI-A Registers
0x7070
0x707F
External Interrupt Registers
ADC Registers
0x7100
0x711F
0x7740
0x774F
SPI-B Registers
0x7750
0x775F
SCI-B Registers
0x7760
0x776F
SPI-C Registers
0x7780
0x778F
SPI-D Registers
0x7900
0x792F
I2C Registers
(1) Peripheral Frame 2 only allows 16-bit accesses. All 32-bit accesses are ignored (invalid data may be returned or written).
(2) Missing segments of memory space are reserved and should not be used in applications.
3.4 Device Emulation Registers
These registers are used to control the protection mode of the C28x CPU and to monitor some critical
device signals. The registers are defined in Table 3-9.
Table 3-9. Device Emulation Registers
ADDRESS
RANGE
NAME
SIZE (x16)
DESCRIPTION
0x0880
0x0881
DEVICECNF
PARTID
2
1
Device Configuration Register
0x0882
Part ID Register
0x002C(1) - F2801/9501
0x0034 - F2806
0x003C - F2808
REVID
0x0883
1
Revision ID Register
0x0000 - Silicon Rev. 0 - TMX
0x0001 - Silicon Rev. A - TMX
0x0002 - Silicon Rev. B - TMS
PROTSTART
PROTRANGE
0x0884
0x0885
1
1
Block Protection Start Address Register
Block Protection Range Address Register
(1) The first byte (00) denotes flash devices. "FF" is reserved for future ROM devices. Other values are reserved for future devices.
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3.5 Interrupts
Figure 3-5 shows how the various interrupt sources are multiplexed within the 280x devices.
Peripherals
2
(SPI, SCI, I C, eCAN, ePWM, eCAP, eQEP, ADC)
WDINT
Watchdog
Low Power Modes
WAKEINT
XINT1
LPMINT
XINT1
Interrupt Control
XINT1CR(15:0)
XINT1CTR(15:0)
INT1 to
INT12
GPIOXINT1SEL(4:0)
XINT2SOC
ADC
XINT2
XINT2
Interrupt Control
XINT2CR(15:0)
XINT2CTR(15:0)
C28
CPU
GPIOXINT2SEL(4:0)
TINT0
CPU TIMER 0
TINT2
TINT1
CPU TIMER 2 (for TI/RTOS)
CPU TIMER 1 (for TI)
INT14
INT13
int13_select
nmi_select
GPIO0.int
XNMI_XINT13
GPIO
MUX
Interrupt Control
XNMICR(15:0)
XNMICTR(15:0)
NMI
GPIO31.int
1
GPIOXNMISEL(4:0)
Figure 3-5. External and PIE Interrupt Sources
Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with 8
interrupts per group equals 96 possible interrupts. On the 280x, 43 of these are used by peripherals as
shown in Table 3-10.
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IFR(12:1)
IER(12:1)
INTM
INT1
INT2
1
CPU
MUX
0
INT11
INT12
Global
Enable
(Flag)
(Enable)
INTx.1
INTx.2
INTx.3
INTx.4
INTx.5
From
Peripherals or
External
INTx
MUX
INTx.6
INTx.7
INTx.8
Interrupts
PIEACKx
(Enable)
(Flag)
(Enable/Flag)
PIEIERx(8:1)
PIEIFRx(8:1)
Figure 3-6. Multiplexing of Interrupts Using the PIE Block
Table 3-10. PIE Peripheral Interrupts(1)
PIE INTERRUPTS
CPU
INTERRUPTS
INTx.8
INTx.7
INTx.6
INTx.5
INTx.4
INTx.3
INTx.2
INTx.1
WAKEINT
(LPM/WD)
TINT0
(TIMER 0)
ADCINT
(ADC)
SEQ2INT
(ADC)
SEQ1INT
(ADC)
INT1
INT2
INT3
INT4
INT5
XINT2
XINT1
reserved
EPWM6_TZINT EPWM5_TZINT EPWM4_TZINT EPWM3_TZINT EPWM2_TZINT EPWM1_TZINT
(ePWM6)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
(ePWM5)
(ePWM4)
(ePWM3)
(ePWM2)
(ePWM1)
EPWM6_INT
(ePWM6)
EPWM5_INT
(ePWM5)
EPWM4_INT
(ePWM4)
EPWM3_INT
(ePWM3)
EPWM2_INT
(ePWM2)
EPWM1_INT
(ePWM1)
ECAP4_INT
(eCAP4)
ECAP3_INT
(eCAP3)
ECAP2_INT
(eCAP2)
ECAP1_INT
(eCAP1)
reserved
reserved
reserved
reserved
EQEP2_INT
(eQEP2)
EQEP1_INT
(eQEP1)
reserved
reserved
SPITXINTD
(SPI-D)
SPIRXINTD
(SPI-D)
SPITXINTC
(SPI-C)
SPIRXINTC
(SPI-C)
SPITXINTB
(SPI-B)
SPIRXINTB
(SPI-B)
SPITXINTA
(SPI-A)
SPIRXINTA
(SPI-A)
INT6
INT7
INT8
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
I2CINT2A
(I2C-A)
I2CINT1A
(I2C-A)
ECAN1_INTB
(CAN-B)
ECAN0_INTB
(CAN-B)
ECAN1_INTA
(CAN-A)
ECAN0_INTA
(CAN-A)
SCITXINTB
(SCI-B)
SCIRXINTB
(SCI-B)
SCITXINTA
(SCI-A)
SCIRXINTA
(SCI-A)
INT9
INT10
INT11
INT12
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
(1) Out of the 96 possible interrupts, 43 interrupts are currently used. The remaining interrupts are reserved for future devices. These
interrupts can be used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is
being used by a peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while
modifying the PIEIFR. To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts:
1) No peripheral within the group is asserting interrupts.
2) No peripheral interrupts are assigned to the group (example PIE group 12).
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Table 3-11. PIE Configuration and Control Registers
NAME
PIECTRL
PIEACK
PIEIER1
PIEIFR1
PIEIER2
PIEIFR2
PIEIER3
PIEIFR3
PIEIER4
PIEIFR4
PIEIER5
PIEIFR5
PIEIER6
PIEIFR6
PIEIER7
PIEIFR7
PIEIER8
PIEIFR8
PIEIER9
PIEIFR9
PIEIER10
PIEIFR10
PIEIER11
PIEIFR11
PIEIER12
PIEIFR12
Reserved
ADDRESS
0x0CE0
0x0CE1
0x0CE2
0x0CE3
0x0CE4
0x0CE5
0x0CE6
0x0CE7
0x0CE8
0x0CE9
0x0CEA
0x0CEB
0x0CEC
0x0CED
0x0CEE
0x0CEF
0x0CF0
0x0CF1
0x0CF2
0x0CF3
0x0CF4
0x0CF5
0x0CF6
0x0CF7
0x0CF8
0x0CF9
SIZE (X16)
DESCRIPTION(1)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
6
PIE, Control Register
PIE, Acknowledge Register
PIE, INT1 Group Enable Register
PIE, INT1 Group Flag Register
PIE, INT2 Group Enable Register
PIE, INT2 Group Flag Register
PIE, INT3 Group Enable Register
PIE, INT3 Group Flag Register
PIE, INT4 Group Enable Register
PIE, INT4 Group Flag Register
PIE, INT5 Group Enable Register
PIE, INT5 Group Flag Register
PIE, INT6 Group Enable Register
PIE, INT6 Group Flag Register
PIE, INT7 Group Enable Register
PIE, INT7 Group Flag Register
PIE, INT8 Group Enable Register
PIE, INT8 Group Flag Register
PIE, INT9 Group Enable Register
PIE, INT9 Group Flag Register
PIE, INT10 Group Enable Register
PIE, INT10 Group Flag Register
PIE, INT11 Group Enable Register
PIE, INT11 Group Flag Register
PIE, INT12 Group Enable Register
PIE, INT12 Group Flag Register
Reserved
0x0CFA
0x0CFF
(1) The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector table
is protected.
3.5.1 External Interrupts
Table 3-12. External Interrupt Registers
NAME
XINT1CR
ADDRESS
0x7070
SIZE (x16)
DESCRIPTION
1
1
XINT1 control register
XINT2 control register
XINT2CR
0x7071
0x7072
0x7076
reserved
5
XNMICR
0x7077
0x7078
0x7079
1
1
1
XNMI control register
XINT1 counter register
XINT2 counter register
XINT1CTR
XINT2CTR
0x707A
0x707E
reserved
5
1
XNMICTR
0x707F
XNMI counter register
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Each external interrupt can be enabled/disabled or qualified using positive, negative, or both positive and
negative edge. For more information, see the TMS320x280x System Control and Interrupts Reference
Guide (literature number SPRU712).
3.6 System Control
This section describes the 280x oscillator, PLL and clocking mechanisms, the watchdog function and the
low power modes. Figure 3-7 shows the various clock and reset domains in the 280x devices that will be
discussed.
Reset
SYSCLKOUT
XRS
Watchdog
Block
(A)
Peripheral Reset
X1
X2
(A)
CLKIN
28x
CPU
PLL
OSC
Power
Modes
Control
XCLKIN
CPU
Timers
Peripheral
Registers
Clock Enables
System
Control
Registers
ePWM 1/2/3/4/5/6
eCAP 1/2/3/4 eQEP 1/2
Peripheral
Registers
I/O
I/O
I/O
eCAN-A/B
I C-A
Peripheral
Registers
2
GPIO
MUX
GPIOs
Low-Speed Prescaler
LSPCLK
Peripheral
Registers
Low-Speed Peripherals
SCI-A/B, SPI-A/B/C/D
High-Speed Prescaler
HSPCLK
ADC
Registers
12-Bit ADC
16 ADC inputs
A. CLKIN is the clock into the CPU. It is passed out of the CPU as SYSCLKOUT (that is, CLKIN is the same frequency
as SYSCLKOUT).
Figure 3-7. Clock and Reset Domains
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The PLL, clocking, watchdog and low-power modes, are controlled by the registers listed in Table 3-13.
Table 3-13. PLL, Clocking, Watchdog, and Low-Power Mode Registers(1)
NAME
XCLK
ADDRESS
0x7010
SIZE (x16)
DESCRIPTION
XCLKOUT Pin Control, X1 and XCLKIN Status Register
PLL Status Register
1
1
PLLSTS
0x7011
0x7012
0x7019
reserved
8
HISPCP
0x701A
0x701B
0x701C
0x701D
0x701E
1
1
1
1
1
High-Speed Peripheral Clock Prescaler Register (for HSPCLK)
Low-Speed Peripheral Clock Prescaler Register (for LSPCLK)
Peripheral Clock Control Register 0
LOSPCP
PCLKCR0
PCLKCR1
LPMCR0
Peripheral Clock Control Register 1
Low Power Mode Control Register 0
0x701F
0x7020
reserved
1
PLLCR
0x7021
0x7022
0x7023
0x7024
0x7025
1
1
1
1
1
PLL Control Register
SCSR
System Control and Status Register
Watchdog Counter Register
WDCNTR
reserved
WDKEY
Watchdog Reset Key Register
Watchdog Control Register
0x7026
0x7028
reserved
WDCR
3
1
6
0x7029
0x702A
0x702F
reserved
(1) All of the registers in this table are EALLOW protected.
3.6.1 OSC and PLL Block
Figure 3-8 shows the OSC and PLL block on the 280x.
OSCCLK
OSCCLK
XCLKIN
(3.3-V clock input)
0
n
xor
OSCCLK or
VCOCLK
CLKIN
PLLSTS[OSCOFF]
PLLSTS[PLLOFF]
VCOCLK
PLL
/2
n ≠ 0
PLLSTS[CLKINDIV]
X1
On chip
oscillator
4-bit PLL Select (PLLCR)
X2
Figure 3-8. OSC and PLL Block Diagram
The on-chip oscillator circuit enables a crystal/resonator to be attached to the 280x devices using the X1
and X2 pins. If the on-chip oscillator is not used, an external oscillator can be used in either one of the
following configurations:
1. A 3.3-V external oscillator can be directly connected to the XCLKIN pin. The X2 pin should be left
unconnected and the X1 pin tied low. The logic-high level in this case should not exceed VDDIO
.
2. A 1.8-V external oscillator can be directly connected to the X1 pin. The X2 pin should be left
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unconnected and the XCLKIN pin tied low. The logic-high level in this case should not exceed VDD
.
The three possible input-clock configurations are shown in Figure 3-9 through Figure 3-11
XCLKIN
X1
X2
NC
External Clock Signal
(Toggling 0−V
)
DDIO
Figure 3-9. Using a 3.3-V External Oscillator
X2
X1
XCLKIN
External Clock Signal
NC
(Toggling 0−V
)
DD
Figure 3-10. Using a 1.8-V External Oscillator
XCLKIN
X1
X2
C
L2
C
L1
Crystal
Figure 3-11. Using the Internal Oscillator
3.6.1.1 External Reference Oscillator Clock Option
The typical specifications for the external quartz crystal for a frequency of 20 MHz are listed below:
•
•
•
•
•
Fundamental mode, parallel resonant
CL (load capacitance) = 12 pF
CL1 = CL2 = 24 pF
Cshunt = 6 pF
ESR range = 30 to 60 Ω
Texas Instruments recommends that customers have the resonator/crystal vendor characterize the
operation of their device with the DSP chip. The resonator/crystal vendor has the equipment and expertise
to tune the tank circuit. The vendor can also advise the customer regarding the proper tank component
values that will produce proper start up and stability over the entire operating range.
3.6.1.2 PLL-Based Clock Module
The 280x devices have an on-chip, PLL-based clock module. This module provides all the necessary
clocking signals for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio
control PLLCR[DIV] to select different CPU clock rates. The watchdog module should be disabled before
writing to the PLLCR register. It can be re-enabled (if need be) after the PLL module has stabilized, which
takes 131072 OSCCLK cycles.
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Table 3-14. PLLCR Register Bit Definitions
SYSCLKOUT
(CLKIN)(2)
PLLCR[DIV](1)
PLLSTS[CLKINDIV]
0000 (PLL bypass)
0
1
0
0
0
0
0
0
0
0
0
0
0
OSCCLK/2
0000 (PLL bypass)
0001
OSCCLK
(OSCCLK*1)/2
(OSCCLK*2)/2
(OSCCLK*3)/2
(OSCCLK*4)/2
(OSCCLK*5)/2
(OSCCLK*6)/2
(OSCCLK*7)/2
(OSCCLK*8)/2
(OSCCLK*9)/2
(OSCCLK*10)/2
reserved
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011-1111
(1) This register is EALLOW protected.
(2) CLKIN is the input clock to the CPU. SYSCLKOUT is the output
clock from the CPU. The frequency of SYSCLKOUT is the same as
CLKIN.
CAUTION
PLLSTS[CLKINDIV] can be set to 1 only if PLLCR is 0x0000. PLLCR should not be
changed once PLLSTS[CLKINDIV] is set.
The PLL-based clock module provides two modes of operation:
•
Crystal-operation - This mode allows the use of an external crystal/resonator to provide the time base
to the device.
•
External clock source operation - This mode allows the internal oscillator to be bypassed. The device
clocks are generated from an external clock source input on the X1 or the XCLKIN pin.
Table 3-15. Possible PLL Configuration Modes
SYSCLKOUT
(CLKIN)
PLL MODE
REMARKS
PLLSTS[CLKINDIV]
Invoked by the user setting the PLLOFF bit in the PLLSTS register. The PLL block
is disabled in this mode. This can be useful to reduce system noise and for low
power operation. The PLLCR register must first be set to 0x0000 (PLL Bypass)
before entering this mode. The CPU clock (CLKIN) is derived directly from the
input clock on either X1/X2, X1 or XCLKIN.
0
OSCCLK/2
PLL Off
1
OSCCLK
PLL Bypass is the default PLL configuration upon power-up or after an external
reset (XRS). This mode is selected when the PLLCR register is set to 0x0000 or
while the PLL locks to a new frequency after the PLLCR register has been
modified. In this mode, the PLL itself is bypassed but the PLL is not turned off.
0
1
OSCCLK/2
OSCCLK
PLL Bypass
PLL Enable
Achieved by writing a non-zero value n into the PLLCR register. Upon writing to the
PLLCR the device will switch to PLL Bypass mode until the PLL locks.
0
OSCCLK*n/2
3.6.1.3 Loss of Input Clock
In PLL-enabled and PLL-bypass mode, if the input clock OSCCLK is removed or absent, the PLL will still
issue a "limp-mode" clock. The limp-mode clock continues to clock the CPU and peripherals at a typical
frequency of 1-5 MHz. Limp mode is not specified to work from power-up, only after input clocks have
been present initially. In PLL bypass mode, the limp mode clock from the PLL is automatically routed to
the CPU if the input clock is removed or absent.
Normally, when the input clocks are present, the watchdog counter decrements to initiate a watchdog
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reset or WDINT interrupt. However, when the external input clock fails, the watchdog counter stops
decrementing (i.e., the watchdog counter does not change with the limp-mode clock). In addition to this,
the device will be reset and the “Missing Clock Status” (MCLKSTS) bit will be set. These conditions could
be used by the application firmware to detect the input clock failure and initiate necessary shut-down
procedure for the system.
NOTE
Applications in which the correct CPU operating frequency is absolutely critical should
implement a mechanism by which the DSP will be held in reset, should the input clocks
ever fail. For example, an R-C circuit may be used to trigger the XRS pin of the DSP,
should the capacitor ever get fully charged. An I/O pin may be used to discharge the
capacitor on a periodic basis to prevent it from getting fully charged. Such a circuit would
also help in detecting failure of the flash memory and the VDD3VFL rail.
3.6.2 Watchdog Block
The watchdog block on the 280x is similar to the one used on the 240x and 281x devices. The watchdog
module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit watchdog up
counter has reached its maximum value. To prevent this, the user disables the counter or the software
must periodically write a 0x55 + 0xAA sequence into the watchdog key register which will reset the
watchdog counter. Figure 3-12 shows the various functional blocks within the watchdog module.
WDCR (WDPS(2:0))
WDCR (WDDIS)
WDCNTR(7:0)
OSCCLK
WDCLK
8-Bit
Watchdog
Counter
CLR
Watchdog
Prescaler
/512
Clear Counter
Internal
Pullup
WDKEY(7:0)
WDRST
WDINT
Generate
Output Pulse
(512 OSCCLKs)
Watchdog
55 + AA
Key Detector
Good Key
XRS
Bad
WDCHK
Key
Core-reset
SCSR (WDENINT)
WDCR (WDCHK(2:0))
1
0
1
(A)
WDRST
A. The WDRST signal is driven low for 512 OSCCLK cycles.
Figure 3-12. Watchdog Module
The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode.
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In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains
functional is the watchdog. The WATCHDOG module will run off OSCCLK. The WDINT signal is fed to the
LPM block so that it can wake the device from STANDBY (if enabled). See Section Section 3.7,
Low-Power Modes Block, for more details.
In IDLE mode, the WDINT signal can generate an interrupt to the CPU, via the PIE, to take the CPU out of
IDLE mode.
In HALT mode, this feature cannot be used because the oscillator (and PLL) are turned off and hence so
is the WATCHDOG.
3.7 Low-Power Modes Block
The low-power modes on the 280x are similar to the 240x devices. Table 3-16 summarizes the various
modes.
Table 3-16. Low-Power Modes
MODE
LPMCR0(1:0)
OSCCLK
CLKIN
SYSCLKOUT
EXIT(1)
XRS, Watchdog interrupt, any enabled
interrupt, XNMI
IDLE
00
On
On
On(2)
On
XRS, Watchdog interrupt, GPIO Port A
signal, debugger(3), XNMI
STANDBY
HALT
01
1X
Off
Off
Off
Off
(watchdog still running)
Off
XRS, GPIO Port A signal, XNMI,
debugger(3)
(oscillator and PLL turned off,
watchdog not functional)
(1) The Exit column lists which signals or under what conditions the low power mode will be exited. A low signal, on any of the signals, will
exit the low power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise the
IDLE mode will not be exited and the device will go back into the indicated low power mode.
(2) The IDLE mode on the C28x behaves differently than on the 24x/240x. On the C28x, the clock output from the CPU (SYSCLKOUT) is
still functional while on the 24x/240x the clock is turned off.
(3) On the C28x, the JTAG port can still function even if the CPU clock (CLKIN) is turned off.
The various low-power modes operate as follows:
IDLE Mode:
This mode is exited by any enabled interrupt or an XNMI that is recognized by
the processor. The LPM block performs no tasks during this mode as long as the
LPMCR0(LPM) bits are set to 0,0.
STANDBY Mode:
Any GPIO port A signal (GPIO[31:0]) can wake the device from STANDBY
mode. The user must select which signal(s) will wake the device in the
GPIOLPMSEL register. The selected signal(s) are also qualified by the OSCCLK
before waking the device. The number of OSCCLKs is specified in the LPMCR0
register.
HALT Mode:
Only the XRS and any GPIO port A signal (GPIO[31:0]) can wake the device
from HALT mode. The user selects the signal in the GPIOLPMSEL register.
NOTE
The low-power modes do not affect the state of the output pins (PWM pins included).
They will be in whatever state the code left them in when the IDLE instruction was
executed. See the TMS320x280x System Control and Interrupts Reference Guide
(literature number SPRU712) for more details.
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4
Peripherals
The integrated peripherals of the 280x are described in the following subsections:
•
•
•
•
•
•
•
•
•
•
Three 32-bit CPU-Timers
Up to six enhanced PWM modules (ePWM1, ePWM2, ePWM3, ePWM4, ePWM5, ePWM6)
Up to four enhanced capture modules (eCAP1, eCAP2, eCAP3, eCAP4)
Up to two enhanced QEP modules (eQEP1, eQEP2)
Enhanced analog-to-digital converter (ADC) module
Up to two enhanced controller area network (eCAN) modules (eCAN-A, eCAN-B)
Up to two serial communications interface modules (SCI-A, SCI-B)
Up to four serial peripheral interface (SPI) modules (SPI-A, SPI-B, SPI-C, SPI-D)
Inter-integrated circuit module (I2C)
Digital I/O and shared pin functions
4.1 32-Bit CPU-Timers 0/1/2
There are three 32-bit CPU-timers on the 280x devices (CPU-TIMER0/1/2).
CPU-Timer 1 is reserved for Texas Instruments system functions and Timer 2 is reserved for
DSP/BIOS™. CPU-Timer 0 can be used in user applications. These timers are different from the timers
that are present in the ePWM modules.
NOTE
NOTE: If the application is not using DSP/BIOS, then CPU-Timer 2 can be used in the
application.
Reset
Timer Reload
16-Bit Timer Divide-Down
32-Bit Timer Period
TDDRH:TDDR
PRDH:PRD
16-Bit Prescale Counter
SYSCLKOUT
PSCH:PSC
TCR.4
32-Bit Counter
TIMH:TIM
(Timer Start Status)
Borrow
Borrow
TINT
Figure 4-1. CPU-Timers
In the 280x devices, the timer interrupt signals (TINT0, TINT1, TINT2) are connected as shown in
Figure 4-2.
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INT1
to
TINT0
PIE
CPU-TIMER 0
INT12
C28x
CPU-TIMER 1
(Reserved for TI
system functions)
TINT1
INT13
XINT13
CPU-TIMER 2
(Reserved for
DSP/BIOS)
TINT2
INT14
A. The timer registers are connected to the memory bus of the C28x processor.
B. The timing of the timers is synchronized to SYSCLKOUT of the processor clock.
C. While TIMER1 is reserved, INT13 is not reserved and the user can use XINT13 connected to INT13.
Figure 4-2. CPU-Timer Interrupt Signals and Output Signal
The general operation of the timer is as follows: The 32-bit counter register "TIMH:TIM" is loaded with the
value in the period register "PRDH:PRD". The counter register decrements at the SYSCLKOUT rate of the
C28x. When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse. The
registers listed in Table 4-1 are used to configure the timers. For more information, see the TMS320x280x
System Control and Interrupts Reference Guide (literature number SPRU712).
Table 4-1. CPU-Timers 0, 1, 2 Configuration and Control Registers
NAME
TIMER0TIM
ADDRESS
0x0C00
0x0C01
0x0C02
0x0C03
0x0C04
0x0C05
0x0C06
0x0C07
0x0C08
0x0C09
0x0C0A
0x0C0B
0x0C0C
0x0C0D
0x0C0E
0x0C0F
0x0C10
0x0C11
0x0C12
0x0C13
0x0C14
0x0C15
SIZE (x16)
DESCRIPTION
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CPU-Timer 0, Counter Register
TIMER0TIMH
TIMER0PRD
TIMER0PRDH
TIMER0TCR
reserved
CPU-Timer 0, Counter Register High
CPU-Timer 0, Period Register
CPU-Timer 0, Period Register High
CPU-Timer 0, Control Register
TIMER0TPR
TIMER0TPRH
TIMER1TIM
TIMER1TIMH
TIMER1PRD
TIMER1PRDH
TIMER1TCR
reserved
CPU-Timer 0, Prescale Register
CPU-Timer 0, Prescale Register High
CPU-Timer 1, Counter Register
CPU-Timer 1, Counter Register High
CPU-Timer 1, Period Register
CPU-Timer 1, Period Register High
CPU-Timer 1, Control Register
TIMER1TPR
TIMER1TPRH
TIMER2TIM
TIMER2TIMH
TIMER2PRD
TIMER2PRDH
TIMER2TCR
reserved
CPU-Timer 1, Prescale Register
CPU-Timer 1, Prescale Register High
CPU-Timer 2, Counter Register
CPU-Timer 2, Counter Register High
CPU-Timer 2, Period Register
CPU-Timer 2, Period Register High
CPU-Timer 2, Control Register
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Table 4-1. CPU-Timers 0, 1, 2 Configuration and Control Registers (continued)
NAME
ADDRESS
0x0C16
SIZE (x16)
DESCRIPTION
CPU-Timer 2, Prescale Register
CPU-Timer 2, Prescale Register High
TIMER2TPR
1
1
TIMER2TPRH
0x0C17
0x0C18
0x0C3F
reserved
40
4.2 Enhanced PWM Modules (ePWM1/2/3/4/5/6)
The 280x device contains up to six enhanced PWM Modules (ePWM). Figure 4-3 shows a block diagram
of multiple ePWM modules. Figure 4-4 shows the signal interconnections with the ePWM. See the
TMS320x280x Enhanced Pulse Width Modulator (ePWM) Module Reference Guide (literature number
SPRU791) for more details.
EPWM1SYNCI
EPWM1SYNCI
EPWM1INT
EPWM1A
EPWM1SOC
ePWM1 module
EPWM1B
TZ1 to TZ6
EPWM1SYNCO
to eCAP1
module
(sync in)
EPWM1SYNCO
.
EPWM2SYNCI
ePWM2 module
EPWM2SYNCO
EPWM2INT
EPWM2A
EPWM2B
TZ1 to TZ6
EPWM2SOC
PIE
GPIO
MUX
EPWMxSYNCI
ePWMx module
EPWMxINT
EPWMxA
EPWMxB
EPWMxSOC
TZ1 to TZ6
ADCSOCx0
EPWMxSYNCO
Peripheral Bus
ADC
Figure 4-3. Multiple PWM Modules in a 280x System
Table 4-2 shows the complete ePWM register set per module.
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Table 4-2. ePWM Control and Status Registers
NAME
EPWM1
EPWM2
EPWM3
EPWM4
EPWM5
EPWM6
SIZE (x16) /
#SHADOW
DESCRIPTION
TBCTL
0x6800
0x6801
0x6802
0x6803
0x6804
0x6805
0x6807
0x6808
0x6809
0x680A
0x680B
0x680C
0x680D
0x680E
0x680F
0x6810
0x6811
0x6812
0x6814
0x6815
0x6816
0x6817
0x6818
0x6819
0x681A
0x681B
0x681C
0x681D
0x681E
0x6820
0x6840
0x6841
0x6842
0x6843
0x6844
0x6845
0x6847
0x6848
0x6849
0x684A
0x684B
0x684C
0x684D
0x684E
0x684F
0x6850
0x6851
0x6852
0x6854
0x6855
0x6856
0x6857
0x6858
0x6859
0x685A
0x685B
0x685C
0x685D
0x685E
0x6860
0x6880
0x6881
0x6882
0x6883
0x6884
0x6885
0x6887
0x6888
0x6889
0x688A
0x688B
0x688C
0x688D
0x688E
0x688F
0x6890
0x6891
0x6892
0x6894
0x6895
0x6896
0x6897
0x6898
0x6899
0x689A
0x689B
0x689C
0x689D
0x689E
0x68A0
0x68C0
0x68C1
0x68C2
0x68C3
0x68C4
0x68C5
0x68C7
0x68C8
0x68C9
0x68CA
0x68CB
0x68CC
0x68CD
0x68CE
0x68CF
0x68D0
0x68D1
0x68D2
0x68D4
0x68D5
0x68D6
0x68D7
0x68D8
0x68D9
0x68DA
0x68DB
0x68DC
0x68DD
0x68DE
0x68E0
0x6900
0x6901
N/A
0x6940
0x6941
N/A
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 1
1 / 0
1 / 1
1 / 1
1 / 1
1 / 0
1 / 0
1 / 0
1 / 1
1 / 1
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
Time Base Control Register
TBSTS
TBPHSHR
TBPHS
TBCNT
TBPRD
CMPCTL
CMPAHR
CMPA
Time Base Status Register
Time Base Phase HRPWM Register
Time Base Phase Register
0x6903
0x6904
0x6905
0x6907
N/A
0x6943
0x6944
0x6945
0x6947
N/A
Time Base Counter Register
Time Base Period Register Set
Counter Compare Control Register
Time Base Compare A HRPWM Register
Counter Compare A Register Set
Counter Compare B Register Set
Action Qualifier Control Register For Output A
Action Qualifier Control Register For Output B
Action Qualifier Software Force Register
0x6909
0x690A
0x690B
0x690C
0x690D
0x690E
0x690F
0x6910
0x6911
0x6912
0x6914
0x6915
0x6916
0x6917
0x6918
0x6919
0x691A
0x691B
0x691C
0x691D
0x691E
N/A
0x6949
0x694A
0x694B
0x694C
0x694D
0x694E
0x694F
0x6950
0x6951
0x6952
0x6954
0x6955
0x6956
0x6957
0x6958
0x6959
0x695A
0x695B
0x695C
0x695D
0x695E
N/A
CMPB
AQCTLA
AQCTLB
AQSFRC
AQCSFRC
DBCTL
DBRED
DBFED
TZSEL
Action Qualifier Continuous S/W Force Register Set
Dead-Band Generator Control Register
Dead-Band Generator Rising Edge Delay Count Register
Dead-Band Generator Falling Edge Delay Count Register
Trip Zone Select Register(1)
TZCTL
Trip Zone Control Register(1)
Trip Zone Enable Interrupt Register(1)
TZEINT
TZFLG
Trip Zone Flag Register
Trip Zone Clear Register(1)
Trip Zone Force Register(1)
TZCLR
TZFRC
ETSEL
Event Trigger Selection Register
Event Trigger Prescale Register
Event Trigger Flag Register
ETPS
ETFLG
ETCLR
ETFRC
PCCTL
HRCNFG
Event Trigger Clear Register
Event Trigger Force Register
PWM Chopper Control Register
HRPWM Configuration Register
(1) Registers that are EALLOW protected.
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Time−base (TB)
Sync
CTR=ZERO
CTR=CMPB
Disabled
in/out
select
Mux
TBPRD shadow (16)
TBPRD active (16)
EPWMxSYNCO
EPWMxSYNCI
CTR=PRD
TBCTL[SYNCOSEL]
TBCTL[CNTLDE]
Counter
up/down
(16 bit)
TBCTL[SWFSYNC]
(software forced sync)
CTR=ZERO
CTR_Dir
TBCNT
active (16)
TBPHSHR (8)
16
8
CTR = PRD
CTR = ZERO
CTR = CMPA
CTR = CMPB
CTR_Dir
Phase
Event
trigger
and
interrupt
(ET)
EPWMxINT
TBPHS active (24)
control
EPWMxSOCA
EPWMxSOCB
Counter compare (CC)
CTR=CMPA
CMPAHR (8)
Action
qualifier
(AQ)
16
8
HiRes PWM (HRPWM)
CMPA active (24)
EPWMA
EPWMB
EPWMxAO
CMPA shadow (24)
CTR=CMPB
Dead
band
(DB)
PWM
chopper
(PC)
Trip
zone
(TZ)
16
EPWMxBO
EPWMxTZINT
TZ1 to TZ6
CMPB active (16)
CMPB shadow (16)
CTR = ZERO
Figure 4-4. ePWM Sub-modules Showing Critical Internal Signal Interconects
4.3 Hi-Resolution PWM (HRPWM)
The HRPWM module offers PWM resolution (time granularity) which is significantly better than what can
be achieved using conventionally derived digital PWM methods. The key points for the HRPWM module
are:
•
•
Significantly extends the time resolution capabilities of conventionally derived digital PWM
Typically used when effective PWM resolution falls below ~ 9-10 bits. This occurs at PWM frequencies
greater than ~200 KHz when using a CPU/System clock of 100 MHz.
•
•
This capability can be utilized in both duty cycle and phase-shift control methods.
Finer time granularity control or edge positioning is controlled via extensions to the Compare A and
Phase registers of the ePWM module.
•
HRPWM capabilities are offered only on the A signal path of an ePWM module (i.e., on the EPWMxA
output). EPWMxB output has conventional PWM capabilities.
Only PWM channels ePWM 1A, 2A, 3A, 4A support HRPWM features. The remaining ePWM
channels do not support the HRPWM features.
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4.4 Enhanced CAP Modules (eCAP1/2/3/4)
The 280x device contains up to four enhanced capture (eCAP) modules. Figure 4-5 shows a functional
block diagram of a module. See the TMS320x280x Enhanced Capture (eCAP) Module Reference Guide
(literature number SPRU807) for more details.
The eCAP modules are clocked at the SYSCLKOUT rate.
The clock enable bits (ECAP1/2/3/4ENCLK) in the PCLKCR1 register are used to turn off the eCAP
modules individually (for low power operation). Upon reset, ECAP1ENCLK, ECAP2ENCLK,
ECAP3ENCLK, and ECAP4ENCLK are set to low, indicating that the peripheral clock is off.
CTRPHS
(phase register−32 bit)
APWM mode
SYNCIn
CTR_OVF
OVF
CTR [0−31]
PRD [0−31]
CMP [0−31]
TSCTR
(counter−32 bit)
SYNCOut
PWM
compare
logic
Delta−mode
RST
32
CTR=PRD
CTR=CMP
CTR [0−31]
PRD [0−31]
32
eCAPx
32
32
LD1
CAP1
(APRD active)
Polarity
select
LD
APRD
shadow
32
CMP [0−31]
32
LD2
CAP2
(ACMP active)
Polarity
select
LD
Event
qualifier
Event
Pre-scale
32
ACMP
shadow
Polarity
select
32
32
LD3
LD4
CAP3
(APRD shadow)
LD
CAP4
(ACMP shadow)
Polarity
select
LD
4
Capture events
4
CEVT[1:4]
Interrupt
Trigger
and
Flag
Continuous /
Oneshot
Capture Control
to PIE
CTR_OVF
CTR=PRD
CTR=CMP
control
Figure 4-5. eCAP Functional Block Diagram
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Table 4-3. eCAP Control and Status Registers
NAME
ECAP1
ECAP2
ECAP3
ECAP4
SIZE
(x16)
DESCRIPTION
TSCTR
CTRPHS
CAP1
0x6A00
0x6A02
0x6A04
0x6A06
0x6A08
0x6A0A
0x6A20
0x6A22
0x6A24
0x6A26
0x6A28
0x6A2A
0x6A40
0x6A42
0x6A44
0x6A46
0x6A48
0x6A4A
0x6A60
0x6A62
0x6A64
0x6A66
0x6A68
0x6A6A
2
2
2
2
2
2
8
Time-Stamp Counter
Counter Phase Offset Value Register
Capture 1 Register
CAP2
Capture 2 Register
CAP3
Capture 3 Register
CAP4
Capture 4 Register
Reserved
0x6A0C-
0x6A12
0x6A2C-
0x6A32
0x6A4C-
0x6A52
0x6A6C-
0x6A72
ECCTL1
ECCTL2
ECEINT
ECFLG
0x6A14
0x6A15
0x6A16
0x6A17
0x6A18
0x6A19
0x6A34
0x6A35
0x6A36
0x6A37
0x6A38
0x6A39
0x6A54
0x6A55
0x6A56
0x6A57
0x6A58
0x6A59
0x6A74
0x6A75
0x6A76
0x6A77
0x6A78
0x6A79
1
1
1
1
1
1
6
Capture Control Register 1
Capture Control Register 2
Capture Interrupt Enable Register
Capture Interrupt Flag Register
Capture Interrupt Clear Register
Capture Interrupt Force Register
ECCLR
ECFRC
Reserved
0x6A1A-
0x6A1F
0x6A3A-
0x6A3F
0x6A5A-
0x6A5F
0x6A7A-
0x6A7F
4.5 Enhanced QEP Modules (eQEP1/2)
The 280x device contains up to two enhanced quadrature encoder (eQEP) modules. See the
TMS320x280x Enhanced Quadrature Encoder (eQEP) Module Reference Guide (literature number
SPRU790) for more details.
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System
control registers
To CPU
EQEPxENCLK
SYSCLKOUT
QCPRD
QCTMR
QCAPCTL
16
16
16
Quadrature
capture unit
(QCAP)
QCTMRLAT
QCPRDLAT
QUTMR
QUPRD
QWDTMR
QWDPRD
Registers
used by
multiple units
32
16
QEPCTL
QEPSTS
QFLG
UTOUT
UTIME
QWDOG
QDECCTL
16
WDTOUT
EQEPxAIN
EQEPxBIN
EQEPxIIN
EQEPxINT
16
QCLK
QDIR
QI
EQEPxA/XCLK
EQEPxB/XDIR
EQEPxI
PIE
Position counter/
control unit
(PCCU)
Quadrature
decoder
(QDU)
EQEPxIOUT
EQEPxIOE
EQEPxSIN
EQEPxSOUT
EQEPxSOE
QS
GPIO
MUX
QPOSLAT
QPOSSLAT
QPOSILAT
PHE
PCSOUT
EQEPxS
32
32
16
QPOSCNT
QPOSINIT
QPOSMAX
QEINT
QFRC
QPOSCMP
QCLR
QPOSCTL
Enhanced QEP (eQEP) peripheral
Figure 4-6. eQEP Functional Block Diagram
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Table 4-4. eQEP Control and Status Registers
NAME
EQEP1
EQEP2
EQEP1
REGISTER DESCRIPTION
ADDRESS
ADDRESS
SIZE(x16)/
#SHADOW
QPOSCNT
QPOSINIT
QPOSMAX
QPOSCMP
QPOSILAT
QPOSSLAT
QPOSLAT
QUTMR
0x6B00
0x6B02
0x6B04
0x6B06
0x6B08
0x6B0A
0x6B0C
0x6B0E
0x6B10
0x6B12
0x6B13
0x6B14
0x6B15
0x6B16
0x6B17
0x6B18
0x6B19
0x6B1A
0x6B1B
0x6B1C
0x6B1D
0x6B1E
0x6B1F
0x6B20
0x6B40
0x6B42
0x6B44
0x6B46
0x6B48
0x6B4A
0x6B4C
0x6B4E
0x6B50
0x6B52
0x6B53
0x6B54
0x6B55
0x6B56
0x6B57
0x6B58
0x6B59
0x6B5A
0x6B5B
0x6B5C
0x6B5D
0x6B5E
0x6B5F
0x6B60
2/0
2/0
2/0
2/1
2/0
2/0
2/0
2/0
2/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
31/0
eQEP Position Counter
eQEP Initialization Position Count
eQEP Maximum Position Count
eQEP Position-compare
eQEP Index Position Latch
eQEP Strobe Position Latch
eQEP Position Latch
eQEP Unit Timer
QUPRD
eQEP Unit Period Register
eQEP Watchdog Timer
QWDTMR
QWDPRD
QDECCTL
QEPCTL
QCAPCTL
QPOSCTL
QEINT
eQEP Watchdog Period Register
eQEP Decoder Control Register
eQEP Control Register
eQEP Capture Control Register
eQEP Position-compare Control Register
eQEP Interrupt Enable Register
eQEP Interrupt Flag Register
eQEP Interrupt Clear Register
eQEP Interrupt Force Register
eQEP Status Register
QFLG
QCLR
QFRC
QEPSTS
QCTMR
eQEP Capture Timer
QCPRD
eQEP Capture Period Register
eQEP Capture Timer Latch
eQEP Capture Period Latch
QCTMRLAT
QCPRDLAT
Reserved
0x6B21-
0x6B3F
0x6B61-
0x6B7F
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4.6 Enhanced Analog-to-Digital Converter (ADC) Module
A simplified functional block diagram of the ADC module is shown in Figure 4-7. The ADC module
consists of a 12-bit ADC with a built-in sample-and-hold (S/H) circuit. Functions of the ADC module
include:
•
•
•
•
•
12-bit ADC core with built-in S/H
Analog input: 0 V to 3 V (Voltages above 3 V produce full-scale conversion results.)
Fast conversion rate: 160 ns at 12.5-MHz ADC clock, 6.25 MSPS
16-channel, MUXed inputs
Autosequencing capability provides up to 16 "autoconversions" in a single session. Each conversion
can be programmed to select any 1 of 16 input channels
•
•
Sequencer can be operated as two independent 8-state sequencers or as one large 16-state
sequencer (i.e., two cascaded 8-state sequencers)
Sixteen result registers (individually addressable) to store conversion values
–
The digital value of the input analog voltage is derived by:
Digital Value + 0,
when input ≤ 0 V
Input Analog Voltage * ADCLO
when 0 V < input < 3 V
when input ≥ 3 V
Digital Value + 4096
3
Digital Value + 4095,
A. All fractional values are truncated.
•
Multiple triggers as sources for the start-of-conversion (SOC) sequence
–
–
–
S/W - software immediate start
ePWM start of conversion
XINT2 ADC start of conversion
•
•
Flexible interrupt control allows interrupt request on every end-of-sequence (EOS) or every other EOS.
Sequencer can operate in "start/stop" mode, allowing multiple "time-sequenced triggers" to
synchronize conversions.
•
•
SOCA and SOCB triggers can operate independently in dual-sequencer mode.
Sample-and-hold (S/H) acquisition time window has separate prescale control.
The ADC module in the 280x has been enhanced to provide flexible interface to ePWM peripherals. The
ADC interface is built around a fast, 12-bit ADC module with a fast conversion rate of 160 ns at 12.5-MHz
ADC clock. The ADC module has 16 channels, configurable as two independent 8-channel modules. The
two independent 8-channel modules can be cascaded to form a 16-channel module. Although there are
multiple input channels and two sequencers, there is only one converter in the ADC module. Figure 4-7
shows the block diagram of the ADC module.
The two 8-channel modules have the capability to autosequence a series of conversions, each module
has the choice of selecting any one of the respective eight channels available through an analog MUX. In
the cascaded mode, the autosequencer functions as a single 16-channel sequencer. On each sequencer,
once the conversion is complete, the selected channel value is stored in its respective RESULT register.
Autosequencing allows the system to convert the same channel multiple times, allowing the user to
perform oversampling algorithms. This gives increased resolution over traditional single-sampled
conversion results.
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SYSCLKOUT
System
Control Block
High-Speed
Prescaler
DSP
HALT
HSPCLK
ADCENCLK
Analog
MUX
Result Registers
70A8h
Result Reg 0
Result Reg 1
ADCINA0
ADCINA7
ADCINB0
ADCINB7
S/H
12-Bit
ADC
Module
Result Reg 7
Result Reg 8
70AFh
70B0h
S/H
Result Reg 15
70B7h
ADC Control Registers
S/W
S/W
EPWMSOCB
EPWMSOCA
SOC
SOC
Sequencer 2
Sequencer 1
GPIO/XINT2
_ADCSOC
Figure 4-7. Block Diagram of the ADC Module
To obtain the specified accuracy of the ADC, proper board layout is very critical. To the best extent
possible, traces leading to the ADCIN pins should not run in close proximity to the digital signal paths.
This is to minimize switching noise on the digital lines from getting coupled to the ADC inputs.
Furthermore, proper isolation techniques must be used to isolate the ADC module power pins ( VDD1A18
,
VDD2A18 , VDDA2, VDDAIO ) from the digital supply.Figure 4-8 shows the ADC pin connections for the 280x
devices.
NOTE
1. The ADC registers are accessed at the SYSCLKOUT rate. The internal timing of the
ADC module is controlled by the high-speed peripheral clock (HSPCLK).
2. The behavior of the ADC module based on the state of the ADCENCLK and HALT
signals is as follows:
–
ADCENCLK: On reset, this signal will be low. While reset is active-low (XRS) the
clock to the register will still function. This is necessary to make sure all registers
and modes go into their default reset state. The analog module, however, will be
in a low-power inactive state. As soon as reset goes high, then the clock to the
registers will be disabled. When the user sets the ADCENCLK signal high, then
the clocks to the registers will be enabled and the analog module will be enabled.
There will be a certain time delay (ms range) before the ADC is stable and can be
used.
–
HALT: This mode only affects the analog module. It does not affect the registers.
In this mode, the ADC module goes into low-power mode. This mode also will stop
the clock to the CPU, which will stop the HSPCLK; therefore, the ADC register
logic will be turned off indirectly.
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Figure 4-8 shows the ADC pin-biasing for internal reference and Figure 4-9 shows the ADC pin-biasing for
external reference.
ADCINA[7:0]
ADCINB[7:0]
ADCLO
ADC 16-Channel Analog Inputs
Analog input 0−3 V with respect to ADCLO
Connect to analog ground
ADCREFIN
Float or ground if internal reference is used
22 kW
ADC External Current Bias Resistor ADCRESEXT
(A)
2.2 mF
ADC Reference Positive Output
ADC Reference Medium Output
ADCREFP
ADCREFM
ADCREFP and ADCREFM should not
be loaded by external circuitry
(A)
2.2 mF
V
V
DD1A18
ADC Analog Power Pin (1.8 V)
ADC Analog Power Pin (1.8 V)
DD2A18
ADC Power
V
V
ADC Analog Ground Pin
ADC Analog Ground Pin
SS1AGND
SS2AGND
ADC Analog Power Pin (3.3 V)
ADC Analog Ground Pin
V
V
DDA2
SSA2
ADC Analog and Reference I/O Power
ADC Analog Power Pin (3.3 V)
ADC Analog I/O Ground Pin
V
V
DDAIO
SSAIO
A. TAIYO YUDEN LMK212BJ225MG-T or equivalent
B. External decoupling capacitors are recommended on all power pins.
C. Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance.
Figure 4-8. ADC Pin Connections With Internal Reference
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ADCINA[7:0]
ADCINB[7:0]
ADCLO
ADC 16-Channel Analog Inputs
Analog input 0−3 V with respect to ADCLO
Connect to Analog Ground
Connect to 1.500, 1.024, or 2.048-V precision source
(D)
ADCREFIN
22 kW
ADC External Current Bias Resistor ADCRESEXT
(A)
2.2 mF
ADC Reference Positive Output
ADC Reference Medium Output
ADCREFP
ADCREFM
(A)
2.2 mF
ADCREFP and ADCREFM should not
be loaded by external circuitry
V
ADC Analog Power Pin (1.8 V)
ADC Analog Power Pin (1.8 V)
DD1A18
V
DD2A18
ADC Analog Power
ADC Analog Ground Pin
ADC Analog Ground Pin
V
V
SS1AGND
SS2AGND
ADC Analog Power Pin (3.3 V)
ADC Analog Ground Pin
V
V
DDA2
SSA2
ADC Analog Power Pin (3.3 V)
ADC Analog I/O Ground Pin
V
V
DDAIO
ADC Analog and Reference I/O Power
SSAIO
A. TAIYO YUDEN LMK212BJ225MG-T or equivalent
B. External decoupling capacitors are recommended on all power pins.
C. Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance.
D. External voltage on ADCREFIN is enabled by changing bits 15:14 in the ADC Reference Select register depending on
the voltage used on this pin. Texas Instruments recommends Texas Instruments part REF3020 or equivalent for
2.048-V generation. Overall gain accuracy will be determined by accuracy of this voltage source.
Figure 4-9. ADC Pin Connections With External Reference
NOTE
The temperature rating of any recommended component must match the rating of the end
product.
The ADC operation is configured, controlled, and monitored by the registers listed in Table 4-5.
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Table 4-5. ADC Registers(1)
NAME
ADDRESS(1) ADDRESS(2) SIZE (x16)
DESCRIPTION
ADCTRL1
0x7100
0x7101
0x7102
0x7103
0x7104
0x7105
0x7106
0x7107
0x7108
0x7109
0x710A
0x710B
0x710C
0x710D
0x710E
0x710F
0x7110
0x7111
0x7112
0x7113
0x7114
0x7115
0x7116
0x7117
0x7118
0x7119
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ADC Control Register 1
ADC Control Register 2
ADCTRL2
ADCMAXCONV
ADCCHSELSEQ1
ADCCHSELSEQ2
ADCCHSELSEQ3
ADCCHSELSEQ4
ADCASEQSR
ADCRESULT0
ADCRESULT1
ADCRESULT2
ADCRESULT3
ADCRESULT4
ADCRESULT5
ADCRESULT6
ADCRESULT7
ADCRESULT8
ADCRESULT9
ADCRESULT10
ADCRESULT11
ADCRESULT12
ADCRESULT13
ADCRESULT14
ADCRESULT15
ADCTRL3
ADC Maximum Conversion Channels Register
ADC Channel Select Sequencing Control Register 1
ADC Channel Select Sequencing Control Register 2
ADC Channel Select Sequencing Control Register 3
ADC Channel Select Sequencing Control Register 4
ADC Auto-Sequence Status Register
0x0B00
0x0B01
0x0B02
0x0B03
0x0B04
0x0B05
0x0B06
0x0B07
0x0B08
0x0B09
0x0B0A
0x0B0B
0x0B0C
0x0B0D
0x0B0E
0x0B0F
ADC Conversion Result Buffer Register 0
ADC Conversion Result Buffer Register 1
ADC Conversion Result Buffer Register 2
ADC Conversion Result Buffer Register 3
ADC Conversion Result Buffer Register 4
ADC Conversion Result Buffer Register 5
ADC Conversion Result Buffer Register 6
ADC Conversion Result Buffer Register 7
ADC Conversion Result Buffer Register 8
ADC Conversion Result Buffer Register 9
ADC Conversion Result Buffer Register 10
ADC Conversion Result Buffer Register 11
ADC Conversion Result Buffer Register 12
ADC Conversion Result Buffer Register 13
ADC Conversion Result Buffer Register 14
ADC Conversion Result Buffer Register 15
ADC Control Register 3
ADCST
ADC Status Register
0x711A
0x711B
Reserved
2
ADCREFSEL
ADCOFFTRIM
0x711C
0x711D
1
1
ADC Reference Select Register
ADC Offset Trim Register
0x711E
0x711F
Reserved
2
ADC Status Register
(1) The registers in this column are Peripheral Frame 2 Registers.
(2) The ADC result registers are dual mapped in the 280x DSP. Locations in Peripheral Frame 2 (0x7108-0x7117) are 2 wait states and left
justified. Locations in Peripheral frame 0 space (0x0B00-0x0B0F) are 0 wait sates and right justified. During high speed/continuous
conversion use of the ADC, use the 0 wait state locations for fast transfer of ADC results to user memory.
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4.7 Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B)
The CAN module has the following features:
•
•
•
Fully compliant with CAN protocol, version 2.0B
Supports data rates up to 1 Mbps
Thirty-two mailboxes, each with the following properties:
–
–
–
–
–
–
–
–
–
–
Configurable as receive or transmit
Configurable with standard or extended identifier
Has a programmable receive mask
Supports data and remote frame
Composed of 0 to 8 bytes of data
Uses a 32-bit time stamp on receive and transmit message
Protects against reception of new message
Holds the dynamically programmable priority of transmit message
Employs a programmable interrupt scheme with two interrupt levels
Employs a programmable alarm on transmission or reception time-out
•
•
•
•
•
Low-power mode
Programmable wake-up on bus activity
Automatic reply to a remote request message
Automatic retransmission of a frame in case of loss of arbitration or error
32-bit local network time counter synchronized by a specific message (communication in conjunction
with mailbox 16)
•
Self-test mode
–
Operates in a loopback mode receiving its own message. A "dummy" acknowledge is provided,
thereby eliminating the need for another node to provide the acknowledge bit.
NOTE
For a SYSCLKOUT of 100 MHz, the smallest bit rate possible is 15.6 kbps.
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Address
Controls
Data
32
eCAN0INT
eCAN1INT
Enhanced CAN Controller
Message Controller
Mailbox RAM
(512 Bytes)
Memory Management
Unit
eCAN Memory
(512 Bytes)
Registers and Message
Objects Control
CPU Interface,
Receive Control Unit,
Timer Management Unit
32-Message Mailbox
of 4 × 32-Bit Words
32
32
32
Receive Buffer
Transmit Buffer
Control Buffer
Status Buffer
eCAN Protocol Kernel
SN65HVD23x
3.3-V CAN Transceiver
CAN Bus
Figure 4-10. eCAN Block Diagram and Interface Circuit
Table 4-6. 3.3-V eCAN Transceivers
PART NUMBER
SUPPLY
LOW-POWER MODE
SLOPE
VREF
OTHER
TA
VOLTAGE
CONTROL
SN65HVD230
SN65HVD230Q
SN65HVD231
SN65HVD231Q
SN65HVD232
SN65HVD232Q
SN65HVD233
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
Standby
Standby
Sleep
Adjustable
Adjustable
Adjustable
Adjustable
None
Yes
Yes
–
–
–
–
–
–
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 85°C
-40°C to 125°C
-40°C to 125°C
Yes
Sleep
Yes
None
None
None
None
None
None
Standby
Adjustable
Diagnostic
Loopback
SN65HVD234
SN65HVD235
3.3 V
3.3 V
Standby & Sleep
Standby
Adjustable
Adjustable
None
None
–
-40°C to 125°C
-40°C to 125°C
Autobaud
Loopback
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eCAN-A Control and Status Registers
Mailbox Enable − CANME
Mailbox Direction − CANMD
Transmission Request Set − CANTRS
Transmission Request Reset − CANTRR
Transmission Acknowledge − CANTA
Abort Acknowledge − CANAA
eCAN-A Memory (512 Bytes)
Control and Status Registers
Received Message Pending − CANRMP
Received Message Lost − CANRML
Remote Frame Pending − CANRFP
Global Acceptance Mask − CANGAM
Master Control − CANMC
6000h
603Fh
6040h
607Fh
6080h
60BFh
60C0h
60FFh
Local Acceptance Masks (LAM)
(32 × 32-Bit RAM)
Message Object Time Stamps (MOTS)
Bit-Timing Configuration − CANBTC
Error and Status − CANES
(32 × 32-Bit RAM)
Message Object Time-Out (MOTO)
Transmit Error Counter − CANTEC
Receive Error Counter − CANREC
Global Interrupt Flag 0 − CANGIF0
Global Interrupt Mask − CANGIM
Global Interrupt Flag 1 − CANGIF1
Mailbox Interrupt Mask − CANMIM
Mailbox Interrupt Level − CANMIL
Overwrite Protection Control − CANOPC
TX I/O Control − CANTIOC
(32 × 32-Bit RAM)
eCAN-A Memory RAM (512 Bytes)
Mailbox 0
Mailbox 1
Mailbox 2
Mailbox 3
Mailbox 4
6100h−6107h
6108h−610Fh
6110h−6117h
6118h−611Fh
6120h−6127h
RX I/O Control − CANRIOC
Time Stamp Counter − CANTSC
Time-Out Control − CANTOC
Time-Out Status − CANTOS
Mailbox 28
Mailbox 29
Mailbox 30
Mailbox 31
61E0h−61E7h
61E8h−61EFh
61F0h−61F7h
61F8h−61FFh
Reserved
Message Mailbox (16 Bytes)
Message Identifier − MSGID
Message Control − MSGCTRL
Message Data Low − MDL
Message Data High − MDH
61E8h−61E9h
61EAh−61EBh
61ECh−61EDh
61EEh−61EFh
Figure 4-11. eCAN-A Memory Map
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eCAN-B Control and Status Registers
Mailbox Enable − CANME
Mailbox Direction − CANMD
Transmission Request Set − CANTRS
Transmission Request Reset − CANTRR
Transmission Acknowledge − CANTA
Abort Acknowledge − CANAA
eCAN-B Memory (512 Bytes)
Received Message Pending − CANRMP
Received Message Lost − CANRML
Remote Frame Pending − CANRFP
Global Acceptance Mask − CANGAM
Master Control − CANMC
6200h
623Fh
6240h
627Fh
6280h
62BFh
62C0h
62FFh
Control and Status Registers
Local Acceptance Masks (LAM)
(32 × 32-Bit RAM)
Message Object Time Stamps (MOTS)
Bit-Timing Configuration − CANBTC
Error and Status − CANES
(32 × 32-Bit RAM)
Message Object Time-Out (MOTO)
Transmit Error Counter − CANTEC
Receive Error Counter − CANREC
Global Interrupt Flag 0 − CANGIF0
Global Interrupt Mask − CANGIM
Global Interrupt Flag 1 − CANGIF1
Mailbox Interrupt Mask − CANMIM
Mailbox Interrupt Level − CANMIL
Overwrite Protection Control − CANOPC
TX I/O Control − CANTIOC
(32 × 32-Bit RAM)
eCAN-B Memory RAM (512 Bytes)
Mailbox 0
Mailbox 1
Mailbox 2
Mailbox 3
Mailbox 4
6300h−6307h
6308h−630Fh
6310h−6317h
6318h−631Fh
6320h−6327h
RX I/O Control − CANRIOC
Time Stamp Counter − CANTSC
Time-Out Control − CANTOC
Time-Out Status − CANTOS
Mailbox 28
Mailbox 29
Mailbox 30
Mailbox 31
63E0h−63E7h
63E8h−63EFh
63F0h−63F7h
63F8h−63FFh
Reserved
Message Mailbox (16 Bytes)
Message Identifier − MSGID
Message Control − MSGCTRL
Message Data Low − MDL
Message Data High − MDH
63E8h−63E9h
63EAh−63EBh
63ECh−63EDh
63EEh−63EFh
Figure 4-12. eCAN-B Memory Map
The CAN registers listed in Table 4-7 are used by the CPU to configure and control the CAN controller
and the message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM
can be accessed as 16 bits or 32 bits. 32-bit accesses are aligned to an even boundary.
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Table 4-7. CAN Register Map(1)
ECAN-A
ADDRESS
ECAN-B
ADDRESS
SIZE
(x32)
REGISTER NAME
DESCRIPTION
CANME
CANMD
0x6000
0x6002
0x6004
0x6006
0x6008
0x600A
0x600C
0x600E
0x6010
0x6012
0x6014
0x6016
0x6018
0x601A
0x601C
0x601E
0x6020
0x6022
0x6024
0x6026
0x6028
0x602A
0x602C
0x602E
0x6030
0x6032
0x6200
0x6202
0x6204
0x6206
0x6208
0x620A
0x620C
0x620E
0x6210
0x6212
0x6214
0x6216
0x6218
0x621A
0x621C
0x621E
0x6220
0x6222
0x6224
0x6226
0x6228
0x622A
0x622C
0x622E
0x6230
0x6232
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Mailbox enable
Mailbox direction
CANTRS
CANTRR
CANTA
Transmit request set
Transmit request reset
Transmission acknowledge
Abort acknowledge
CANAA
CANRMP
CANRML
CANRFP
CANGAM
CANMC
Receive message pending
Receive message lost
Remote frame pending
Global acceptance mask
Master control
CANBTC
CANES
Bit-timing configuration
Error and status
CANTEC
CANREC
CANGIF0
CANGIM
CANGIF1
CANMIM
CANMIL
CANOPC
CANTIOC
CANRIOC
CANTSC
CANTOC
CANTOS
Transmit error counter
Receive error counter
Global interrupt flag 0
Global interrupt mask
Global interrupt flag 1
Mailbox interrupt mask
Mailbox interrupt level
Overwrite protection control
TX I/O control
RX I/O control
Time stamp counter (Reserved in SCC mode)
Time-out control (Reserved in SCC mode)
Time-out status (Reserved in SCC mode)
(1) These registers are mapped to Peripheral Frame 1.
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4.8 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B)
The 280x devices include two serial communications interface (SCI) modules. The SCI modules support
digital communications between the CPU and other asynchronous peripherals that use the standard
non-return-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its
own separate enable and interrupt bits. Both can be operated independently or simultaneously in the
full-duplex mode. To ensure data integrity, the SCI checks received data for break detection, parity,
overrun, and framing errors. The bit rate is programmable to over 65000 different speeds through a 16-bit
baud-select register.
Features of each SCI module include:
•
Two external pins:
–
–
SCITXD: SCI transmit-output pin
SCIRXD: SCI receive-input pin
NOTE: Both pins can be used as GPIO if not used for SCI.
Baud rate programmable to 64K different rates:
–
LSPCLK
(BRR ) 1) * 8
Baud rate =
when BRR ≠ 0
when BRR = 0
LSPCLK
16
Baud rate =
•
Data-word format
–
–
–
–
One start bit
Data-word length programmable from one to eight bits
Optional even/odd/no parity bit
One or two stop bits
•
•
•
•
•
Four error-detection flags: parity, overrun, framing, and break detection
Two wake-up multiprocessor modes: idle-line and address bit
Half- or full-duplex operation
Double-buffered receive and transmit functions
Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms
with status flags.
–
Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX
EMPTY flag (transmitter-shift register is empty)
–
Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag
(break condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
•
Separate enable bits for transmitter and receiver interrupts (except BRKDT)
100 MHz
Max bit rate +
+ 6.25 106 bńs
16
•
•
•
NRZ (non-return-to-zero) format
Ten SCI module control registers located in the control register frame beginning at address 7050h
NOTE
All registers in this module are 8-bit registers that are connected to Peripheral Frame 2.
When a register is accessed, the register data is in the lower byte (7-0), and the upper
byte (15-8) is read as zeros. Writing to the upper byte has no effect.
Enhanced features:
•
•
Auto baud-detect hardware logic
16-level transmit/receive FIFO
The SCI port operation is configured and controlled by the registers listed in Table 4-8 and Table 4-9.
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Table 4-8. SCI-A Registers(1)
NAME
ADDRESS
0x7050
0x7051
0x7052
0x7053
0x7054
0x7055
0x7056
0x7057
0x7059
0x705A
0x705B
0x705C
0x705F
SIZE (x16)
DESCRIPTION
SCICCRA
1
1
1
1
1
1
1
1
1
1
1
1
1
SCI-A Communications Control Register
SCI-A Control Register 1
SCICTL1A
SCIHBAUDA
SCILBAUDA
SCICTL2A
SCI-A Baud Register, High Bits
SCI-A Baud Register, Low Bits
SCI-A Control Register 2
SCIRXSTA
SCIRXEMUA
SCIRXBUFA
SCITXBUFA
SCIFFTXA(2)
SCIFFRXA(2)
SCIFFCTA(2)
SCIPRIA
SCI-A Receive Status Register
SCI-A Receive Emulation Data Buffer Register
SCI-A Receive Data Buffer Register
SCI-A Transmit Data Buffer Register
SCI-A FIFO Transmit Register
SCI-A FIFO Receive Register
SCI-A FIFO Control Register
SCI-A Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce
undefined results.
(2) These registers are new registers for the FIFO mode.
Table 4-9. SCI-B Registers(1)(2)
NAME
ADDRESS
0x7750
0x7751
0x7752
0x7753
0x7754
0x7755
0x7756
0x7757
0x7759
0x775A
0x775B
0x775C
0x775F
SIZE (x16)
DESCRIPTION
SCI-B Communications Control Register
SCI-B Control Register 1
SCICCRB
1
1
1
1
1
1
1
1
1
1
1
1
1
SCICTL1B
SCIHBAUDB
SCILBAUDB
SCICTL2B
SCI-B Baud Register, High Bits
SCI-B Baud Register, Low Bits
SCI-B Control Register 2
SCIRXSTB
SCIRXEMUB
SCIRXBUFB
SCITXBUFB
SCIFFTXB(2)
SCIFFRXB(2)
SCIFFCTB(2)
SCIPRIB
SCI-B Receive Status Register
SCI-B Receive Emulation Data Buffer Register
SCI-B Receive Data Buffer Register
SCI-B Transmit Data Buffer Register
SCI-B FIFO Transmit Register
SCI-B FIFO Receive Register
SCI-B FIFO Control Register
SCI-B Priority Control Register
(1) Registers in this table are mapped to peripheral bus 16 space. This space only allows 16-bit accesses. 32-bit accesses produce
undefined results.
(2) These registers are new registers for the FIFO mode.
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Figure 4-13 shows the SCI module block diagram.
SCICTL1.1
SCITXD
Frame Format and Mode
SCITXD
TXSHF
TXENA
Register
Parity
Even/Odd Enable
TX EMPTY
SCICTL2.6
8
SCICCR.6 SCICCR.5
TXRDY
TX INT ENA
Transmitter-Data
Buffer Register
SCICTL2.7
TXWAKE
SCICTL1.3
1
SCICTL2.0
8
TX FIFO
Interrupts
TXINT
TX FIFO _0
TX Interrupt
Logic
TX FIFO _1
-----
SCITXBUF.7-0
To CPU
TX FIFO _15
SCI TX Interrupt select logic
WUT
TX FIFO registers
SCIFFENA
AutoBaud Detect logic
SCIFFTX.14
SCIHBAUD. 15 - 8
SCIRXD
RXSHF
Register
Baud Rate
MSbyte
Register
SCIRXD
RXWAKE
LSPCLK
SCIRXST.1
SCILBAUD. 7 - 0
RXENA
SCICTL1.0
8
Baud Rate
LSbyte
Register
SCICTL2.1
Receive Data
Buffer register
SCIRXBUF.7-0
RXRDY
RX/BK INT ENA
SCIRXST.6
8
BRKDT
RX FIFO _15
SCIRXST.5
-----
RX FIFO _0
RX FIFO
Interrupts
RX FIFO_1
RXINT
RX Interrupt
Logic
SCIRXBUF.7-0
RX FIFO registers
To CPU
RXFFOVF
SCIRXST.7 SCIRXST.4 - 2
SCIFFRX.15
RX Error
FE OE PE
RX Error
RX ERR INT ENA
SCI RX Interrupt select logic
SCICTL1.6
Figure 4-13. Serial Communications Interface (SCI) Module Block Diagram
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4.9 Serial Peripheral Interface (SPI) Modules (SPI-A, SPI-B, SPI-C, SPI-D)
The 280x devices include the four-pin serial peripheral interface (SPI) module. Up to four SPI modules
(SPI-A, SPI-B, SPI-C, and SPI-D) are available. The SPI is a high-speed, synchronous serial I/O port that
allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the
device at a programmable bit-transfer rate. Normally, the SPI is used for communications between the
DSP controller and external peripherals or another processor. Typical applications include external I/O or
peripheral expansion through devices such as shift registers, display drivers, and ADCs. Multidevice
communications are supported by the master/slave operation of the SPI.
The SPI module features include:
•
Four external pins:
–
–
–
–
SPISOMI: SPI slave-output/master-input pin
SPISIMO: SPI slave-input/master-output pin
SPISTE: SPI slave transmit-enable pin
SPICLK: SPI serial-clock pin
NOTE: All four pins can be used as GPIO, if the SPI module is not used.
•
Two operational modes: master and slave
Baud rate: 125 different programmable rates.
LSPCLK
Baud rate =
when SPIBRR = 3 to 127
when SPIBRR = 0,1, 2
(SPIBRR ) 1)
LSPCLK
Baud rate =
4
•
•
Data word length: one to sixteen data bits
Four clocking schemes (controlled by clock polarity and clock phase bits) include:
–
–
–
–
Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the
falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the
falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
•
•
Simultaneous receive and transmit operation (transmit function can be disabled in software)
Transmitter and receiver operations are accomplished through either interrupt-driven or polled
algorithms.
•
Nine SPI module control registers: Located in control register frame beginning at address 7040h.
NOTE
All registers in this module are 16-bit registers that are connected to Peripheral Frame 2.
When a register is accessed, the register data is in the lower byte (7-0), and the upper
byte (15-8) is read as zeros. Writing to the upper byte has no effect.
Enhanced feature:
•
•
16-level transmit/receive FIFO
Delayed transmit control
The SPI port operation is configured and controlled by the registers listed in Table 4-10.
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Table 4-10. SPI-A Registers
NAME
SPICCR
SPICTL
ADDRESS
0x7040
0x7041
0x7042
0x7044
0x7046
0x7047
0x7048
0x7049
0x704A
0x704B
0x704C
0x704F
SIZE (X16)
DESCRIPTION(1)
SPI-A Configuration Control Register
SPI-A Operation Control Register
1
1
1
1
1
1
1
1
1
1
1
1
SPISTS
SPI-A Status Register
SPIBRR
SPIRXEMU
SPIRXBUF
SPITXBUF
SPIDAT
SPI-A Baud Rate Register
SPI-A Receive Emulation Buffer Register
SPI-A Serial Input Buffer Register
SPI-A Serial Output Buffer Register
SPI-A Serial Data Register
SPIFFTX
SPIFFRX
SPIFFCT
SPIPRI
SPI-A FIFO Transmit Register
SPI-A FIFO Receive Register
SPI-A FIFO Control Register
SPI-A Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.
Table 4-11. SPI-B Registers
NAME
SPICCR
SPICTL
ADDRESS
0x7740
0x7741
0x7742
0x7744
0x7746
0x7747
0x7748
0x7749
0x774A
0x774B
0x774C
0x774F
SIZE (X16)
DESCRIPTION(1)
SPI-B Configuration Control Register
1
1
1
1
1
1
1
1
1
1
1
1
SPI-B Operation Control Register
SPI-B Status Register
SPISTS
SPIBRR
SPIRXEMU
SPIRXBUF
SPITXBUF
SPIDAT
SPI-B Baud Rate Register
SPI-B Receive Emulation Buffer Register
SPI-B Serial Input Buffer Register
SPI-B Serial Output Buffer Register
SPI-B Serial Data Register
SPIFFTX
SPIFFRX
SPIFFCT
SPIPRI
SPI-B FIFO Transmit Register
SPI-B FIFO Receive Register
SPI-B FIFO Control Register
SPI-B Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.
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Table 4-12. SPI-C Registers
NAME
SPICCR
SPICTL
ADDRESS
0x7760
0x7761
0x7762
0x7764
0x7766
0x7767
0x7768
0x7769
0x776A
0x776B
0x776C
0x776F
SIZE (X16)
DESCRIPTION(1)
1
1
1
1
1
1
1
1
1
1
1
1
SPI-C Configuration Control Register
SPI-C Operation Control Register
SPISTS
SPI-C Status Register
SPIBRR
SPIRXEMU
SPIRXBUF
SPITXBUF
SPIDAT
SPI-C Baud Rate Register
SPI-C Receive Emulation Buffer Register
SPI-C Serial Input Buffer Register
SPI-C Serial Output Buffer Register
SPI-C Serial Data Register
SPIFFTX
SPIFFRX
SPIFFCT
SPIPRI
SPI-C FIFO Transmit Register
SPI-C FIFO Receive Register
SPI-C FIFO Control Register
SPI-C Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.
Table 4-13. SPI-D Registers
NAME
SPICCR
SPICTL
ADDRESS
0x7780
0x7781
0x7782
0x7784
0x7786
0x7787
0x7788
0x7789
0x778A
0x778B
0x778C
0x778F
SIZE (X16)
DESCRIPTION(1)
SPI-D Configuration Control Register
1
1
1
1
1
1
1
1
1
1
1
1
SPI-D Operation Control Register
SPI-D Status Register
SPISTS
SPIBRR
SPIRXEMU
SPIRXBUF
SPITXBUF
SPIDAT
SPI-D Baud Rate Register
SPI-D Receive Emulation Buffer Register
SPI-D Serial Input Buffer Register
SPI-D Serial Output Buffer Register
SPI-D Serial Data Register
SPIFFTX
SPIFFRX
SPIFFCT
SPIPRI
SPI-D FIFO Transmit Register
SPI-D FIFO Receive Register
SPI-D FIFO Control Register
SPI-D Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.
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Figure 4-14 is a block diagram of the SPI in slave mode.
SPIFFENA
Overrun
Receiver
Overrun Flag
SPIFFTX.14
RX FIFO registers
SPIRXBUF
INT ENA
SPISTS.7
SPICTL.4
RX FIFO _0
RX FIFO _1
SPIINT/SPIRXINT
RX FIFO Interrupt
−−−−−
RX Interrupt
Logic
RX FIFO _15
16
SPIRXBUF
Buffer Register
SPIFFOVF FLAG
SPIFFRX.15
To CPU
TX FIFO registers
SPITXBUF
TX FIFO _15
TX Interrupt
Logic
TX FIFO Interrupt
−−−−−
TX FIFO _1
SPITXINT
TX FIFO _0
16
SPI INT
ENA
SPI INT FLAG
SPITXBUF
Buffer Register
SPISTS.6
16
SPICTL.0
16
M
S
M
SPIDAT
Data Register
S
SW1
SW2
SPISIMO
M
S
M
SPIDAT.15 − 0
S
SPISOMI
Talk
SPICTL.1
(A)
SPISTE
State Control
Master/Slave
SPICTL.2
SPI Char
SPICCR.3 − 0
S
3
2
1
0
SW3
Clock
Polarity
Clock
Phase
M
S
SPI Bit Rate
LSPCLK
SPICCR.6
SPICTL.3
SPICLK
SPIBRR.6 − 0
M
6
5
4
3
2
1
0
A. SPISTE is driven low by the master for a slave device.
Figure 4-14. SPI Module Block Diagram (Slave Mode)
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4.10 Inter-Integrated Circuit (I2C)
The 280x device contains one I2C Serial Port. Figure 4-15 shows how the I2C peripheral module interfaces
within the 280x device.
The I2C module has the following features:
•
Compliance with the Philips Semiconductors I2C-bus specification (version 2.1):
–
–
–
–
–
–
–
–
Support for 1-bit to 8-bit format transfers
7-bit and 10-bit addressing modes
General call
START byte mode
Support for multiple master-transmitters and slave-receivers
Support for multiple slave-transmitters and master-receivers
Combined master transmit/receive and receive/transmit mode
Data transfer rate of from 10 kbps up to 400 kbps (Philips Fast-mode rate)
•
•
One 16-bit receive FIFO and one 16-bit transmit FIFO
One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the
following conditions:
–
–
–
–
–
–
–
Transmit-data ready
Receive-data ready
Register-access ready
No-acknowledgment received
Arbitration lost
Stop condition detected
Addressed as slave
•
•
•
An additional interrupt that can be used by the CPU when in FIFO mode
Module enable/disable capability
Free data format mode
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System Control
Block
C28X CPU
I2CAENCLK
SYSCLKOUT
SYSRS
Control
Data[16]
SDAA
SCLA
Data[16]
Addr[16]
GPIO
MUX
2
I C−A
I2CINT1A
I2CINT2A
PIE
Block
A. The I2C registers are accessed at the SYSCLKOUT rate. The internal timing and signal waveforms of the I2C port are
also at the SYSCLKOUT rate.
B. The clock enable bit (I2CAENCLK) in the PCLKCRO register turns off the clock to the I2C port for low power
operation. Upon reset, I2CAENCLK is clear, which indicates the peripheral internal clocks are off.
Figure 4-15. I2C Peripheral Module Interfaces
The registers in Table 4-14 configure and control the I2C port operation.
Table 4-14. I2C-A Registers
NAME
I2COAR
I2CIER
ADDRESS
0x7900
0x7901
0x7902
0x7903
0x7904
0x7905
0x7906
0x7907
0x7908
0x7909
0x790A
0x790C
0x7920
0x7921
-
DESCRIPTION
I2C own address register
I2C interrupt enable register
I2C status register
I2C clock low-time divider register
I2C clock high-time divider register
I2C data count register
I2C data receive register
I2C slave address register
I2C data transmit register
I2C mode register
I2C interrupt source register
I2C prescaler register
I2C FIFO transmit register
I2C FIFO receive register
I2C receive shift register (not accessible to the CPU)
I2C transmit shift register (not accessible to the CPU)
I2CSTR
I2CCLKL
I2CCLKH
I2CCNT
I2CDRR
I2CSAR
I2CDXR
I2CMDR
I2CISRC
I2CPSC
I2CFFTX
I2CFFRX
I2CRSR
I2CXSR
-
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4.11 GPIO MUX
On the 280x, the GPIO MUX can multiplex up to three independent peripheral signals on a single GPIO
pin in addition to providing individual pin bit-banging IO capability. The GPIO MUX block diagram per pin
is shown in Figure 4-16. Because of the open drain capabilities of the I2C pins, the GPIO MUX block
diagram for these pins differ. See the TMS320x280x System Control and Interrupts Reference Guide
(literature number SPRU712) for details.
GPIOXINT1SEL
GPIOLMPSEL
GPIOXINT2SEL
LPMCR0
GPIOXNMISEL
External Interrupt
MUX
Low Power
Modes Block
PIE
Asynchronous
path
GPxDAT (read)
GPxQSEL1/2
GPxCTRL
N/C
00
GPxPUD
Peripheral 1 Input
Peripheral 2 Input
01
Input
Qualification
Internal
Pullup
10
11
Peripheral 3 Input
GPxTOGGLE
Asynchronous path
GPIOx pin
GPxCLEAR
GPxSET
00
01
GPxDAT (latch)
Peripheral 1 Output
10
11
Peripheral 2 Output
Peripheral 3 Output
High Impedance
Output Control
GPxDIR (latch)
00
01
Peripheral 1 Output Enable
Peripheral 2 Output Enable
0 = Input, 1 = Output
XRS
10
11
Peripheral 3 Output Enable
= Default at Reset
GPxMUX1/2
A. x stands for the port, either A or B. For example, GPxDIR refers to either the GPADIR and GPBDIR register
depending on the particular GPIO pin selected.
B. GPxDAT latch/read are accessed at the same memory location.
Figure 4-16. GPIO MUX Block Diagram
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The 280x supports 34 GPIO pins. The GPIO control and data registers are mapped to Peripheral Frame 1
to enable 32-bit operations on the registers (along with 16-bit operations). Table 4-15 shows the GPIO
register mapping.
Table 4-15. GPIO Registers
NAME
ADDRESS
SIZE (x16)
DESCRIPTION
GPIO CONTROL REGISTERS (EALLOW PROTECTED)
GPACTRL
GPAQSEL1
GPAQSEL2
GPAMUX1
GPAMUX2
GPADIR
0x6F80
0x6F82
0x6F84
0x6F86
0x6F88
0x6F8A
0x6F8C
2
2
2
2
2
2
2
GPIO A Control Register (GPIO0 to 31)
GPIO A Qualifier Select 1 Register (GPIO0 to 15)
GPIO A Qualifier Select 2 Register (GPIO16 to 31)
GPIO A MUX 1 Register (GPIO0 to 15)
GPIO A MUX 2 Register (GPIO16 to 31)
GPIO A Direction Register (GPIO0 to 31)
GPIO A Pull Up Disable Register (GPIO0 to 31)
GPAPUD
0x6F8E
0x6F8F
reserved
2
GPBCTRL
GPBQSEL1
GPBQSEL2
GPBMUX1
GPBMUX2
GPBDIR
0x6F90
0x6F92
0x6F94
0x6F96
0x6F98
0x6F9A
0x6F9C
2
2
2
2
2
2
2
GPIO B Control Register (GPIO32 to 35)
GPIO B Qualifier Select 1 Register (GPIO32 to 35)
reserved
GPIO B MUX 1 Register (GPIO32 to 35)
reserved
GPIO B Direction Register (GPIO32 to 35)
GPIO B Pull Up Disable Register (GPIO32 to 35)
GPBPUD
0x6F9E
0x6F9F
reserved
reserved
2
reserved
0x6FA0
0x6FBF
32
GPIO DATA REGISTERS (NOT EALLOW PROTECTED)
GPADAT
GPASET
0x6FC0
0x6FC2
0x6FC4
0x6FC6
0x6FC8
0x6FCA
0x6FCC
0x6FCE
2
2
2
2
2
2
2
2
GPIO Data Register (GPIO0 to 31)
GPIO Data Set Register (GPIO0 to 31)
GPIO Data Clear Register (GPIO0 to 31)
GPIO Data Toggle Register (GPIO0 to 31)
GPIO Data Register (GPIO32 to 35)
GPACLEAR
GPATOGGLE
GPBDAT
GPBSET
GPIO Data Set Register (GPIO32 to 35)
GPIO Data Clear Register (GPIO32 to 35)
GPIO Data Toggle Register (GPIO32 to 35)
GPBCLEAR
GPBTOGGLE
0x6FD0
0x6FDF
reserved
16
GPIO INTERRUPT AND LOW POWER MODES SELECT REGISTERS (EALLOW PROTECTED)
GPIOXINT1SEL
GPIOXINT2SEL
GPIOXNMISEL
0x6FE0
0x6FE1
0x6FE2
1
1
1
XINT1 GPIO Input Select Register (GPIO0 to 31)
XINT2 GPIO Input Select Register (GPIO0 to 31)
XNMI GPIO Input Select Register (GPIO0 to 31)
0x6FE3
0x6FE7
reserved
GPIOLPMSEL
reserved
5
2
0x6FE8
LPM GPIO Select Register (GPIO0 to 31)
0x6FEA
0x6FFF
22
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Table 4-16. F2808 GPIO MUX Table
DEFAULT AT RESET
PRIMARY I/O
GPAMUX1/2(1) FUNCTION
PERIPHERAL SELECTION
1(2)
(GPxMUX1/2 BITS = 0,1)
REGISTER
BITS
(GPxMUX1/2 BITS =
0,0)
PERIPHERAL SELECTION 2 PERIPHERAL SELECTION 3
(GPxMUX1/2 BITS = 1,0)
(GPxMUX1/2 BITS = 1,1)
GPAMUX1
EPWM1A (O)
EPWM1B (O)
EPWM2A (O)
EPWM2B (O)
EPWM3A (O)
EPWM3B (O)
EPWM4A (O)
EPWM4B (O)
EPWM5A (O)
EPWM5B (O)
EPWM6A (O)
EPWM6B (O)
TZ1 (I)
1-0
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
Reserved(3)
Reserved(3)
Reserved(3)
Reserved(3)
Reserved(3)
3-2
SPISIMOD (I/O)
Reserved(3)
5-4
7-6
SPISOMID (I/O)
Reserved(3)
9-8
Reserved(3)
11-10
13-12
15-14
17-16
19-18
21-20
23-22
25-24
27-26
29-28
31-30
SPICLKD (I/O)
EPWMSYNCI (I)
SPISTED (I/O)
CANTXB (O)
SCITXDB (O)
CANRXB (I)
ECAP1 (I/O)
EPWMSYNCO (O)
ECAP2 (I/O)
ADCSOCAO (O)
ECAP3 (I/O)
ADCSOCBO (O)
ECAP4 (I/O)
SCIRXDB (I)
CANTXB (O)
CANRXB (I)
SPISIMOB (I/O)
SPISOMIB (I/O)
SPICLKB (I/O)
SPISTEB (I/O)
TZ2 (I)
TZ3 (I)
SCITXDB (O)
SCIRXDB (I)
TZ4 (I)
GPAMUX2
1-0
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
GPIO30
GPIO31
SPISIMOA (I/O)
SPISOMIA (I/O)
SPICLKA (I/O)
SPISTEA (I/O)
EQEP1A (I)
CANTXB (O)
CANRXB (I)
SCITXDB (O)
SCIRXDB (I)
SPISIMOC (I/O)
SPISOMIC (I/O)
SPICLKC (I/O)
SPISTEC (I/O)
EQEP2A (I)
TZ5 (I)
3-2
TZ6 (I)
5-4
Reserved(3)
Reserved(3)
CANTXB (O)
CANRXB (I)
SCITXDB (O)
SCIRXDB (I)
SPISIMOB (I/O)
SPISOMIB (I/O)
SPICLKB (I/O)
SPISTEB (I/O)
TZ5 (I)
7-6
9-8
11-10
13-12
15-14
17-16
19-18
21-20
23-22
25-24
27-26
29-28
31-30
EQEP1B (I)
EQEP1S (I/O)
EQEP1I (I/O)
ECAP1 (I/O)
ECAP2 (I/O)
ECAP3 (I/O)
ECAP4 (I/O)
SCIRXDA (I)
SCITXDA (O)
CANRXA (I)
CANTXA (O)
GPBMUX1
EQEP2B (I)
EQEP2I (I/O)
EQEP2S (I/O)
Reserved(3)
Reserved(3)
Reserved(3)
TZ6 (I)
Reserved(3)
Reserved(3)
Reserved(3)
1-0
3-2
5-4
GPIO32
GPIO33
GPIO34
SDAA (I/OC)
SCLA (I/OC)
Reserved(3)
EPWMSYNCI (I)
EPWMSYNCO (O)
Reserved(3)
ADCSOCAO (O)
ADCSOCBO (O)
Reserved(3)
(1) GPxMUX1/2 refers to the appropriate MUX register for the pin; GPAMUX1, GPAMUX2 or GPBMUX1.
(2) This table pertains to the 2808 device. Some peripherals may not be available in the 2806 or 2801 devices. See the pin descriptions for
more detail.
(3) The word "Reserved" means that there is no peripheral assigned to this GPxMUX1/2 register setting. Should it be selected, the state of
the pin will be undefined and the pin may be driven. This selection is a reserved configuration for future expansion.
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The user can select the type of input qualification for each GPIO pin via the GPxQSEL1/2 registers from
four choices:
•
Synchronization To SYSCLKOUT Only (GPxQSEL1/2=0,0): This is the default mode of all GPIO pins
at reset and it simply synchronizes the input signal to the system clock (SYSCLKOUT).
•
Qualification Using Sampling Window (GPxQSEL1/2=0,1 and 1,0): In this mode the input signal, after
synchronization to the system clock (SYSCLKOUT), is qualified by a specified number of cycles before
the input is allowed to change.
Time between samples
GPyCTRL Reg
Input Signal
Qualified By 3
or 6 Samples
Qualification
GPIOx
SYNC
GPxQSEL
SYSCLKOUT
Number of Samples
Figure 4-17. Qualification Using Sampling Window
•
•
The sampling period is specified by the QUALPRD bits in the GPxCTRL register and is configurable in
groups of 8 signals. It specifies a multiple of SYSCLKOUT cycles for sampling the input signal. The
sampling window is either 3-samples or 6-samples wide and the output is only changed when ALL
samples are the same (all 0s or all 1s) as shown in Figure 4-18 (for 6 sample mode).
No Synchronization (GPxQSEL1/2=1,1): This mode is used for peripherals where synchronization is
not required (synchronization is performed within the peripheral).
Due to the multi-level multiplexing that is required on the 280x device, there may be cases where a
peripheral input signal can be mapped to more then one GPIO pin. Also, when an input signal is not
selected, the input signal will default to either a 0 or 1 state, depending on the peripheral.
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5
Device Support
Texas Instruments (Texas Instruments) offers an extensive line of development tools for the C28x™
generation of DSPs, including tools to evaluate the performance of the processors, generate code,
develop algorithm implementations, and fully integrate and debug software and hardware modules.
The following products support development of 280x-based applications:
Software Development Tools
•
Code Composer Studio™ Integrated Development Environment (IDE)
–
–
–
–
C/C++ Compiler
Code generation tools
Assembler/Linker
Cycle Accurate Simulator
•
•
Application algorithms
Sample applications code
Hardware Development Tools
•
•
•
•
2808 eZdsp™
JTAG-based emulators - SPI515, XDS510PP, XDS510PP Plus, XDS510USB™
Universal 5-V dc power supply
Documentation and cables
5.1 Device and Development Support Tool Nomenclature
To designate the stages in the product development cycle, Texas Instruments assigns prefixes to the part
numbers of all TMS320™ DSP devices and support tools. Each TMS320™ DSP commercial family
member has one of three prefixes: TMX, TMP, or TMS. Texas Instruments recommends two of three
possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary
stages of product development from engineering prototypes (TMX/TMDX) through fully qualified
production devices/tools (TMS/TMDS).
Device development evolutionary flow:
TMX
TMP
TMS
Experimental device that is not necessarily representative of the final device's electrical
specifications
Final silicon die that conforms to the device's electrical specifications but has not completed
quality and reliability verification
Fully qualified production device
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal qualification
testing
TMDS Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped against the following
disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully and the quality and
reliability of the device have been demonstrated fully. Texas Instruments standard warranty applies.
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Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production
system because their expected end-use failure rate still is undefined. Only qualified production devices are
to be used.
Texas Instruments device nomenclature also includes a suffix with the device family name. This suffix
indicates the package type (for example, PBK) and temperature range (for example, A). Figure 5-1
provides a legend for reading the complete device name for any family member.
M
E P - E n h an ce d P las tic
T EM PER AT U R E R A N GE
SM 320
F
2808
PZ
P R E FI X
SM
A
S
Q
M
=
=
=
=
- 405C to 85 5C
- 405C to 12 5 5C
- 405C to 12 5 5C
- 55 5C to 12 5 5C
=
C o mme rc ia l P ro c e ss i ng
PAC KA GE T Y P E
DEVICE FAMILY
32 0 T MS 32 0E D S P F a mily
P Z
=
10 0Ćp in lo w p r o file q u ad
fla tp ac k (L Q F P)
=
G GM
Z GM
=
=
10 0Ćb a ll b all g r id ar r ay (B GA )
10 0Ćb a ll BG A le ad Ćfr ee
DE V IC E
28 08
28 06
28 01
T EC H N O L O G Y
F
=
F la s h E E P R O M (1 . 8Ć V C o re /3 .3 Ć V I/ O )
Figure 5-1. Example of SM320x280x Device Nomenclature
X
UCD
9501
PZ
A
P R E FI X
T E MP E RAT URE RANGE
X
=
e xp e ri me n ta l d e vi ce
B la n k = q u al ifi e d d e vi ce
A
=
- 405C to 85 5C
PAC KA GE T Y P E
DEVICE FAMILY
U C D = U C D F a mily
P Z
=
10 0Ćp in lo w p r o file q u ad
fla tp ac k (L Q F P)
D E V IC E
Figure 5-2. Example of UCD Device Nomenclature
5.2 Documentation Support
Extensive documentation supports all of the TMS320™ DSP family generations of devices from product
announcement through applications development. The types of documentation available include: data
sheets and data manuals, with design specifications; and hardware and software applications.
TMS320x280x device reference guides are applicable to the UCD9501 device as well. Useful reference
documentation includes:
SPRU051: TMS320x281x, 280x Serial Communication Interface (SCI) Reference Guide
Describes the SCI, which is a two-wire asynchronous serial port, commonly known as a
UART. The SCI modules support digital communications between the CPU and other
asynchronous peripherals that use the standard non-return-to-zero (NRZ) format.
SPRU059: TMS320x281x, 280x Serial Peripheral Interface (SPI) Reference Guide
Describes the SPI - a high-speed synchronous serial input/output (I/O) port that allows a
serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the
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device at a programmed bit-transfer rate. The SPI is used for communications between the
DSP controller and external peripherals or another controller.
SPRU074: TMS320x281x, 280x Enhanced Controller Area Network (eCAN) Reference Guide
Describes the eCAN that uses established protocol to communicate serially with other
controllers in electrically noisy environments. With 32 fully configurable mailboxes and
time-stamping feature, the eCAN module provides
a versatile and robust serial
communication interface. The eCAN module implemented in the 281x DSP is compatible
with the CAN 2.0B standard (active).
SPRU430: TMS320C28x DSP CPU and Instruction Set Reference Guide
Describes the central processing unit (CPU) and the assembly language instructions of the
TMS320C28x fixed-point digital signal processors (DSPs). It also describes emulation
features available on these DSPs.
SPRU513: TMS320C28x Assembly Language Tools User's Guide
Describes the assembly language tools (assembler and other tools used to develop
assembly language code), assembler directives, macros, common object file format, and
symbolic debugging directives for the TMS320C28x device.
SPRU514: TMS320C28x Optimizing C Compiler User's Guide
describes the TMS320C28x C/C++ compiler. This compiler accepts ANSI standard C/C++
source code and produces TMS320 DSP assembly language source code for the
TMS320C28x device.
SPRU566: TMS320x281x, 280x Peripheral Reference Guide
Describes the peripheral reference guides of the 28x digital signal processors (DSPs).
SPRU608: The TMS320C28x Instruction Set Simulator Technical Overview
Describes the simulator, available within the Code Composer Studio for TMS320C2000 IDE,
that simulates the instruction set of the C28x core.
SPRU625: TMS320C28x DSP/BIOS Application Programming Interface (API) Reference Guide
Describes development using DSP/BIOS.
SPRU712: TMS320x280x System Control and Interrupts Reference Guide
Describes the various interrupts and system control features of the 280x digital signal
processors (DSPs).
SPRU716: TMS320x280x Analog-to-Digital Converter (ADC) Reference Guide
Describes the ADC module. The module is a 12-bit pipelined ADC. The analog circuits of
this converter, referred to as the core in this document, include the front-end analog
multiplexers (MUXs), sample-and-hold (S/H) circuits, the conversion core, voltage regulators,
and other analog supporting circuits. Digital circuits, referred to as the wrapper in this
document, include programmable conversion sequencer, result registers, interface to analog
circuits, interface to device peripheral bus, and interface to other on-chip modules.
SPRU722: TMS320x280x Boot ROM Reference Guide
Describes the purpose and features of the bootloader (factory-programmed boot-loading
software). It also describes other contents of the device on-chip boot ROM and identifies
where all of the information is located within that memory.
SPRU790: TMS320x280x Enhanced Quadrature Encoder Pulse (eQEP) Reference Guide
Describes the eQEP module, which is used for interfacing with a linear or rotary incremental
encoder to get position, direction, and speed information from a rotating machine in high
performance motion and position control systems. It includes the module description and
registers.
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SPRU791: TMS320x280x Enhanced Pulse Width Modulator (ePWM) Module Reference Guide
The PWM peripheral is an essential part of controlling many of the power related systems
found in both commercial and industrial equipments. This guide describes the main areas
that include digital motor control, switch mode power supply control, UPS (uninterruptible
power supplies), and other forms of power conversion. The PWM peripheral can be
considered as performing a DAC function, where the duty cycle is equivalent to a DAC
analog value, it is sometimes referred to as a Power DAC.
SPRU807: TMS320x280x Enhanced Capture (eCAP) Module Reference Guide
Describes the enhanced capture module. It includes the module description and registers.
SPRU924: High-Resolution Pulse Width Modulator (HRPWM) describes the operation of the
high-resolution extension to the pulse width modulator (HRPWM)
SPRA550: 3.3 V DSP for Digital Motor Control describes a scenario of a 3.3-V-only motor controller
indicating that for most applications, no significant issue of interfacing between 3.3 V and 5 V
exists. On-chip 3.3-V analog-to-digital converter (ADC) versus 5-V ADC is also discussed.
Guidelines for component layout and printed circuit board (PCB) design that can reduce
system noise and EMI effects are summarized.
A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal
processing research and education. The TMS320 DSP newsletter, Details on Signal Processing, is
published quarterly and distributed to update TMS320 DSP customers on product information.
Updated information on the TMS320 DSP controllers can be found on the worldwide web at:
http://www.ti.com.
To send comments regarding this data manual (literature number SPRS230), use the
comments@books.sc.ti.com email address, which is a repository for feedback. For questions and support,
contact the Product Information Center listed at the http://www.ti.com/sc/docs/pic/home.htm site.
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6
Electrical Specifications
This section provides the absolute maximum ratings and the recommended operating conditions for the
TMS320F280x DSPs.
6.1 Absolute Maximum Ratings(1)(2)
Unless otherwise noted, the list of absolute maximum ratings are specified over operating temperature ranges.
Supply voltage range, VDDIO, VDD3VFL
Supply voltage range, VDDA2, VDDAIO
Supply voltage range, VDD
with respect to VSS
with respect to VSSA
with respect to VSS
with respect to VSSA
with respect to VSS
-0.3 V to 4.6 V
-0.3 V to 4.6 V
-0.3 V to 2.5 V
-0.3 V to 2.5 V
-0.3 V to 0.3 V
-0.3 V to 4.6 V
-0.3 V to 4.6 V
±20 mA
Supply voltage range, VDD1A18, VDD2A18
Supply voltage range, VSSA2, VSSAIO, VSS1AGND, VSS2AGND
Input voltage range, VIN
Output voltage range, VO
(3)
Input clamp current, IIK (VIN < 0 or VIN > VDDIO
)
Output clamp current, IOK (VO < 0 or VO > VDDIO
)
±20 mA
(4)
Operating ambient temperature ranges, TA
Junction temperature range, Tj(4)
-55°C to 125°C
-55°C to 150°C
- 65°C to 150°C
(4)
Storage temperature range, Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 6.2 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, unless otherwise noted.
(3) Continuous clamp current per pin is ± 2 mA. This includes the analog inputs which have an internal clamping circuit that clamps the
voltage to a diode drop above VDDA2 or below VSSA2
.
(4) Long-term high-temperature storage and/or extended use at maximum temperature conditions may result in a reduction of overall device
life. For additional information, see IC Package Thermal Metrics Application Report (literature number SPRA953) and Reliability Data for
TMS320LF24x and TMS320F281x Devices Application Report (literature number SPRA963)
6.2 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3.14
1.71
NOM
3.3
1.8
0
MAX
3.47
1.89
UNIT
V
Device supply voltage, I/O, VDDIO
Device supply voltage CPU, VDD
Supply ground, VSS, VSSIO
V
V
ADC supply voltage (3.3 V), VDDA2, VDDAIO
ADC supply voltage (1.8 V), VDD1A18, VDD2A18
Flash supply voltage, VDD3VFL
3.14
1.71
3.14
2
3.3
1.8
3.3
3.47
1.89
3.47
100
VDDIO
0.8
-4
V
V
V
Device clock frequency (system clock), fSYSCLKOUT
High-level input voltage, VIH
MHz
V
2
Low-level input voltage, VIL
All I/Os except Group 2
Group 2(1)
mA
mA
°C
High-level output source current, VOH = 2.4 V, IOH
-8
All I/Os except Group 2
Group 2(1)
4
Low-level output sink current, VOL = VOL MAX, IOL
Ambient temperature, TA
8
-55
125
(1) Group 2 pins are as follows: GPIO28, GPIO29, GPIO30, GPIO31, TDO, XCLKOUT, EMU0, and EMU1
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6.3 Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
2.4
TYP
MAX UNIT
IOH = IOHMAX
VOH High-level output voltage
VOL Low-level output voltage
V
IOH = 50 µA
VDDIO - 0.2
IOL = IOLMAX
0.4
-190
±2
V
With pullup
VDDIO = 3.3 V, VIN = 0 V
VDDIO = 3.3 V, VIN = 0 V
VDDIO = 3.3 V, VIN = VDD
VDDIO = 3.3 V, VIN = VDD
All I/Os (including XRS)
-80
38
-140
Input current
(low level)
IIL
µA
Pullup disabled
With pullup
±2
Input current
(high level)
IIH
µA
Pullup disabled
50
2
80
Output current, high-impedance
state (off-state)
IOZ
CI
VO = VDDIO or 0 V
±2
µA
Input capacitance
pF
6.4 Current Consumption
Table 6-1. SM320F2808 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT
(1)
(2)
(3)
IDD
IDDIO
TYP(4)
IDD3VFL
IDDA18
TYP(4)
IDDA33
TYP(4)
MODE
TEST CONDITIONS
TYP(4)
MAX
MAX
TYP
MAX
MAX
MAX
The following peripheral
clocks are enabled:
•
•
•
•
•
•
•
•
ePWM1/2/3/4/5/6
eCAP1/2/3/4
eQEP1/2
eCAN-A
SCI-A/B
SPI-A
ADC
I2C
Operational
(Flash)
195 mA
230 mA
15 mA
27 mA
35 mA
40 mA
30 mA
38 mA
1.5 mA
2 mA
All PWM pins are toggled
at 100 kHz.
Data is continuously
transmitted out of the
SCI-A, SCI-B, and
eCAN-A ports. The
hardware multiplier is
exercised.
Code is running out of
flash with 3 wait states.
XCLKOUT is turned off.
Flash is powered down.
XCLKOUT is turned off.
The following peripheral
clocks are enabled:
IDLE
75 mA
90 mA
12 mA
500 µA
2 mA
2 µA
10 µA
5 µA
50 µA
15 µA
30 µA
•
•
•
•
eCAN-A
SCI-A
SPI-A
I2C
Flash is powered down.
Peripheral clocks are off.
STANDBY
HALT
6 mA
100 µA
60 µA
500 µA
120 µA
2 µA
2 µA
10 µA
10 µA
5 µA
5 µA
50 µA
50 µA
15 µA
15 µA
30 µA
30 µA
Flash is powered down.
Peripheral clocks are off.
Input clock is disabled.
70 µA
(1) IDDIO current is dependent on the electrical loading on the I/O pins.
(2) IDDA18 includes current into VDD1A18 and VDD2A18 pins.
(3) IDDA33 includes current into VDDA2 and VDDAIO pins.
(4) The TYP numbers are applicable over room temperature and nominal voltage.
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CAUTION
The peripheral - I/O multiplexing implemented in the 280x devices prevents all
available peripherals from being used at the same time. This is because more than
one peripheral function may share an I/O pin. It is, however, possible to turn on the
clocks to all the peripherals at the same time, although such a configuration is not
useful. If this is done, the current drawn by the device will be more than the numbers
specified in the current consumption tables.
Table 6-2. F2806 Current Consumption by Power-supply Pins at 100 MHz SYSCLKOUT
(1)
(2)
(3)
IDD
IDDIO
TYP(4)
IDD3VFL
IDDA18
TYP(4)
IDDA33
TYP(4)
MAX
MODE
TEST CONDITIONS
TYP(4)
MAX
MAX
TYP(4)
MAX
MAX
The following peripheral
clocks are enabled:
•
•
•
•
•
•
•
•
ePWM1/2/3/4/5/6
eCAP1/2/3/4
eQEP1/2
eCAN-A
SCI-A/B
SPI-A
ADC
I2C
Operational
(Flash)
195 mA
230 mA
15 mA
27 mA
35 mA
40 mA
30 mA
38 mA
1.5 mA
2 mA
All PWM pins are toggled at
100 kHz.
Data is continuously
transmitted out of the
SCI-A, SCI-B, and eCAN-A
ports. The hardware
multiplier is exercised.
Code is running out of flash
with 3 wait states.
XCLKOUT is turned off
Flash is powered down.
XCLKOUT is turned off.
The following peripheral
clocks are enabled:
IDLE
75 mA
90 mA
12 mA
500 µA
2 mA
2 µA
10 µA
5 µA
50 µA
15 µA
30 µA
•
•
•
•
eCAN-A
SCI-A
SPI-A
I2C
Flash is powered down.
Peripheral clocks are off.
STANDBY
HALT
6 mA
100 µA
60 µA
500 µA
120 µA
2 µA
2 µA
10 µA
10 µA
5 µA
5 µA
50 µA
50 µA
15 µA
15 µA
30 µA
30 µA
Flash is powered down.
Peripheral clocks are off.
Input clock is disabled.
70 µA
(1) IDDIO current is dependent on the electrical loading on the I/O pins.
(2) IDDA18 includes current into VDD1A18 and VDD2A18 pins.
(3) IDDA33 includes current into VDDA2 and VDDAIO pins.
(4) The TYP numbers are applicable over room temperature and nominal voltage.
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16
14
12
10
8
6
EM Life
4
2
Wirebond Life
Voiding Effects
0
100 105 110 115 120 125 130 135 140 145 150
T − Junction Temperature − °C
J
G001
Figure 6-1. Wirebond / EM Life for SM320F280xPZMEP
CAUTION
The peripheral - I/O multiplexing implemented in the 280x devices prevents all
available peripherals from being used at the same time. This is because more than
one peripheral function may share an I/O pin. It is, however, possible to turn on the
clocks to all the peripherals at the same time, although such a configuration is not
useful. If this is done, the current drawn by the device will be more than the numbers
specified in the current consumption tables.
Table 6-3. F2801/UCD9501 Current Consumption by Power-supply Pins at 100-MHz SYSCLKOUT
(1)
(2)
(3)
IDD
IDDIO
TYP(4)
IDD3VFL
TYP(4)
IDDA18
TYP(4)
IDDA33
TYP(4)
MODE
TEST CONDITIONS
TYP(4)
MAX
MAX
MAX
MAX
MAX
The following peripheral
clocks are enabled:
•
•
•
•
•
•
•
•
ePWM1/2/3
eCAP1/2
eQEP1
eCAN-A
SCI-A
SPI-A
ADC
I2C
Operational
(Flash)
180 mA
210 mA
15 mA
27 mA
35 mA
40 mA
30 mA
38 mA
1.5 mA
2 mA
All PWM pins are toggled at
100 kHz.
Data is continuously
transmitted out of the SCI-A,
SCI-B, and eCAN-A ports.
The hardware multiplier is
exercised.
Code is running out of flash
with 3 wait states.
XCLKOUT is turned off.
(1) IDDIO current is dependent on the electrical loading on the I/O pins.
(2) IDDA18 includes current into VDD1A18 and VDD2A18 pins.
(3) IDDA33 includes current into VDDA2 and VDDAIO pins.
(4) The TYP numbers are applicable over room temperature and nominal voltage.
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Table 6-3. F2801/UCD9501 Current Consumption by Power-supply Pins at 100-MHz SYSCLKOUT
(continued)
(1)
(2)
(3)
IDD
IDDIO
TYP(4)
IDD3VFL
TYP(4)
IDDA18
TYP(4)
IDDA33
TYP(4)
MODE
TEST CONDITIONS
TYP(4)
MAX
MAX
MAX
MAX
MAX
Flash is powered down.
XCLKOUT is turned off.
The following peripheral
clocks are enabled:
IDLE
75 mA
90 mA
500 µA
2 mA
2 µA
10 µA
5 µA
50 µA
15 µA
30 µA
•
•
•
•
eCAN-A
SCI-A
SPI-A
I2C
Flash is powered down.
Peripheral clocks are off.
STANDBY
HALT
6 mA
12 mA
100 µA
60 µA
500 µA
120 µA
2 µA
2 µA
10 µA
10 µA
5 µA
5 µA
50 µA
50 µA
15 µA
15 µA
30 µA
30 µA
Flash is powered down.
Peripheral clocks are off.
Input clock is disabled.
70 µA
6.4.1 Reducing Current Consumption
280x devices have a richer peripheral mix compared to the 281x family. While the McBSP has been
removed, the following new peripherals have been added on the 280x:
•
•
•
3 SPI modules
1 CAN module
1 I2C module
The two event manager modules of the 281x have been enhanced and replaced with separate ePWM (6),
eCAP (4) and eQEP (2) modules, providing tremendous flexibility in applications. Like 281x, 280x DSPs
incorporate a unique method to reduce the device current consumption. Since each peripheral unit has an
individual clock-enable bit, significant reduction in current consumption can be achieved by turning off the
clock to any peripheral module that is not used in a given application. Furthermore, any one of the three
low-power modes could be taken advantage of to reduce the current consumption even further. Table 6-4
indicates the typical reduction in current consumption achieved by turning off the clocks.
Table 6-4. Typical Current Consumption by Various
Peripherals (at 100 MHz)(1)
PERIPHERAL
MODULE
IDD CURRENT
REDUCTION (mA)
ADC
I2C
8(2)
5
eQEP
ePWM
eCAP
SCI
5
5
2
4
SPI
5
eCAN
11
(1) All peripheral clocks are disabled upon reset. Writing to/reading
from peripheral registers is possible only after the peripheral clocks
are turned on.
(2) This number represents the current drawn by the digital portion of
the ADC module. Turning off the clock to the ADC module results in
the elimination of the current drawn by the analog portion of the
ADC (IDDA18) as well.
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NOTE
The baseline IDD current (current when the core is executing a dummy loop with no
peripherals enabled) is 110 mA, typical. To arrive at the IDD current for a given application,
the current-drawn by the peripherals (enabled by that application) must be added to the
baseline IDD current.
6.4.2 Current Consumption Graphs
250.0
200.0
150.0
100.0
50.0
0.0
10
20
30
40
50
60
70
80
90
100
SYSCLKOUT (MHz)
1.8-V current
IDD
IDDA18
IDDIO
IDD3VFL
3.3-V current
Figure 6-2. Typical Operational Current Versus Frequency (F2808)
600.0
500.0
400.0
300.0
200.0
100.0
0.0
10
20
30
40
50
60
70
80
90
100
SYSCLKOUT (MHz)
TOTAL POWER
Figure 6-3. Typical Operational Power Versus Frequency (F2808)
6.5 Timing Parameter Symbology
Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the
symbols, some of the pin names and other related terminology have been abbreviated as follows:
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Lowercase subscripts and their
meanings:
Letters and symbols and their
meanings:
a
c
d
access time
H
L
High
cycle time (period)
delay time
Low
V
Valid
Unknown, changing, or don't
care level
f
fall time
X
Z
h
r
hold time
High impedance
rise time
su
t
setup time
transition time
valid time
v
w
pulse duration (width)
6.5.1 General Notes on Timing Parameters
All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that
all output transitions for a given half-cycle occur with a minimum of skewing relative to each other.
The signal combinations shown in the following timing diagrams may not necessarily represent actual
cycles. For actual cycle examples, see the appropriate cycle description section of this document.
6.5.2 Test Load Circuit
This test load circuit is used to measure all switching characteristics provided in this document.
Tester Pin Electronics
Data Sheet Timing Reference Point
Output
Under
Test
42 Ω
3.5 nH
Transmission Line
(Α)
Z0 = 50 Ω
(B)
Device Pin
4.0 pF
1.85 pF
A. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the
device pin.
B. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to
produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to
add or subtract the transmission line delay (2 ns or longer) from the data sheet timing.
Figure 6-4. 3.3-V Test Load Circuit
6.5.3 Device Clock Table
This section provides the timing requirements and switching characteristics for the various clock options
available on the 280x DSPs. Table 6-5 lists the cycle times of various clocks.
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Table 6-5. TMS320x280x Clock Table and Nomenclature
MIN
28.6
20
10
4
NOM
MAX UNIT
tc(OSC), Cycle time
Frequency
50
35
ns
MHz
ns
On-chip oscillator
clock
tc(CI), Cycle time
Frequency
250
100
500
100
2000
100
XCLKIN(1)
SYSCLKOUT
XCLKOUT
HSPCLK(2)
LSPCLK(2)
ADC clock
MHz
ns
tc(SCO), Cycle time
Frequency
10
2
MHz
ns
tc(XCO), Cycle time
Frequency
10
0.5
10
MHz
ns
tc(HCO), Cycle time
Frequency
20(3)
50(3)
40(3)
25(3)
100
100
MHz
ns
tc(LCO), Cycle time
Frequency
10
80
MHz
ns
tc(ADCCLK), Cycle time
Frequency
12.5
MHz
(1) This also applies to the X1 pin if a 1.8-V oscillator is used.
(2) Lower LSPCLK and HSPCLK will reduce device power consumption.
(3) This is the default reset value if SYSCLKOUT = 100 MHz.
6.6 Clock Requirements and Characteristics
Table 6-6. Input Clock Frequency
PARAMETER
Resonator (X1/X2)
MIN
TYP MAX UNIT
20
20
4
35
Crystal (X1/X2)
35
MHz
100
fx
Input clock frequency
Without PLL
With PLL
External oscillator/clock
source (XCLKIN or X1 pin)
5
30
fl
Limp mode clock frequency range
1-5
MHz
Table 6-7. XCLKIN(1) Timing Requirements - PLL Enabled
NO.
C8
MIN
MAX UNIT
tc(CI)
tf(CI)
Cycle time, XCLKIN
33.3
200
6
ns
ns
ns
%
C9
Fall time, XCLKIN
C10 tr(CI)
Rise time, XCLKIN
6
C11 tw(CIL)
C12 tw(CIH)
Pulse duration, XCLKIN low as a percentage of tc(OSCCLK)
Pulse duration, XCLKIN high as a percentage of tc(OSCCLK)
45
45
55
55
%
(1) This applies to the X1 pin also.
Table 6-8. XCLKIN(1) Timing Requirements - PLL Disabled
NO.
C8
MIN
MAX UNIT
tc(CI)
tf(CI)
Cycle time, XCLKIN
Fall time, XCLKIN
10
250
6
ns
ns
ns
ns
ns
C9
Up to 20 MHz
20 MHz to 100 MHz
Up to 20 MHz
2
C10 tr(CI)
Rise time, XCLKIN
6
20 MHz to 100 MHz
2
(1) This applies to the X1 pin also.
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Table 6-8. XCLKIN Timing Requirements - PLL Disabled (continued)
NO.
MIN
45
45
MAX UNIT
C11 tw(CIL)
C12 tw(CIH)
Pulse duration, XCLKIN low as a percentage of tc(OSCCLK)
Pulse duration, XCLKIN high as a percentage of tc(OSCCLK)
55
55
%
%
The possible configuration modes are shown in Table 3-15.
Table 6-9. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)(1)(2)
NO.
C1
C3
C4
C5
C6
PARAMETER
Cycle time, XCLKOUT
MIN
TYP
MAX
UNIT
ns
tc(XCO)
tf(XCO)
tr(XCO)
tw(XCOL)
tw(XCOH)
tp
10
Fall time, XCLKOUT
2
2
ns
Rise time, XCLKOUT
Pulse duration, XCLKOUT low
Pulse duration, XCLKOUT high
PLL lock time
ns
H-2
H-2
H+2
ns
H+2
ns
(3)
131072tc(OSCCLK)
cycles
(1) A load of 40 pF is assumed for these parameters.
(2) H = 0.5tc(XCO)
(3) OSCCLK is either the output of the on-chip oscillator or the output from an external oscillator.
C10
C9
C8
(A)
XCLKIN
C6
C3
C1
C4
C5
(B)
XCLKOUT
A. The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown is
intended to illustrate the timing parameters only and may differ based on actual configuration.
B. XCLKOUT configured to reflect SYSCLKOUT.
Figure 6-5. Clock Timing
6.7 Power Sequencing
No requirements are placed on the power up/down sequence of the various power pins to ensure the
correct reset state for all the modules. However, if the 3.3-V transistors in the level shifting output buffers
of the I/O pins are powered prior to the 1.8-V transistors, it is possible for the output buffers to turn on,
causing a glitch to occur on the pin during power up. To avoid this behavior, power the VDD pins prior to or
simultaneously with the VDDIO pins, ensuring that the VDD pins have reached 0.7 V before the VDDIO pins
reach 0.7 V.
There are some requirements on the XRS pin:
1. During power up, the XRS pin must be held low for tw(RSL1) after the input clock is stable (see
Table 6-11). This is to enable the entire device to start from a known condition.
2. During power down, the XRS pin must be pulled low at least 8 µs prior to VDD reaching 1.5 V. This is to
enhance flash reliability.
Additionally it is recommended that no voltage larger than a diode drop (0.7 V) should be applied to any
pin prior to powering up the device. Voltages applied to pins on an unpowered device can bias internal p-n
junctions in unintended ways and produce unpredictable results.
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6.7.1 Power Management and Supervisory Circuit Solutions
Table 6-10 lists the power management and supervisory circuit solutions for 280x DSPs. LDO selection
depends on the total power consumed in the end application. Go to www.power.ti.com for a complete list
of Texas Instruments power ICs or select Texas Instruments DSP Power Solutions for links to the DSP
Power Selection Guide (slub006a.pdf) and links to specific power reference designs.
Table 6-10. Power Management and Supervisory Circuit Solutions
SUPPLIER
TYPE
LDO
PART
DESCRIPTION
Texas Instruments
Texas Instruments
Texas Instruments
Texas Instruments
Texas Instruments
Texas Instruments
Texas Instruments
Texas Instruments
Texas Instruments
TPS767D301 Dual 1-A low-dropout regulator (LDO) with supply voltage supervisor (SVS)
LDO
TPS70202
TPS766xx
TPS3808
TPS3803
TPS799xx
TPS736xx
TPS62110
TPS6230x
Dual 500/250-mA LDO with SVS
LDO
250-mA LDO with PG
SVS
Open Drain SVS with programmable delay
Low-cost Open-drain SVS with 5 µS delay
200-mA LDO in WCSP package
SVS
LDO
LDO
400-mA LDO with 40 mV of VDO
DC/DC
DC/DC
High Vin 1.2-A dc/dc converter in 4x4 QFN package
500-mA converter in WCSP package
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V
, V
DDIO DD3VFL
V
, V
DDA2 DDAIO
(3.3 V)
V
, V
DD DD1A18,
V
DD2A18
(1.8 V)
XCLKIN
X1/X2
(A)
OSCCLK/8
XCLKOUT
XRS
User-Code Dependent
t
OSCST
t
w(RSL1)
Address/Data Valid. Internal Boot-ROM Code Execution Phase
Address/Data/
Control
(Internal)
User-Code Execution Phase
User-Code Dependent
t
d(EX)
(B)
h(boot-mode)
t
Boot-Mode
Pins
GPIO Pins as Input
Boot-ROM Execution Starts
Peripheral/GPIO Function
Based on Boot Code
(C)
GPIO Pins as Input (State Depends on Internal PU/PD)
User-Code Dependent
I/O Pins
A. Upon power up, SYSCLKOUT is OSCCLK/2. Since the XCLKOUTDIV bits in the XCLK register come up with a reset
state of 0, SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. This explains why XCLKOUT =
OSCCLK/8 during this phase.
B. After reset, the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code
branches to destination memory or boot code function. If boot ROM code executes after power-on conditions (in
debugger environment), the boot code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT
will be based on user environment and could be with or without PLL enabled.
Figure 6-6. Power-on Reset
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Table 6-11. Reset (XRS) Timing Requirements
MIN
8tc(OSCCLK)
8tc(OSCCLK)
NOM
MAX
UNIT
(1)
tw(RSL1)
tw(RSL2)
Pulse duration, stable XCLKIN to XRS high
Pulse duration, XRS low
cycles
cycles
Warm reset
Pulse duration, reset pulse generated by
watchdog
tw(WDRS)
td(EX)
512tc(OSCCLK)
cycles
Delay time, address/data valid after XRS high
Oscillator start-up time
32tc(OSCCLK)
10
cycles
ms
(2)
tOSCST
1
th(boot-mode)
Hold time for boot-mode pins
200tc(OSCCLK)
cycles
(1) In addition to the tw(RSL1) requirement, XRS has to be low at least for 1 ms after VDD reaches 1.5 V.
(2) Dependent on crystal/resonator and board design.
XCLKIN
X1/X2
OSCCLK/8
XCLKOUT
XRS
User-Code Dependent
OSCCLK * 5
t
w(RSL2)
User-Code Execution Phase
t
d(EX)
Address/Data/
Control
(Don’t Care)
User-Code Execution
(Internal)
(A)
t
Boot-ROM Execution Starts
GPIO Pins as Input
h(boot-mode)
Boot-Mode
Pins
Peripheral/GPIO Function
User-Code Dependent
Peripheral/GPIO Function
User-Code Execution Starts
I/O Pins
GPIO Pins as Input (State Depends on Internal PU/PD)
User-Code Dependent
A. After reset, the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code
branches to destination memory or boot code function. If Boot ROM code executes after power-on conditions (in
debugger environment), the Boot code execution time is based on the current SYSCLKOUT speed. The
SYSCLKOUT will be based on user environment and could be with or without PLL enabled.
Figure 6-7. Warm Reset
Figure 6-8 shows an example for the effect of writing into PLLCR register. In the first phase, PLLCR =
0x0004 and SYSCLKOUT = OSCCLK x 2. The PLLCR is then written with 0x0008. Right after the PLLCR
register is written, the PLL lock-up phase begins. During this phase, SYSCLKOUT = OSCCLK/2. After the
PLL lock-up is complete (which takes 131072 OSCCLK cycles), SYSCLKOUT reflects the new operating
frequency, OSCCLK x 4.
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OSCCLK
Write to PLLCR
SYSCLKOUT
OSCCLK * 2
OSCCLK/2
OSCCLK * 4
(Current CPU
Frequency)
(CPU Frequency While PLL is Stabilizing
With the Desired Frequency. This Period
(Changed CPU Frequency)
(PLL Lock-up Time, t ) is
p
131072 OSCCLK Cycles Long.)
Figure 6-8. Example of Effect of Writing Into PLLCR Register
6.8 General-Purpose Input/Output (GPIO)
6.8.1 GPIO - Output Timing
Table 6-12. General-Purpose Output Switching Characteristics
PARAMETER
Rise time, GPIO switching low to high
Fall time, GPIO switching high to low
Toggling frequency, GPO pins
MIN
MAX
8
UNIT
ns
tr(GPO)
tf(GPO)
tfGPO
All GPIOs
All GPIOs
8
ns
25
MHz
GPIO
t
r(GPO)
t
f(GPO)
Figure 6-9. General-Purpose Output Timing
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6.8.2 GPIO - Input Timing
(A)
1
GPIO Signal
GPxQSELn = 1,0 (6 samples)
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
t
Sampling Period determined
by GPxCTRL[QUALPRD]
w(SP)
(B)
t
w(IQSW)
(C)
(SYSCLKOUT cycle * 2 * QUALPRD) * 5
)
Sampling Window
SYSCLKOUT
QUALPRD = 1
(SYSCLKOUT/2)
(D)
Output From
Qualifier
A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It
can vary from 00 to 0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLKOUT cycle. For any other value
"n", the qualification sampling period in 2n SYSCLKOUT cycles (i.e., at every 2n SYSCLKOUT cycles, the GPIO pin
will be sampled)..
B. The qualification period selected via the GPxCTRL register applies to groups of 8 GPIO pins.
C. The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is
used.
D. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or
greater. In other words, the inputs should be stable for (5 x QUALPRD x 2) SYSCLKOUT cycles. This would ensure 5
sampling periods for detection to occur. Since external signals are driven asynchronously, an 13-SYSCLKOUT-wide
pulse ensures reliable recognition.
Figure 6-10. Sampling Mode
Table 6-13. General-Purpose Input Timing Requirements
MIN
1tc(SCO)
MAX
UNIT
cycles
cycles
cycles
cycles
cycles
QUALPRD = 0
tw(SP)
Sampling period
QUALPRD ≠ 0
2tc(SCO) * QUALPRD
tw(SP) * (n(1) - 1)
2tc(SCO)
tw(IQSW)
Input qualifier sampling window
Pulse duration, GPIO low/high
Synchronous mode
With input qualifier
(2)
tw(GPI)
tw(IQSW) + tw(SP) + 1tc(SCO)
(1) "n" represents the number of qualification samples as defined by GPxQSELn register.
(2) For tw(GPI), pulse width is measured from VIL to VIL for an active low signal and VIH to VIH for an active high signal.
6.8.3 Sampling Window Width for Input Signals
The following section summarizes the sampling window width for input signals for various input qualifier
configurations.
Sampling frequency denotes how often a signal is sampled with respect to SYSCLKOUT.
Sampling frequency = SYSCLKOUT/(2 * QUALPRD), if QUALPRD ≠ 0
Sampling frequency = SYSCLKOUT, if QUALPRD = 0
Sampling period = SYSCLKOUT cycle x 2 x QUALPRD, if QUALPRD ≠ 0
In the above equations, SYSCLKOUT cycle indicates the time period of SYSCLKOUT.
Sampling period = SYSCLKOUT cycle, if QUALPRD = 0
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In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity of
the signal. This is determined by the value written to GPxQSELn register.
Case 1:
Qualification using 3 samples
Sampling window width = (SYSCLKOUT cycle x 2 x QUALPRD) x 2, if QUALPRD ≠ 0
Sampling window width = (SYSCLKOUT cycle) x 2, if QUALPRD = 0
Case 2:
Qualification using 6 samples
Sampling window width = (SYSCLKOUT cycle x 2 x QUALPRD) x 5, if QUALPRD ≠ 0
Sampling window width = (SYSCLKOUT cycle) x 5, if QUALPRD = 0
XCLKOUT
GPIOxn
t
w(GPI)
Figure 6-11. General-Purpose Input Timing
NOTE
The pulse-width requirement for general-purpose input is applicable for the
XINT2_ADCSOC signal as well.
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6.8.4 Low-Power Mode Wakeup Timing
Table 6-14 shows the timing requirements, Table 6-15 shows the switching characteristics, and
Figure 6-12 shows the timing diagram for IDLE mode.
Table 6-14. IDLE Mode Timing Requirements(1)
MIN NOM
MAX
UNIT
Without input qualifier
With input qualifier
2tc(SCO)
5tc(SCO) + tw(IQSW)
tw(WAKE-INT) Pulse duration, external wake-up signal
cycles
(1) For an explanation of the input qualifier parameters, see Table 6-13.
Table 6-15. IDLE Mode Switching Characteristics(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Delay time, external wake signal to
(2)
program execution resume
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
20tc(SCO)
20tc(SCO) + tw(IQSW)
1050tc(SCO)
cycles
cycles
cycles
•
•
•
Wake-up from Flash
Flash module in active state
–
td(WAKE-IDLE)
Wake-up from Flash
Flash module in sleep state
–
1050tc(SCO) + tw(IQSW)
20tc(SCO)
Wake-up from SARAM
20tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Table 6-13.
(2) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered
by the wake up) signal involves additional latency.
t
d(WAKE−IDLE)
Addres/Data
(internal)
XCLKOUT
t
w(WAKE−INT)
(A)
WAKE INT
A. WAKE INT can be any enabled interrupt, WDINT, XNMI, or XRS.
Figure 6-12. IDLE Entry and Exit Timing
Table 6-16. STANDBY Mode Timing Requirements
TEST CONDITIONS
MIN
NOM
MAX
UNIT
Without input qualification
With input qualification(1)
3tc(OSCCLK)
tw(WAKE-
Pulse duration, external
wake-up signal
cycles
INT)
(2 + QUALSTDBY) * tc(OSCCLK)
(1) QUALSTDBY is a 6-bit field in the LPMCR0 register.
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Table 6-17. STANDBY Mode Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Delay time, IDLE instruction
executed to XCLKOUT low
td(IDLE-XCOL)
32tc(SCO)
45tc(SCO)
cycles
Delay time, external wake signal
to program execution resume(1)
cycles
cycles
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
100tc(SCO)
100tc(SCO) + tw(WAKE-INT)
1125tc(SCO)
•
Wake up from flash
–
Flash module in active
state
td(WAKE-STBY)
•
Wake up from flash
cycles
cycles
–
Flash module in sleep
state
1125tc(SCO) + tw(WAKE-INT)
Without input qualifier
With input qualifier
100tc(SCO)
•
Wake up from SARAM
100tc(SCO) + tw(WAKE-INT)
(1) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered
by the wake up signal) involves additional latency.
(A)
(C)
(E)
(D)
(B)
(F)
Device
Status
STANDBY
STANDBY
Normal Execution
Flushing Pipeline
Wake−up
Signal
t
w(WAKE-INT)
t
d(WAKE-STBY)
X1/X2 or
X1 or
XCLKIN
XCLKOUT
t
d(IDLE−XCOL)
A. IDLE instruction is executed to put the device into STANDBY mode.
B. The PLL block responds to the STANDBY signal. SYSCLKOUT is held for approximately 32 cycles before being
turned off. This 32-cycle delay enables the CPU pipe and any other pending operations to flush properly.
C. Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in
STANDBY mode.
D. The external wake-up signal is driven active.
E. After a latency period, the STANDBY mode is exited.
F. Normal execution resumes. The device will respond to the interrupt (if enabled).
Figure 6-13. STANDBY Entry and Exit Timing Diagram
Table 6-18. HALT Mode Timing Requirements
MIN NOM
MAX
UNIT
cycles
cycles
(1)
tw(WAKE-GPIO)
tw(WAKE-XRS)
Pulse duration, GPIO wake-up signal
Pulse duration, XRS wakeup signal
toscst + 2tc(OSCCLK)
toscst + 8tc(OSCCLK)
(1) See Table 6-11 for an explanation of toscst
.
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Table 6-19. HALT Mode Switching Characteristics
PARAMETER
MIN
TYP
MAX
UNIT
cycles
cycles
td(IDLE-XCOL)
tp
Delay time, IDLE instruction executed to XCLKOUT low
PLL lock-up time
32tc(SCO)
45tc(SCO)
131072tc(OSCCLK)
Delay time, PLL lock to program execution resume
1125tc(SCO)
35tc(SCO)
cycles
cycles
•
•
Wake up from flash
Flash module in sleep state
td(WAKE-HALT)
–
Wake up from SARAM
(G)
(A)
(C)
(E)
(B)
(D)
(F)
Device
Status
HALT
HALT
Flushing Pipeline
PLL Lock-up Time
Normal
Execution
Wake-up Latency
GPIOn
t
d(WAKE−HALT)
t
w(WAKE-GPIO)
t
p
X1/X2
or XCLKIN
Oscillator Start-up Time
XCLKOUT
t
d(IDLE−XCOL)
A. IDLE instruction is executed to put the device into HALT mode.
B. The PLL block responds to the HALT signal. SYSCLKOUT is held for approximately 32 cycles before the oscillator is
turned off and the CLKIN to the core is stopped. This 32-cycle delay enables the CPU pipe and any other pending
operations to flush properly.
C. Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as
the clock source, the internal oscillator is shut down as well. The device is now in HALT mode and consumes
absolute minimum power.
D. When the GPIOn pin is driven low, the oscillator is turned on and the oscillator wake-up sequence is initiated. The
GPIO pin should be driven high only after the oscillator has stabilized. This enables the provision of a clean clock
signal during the PLL lock sequence. Since the falling edge of the GPIO pin asynchronously begins the wakeup
procedure, care should be taken to maintain a low noise environment prior to entering and during HALT mode.
E. When GPIOn is deactivated, it initiates the PLL lock sequence, which takes 131,072 OSCCLK (X1/X2 or X1 or
XCLKIN) cycles.
F. When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after a latency. The HALT
mode is now exited.
G. Normal operation resumes.
Figure 6-14. HALT Wake Up Using GPIOn
6.9 Enhanced Control Peripherals
6.9.1 Enhanced Pulse Width Modulator (ePWM) Timing
PWM refers to PWM outputs on ePWM1-6. Table 6-20 shows the PWM timing requirements and
Table 6-21, switching characteristics.
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Table 6-20. ePWM Timing Requirements(1)
TEST CONDITIONS
Asynchronous
MIN
2tc(SCO)
MAX
UNIT
cycles
cycles
cycles
tw(SYCIN)
Sync input pulse width
Synchronous
2tc(SCO)
With input qualifier
1tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Table 6-13.
Table 6-21. ePWM Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
20
MAX
UNIT
ns
tw(PWM)
Pulse duration, PWMx output high/low
Sync output pulse width
tw(SYNCOUT)
td(PWM)tza
8tc(SCO)
cycles
ns
Delay time, trip input active to PWM forced high
Delay time, trip input active to PWM forced low
no pin load
25
20
td(TZ-PWM)HZ
Delay time, trip input active to PWM Hi-Z
ns
6.9.2 Trip-Zone Input Timing
(A)
XCLKOUT
t
w(TZ)
TZ
t
d(TZ-PWM)HZ
(B)
PWM
A. TZ - TZ1, TZ2, TZ3, TZ4, TZ5, TZ6
B. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM
recovery software.
Figure 6-15. PWM Hi-Z Characteristics
Table 6-22. Trip-Zone input Timing Requirements(1)
MIN
1tc(SCO)
MAX UNIT
cycles
tw(TZ)
Pulse duration, TZx input low
Asynchronous
Synchronous
2tc(SCO)
cycles
With input qualifier
1tc(SCO) + tw(IQSW)
cycles
(1) For an explanation of the input qualifier parameters, see Table 6-13.
Table 6-23 shows the high-resolution PWM switching characteristics.
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Table 6-23. High Resolution PWM Characteristics at SYSCLKOUT = (60 - 100 MHz)
MIN
TYP
MAX UNIT
Micro Edge Positioning (MEP) step size(1)
150
310
ps
(1) Maximum MEP step size is based on worst-case process, maximum temperature and maximum voltage. MEP step size will increase
with low voltage and high temperature and decrease with voltage and cold temperature.
Applications that use the HRPWM feature should use MEP Scale Factor Optimizer (SFO) estimation software functions. See the Texas
Instruments software libraries for details of using SFO function in end applications. SFO functions help to estimate the number of MEP
steps per SYSCLKOUT period dynamically while the HRPWM is in operation.
Table 6-24 shows the eCAP timing requirement and Table 6-25 shows the eCAP switching characteristics.
Table 6-24. Enhanced Capture (eCAP) Timing Requirement(1)
TEST CONDITIONS
Asynchronous
MIN
2tc(SCO)
MAX UNIT
cycles
tw(CAP)
Capture input pulse width
Synchronous
2tc(SCO)
cycles
With input qualifier
1tc(SCO) + tw(IQSW)
cycles
(1) For an explanation of the input qualifier parameters, see Table 6-13.
Table 6-25. eCAP Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
tw(APWM)
Pulse duration, APWMx output high/low
20
ns
Table 6-26 shows the eQEP timing requirement and Table 6-27 shows the eQEP switching
characteristics.
Table 6-26. Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements(1)
TEST CONDITIONS
Asynchronous/synchronous
With input qualifier
MIN
MAX
UNIT
cycles
cycles
cycles
cycles
cycles
cycles
cycles
cycles
cycles
cycles
tw(QEPP)
QEP input period
2tc(SCO)
2(1tc(SCO) + tw(IQSW)
)
tw(INDEXH)
tw(INDEXL)
tw(STROBH)
tw(STROBL)
QEP Index Input High time
QEP Index Input Low time
QEP Strobe High time
QEP Strobe Input Low time
Asynchronous/synchronous
With input qualifier
2tc(SCO)
2tc(SCO) +tw(IQSW)
2tc(SCO)
Asynchronous/synchronous
With input qualifier
2tc(SCO) + tw(IQSW)
2tc(SCO)
2tc(SCO) + tw(IQSW)
2tc(SCO)
Asynchronous/synchronous
With input qualifier
Asynchronous/synchronous
With input qualifier
2tc(SCO) +tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Table 6-13.
Table 6-27. eQEP Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
MAX
4tc(SCO)
6tc(SCO)
UNIT
cycles
cycles
td(CNTR)xin
Delay time, external clock to counter increment
td(PXCSOUT)QEP Delay time, QEP input edge to position compare sync output
Table 6-28. External ADC Start-of-Conversion Switching Characteristics
PARAMETER
MIN
MAX
UNIT
tw(ADCSOCAL)
Pulse duration, ADCSOCAO low
32tc(HCO)
cycles
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t
w(ADCSOCAL)
ADCSOCAO
or
ADCSOCBO
Figure 6-16. ADCSOCAO or ADCSOCBO Timing
6.9.3 External Interrupt Timing
t
w(INT)
XNMI, XINT1, XINT2
t
d(INT)
Address bus
(internal)
Interrupt Vector
Figure 6-17. External Interrupt Timing
Table 6-29. External Interrupt Timing Requirements(1)
TEST CONDITIONS
MIN
1tc(SCO)
MAX
UNIT
cycles
cycles
tw(INT)
Pulse duration, INT input low/high
Synchronous
With qualifier
1tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Table 6-13.
Table 6-30. External Interrupt Switching Characteristics(1)
PARAMETER
MIN
MAX
UNIT
td(INT)
Delay time, INT low/high to interrupt-vector fetch
tw(IQSW) + 12tc(SCO)
cycles
(1) For an explanation of the input qualifier parameters, see Table 6-13.
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6.9.4 I2C Electrical Specification and Timing
Table 6-31. I2C Timing
TEST CONDITIONS
MIN
MAX
400
UNIT
kHz
fSCL
SCL clock frequency
I2C clock module frequency is between 7
MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
vil
Low level input voltage
High level input voltage
Input hysteresis
0.3 VDDIO
V
V
Vih
0.7 VDDIO
Vhys
Vol
0.05 VDDIO
V
Low level output voltage
Low period of SCL clock
3 mA sink current
0
0.4
V
tLOW
I2C clock module frequency is between 7
MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
1.3
µs
tHIGH
High period of SCL clock
I2C clock module frequency is between 7
MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
0.6
-10
µs
lI
Input current with an input voltage
10
µA
between 0.1 VDDIO and 0.9 VDDIO MAX
6.9.5 Serial Peripheral Interface (SPI) Master Mode Timing
Table 6-32 lists the master mode timing (clock phase = 0) and Table 6-33 lists the timing (clock phase =
1). Figure 6-18 and Figure 6-19 show the timing waveforms.
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Table 6-32. SPI Master Mode External Timing (Clock Phase = 0)(1)(2)(3)(4)(5)
NO.
SPI WHEN (SPIBRR + 1) IS EVEN OR
SPIBRR = 0 OR 2
SPI WHEN (SPIBRR + 1) IS ODD
AND SPIBRR > 3
UNIT
MIN
4tc(LCO)
MAX
MIN
MAX
1
2
tc(SPC)M
Cycle time, SPICLK
128tc(LCO)
0.5tc(SPC)M
5tc(LCO)
127tc(LCO)
ns
ns
tw(SPCH)M
Pulse duration, SPICLK high
(clock polarity = 0)
0.5tc(SPC)M -10
0.5tc(SPC)M - 0.5tc(LCO) - 10
0.5tc(SPC)M - 0.5tc(LCO) - 10
0.5tc(SPC)M + 0.5tc(LCO)-10
0.5tc(SPC)M + 0.5tc(LCO)- 10
0.5tc(SPC)M - 0.5tc(LCO)
0.5tc(SPC)M - 0.5tc(LCO)
0.5tc(SPC)M + 0.5tc(LCO)
0.5tc(SPC)M + 0.5tc(LCO)
10
tw(SPCL)M
Pulse duration, SPICLK low
(clock polarity = 1)
0.5tc(SPC)M - 10
0.5tc(SPC)M - 10
0.5tc(SPC)M - 10
0.5tc(SPC)M
0.5tc(SPC)M
0.5tc(SPC)M
10
3
4
5
8
9
tw(SPCL)M
Pulse duration, SPICLK low
(clock polarity = 0)
ns
ns
tw(SPCH)M
Pulse duration, SPICLK high
(clock polarity = 1)
td(SPCH-SIMO)M
td(SPCL-SIMO)M
tv(SPCL-SIMO)M
tv(SPCH-SIMO)M
tsu(SOMI-SPCL)M
tsu(SOMI-SPCH)M
tv(SPCL-SOMI)M
tv(SPCH-SOMI)M
Delay time, SPICLK high to SPISIMO
valid (clock polarity = 0)
Delay time, SPICLK low to SPISIMO
valid (clock polarity = 1)
10
10
Valid time, SPISIMO data valid after
SPICLK low (clock polarity = 0)
0.5tc(SPC)M -10
0.5tc(SPC)M -10
35
0.5tc(SPC)M + 0.5tc(LCO) -10
0.5tc(SPC)M + 0.5tc(LCO) -10
35
Valid time, SPISIMO data valid after
SPICLK high (clock polarity = 1)
Setup time, SPISOMI before SPICLK
low (clock polarity = 0)
ns
ns
Setup time, SPISOMI before SPICLK
high (clock polarity = 1)
35
35
Valid time, SPISOMI data valid after
SPICLK low (clock polarity = 0)
0.25tc(SPC)M -10
0.25tc(SPC)M - 10
0.5tc(SPC)M- 0.5tc(LCO)- 10
0.5tc(SPC)M- 0.5tc(LCO)- 10
Valid time, SPISOMI data valid after
SPICLK high (clock polarity = 1)
ns
(1) The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR +1)
(3) tc(LCO) = LSPCLK cycle time
(4) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MAX, slave mode receive 12.5-MHz MAX.
(5) The active edge of the SPICLK signal referenced is controlled by the clock polarity bit (SPICCR.6).
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1
SPICLK
(clock polarity = 0)
2
4
3
SPICLK
(clock polarity = 1)
5
SPISIMO
SPISOMI
Master Out Data Is Valid
8
9
Master In Data
Must Be Valid
(A)
SPISTE
A. In the master mode, SPISTE goes active 0.5tc(SPC) (minimum) before valid SPI clock edge. On the trailing end of the
word, the SPISTE will go inactive 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.
Figure 6-18. SPI Master Mode External Timing (Clock Phase = 0)
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Table 6-33. SPI Master Mode External Timing (Clock Phase = 1)(1)(2)(3)(4)(5)
NO.
SPI WHEN (SPIBRR + 1) IS EVEN
OR SPIBRR = 0 OR 2
SPI WHEN (SPIBRR + 1) IS ODD
AND SPIBRR > 3
UNIT
MIN
4tc(LCO)
MAX
MIN
MAX
1
2
tc(SPC)M
Cycle time, SPICLK
128tc(LCO)
0.5tc(SPC)M
5tc(LCO)
127tc(LCO)
ns
ns
tw(SPCH)M
Pulse duration, SPICLK high (clock
polarity = 0)
0.5tc(SPC)M -10
0.5tc(SPC)M - 0.5tc (LCO)-10
0.5tc(SPC)M - 0.5tc (LCO)-10
0.5tc(SPC)M + 0.5tc(LCO) - 10
0.5tc(SPC)M + 0.5tc(LCO) -10
0.5tc(SPC)M - 10
0.5tc(SPC)M - 0.5tc(LCO)
0.5tc(SPC)M - 0.5tc(LCO
0.5tc(SPC)M + 0.5tc(LCO)
0.5tc(SPC)M + 0.5tc(LCO)
tw(SPCL))M
Pulse duration, SPICLK low (clock
polarity = 1)
0.5tc(SPC)M -10
0.5tc(SPC)M -10
0.5tc(SPC)M -10
0.5tc(SPC)M -10
0.5tc(SPC)M
0.5tc(SPC)M
0.5tc(SPC)M
ns
ns
ns
ns
3
6
tw(SPCL)M
Pulse duration, SPICLK low (clock
polarity = 0)
tw(SPCH)M
Pulse duration, SPICLK high (clock
polarity = 1)
tsu(SIMO-SPCH)M
Setup time, SPISIMO data valid
before SPICLK high (clock polarity
= 0)
tsu(SIMO-SPCL)M
Setup time, SPISIMO data valid
before SPICLK low (clock polarity =
1)
0.5tc(SPC)M -10
0.5tc(SPC)M - 10
ns
7
tv(SPCH-SIMO)M
tv(SPCL-SIMO)M
tsu(SOMI-SPCH)M
tsu(SOMI-SPCL)M
tv(SPCH-SOMI)M
tv(SPCL-SOMI)M
Valid time, SPISIMO data valid after
SPICLK high (clock polarity = 0)
0.5tc(SPC)M -10
0.5tc(SPC)M -10
35
0.5tc(SPC)M - 10
0.5tc(SPC)M -10
35
ns
ns
ns
ns
ns
ns
Valid time, SPISIMO data valid after
SPICLK low (clock polarity = 1)
10
11
Setup time, SPISOMI before
SPICLK high (clock polarity = 0)
Setup time, SPISOMI before
SPICLK low (clock polarity = 1)
35
35
Valid time, SPISOMI data valid after
SPICLK high (clock polarity = 0)
0.25tc(SPC)M -10
0.25tc(SPC)M -10
0.5tc(SPC)M -10
0.5tc(SPC)M -10
Valid time, SPISOMI data valid after
SPICLK low (clock polarity = 1)
(1) The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25 MHz MAX, master mode receive 12.5 MHz MAX
Slave mode transmit 12.5 MHz MAX, slave mode receive 12.5 MHz MAX.
(4) tc(LCO) = LSPCLK cycle time
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
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1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
6
7
SPISIMO
SPISOMI
Master Out Data Is Valid
10
Data Valid
11
Master In Data Must
Be Valid
(A)
SPISTE
A. In the master mode, SPISTE goes active 0.5tc(SPC) (minimum) before valid SPI clock edge. On the trailing end of the
word, the SPISTE will go inactive 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.
Figure 6-19. SPI Master External Timing (Clock Phase = 1)
6.9.6 SPI Slave Mode Timing
Table 6-34 lists the slave mode external timing (clock phase = 0) and Table 6-35 (clock phase = 1).
Figure 6-20 and Figure 6-21 show the timing waveforms.
Table 6-34. SPI Slave Mode External Timing (Clock Phase = 0)(1)(2)(3)(4)(5)
NO.
MIN
MAX UNIT
12 tc(SPC)S
13 tw(SPCH)S
tw(SPCL)S
Cycle time, SPICLKCycle time, SPICLK
4tc(LCO)
ns
Pulse duration, SPICLK high (clock polarity = 0)
0.5tc(SPC)S - 10 0.5tc(SPC)S
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Pulse duration, SPICLK low (clock polarity = 1)
0.5tc(SPC)S - 10 0.5tc(SPC)S
14 tw(SPCL)S
tw(SPCH)S
Pulse duration, SPICLK low (clock polarity = 0)
0.5tc(SPC)S - 10 0.5tc(SPC)S
Pulse duration, SPICLK high (clock polarity = 1)
0.5tc(SPC)S - 10 0.5tc(SPC)S
15 td(SPCH-SOMI)S
td(SPCL-SOMI)S
16 tv(SPCL-SOMI)S
tv(SPCH-SOMI)S
19 tsu(SIMO-SPCL)S
tsu(SIMO-SPCH)S
20 tv(SPCL-SIMO)S
tv(SPCH-SIMO)S
Delay time, SPICLK high to SPISOMI valid (clock polarity = 0)
Delay time, SPICLK low to SPISOMI valid (clock polarity = 1)
Valid time, SPISOMI data valid after SPICLK low (clock polarity = 0)
Valid time, SPISOMI data valid after SPICLK high (clock polarity = 1)
Setup time, SPISIMO before SPICLK low (clock polarity = 0)
Setup time, SPISIMO before SPICLK high (clock polarity = 1)
Valid time, SPISIMO data valid after SPICLK low (clock polarity = 0)
Valid time, SPISIMO data valid after SPICLK high (clock polarity = 1)
35
35
0.75tc(SPC)S
0.75tc(SPC)S
35
35
0.5tc(SPC)S
0.5tc(SPC)S
(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
(4) tc(LCO) = LSPCLK cycle time
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
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12
SPICLK
(clock polarity = 0)
13
15
14
SPICLK
(clock polarity = 1)
16
SPISOMI
SPISIMO
SPISOMI Data Is Valid
19
20
SPISIMO Data
Must Be Valid
(A)
SPISTE
A. In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) (minimum) before the valid SPI clock
edge and remain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.
Figure 6-20. SPI Slave Mode External Timing (Clock Phase = 0)
Table 6-35. SPI Slave Mode External Timing (Clock Phase = 1)(1)(2)(3)(4)
NO.
12
MIN
8tc(LCO)
MAX UNIT
tc(SPC)S
Cycle time, SPICLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
13
tw(SPCH)S
Pulse duration, SPICLK high (clock polarity = 0)
Pulse duration, SPICLK low (clock polarity = 1)
Pulse duration, SPICLK low (clock polarity = 0)
Pulse duration, SPICLK high (clock polarity = 1)
Setup time, SPISOMI before SPICLK high (clock polarity = 0)
Setup time, SPISOMI before SPICLK low (clock polarity = 1
Valid time, SPISOMI data valid after SPICLK low (clock polarity = 0)
0.5tc(SPC)S - 10
0.5tc(SPC)S - 10
0.5tc(SPC)S - 10
0.5tc(SPC)S - 10
0.125tc(SPC)S
0.125tc(SPC)S
0.75tc(SPC)S
0.5tc(SPC)S
0.5tc(SPC)S
0.5tc(SPC)S
0.5tc(SPC)S
tw(SPCL)S
14
17
18
tw(SPCL)S
tw(SPCH)S
tsu(SOMI-SPCH)S
tsu(SOMI-SPCL)S
tv(SPCH-SOMI)S
tv(SPCL-SOMI)S
Valid time, SPISOMI data valid after SPICLK high (clock polarity =
1)
0.75tc(SPC)S
21
22
tsu(SIMO-SPCH)S
tsu(SIMO-SPCL)S
tv(SPCH-SIMO)S
Setup time, SPISIMO before SPICLK high (clock polarity = 0)
Setup time, SPISIMO before SPICLK low (clock polarity = 1)
35
35
ns
ns
ns
Valid time, SPISIMO data valid after SPICLK high (clock polarity =
0)
0.5tc(SPC)S
tv(SPCL-SIMO)S
Valid time, SPISIMO data valid after SPICLK low (clock polarity = 1)
0.5tc(SPC)S
ns
(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
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12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
17
18
SPISOMI
SPISIMO
SPISOMI Data Is Valid
21
Data Valid
22
SPISIMO Data
Must Be Valid
(A)
SPISTE
A. In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) before the valid SPI clock edge and
remain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.
Figure 6-21. SPI Slave Mode External Timing (Clock Phase = 1)
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6.9.7 On-Chip Analog-to-Digital Converter
Table 6-36. ADC Electrical Characteristics (over recommended operating conditions)(1)(2)
PARAMETER
DC SPECIFICATIONS
Resolution
MIN
TYP
MAX
UNIT
12
1
Bits
kHz
MHz
ADC clock
12.5
ACCURACY
INL (Integral nonlinearity)
DNL (Differential nonlinearity)(3)
1-12.5 MHz ADC clock (6.25 MSPS)
1-12.5 MHz ADC clock (6.25 MSPS)
±1.5
±1
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
(4)
Offset error
-60
+60
Offset error with hardware trimming
Overall gain error with internal reference
Overall gain error with external reference
Channel-to-channel offset variation
Channel-to-channel gain variation
ANALOG INPUT
±4
(5)
-60
-60
+60
+60
±4
±4
(6)
Analog input voltage (ADCINx to ADCLO)
ADCLO
0
3
5
V
-5
0
mV
pF
µA
Input capacitance
10
Input leakage current
±5
(5)
INTERNAL VOLTAGE REFERENCE
VADCREFP - ADCREFP output voltage at the pin based on
internal reference
1.275
0.525
V
V
VADCREFM - ADCREFM output voltage at the pin based on
internal reference
Voltage difference, ADCREFP - ADCREFM
Temperature coefficient
0.75
50
V
PPM/°C
EXTERNAL VOLTAGE REFERENCE(5)(7)
ADCREFSEL[15:14] = 11b
ADCREFSEL[15:14] = 10b
ADCREFSEL[15:14] = 01b
1.024
1.500
2.048
V
V
V
VADCREFIN - External reference voltage input on ADCREFIN
pin 0.2% or better accurate reference recommended
AC SPECIFICATIONS
SINAD (100 kHz) Signal-to-noise ratio + distortion
SNR (100 kHz) Signal-to-noise ratio
THD (100 kHz) Total harmonic distortion
ENOB (100 kHz) Effective number of bits
SFDR (100 kHz) Spurious free dynamic range
67.5
68
dB
dB
-79
10.9
83
dB
Bits
dB
(1) Tested at 12.5 MHz ADCCLK.
(2) All voltages listed in this table are with respect to VSSA2
.
(3) Texas Instruments specifies that the ADC will have no missing codes.
(4) 1 LSB has the weighted value of 3.0/4096 = 0.732 mV.
(5) A single internal/external band gap reference sources both ADCREFP and ADCREFM signals, and hence, these voltages track
together. The ADC converter uses the difference between these two as its reference. The total gain error listed for the internal reference
is inclusive of the movement of the internal bandgap over temperature. Gain error over temperature for the external reference option will
depend on the temperature profile of the source used.
(6) Voltages above VDDA + 0.3 V or below VSS - 0.3 V applied to an analog input pin may temporarily affect the conversion of another pin.
To avoid this, the analog inputs should be kept within these limits.
(7) Texas Instruments recommends using high precision external reference Texas Instruments part REF3020/3120 or equivalent for
2.048-V reference.
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6.9.7.1 ADC Power-Up Control Bit Timing
ADC Power Up Delay
ADC Ready for Conversions
PWDNBG
PWDNREF
PWDNADC
t
d(BGR)
t
d(PWD)
Request for
ADC
Conversion
Figure 6-22. ADC Power-Up Control Bit Timing
Table 6-37. ADC Power-Up Delays
PARAMETER(1)
MIN
TYP
MAX
UNIT
td(BGR)
td(PWD)
Delay time for band gap reference to be stable. Bits 7 and 6 of the ADCTRL3
register (ADCBGRFDN1/0) must be set to 1 before the PWDNADC bit is enabled.
5
ms
Delay time for power-down control to be stable. Bit delay time for band-gap
reference to be stable. Bits 7 and 6 of the ADCTRL3 register (ADCBGRFDN1/0)
must be set to 1 before the PWDNADC bit is enabled. Bit 5 of the ADCTRL3
register (PWDNADC)must be set to 1 before any ADC conversions are initiated.
20
50
µs
1
ms
(1) Timings maintain compatibility to the 281x ADC module. The 280x ADC also supports driving all 3 bits at the same time and waiting
td(BGR) ms before first conversion.
Table 6-38. Current Consumption for Different ADC Configurations (at 12.5-MHz ADCCLK)(1)(2)
ADC OPERATING MODE
CONDITIONS
VDDA18
VDDA3.3
UNIT
Mode A (Operational Mode):
30
2
mA
•
•
BG and REF enabled
PWD disabled
Mode B:
Mode C:
Mode D:
9
5
5
0.5
20
15
ma
µA
µA
•
•
•
ADC clock enabled
BG and REF enabled
PWD enabled
•
•
•
ADC clock enabled
BG and REF disabled
PWD enabled
•
•
•
ADC clock disabled
BG and REF disabled
PWD enabled
(1) Test Conditions:
SYSCLKOUT = 100 MHz
ADC module clock = 12.5 MHz
ADC performing a continuous conversion of all 16 channels in Mode A
(2) VDDA18 includes current into VDD1A18 and VDD2A18. VDDA3.3 includes current into VDDA2 and VDDAIO
.
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R
1 kΩ
on
Switch
R
s
ADCIN0
C
10 pF
C
h
1.64 pF
p
Source
Signal
ac
28x DSP
Typical Values of the Input Circuit Components:
Switch Resistance (R ):
1 kΩ
1.64 pF
on
Sampling Capacitor (C ):
h
Parasitic Capacitance (C ): 10 pF
p
Source Resistance (R ):
50 Ω
s
Figure 6-23. ADC Analog Input Impedance Model
6.9.7.2 Definitions
Reference Voltage
The on-chip ADC has a built-in reference, which provides the reference voltages for the ADC.
Analog Inputs
The on-chip ADC consists of 16 analog inputs, which are sampled either one at a time or two channels at
a time. These inputs are software-selectable.
Converter
The on-chip ADC uses a 12-bit four-stage pipeline architecture, which achieves a high sample rate with
low power consumption.
Conversion Modes
The conversion can be performed in two different conversion modes:
•
•
Sequential sampling mode (SMODE = 0)
Simultaneous sampling mode (SMODE = 1)
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6.9.7.3 Sequential Sampling Mode (Single-Channel) (SMODE = 0)
In sequential sampling mode, the ADC can continuously convert input signals on any of the channels (Ax
to Bx). The ADC can start conversions on event triggers from the ePWM, software trigger, or from an
external ADCSOC signal. If the SMODE bit is 0, the ADC will do conversions on the selected channel on
every Sample/Hold pulse. The conversion time and latency of the Result register update are explained
below. The ADC interrupt flags are set a few SYSCLKOUT cycles after the Result register update. The
selected channels will be sampled at every falling edge of the Sample/Hold pulse. The Sample/Hold pulse
width can be programmed to be 1 ADC clock wide (minimum) or 16 ADC clocks wide (maximum).
Sample n+2
Sample n+1
Analog Input on
Sample n
Channel Ax or Bx
ADC Clock
Sample and Hold
SH Pulse
SMODE Bit
t
d(SH)
t
dschx_n+1
t
dschx_n
ADC Event Trigger from
ePWM or Other Sources
t
SH
Figure 6-24. Sequential Sampling Mode (Single-Channel) Timing
Table 6-39. Sequential Sampling Mode Timing
SAMPLE n
SAMPLE n + 1
AT 12.5 MHz
REMARKS
ADC CLOCK,
tc(ADCCLK) = 80 nS
td(SH)
Delay time from event trigger to
2.5tc(ADCCLK)
sampling
tSH
Sample/Hold width/Acquisition
Width
(1 + Acqps) *
tc(ADCCLK)
80 ns with Acqps = 0
320 ns
Acqps value = 0-15
ADCTRL1[8:11]
td(schx_n)
td(schx_n+1)
Delay time for first result to appear
in Result register
4tc(ADCCLK)
Delay time for successive results to
appear in Result register
(2 + Acqps) *
tc(ADCCLK)
160 ns
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6.9.7.4 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)
In simultaneous mode, the ADC can continuously convert input signals on any one pair of channels
(A0/B0 to A7/B7). The ADC can start conversions on event triggers from the ePWM, software trigger, or
from an external ADCSOC signal. If the SMODE bit is 1, the ADC will do conversions on two selected
channels on every Sample/Hold pulse. The conversion time and latency of the result register update are
explained below. The ADC interrupt flags are set a few SYSCLKOUT cycles after the Result register
update. The selected channels will be sampled simultaneously at the falling edge of the Sample/Hold
pulse. The Sample/Hold pulse width can be programmed to be 1 ADC clock wide (minimum) or 16 ADC
clocks wide (maximum).
NOTE
In simultaneous mode, the ADCIN channel pair select has to be A0/B0, A1/B1, ..., A7/B7,
and not in other combinations (such as A1/B3, etc.).
Sample n
Sample n+2
Sample n+1
Analog Input on
Channel Ax
Analog Input on
Channel Bx
ADC Clock
Sample and Hold
SH Pulse
SMODE Bit
t
d(SH)
t
dschA0_n+1
t
SH
ADC Event Trigger from
ePWM or Other Sources
t
t
dschA0_n
dschB0_n+1
t
dschB0_n
Figure 6-25. Simultaneous Sampling Mode Timing
Table 6-40. Simultaneous Sampling Mode Timing
SAMPLE n
SAMPLE n + 1
AT 12.5 MHz
ADC CLOCK,
REMARKS
tc(ADCCLK) = 80 ns
td(SH)
Delay time from event trigger to
2.5 tc(ADCCLK)
sampling
tSH
Sample/Hold width/Acquisition
Width
(1 + Acqps) x
tc(ADCCLK)
80 ns with Acqps = 0 Acqps value = 0-15
ADCTRL1[8:11]
td(schA0_n)
td(schB0_n)
Delay time for first result to
appear in Result register
4 tc(ADCCLK)
320 ns
Delay time for first result to
appear in Result register
5 tc(ADCCLK)
400 ns
td(schA0_n+1) Delay time for successive results
to appear in Result register
(3 + Acqps) x tc(ADCCLK) 240 ns
(3 + Acqps) x tc(ADCCLK) 240 ns
td(schB0_n+1) Delay time for successive results
to appear in Result register
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6.10 Detailed Descriptions
Integral Nonlinearity
Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full
scale. The point used as zero occurs one-half LSB before the first code transition. The full-scale point is
defined as level one-half LSB beyond the last code transition. The deviation is measured from the center
of each particular code to the true straight line between these two points.
Differential Nonlinearity
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal
value. A differential nonlinearity error of less than ±1 LSB ensures no missing codes.
Zero Offset
The major carry transition should occur when the analog input is at zero volts. Zero error is defined as the
deviation of the actual transition from that point.
Gain Error
The first code transition should occur at an analog value one-half LSB above negative full scale. The last
transition should occur at an analog value one and one-half LSB below the nominal full scale. Gain error is
the deviation of the actual difference between first and last code transitions and the ideal difference
between first and last code transitions.
Signal-to-Noise Ratio + Distortion (SINAD)
SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral
components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is
expressed in decibels.
Effective Number of Bits (ENOB)
For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following
(
)
SINAD * 1.76
N +
formula,
6.02
it is possible to get a measure of performance expressed as N, the effective
number of bits. Thus, effective number of bits for a device for sine wave inputs at a given input frequency
can be calculated directly from its measured SINAD.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first nine harmonic components to the rms value of the measured
input signal and is expressed as a percentage or in decibels.
Spurious Free Dynamic Range (SFDR)
SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal.
112
Electrical Specifications
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SM320F2801-EP
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SGLS316A–MARCH 2006–REVISED FEBRUARY 2007
6.11 Flash Timing
Table 6-41. Flash Endurance
MIN
TYP
MAX
UNIT
cycles
write
Nf
Flash endurance for the array (write/erase cycles)
-55°C to 125°C (ambient)
-55°C to 125°C (ambient)
100
1000
NOTP OTP endurance for the array (write cycles)
1
Table 6-42. Flash Parameters at 100-MHz SYSCLKOUT
PARAMETER(1)
16-Bit Word
16K Sector
8K Sector
TEST CONDITIONS
MIN
TYP
50
MAX
UNIT
µs
Program
Time
500
250
125
10
ms
ms
ms
S
4K Sector
Erase Time
16K Sector
8K Sector
10
S
4K Sector
10
S
IDD3VFLP
VDD3VFL current consumption during the
Erase/Program cycle
Erase
75
mA
mA
mA
Program
35
IDDP
VDD current consumption during Erase/Program
cycle
140
IDDIOP
VDDIO current consumption during Erase/Program
cycle
20
mA
(1) Typical parameters as seen at room temperature using flash API version 3.00 including function call overhead.
Table 6-43. Flash/OTP Access Timing
PARAMETER(1)
Paged flash access time
MIN
36
TYP
MAX
UNIT
ns
ta(fp)
ta(fr)
Random flash access time
OTP access time
36
ns
ta(OTP)
60
ns
(1) For 100 MHz, PAGE WS = 3 and RANDOM WS = 3; for 75 MHz, PAGE WS = 2, and RANDOM WS = 2.
Equations to compute the page wait state and random wait state in Table 6-44 are as follows:
ta(fp)
Flash Page Wait-State
+
ǒ Ǔ* 1
ƪ ƫ(round up to the next highest integer) or 0, whichever is larger
tc(SCO)
ta(fr)
(round up to the next highest integer) or 1, whichever is larger
Flash Random Wait-State
+
ǒ Ǔ* 1
ƪ ƫ
tc(SCO)
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Electrical Specifications
113
SM320F2808-EP, SM320F2806-EP
SM320F2801-EP
Digital Signal Processors
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SGLS316A–MARCH 2006–REVISED FEBRUARY 2007
Table 6-44. Minimum Required Wait-States at Different Frequencies
SYSCLKOUT (MHz)
SYSCLKOUT (ns)
PAGE WAIT-STATE
RANDOM WAIT STATE(1)
100
75
50
30
25
15
4
10
13.33
20
3
2
1
1
0
0
0
3
2
1
1
1
1
1
33.33
40
66.67
250
(1) Random wait state must be greater than or equal to 1.
114
Electrical Specifications
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SGLS316A–MARCH 2006–REVISED FEBRUARY 2007
7
Mechanical Data
Table 7-1 and Table 7-2 show the thermal data.
The mechanical package diagram(s) that follow the tables reflect the most current released mechanical
data available for the designated device(s).
Table 7-1. F280x Thermal Model 100-pin GGM Results
Air Flow
PARAMETER
0 lfm
30.58
0.4184
12.08
16.46
150 lfm
29.31
0.32
250 lfm
28.09
500 lfm
26.62
θJA[°C/W] High k PCB
ΨJT[°C/W]
θJC
0.3725
0.4887
θJB
Table 7-2. F280x Thermal Model 100-pin PZ Results
Air Flow
PARAMETER
0 lfm
48.16
0.3425
12.89
29.58
150 lfm
40.06
0.85
250 lfm
37.96
500 lfm
35.17
θJA[°C/W] High k PCB
ΨJT[°C/W]
θJC
1.0575
1.410
θJB
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Mechanical Data
115
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
SM320F2801PZMEP
SM320F2808PZMEP
V62/06619-01XE
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
LQFP
PZ
100
100
100
100
90 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
LQFP
LQFP
LQFP
PZ
PZ
PZ
90 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
V62/06619-03XE
90 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996
PZ (S-PQFP-G100)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
75
M
0,08
51
50
76
26
100
0,13 NOM
1
25
12,00 TYP
Gage Plane
14,20
SQ
13,80
0,25
16,20
SQ
0,05 MIN
0°–7°
15,80
1,45
1,35
0,75
0,45
Seating Plane
0,08
1,60 MAX
4040149/B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
1
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