SM320MCM41DHFHL40 [TI]
32-BIT, 40MHz, OTHER DSP, CQFP352, CERAMIC, QFP-352;
| 型号： | SM320MCM41DHFHL40 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 32-BIT, 40MHz, OTHER DSP, CQFP352, CERAMIC, QFP-352 时钟 外围集成电路 |
| 文件： | 总12页 (文件大小：184K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SMJ320MCM41D
SINGLE-SMJ320C40 MULTICHIP MODULE
SGKS002 – OCTOBER 1997
352-LEAD HFH QUAD FLATPACK PACKAGE
(TOP VIEW)
Performance
– 40 MFLOPS (Million Floating-Point
Operations per Second) With
256-Megabyte/s Burst I/O Rate for
40-MHz Modules
– 128K Word × 32 Bit Zero-Wait-State
SRAM Connected to the ’C40 Local Bus
352
265
1
264
Compliant to MIL-PRF-38535 QML
’C40 Performance With Local Memory
Requiring Only 4.35 Square Inches of
Board Space
Enhanced Performance Offered By
Multichip-Module Solution
– 46% Reduction In Number of
Interconnects
– 23% Reduction (Minimum) in Board Area
– Estimated 20% Reduction in Power
Dissipation Due to Reduced Parasitic
Capacitance and Interconnect Lengths
88
177
Two Memory Ports for High Data
Bandwidth
89
176
– Full 2-Gigaword External Bus
– Internal Bus Mapped to 128K Word ×
32 Bit Zero-Wait-State SRAM
Six External Communication Ports for
Direct Processor-to-Processor
Communication
†
Supports IEEE-1149.1 -Compliant (JTAG)
With Boundary-Scan Testing
Operating Free-Air Temperature Ranges:
– Military: –55°C to 125°C
– Commercial: 0°C to 70°C
Packaging:
352-Lead Ceramic Quad Flatpack
(HFH Suffix)
description
‡
The ’MCM41 single-SMJ320C40 multichip module (MCM) contains one SMJ320C40 device with 128K word
× 32 bit zero-wait-state SRAM mapped to the local memory bus. The MCM is footprint-compatible with the
monolithic ’320C40HFH package to allow easy upgradeability and design-in. The local memory bus is not
routed to the device footprint. The ’MCM41 is available in both a commercial temperature range (0°C to 70°C)
and a military temperature range (–55°C to 125°C) option.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
‡
IEEE Standard 1149.1–1990, IEEE Standard Test-Access Port and Boundary-Scan Architecture
The ’MCM41 single-SMJ320C40 multichip module will be referred to as ’MCM41 throughout this data sheet.
Copyright 1997, Texas Instruments Incorporated
ADVANCE INFORMATION concerns new products in the sampling or
preproduction phase of development. Characteristic data and other
specifications are subject to change without notice.
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320MCM41D
SINGLE-SMJ320C40 MULTICHIP MODULE
SGKS002 – OCTOBER 1997
Table 1. MCM Processing Matrix
TEST
TEMPERATURE
RANGE
PROCESS
LEVEL
100%
PROCESSED
SPEED
TEST
QUALIFICATION
TESTING
TEMPERATURE RANGE
DIE
L version
M version
M version
0°C to 70°C
Probed
Probed
No
No
No
Yes
Yes
25°C to 70°C
Package
SM
–55°C to 125°C
–55°C to 125°C
–55°C to 125°C
–55°C to 125°C
Package
†
‡
SMJ
KGD
Yes
MIL-H-38534
†
‡
SMJ-level product is fully MIL-PRF-38535 QML compliant.
KGD stands for the known-good-die strategy as defined in the reference documentation and data sheet scope section.
Multichip Module Naming Nomenclature and Ordering Information
Example: SMJ
320
MCM
4
1
D
HFH
M
40
Process Level Prefix
(Refer to Table 1)
320 DSP Family Designator
Multichip Module
Processor Family
Number of CPUs per Module
Module Revision
Package
HFH = 352-Lead Ceramic Quad Flatpack
Temperature Range
L (Commercial)
M (Military)
=
=
0°C to 70°C
–55°C to 125°C
Speed Designator
40 = 40 MHz
For descriptions of the HFH package pin assignments, refer to the SMJ320C40 signals descriptions table in the
SMJ320C40 data sheet (literature number SGUS017).
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320MCM41D
SINGLE-SMJ320C40 MULTICHIP MODULE
SGKS002 – OCTOBER 1997
HFH package pin assignments — numerical listing
PIN
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
SIGNAL
D31
PIN
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
SIGNAL
D0
PIN
81
SIGNAL
CSTRB5
CACK5
CREQ5
CRDY4
CSTRB4
CACK4
CREQ4
PIN
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
SIGNAL
PIN
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
SIGNAL
C1D7
C1D6
C1D5
C1D4
C1D3
C1D2
C1D1
C1D0
‡
DV
DD
†
D30
CE1
82
IV
SS
IV
SS
†
D29
RDY1
83
§
§
†
†
D28
DV
DV
CV
CV
84
C2D7
C2D6
C2D5
C2D4
C2D3
C2D2
C2D1
C2D0
SS
SS
SS
SS
D27
85
D26
86
‡
GDDV
87
DD
D25
†
§
§
‡
LOCK
88
CV
DV
DV
DV
SS
SS
SS
¶
‡
D24
D23
D22
D21
D20
D19
D18
D17
D16
V
DDL
89
DV
DD
#
V
SSL
CE0
90
C0D7
C0D6
C0D5
C0D4
C0D3
C0D2
C0D1
C0D0
91
DD
†
RDY0
DE
92
C5D7
C5D6
C5D5
C5D4
C5D3
C5D2
C5D1
C5D0
CV
SS
SS
SS
§
§
‡
93
DV
DV
DV
TCK
94
TDO
TDI
95
DD
96
CRDY3
CSTRB3
CACK3
CREQ3
TMS
TRST
EMU0
EMU1
97
†
†
†
CV
98
CV
SS
SS
SS
DD
‡
CV
IV
99
DV
†
‡
¶
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
DV
V
DDL
ROMEN
IIOF0
SS
DD
‡
‡
§
#
GDDV
GDDV
DV
DV
DV
C4D7
V
SSL
DD
SS
SS
§
‡
§
§
C4D6
C4D5
C4D4
C4D3
C4D2
C4D1
C4D0
CRDY2
CSTRB2
CACK2
CREQ2
DV
DV
DD
§
SS
SS
DV
DV
SS
DD
§
PAGE1
R/W1
IIOF1
IIOF2
IIOF3
NMI
SS
D15
D14
D13
D12
D11
D10
D9
‡
STRB1
STAT0
STAT1
DV
DD
CRDY1
CSTRB1
CACK1
CREQ1
CRDY0
CSTRB0
CACK0
CREQ0
||
||
||
||
||
||
||
NC
NC
NC
NC
NC
NC
NC
†
†
IV
SS
CV
SS
SS
SS
§
§
‡
STAT2
STAT3
DV
DV
DV
D8
PAGE0
R/W0
DD
D7
C3D7
C3D6
C3D5
C3D4
C3D3
C3D2
C3D1
C3D0
D6
STRB0
AE
†
†
§
§
‡
D5
CV
CV
DV
DV
DV
CV
SS
SS
SS
SS
DD
‡
†
GDDV
RESETLOC1
DD
SS
‡
||
||
||
||
D4
D3
D2
D1
DV
NC
DD
RESETLOC0
RESET
NC
NC
NC
†
IV
SS
‡
CRDY5
DV
DD
†
‡
§
¶
#
||
CV
and IV
pins are connected internally.
SS
SS
DD
SS
DV , LADV , LDDV , GDDV , and GADV
DV
pins are connected internally.
DD
DD
DD
DD
pins are connected internally.
pins are connected internally.
pins are connected internally.
V
DDL
V
SSL
Pins marked NC should be left electrically unconnected.
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320MCM41D
SINGLE-SMJ320C40 MULTICHIP MODULE
SGKS002 – OCTOBER 1997
HFH package pin assignments — numerical listing (continued)
PIN
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
SIGNAL
TCLK0
TCLK1
H3
PIN
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
SIGNAL
PIN
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
SIGNAL
PIN
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
SIGNAL
A20
†
§
§
‡
CV
DV
DV
LDDV
SS
SS
SS
DD
†
CV
DV
DV
A19
SS
§
A18
SS
SS
||
||
||
||
||
||
||
||
||
||
§
H1
NC
A17
||
†
‡
‡
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
IV
SS
GADV
GADV
DD
†
IV
SS
NC||
NC||
NC||
NC||
NC||
NC||
NC||
NC||
NC||
NC||
NC||
NC||
DD
†
||
||
||
||
||
NC
NC
NC
NC
NC
CV
CV
DV
DV
SS
†
§
§
SS
SS
SS
A16
A15
A14
A13
A12
A11
A10
A9
IACK
¶
V
DDL
#
V
SSL
X1
NC||
NC||
‡
X2/CLKIN
LADV
DD
†
†
‡
CV
CV
DV
DV
DV
NC||
SS
SS
‡
NC||
NC||
NC||
LDDV
DD
NC||
A8
DD
§
NC||
NC||
NC||
NC||
A7
SS
§
§
§
†
DV
A6
SS
SS
SS
SS
||
||
||
||
NC
DV
CV
A5
NC
NC
NC
A4
¶
‡
NC||
NC||
NC||
NC||
V
DDL
GADV
DD
#
†
V
A3
A2
A1
A0
SSL
‡
LADV
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
CV
CV
DV
DV
DD
SS
||
||
||
||
||
||
||
||
||
||
||
†
§
§
SS
SS
SS
‡
LDDV
DD
†
§
§
NC||
CV
SS
SS
SS
NC||
NC||
NC||
NC||
NC||
NC||
NC||
NC||
NC||
NC||
A30
A29
A28
DV
DV
SUBS
‡
GADV
DD
A27
A26
A25
A24
A23
A22
A21
‡
‡
LADV
LADV
DD
DD
†
‡
CV
LDDV
DD
SS
†
‡
§
¶
#
||
CV
and IV
pins are connected internally.
SS
SS
DD
SS
DV , LADV , LDDV , GDDV , and GADV
DV
pins are connected internally.
DD
DD
DD
DD
pins are connected internally.
pins are connected internally.
pins are connected internally.
V
DDL
V
SSL
Pins marked NC should be left electrically unconnected.
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320MCM41D
SINGLE-SMJ320C40 MULTICHIP MODULE
SGKS002 – OCTOBER 1997
functional block diagram
The following pins have 10-kΩ pullup resistors added within the module:
CREQx, CACKx, CSTRBx, CRDYx, where x = 0–5
LCE1 (internal connections)
A total of eight decoupling capacitors have been connected within the module.
Between clean power and ground (V
One 0.1-µF capacitor
and CV ), the following capacitors have been connected:
SS
DDL
One 0.01-µF capacitor
Between dirty power and ground (GDDV
have been connected:
GADV
LDDV
LADV and DV ), the following capacitors
DD, SS
DD,
DD,
DD,
Three 0.1-µF capacitors
Three 0.01-µF capacitors
TDI
TCK
TMS
IEEE 1149.1
TRST
EMU0
EMU1
TDO
TDI
TDO
CLKIN
RESET
’C40
ADDR
SRAM
V
DDL
DATA
CV , IV , V
, SUBS
†
128K × 8 × 4
SS SS SSL
CNTL
yyV
DD
DV
SS
D31–D0
A30–A0
AE
DE
STAT3 – STAT0
LOCK
Global Bus
STRB0– STRB1
R/W0–R/W1
PAGE0–PAGE1
RDY0–RDY1
CE0–CE1
Communication Ports
(x = 0– 5)
Control
†
yyV
represents GDDV , GADV , LDDV , and LADV .
DD DD DD DD
DD
operational overview
Treatment of the detailed operation of the ’C40 device is beyond the scope of this document. Refer to the
TMS320C4x User’s Guide (literature number SPRU063) for a detailed description of this DSP.
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320MCM41D
SINGLE-SMJ320C40 MULTICHIP MODULE
SGKS002 – OCTOBER 1997
000000000h
4K ROM (reserved)
Reserved
Structure
000000FFFh
000001000h
Depends On
ROMEN Bit
Reserved
1M
1M
0000FFFFFh
000100000h
Peripherals (internal)
Reserved
Peripherals (internal)
Reserved
0001000FFh
000100100h
0001FFFFFh
000200000h
Reserved
Reserved
0002FF7FFh
0002FF800h
2G
1M
1K RAM BLK 0 (internal)
1K RAM BLK 1 (internal)
1K RAM BLK 0 (internal)
1K RAM BLK 1 (internal)
0002FFBFFh
0002FFC00h
0002FFFFFh
000300000h
Reserved
Local Bus Module RAM
Reserved
Reserved
Local Bus Module RAM
Reserved
5M
0007FFFFFh
000800000h
Structure
Identical
128K
00081FFFFh
000820000h
07FFFFFFFh
080000000h
Global Bus (external)
Global Bus (external)
2G
0FFFFFFFFh
(a) INTERNAL ROM DISABLED
(ROMEN = 0)
(b) INTERNAL ROM ENABLED
(ROMEN = 1)
Figure 1. Memory Map for the ’C40 Within the Multichip Module
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320MCM41D
SINGLE-SMJ320C40 MULTICHIP MODULE
SGKS002 – OCTOBER 1997
reference documentation and data sheet scope
The SMJ320MCM41D is qualified to MIL-PRF-38535. Electrical continuity of the module is ensured through use
of IEEE-1149.1-compatible boundary-scan testing and functional checkout of local SRAM space.
KGD refers to Texas Instruments (TI ) known-good-die strategy. TI KGDs are fully tested over the military
temperature range per MIL-PRF-38535 QML. Electrical testing ensures compliance of the ’C40 KGD
components to the SMJ320C40 data sheet (literature number SGUS017) over the operating temperature
range. The SMJ320MCM41D module timings are virtually unchanged from the SMJ320C40 data sheet timings.
A SMJ320C40 data sheet is provided for customer reference only and does not imply MCM compliance to
published timings.
For a complete description of the ’C40 operation and application information, refer to the TMS320C4x User’s
Guide (literature number SPRU063).
capacitance
Capacitanceofasingle’C40dieisspecifiedbydesigntobe15pFmaximumforbothinputsandoutputs. Module
networks add up to 25 pF. Simulation of die or substrate capacitance is performed after any design change.
Power measurements taken for the ’C40 die are made with an additional 80-pF load capacitance. Refer to the
SMJ320C40 data sheet (literature number SGUS017) for the test load circuit.
operational timings and module testing
TIprocessingensuresthatoperationisverifiedtothepublisheddatasheetspecificationsonthe’C40indieform.
All voltage, timing, speed, and temperature specifications are met before any die is placed into a multichip
module. For this reason, it is unnecessary to verify all ’C40 voltage and timing parameters at the module level.
Characterization of the ’MCM41D substrate shows that the module performs as an equivalent system of
discretely packaged ’C40 devices. This performance is ensured through a full-frequency functional checkout
of the module that verifies selected worst-case timings. An additional propagation delay is introduced by the
substrate. This value is assured by design to be less than 1 ns, but it is not tested. Refer to the SMJ320C40
data sheet (literature number SGUS017) for a complete listing of timing diagrams and limits.
module test capability (future compatibility)
The ’C40 supports the IEEE-1149.1 testability standard, and all test-access port (TAP) pins are brought out to
the module footprint. This configuration allows users to test the module using third-party JTAG testability tools
or other boundary-scan control software. Proper software configuration allows users to debug or launch code
on the module via the ’C40 emulator and XDS pod. Both of these tools are used as a part of outgoing module
testing.
The ’MCM41 supports third-party JTAG diagnostic families of products for verification and debug of
boundary-scan circuits, boards, and systems. For further information on JTAG testability tools, please contact
your local TI sales representative or authorized TI distributor.
TI and XDS are trademarks of Texas Instruments Incorporated.
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320MCM41D
SINGLE-SMJ320C40 MULTICHIP MODULE
SGKS002 – OCTOBER 1997
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
CC
Voltage range on any pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Output voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
O
Operating free-air temperature range, T : L version (commercial) . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
M version (military) . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to125°C
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to V
.
SS
recommended operating conditions
MIN
4.75
2.6
MAX
UNIT
V
V
V
Supply voltage
5.25
V
CC
IH
CLKIN
V
V
V
+ 0.3
CC
CC
CC
High-level input voltage
CSTRBx, CRDYx, CREQx, CACKx
All others inputs
2.2
+ 0.3
+ 0.3
V
2
Low-level input voltage
High-level output current
Low-level output current
– 0.3
0.8
V
IL
I
– 300
2
µA
mA
°C
°C
OH
OL
I
L Version (Commercial)
M Version (Military)
0
70
T
A
Operating free-air temperature
– 55
125
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature
‡
PARAMETER
High-level output voltage
TEST CONDITIONS
MIN
TYP
3
MAX
UNIT
V
V
V
V
= MIN,
= MIN,
= MAX
I
I
= MAX
2.4
OH
CC
CC
CC
OH
Low-level output voltage
Supply current
V
V
= MAX
0.3
0.4
0.6
0.6
20
V
OL
OL
I
I
I
I
I
I
A
CC
Three-state current
V = V
to V
to V
to V
to V
to V
– 20
– 10
µA
µA
µA
µA
µA
Z
I
SS
SS
SS
SS
SS
CC
CC
CC
CC
CC
Input current
V = V
10
I
I
Input current, internal pullup (see Note 2)
Input current, CLKIN
V = V
– 400
– 50
30
IP
IC
IPD
I
V = V
50
I
Input current, internal pulldowns, TRST
V = V
– 20
400
I
‡
For conditions shown as MIN/MAX, use the appropriate value specified under recommended operating conditions.
NOTE 2: Pins with internal pullup devices: TDI, TCK, TMS
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320MCM41D
SINGLE-SMJ320C40 MULTICHIP MODULE
SGKS002 – OCTOBER 1997
module test circuit
Figure 2illustratesthebasiccircuitsforthe’MCM41D. RefertotheTMS320C4xUser’sGuide(literaturenumber
SPRU063) for more detailed information.
CLKIN = Clock Pulse per Data Sheet
RESET = Reset Pulse per Data Sheet
5 V
4.7 kΩ–10 kΩ
Suggested
’C40
TDO
TDI
TDO
TMS
TCK
TRST
EMU0
EMU1
TDI
SMJ320MCM41D
†
Test Header
All V
All V
to 5 V
CC
SS
to GND
†
The test header normally consists of the XDS510 for the ’C40 emulation or ASSET hardware for interconnect testing.
Figure 2. Sample Test Circuit
XDS510 is a trademark of Texas Instruments Incorporated.
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320MCM41D
SINGLE-SMJ320C40 MULTICHIP MODULE
SGKS002 – OCTOBER 1997
thermal analysis
Thermal conduction of components in the SMJ320MCM41D is dependent on the thermal resistance of the
material under each die as well as the die area thermally connected to the heat-dissipating medium. Since these
properties vary with layout and die size, ’C40 and SRAM components should be considered separately. The
following table lists primary parameters required for thermal analysis of the module. The junction temperature,
T , is not to be exceeded for the ’C40 or the SRAM die.
J
primary parameters required for thermal analysis of the SMJ320MCM41D module
PARAMETER
ALTERNATE
SYMBOL
MIN
TYP
MAX
UNIT
T
Junction temperature under operating condition
Single MCM power dissipation
T
150
5.2
°C
W
J
J
P
P
2.0
1.3
MCM
0JC
MCM
jc
Z
Z
T
Thermal impedance (junction-to-case) of package
Thermal impedance (junction-to-ambient air, 0 cfm) of package
Maximum solder temperature (10 s duration)
T
T
T
°C/W
°C/W
°C
28.0
0JA
ja
260
SOL
SOL
power estimation
The power requirements of the ’320MCM41 have been characterized over the operating temperature range.
See the application report Calculation of TMS320C40 Power Dissipation (literature number SPRA032) as
reference for power estimation of the ’C40 components.
Typical power dissipation has been measured with the ’C40s executing a 64-point Fast Fourier Transform (FFT)
algorithm. Input and output data arrays resided in module SRAM, and output data was written out to the
global-address space. The global databus was loaded with 80-pF test loads, and both local and global writes
were configured for zero-wait-state memory. Under typical conditions of 25°C, 5-V V , and 40-MHz CLKIN
CC
frequency, the power dissipation was measured to be 1.75 W.
Maximum power dissipation has been measured under worst-case conditions. The global databus was loaded
with 80-pF test loads, and simultaneous zero-wait-state writes have been performed to both local and global
buses. Under worst-case conditions of – 55°C, 5.25-V V , and 40-MHz CLKIN frequency, the power
CC
dissipation was determined to be 3 W. The algorithm executed during these tests consists of parallel writes of
alternating 0xAAs and 0x55s to both local SRAM and global-address spaces. This algorithm is not considered
to be a practical use of the ’C40’s resources; therefore, the associated power measurement should be
considered absolute maximum only.
10
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320MCM41D
SINGLE-SMJ320C40 MULTICHIP MODULE
SGKS002 – OCTOBER 1997
MECHANICAL DATA
HFH (S-CQFP-F352)
CERAMIC QUAD FLATPACK WITH NCTB
76,40
74,85
75,40
74,60
57,00
55,60
48,48
47,52
5,50
4,50
1,55
Dia
43,50
BSC
1,45
4 Places
265
264
352
1
Detail “C”
70,00
3,60
3,50
177
176
88
89
Detail “B”
2,60
2,50
2,60
Dia (2 Places)
“A”
2,50
0,50 MAX
0,25
0,18
352
4,55 MAX
4,00 MAX
0,20
0,10
1,05
0,75
0,35
0,05
0,50
DETAIL “C”
DETAIL “B”
DETAIL “A”
4040232-5/E 09/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MO-134 AE
11
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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