SM72295 [TI]
SM72295 Photovoltaic Full Bridge Driver;
| 型号： | SM72295 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SM72295 Photovoltaic Full Bridge Driver |
| 文件： | 总17页 (文件大小：843K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SM72295
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SNVS688E –OCTOBER 2010–REVISED APRIL 2013
SM72295 Photovoltaic Full Bridge Driver
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1
FEATURES
DESCRIPTION
The SM72295 is designed to drive 4 discrete N type
MOSFET’s in a full bridge configuration. The drivers
provide 3A of peak current for fast efficient switching
and integrated high speed bootstrap diodes. Current
sensing is provided by 2 transconductance amplifiers
with externally programmable gain and filtering to
remove ripple current to provide average current
information to the control circuit. The current sense
amplifiers have buffered outputs available to provide
a low impedance interface to an A/D converter if
needed. An externally programmable input over
voltage comparator is also included to shutdown all
outputs. Under voltage lockout with a PGOOD
indicator prevents the drivers from operating if VCC is
too low.
2
•
•
•
•
•
Renewable Energy Grade
Dual Half Bridge MOSFET Drivers
Integrated 100V Bootstrap Diodes
Independent High and Low Driver Logic Inputs
Bootstrap Supply Voltage Range up to 115V
DC
•
Two Current Sense Amplifiers with Externally
Programmable Gain and Buffered Outputs
•
•
Programmable Over Voltage Protection
Supply Rail Under-Voltage Lockouts with
Power Good Indicator
PACKAGE
•
SOIC-28
Typical Application Circuit
R16
10m
R15
10m
+
+
R10
R12
R11
Vout
PV
Vin
C1
R9
10k
R13 R14
-
C4
0.47 uF
-
C5
0.47 uF
C6
1
uF
5V
C3
1
uF
10V
R6
500
R7
500
C8
10 nF
R8
500
C10
10n
optional
optional
R5
500
R3
40k
C7
C2
R4
40k
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2013, Texas Instruments Incorporated
SM72295
SNVS688E –OCTOBER 2010–REVISED APRIL 2013
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Connection Diagram
1
2
3
28
27
26
SIA
HSA
HOA
HBA
SOA
IIN
4
5
6
7
8
25
24
23
22
21
BIN
VCCA
LOA
AGND
LIA
PGND
LOB
HIA
SM72295
HIB
VCCB
HBB
9
10
11
12
20
19
18
17
LIB
PGOOD
BOUT
IOUT
SOB
SIB
HOB
HSB
VDD
OVS
OVP
13
14
16
15
Figure 1. Top View
SOIC-28
PIN DESCRIPTIONS
Pin
Name
Description
Application Information
1
SIA
Sense high input for input current
sense transconductance amplifier
Tie to positive side of the current sense resistor through an external gain
programming resistor (RI). Amplifier transconductance is 1/RI.
2
3
S0A
IIN
Sense low input for input current
sense transconductance amplifier
Tie to negative side of the current sense resistor through an external gain
programming resistor. Amplifier transconductance is 1/RI.
Output for current sense
transconductance amplifier
Output of the input current sense amplifier. Requires an external resistor to
ground (RL). Gain is RL/RI, where RI is the external resistor in series with the
SIA pin.
4
5
BIN
Buffered IIN
Buffered IIN.
AGND Analog ground
Ground return for the analog circuitry. Tie to the ground plane under the IC
6, 9
LIA, LIB Low side driver control input
The inputs have TTL type thresholds. Unused inputs should be tied to ground
and not left open.
7, 8
10
HIA, HIB High side driver control input
PGOOD Power good indicator output
The inputs have TTL type thresholds. Unused inputs should be tied to ground
and not left open.
Open drain output with an internal pull-up resistor to VDD indicating VCC is in
regulation. PGOOD low implies VCC is out of regulation.
11
12
BOUT
IOUT
Buffered IOUT
Buffered IOUT.
Output for current sense
comparator.
Output of the output current sense amplifier. Requires an external resistor to
ground (RL). Gain is RL/RI, where RI is the external resistor in series with the
SIB pin.
13
14
15
S0B
SIB
Sense low input for output current Tie to negative side of the current sense resistor through an external gain
sense amplifier programming resistor. Amplifier transconductance is 1/RI.
Sense high input for output current Tie to positive side of the current sense resistor through an external gain
sense amplifier
programming resistor (RI). Amplifier transconductance is 1/RI.
OVP
Over voltage indicator output
Open drain output with an internal pull-up resistor to VDD indicating OVS >VDD.
OVP is low when OVS>VDD.
16
17
OVS
VDD
Sense input for over voltage
3.3V or 5V regulator output
Requires an external resistor divider. VDD is the reference voltage.
Bypass with 0.1uF. Reference for over voltage shutdown and IOUT/IIN clamp
18, 28
HSA,
HSB
High side MOSFET source
connection
Connect to bootstrap capacitor negative terminal and the source of the high side
MOSFET.
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PIN DESCRIPTIONS (continued)
Pin
Name
Description
Application Information
19, 27
HOA,
HOB
High side gate driver output
Connect to gate of high side MOSFET with a short low inductance path.
20,26
HBA,
HBB
High side gate driver bootstrap rail. Connect the positive terminal of the bootstrap capacitor to HB and the negative
terminal to HS. The bootstrap capacitor should be placed as close to IC as
possible.
21,25
22, 24
23
VCCA, Positive gate drive supply
VCCB
Locally decouple to PGND using low ESR/ESL capacitor located as close to IC
as possible.
LOA,
LOB
Low side gate driver output
Connect to the gate of the low side MOSFET with a short low inductance path.
PGND Power ground return
Ground return for the LO drivers. Tie to the ground plane under the IC
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
VCCA, VCCB
-0.3 to 14V
-0.3 to 7V
VDD
HBA to HSA, HBB to HSB
LIA,LIB,HIA,HIB,OVS
LOA,LOB
-0.3 to 15V
-0.3 to 7V
-0.3 to VCC+ 0.3V
HS–0.3 to HB + 0.3V
-0.3 to 100V
-0.8 to 0.8V
-5 to 100V
HOA,HOB
SIA,SOA,SIB,SOB
SIA to SOA, SIB to SOB
HSA,HSB(3)
HBA, HBB
115V
PGOOD, OVP
IIN, IOUT
-0.3 to VDD
-0.3 to VDD
-0.3 to VDD
150°C
BIN, BOUT
Junction Temperature
Storage Temperatue Range
ESD Rating(4)
-55°C to +150°C
2 kV
Human Body Model
(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under
which operation of the device is ensured. Operating Ratings do not imply ensured performance limits. For ensured performance limits
and associated test conditions, see the Electrical Characteristics tables.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
(3) In the application the HS nodes are clamped by the body diode of the external lower N-MOSFET, therefore the HS node will generally
not exceed –1V. However, in some applications, board resistance and inductance may result in the HS node exceeding this stated
voltage transiently. If negative transients occur, the HS voltage must never be more negative than VCC-15V. For example if VCC = 10V,
the negative transients at HS must not exceed –5V.
(4) The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. 2 kV for all pins except HB, HO & HS
which are rated at 1000V.
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Recommended Operating Conditions
VCCA,VCCB
+8V to +14V
+3V to 7V
VDD
SI, SO common mode
HS(1)
VDD+1V to 100V
-1V to 100V
HBA, HBB
HS+7V to HS+14V
<50V/ns
HS Slew Rate
Junction Temperature
-40°C to +125°C
(1) In the application the HS nodes are clamped by the body diode of the external lower N-MOSFET, therefore the HS node will generally
not exceed –1V. However, in some applications, board resistance and inductance may result in the HS node exceeding this stated
voltage transiently. If negative transients occur, the HS voltage must never be more negative than VCC-15V. For example if VCC = 10V,
the negative transients at HS must not exceed –5V.
Electrical Characteristics(1)
Specifications in standard typeface are for TJ = 25°C, and those in boldface type apply over the full operating junction
temperature range. No load on LO & HO, VCC = 10V, VDD = 5V, HB-HS = 10V, OVS = 0V unless otherwise indicated.
Symbol
SUPPLY CURRENTS
IDD VDD Quiescent Current
Parameter
Conditions
Min
Typ
Max
Units
SIA = SOB, SIB = SOB.
All outputs off
25
40
μA
μA
VCC Quiescent Current
(ICCA+ICCB)
ICC
500
800
VCC Operating Current
(ICCA+ICCB)
ICCO
LOA & LOB switching at 200kHz
2.2
3
mA
IHB
HBA, HBB Quiescent Current
HBA, HBB Operating Current
All outputs off
55
200
μA
μA
IHBO
HOA & HOB switching at 200kHz
700
1000
HBA & HBB to VSS Current,
Quiescent
IHBS
HS = 100V, HB = 110V
f = 200kHz
0.1
10
μA
μA
HBA and HBB to VSS Current,
Operating
IHBSO
130
PGOOD, OVB OUTPUTs
VOL
RPU
Output Low RDS
25
50
50
90
Ω
VDD pull up resistor
kΩ
LI ,HI INPUT PINS
VIL
Input Voltage Threshold
1.3
100
1.8
50
2.3
400
V
VIHYS
RI
Input Voltage Hysteresis
mV
kΩ
LI, HI Pull down Resistance
200
OVER VOLTAGE SHUTDOWN
VOVR
VOVH
IOVS
OVS Rising Threshold
OVS threshold Hysteresis
OVS input bias current
VDD-50mV
VDD
5%
1
VDD+50mV
V
VDD
nA
OVS<VDD
UNDER VOLTAGE SHUTDOWN
VCCR
VCCH
VHBR
VHBH
VCC Rising Threshold
6
6.9
0.5
6.6
0.4
7.4
7.1
V
V
V
V
VCC threshold Hysteresis
HB-HS Rising Threshold
HB-HS Threshold Hysteresis
5.7
BOOT STRAP DIODE
VDH
RD
High-Current Forward Voltage
Dynamic Resistance
IVCC-HB = 100mA
IVCC-HB = 100mA
0.8
1
1
V
1.65
Ω
(1) Min and Max limits are 100% production tested at 25ºC. Limits over the operating temperature range are ensured through correlation
using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
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Electrical Characteristics(1) (continued)
Specifications in standard typeface are for TJ = 25°C, and those in boldface type apply over the full operating junction
temperature range. No load on LO & HO, VCC = 10V, VDD = 5V, HB-HS = 10V, OVS = 0V unless otherwise indicated.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
LO & HO GATE DRIVER
ILO = 100mA
VOL = LO-PGND or HO-HS
VOL
VOH
Low-Level Output Voltage
0.16
0.28
0.4
0.6
V
V
ILO = -100mA
VOH = VCC-LO or VCC-HO
High-Level Output Voltage
IOHL
Peak Pullup Current
HO, LO = 12V
HO, LO = 0V
3
A
IOLL
Peak Pulldown Current
3
A
tLPHL
tLPLH
tHPHL
tHPLH
LO Turn-Off Propagation Delay LI Falling to LO Falling
LO Turn-On Propagation Delay LI Rising to LO Rising
HO Turn-Off Propagation Delay HI Falling to HO Falling
LO Turn-On Propagation Delay HI Rising to HO Rising
22
26
22
26
ns
ns
ns
ns
Delay Matching: LO on & HO
off
tMON
1
ns
Delay Matching: LO off & HO
on
tMOFF
tRC, tFC
tPW
1
8
ns
ns
ns
Either Output Rise/Fall Time
CL = 1000pF
Minimum Input Pulse Width that
Changes the Output
50
Bootstrap Diode Turn-On or
Turn-Off Time
tBS
IF = 100mA/ IR = 100mA
37
ns
CURRENT SENSE AMPLIFIER
RSI = RSO = 500, 10mV sense
resistor voltage
VOS
Offset voltage
-2
2
mV
mV
Gain is programmed with
5mV sense resistor voltage
RSI = RSO = 1000, RL = 75K
Gain 5mV external resistors
IOUT, IIN =(RL/RSI )* (SI-SO)
390
Gain is programmed with
external resistors
IOUT, IIN =(RL/RSI )* (SI-SO)
Gain
50mV
50mV sense resistor voltage
RSI = RSO = 1000, RL = 75K
3.85
VDD
V
V
0.1V sense resistor voltage
RSI = RSO = 1000, RL = 75K
Vclamp
Output Clamp
CURRENT SENSE BUFFER
Offset voltage (BIN-IIN),
IIN = 2.5V
-60
60
mV
(BOUT-IOUT)
Output low voltage BOUT,BIN
IIN, IOUT = 0
0
50
mV
mV
Output high voltage BOUT,BIN IIN, IOUT = VDD
THERMAL RESISTANCE
θJA Junction to Ambient
VDD-100mV
VDD-30mV
60
VDD
SOIC-28(2)
°C/W
(2) 2 layer board with 2 oz Cu using JEDEC JESD51 thermal board.
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Block Diagram
HBB
HOB
VCCB
VCCA
VDD
3V
UVLO
DRIVER
LEVEL
SHIFT
3V
200k
HSB
HBA
UVLO
HOA
DRIVER
DRIVER
VDD
VCC
LEVEL
SHIFT
3V
HSA
VCCA
LOB
50k
UVLO
PGOOD
3V
VDD
50k
PGND
VCCB
OVP
OVS
3V
LOA
DRIVER
+
PGND
VDD3.3V/5V
-
SIA
SOA
IIN
SIB
+
_
+
_
SOB
IOUT
+
_
+
_
VDD
CLAMP
VDD
CLAMP
BIN
BOUT
AGND
Figure 2. Block Diagram
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Typical Performance Characteristics
Operating Current
vs Temperature
VCC Undervoltage Rising Threshold
vs Temperature
Figure 3.
Figure 4.
VCC Quiescent Current
vs Temperature
VCC Undervoltage Threshold Hysteresis
vs Temperature
Figure 5.
Figure 6.
VDD Quiescent Current
vs Temperature
Gate Drive High Level Output Voltage
vs Temperature
Figure 7.
Figure 8.
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Typical Performance Characteristics (continued)
Gate Drive Low level Output Voltage
vs Temperature
Bootstrap Diode Forward Voltage
vs Temperature
Figure 9.
Figure 10.
Current Sense Amplifier Input Offset Voltage
vs Temperature
Current Sense Amplifier Output Buffer Offset Voltage
vs Temperature
Figure 11.
Figure 12.
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SNVS688E –OCTOBER 2010–REVISED APRIL 2013
Timing Diagram
LI
LI
HI
HI
t
HPLH
t
LPLH
t
HPHL
t
LPHL
LO
LO
HO
HO
t
t
MOFF
MON
Power Dissipation Considerations
The total IC power dissipation is the sum of the gate driver losses and the bootstrap diode losses. The gate
driver losses are related to the switching frequency (f), output load capacitance on LO and HO (CL), and supply
voltage (VDD) and can be roughly calculated as:
2
PDGATES = 2 • f • CL • VDD
(1)
There are some additional losses in the gate drivers due to the internal CMOS stages used to buffer the LO and
HO outputs. The following plot shows the measured gate driver power dissipation versus frequency and load
capacitance. At higher frequencies and load capacitance values, the power dissipation is dominated by the
power losses driving the output loads and agrees well with the above equation. This plot can be used to
approximate the power losses due to the gate drivers.
Figure 13. Gate Driver Power Dissipation (LO + HO)
VCC = 12V, Neglecting Diode Losses
1.000
C
= 4400 pF
L
0.100
0.010
0.001
C
= 1000 pF
L
C
= 0 pF
L
0.1
1.0
10.0
100.0
1000.0
SWITCHING FREQUENCY (kHz)
The bootstrap diode power loss is the sum of the forward bias power loss that occurs while charging the
bootstrap capacitor and the reverse bias power loss that occurs during reverse recovery. Since each of these
events happens once per cycle, the diode power loss is proportional to frequency. Larger capacitive loads
require more current to recharge the bootstrap capacitor resulting in more losses. Higher input voltages (VIN) to
the half bridge result in higher reverse recovery losses. The following plot was generated based on calculations
and lab measurements of the diode recovery time and current under several operating conditions. This can be
useful for approximating the diode power dissipation. The total IC power dissipation can be estimated from the
previous plots by summing the gate drive losses with the bootstrap diode losses for the intended application.
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Figure 14. Diode Power Dissipation VIN = 50V
0.100
0.010
0.001
C
= 4400 pF
L
C
= 0 pF
L
1
10
100
1000
SWITCHING FREQUENCY (kHz)
Layout Considerations
The optimum performance of high and low-side gate drivers cannot be achieved without taking due
considerations during circuit board layout. Following points are emphasized.
1. Low ESR / ESL capacitors must be connected close to the IC, between VDD and VSS pins and between the
HB and HS pins to support the high peak currents being drawn from VDD during turn-on of the external
MOSFET.
2. To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor must be
connected between MOSFET drain and ground (VSS).
3. In order to avoid large negative transients on the switch node (HS pin), the parasitic inductances in the
source of top MOSFET and in the drain of the bottom MOSFET (synchronous rectifier) must be minimized.
4. Grounding Considerations:
(a) The first priority in designing grounding connections is to confine the high peak currents that charge and
discharge the MOSFET gate into a minimal physical area. This will decrease the loop inductance and
minimize noise issues on the gate terminal of the MOSFET. The MOSFETs should be placed as close as
possible to the gate driver.
(b) The second high current path includes the bootstrap capacitor, the bootstrap diode, the local ground
referenced bypass capacitor and low-side MOSFET body diode. The bootstrap capacitor is recharged on
a cycle-by-cycle basis through the bootstrap diode from the ground referenced VDD bypass capacitor.
The recharging occurs in a short time interval and involves high peak current. Minimizing this loop length
and area on the circuit board is important to ensure reliable operation.
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REVISION HISTORY
Changes from Revision D (April 2013) to Revision E
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 10
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PACKAGE OPTION ADDENDUM
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12-Oct-2014
PACKAGING INFORMATION
Orderable Device
SM72295MA/NOPB
SM72295MAE/NOPB
SM72295MAX/NOPB
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
SOIC
SOIC
SOIC
DW
28
28
28
26
Green (RoHS
& no Sb/Br)
CU SN
CU SN
CU SN
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
S72295
ACTIVE
ACTIVE
DW
DW
250
Green (RoHS
& no Sb/Br)
-40 to 125
S72295
S72295
1000
Green (RoHS
& no Sb/Br)
-40 to 125
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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12-Oct-2014
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SM72295MAE/NOPB
SM72295MAX/NOPB
SOIC
SOIC
DW
DW
28
28
250
178.0
330.0
24.4
24.4
10.8
10.8
18.4
18.4
3.2
3.2
12.0
12.0
24.0
24.0
Q1
Q1
1000
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SM72295MAE/NOPB
SM72295MAX/NOPB
SOIC
SOIC
DW
DW
28
28
250
213.0
367.0
191.0
367.0
55.0
45.0
1000
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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Products
Applications
Audio
www.ti.com/audio
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
Automotive and Transportation www.ti.com/automotive
Communications and Telecom www.ti.com/communications
Amplifiers
Data Converters
DLP® Products
DSP
Computers and Peripherals
Consumer Electronics
Energy and Lighting
Industrial
www.ti.com/computers
www.ti.com/consumer-apps
www.ti.com/energy
dsp.ti.com
Clocks and Timers
Interface
www.ti.com/clocks
interface.ti.com
logic.ti.com
www.ti.com/industrial
www.ti.com/medical
Medical
Logic
Security
www.ti.com/security
Power Mgmt
Microcontrollers
RFID
power.ti.com
Space, Avionics and Defense
Video and Imaging
www.ti.com/space-avionics-defense
www.ti.com/video
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/omap
OMAP Applications Processors
Wireless Connectivity
TI E2E Community
e2e.ti.com
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2014, Texas Instruments Incorporated
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