SM73306MA [TI]
SM73306 CMOS Rail-to-Rail Input and Output Operational Amplifier; SM73306 CMOS轨到轨输入和输出运算放大器
| 型号： | SM73306MA |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SM73306 CMOS Rail-to-Rail Input and Output Operational Amplifier |
| 文件： | 总22页 (文件大小：918K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SM73306
SM73306 CMOS Rail-to-Rail Input and Output Operational Amplifier
Literature Number: SNOSB99A
July 5, 2011
SM73306
CMOS Rail-to-Rail Input and Output Operational Amplifier
General Description
Features
The SM73306 amplifier was specifically developed for single
supply applications that operate from −40°C to +125°C. This
wide temperature range makes it well-suited for photovoltaic
systems. A unique design topology enables the SM73306
common-mode voltage range to accommodate input signals
beyond the rails. This eliminates non-linear output errors due
to input signals exceeding a traditionally limited common-
mode voltage range. The SM73306 signal range has a high
CMRR of 82 dB for excellent accuracy in non-inverting circuit
configurations.
(Typical unless otherwise noted)
Renewable Energy Grade
■
■
Rail-to-Rail input common-mode voltage range,
guaranteed over temperature
Rail-to-Rail output swing within 20 mV of supply rail,
100 kΩ load
■
Operates from 5V to 15V supply
■
■
■
Excellent CMRR and PSRR 82 dB
Ultra low input current 150 fA
The SM73306 rail-to-rail input is complemented by rail-to-rail
output swing. This assures maximum dynamic signal range
which is particularly important in 5V systems.
High voltage gain (RL = 100 kΩ) 120 dB
Low supply current (@ VS = 5V)ꢀ500 μA/Amplifier
Low offset voltage driftꢀ1.0 μV/°C
■
■
■
Ultra-low input current of 150 fA and 120 dB open loop gain
provide high accuracy and direct interfacing with high
impedance sources.
Applications
Automotive transducer amplifier
■
■
■
■
Pressure sensor
Oxygen sensor
Temperature sensor
Speed sensor
■
Connection Diagram
8-Pin SO
30159501
Top View
© 2011 National Semiconductor Corporation
301595
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Ordering Information
Transport
Media
NSC
Drawing
Part Number
Package
Package Marking
SM73306MA
SM73306MAE
SM73306MAX
95 Units in Rails
S3306
S3306
S3306
SOIC-8
250 Units in Tape and Reel
2500 Units in Tape and Reel
M08A
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2
Absolute Maximum Ratings (Note 1)
Operating Conditions (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
2.5V ≤ V+ ≤ 15.5V
Supply Voltage
Junction Temperature Range
Thermal Resistance (θJA
−40°C ≤ TJ ≤ +125°C
)
171°C/W
ESD Tolerance (Note 2)
2000V
±Supply Voltage
Differential Input Voltage
Voltage at Input/Output Pin
Supply Voltage (V+ − V−)
Current at Input Pin
(V+) + 0.3V, (V−) − 0.3V
16V
±5 mA
Current at Output Pin (Note 3)
Current at Power Supply Pin
Lead Temp. (Soldering, 10 sec.)
Storage Temperature Range
Junction Temperature (Note 4)
±30 mA
40 mA
260°C
−65°C to +150°C
150°C
DC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ = 25°C, V+ = 5V, V− = 0V, VCM = VO = V+/2 and RL > 1 MΩ. Boldface limits
apply at the temperature extremes
Symbol
VOS
Parameter
Conditions
Typ (Note 5)
Limit (Note 6)
Units
mV
Input Offset Voltage
6.0
0.11
6.8
max
TCVOS
Input Offset Voltage
Average Drift
1.0
μV/°C
IB
Input Bias Current
Input Offset Current
Input Resistance
Common-Mode
(Note 11)
(Note 11)
0.15
0.075
>10
3
200
100
pA max
pA max
IOS
RIN
CIN
Tera Ω
pF
Input Capacitance
Common-Mode
CMRR
63
58
63
dB
min
82
82
0V ≤ VCM ≤ 15V
Rejection Ratio
V+ = 15V
0V ≤ VCM ≤ 5V
58
5V ≤ V+ ≤ 15V,
VO = 2.5V
+PSRR
−PSRR
VCM
Positive Power Supply
Rejection Ratio
63
dB
min
dB
82
58
0V ≤ V− ≤ −10V,
VO = 2.5V
Negative Power Supply
63
82
Rejection Ratio
58
−0.25
0
min
V
Input Common-Mode
Voltage Range
V+ = 5V and 15V
V− −0.3
V+ + 0.3
max
V
For CMRR ≥ 50 dB
V+ + 0.25
V+
min
V/mV
min
AV
Large Signal Voltage Gain
300
40
RL = 2 kΩ: Sourcing
(Note 7)
Sinking
3
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Symbol
VO
Parameter
Output Swing
Conditions
Typ (Note 5)
Limit (Note 6)
Units
V
V+ = 5V
4.8
4.9
RL = 2 kΩ to V+/2
4.7
min
0.1
4.7
0.18
0.24
4.5
V
max
V
V+ = 5V
RL = 600Ω to V+/2
4.24
min
0.3
0.5
V
max
V
0.65
14.4
14.0
V+ = 15V
14.7
RL = 2 kΩ to V+/2
min
0.16
14.1
0.35
0.5
V
max
V
V+ = 15V
13.4
13.0
RL = 600Ω to V+/2
min
0.5
25
1.0
1.5
16
V
max
ISC
ISC
IS
Output Short Circuit Current Sourcing, VO = 0V
V+ = 5V
10
Sinking, VO = 5V
Output Short Circuit Current Sourcing, VO = 0V
11
22
8
mA
min
28
30
20
V+ = 15V
Sinking, VO = 5V (Note 8)
V+ = +5V, VO = V+/2
30
30
22
Supply Current
1.75
2.1
1.95
2.3
mA
max
mA
1.0
1.3
V+ = +15V, VO = V+/2
max
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AC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ = 25°C, V+ = 5V, V− = 0V, VCM = VO = V+/2 and RL > 1 MΩ. Boldface limits
apply at the temperature extremes
Typ
(Note 5)
Limit (Note 6)
Symbol
Parameter
Slew Rate
Conditions
Units
SR
(Note 9)
0.7
1.3
Vμs min
0.5
GBW
φm
Gain-Bandwidth Product V+ = 15V
Phase Margin
1.5
50
MHz
Deg
dB
Gm
Gain Margin
15
150
37
Amp-to-Amp Isolation
Input-Referred
(Note 10)
dB
en
F = 1 kHz
VCM = 1V
Voltage Noise
in
Input-Referred
Current Noise
F = 1 kHz
0.06
0.01
T.H.D.
Total Harmonic Distortion F = 1 kHz, AV = −2
RL = 10 kΩ, VO = −4.1 VPP
F = 10 kHz, AV = −2
RL = 10 kΩ, VO = 8.5 VPP
V+ = 10V
%
0.01
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics.
Note 2: Human body model, 1.5 kΩ in series with 100 pF.
Note 3: Applies to both single-supply and split-supply operation. Continuous short operation at elevated ambient temperature can result in exceeding the maximum
allowed junction temperature at 150°C. Output currents in excess of ±30 mA over long term may adversely affect reliability.
Note 4: The maximum power dissipation is a function of TJ(max), θJA and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ
(max) − TA)/θJA. All numbers apply for packages soldered directly into a PC board.
Note 5: Typical Values represent the most likely parametric norm.
Note 6: All limits are guaranteed by testing or statistical analysis.
Note 7: V+ = 15V, VCM = 7.5V and RL connected to 7.5V. For Sourcing tests, 7.5V ≤ VO ≤ 11.5V. For Sinking tests, 3.5V ≤ VO ≤ 7.5V.
Note 8: Do not short circuit output to V+, when V+ is greater than 13V or reliability will be adversely affected.
Note 9: V+ = 15V. Connected as voltage follower with 10V step input. Number specified is the slower of the positive and negative slew rates.
Note 10: Input referred, V+ = 15V and RL = 100 kΩ connected to 7.5V. Each amp excited in turn with 1 kHz to produce VO = 12 VPP
.
Note 11: Guaranteed limits are dictated by tester limits and not device performance. Actual performance is reflected in the typical value.
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Typical Performance Characteristics VS = +15V, Single Supply, TA = 25°C unless otherwise specified
Supply Current vs
Supply Voltage
Input Current vs
Temperature
30159525
30159526
Sourcing Current vs
Output Voltage
Sourcing Current vs
Output Voltage
30159527
30159528
Sourcing Current vs
Output Voltage
Sinking Current vs
Output Voltage
30159530
30159529
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Sinking Current vs
Output Voltage
Sinking Current vs
Output Voltage
30159531
30159532
Output Voltage Swing vs
Supply Voltage
Input Voltage Noise
vs Frequency
30159534
30159533
Input Voltage Noise
vs Input Voltage
Input Voltage Noise
vs Input Voltage
30159535
30159536
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Input Voltage Noise
vs Input Voltage
Crosstalk Rejection
vs Frequency
30159537
30159538
30159540
30159542
Crosstalk Rejection
vs Frequency
Positive PSRR
vs Frequency
30159539
Negative PSRR
vs Frequency
CMRR vs
Frequency
30159541
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CMRR vs
Input Voltage
CMRR vs
Input Voltage
30159543
30159544
CMRR vs
Input Voltage
ΔVOS
vs CMR
30159545
30159546
Input Voltage vs
Output Voltage
ΔVOS
vs CMR
30159548
30159547
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Input Voltage vs
Output Voltage
Open Loop
Frequency Response
30159549
30159550
Open Loop
Frequency Response
Open Loop Frequency
Response vs Temperature
30159551
30159552
Maximum Output Swing
vs Frequency
Gain and Phase vs
Capacitive Load
30159553
30159554
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Gain and Phase vs
Capacitive Load
Open Loop Output
Impedance vs Frequency
30159555
30159556
Open Loop Output
Impedance vs Frequency
Slew Rate vs
Supply Voltage
30159558
30159557
Non-Inverting Large
Signal Pulse Response
Non-Inverting Large
Signal Pulse Response
30159559
30159560
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Non-Inverting Large
Signal Pulse Response
Non-Inverting Small
Signal Pulse Response
30159561
30159563
30159565
30159562
Non-Inverting Small
Non-Inverting Small
Signal Pulse Response
Signal Pulse Response
30159564
Inverting Large
Signal Pulse Response
Inverting Large Signal
Pulse Response
30159566
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Inverting Large Signal
Pulse Response
Inverting Small Signal
Pulse Response
30159567
30159568
Inverting Small Signal
Pulse Response
Inverting Small Signal
Pulse Response
30159569
30159570
Stability vs
Capacitive Load
Stability vs
Capacitive Load
30159571
30159572
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Stability vs
Capacitive Load
Stability vs
Capacitive Load
30159573
30159574
Stability vs
Capacitive Load
Stability vs
Capacitive Load
30159575
30159576
The absolute maximum input voltage is 300 mV beyond either
supply rail at room temperature. Voltages greatly exceeding
this absolute maximum rating, as in Figure 2, can cause ex-
cessive current to flow in or out of the input pins possibly
affecting reliability.
Application Hints
INPUT COMMON-MODE VOLTAGE RANGE
Unlike Bi-FET amplifier designs, the SM73306 does not ex-
hibit phase inversion when an input voltage exceeds the
negative supply voltage. Figure 1 shows an input voltage ex-
ceeding both supplies with no resulting phase inversion on
the output.
30159509
FIGURE 2. A ±7.5V Input Signal Greatly
Exceeds the 5V Supply in Figure 3 Causing
No Phase Inversion Due to RI
30159508
Applications that exceed this rating must externally limit the
maximum input current to ±5 mA with an input resistor (RI) as
shown in Figure 3.
FIGURE 1. An Input Voltage Signal Exceeds the
SM73306 Power Supply Voltages with
No Output Phase Inversion
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14
included in this integrator stage. The frequency location of the
dominant pole is affected by the resistive load on the amplifier.
Capacitive load driving capability can be optimized by using
an appropriate resistive load in parallel with the capacitive
load (see Typical Curves).
Direct capacitive loading will reduce the phase margin of
many op-amps. A pole in the feedback loop is created by the
combination of the op-amp's output impedance and the ca-
pacitive load. This pole induces phase lag at the unity-gain
crossover frequency of the amplifier resulting in either an os-
cillatory or underdamped pulse response. With a few external
components, op amps can easily indirectly drive capacitive
loads, as shown in Figure 5.
30159510
FIGURE 3. RI Input Current Protection for
Voltages Exceeding the Supply Voltages
RAIL-TO-RAIL OUTPUT
The approximate output resistance of the SM73306 is 110Ω
sourcing and 80Ω sinking at Vs = 5V. Using the calculated
output resistance, maximum output voltage swing can be es-
itmated as a function of load.
COMPENSATING FOR INPUT CAPACITANCE
It is quite common to use large values of feedback resistance
for amplifiers with ultra-low input current, like the SM73306.
Although the SM73306 is highly stable over a wide range of
operating conditions, certain precautions must be met to
achieve the desired pulse response when a large feedback
resistor is used. Large feedback resistors with even small
values of input capacitance, due to transducers, photodiodes,
and circuit board parasitics, reduce phase margins.
When high input impedances are demanded, guarding of the
SM73306 is suggested. Guarding input lines will not only re-
duce leakage, but lowers stray input capacitance as well.
(See Printed-Circuit-Board Layout for High Impedance
Work).
30159512
FIGURE 5. SM73306 Noninverting Amplifier,
Compensated to Handle Capacitive Loads
PRINTED-CIRCUIT-BOARD LAYOUT
FOR HIGH-IMPEDANCE WORK
The effect of input capacitance can be compensated for by
adding a capacitor, Cf, around the feedback resistors (as in
Figure 1 ) such that:
It is generally recognized that any circuit which must operate
with less than 1000 pA of leakage current requires special
layout of the PC board. When one wishes to take advantage
of the ultra-low bias current of the SM73306, typically
150 fA, it is essential to have an excellent layout. Fortunately,
the techniques of obtaining low leakages are quite simple.
First, the user must not ignore the surface leakage of the PC
board, even though it may sometimes appear acceptably low,
because under conditions of high humidity or dust or contam-
ination, the surface leakage will be appreciable.
or
R1 CIN ≤ R2 Cf
Since it is often difficult to know the exact value of CIN, Cf can
be experimentally adjusted so that the desired pulse re-
sponse is achieved.
To minimize the effect of any surface leakage, lay out a ring
of foil completely surrounding the SM73306's inputs and the
terminals of components connected to the op-amp's inputs,
as in Figure 6. To have a significant effect, guard rings should
be placed on both the top and bottom of the PC board. This
PC foil must then be connected to a voltage which is at the
same voltage as the amplifier inputs, since no leakage current
can flow between two points at the same potential. For ex-
ample, a PC board trace-to-pad resistance of 1012Ω, which is
normally considered a very large resistance, could leak 5 pA
if the trace were a 5V bus adjacent to the pad of the input.
This would cause a 33 times degradation from the SM73306's
actual performance. If a guard ring is used and held within 5
mV of the inputs, then the same resistance of 1012Ω will only
cause 0.05 pA of leakage current. See Figure 7 for typical
connections of guard rings for standard op-amp configura-
tions.
30159511
FIGURE 4. Cancelling the Effect of Input Capacitance
CAPACITIVE LOAD TOLERANCE
All rail-to-rail output swing operational amplifiers have voltage
gain in the output stage. A compensation capacitor is normally
15
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30159513
FIGURE 6. Examples of Guard
Ring in PC Board Layout
Application Circuits
DC Summing Amplifier (VIN ≥ 0VDC and VO ≥ VDC
30159514
Inverting Amplifier
30159518
Where: V0 = V1 + V2 − V3 – V4
(V1 + V2 ≥ (V3 + V4) to keep V0 > 0VDC
High Input Z, DC Differential Amplifier
30159515
Non-Inverting Amplifier
30159516
30159519
Follower
For
FIGURE 7. Typical Connections of Guard Rings
(CMRR depends on this resistor ratio match)
As shown: VO = 2(V2 − V1)
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16
Photo Voltaic-Cell Amplifier
also take advantage of the SM73306 ultra-low input current.
The ultra-low input current yields negligible offset error even
when large value resistors are used. This in turn allows the
use of smaller valued capacitors which take less board space
and cost less.
Low Voltage Peak Detector with Rail-to-Rail Peak Capture
Range
30159520
Instrumentation Amplifier
30159523
Dielectric absorption and leakage is minimized by using a
polystyrene or polypropylene hold capacitor. The droop rate
is primarily determined by the value of CH and diode leakage
current. Select low-leakage current diodes to minimize droop-
ing.
Pressure Sensor
30159521
If R1 = R5, R3 = R6, and R4 = R7; then
∴AV ≈ 100 for circuit shown (R2 = 9.3k).
30159524
Rail-to-Rail Single Supply Low Pass Filter
Rf = Rx
Rf >> R1, R2, R3, and R4
In a manifold absolute pressure sensor application, a strain
gauge is mounted on the intake manifold in the engine unit.
Manifold pressure causes the sensing resistors, R1, R2, R3
and R4 to change. The resistors change in a way such that
R2 and R4 increase by the same amount R1 and R3 de-
crease. This causes a differential voltage between the input
of the amplifier. The gain of the amplifier is adjusted by Rf.
30159522
This low-pass filter circuit can be used as an anti-aliasing filter
with the same supply as the A/D converter. Filter designs can
17
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Physical Dimensions inches (millimeters) unless otherwise noted
8-Pin Small Outline Package
NS Package Number M08A
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18
Notes
19
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