SM74104MAX/NOPB [TI]
具有 8V UVLO 和自适应延迟的 1.8A、100V 半桥栅极驱动器 | D | 8 | -40 to 125;
| 型号： | SM74104MAX/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 8V UVLO 和自适应延迟的 1.8A、100V 半桥栅极驱动器 | D | 8 | -40 to 125 栅极驱动 接口集成电路 驱动器 驱动程序和接口 |
| 文件： | 总16页 (文件大小：359K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SM74104
SM74104 High Voltage Half-Bridge Gate Driver with Adaptive Delay
Literature Number: SNOSBA3B
November 14, 2011
SM74104
High Voltage Half-Bridge Gate Driver with Adaptive Delay
General Description
Features
The SM74104 High Voltage Gate Driver is designed to drive
both the high side and the low side N-Channel MOSFETs in
a synchronous buck configuration. The floating high-side driv-
er is capable of working with supply voltages up to 100V. The
high side and low side gate drivers are controlled from a single
input. Each change in state is controlled in an adaptive man-
ner to prevent shoot-through issues. In addition to the adap-
tive transition timing, an additional delay time can be added,
proportional to an external setting resistor. An integrated high
voltage diode is provided to charge the high side gate drive
bootstrap capacitor. A robust level shifter operates at high
speed while consuming low power and providing clean level
transitions from the control logic to the high side gate driver.
Under-voltage lockout is provided on both the low side and
the high side power rails. This device is available in the stan-
dard SOIC-8 pin and the LLP-10 pin packages.
Renewable Energy Grade
■
■
■
Drives both a high side and low side N-channel MOSFET
Adaptive rising and falling edges with programmable
additional delay
Single input control
■
■
■
■
Bootstrap supply voltage range up to 118V DC
Fast turn-off propagation delay (25 ns typical)
Drives 1000 pF loads with 15 ns rise and fall times
Supply rail under-voltage lockout
■
Typical Applications
Current Fed Push-Pull Power Converters
■
■
■
■
High Voltage Buck Regulators
Active Clamp Forward Power Converters
Half and Full Bridge Converters
Package
LLP-10 (4 mm x 4 mm)
■
■
SOIC-8
© 2011 Texas Instruments Incorporated
301600
www.ti.com
Simplified Block Diagram
30160003
Connection Diagrams
30160001
8-Lead SOIC
See NS Package Number M08A
30160002
10-Lead LLP
See NS Package Number SDC10A
www.ti.com
2
Ordering Information
NSC Package
Drawing
Ordering Number
Package Type
Package Marking
Supplied As
SM74104SD
SM74104SDE
SM74104SDX
SM74104MA
SM74104MAE
SM74104 MAX
1000 Units in Tape and Reel
250 Units in Tape & Reel
4500 Units in Tape & Reel
95 Units in Rail
LLP-10
SOIC-8
S74104
SDC10A
M08A
S74104
250 Units in Tape & Reel
2500 Units in Tape & Reel
Pin Descriptions
Pin
Name
Description
Application Information
SOIC-8 LLP-10
1
1
VDD
HB
Positive gate drive supply Locally decouple to VSS using low ESR/ESL capacitor, located as close to
IC as possible.
2
2
High side gate driver
bootstrap rail
Connect the positive terminal of bootstrap capacitor to the HB pin and
connect negative terminal to HS. The Bootstrap capacitor should be placed
as close to IC as possible.
3
4
3
4
HO
HS
High side gate driver output Connect to gate of high side MOSFET with short low inductance path.
High side MOSFET source Connect to bootstrap capacitor negative terminal and source of high side
connection
MOSFET.
5
6
7
8
RT
IN
Deadtime programming pin Resistor from RT to ground programs the deadtime between high and low
side transitions.The resistor should be located close to the IC to minimize
noise coupling from adjacent traces.
Control input
Logic 1 equals High Side ON and Low Side OFF. Logic 0 equals High Side
OFF and Low Side ON.
7
8
9
VSS
LO
Ground return
All signals are referenced to this ground.
10
Low side gate driver output Connect to the gate of the low side MOSFET with a short low inductance
path.
Note: For LLP-10 package, it is recommended that the exposed pad on the bottom of the SM74104 be soldered to ground plane on the PC board, and
the ground plane should extend out from beneath the IC to help dissipate the heat. Pins 5 and 6 have no connection.
3
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RT to VSS
–0.3V to 5V
+150°C
–55°C to +150°C
2 kV
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the Texas Instruments Sales Office/
Distributors for availability and specifications.
Junction Temperature
Storage Temperature Range
ESD Rating HBM (Note 2)
VDD to VSS
VHB to VHS
IN to VSS
–0.3V to +18V
Recommended Operating
–0.3V to +18V
–0.3V to VDD + 0.3V
–0.3V to VDD + 0.3V
VHS – 0.3V to VHB + 0.3V
−1V to +100V
Conditions
VDD
HS
+9V to +14V
–1V to 100V
LO Output
HO Output
VHS to VSS
VHB to VSS
HB
VHS + 8V to VHS + 14V
<50V/ns
HS Slew Rate
Junction Temperature
118V
–40°C to +125°C
Electrical Characteristics Specifications in standard typeface are for TJ = +25°C, and those in boldface type
apply over the full operating junction temperature range. Unless otherwise specified, VDD = VHB = 12V, VSS = VHS = 0V, RT =
100kΩ. No Load on LO or HO.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
SUPPLY CURRENTS
IDD
VDD Quiescent Current
VDD Operating Current
LI = HI = 0V
0.4
1.9
0.6
3
mA
mA
mA
mA
µA
IDDO
f = 500 kHz
IHB
Total HB Quiescent Current
Total HB Operating Current
HB to VSS Current, Quiescent
HB to VSS Current, Operating
LI = HI = 0V
f = 500 kHz
0.06
1.3
0.2
3
IHBO
IHBS
VHS = VHB = 100V
f = 500 kHz
0.05
0.08
10
IHBSO
mA
INPUT PINS
VIL
VIH
RI
Low Level Input Voltage Threshold
High Level Input Voltage Threshold
Input Pulldown Resistance
0.8
1.8
1.8
V
V
2.2
100
200
500
kΩ
TIME DELAY CONTROLS
VRT
IRT
Nominal Voltage at RT
2.7
0.75
58
3
3.3
2.25
130
270
V
mA
ns
RT Pin Current Limit
RT = 0V
1.5
90
TD1
TD2
Delay Timer, RT = 10 kΩ
Delay Timer, RT = 100 kΩ
140
200
ns
UNDER VOLTAGE PROTECTION
VDDR
VDDH
VHBR
VHBH
VDD Rising Threshold
VDD Threshold Hysteresis
HB Rising Threshold
6.0
5.7
6.9
0.5
6.6
0.4
7.4
7.1
V
V
V
V
HB Threshold Hysteresis
BOOT STRAP DIODE
VDL
VDH
RD
Low-Current Forward Voltage
IVDD-HB = 100 µA
IVDD-HB = 100 mA
IVDD-HB = 100 mA
0.60
0.85
0.8
0.9
1.1
1.5
V
V
Ω
High-Current Forward Voltage
Dynamic Resistance
LO GATE DRIVER
VOLL
VOHL
Low-Level Output Voltage
ILO = 100 mA
0.25
0.35
0.4
V
V
High-Level Output Voltage
ILO = –100 mA
0.55
VOHL = VDD – VLO
IOHL
IOLL
Peak Pullup Current
VLO = 0V
1.6
1.8
A
A
Peak Pulldown Current
VLO = 12V
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4
Symbol
Parameter
Conditions
IHO = 100 mA
Min
Typ
Max
Units
HO GATE DRIVER
VOLH
VOHH
Low-Level Output Voltage
High-Level Output Voltage
0.25
0.35
0.4
V
V
IHO = –100 mA,
0.55
VOHH = VHB – VHO
IOHH
IOLH
Peak Pullup Current
VHO = 0V
1.6
1.8
A
A
Peak Pulldown Current
VHO = 12V
THERMAL RESISTANCE
Junction to Ambient
SOIC-8
170
40
°C/W
θJA
LLP-10 (Note 3)
Switching Characteristics Specifications in standard typeface are for TJ = +25°C, and those in boldface
type apply over the full operating junction temperature range. Unless otherwise specified, VDD = VHB = 12V, VSS = VHS = 0V,
No Load on LO or HO .
Symbol
tLPHL
Parameter
Conditions
Min
Typ
Max
56
Units
Lower Turn-Off Propagation Delay (IN Rising
to LO Falling)
25
ns
tHPHL
Upper Turn-Off Propagation Delay (IN Falling
to HO Falling)
25
56
ns
tRC, tFC
tR, tF
Either Output Rise/Fall Time
CL = 1000 pF
15
ns
µs
Either Output Rise/Fall Time
(3V to 9V)
CL = 0.1 µF
0.6
tBS
Bootstrap Diode Turn-Off Time
IF = 20 mA, IR = 200 mA
50
ns
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation
of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions,
see the Electrical Characteristics tables.
Note 2: The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin. 2 kV for all pins except Pin 2, Pin 3 and Pin 4 which are
rated at 500V.
Note 3: 4 layer board with Cu finished thickness 1.5/1/1/1.5 oz. Maximum die size used. 5x body length of Cu trace on PCB top. 50 x 50mm ground and power
planes embedded in PCB. See Application Note AN-1187.
Note 4: Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using Statistical
Quality Control (SQC) methods. Limits are used to calculate National’s Average Outgoing Quality Level (AOQL).
Note 5: The θJA is not a given constant for the package and depends on the printed circuit board design and the operating environment.
5
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Typical Performance Characteristics
IDD vs Frequency
Operating Current vs Temperature
30160010
30160011
Quiescent Current vs Supply Voltage
Quiescent Current vs Temperature
30160013
30160012
IHB vs Frequency
HO & LO Peak Output Current vs Output Voltage
30160018
30160017
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6
Diode Forward Voltage
Undervoltage Threshold Hysteresis vs Temperature
30160019
30160016
Undervoltage Rising Threshold vs Temperature
LO & HO Gate Drive—High Level Output Voltage vs
Temperature
30160020
30160021
LO & HO Gate Drive—Low Level Output Voltage vs
Temperature
Turn Off Propagation Delay vs Temperature
30160023
30160022
7
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Timing vs Temperature RT = 10K
Timing vs Temperature RT = 100K
30160015
30160024
Turn On Delay vs RT Resistor Value
30160014
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8
SM74104 Waveforms
30160005
FIGURE 1. Application Timing Waveforms
9
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top MOSFET and in the drain of the bottom MOSFET
(synchronous rectifier) must be minimized.
Operational Description
4. Grounding considerations:
ADAPTIVE SHOOT-THROUGH PROTECTION
a) The first priority in designing grounding connections is
to confine the high peak currents from charging and
discharging the MOSFET gate in a minimal physical
area. This will decrease the loop inductance and
minimize noise issues on the gate terminal of the
MOSFET. The MOSFETs should be placed as close as
possible to the gate driver.
b) The second high current path includes the bootstrap
capacitor, the bootstrap diode, the local ground
referenced bypass capacitor and low side MOSFET body
diode. The bootstrap capacitor is recharged on the cycle-
by-cycle basis through the bootstrap diode from the
ground referenced VDD bypass capacitor. The recharging
occurs in a short time interval and involves high peak
current. Minimizing this loop length and area on the
circuit board is important to ensure reliable operation.
SM74104 is a high voltage, high speed dual output driver de-
signed to drive top and bottom MOSFET’s connected in syn-
chronous buck or half-bridge configuration, from one exter-
nally provided PWM signal. SM74104 features adaptive delay
to prevent shoot-through current through top and bottom
MOSFETs during switching transitions. Referring to the tim-
ing diagram Figure 1, the rising edge of the PWM input (IN)
turns off the bottom MOSFET (LO) after a short propagation
delay (tP). An adaptive circuit in the SM74104 monitors the
bottom gate voltage (LO) and triggers a programmable delay
generator when the LO pin falls below an internally set thresh-
old (≈ Vdd/2). The gate drive of the upper MOSFET (HO) is
disabled until the deadtime expires. The upper gate is en-
abled after the TIMER delay (tP+TRT) , and the upper MOS-
FET turns-on. The additional delay of the timer prevents lower
and upper MOSFETs from conducting simultaneously, there-
by preventing shoot-through.
5. The resistor on the RT pin must be placed very close to
the IC and seperated from high current paths to avoid
noise coupling to the time delay generator which could
disrupt timer operation.
A falling transition on the PWM signal (IN) initiates the turn-
off of the upper MOSFET and turn-on of the lower MOSFET.
A short propagation delay (tP) is encountered before the up-
per gate voltage begins to fall. Again, the adaptive shoot-
through circuitry and the programmable deadtime TIMER
delays the lower gate turn-on time. The upper MOSFET gate
voltage is monitored and the deadtime delay generator is trig-
gered when the upper MOSFET gate voltage with respect to
ground drops below an internally set threshold (≈ Vdd/2). The
lower gate drive is momentarily disabled by the timer and
turns on the lower MOSFET after the deadtime delay expires
(tP+TRT).
POWER DISSIPATION CONSIDERATIONS
The total IC power dissipation is the sum of the gate driver
losses and the bootstrap diode losses. The gate driver losses
are related to the switching frequency (f), output load capac-
itance on LO and HO (CL), and supply voltage (VDD) and can
be roughly calculated as:
2
PDGATES = 2 • f • CL • VDD
There are some additional losses in the gate drivers due to
the internal CMOS stages used to buffer the LO and HO out-
puts. The following plot shows the measured gate driver
power dissipation versus frequency and load capacitance. At
higher frequencies and load capacitance values, the power
dissipation is dominated by the power losses driving the out-
put loads and agrees well with the above equation. This plot
can be used to approximate the power losses due to the gate
drivers.
The RT pin is biased at 3V and current limited to 1mA. It is
designed to accommodate a resistor between 5K and 100K,
resulting in an effective dead-time proportional to RT and
ranging from 90ns to 200ns. RT values below 5K will saturate
the timer and are not recommended.
Startup and UVLO
Both top and bottom drivers include under-voltage lockout
(UVLO) protection circuitry which monitors the supply voltage
(VDD) and bootstrap capacitor voltage (VHB – VHS) indepen-
dently. The UVLO circuit inhibits each driver until sufficient
supply voltage is available to turn-on the external MOSFETs,
and the built-in hysteresis prevents chattering during supply
voltage transitions. When the supply voltage is applied to
VDD pin of SM74104, the top and bottom gates are held low
until VDD exceeds UVLO threshold, typically about 6.9V. Any
UVLO condition on the bootstrap capacitor will disable only
the high side output (HO).
Gate Driver Power Dissipation (LO + HO)
VCC = 12V, Neglecting Diode Losses
LAYOUT CONSIDERATIONS
The optimum performance of high and low side gate drivers
cannot be achieved without taking due considerations during
circuit board layout. Following points are emphasized.
1. A low ESR/ESL capacitor must be connected close to the
IC, and between VDD and VSS pins and between HB and
HS pins to support high peak currents being drawn from
VDD during turn-on of the external MOSFET.
2. To prevent large voltage transients at the drain of the top
MOSFET, a low ESR electrolytic capacitor must be
connected between MOSFET drain and ground (VSS).
30160006
The bootstrap diode power loss is the sum of the forward bias
power loss that occurs while charging the bootstrap capacitor
and the reverse bias power loss that occurs during reverse
recovery. Since each of these events happens once per cycle,
3. In order to avoid large negative transients on the switch
node (HS) pin, the parasitic inductances in the source of
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10
Diode Power Dissipation VIN = 40V
the diode power loss is proportional to frequency. Larger ca-
pacitive loads require more current to recharge the bootstrap
capacitor resulting in more losses. Higher input voltages
(VIN) to the half bridge result in higher reverse recovery loss-
es. The following plot was generated based on calculations
and lab measurements of the diode recovery time and current
under several operating conditions. This can be useful for ap-
proximating the diode power dissipation.
Diode Power Dissipation VIN = 80V
30160008
The total IC power dissipation can be estimated from the
above plots by summing the gate drive losses with the boot-
strap diode losses for the intended application. Because the
diode losses can be significant, an external diode placed in
parallel with the internal bootstrap diode (refer to Figure 2)
can be helpful in removing power from the IC. For this to be
effective, the external diode must be placed close to the IC to
minimize series inductance and have a significantly lower for-
ward voltage drop than the internal diode.
30160007
30160009
FIGURE 2. SM74104 Driving MOSFETs Connected in Synchronous Buck Configuration
11
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Physical Dimensions inches (millimeters) unless otherwise noted
Notes: Unless otherwise specified
Standard lead finish to be 200 microinches/5.00 micrometers minimum tin/lead (solder) on copper.
1.
Pin 1 identification to have half of full circle option.
2.
No JEDEC registration as of Feb. 2000.
3.
LLP-10 Outline Drawing
NS Package Number SDC10A
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12
Notes: Unless otherwise specified
For solder thickness and composition, see “Solder Information” in the packaging section of the National Semiconductor web page (www.national.com).
1.
Maximum allowable metal burr on lead tips at the package edges is 76 microns.
2.
No JEDEC registration as of May 2003.
3.
SOIC-8 Outline Drawing
NS Package Number M08A
13
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Notes
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相关型号：
SM74104SD/NOPB
1.8-A, 100-V half bridge gate driver with 8-V UVLO and adaptive delay 10-WSON -40 to 125
TI
SM74104SDX/NOPB
1.8-A, 100-V half bridge gate driver with 8-V UVLO and adaptive delay 10-WSON -40 to 125
TI
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