SMJ320C30HFGM50_技术文档

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ꢇꢈ ꢉꢈ ꢊꢋꢌ ꢀꢈ ꢉ ꢍꢋꢌ ꢎꢏ ꢐ ꢆꢑ ꢀ ꢀꢐ ꢏ

SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004

2

D

−55°C to 125°C Operating Temperature

D

Two 32-Bit External Ports

(24- and 13-Bit Address)

Range, QML Processing

D

Processed to MIL-PRF-38535 (QML)

Two Serial Ports With Support for

8- / 16- /24- /32-Bit Transfers

D

Performance

− SMJ320C30-40 (50-ns Cycle)

40 MFLOPS

Packaging

− 181-Pin Grid Array Ceramic Package

(GB Suffix)

20 MIPS

− SMJ320C30-50 (40-ns Cycle)

50 MFLOPS

− 196-Pin Ceramic Quad Flatpack With

Nonconductive Tie-Bar (HFG Suffix)

25 MIPS

D

SMD Approval for 40- and 50-MHz Versions

D

Two 1K-Word × 32-Bit Single-Cycle

Dual-Access On-Chip RAM Blocks

Two Address Generators With Eight

Auxiliary Registers and Two Auxiliary

Register Arithmetic Units (ARAUs)

D

Validated Ada Compiler

64-Word × 32-Bit Instruction Cache

32-Bit Instruction and Data Words,

24-Bit Addresses

D

Zero-Overhead Loops With Single-Cycle

Branches

Interlocked Instructions for

Multiprocessing Support

40 / 32-Bit Floating-Point /Integer Multiplier

and Arithmetic Logic Unit (ALU)

D

32-Bit Barrel Shifter

Parallel ALU and Multiplier Execution in a

Single Cycle

D

Eight Extended-Precision Registers

(Accumulators)

On-Chip Direct Memory Access (DMA)

Controller for Concurrent I/O and CPU

Operation

D

Two- and Three-Operand Instructions

Conditional Calls and Returns

Block Repeat Capability

D

Integer, Floating-Point, and Logical

Operations

Fabricated Using Enhanced Performance

Implanted CMOS (EPICt) by Texas

Instruments

One 4K-Word × 32-Bit Single-Cycle

Dual-Access On-Chip ROM Block

D

Two 32-Bit Timers

description

The SMJ320C30 internal busing and special digital signal processor (DSP) instruction set has the speed and

flexibility to execute up to 50 MFLOPS. The SMJ320C30 device optimizes speed by implementing functions

in hardware that other processors implement through software or microcode. This hardware-intensive approach

provides performance previously unavailable on a single chip. The emphasis on total system cost has resulted

in a less expensive processor that can be designed into systems currently using costly bit-slice processors.

D

SMJ320C30-40: 50-ns single-cycle execution time, 5% supply

SMJ320C30-50: 40-ns single-cycle execution time, 5% supply

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

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Copyright  2004, Texas Instruments Incorporated

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1

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

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SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004

description (continued)

196-Pin HFG Quad Flatpack

(TOP VIEW)

181-Pin GB Grid Array Package

(BOTTOM VIEW)

A B C D E F G H J K L M N P R

1

2

3

4

1

147

5

DVDD DVSS

6

7

8

9

10

11

12

13

14

15

DVSS DVDD

49

99

The SMJ320C30 can perform parallel multiply and ALU operations on integer or floating-point data in a single

cycle. Each processor also possesses a general-purpose register file, a program cache, dedicated ARAUs,

internal dual-access memories, one DMA channel supporting concurrent I/O, and a short machine-cycle time.

High performance and ease of use are results of these features.

General-purpose applications are enhanced by the large address space, multiprocessor interface, internally

and externally generated wait states, two external interface ports, two timers, two serial ports, and multiple

interrupt structure. The SMJ320C30 supports a wide variety of system applications from host processor to

dedicated coprocessor.

High-level language support is implemented easily through a register-based architecture, large address space,

powerful addressing modes, flexible instruction set, and well-supported floating-point arithmetic.

For additional information when designing for cold temperature operation, please see Texas Instruments

application report 320C3x, 320C4x and 320MCM42x Power-up Sensitivity at Cold Temperature, literature

number SGUA001.

2

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SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004

functional block diagram

RAM

ROM

Cache

⁽⁶⁴× 32)

Block 0

Block 1

Block

^(1K× 32)

(1K × 32)

^(4K× 32)

32

24

32

24

32

24

32

PDATA Bus

PADDR Bus

XRDY

RDY

HOLD

MSTRB

IOSTRB

XR /W

DDATA Bus

HOLDA

STRB

DADDR1 Bus

XD31−XD0

XA12 −XA0

R / W

DADDR2 Bus

D31−D0

A23 −A0

DMADATA Bus

DMAADDR Bus

32

24

32

24

32

24

DMA Controller

Serial Port 0

Serial-Port-Control

FSX0

Global-Control

Register

DX0

MUX

CLKX0

FSR0

DR0

Receive/Transmit

IR

(R/X) Timer Register

Source-Address

Register

PC

CPU1

CPU2

REG1

REG2

RESET

INT(3 −0)

IACK

Data-Transmit

Register

CLKR0

Destination-

Address

Register

Data-Receive

Register

MC /MP

XF(1,0)

Transfer-

Counter

Register

V

DD

Serial Port 1

IODV

32

40

DD

Serial-Port-Control

Register

ADV

DD

FSX1

DX1

32-Bit

Barrel

Shifter

PDV

DD

Multiplier

DDV

DD

CLKX1

FSR1

DR1

Receive/Transmit

(R/X) Timer Register

MDV

DD

ALU

40

V

SS

Data-Transmit

Register

DV

CLKR1

SS

40

CV

SS

IV

SS

40

Extended-

Precision

Registers

(R7−R0)

40

32

Data-Receive

Register

V

BBP

V

SUBS

X1

Timer 0

X2 /CLKIN

H1

Global-Control

Register

DISP0, IR0, IR1

H3

TCLK0

Timer-Period

Register

ARAU0

ARAU1

EMU(6 −0)

RSV(10 −0)

BK

Timer-Counter

Register

24

Auxiliary

Registers

(AR0 −AR7)

Timer 1

32

Global-Control

Register

32

TCLK1

Timer-Period

Register

32

Other

Registers

(12)

Timer-Counter

Register

Port Control

Primary-Control

Register

Expansion-Control

Register

3

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SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004

memory map

Figure 1 shows the memory map for the SMJ320C30. See the TMS320C3x User’s Guide (literature number

SPRU031) for a detailed description of this memory mapping. Figure 2 shows the reset, interrupt, and trap

vector/branches memory-map locations. Figure 3 shows the peripheral bus memory-mapped registers.

0h

Reset, Interrupt, Trap

Vectors, and Reserved

Locations (64) (External

STRB Active)

Reset, Interrupt,

Trap Vectors, and Reserved

Locations (192)

0BFh

0C0h

03Fh

040h

ROM

(Internal)

0FFFh

1000h

External

STRB Active

External

STRB Active

(8M Words − 64 Words)

(8M Words − 4K Words)

7FFFFFh

800000h

7FFFFFh

800000h

Expansion-Bus

MSTRB Active

(8K Words)

Expansion-Bus

MSTRB Active

(8K Words)

801FFFh

802000h

801FFFh

802000h

Reserved

(8K Words)

803FFFh

804000h

803FFFh

804000h

Expansion-Bus

IOSTRB Active

(8K Words)

Expansion-Bus

IOSTRB Active

(8K Words)

805FFFh

806000h

805FFFh

806000h

Reserved

(8K Words)

807FFFh

808000h

807FFFh

808000h

Peripheral-Bus

Memory-Mapped

Registers

Peripheral-Bus

Memory-Mapped

Registers

(6K Words Internal)

8097FFh

809800h

8097FFh

809800h

RAM Block 0

(1K Word Internal)

809BFFh

809C00h

809BFFh

809C00h

RAM Block 1

(1K Word Internal)

809FFFh

80A000h

809FFFh

80A000h

External

STRB Active

(8M Words − 40K Words)

External

STRB Active

(8M Words − 40K Words)

0FFFFFFh

(a) Microprocessor Mode

(b) Microcomputer Mode

Figure 1. Memory Map

4

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SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004

memory map (continued)

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

Reset

INT0

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

1Fh

20h

Reset

INT0

INT1

INT2

INT3

XINT0

RINT0

XINT1

RINT1

TINT0

TINT1

DINT

XINT0

RINT0

XINT1

RINT1

TINT0

TINT1

DINT

Reserved

TRAP 0

Reserved

TRAP 0

1Fh

20h

.

3Bh

3Ch

3Fh

TRAP 27

3Bh

3Ch

BFh

TRAP 27

Reserved

(a) Microprocessor Mode

(a) Microcomputer Mode

Figure 2. Reset, Interrupt, and Trap Vector/Branches Memory-Map Locations

5

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SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004

memory map (continued)

808000h

808004h

808006h

808008h

808020h

808024h

808028h

808030h

808034h

808038h

808040h

DMA Global Control

DMA Source Address

DMA Destination Address

DMA Transfer Counter

Timer 0 Global Control

Timer 0 Counter

Timer 0 Period

Timer 1 Global Control

Timer 1 Counter

Timer 1 Period Register

Serial Port 0 Global Control

808042h

808043h

808044h

808045h

808046h

FSX/DX/CLKX Serial Port 0 Control

FSR/DR/CLKR Serial Port 0 Control

Serial Port 0 R/X Timer Control

Serial Port 0 R/X Timer Counter

Serial Port 0 R/X Timer Period

808048h

80804Ch

808050h

Serial Port 0 Data Transmit

Serial Port 0 Data Receive

Serial Port 1 Global Control

808052h

808053h

808054h

808055h

808056h

FSX/DX/CLKX Serial Port 1 Control

FSR/DR/CLKR Serial Port 1 Control

Serial Port 1 R/X Timer Control

Serial Port 1 R/X Timer Counter

Serial Port 1 R/X Timer Period

808058h

80805Ch

808060h

808064h

Serial Port 1 Data Transmit

Serial Port 1 Data Receive

Expansion-Bus Control

Primary-Bus Control

†

Shading denotes reserved address locations

†

Figure 3. Peripheral Bus Memory-Mapped Registers

6

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SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004

pin functions

This section gives signal descriptions for the SMJ320C30 devices in the microprocessor mode. The following

tables list each signal, the number of pins, type of operating mode(s) (that is, input, output, or high-impedance

state as indicated by I, O, or Z, respectively), and a brief function description. All pins labeled NC have special

functions and should not be connected by the user. A line over a signal name (for example, RESET) indicates

that the signal is active low (true at logic-0 level). The signals are grouped according to functions.

Pin Functions

CONDITIONS

WHEN

SIGNAL IS Z TYPE

†

DESCRIPTION

TYPE

‡

QTY

NAME

§

PRIMARY BUS INTERFACE

D31−D0

A23−A0

32

24

I/O/Z 32-bit data port of the primary bus interface

S

H

O/Z

I

24-bit address port of the primary bus interface

R

Read/write for primary bus interface. R/W is high when a read is performed and low

when a write is performed over the parallel interface.

R/W

STRB

RDY

1

S

H

External access strobe for the primary bus interface

Ready. RDY indicates that the external device is prepared for a primary bus interface

transaction to complete.

Hold for primary bus interface. When HOLD is a logic low, any ongoing transaction

is completed. A23−A0, D31−D0, STRB, and R/W are in the high-impedance state

and all transactions over the primary bus interface are held until HOLD becomes a

logic high or the NOHOLD bit of the primary bus control register is set.

HOLD

1

I

Hold acknowledge for primary bus interface. HOLDA is generated in response to a

logic low on HOLD. HOLDA indicates that A23−A0, D31−D0, STRB, and R/W are

in the high-impedance state and that all transactions over the bus are held. HOLDA

is high in response to a logic high of HOLD or when the NOHOLD bit of the primary

bus control register is set.

HOLDA

O/Z

S

EXPANSION BUS INTERFACE

XD31−XD0

XA12−XA0

32

13

I/O/Z 32-bit data port of the expansion bus interface

S

R

O/Z

13-bit address port of the expansion bus interface

Read/write signal for expansion bus interface. When a read is performed, XR/W is

held high; when a write is performed, XR/W is low.

XR/W

1

O/Z

S

R

MSTRB

IOSTRB

1

O/Z

External memory access strobe for the expansion bus interface

External I/O access strobe for the expansion bus interface

S

Ready signal. XRDY indicates that the external device is prepared for an expansion

bus interface transaction to complete.

XRDY

1

I

CONTROL SIGNALS

Reset. When RESET is a logic low, the device is in the reset condition. When RESET

becomes a logic high, execution begins from the location specified by the reset vector.

RESET

1

4

1

2

I

INT3−INT0

IACK

I

External interrupts

Interrupt acknowledge. IACK is set to a logic high by the IACK instruction. IACK can

be used to indicate the beginning or end of an interrupt-service routine.

O/Z

I

S

MC/MP

XF1, XF0

Microcomputer/microprocessor mode

External flags. XF1 and XF0 are used as general-purpose I/Os or to support

interlocked processor instructions.

I/O/Z

R

†

‡

§

I = input, O = output, Z = high-impedance state, NC = no connect

For GB package

S = SHZ active, H = HOLD active, R = RESET active

7

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SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004

Pin Functions (Continued)

CONDITIONS

WHEN

SIGNAL IS Z TYPE

†

DESCRIPTION

TYPE

‡

QTY

NAME

§

SERIAL PORT 0 SIGNALS

Serial port 0 transmit clock. CLKX0 is the serial-shift clock for the serial port 0

transmitter.

CLKX0

DX0

1

I/O/Z

S

R

I/O/Z Data transmit output. Serial port 0 transmits serial data on DX0.

Frame synchronization pulse for transmit. The FSX0 pulse initiates the transmit-data

process over DX0.

FSX0

I/O/Z

CLKR0

DR0

1

I/O/Z Serial port 0 receive clock. CLKR0 is the serial-shift clock for the serial port 0 receiver.

I/O/Z Data receive. Serial port 0 receives serial data on DR0.

S

R

Frame synchronization pulse for receive. The FSR0 pulse initiates the receive-data

process over DR0.

FSR0

1

I/O/Z

S

R

SERIAL PORT 1 SIGNALS

Serial port 1 transmit clock. CLKX1 is the serial-shift clock for the serial port 1

transmitter.

CLKX1

DX1

1

I/O/Z

S

R

I/O/Z Data transmit output. Serial port 1 transmits serial data on DX1.

Frame synchronization pulse for transmit. The FSX1 pulse initiates the transmit-data

process over DX1.

FSX1

I/O/Z

CLKR1

DR1

1

I/O/Z Serial port 1 receive clock. CLKR1 is the serial-shift clock for the serial port 1 receiver.

I/O/Z Data receive. Serial port 1 receives serial data on DR1.

S

R

Frame synchronization pulse for receive. The FSR1 pulse initiates the receive-data

process over DR1.

FSR1

1

I/O/Z

S

R

TIMER 0 SIGNALS

Timer clock 0. As an input, TCLK0 is used by timer 0 to count external pulses. As an

output, TCLK0 outputs pulses generated by timer 0.

TCLK0

TCLK1

I/O/Z

TIMER 1 SIGNALS

Timer clock 1. As an input, TCLK1 is used by timer 1 to count external pulses. As an

output, TCLK1 outputs pulses generated by timer 1.

I/O/Z

SUPPLY AND OSCILLATOR SIGNALS (see Note 1)

¶

V

4

2

1

2

1

4

2

I

5-V supply

Ground

DD

IODV

DD

ADV

PDV

DDV

DD

MDV

DD

V

SS

DV

CV

Ground

SS

Ground

†

‡

§

¶

I = input, O = output, Z = high-impedance state, NC = no connect

For GB package

S = SHZ active, H = HOLD active, R = RESET active

Recommended decoupling capacitor is 0.1 µF.

NOTE 1: CV , V , and IV

are on the same plane.

SS SS

SS

8

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SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004

Pin Functions (Continued)

CONDITIONS

WHEN

SIGNAL IS Z TYPE

†

DESCRIPTION

TYPE

‡

QTY

NAME

§

SUPPLY AND OSCILLATOR SIGNALS (see Note 1) (CONTINUED)

IV

1

I

NC

I

Ground

SS

V

BB

pump oscillator output

BBP

Substrate pin. Tie to ground

SUBS

Output from the internal oscillator for the crystal. If a crystal is not used, X1 must

be left unconnected.

X1

1

O

X2/CLKIN

1

I

Input to the internal oscillator from the crystal or a clock

External H1 clock. H1 has a period equal to twice CLKIN.

External H3 clock. H3 has a period equal to twice CLKIN.

RESERVED (see Note 2)

H1

H3

O/Z

S

EMU0−EMU2

EMU3

3

1

I

Reserved. Use pullup resistors to 5 V

Reserved

O/Z

S

Shutdown high impedance. When active, EMU4/SHZ shuts down the SMJ320C30

and places all pins in the high-impedance state. EMU4/SHZ is used for board-level

testing to ensure that no dual-drive conditions occur. CAUTION: A low on SHZ

corrupts SMJ320C30 memory and register contents. Reset the device with SHZ

high to restore it to a known operating condition.

EMU4/SHZ

1

I

EMU5, EMU6

RSV0−RSV4

RSV5−RSV10

Locator

2

5

6

1

NC

I

Reserved

Reserved. Tie pins directly to 5 V

Reserved. Use pullups on each pin to 5 V

Reserved

I/O

NC

†

‡

§

I = input, O = output, Z = high-impedance state, NC=No Connect

For GB package

S = SHZ active, H = HOLD active, R = RESET active

NOTES: 1. CV , V , IV

are on the same plane.

SS SS SS

2. The connections specified for the reserved pins must be followed. For best results, 18-kΩ−22-kΩ pullup resistors are

recommended. All 5-V supply pins must be connected to a common supply plane, and all ground pins must be connected to a

common ground plane.

9

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SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004

Pin Assignments

NUMBER

GB HFG

PKG PKG

139 D5

138 D6

NUMBER

GB HFG

PKG PKG

NUMBER

GB HFG

PKG PKG

NUMBER

HFG

PKG

NAME

GB

HFG

PKG PKG

NAME

GB

PKG

F15

82

A0

C5

D6

A4

B5

C6

A5

B6

D7

A6

C7

B7

A7

A8

B8

A9

B9

C9

P2

195 DX1

L2

185 RSV6

186 RSV7

R8

R9

P9

N9

29

30

31

32

XD11

XD12

XD13

XD14

XD15

XD16

XD17

XD18

XD19

XD20

XD21

XD22

XD23

XD24

XD25

XD26

XD27

XD28

XD29

XD30

XD31

G12 81

G13 80

G14 79

G15 78

A1

F14

E15

F13

E14

F12

C1

M6

B3

83

84

85

86

87

EMU0

K4

M1

L3

A2

137 D7

EMU1

187 RSV8

188 RSV9

189 RSV10

A3

136 D8

EMU2

A4

135 D9

EMU3

M2

R10 33

{

H15

H14

J15

J14

J13

K15

J12

K14

L15

K13

L14

77

72

71

70

69

68

67

66

65

63

62

A5

134 D10

133 D11

132 D12

131 D13

130 D14

129 D15

128 D16

127 D17

122 D18

121 D19

120 D20

119 D21

EMU4/SHZ

D12 100 ADV

M9

34

35

36

DD

A6

155 EMU5

11 EMU6

H11

D4

E8

64

ADV

P10

R11

A7

114 DDV

147 DDV

DD

{

A8

145 H1

N10 37

P11 38

{

A9

A1

146 H3

L8

15

IODV

DD

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

C2

B1

152 X1

M12 16

49

IODV

R12 39

M10 40

151 X2/CLKIN

{

P4

9

TCLK0

TCLK1

H5

162 MDV

163 MDV

N11

P12

41

42

DD

{

N5

G2

G3

D3

E4

10

DD

{

169 XF0

168 XF1

M4

B2

1

PDV

R13 43

R14 44

M11 45

N12 46

DD

w

51

52

25

26

172

173

28

75

CV

SS

w

M15 61

154

153

123

73

V

P14

BBP

SS

}

K12

L13

60

59

A10 118 D22

D9 117 D23

B10 116 D24

A11 115 D25

C10 113 D26

B11 112 D27

A12 111 D28

V

SUBS

DD

}

H4

D8

M8

P13

47

DD

}

M14 58

N15 57

M13 56

R15 48

DD

}

74

P15

C3

53

2

DD

}

w

H12 124

C8

H3

DV

DD

w

SS

DD

L12

N14

E5

G1

H2

H1

J1

55

54

N8

27

101 DV

SS

DD

W

A13

A14

D11

107 XA0

106 XA1

105 XA2

H13 76

125

50

DV

SS

W

LOCATOR/NC

D10 110 D29

C11 109 D30

B12 108 D31

C13 98

N3

N13 196 DV

170 IACK

171 INT0

176 INT1

177 INT2

178 INT3

126

149

150

174

175

99

148 DV

C12 104 XA3

SS

w

F3

E2

D2

D1

P3

R2

N4

M5

R1

R3

M3

P1

L4

161 HOLD

160 HOLDA

156 XRDY

159 XR/W

B13

A15

B15

103 XA4

102 XA5

B14

96

97

IV

SS

w

SS

J2

95

XA6

D15

E3

E1

F1

88

MC/MP

C14 94

E12 93

XA7

SUBS

157 MSTRB

164 RDY

167 RESET

166 R/ W

165 STRB

158 IOSTRB

144 D0

4

7

5

6

3

8

FSR0

FSX0

CLKR0

CLKX0

DR0

XA8

R4

P5

N6

R5

P6

M7

R6

N7

P7

R7

P8

12

XD0

XD1

XD2

XD3

XD4

XD5

XD6

XD7

XD8

XD9

XD10

D13 92

C15 91

D14 90

XA9

13

XA10

XA11

XA12

14

G4

F2

17

E13

J3

89

18

F4

DX0

179 RSV0

180 RSV1

181 RSV2

182 RSV3

183 RSV4

184 RSV5

19

C4

D5

A2

A3

B4

191 FSR1

194 FSX1

192 CLKR1

193 CLKX1

190 DR1

J4

20

143 D1

K1

K2

L1

21

142 D2

22

141 D3

N2

N1

23

140 D4

K3

24

†

‡

§

¶

ADV , DDV , IODV , MDV , and PDV

are on a common plane internal to the device.

DD

V

DV

is on a common plane internal to the device.

DD

, CV , and IV

SS SS SS

are on a common plane internal to the device.

is on a common plane internal to the device.

SS

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SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004

†

absolute maximum ratings over operating case temperature range (unless otherwise noted)

Supply voltage range, V

(see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V

CC

Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 7 V

I

Output voltage range, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V

O

Continuous power dissipation (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.15 W

Operating case temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 55°C to 125°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 65°C to 150°C

C

Storage temperature range, T

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 3. All voltage values are with respect to V

.

SS

4. Actual operating power is less. This value was obtained under specially produced worst-case test conditions, which are not

sustained during normal device operation. These conditions consist of continuous parallel writes of a checkerboard pattern to both

primary and extension buses at the maximum rate possible. See normal (I ) current specification in the electrical characteristics

CC

table and also read Calculation of TMS320C30 Power Dissipation Application Report (literature number SPRA020).

recommended operating conditions (see Note 5)

‡

MIN

NOM

MAX

UNIT

V

Supply voltage (AV , etc.)

DD

Supply voltage (CV , etc.)

SS

4.75

5

0

5.25

V

DD

SS

IH

High-level input voltage

2.1

3

V

+ 0.3*

V

DD

High-level input voltage for CLKIN

Low-level input voltage

+ 0.3*

0.8

V

TH

IL

DD

− 0.3*

V

I

High-level output current

− 300

2

µA

mA

°C

OH

OL

Low-level output current

T

Operating case temperature (see Note 6)

− 55

125

C

‡

All nominal values are at V

= 5 V, T (ambient-air temperature)= 25°C.

A

DD

* This parameter is not production tested.

NOTE 5: All input and output voltage levels are TTL compatible.

NOTE 6:

T

C

MAX at maximum rated operating conditions at any point on the case, T MIN at initial (time zero) power up

C

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SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004

electrical characteristics over recommended ranges of supply voltage (unless otherwise noted)

(see Note 5)

†

‡

PARAMETER

TEST CONDITIONS

MIN TYP

MAX

UNIT

V

High-level output voltage

V

= MIN,

= MAX

I

= MAX

2.4

3

OH

DD

OH

OL

For XA12−XA0

All others

0.6*

0.6

20

V

Low-level output voltage

OL

0.3

V

I

High-impedance current

Input current

µA

Z

V = V

I SS

to V

DD

10

I

Input current

Inputs with internal pullups (see Note 7)

V = V to V

− 600

20

IP

IC

Input current (X2/CLKIN)

50

I

SS DD

V

= MAX, T = 25°C,

= MIN, See Note 8

DD

A

I

Supply current

200

50

600

mA

CC

DD

t

c(CI)

I

Supply current, standby; IDLE2, clock shut off

Input capacitance

V

DD

= 5 V, T = 25°C

mA

pF

A

C

15*

20*

25*

i

Output capacitance

o

x

X2/CLKIN capacitance

†

‡

For conditions shown as MIN/MAX, use the appropriate value specified in recommended operating conditions.

All typical values are at V

= 5 V, T = 25°C.

DD

A

* This parameter is not production tested.

NOTES: 5. All input and output voltage levels are TTL compatible.

7. Pins with internal pullup devices: INT0−INT3, MC/MP, RSV0−RSV10. Although RSV0−RSV10 have internal pullup devices,

external pullups should be used on each pin as identified in the pin function tables.

8. Actual operating current is less than this maximum value. This value was obtained under specially produced worst-case test

conditions, which are not sustained during normal device operation. These conditions consist of continuous parallel writes of a

checkerboard pattern to both primary and expansion buses at the maximum rate possible. See Calculation of TMS320C30 Power

Dissipation Application Report (literature number SPRA020).

PARAMETER MEASUREMENT INFORMATION

I

OL

Output

Under

Test

Tester Pin

Electronics

V

LOAD

C

T

I

OH

Where:

I

V

= 2 mA (all outputs)

= 300 µA (all outputs)

= Selected to emulate 50 Ω termination (typical value = 1.54 V).

= 80-pF typical load-circuit capacitance

OL

OH

LOAD

T

C

Figure 4. Test Load Circuit

12

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SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004

PARAMETER MEASUREMENT INFORMATION (CONTINUED)

signal transition levels

TTL-level outputs are driven to a minimum logic-high level of 2.4 V and to a maximum logic-low level of 0.6 V.

Output transition times are specified as follows:

D

For a high-to-low transition on a TTL-compatible output signal, the level at which the output is said to be

no longer high is 2 V and the level at which the output is said to be low is 1 V.

For a low-to-high transition, the level at which the output is said to be no longer low is 1 V and the level at

which the output is said to be high is 2 V.

2.4 V

2 V

1 V

0.6 V

Figure 5. TTL-Level Outputs

Transition times for TTL-compatible inputs are specified as follows:

D

For a high-to-low transition on an input signal, the level at which the input is said to be no longer high is

2.1 V and the level at which the input is said to be low is 0.8 V.

For a low-to-high transition on an input signal, the level at which the input is said to be no longer low is

0.8 V and the level at which the input is said to be high is 2.1 V.

2.1 V

0.8 V

Figure 6. TTL-Level Inputs

13

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SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004

PARAMETER MEASUREMENT INFORMATION (CONTINUED)

timing parameter symbology

Timing parameter symbols used herein were created in accordance with JEDEC Standard 100-A. To shorten

the symbols, some of the terminal names and other related terminology have been abbreviated as follows,

unless otherwise noted:

A

A23−A0

IACK

INT

IACK

ASYNCH

Asynchronous reset signals include XF0, XF1,

CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, CLKX1,

DX1, FSX1, CLKR1, DR1, FSR1, TCLK0, and TCLK1

INT3−INT0

CH

CLKX includes CLKX0 and CLKX1

IOS

IOSTRB

CI

CLKIN

(M)S

RDY

RESET

RW

(M)STRB includes MSTRB and STRB

CONTROL

Control signals include STRB, MSTRB, and IOSTRB

RDY

D

D31−D0

RESET

R/W

DR

DX

Includes DR0, DR1

Includes DX0, DX1

S

STRB

SCK

CLKX/R includes CLKX0, CLKX1,

CLKR0, and CLKR1

FS

FSX/R includes FSX0, FSX1, FSR0, and FSR1

FSR

FSX

Includes FSR0, FSR1

Includes FSX0, FSX1

TCLK

(X)A

TCLK0, TCLK1

Includes A23−A0 and XA12−XA0

GPIO

General-purpose input/output; peripheral pins include

CLKX0/1, CLKR0/1, DX0/1, DR0/1, FSX0/1, FSR0/1,

and TCLK0/1

(X)D

Includes D31−D0 and XD31−XD0

H

Includes H1, H3

XF

XFx includes XF0 and XF1

XF0

H1

XF0

H3

XF1

HOLD

HOLDA

HOLD

HOLDA

(X)RDY

(X)RW

Includes RDY and XRDY

(X)R/W includes R/W and XR/W

14

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SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004

X2/CLKIN, H1, and H3 timing

The following table defines the timing parameters for the X2/CLKIN, H1, and H3 interface signals. See the

RESET timing in Figure 20 for CLKIN to H1 and H3 delay specification.

timing parameters for X2/CLKIN, H1, H3 (see Note 5, Figure 7, Figure 8, and Figure 9)

320C30-40

320C30-50

†

NO.

UNIT

MIN

MAX

MIN

MAX

1

2

3

4

5

6

7

8

9

t

Fall time, CLKIN

5*

ns

f(CI)

Pulse duration, CLKIN low, t

= MIN (see Note 9)

9

7

w(CIL)

w(CIH)

r(CI)

c(CI)

Pulse duration, CLKIN high, t

Rise time, CLKIN

= MIN (see Note 9)

c(CI)

5*

303

3

5*

303

3

Cycle time, CLKIN

25

20

c(CI)

Fall time, H1/H3

f(H)

Pulse duration, H1/H3 low (see Note 10)

Pulse duration, H1/H3 high (see Note 10)

Rise time, H1/H3

P − 5

P − 6

P − 5

P − 6

w(HL)

w(HH)

r(H)

3

4

3

4

9.1

10

Delay time, from H1 low to H3 high or from H3 low to H1 high

Cycle time, H1/H3

0

d(HL-HH)

c(H)

50

606

40

606

†

Numbers in this column match those used in Figure 7, Figure 8, and Figure 9.

* This parameter is not production tested.

NOTES: 5. All input and output voltage levels are TTL compatible.

9. Rise and fall times, assuming a 35 − 65% duty cycle, are incorporated within this specification (see Figure 6).

10. P = t

c(CI)

5

4

1

3

X2/CLKIN

(1.5 V)

2

Figure 7. X2/CLKIN Timing

15

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SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004

timing parameters for X2/CLKIN, H1, H3 (see Note 5, Figure 7, Figure 8, and Figure 9) (continued)

10

6

9

H1

8

7

9.1

H3

8

9

6

7

10

Figure 8. H1/H3 Timings

8

7

4.5 V Band

6

5

4

3

5.5 V Band

2

1

0

−60

−40

−20

0

20

40

60

80

100

120

140

Temperature − Degrees C

Figure 9. CLKIN to H1/H3 as a Function of Temperature

(Typical)

16

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SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004

memory read/write timing

The following table defines memory read/write timing parameters for (M)STRB.

timing parameters for a memory [(M)STRB = 0] read/write (see Figure 10 and Figure 11)

320C30-40

320C30-50

†

NO.

UNIT

MIN MAX

11

12

t

Delay time, H1 low to (M)STRB low

Delay time, H1 low to (M)STRB high

Delay time, H1 high to R/W low

0*

14

16

0*

8

10

6

0*

10

14

0*

6

4

ns

d[H1L-(M)SL]

d[H1L-(M)SH]

d(H1H-RWL)

d[H1H-(X)RWL]

d(H1L-A)

13.1

13.2

14.1

14.2

15.1

15.2

16

9

7

Delay time, H1 high to (X)R/W low

Delay time, H1 low to A valid

13

11

9

11

9

Delay time, H1 low to (X)A valid

8

d[H1L-(X)A]

Setup time, D valid before H1 low (read)

Setup time, (X)D before H1 low (read)

Hold time, (X)D after H1 low (read)

su(D-H1L)R

su[(X)DR-H1L]R

h[H1L-(X)D]R

su(RDY-H1H)

su[(X)RDY-H1H]

h[H1H-(X)RDY]

d[H1H-(X)RWH]W

v[H1L(X)D]W

h[H1H-(X)D]W

d(H1H-A)

17.1

17.2

18

Setup time, RDY before H1 high

Setup time, (X)RDY before H1 high

Hold time, (X)RDY after H1 high

9

8

0

19

Delay time, H1 high to (X)R/W high (write)

Valid time, (X)D after H1 low (write)

Hold time, (X)D after H1 high (write)

Delay time, H1 high to A valid on back-to-back write cycles (write)

Delay time, H1 high to (X)A valid on back-to-back write cycles (write)

Delay time, (X)RDY from A valid

9

7

20

17

14

21

0*

22.1

22.2

26

15

21

7*

12

18

6*

d[H1H-(X)A]

d[A-(X)RDY]

†

Numbers in this column match those used in Figure 10 and Figure 11.

* This parameter is not production tested.

17

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SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004

memory read/write timing (continued)

H3

H1

11

12

(M)STRB

(see Note A)

(X)R/W

(X)A

14.1/14.2

13.1/13.2

15.1/15.2

16

26

(X)D

17.1/17.2

18

(X)RDY

NOTE A: (M)STRB remains low during back-to-back read operations.

Figure 10. Timing for Memory [(M)STRB = 0] Read

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SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004

memory read/write timing (continued)

H3

H1

12

11

(M)STRB

19

13.1/13.2

(X)R/W

14.1/14.2

22.1/22.2

(X)A

20

21

(X)D

18

26

17.1/17.2

(X)RDY

Figure 11. Timing for Memory [(M)STRB = 0] Write

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SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004

memory read/write timing (continued)

The following table defines memory read timing parameters for IOSTRB.

timing parameters for a memory (IOSTRB = 0) read (see Figure 12)

320C30-40

320C30-50

†

NO.

UNIT

MIN MAX

27

28

29

30

31

32

33

34

t

Delay time, H1 high to IOSTRB low

Delay time, H1 high to IOSTRB high

Delay time, H1 low to (X)R/W high

Delay time, H1 low to (X)A valid

Setup time, (X)D before H1 high

Hold time, (X)D after H1 high

0*

13

0*

9

0*

11

0*

8

ns

d(H1H-IOSL)

d(H1H-IOSH)

d[H1L-(X)RWH]

d[H1L-(X)A]

su[(X)D-H1H]R

h[H1H-(X)D]R

su[(X)RDY-H1H]

h[H1H-(X)RDY]

Setup time, (X)RDY before H1 high

Hold time, (X)RDY after H1 high

0

†

Numbers in this column match those used in Figure 12.

* This parameter is not production tested.

H3

H1

28

27

IOSTRB

(X)R/W

29

30

(X)A

(X)D

31

32

33

34

(X)RDY

Figure 12. Timing for Memory (IOSTRB = 0) Read

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SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004

memory read/write timing (continued)

The following table defines memory write timing parameters for IOSTRB.

timing parameters for a memory (IOSTRB = 0) write (see Figure 13)

320C30-40

320C30-50

†

NO.

UNIT

MIN

0*

9

MAX

MIN

0*

8

MAX

27

28

29

30

33

34

t

Delay time, H1 high to IOSTRB low

Delay time, H1 high to IOSTRB high

Delay time, H1 low to (X)R/W high

Delay time, H1 low to (X)A valid

Setup time, (X)RDY before H1 high

Hold time, (X)RDY after H1 high

9

8

ns

d(H1H-IOSL)

d(H1H-IOSH)

d[H1L-(X)RWH]

d[H1L-(X)A]

su[(X)RDY-H1H]

h[H1H-(X)RDY]

0

35

36

37

t

Delay time, H1 low to XR/W low

Valid time, (X)D after H1 high

Hold time, (X)D after H1 low

0*

13

25

0*

11

20

ns

d(H1L-XRWL)

v[H1H(X)D]W

h[H1L-(X)D]W

0

†

Numbers in this column match those used in Figure 13.

* This parameter is not production tested.

H3

H1

27

28

IOSTRB

(X)R/W

29

35

30

(X)A

(X)D

37

36

33

34

(X)RDY

Figure 13. Timing for Memory (IOSTRB = 0) Write

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SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004

XF0 and XF1 timing when executing LDFI or LDII

The following table defines the timing parameters for XF0 and XF1 during execution of LDFI or LDII.

timing parameters for XF0 and XF1 when executing LDFI or LDII (see Figure 14)

320C30-40

320C30-50

†

NO.

UNIT

MIN

MAX

13

MIN

MAX

12

38

39

40

t

Delay time, H3 high to XF0 low

Setup time, XF1 valid before H1 low

Hold time, XF1 after H1 low

ns

d(H3H-XF0L)

su(XF1-H1L)

h(H1L-XF1)

9

0

9

0

†

Numbers in this column match those used in Figure 14.

Fetch

LDFI or LDII

Decode

Read

Execute

H3

H1

(M)STRB

(X)R/W

(X)A

(X)D

(X)RDY

38

39

XF0

XF1

40

Figure 14. Timing for XF0 and XF1 When Executing LDFI or LDII

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SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004

XF0 timing when executing STFI and STII

The following table defines the timing parameters for the XF0 pin during execution of STFI or STII.

timing parameters for XF0 when executing STFI or STII (see Figure 15)

320C30-40

MIN MAX

13

320C30-50

MIN MAX

12

†

NO.

UNIT

41

t

Delay time, H3 high to XF0 high

ns

d(H3H-XF0H)

†

The number in this column matches that used in Figure 15.

Fetch

STFI or STII

Decode

Read

Execute

H3

H1

(M)STRB

(X)R/W

(X)A

(X)D

(X)RDY

XF0

41

Figure 15. Timing for XF0 When Executing an STFI or STII

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SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004

XF0 and XF1 timing when executing SIGI

The following table defines the timing parameters for the XF0 and XF1 pins during execution of SIGI.

timing parameters for XF0 and XF1 when executing SIGI (see Figure 16)

320C30-40

320C30-50

†

NO.

UNIT

MIN

MAX

MIN

MAX

41.1

42

t

Delay time, H3 high to XF0 low

Delay time, H3 high to XF0 high

Setup time, XF1 valid before H1 low

Hold time, XF1 after H1 low

13

12

ns

d(H3H-XF0L)

d(H3H-XF0H)

su(XF1-H1L)

h(H1L-XF1)

43

9

0

9

0

44

†

Numbers in this column match those used in Figure 16.

Fetch

SIGI

Decode

Read

Execute

H3

H1

41.1

43

42

XF0

44

XF1

Figure 16. Timing for XF0 and XF1 When Executing SIGI

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SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004

loading when XFx is configured as an output

The following table defines the timing parameter for loading the XF register when the XFx pin is configured as

an output.

timing parameters for loading the XFx register when configured as an output pin (see Figure 17)

320C30-40

320C30-50

MIN MAX

12

†

NO.

UNIT

MIN

MAX

13

45

t

Valid time, H3 high to XF valid

ns

v(H3H-XF)

†

The number in this column matches that used in Figure 17.

Fetch Load

Instruction

Decode

Read

Execute

H3

H1

1 or 0

45

OUTXF Bit

XFx

NOTE A: OUTXFx represents either bit 2 or 6 of the IOF register.

Figure 17. Timing for Loading XFx Register When Configured as an Output Pin

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SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004

changing XFx from an output to an input

The following table defines the timing parameters for changing the XFx pin from an output pin to an input pin.

timing parameters of XFx changing from output to input mode (see Figure 18)

320C30-40

320C30-50

†

NO.

UNIT

MIN

MAX

MIN

MAX

12*

46

47

48

t

Delay time, XFx after H3 high

Setup time, XFx before H1 low

Hold time, XFx after H1 low

13*

ns

d(H3H-XFx)

su(XFx-H1L)

h(H1L-XFx)

9

0

9

0

†

Numbers in this column match those used in Figure 18.

* This parameter is not production tested.

Value on

Terminal

Seen in IOF

Buffers Go

From Output

to Input

Execute

Load of IOF

Synchronizer

Delay

H3

H1

47

48

I/OXFx Bit

(see Note A)

46

XFx

Output

INXFx Bit

(see Note A)

Data

Sampled

Data

Seen

NOTE A: I/OXFx represents either bit 1 or bit 5 of the IOF register, and INXFx represents either bit 3 or bit 7 of the IOF register depending on

whether XF0 or XF1, respectively, is being affected.

Figure 18. Timing for Change of XFx From Output to Input Mode

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SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004

changing XFx from an input to an output

The following table defines the timing parameter for changing the XFx pin from an input pin to an output pin.

timing parameters of XFx changing from input to output mode (see Figure 19)

320C30-40

MIN MAX

17

320C30-50

MIN MAX

17

†

NO.

UNIT

49

t

Delay time, H3 high to XF switching from input to output

ns

d(H3H-XFIO)

†

The number in this column matches that used in Figure 19.

Execution of

Load of IOF

H3

H1

I/OXFx Bit

(see Note A)

49

XFx

(see Note A)

NOTE A: I/OXFx represents either bit 1 or bit 5 of the IOF register, and INXFx represents either bit 3 or bit 7 of the IOF register depending on

whether XF0 or XF1, respectively, is being affected.

Figure 19. Timing for Change of XFx From Input to Output Mode

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SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004

reset timing

RESET is an asynchronous input that can be asserted at any time during a clock cycle. If the specified timings

are met, the exact sequence shown in Figure 20 occurs; otherwise, an additional delay of one clock cycle can

occur. R/W and XR/W are in the high-impedance state during reset and can be provided with a resistive pullup,

nominally 18 kΩ to 22 kΩ, to prevent spurious writes from occurring. The asynchronous reset signals include

XF0/1, CLKX0/1, DX0/1, FSX0/1, CLKR0/1, DR0/1, FSR0/1, and TCLK0/1. HOLD is an asynchronous input and

can be asserted during reset.

Resetting the device initializes the primary- and expansion-bus control registers to seven software wait states

and, therefore, results in slow external accesses until these registers are initialized.

timing parameters for RESET [P = t

] (see Figure 9 and Figure 20)

c(CI)

320C30-40

320C30-50

NO.

UNIT

MIN

10

2

MAX

P*

MIN

10

2

MAX

50

51

52

t

Setup time, RESET before CLKIN low

P*

10

ns

su(RESET)

†

Delay time, CLKIN high to H1 high

14

d(CLKINH-H1H)

d(CLKINH-H1L)

†

Delay time, CLKIN high to H1 low

2

14

2

Setup time, RESET high beforeH1 low after ten H1 clock

cycles

53

t

9

7

ns

su(RESETH-H1L)

†

54

55

56

57

58

59

t

Delay time, CLKIN high to H3 low

2

14

15*

9*

2

10

12*

8*

ns

d(CLKINH-H3L)

d(CLKINH-H3H)

dis(H1H-XD)

†

Delay time, CLKIN high to H3 high

Disable time, H1 high to (X)D high-impedance state

Disable time, H3 high to (X)A high-impedance state

Delay time, H3 high to control signals high

Delay time, H1 high to IACK high

dis(H3H-XA)

9*

8*

d(H3H-CONTROLH)

d(H1H-IACKH)

9*

8*

Disable time, RESET low to asynchronous reset signals in

the high-impedance state

60

t

21*

17*

ns

dis(RESETL-ASYNCH)

†

See Figure 9 for temperature dependence for the 40-MHz SMJ320C30.

* This parameter is not production tested.

28

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SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004

reset timing (continued)

CLKIN

50

RESET

51

53

52

H1

54

H3

Ten H1 Clock Cycles

56

(X)D

(see Note A)

57

58

55

(X)A

(see Note B)

Control Signals

(see Note C)

59

IACK

60

Asynchronous

Reset Signals

(see Note D)

NOTES: A. In this diagram X(D) includes D31−D0 and XD31−XD0.

B. In this diagram, (X)A includes A23−A0 and XA12−XA0.

C. Control signals include STRB, MSTRB, and IOSTRB.

D. Asynchronous reset signals include XF1, XF0, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, CLKX1, DX1, FSX1, CLKR1, DR1, FSR1,

TCLK0, and TCLK1.

E. In microprocessor mode, the reset vector is fetched twice, with seven software wait states each time. In micromputer mode, the reset

vector is fetched twice, with no software wait states.

Figure 20. Timing for Reset [P=t

]

c(Cl)

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SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004

interrupt-response timing

The following table defines the timing parameters for the INT signals.

timing parameters for INT3−INT0 [Q = t

] (see Figure 21)

c(H)

320C30-40

320C30-50

NO.

UNIT

MIN

13

MAX

MIN

10

MAX

61

62

t

Setup time, INT3−INT0 before H1 low

ns

su(INT)

Pulse duration, INT3−INT0, to assure only one interrupt seen

Q

< 2Q*

Q

< 2Q*

w(INT)

* This parameter is not production tested.

The interrupt (INT) pins are asynchronous inputs that can be asserted at any time during a clock cycle. The

SMJ320C30 interrupts are level-sensitive, not edge-sensitive. Interrupts are detected on the falling edge of H1.

Therefore, interrupts must be set up and held to the falling edge of H1 for proper detection. The CPU and DMA

respond to detected interrupts on instruction-fetch boundaries only.

For the processor to recognize only one interrupt on a given input, an interrupt pulse must be set up and held

to:

D

A minimum of one H1 falling edge

No more than two H1 falling edges

The SMJ320C30 can accept an interrupt from the same source every two H1 clock cycles.

If the specified timings are met, the exact sequence shown in Figure 21 occurs; otherwise, an additional delay

of one clock cycle is possible.

Reset or

Fetch First

Instruction of

Service Routine

Interrupt

Vector

Read

H3

H1

61

INT3−INT0

Pins

62

First

Instruction

Address

INT3−INT0

Flag

Vector Address

Addr

Data

Figure 21. Timing for INT3−INT0 Response [Q=t

]

c(H)

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SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004

interrupt-acknowledge timing

The IACK output goes active on the first half-cycle (H1 rising) of the decode phase of the IACK instruction and

goes inactive at the first half-cycle (H1 rising) of the read phase of the IACK instruction.

The following table defines the timing parameters for the IACK signal.

timing parameters for IACK (see Figure 22)

320C30-40

MIN MAX

320C30-50

MIN MAX

†

NO.

UNIT

63

64

t

Delay time, H1 high to IACK low

Delay time, H1 high to IACK high

9

7

ns

d(H1H-IACKL)

d(H1H-IACKH)

†

Numbers in this column match those used in Figure 22.

Fetch IACK

Instruction

IACK

Data Read

H3

H1

63

64

IACK

Address

Data

Figure 22. Timing for Interrupt-Acknowledge (IACK)

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SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004

serial-port timing parameters (see Figure 23 and Figure 24)

320C30-40

320C30-50

CLOCK

SOURCE

NO.

UNIT

MIN

MAX

MIN

MAX

Delay time, H1 high to

internal CLKX/R

65

t

13

10

ns

d(H1-SCK)

CLKX/R ext

t

× 2.5*

t

× 2.6*

Cycle time,

CLKX/R

c(H)

66

67

ns

c(SCK)

32

× 2

32

× 2 *

CLKX/R int

CLKX/R ext

t

× 2

t

*

t

× 2

t

c(H)

Pulse

t

+12*

t

+10*

c(H)

duration,

CLKX /R

high/low

t

w(SCK)

CLKX/R int

[t

/2]−15

[t

/ 2]+5

[t

/2]−5

[t

/ 2]+5

c(SCK)

68

69

t

Rise time, CLKX/R

Fall time, CLKX/R

7*

6*

ns

r(SCK)

f(SCK)

Delay time,

CLKX to DX

valid

CLKX ext

CLKX int

CLKR ext

CLKR int

CLKR ext

CLKR int

30

17

24

16

70

71

72

t

ns

d(DX)

Setup time,

DR before

CLKR low

9

21

9

17

7

t

su(DR)

Hold time,

DR from

CLKR low

h(DR)

0

Delay time,

CLKX to

internal FSX

high/low

CLKX ext

CLKX int

27

15

22

15

73

74

75

t

ns

d(FSX)

su(FSR)

h(FS)

Setup time,

FSR before

CLKR low

CLKR ext

CLKR int

9

7

Hold time,

FSX/R input

from

CLKX/R ext

CLKX/R int

CLKX ext

9

0

7

0

CLKX/R low

Setup time,

external FSX

before CLKX

high

−[t

c(H)

− 8]

[t

/ 2]−10*

−[t

c(H)

− 8]

[t

/ 2]−10*

c(SCK)

76

77

t

ns

su(FSX)

CLKX int

−[t

c(H)

−21]

t

/2*

−[t

c(H)

−21]

t

/2*

c(SCK)

30

c(SCK)

Delay time,

CLKX to first

DX bit, FSX

precedes

CLKX ext

CLKX int

24

t

d(CH-DX)V

18

30

14

24

CLKX high

Delay time, FSX to first DX

bit, CLKX precedes FSX

78

79

t

ns

d(FSX-DX)V

Delay time, CLKX high to DX

high impedance following last

data bit

17*

14*

dDXZ

* This parameter is not production tested.

32

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SOURCED FROM: SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004

serial-port timing parameters (continued)

Unless otherwise indicated, the data-rate timings shown in Figure 23 and Figure 24 are valid for all serial-port

modes, including handshake. See serial-port timing parameter tables.

Timing diagrams shown in Figure 23 and Figure 24 show operations with the serial port global-control register

bits CLKXP = CLKRP = FSXP = FSRP = 0.

Timing diagrams shown in Figure 23 and Figure 24 depend upon the length of the serial-port word, n, where

n = 8, 16, 24, or 32 bits, respectively.

66

65

H1

65

67

CLKX/R

69

68

72

79

70

Bit n − 1

71

Bit n − 2

Bit 0

DX

DR

Bit n − 1

Bit n − 2

FSR

74

73

FSX (int)

FSX (ext)

75

76

Figure 23. Serial-Port Timing for Fixed-Data-Rate Mode

CLKX/R

73

FSX (int)

FSX (ext)

78

76

77

70

79

Bit n − 1

75

Bit n − 2

Bit n − 3

Bit 0

DX

FSR

68

DR

Bit n − 1

Bit n − 2

Bit n − 3

71

72

NOTE A: Timings not expressly specified for variable-data-rate mode are the same as those for fixed-data-rate mode.

Figure 24. Serial-Port Timing for Variable-Data-Rate Mode

33

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SOURCED FROM: SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004

HOLD timing

HOLD is an asynchronous input that can be asserted at any time during a clock cycle. If the specified timings

are met, the exact sequence shown in Figure 25 occurs; otherwise, an additional delay of one clock cycle is

possible.

The “timing parameters for HOLD/HOLDA” table defines the timing parameters for the HOLD and HOLDA

signals.

The NOHOLD bit of the primary bus control register overrides the HOLD signal. When this bit is set, the device

comes out of hold and prevents future hold cycles.

Asserting HOLD prevents the processor from accessing the primary bus. Program execution continues until a

read from or a write to the primary bus is requested. In certain circumstances, the first write is pending, allowing

the processor to continue until a second write is encountered.

HOLD/HOLDA timing (see Figure 25)

320C30-40

320C30-50

†

NO.

UNIT

MIN

13

MAX

MIN

10

MAX

80

81

82

83

84

85

86

87

88

89

90

91

t

Setup time, HOLD before H1 low

ns

su(HOLD)

v(HOLDA)

w(HOLD)

Valid time, HOLDA after H1 low

0*

9

0*

7

Pulse duration, HOLD low

2t

c(H)

2t

c(H)

Pulse duration, HOLDA low

t

−5*

t

−5*

w(HOLDA)

d(H1L-SH)H

dis(H1L-S)

en(H1L-S)

dis(H1L-RW)

en(H1L-RW)

dis(H1L-A)

en(H1L-A)

dis(H1H-D)

c(H)

7

Delay time, H1 low to STRB high for a HOLD

Disable time, H1 low to STRB high impedance

Enable time, H1 low to STRB active

Disable time, H1 low to R/W high impedance

Enable time, H1 low to R/W active

Disable time, H1 low to address high impedance

Enable time, H1 low to address valid

Disable time, H1 high to data high impedance

0*

9*

0*

*

8

7

8

7

8

0*

9*

13*

12*

8

*

†

Numbers in this column are used in Figure 25.

* This parameter is not production tested.

34

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SOURCED FROM: SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004

HOLD/HOLDA timing (continued)

H3

H1

80

82

HOLD

81

83

HOLDA

(see Note A)

84

85

86

(M)STRB

and

STRB

88

90

87

89

R/W

A

91

D

Write Data

NOTE A: HOLDA goes low in response to HOLD going low and continues to remain low through one H1 cycle after HOLD returns to high.

Figure 25. Timing for HOLD/HOLDA

35

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SOURCED FROM: SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004

general-purpose I/O timing

Peripheral pins include CLKX0/1, CLKR0/1, DX0/1, DR0/1, FSX0/1, FSR0/1, and TCLK0/1. The contents of the

internal-control registers associated with each peripheral define the modes for these pins.

peripheral pin I/O timing

The following table defines peripheral pin general-purpose I/O timing parameters.

timing parameters for peripheral pin general-purpose I/O (see Note 11 and Figure 26)

320C30-40

320C30-50

†

NO.

UNIT

MIN

10*

0*

MAX

MIN

9*

MAX

92

93

94

t

Setup time, general-purpose input before H1 low

Hold time, general-purpose input after H1 low

Delay time, general-purpose output after H1 high

ns

su(GPIOH1L)

h(GPIOH1L)

d(GPIOH1H)

0*

13*

10*

†

Numbers in this column are used in Figure 26.

* This parameter is not production tested.

NOTE 11: Peripheral pins include CLKX0/1, CLKR0/1, DX0/1, DR0/1, FSX0/1, FSR0/1, and TCLK0/1. The modes of these pins are defined

by the contents of internal control registers associated with each peripheral.

H3

H1

94

93

94

92

Peripheral

Figure 26. Timing for Peripheral Pin General-Purpose I/O

36

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SOURCED FROM: SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004

changing the peripheral pin I/O modes

The following tables show the timing parameters for changing the peripheral pin from a general-purpose output

pin to a general-purpose input pin and the reverse.

timing parameters for peripheral pin changing from general-purpose output to input mode

(see Note 12 and Figure 27)

320C30-40

320C30-50

†

NO.

UNIT

MIN

MAX

MIN

MAX

95

96

97

t

Hold time after H1 high

13

10

ns

h(H1H)

Setup time, peripheral pin before H1 low

Hold time, peripheral pin after H1 low

9

0

9

0

su(GPIOH1L)

h(GPIOH1L)

†

Numbers in this column are used in Figure 27.

NOTE 12: Peripheral pins include CLKX0/1, CLKR0/1, DX0/1, DR0/1, FSX0/1, FSR0/1, and TCLK0/1. The modes of these pins are defined

by the contents of internal control registers associated with each peripheral.

Execute Store

of Peripheral

Control

Value on

Terminal Seen in

Peripheral

Buffers Go

From Output to

Input

Synchronizer Delay

Register

Control Register

H3

H1

96

I/O

Control Bit

97

95

Peripheral

Output

Data Bit

Data Sampled

Data

Seen

Figure 27. Timing for Change of Peripheral Pin From General-Purpose Output to Input Mode

37

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SOURCED FROM: SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004

timing parameters for peripheral pin changing from general-purpose input to output mode

(see Figure 28)

320C30-40

320C30-50

NO.

UNIT

MIN

MAX

MIN

MAX

98

t

Delay time, H1 high to peripheral pin switching from input to output

13

10

ns

d(GPIOH1H)

Execution of Store of

Peripheral Control

Register

H3

H1

I/O

Control

Bit

98

Peripheral

Figure 28. Timing for Change of Peripheral Pin From General-Purpose Input to Output Mode

38

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SOURCED FROM: SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004

timer pin (TCLK0 and TCLK1) timing

Valid logic-level periods and polarity are specified by the contents of the internal control registers.

The following table defines the timing parameters for the timer pin.

timing parameters for timer pin (TCLK0 and TCLK1) (see Figure 29)

‡

320C30-40

320C30-50

NO.

UNIT

MIN

MAX

MIN

MAX

Setup time,

TCLK ext

before H1 low

99

t

TCLK ext

10

0

8

0

ns

su(TCLK-H1L)

h(TCLK-H1L)

d(TCLK-H1H)

Hold time,

TCLK ext after TCLK ext

H1 low

100

101

ns

Delay time, H1

high to TCLK

int valid

TCLK int

9

TCLK ext

TCLK int

TCLK ext

TCLK int

t

× 2.6*

t

× 2.6*

ns

c(H)

Cycle time,

TCLK

102

103

t

c(TCLK)

32

× 2

32

× 2 *

t

× 2

t

*

t

× 2

t

c(H)

t

+ 12*

t

+ 10*

c(H)

Pulse duration,

TCLK high/low

w(TCLK)

[t

c(TCLK)

/2]−5 [t

/2]+5

[t

c(TCLK)

/2]−5 [t

/2]+5

c(TCLK)

†

‡

Numbers in this column are used in Figure 29.

Timing parameters 99 and 100 are applicable for a synchronous input clock. Timing parameters 102 and 103 are applicable for an asynchronous

input clock.

* This parameter is not production tested.

H3

H1

100

101

103

101

99

Timer

102

NOTE A: Period and polarity of valid logic level are specified by contents of internal control registers.

Figure 29. Timing for Timer Pin

39

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SOURCED FROM: SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004

SHZ pin timing

The following table defines the timing parameter for the SHZ pin.

timing parameters for SHZ pin (see Figure 30)

320C30-40

320C30-50

†

NO.

UNIT

MIN

MAX

104

105

t

Disable time, SHZ low to all O, I/O high impedance

Enable time, SHZ high to all O, I/O active

0* 3P + 15*

ns

dis(SHZ)

0*

2P*

en(SHZ)

†

Numbers in this column are used in Figure 30.

* This parameter is not production tested.

H3

H1

1.5

SHZ

(see

Note A)

104

105

All I/Os

NOTE A: Enabling SHZ destroys SMJ320C30 register and memory contents. Assert SHZ and reset the SMJ320C30 to restore it to a known

condition.

Figure 30. Timing for SHZ

40

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SOURCED FROM: SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004

SMJ320C30 part order information

POWER

SUPPLY

OPERATING

FREQUENCY

PROCESSING

LEVEL

DEVICE

TECHNOLOGY

PACKAGE TYPE

Ceramic 181-pin PGA

SMJ320C30GBM40

SM320C30GBM40

0.7-µm CMOS

5 V 5%

40 MHz

QML

40 MHz

Ceramic 181-pin PGA

Standard

Ceramic 196-pin quad flatpack with

nonconductive tie bar

SMJ320C30HFGM40

0.7-µm CMOS

5 V 5%

40 MHz

QML

Ceramic 196-pin quad flatpack with

nonconductive tie bar

SM320C30HFGM40

5962−9052604MXA

5962−9052604MUA

0.7-µm CMOS

5 V 5%

40 MHz

Standard

DESC SMD

Ceramic 181-pin PGA

Ceramic 196-pin quad flatpack with

nonconductive tie bar

SMJ320C30GBM50

SM320C30GBM50

0.7-µm CMOS

5 V 5%

50 MHz

Ceramic 181-pin PGA

QML

Standard

Ceramic 196-pin quad flatpack with

nonconductive tie bar

SMJ320C30HFGM50

0.7-µm CMOS

5 V 5%

50 MHz

QML

Ceramic 196-pin quad flatpack with

nonconductive tie bar

SM320C30HFGM50

5962−9052605MXA

5962−9052605MUA

0.7-µm CMOS

5 V 5%

50 MHz

Standard

DESC SMD

Ceramic 181-pin PGA

Ceramic 196-pin quad flatpack with

nonconductive tie bar

SMJ

320

C

30

GB

M

40

SPEED RANGE

PREFIX

40

50

=

40 MHz

50 MHz

SMJ = MIL-STD-38535 (QML)

SM Standard Processing

=

TEMPERATURE RANGE

DEVICE FAMILY

320 SMJ320 Family

M = − 55°C to125°C

=

L =

0°C to 70°C

PACKAGE TYPE

TECHNOLOGY

C = CMOS

GB

=

181-Pin Grid Array (PGA) Ceramic

Package

HFG

KGD

196-Pin Ceramic Quad Flatpack with a

nonconductive tie bar

Known Good Die

DEVICE

30 = 320C30

Figure 31. SMJ320C30 Device Nomenclature

41

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SOURCED FROM: SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004

MECHANICAL DATA

HFG (S-CQFP-F196)

CERAMIC QUAD FLATPACK WITH TIE BAR

1.365 (34,67)

1.325 (33,66)

Thermal Resistance Characteristics

PARAMETER

°C/W

28.9

1.3

1.200 (30,48) TYP

0.600 (15,20) TYP

R

θJA

“A”

0.225 (5,72)

0.175 (4,45)

R

θJC

Tie Bar Width

49

1

50

196

2.505 (63,63)

2.485 (63,12)

1.710 (43,43)

1.690 (42,93)

98

148

99

147

“C”

1.150 (29,21)

8 Places

“B”

0.061 (1,55)

DIA 4 Places

0.059 (1,50)

0.105 (2,67) MAX

0.018 (0,46) MAX

0.010 (0,25)

0.006 (0,15)

196 ꢀ

Braze

0.014 (0,36)

0.002 (0,05)

0.040 (1,02)

0.030 (0,76)

0.008 (0,20)

0.004 (0,10)

0.020 (0,51) MAX

DETAIL “B”

0.025 (0,64)

DETAIL “A”

0.130 (3,30) MAX

DETAIL “C”

4040231-6/F 04/96

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Ceramic quad flatpack with flat leads brazed to nonconductive tie-bar carrier

D. This package can be hermetically sealed with a metal lid.

E. The terminals will be gold plated.

F. Falls within JEDEC MO-113 AB

The above data applies to the SMJ320C30 196-pin QFP.

42

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

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SOURCED FROM: SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004

MECHANICAL DATA (CONTINUED)

GA-GB (S-CPGA-P15 X 15)

CERAMIC PIN GRID ARRAY PACKAGE

A or A1 SQ

1.400 (35,56) TYP

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

DIM

A

MIN

MAX

Notes

Large

Outline

1.540 (39,12)

1.480 (37,59)

0.110 (2,79)

0.095 (2,41)

0.040 (1,02)

0.025 (0,63)

1.590 (40,38)

1.535 (38,99)

0.205 (5,21)

0.060 (1,52)

B or B1

Small

Outline

A1

B

Cavity

Up

Cavity

Down

B1

C

C or C1

Cavity

Up

0.140 (3,56)

0.120 (3,05)

0.050 (1,27) DIA

4 Places

Cavity

Down

C1

0.100 (2,54)

0.022 (0,55)

DIA TYP

MAXIMUM PINS WITHIN MATRIX − 225

0.016 (0,41)

4040114-8/C 04/96

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Index mark may appear on top or bottom depending on package vendor.

D. Pins are located within 0.010 (0,25) diameter of true position relative to each other at maximum material condition and within

0.030 (0,76) diameter relative to the edges of the ceramic.

E. This package can be hermetically sealed with metal lids or with ceramic lids using glass frit.

F. The pins can be gold plated or solder dipped.

G. Falls within MIL-STD-1835 CMGA7-PN and CMGA19-PN and JEDEC MO-067AG and MO-066AG, respectively

Thermal Resistance Characteristics

PARAMETER

°C/W

26.6

1.1

R

θJA

R

θJC

The above data applies to the SMJ320C30 181-pin PGA.

43

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

PACKAGE OPTION ADDENDUM

www.ti.com

2-May-2005

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

HFG

GB

5962-9052604MUA

5962-9052604MXA

5962-9052604Q9A

5962-9052605MUA

5962-9052605MXA

5962-9052605QXC

SM320C30GBM40

SM320C30GBM50

SM320C30HFGM40

SM320C30HFGM50

SMJ320C30GBM40

SMJ320C30GBM50

SMJ320C30HFGM40

SMJ320C30HFGM50

ACTIVE

CFP

196

181

0

1

TBD

Call TI

Level-NC-NC-NC

Call TI

CPGA

OBSOLETE XCEPT

KGD

HFG

GB

ACTIVE

CFP

CPGA

CFP

196

181

196

181

196

4

1

4

Level-NC-NC-NC

GB

HFG

GB

CFP

CPGA

CFP

GB

HFG

CFP

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan

-

The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS

&

no Sb/Br)

-

please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

MECHANICAL DATA

MCFP023C – JANUARY 1995 – REVISED JUNE 1999

HFG (S-CQFP-F196)

CERAMIC QUAD FLATPACK WITH NCTB

1.365 (34,67)

1.335 (33,91)

SQ

0.225 (5,72)

0.175 (4,45)

”A”

Tie Bar Width

1.200 (30,48)

BSC

49

1

50

196

1.710 (43,43)

1.690 (42,93)

2.505 (63,63)

2.485 (63,12)

98

148

99

147

”C”

1.150 (29,21)

BSC 8 Places

”B”

0.061 (1,55)

DIA 4 Places

0.059 (1,50)

0.105 (2,67) MAX

0.018 (0,46) MAX

0.013 (0,33)

0.007 (0,18)

196 X

Braze

0.014 (0,36)

0.002 (0,05)

0.040 (1,02)

0.030 (0,76)

0.009 (0,23)

0.004 (0,10)

0.020 (0,51) MAX

DETAIL ”B”

0.130 (3,30) MAX

0.025 (0,64)

DETAIL ”A”

DETAIL ”C”

4040231-6/J 01/99

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Ceramic quad flatpack with flat leads brazed to non-conductive tie bar carrier

D. This package is hermetically sealed with a metal lid.

E. The leads are gold-plated and can be solder-dipped.

F. Leads not shown for clarity purposes

G. Falls within JEDEC MO-113AB

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MCPG014A – FEBRUARY 1996 – REVISED JANUARY 2002

GB (S-CPGA-P181)

CERAMIC PIN GRID ARRAY

1.590 (40,40)

1.560 (39,62)

SQ

1.400 (35,56) TYP

0.100 (2,54) TYP

R

P

N

M

L

K

J

H

G

F

A1 Corner

E

D

C

B

A

1 2

3

4

5

6

7

8

9 10 11 12 13 14 15

Bottom View

0.185 (4,70)

0.140 (3,55)

0.055 (1,40)

0.045 (1,14)

0.140 (3,56)

0.120 (3,05)

0.050 (1,27) DIA

4 Places

0.022 (0,55)

0.016 (0,41)

DIA TYP

4073426/C 11/01

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Index mark can appear on top or bottom, depending on package vendor.

D. Pins are located within 0.010 (0,25) diameter of true position relative to

each other at maximum material condition and within 0.030 (0,76) diameter

relative to the edge of the ceramic.

E. This package can be hermetically sealed with metal lids or with ceramic lids using glass frit.

F. The pins can be gold-plated or solder-dipped.

G. Falls within MIL-STD-1835 CMGA7-PN

1

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型号：	SMJ320C30HFGM50
厂家：	TEXAS INSTRUMENTS
描述：	DIGITAL SIGNAL PROCESSOR 数字信号处理器微控制器和处理器外围集成电路数字信号处理器时钟
文件：	总47页 (文件大小：721K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SMJ320C30HFGM50 [TI]

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