SMJ320C50HFGM50 [TI]
DIGITAL SIGNAL PROCESSOR; 数字信号处理器
| 型号： | SMJ320C50HFGM50 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DIGITAL SIGNAL PROCESSOR |
| 文件： | 总31页 (文件大小：484K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020 – JUNE 1996
HFG PACKAGE
(TOP VIEW)
Military Operating Temperature Range:
– 55°C to 125°C
Processed to MIL-PRF-38535
Fast Instruction Cycle Time (30 ns and
40 ns)
1
99
Source-Code Compatible With All ’C1x
and ’C2x Devices
RAM-Based Operation
– 9K × 16-Bit Single-Cycle On-Chip
Program/Data RAM
– 1056 × 16-Bit Dual-Access On-Chip
Data RAM
33
67
2K × 16-Bit On-Chip Boot ROM
224K × 16-Bit Maximum Addressable
External Memory Space (64K Program,
64K Data, 64K I/O, and 32K Global)
GFA PACKAGE
(TOP VIEW)
32-Bit Arithmetic Logic Unit (ALU)
– 32-bit Accumulator (ACC)
– 32-Bit Accumulator Buffer (ACCB)
A
C
B
D
F
E
G
J
16-Bit Parallel Logic Unit (PLU)
16 × 16-Bit Multiplier, 32-Bit Product
11 Context-Switch Registers
H
K
L
M
P
T
Two Buffers for Circular Addressing
Full-Duplex Synchronous Serial Port
Time-Division Multiplexed Serial Port (TDM)
Timer With Control and Counter Registers
N
R
U
W
V
2
4
6
8 10 12 14 16 18
11 13 15 17 19
1
3
5
7
9
16 Software Programmable Wait-State
Generators
PQ PACKAGE
(TOP VIEW)
Divide-by-One Clock Option
†
1 132
117
17
IEEE 1149.1 Boundary Scan Logic
Operations Are Fully Static
18
116
Enhanced Performance Implanted CMOS
(EPIC ) 0.72-µm Technology Fabricated by
Texas Instruments
Packaging
– 141-Pin Ceramic Grid Array (GFA Suffix)
– 132-Lead Ceramic Quad Flat Package
(HFG Suffix)
– 132-Lead Plastic Quad Flat Package
(PQ Suffix)
84
50
51
83
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture
EPIC and TI are trademarks of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020 – JUNE 1996
description
The SMJ320C50 digital signal processor (DSP) is a high-performance, 16-bit, fixed-point processor
manufactured in 0.72-µm double-level metal CMOS technology. The SMJ320C50 is the first DSP from TI
designed as a fully static device. Full-static CMOS design contributes to low power consumption while
maintaining high performance, making it ideal for applications such as battery-operated communications
systems, satellite systems, and advanced control algorithms.
AnumberofenhancementstothebasicSMJ320C2xarchitecturegivethe’C50aminimum2× performanceover
the previous generation. A four-deep instruction pipeline, incorporating delayed branching, delayed call to
subroutine, and delayed return from subroutine, allows the ’C50 to perform instructions in fewer cycles. The
addition of a parallel logic unit (PLU) gives the ’C50 a method for manipulating bits in data memory without using
the accumulator and ALU. The ’C50 has additional shifting and scaling capability for proper alignment of
multiplicands or storage of values to data memory.
The ’C50 achieves its low-power consumption through the IDLE2 instruction. IDLE2 removes the functional
clock from the internal hardware of the ’C50, which puts it into a total-sleep mode that uses only 7µA. A low-logic
level on an external interrupt with a duration of at least five clock cycles ends the IDLE2 mode.
The ’C50 is available with two clock speeds. The clock frequencies are 50 MHz, providing a 40-ns cycle time,
and 66 MHz, providing a 30-ns cycle time. The available options are listed in the following table.
AVAILABLE OPTIONS
SUPPLY
PART NUMBER
SPEED
VOLTAGE
PACKAGE
TOLERANCE
SMJ320C50GFAM66
SMJ320C50HFGM66
SMJ320C50GFAM50
SMJ320C50HFGM50
30-ns cycle time
30-ns cycle time
40 ns cycle time
40 ns cycle time
30 ns cycle time
±5%
±5%
±5%
±5%
±5%
Pin grid array
Quad flat package
Pin grid array
Quad flat package
Plastic Quad flat package
†
SMQ320C50PQM66
When ordering use DESC P/N 5962-9455804NZD
†
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020 – JUNE 1996
functional block diagram
Program Bus (Address)
Program Bus (Data)
IPTR INT#
INTM
IMR
IFR
BMAR
MUX
PASR
BRAF
PC(16)
MP/MC
CNF
RAM
Compare
PAER
Program Memory
Stack
(8 × 16)
BRCR
Data Bus (Data)
TRM
MUX
TREG2
TREG1
TREG0
Multiplier
MUX
PREG(32)
PM
MUX
COUNT
Prescaler
P-Scaler
MUX
OVM
SXM
ALU(32)
ACC(32)
ACCB(32)
Post-Scaler
OV
TC
C
DBMR
MUX
BIM
PLU(16)
Data Bus (Data)
MUX
ARP
CBER
INDX
MUX
ARCR
NDX
CBSR
AUXREGS
(8 × 16)
DP(9)
dma(7)
CBCR
MUX
ARB
MUX
XF
ARAU(16)
Data Bus (Address)
Data Memory
GREG
BR
CNF
OVLY
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020 – JUNE 1996
pin assignments
PQ PKG
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
HFG PKG
1
GFA PKG
NAME
PQ PKG
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
HFG PKG
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
GFA PKG
W3
U7
NAME
A2
†
†
NC
NC
2
A3
3
D8
VSS3
VSS4
V6
A4
4
D10
W5
U9
A5
†
5
NC
A6
6
E3
D2
C1
G3
F2
D7
D6
V8
A7
7
W7
W9
E9
A8
8
D5
A9
9
D4
VDD7
VDD8
TDI
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
D3
E11
V10
K4
E1
J3
D2
D1
VSS9
VSS10
H2
G1
C3
D4
J1
D0(LSB)
TMS
VDD3
VDD4
TCK
VSS5
VSS6
M4
†
NC
W11
W13
V12
U11
W15
V14
U13
CLKMD1
A10
A11
D12
F4
A12
A13
†
NC
A14
L1
N1
M2
L3
INT1
INT2
INT3
INT4
NMI
A15(MSB)
†
†
NC
NC
E13
G5
VDD9
VDD10
RD
R1
P2
N3
T2
R3
E5
E7
DR
V16
U15
TDR
FSR
WE
†
†
NC
NC
CLKR
VDD5
VDD6
P4
T4
VSS11
VSS12
†
†
†
†
†
NC
NC
NC
NC
NC
R17
T18
U19
N17
P18
R19
L17
DS
IS
PS
H4
K2
U5
V4
VSS7
VSS8
A0
R/W
STRB
BR
A1
CLKIN2
†
NC = No internal connection
GFA Package additional connections:
V
V
: R11, E15, G15, J15, L15, N15, R13, R15, T16, U17, V18, W17, W19
DD
: T14, U1, U3, V2, W1, C17, C19, D14, D16, D18, F16, H16, K16, M16, P16
SS
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020 – JUNE 1996
pin assignments (continued)
PQ PKG
96
HFG PKG
79
GFA PKG
M18
N19
J5
NAME
X2/CLKIN
X1
PQ PKG
123
124
125
126
127
128
129
130
131
132
1
HFG PKG
106
107
108
109
110
111
GFA PKG
B16
A17
C13
B14
A15
C11
B12
A13
R7
NAME
TCLKX
CLKX
TFSR/TADD
TCLKR
RS
97
80
98
81
VDD11
VDD12
TDO
99
82
L5
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
83
L19
T6
84
VSS13
VSS14
CLKMD2
FSX
READY
HOLD
BIO
85
T8
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
86
K18
J19
87
VDD15
VDD16
IAQ
88
G19
H18
J17
TFSX/TFRM
DX
R9
89
A11
A9
90
TDX
2
TRST
VSS1
VSS2
MP/MC
D15(MSB)
D14
91
E19
F18
G17
HOLDA
XF
3
B10
D6
92
4
93
CLKOUT1
5
A7
†
94
NC
6
B8
95
E17
N5
IACK
7
C9
96
VDD13
VDD14
8
A5
D13
97
R5
9
B6
D12
†
†
†
98
NC
NC
NC
10
C7
D11
99
11
A3
D10
100
101
102
103
104
105
12
B4
D9
B18
A19
T10
T12
C15
EMU0
EMU1/OFF
VSS15
13
C5
D8
14
A1
VDD1
VDD2
15
B2
†
†
VSS16
16
NC
NC
TOUT
17
†
NC = No internal connection
GFA Package additional connections:
V
V
: R11, E15, G15, J15, L15, N15, R13, R15, T16, U17, V18, W17, W19
DD
: T14, U1, U3, V2, W1, C17, C19, D14, D16, D18, F16, H16, K16, M16, P16
SS
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020 – JUNE 1996
Terminal Functions
PIN
DESCRIPTION
†
TYPE
NAME
ADDRESS AND DATA BUSES
A15 (MSB)
A14
A13
A12
A11
A10
A9
A8
A7
A6
Parallel address bus. Multiplexed to address external data, program memory, or I/O. A0–A15 are in the
high-impedancestate in hold mode and when OFF is active (low). These signals are used as inputs for external DMA
access of the on-chip single-access RAM. They become inputs while HOLDA is active (low) if BR is driven low
externally.
I/O/Z
A5
A4
A3
A2
A1
A0 (LSB)
D15 (MSB)
D14
D13
D12
D11
D10
D9
D8
D7
D6
Parallel data bus. Multiplexed to transfer data between the core CPU and external data, program memory, or I/O
devices. D0–D15 are in the high-impedance state when not outputting data, when RS or HOLD is asserted, or when
OFF is active (low). These signals also are used in external DMA access of the on-chip single-access RAM.
I/O/Z
D5
D4
D3
D2
D1
D0 (LSB)
MEMORY CONTROL SIGNALS
DS
PS
IS
Data, program, and I/O space select signals. Always high unless asserted for communicating to a particular external
space. DS, PS, and IS are in the high-impedance state in hold mode or when OFF is active (low).
O/Z
I
Data ready input. Indicates that an external device is prepared for the bus transaction to be completed. If the device
is not ready (READY is low), the processor waits one cycle and checks READY again. READY also indicates a bus
grant to an external device after a BR (bus request) signal.
READY
R/W
Read/write. R/W indicates transfer direction during communication to an external device and is normally in read
mode (high) unless asserted for performing a write operation. R/W is in the high-impedance state in hold mode or
when OFF is active (low). Used in external DMA access of the 9K RAM cell, this signal indicates the direction of the
data bus for DMA reads (high) and writes (low) when HOLDA and IAQ are active (low).
I/O/Z
Strobe. Always high unless asserted to indicate an external bus cycle, STRB is in the high-impedance state in the
hold mode or when OFF is active (low). Used in external DMA access of the on-chip single-access RAM and while
HOLDA and IAQ are active (low), STRB is used to select the memory access.
STRB
RD
I/O/Z
O/Z
Readselect. RDindicatesanactiveexternalreadcycleandcanconnectdirectlytotheoutputenable(OE)ofexternal
devices. This signal is active on all external program, data, and I/O reads. RD is in the high-impedance state in hold
mode or when OFF is active (low).
†
I = input, O = output, Z = high-impedance
NOTE: All input pins that are unused should be connected to V
or an external pullup resistor. The BR pin has an internal pullup for performing
DD
DMA to the on-chip RAM. For emulation, TRST has an internal pulldown, and TMS, TCK, and TDI have internal pullups. EMU0 and EMU1
require external pullups to support emulation.
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020 – JUNE 1996
Terminal Functions (continued)
PIN
NAME
DESCRIPTION
†
TYPE
MEMORY CONTROL SIGNALS (CONTINUED)
Write enable. The falling edge indicates that the device is driving the external data bus (D15–D0). Data can be
latched by an external device on the rising edge of WE. This signal is active on all external program, data, and I/O
writes. WE is in the high-impedance state in hold mode or when OFF is active (low).
WE
O/Z
MULTIPROCESSING SIGNALS
Hold. HOLD is asserted to request control of the address, data, and control lines. When acknowledged by the ’C50,
these lines go to the high-impedance state.
HOLD
I
Hold acknowledge. HOLDA indicates to the external circuitry that the processor is in a hold state and that the
address, data, and memory control lines are in the high-impedance state so that they are available to the external
circuitry for access to local memory. This signal also goes to the high-impedance state when OFF is active (low).
HOLDA
O/Z
Bus request. BR is asserted during access of external global data memory space. READY is asserted when the
global data memory is available for the bus transaction. BR can be used to extend the data memory address space
byupto32Kwords. BRgoestothehigh-impedancestatewhenOFFisactivelow. BRisusedinexternalDMAaccess
of the on-chip single-access RAM. While HOLDA is active (low), BR is externally driven (low) to request access to
the on-chip single-access RAM.
BR
I/O/Z
O/Z
Instruction acquisition. Asserted (active) when there is an instruction address on the address bus; goes into the
high-impedance state when OFF is active (low). IAQ is also used in external DMA access of the on-chip
single-access RAM. While HOLDA is active (low), IAQ acknowledges the BR request for access of the on-chip
single-access RAM and stops indicating instruction acquisition.
IAQ
Branch control. BIO samples as the BIO condition and, if it is low, causes the device to execute the conditional
instruction. BIO must be active during the fetch of the conditional instruction.
BIO
XF
I
External flag (latched software-programmable signal). Set high or low by a specific instruction or by loading status
register 1 (ST1). Used for signaling other processors in multiprocessor configurations or as a general-purpose
output. XF goes to the high-impedance state when OFF is active (low) and is set high at reset.
O/Z
O/Z
Interrupt acknowledge. Indicates receipt of an interrupt and that the program counter is fetching the interrupt vector
location designated by A15–A0. IACK goes to the high-impedance state when OFF is active (low).
IACK
INITIALIZATION, INTERRUPT, AND RESET OPERATIONS
INT4
INT3
INT2
INT1
Externalinterrupts. INT1–INT4 are prioritized and maskable by the interrupt mask register (IMR) and interrupt mode
bit (INTM, bit 9 of status register 0). These signals can be polled and reset by using the interrupt flag register.
I
Nonmaskableinterrupt. NMI is the external interrupt that cannot be masked via INTM or IMR. When NMI is activated,
the processor traps to the appropriate vector location.
NMI
RS
I
I
Reset. RS causes the device to terminate execution and forces the program counter to zero. When RS is brought
to a high level, execution begins at location zero of program memory.
Microprocessor/microcomputer select. If active (low) at reset (microcomputer mode), the signal causes the internal
program ROM to be mapped into program memory space. In the microprocessor mode, all program memory is
mapped externally. This signal is sampled only during reset, and the mode that is set at reset can be overridden via
the software control bit MP/MC in the PMST register.
MP/MC
I
OSCILLATOR/TIMER SIGNALS
Master clock (or CLKIN2 frequency). CLKOUT1 cycles at the machine-cycle rate of the CPU. The internal machine
CLKOUT1
O/Z
cycle is bounded by the rising edges of this signal. This signal goes to the high-impedance state when OFF is active
(low).
†
I = input, O = output, Z = high-impedance
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020 – JUNE 1996
Terminal Functions (continued)
PIN
DESCRIPTION
†
NAME
TYPE
OSCILLATOR/TIMER SIGNALS (CONTINUED)
CLKMD1 CLKMD2
Clock mode
0
0
External clock with divide-by-two option. Input clock is provided to X2/CLKIN1. Internal
oscillator and PLL are disabled.
CLKMD1
CLKMD2
0
1
1
0
Reserved for test purposes
External divide-by-one option. Input clock is provided to CLKIN2. Internal oscillator is
disabled and internal PLL is enabled.
Internal or external divide-by-two option. Input clock is provided to X2/CLKIN1. Internal
oscillator is enabled and internal PLL is disabled.
I
I
1
1
Input to the internal oscillator from the crystal. If the internal oscillator is not being used, a clock can be input to the
device on X2/CLKIN. The internal machine cycle is half this clock rate.
X2/CLKIN
Output from the internal oscillator for the crystal. If the internal oscillator is not used, X1 must be left unconnected.
This signal does not go to the high-impedance state when OFF is active (low).
X1
O
I
CLKIN2
TOUT
Divide-by-one input clock for driving the internal machine rate.
Timer output. TOUT signals a pulse when the on-chip timer counts down past zero. The pulse is a CLKOUT1 cycle
wide.
O
SUPPLY PINS
V
DD1
V
DD2
V
DD3
V
DD4
I
Power supply for data bus
V
V
DD5
DD6
I
I
I
I
I
I
I
Power supply for address bus
V
DD7
V
DD8
Power supply for inputs and internal logic
Power supply for address bus
V
V
DD9
DD10
V
DD11
V
DD12
Power supply for memory control signals
Power supply for inputs and internal logic
Power supply for memory control signals
Ground for memory control signals
V
DD13
V
DD14
V
DD15
V
DD16
V
SS1
V
SS2
V
SS3
V
SS4
V
SS5
V
SS6
I
Ground for data bus
V
V
V
V
SS7
SS8
SS9
SS10
I
I
I
Ground for address bus
V
SS11
V
SS12
Ground for memory control signals
Ground for inputs and internal logic
V
SS13
V
SS14
V
SS15
V
SS16
†
I = input, O = output, Z = high-impedance
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020 – JUNE 1996
Terminal Functions (continued)
PIN
NAME
DESCRIPTION
†
TYPE
SERIAL PORT SIGNALS
Receive clock. External clock signal for clocking data from DR (data receive) or TDR (TDM data receive) into the
RSR (serial port receive shift register). Must be present during serial port transfers. If the serial port is not being used,
these signals can be sampled as an input via the IN0 bit of the serial port control (SPC) or TDR serial port control
(TSPC) registers.
CLKR
TCLKR
I
Transmit clock. Clock signal for clocking data from the DR or TDR to the DX (data transmit) or TDX (TDM data
transmit pins). CLKX can be an input if the MCM bit in the serial port control register is set to 0. It can also be driven
by the device at 1/4 the CLKOUT1 frequency when the MCM bit is set to 1. If the serial port is not being used, this
pin can be sampled as an input via the IN1 bit of the SPC or TSPC register. This signal goes into the high-impedance
state when OFF is active (low).
CLKX
TCLKX
I/O/Z
DR
TDR
I
Serial data receive. Serial data is received in the RSR (serial port receive shift register) via DR or TDR.
DX
TDX
Serial port transmit. Serial data transmitted from XSR (serial port transmit shift register) via DX or TDX. This signal
is in the high-impedance state when not transmitting and when OFF is active (low).
O/Z
Frame synchronization pulse for receive. The falling edge of FSR or TFSR initiates the data receive process, which
begins the clocking of the RSR. TFSR becomes an input/output (TADD) pin when the serial port is operating in the
TDM mode (TDM bit = 1). In TDM mode, this pin is used to input/output the address of the port. This signal goes
into the high-impedance state when OFF is active (low).
FSR
TFSR/TADD
I
I/O/Z
Frame synchronization pulse for transmit. The falling edge of FSX/TFSX initiates the data transmit process, which
begins the clocking of the XSR. Following reset, the default operating condition of FSX/TFSX is an input. This pin
may be selected by software to be an output when the TXM bit in the serial control register is set to 1. This signal
goes to the high-impedance state when OFF is active (low). When operating in TDM mode (TDM bit = 1), TFSX
becomes TFRM, the TDM frame-synchronization pulse.
FSX
TFSX/TFRM
I/O/Z
TEST SIGNALS
Boundary scan test clock. This is normally a free-running clock with a 50% duty cycle. The changes of TAP (test
access port) input signals (TMS and TDI) are clocked into the TAP controller, instruction register, or selected test
data register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur on the falling edge of TCK.
TCK
TDI
I
I
Boundary scan test data input. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK.
Boundary scan test data output. The contents of the selected register (instruction or data) is shifted out of TDO on
the falling edge of TCK. TDO is in the high-impedance state except when scanning of data is in progress. This signal
also goes to the high-impedance state when OFF is active (low).
TDO
O/Z
Boundary scan test mode select. This serial control input is clocked into the test access port (TAP) controller on the
rising edge of TCK.
TMS
I
I
Boundary scan test reset. Asserting this signal gives the JTAG scan system control of the operations of the device.
If this signal is not connected or is driven low, the device operates in its functional mode and the boundary scan
signals are ignored.
TRST
Emulator 0. When TRST is driven low, EMU0 must be high for activation of the OFF condition (see EMU1/OFF).
WhenTRSTisdrivenhigh, EMU0isusedasaninterrupttoorfromtheemulatorsystemandisdefinedasinput/output
put via boundary scan.
EMU0
I/O/Z
Emulator 1/OFF. When TRST is driven high, EMU1/OFF is used as an interrupt to or from the emulator system and
is defined as input/output via boundary scan. When TRST is driven low, EMU1/OFF is configured as OFF. When
the OFF signal is active (low), all output drivers are in the high-impedance state. OFF is used exclusively for testing
andemulationpurposes(notformultiprocessingapplications). FortheOFFcondition, thefollowingconditionsapply:
EMU1/OFF
I/O/Z
N/C
•
•
•
TRST = Low
EMU0 = High
EMU1/OFF = Low
‡
RESERVED
Reserved. This pin must be left unconnected.
†
‡
I = input, O = output, Z = high-impedance
Quad flat pack only
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020 – JUNE 1996
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
DD
Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Maximum operating case temperature, T
Minimum operating free-air temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125°C
C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to V
.
SS
recommended operating conditions
MIN NOM
MAX
UNIT
V
V
V
Supply voltage
Supply voltage
4.75
5
0
5.25
DD
V
SS
CLKIN, CLKIN2
3.0
2.5
V
V
V
V
DD + 0.3
V
IH
High-level input voltage
CLKX, CLKR, TCLKX, TCLKR
All others
V
DD + 0.3
2.2
V
DD + 0.3
0.6
V
IL
Low-level input voltage
– 0.3
V
‡
I
I
High-level output current
Low-level output current
Operating case temperature
Operating free-air temperature
– 300
µA
mA
°C
°C
OH
2
OL
T
125
C
T
– 55
A
‡
This I
can be exceeded when using a 1-KΩ pulldown resistor on the TDM serial port TADD output, however this output still meets V
OH
OH
specifications under these conditions.
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
§
¶
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
#
V
V
High-level output voltage
I
I
= MAX
= MAX
2.4
3
OH
OH
¶
Low-level output voltage
0.3
||
0.6
30
V
OL
OL
BR (with internal pullup)
All others
– 500
– 30
– 30
– 500
– 50
– 30
High-impedance output
I
µA
OZ
||
||
||
||
||
current (V
= MAX)
30
DD
TRST (with internal pulldown)
TMS, TCK, TDI (with internal pullups)
X2/CLKIN
800
30
µA
Input current
(V = V to V )
DD
I
I
50
I
SS
All other inputs
30
µA
mA
mA
mA
µA
pF
I
I
Supply current, core CPU
Supply current, pins
Operating,
T
= 25°C,
= 25°C,
= 125°C,
V
DD
V
DD
V
DD
= 5.25 V, f = 50 MHz
60
40
225
225
30
DDC
A
x
Operating,
T
= 5.25 V, f = 50 MHz
x
DDP
A
IDLE instruction,
T
= 5.25 V, f = 50 MHz
x
A
I
Supply current, standby
DD
IDLE2 instruction, Clocks shut off, T =125°C,
V
DD
=5.25 V
7
A
C
C
Input capacitance
Output capacitance
15
15
40
i
40
pF
o
§
¶
#
For conditions shown as MIN/MAX, use the appropriate value specified under recommended operating conditions.
All typical or nominal values are at V = 5 V, T = 25°C.
All input and output voltage levels are TTL-compatible. Figure 1 shows the test load circuit; Figure 2 and Figure 3 show the voltage reference
DD
A
levels.
||
These values are not specified pending detailed characterization.
10
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020 – JUNE 1996
PARAMETER MEASUREMENT INFORMATION
I
OL
Tester Pin
Electronics
Output
Under
Test
50 Ω
V
LOAD
C
T
I
OH
Where:
I
I
V
=
=
=
=
2.0 mA (all outputs)
300 µA (all outputs)
1.5 V
OL
OH
LOAD
T
C
80 pF typical load circuit capacitance
Figure 1. Test Load Circuit
signal transition levels
Transistor-to-transistor logic (TTL) output levels are driven to a minimum logic-high level of 2.4 V and to a
maximum logic-low level of 0.6 V. Figure 2 shows the TTL-level outputs.
2.4 V
2 V
1 V
0.6 V
Figure 2. TTL-Level Outputs
TTL-output transition times are specified as follows:
For a high-to-low transition, the level at which the output is said to be no longer high is 2 V, and the level
at which the output is said to be low is 1 V.
For a low-to-high transition, the level at which the output is said to be no longer low is 1 V, and the level
at which the output is said to be high is 2 V.
Figure 3 shows the TTL-level inputs.
2.2 V
0.6 V
Figure 3. TTL-Level Inputs
TTL-compatible input transition times are specified as follows:
For a high-to-low transition on an input signal, the level at which the input is said to be no longer high
is 2 V, and the level at which the input is said to be low is 0.8 V.
For a low to high transisiton on an input signal, the level at which the input is said to be no longer low
is 0.8 V, and the level at which the input is said to be high is 2 V.
11
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020 – JUNE 1996
CLOCK CHARACTERISTICS AND TIMING
The ’C50 can use either its internal oscillator or an external frequency source for a clock. The clock mode is
determined by the CLKMD1 and CLKMD2 pins. Table 1 outlines the selection of the clock mode by these pins.
Table 1. Clock Mode Selection
CLKMD1
CLKMD2
CLOCK SOURCE
External divide-by-one clock option
1
0
0
1
Reserved for test purposes
External divide-by-two option or internal divide-by-two clock option
with an external crystal
1
0
1
0
External divide-by-two option with the internal oscillator disabled
internal divide-by-two clock option with external crystal
The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN. The frequency of CLKOUT1
is one-half the crystal’s oscillating frequency. The crystal should be in either fundamental or overtone operation
and parallel resonant, with an effective series resistance of 30 Ω and a power dissipation of 1 mW; it should be
specifiedat a load capacitance of 20 pF. Overtone crystals require an additional tuned LC circuit. Figure 4 shows
an external crystal (fundamental frequency) connected to the on-chip oscillator.
recommended operating conditions for internal divide-by-two clock option
’320C50-50
MIN NOM
’320C50-66
MIN NOM
UNIT
MAX
MAX
†
†
f
Input clock frequency
0
50
0
66
MHz
pF
x
C1, C2 Load capacitance
10
10
†
This device utilizes a fully static design and therefore can operate with t
approaching ∞. The device is characterized at frequencies
approaching 0 Hz but is tested at a minimum of 3.3 MHz to meet device test time requirements.
c(CI)
X1
X2/CLKIN
Crystal
C1
C2
Figure 4. Internal Clock Option
12
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020 – JUNE 1996
external divide-by-two clock option
An external frequency source can be used by injecting the frequency directly into X2/CLKIN with X1 left
unconnected, CLKMD1 set high, and CLKMD2 set high. The external frequency is divided by two to generate
the internal machine cycle. The external frequency injected must conform to specifications listed in the timing
requirements table.
switching characteristics over recommended operating conditions [H = 0.5 t
]
c(CO)
’320C50-50
’320C50-66
TYP
PARAMETER
UNIT
MIN
40 2t
TYP
MAX
MIN
MAX
†
†
t
t
t
t
t
t
Cycle time, CLKOUT1
30 2t
ns
ns
ns
ns
ns
ns
c(CO)
c(CI)
11
c(CI)
11
Delay time, X2/CLKIN high to CLKOUT1 high/low
Fall time, CLKOUT1
3
20
3
20
d(CIH-COH/L)
f(CO)
5
5
5
5
Rise time, CLKOUT1
r(CO)
Pulse duration, CLKOUT1 low
Pulse duration, CLKOUT1 high
H – 3
H – 3
H
H
H + 2 H – 3
H + 2 H – 3
H
H
H + 2
H + 2
w(COL)
w(COH)
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
’320C50-50
’320C50-66
UNIT
MIN
MAX
MIN
MAX
†
†
t
t
t
t
t
Cycle time, X2/CLKIN
20
15
ns
ns
ns
ns
ns
c(CI)
‡
Fall time, X2/CLKIN
5
5
f(CI)
‡
Rise time, X2/CLKIN
5
†
5
†
r(CI)
Pulse duration, X2/CLKIN low
Pulse duration, X2/CLKIN high
8
8
7
7
w(CIL)
w(CIH)
†
†
†
This device utilizes a fully static design and therefore can operate with t
c(CI)
approaching ∞. The device is characterized at frequencies
approaching 0 Hz, but is tested at a minimum of 6.7 MHz to meet device test time requirements.
Values derived from characterization data and not tested.
‡
t
r(CI)
t
t
f(CI)
w(CIH)
t
t
w(CIL)
c(CI)
CLKIN
t
f(CO)
t
c(CO)
d(CIH-COH/L)
t
r(CO)
t
t
w(COL)
t
w(COH)
CLKOUT1
Figure 5. External Divide-by-Two Clock Timing
13
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020 – JUNE 1996
external divide-by-one clock option
An external frequency source can be used by injecting the frequency directly into CLKIN2 with X1 left
unconnected and X2 connected to V . This external frequency is divided by one to generate the internal
DD
machine cycle. The divide-by-one option is used when CLKMD1 is strapped high and CLKMD2 is strapped low.
The external frequency injected must conform to specifications listed in the timing requirements table (see
Figure 6 for more details).
switching characteristics over recommended operating conditions [H = 0.5 t
]
c(CO)
’320C50-50
TYP
’320C50-66
TYP
PARAMETER
UNIT
MIN
40
2
MAX
MIN
30
2
MAX
†
†
t
t
t
t
t
t
Cycle time, CLKOUT1
t
75
16
t
75
16
ns
ns
ns
ns
ns
ns
c(CO)
c(CI)
9
c(CI)
9
Delay time, CLKIN2 high to CLKOUT1 high
Fall time, CLKOUT1
d(C2H-COH)
f(CO)
5
5
5
5
Rise time, CLKOUT1
r(CO)
†
†
†
†
†
†
†
†
Pulse duration, CLKOUT1 low
Pulse duration, CLKOUT1 high
H – 3
H
H
H + 2
H – 3
H
H
H + 2
w(COL)
w(COH)
H – 3
H + 2
H – 3
H + 2
Delay time, transitory phase–PLL
synchronized after CLKIN2 supplied
§
§
t
1000t
c(C2)
1000t
c(C2)
ns
d(TP)
†
Values assured by design and not tested
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
’320C50-50
’320C50-66
UNIT
UNIT
ns
MIN
MAX
MIN
MAX
‡
‡
t
t
t
t
t
Cycle time, CLKIN2
40
75
30
75
c(C2)
§
Fall time, CLKIN2
5
5
5
5
ns
f(C2)
§
Rise time, CLKIN2
ns
r(C2)
Pulse duration, CLKIN2 low
Pulse duration, CLKIN2 high
11
11
t
t
9
9
t
t
ns
w(C2L)
w(C2H)
c(C2)–11
c(C2)–9
ns
c(C2)–11
c(C2)–9
‡
Clocks can be stopped only while the device executes IDLE2 when using the external divide-by-one clock option. Note that tp (the transitory
phase) occurs when restarting clock from IDLE2 in this mode.
Values derived from characterization data and not tested.
§
t
w(C2L)
t
f(C2)
t
w(C2H)
t
r(C2)
t
c(C2)
CLKIN2
t
t
w(COH)
d(C2H-COH)
t
f(CO)
t
t
r(CO)
c(CO)
t
w(COL)
t
d(TP)
Unstable
CLKOUT1
Figure 6. External Divide-by-One Clock Timing
14
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020 – JUNE 1996
MEMORY AND PARALLEL I/O INTERFACE READ
Memory and parallel I/O interface read timings are illustrated in Figure 7.
switching characteristics over recommended operating conditions [H = 0.5t
]
c(CO)
PARAMETER
MIN
MAX
UNIT
ns
†
‡
t
t
t
t
t
Setup time, address valid before RD low
H–10
0
su(AV-RDL)
h(RDH-AV)
w(RDL)
†
‡
Hold time, address valid after RD high
§¶
ns
Pulse duration, RD low
H–2
H–2
ns
§¶
Pulse duration, RD high
ns
w(RDH)
Delay time, RD high to WE low
2H–5
ns
d(RDH-WEL)
†
A15–A0, PS, DS, IS, R/W, and BR timings are all included in timings referenced as address.
See Figure 8 for address-bus timing variation with load capacitance.
STRB and RD timing is – 3/+5 ns from CLKOUT1 timing on read cycles, following the first cycle after reset, which is always a seven wait-state cycle.
Values are derived from characterization data and are not tested.
‡
§
¶
timing requirements over recommended ranges of supply voltage and operating free-air
temperature [H = 0.5t
]
c(CO)
MIN
MAX
UNIT
ns
‡
t
t
t
t
Access time, read data valid from address valid
Access time, read data valid after RD low
Setup time, read data valid before RD high
Hold time, read data valid after RD high
2H–15
a(RDAV)
H–10
ns
a(RDL-RD)
su(RD-RDH)
h(RDH-RD)
10
0
ns
ns
‡
See Figure 8 for address-bus timing variation with load capacitance.
15
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020 – JUNE 1996
MEMORY AND PARALLEL I/O INTERFACE WRITE
Memory and parallel I/O interface read timings are illustrated in Figure 7.
switching characteristics over recommended operating conditions [H = 0.5t
]
c(CO)
PARAMETER
MIN
MAX
UNIT
ns
†
‡
t
t
t
t
t
t
t
t
Setup time, address valid before WE low
H – 5
su(AV-WEL)
h(WEH-AV)
w(WEL)
†
‡
Hold time, address valid after WE high
H – 10
ns
§
¶
Pulse duration, WE low
2H – 4 2H + 2
ns
§
Pulse duration, WE high
Delay time, WE high to RD low
Setup time, write data valid before WE high
2H – 2
ns
w(WEH)
3H – 10
ns
d(WEH-RDL)
su(WDV-WEH)
h(WEH-WDV)
en(WE-BUd)
§
¶#
2H – 20
H – 5
2H
ns
§
¶
Hold time, write data valid after WE high
Enable time, WE to data bus driven
H+10
ns
¶
–5
ns
†
‡
§
A15–A0,PS, DS, IS, R/W, and BR timings are all included in timings referenced as address.
See Figure 8 for address bus timing variation with load capacitance.
STRBandWEedgesare0–4nsfromCLKOUT1edgesonwrites. Risingandfallingedgesofthesesignalstrackeachother;toleranceofresulting
pulse durations is ± 2 ns, not ± 4 ns.
¶
#
Values derived from characterization data and are not tested.
This value holds true for zero or one wait state only.
ADDRESS
t
h(WEH-AV)
t
su(AV-WEL)
t
a(RDAV)
R/W
t
h(RDH-RD)
t
t
a(RDL-RD)
en(WE-BUd)
t
su(RD-RDH)
t
h(WEH-WDV)
DATA
RD
t
t
su(WDV-WEH)
t
t
su(AV-RDL)
h(RDH-AV)
t
d(WEH-RDL)
t
d(RDH-WEL)
t
w(RDH)
t
w(WEL)
w(RDL)
WE
t
w(WEH)
STRB
NOTE A: All timings are for 0 wait states. However, external writes always require two cycles to prevent external bus conflicts. The above diagram
illustrates a one-cycle read and a two-cycle write and is not drawn to scale. All external writes immediately preceded by an external
read or immediately followed by an external read require three machine cycles.
Figure 7. Memory and Parallel I/O Interface Read and Write Timing
16
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020 – JUNE 1996
2
1.75
1.50
1.25
1
0.75
0.50
0.25
10 15 20 25
30 35 40
45 50 55
60 65 70 75
80 85 90
95
Change in Load Capacitance – pF
Figure 8. Address Bus Timing Variation With Load Capacitance
17
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020 – JUNE 1996
READY TIMING FOR EXTERNALLY GENERATED WAIT STATES
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN
10
MAX
UNIT
ns
t
t
t
t
t
t
Setup time, READY before CLKOUT1 rises
Hold time, READY after CLKOUT1 rises
Setup time, READY before RD falls
Hold time, READY after RD falls
su(RY-COH)
h(CO-RYH)
su(RY-RDL)
h(RDL-RY)
v(WEL-RY)
h(WEL-RY)
0
ns
10
ns
0
ns
Valid time, READY after WE falls
Hold time, READY after WE falls
H – 15
H + 5
ns
ns
CLKOUT1
t
su(RY-COH)
ADDRESS
t
h(CO-RYH)
READY
Wait State
Generated
by READY
t
su(RY-RDL)
Wait State
Generated
Internally
t
h(RDL-RY)
RD
Figure 9. Ready Timing for Externally Generated Wait States During an External Read Cycle
CLKOUT1
t
h(CO-RYH)
ADDRESS
READY
t
su(RY-COH)
t
v(WEL-RY)
t
h(WEL-RY)
WE
Wait State Generated by READY
Figure 10. Ready Timing for Externally Generated Wait States During an External Write Cycle
18
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020 – JUNE 1996
RESET, INTERRUPT, AND BIO
timing requirements over recommended ranges of supply voltage and operating free-air
temperature [H = 0.5t
]
c(CO)
PARAMETER
Setup time, INT1–INT4, NMI, before CLKOUT1 low
MIN
15
0
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
†
t
t
t
t
t
t
t
t
t
t
t
t
t
su(IN-COL)
h(COL-IN)
w(INL)SYN
w(INH)SYN
w(INL)ASY
w(INH)ASY
su(RS-X2L)
w(RSL)
†
Hold time, INT1–INT4, NMI, after CLKOUT1 low
‡
4H+15
Pulse duration, INT1–INT4, NMI low, synchronous
Pulse duration, INT1–INT4, NMI high, synchronous
Pulse duration, INT1–INT4, NMI low, asynchronous
‡§
2H+15
6H+15
4H+15
¶
‡
‡
¶
Pulse duration, INT1–INT4, NMI high, asynchronous
Setup time, RS before X2/CLKIN low
Pulse duration, RS low
10
12H
34H
15
Delay time, RS high to reset vector fetch
Pulse duration, BIO low, synchronous
d(RSH)
w(BIL)SYN
w(BIL)ASY
su(BI-COL)
h(COL-BI)
¶
Pulse duration, BIO low, asynchronous
Setup time, BIO before CLKOUT1 low
Hold time, BIO after CLKOUT1 low
H+15
15
0
†
These parameters must be met to use the synchronous timings. Both reset and the interrupts can operate asynchronously. The pulse durations
require an extra half-cycle to assure internal synchronization.
‡
§
¶
If in IDLE2, add 4H to these timings.
Values are specified by design and not tested.
Values derived from characterization data and are not tested.
X2/CLKIN
t
t
d(RSH)
su(RS-X2L)
t
w(RSL)
RS
t
t
su(BI-COL)
su(IN-COL)
CLKOUT1
t
w(BIL)SYN
t
h(COL-BI)
BIO
A15–A0
INT4–
INT1
t
t
h(COL-IN)
su(IN-COL)
t
su(IN-COL)
t
w(INL)SYN
t
w(INH)SYN
Figure 11. Reset, Interrupt, and BIO Timings
19
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020 – JUNE 1996
INSTRUCTION ACQUISITION (IAQ), INTERRUPT ACKNOWLEDGE (IACK),
EXTERNAL FLAG (XF), AND TOUT
switching characteristics over recommended operating conditions [H = 0.5t
]
c(CO)
PARAMETER
MIN
MAX
UNIT
ns
†
‡
‡
‡
t
t
t
t
t
t
t
t
t
Setup time, address valid before IAQ low
Hold time, address valid after IAQ low
Pulse duration, IAQ low
H–12
H–10
H–10
su(AV-IQL)
h(IQL-AV)
w(IQL)
ns
ns
Delay time, CLKOUT1 falling to TOUT
–6
6
ns
d(CO-TU)
su(AV-IKL)
h(IKH-AV)
w(IKL)
§
‡
‡
‡
Setup time, address valid before IACK low
H–12
H–10
H–10
ns
§
Hold time, address valid after IACK high
Pulse duration, IACK low
ns
ns
Pulse duration, TOUT high
2H–12
0
ns
w(TUH)
Delay time, XF valid after CLKOUT1
12
ns
d(CO-XFV)
†
IAQ goes low during an instruction acquisition. It goes low only on the first cycle of the read when wait states are used. The falling edge should
be used to latch the valid address. The AVIS bit in the PMST register must be set to zero for the address to be valid when the instruction being
addressed resides in on-chip memory.
‡
§
Valid only if the external address reflects the current instruction activity (that is, code is executing on chip with no external bus cycles and AVIS
is on, or code is executing off-chip).
IACK goes low during the fetch of the first word of the interrupt vector. It goes low only on the first cycle of the read when wait states are used.
Address pins A1 – A4 can be decoded at the falling edge to identify the interrupt being acknowledged. The AVIS bit in the PMST register must
be set to zero for the address to be valid when the vectors reside in on-chip memory.
t
h(IQL-AV)
ADDRESS
t
su(AV-IQL)
t
w(IQL)
IAQ
t
h(IKH-AV)
t
su(AV-IKL)
IACK
t
w(IKL)
STRB
CLKOUT1
t
d(CO-XFV)
t
t
d(CO-TU)
t
d(CO-TU)
XF
TOUT
w(TUH)
NOTE: IAQ and IACK are not affected by wait states.
Figure 12. IAQ, IACK, and XF Timings Example With Two External Wait States
20
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020 – JUNE 1996
EXTERNAL DMA TIMING
switching characteristics over recommended operating conditions [H = 0.5t
] (see Note 2)
c(CO)
PARAMETER
Delay time, HOLD low to HOLDA low
MIN
4H
2H
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
‡
t
t
t
t
t
t
t
t
t
t
t
t
d(HOL-HAL)
d(HOH-HAH)
dis(AZ-HAL)
en(HAH-Ad)
d(XBL-IQL)
d(XBH-IQH)
d(XSL-RDV)
h(XSH-RD)
en(IQL-RDd)
dis(W)
Delay time, HOLD high before HOLDA high
Disable time, address in the high-impedance state before HOLDA low
Enable time, HOLDA high to address driven
Delay time, XBR low to IAQ low
§
†
†
†
†
H–15
H–5
4H
†
†
6H
Delay time, XBR high to IAQ high
2H
4H
Delay time, read data valid after XSTRB low
Hold time, read data after XSTRB high
40
0
†
¶
†
†
†
†
Enable time, IAQ low to read data driven
0
0
2H
15
H
†
Disable time, XR/W low to data in the high-impedance state
Disable time, IAQ high to data in the high-impedance state
Enable time, data from XR/W going high
dis(I-D)
4
en(D-XRH)
†
Values derived from characterization data and are not tested.
HOLD is not acknowledged until current external access request is complete.
This parameter includes all memory control lines.
This parameter refers to the delay between the time the condition (IAQ = 0 and XR/W = 1) is satisfied and the time that the SMJ320C50x data
lines become valid.
‡
§
¶
NOTE 2: X preceding a name refers to the external drive of the signal.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN
MAX
UNIT
ns
#
#
t
t
t
t
t
t
t
t
t
t
Delay time, HOLDA low to XBR low
0
0
d(HAL-XBL)
d(IQL-XSL)
su(AV-XSL)
su(DV-XSL)
h(XSL-D)
#
#
Delay time, IAQ low to XSTRB low
ns
Setup time, Xaddress valid before XSTRB low
Setup time, Xdata valid before XSTRB low
Hold time, Xdata hold after XSTRB low
Hold time, write Xaddress hold after XSTRB low
Pulse duration, XSTRB low
15
15
15
15
45
45
20
0
ns
ns
ns
ns
h(XSL-WA)
w(XSL)
ns
Pulse duration, XSTRB high
ns
w(XSH)
Setup time, R/W valid before XSTRB low
Hold time, read Xaddress after XSTRB high
ns
su(RW-XSL)
h(XSH-RA)
ns
#
XBR, XR/W, and XSTRB lines should be pulled up with a 10-kΩ resistor to assure that they are in an inactive (high) state during the transition
period between the SMJ320C50x driving them and the external circuit driving them.
NOTE 2. X preceding a name refers to the external drive of the signal.
21
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020 – JUNE 1996
EXTERNAL DMA
HOLD
t
d(HOH-HAH)
t
d(HOL-HAL)
HOLDA
t
en(HAH-Ad)
t
dis(AZ-HAL)
Address
Bus/
Control
†
Signals
t
en(I-B)
t
d(HAL-XBL)
XBR
IAQ
t
d(XBL-IQL)
t
d(XBH-IQH)
t
d(IQL-XSL)
t
su(RW-XSL)
XSTRB
XR/W
t
w(XSH)
t
w(XSL)
t
dis(W)
t
su(AV-XSL)
t
h(XSH-RD)
t
h(XSH-RA)
t
en(IQL-RDd)
XADDRESS
t
d(XSL-RDV)
t
su(AV-XSL)
t
h(XSL-WA)
t
dis(I-D)
DATA(RD)
t
en(IQL-RDd)
t
t
en(D-XRH)
h(XSL-D)
t
su(DV-XSL)
XDATA(WR)
†
A15–A0, PS, DS, IS, R/W, and BR timings are all included in timings referenced as address bus/control signals.
Figure 13. External DMA Timing
22
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020 – JUNE 1996
SERIAL-PORT RECEIVE
timing requirements over recommended ranges of supply voltage and operating free-air
temperature [H = 0.5t
]
c(CO)
PARAMETER
MIN
MAX
UNIT
ns
†
t
t
t
t
t
t
t
t
Cycle time, serial-port clock
Fall time, serial-port clock
Rise time, serial-port clock
5.2H
c(SCK)
‡
8
8
ns
f(SCK)
‡
ns
r(SCK)
Pulse duration, serial-port clock low/high
Setup time, FSR before CLKR falling edge
Hold time, FSR after CLKR falling edge
Setup time, DR before CLKR falling edge
Hold time, DR after CLKR falling edge
2.1H
10
ns
w(SCK)
ns
su(FS-CK)
h(CK-FS)
su(DR-CK)
h(CK-DR)
10
ns
10
ns
10
ns
†
The serial-port design is fully static and therefore can operate with t
0 Hz but tested at a much higher frequency to minimize test time.
Values derived from characterization data and are not tested.
approaching ∞. It is characterized approaching an input frequency of
c(SCK)
‡
t
c(SCK)
t
f(SCK)
t
w(SCK)
CLKR
FSR
t
t
r(SCK)
h(CK-FS)
t
w(SCK)
t
su(FS-CK)
t
su(DR-CK)
t
h(CK-DR)
DR
Bit
1
2
7 or 15
(see Note A)
8 or 16
(see Note A)
NOTE A: Depending on whether information is sent in an 8-bit or 16-bit packet.
Figure 14. Serial-Port Receive Timing
23
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020 – JUNE 1996
SERIAL-PORT TRANSMIT, EXTERNAL CLOCKS AND EXTERNAL FRAMES
switching characteristics over recommended operating conditions (see Note 3)
PARAMETER
MIN
MAX
UNIT
ns
t
t
t
Delay time, DX valid after CLKX high
Disable time, DX valid after CLKX high
Hold time, DX valid after CLKX high
25
d(CXH-DXV)
dis(CXH-DX)
h(CXH-DXV)
†
40
ns
–5
ns
timing requirements over recommended ranges of supply voltage and operating free-air
temperature [H = 0.5t ] (see Note 3)
c(CO)
MIN
MAX
UNIT
ns
t
t
t
t
t
t
t
Cycle time, serial-port clock
5.2H
‡
c(SCK)
†
Fall time, serial-port clock
8
8
ns
f(SCK)
†
Rise time, serial-port clock
ns
r(SCK)
Pulse duration, serial-port clock low/high
Delay time, FSX after CLKX high edge
Hold time, FSX after CLKX falling edge
Hold time, FSX after CLKX high edge
2.1H
10
ns
w(SCK)
2H–8
ns
d(CXH-FXH)
h(CXL-FXL)
h(CXH-FXL)
ns
†§
2H–8
ns
†
‡
Values derived from characterization data and are not tested.
The serial-port design is fully static and therefore can operate with t
0 Hz but tested at a much higher frequency to minimize test time.
approaching ∞. It is characterized approaching an input frequency of
c(SCK)
§
If the FSX pulse does not meet this specification, the first bit of serial data will be driven on the DX pin until the fallingedge of FSX. After the falling
edgeofFSX,datawillbeshiftedoutontheDXpin.Thetransmit-buffer-emptyinterruptwillbegeneratedwhenthet
is met.
t
specification
h(FS)and h(FS)H
NOTE 3: Internal clock with external FSX and vice versa are also allowable. However, FSX timings to CLKX are always defined depending on
the source of FSX, and CLKX timings are always dependent upon the source of CLKX. Specifically, the relationship of FSX to CLKX
is independent of the source of CLKX.
t
c(SCK)
t
f(SCK)
t
w(SCK)
CLKX
t
t
r(SCK)
d(CXH-FXH))
t
h(CXH-FXL)
t
h(CXL-FXL)
t
w(SCK)
FSX
t
d(CXH-DXV)
1
t
dis(CXH-DX)
t
h(CXH-DXV)
DX Bit
2
7 or 15
(see Note A)
8 or 16
(see Note A)
NOTE A: Depending on whether information is sent in an 8-bit or 16-bit packet.
Figure 15. Serial-Port Transmit Timing of External Clocks and External Frames
24
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020 – JUNE 1996
SERIAL-PORT TRANSMIT, INTERNAL CLOCKS AND INTERNAL FRAMES
switching characteristics over recommended operating conditions [H = 0.5t ] (see Note 3)
c(CO)
PARAMETER
Delay time, CLKX rising to FSX
MIN
TYP
MAX
25
UNIT
ns
t
t
t
t
t
t
t
t
d(CX-FX)
d(CX-DX)
dis(CX-DX)
c(SCK)
Delay time, CLKX rising to DX
Disable time, CLKX rising to DX
Cycle time, serial-port clock
25
ns
†
40
ns
8H
5
ns
Fall time, serial-port clock
ns
f(SCK)
Rise time, serial-port clock
5
ns
r(SCK)
Pulse duration, serial-port clock low/high
Hold time, DX valid after CLKX high
4H – 20
– 6
ns
w(SCK)
ns
h(CXH-DXV)
†
Values derived from characterization and not tested.
NOTE 3: Internal clock with external FSX and vice versa are also allowable. However, FSX timings to CLKX are always defined depending on
the source of FSX, and CLKX timings are always dependent upon the source of CLKX. Specifically, the relationship of FSX to CLKX
is independent of the source of CLKX.
t
)
c(SCK
t
f(SCK)
t
w(SCK)
CLKX
FSX
t
t
d(CX-FX)
w(SCK)
t
r(SCK)
t
d(CX-FX)
t
d(CX-DX)
t
dis(CX-DX)
t
h(CXH-DXV)
DX
Bit
1
2
7 or 15
(see Note A)
8 or 16
(see Note A)
NOTE A: Depending on whether information is sent in an 8-bit or 16-bit packet.
Figure 16. Serial-Port Transmit Timing of Internal Clocks and Internal Frames
25
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020 – JUNE 1996
SERIAL-PORT RECEIVE TIMING IN TDM MODE
timing requirements over recommended ranges of supply voltage and operating free-air
temperature [H = 0.5t
]
c(CO)
MIN
MAX
UNIT
ns
†
t
t
t
t
t
t
t
t
t
t
Cycle time, serial-port clock
5.2H
c(SCK)
‡
Fall time, serial-port clock
8
8
ns
f(SCK)
‡
Rise time, serial-port clock
ns
r(SCK)
Pulse duration, serial-port clock low/high
Setup time, TDAT/TADD before TCLK rising
Hold time, TDAT/TADD after TCLK rising
Setup time, TDAT/TADD before TCLK rising
2.1H
30
ns
w(SCK)
ns
su(TD-TCH)
h(TCH-TD)
su(TA-TCH)
h(TCH-TA)
su(TF-TCH)
h(TCH-TF)
–3
20
ns
§
ns
§
Hold time, TDAT/TADD after TCLK rising
– 3
10
ns
¶
Setup time, TRFM before TCLK rising edge
ns
¶
Hold time, TRFM after TCLK rising edge
10
ns
†
The serial-port design is fully static and therefore can operate with t
0 Hz but tested at a much higher frequency to minimize test time.
Values derived from characterization data and are not tested.
These parameters apply only to the first bits in the serial bit string.
TFRM timing and waveforms shown in Figure 17 are for external TFRM. TFRM also can be configured as internal. The TFRM internal case is
illustrated in the transmit timing diagram in Figure 18.
approaching ∞. It is characterized approaching an input frequency of
c(SCK)
‡
§
¶
t
t
f(SCK)
w(SCK)
t
t
w(SCK)
r(SCK)
TCLK
TDAT
t
t
su(TD-TCH)
c(SCK)
t
h(TCH-TD)
B13
B15
B1
B0
B0
B14
B12
A3
B8
A7
B7
B2
t
t
h(TCH-TA)
t
su(TA-TCH)
h(TCH-TA)
t
su(TF-TCH)
TADD
TFRM
A0
A1
A2
t
h(TCH-TF)
Figure 17. Serial-Port Receive Timing in TDM Mode
26
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020 – JUNE 1996
SERIAL-PORT TRANSMIT TIMING IN TDM MODE
switching characteristics over recommended operating conditions [H = 0.5t
]
c(CO)
PARAMETER
MIN
0
MAX
UNIT
ns
t
t
t
Hold time, TDAT/TADD valid after TCLK rising
h(TCH-TDV)
d(TCH-TFV)
d(TC-TDV)
†
Delay time, TFRM valid after TCLK rising
Delay time, TCLK to valid TDAT/TADD
H
3H+10
20
ns
ns
†
TFRM timing and waveforms shown in Figure 18 are for internal TFRM. TFRM can also be configured as external, and the TFRM external case
is illustrated in the receive timing diagram in Figure 17.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature [(H = 0.5t
]
c(CO)
MIN
TYP
MAX
UNIT
ns
‡
8H
§
t
t
t
t
Cycle time, serial-port clock
Fall time, serial-port clock
Rise time, serial-port clock
5.2H
c(SCK)
f(SCK)
r(SCK)
w(SCK)
¶
8
8
ns
¶
ns
Pulse duration, serial-port clock low/high
2.1H
ns
‡
§
When SCK is generated internally.
The serial-port design is fully static and therefore can operate with t
0 Hz but tested at a much higher frequency to minimize test time.
Values derived from characterization data and are not tested.
approaching ∞. It is characterized approaching an input frequency of
c(SCK)
¶
t
f(SCK)
t
w(SCK)
t
w(SCK)
t
r(SCK)
TCLK
t
t
c(SCK)
d(TCV-TDV)
B14
h(TCH-TDV)
B15
TDAT
TADD
B0
h(TCH-TDV)
B13
A2
B12
A3
B8 B7
B2
B1
B0
t
t
t
d(TC-TDV)
A1
A7
t
d(TCH-TFV)
A0
t
d(TCH-TFV)
TFRM
Figure 18. Serial-Port Transmit Timing in TDM Mode
27
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020 – JUNE 1996
MECHANICAL DATA
HFG (S-CQFP-F132)
CERAMIC QUAD FLATPACK WITH TIE-BAR
0.960 (24,38)
0.945 (24,00)
TYP SQ
0.800 (20,32) TYP SQ
”A”
0.225 (5,72)
0.175 (4,45)
Tie Bar Width
33
1
34
2.025 (51,44) MAX
66
132
1.210 (30,73)
TYP
2.015 (51,18)
1.990 (50,55)
100
67
99
“C”
“B”
0.061 (1,55)
DIA TYP
0.059 (1,50)
0.013 (0,33)
132
0.006 (0,15)
Braze
0.014 (0,36)
0.002 (0,05)
0.040 (1,02)
0.030 (0,76)
0.010 (0,25)
0.005 (0,12)
0.020 (0,51) MAX
0.025 (0,64)
DETAIL “A”
0.116 (2,95) MAX
DETAIL “B”
DETAIL “C”
4040231-8/F 04/96
NOTES: A. All linear dimensions are in inches (millimeters)..
B. This drawing is subject to change without notice.
C. Ceramic quad flatpack with flat leads brazed to non-conductive tie bar carrier.
D. This package can be hermetically sealed with a metal lid.
E. The terminals will be gold plated.
28
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020 – JUNE 1996
MECHANICAL DATA
GFA (S-CPGA-P141)
CERAMIC PIN GRID ARRAY PACKAGE
1.080 (27,43)
1.040 (26,42)
SQ
0.900 (22,86) TYP
0.100 (2,54) TYP
0.050 (1,27) TYP
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
2
4
6
8
10 12 14 16 18
9 11 13 15 17 19
1
3
5
7
0.026 (0,66)
0.006 (0,15)
0.145 (3,68)
0.105 (2,67)
0.034 (0,86) TYP
0.140 (3,56)
0.120 (3,05)
0.022 (0,56)
0.016 (0,41)
DIA TYP
0.048 (1,22) DIA TYP
4 Places
4040133/D 04/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-128
29
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ320C50/SMQ320C50
DIGITAL SIGNAL PROCESSOR
SGUS020 – JUNE 1996
MECHANICAL DATA
PQ (S-PQFP-G***)
PLASTIC QUAD FLATPACK
100 LEAD SHOWN
13
1 100
89
14
88
0.012 (0,30)
0.006 (0,15)
M
0.008 (0,20)
”D3” SQ
0.025 (0,635)
0.006 (0,16) NOM
64
38
0.150 (3,81)
0.130 (3,30)
39
63
Gage Plane
”D1” SQ
”D” SQ
0.010 (0,25)
0.020 (0,51) MIN
Seating Plane
”D2” SQ
0°–8°
0.046 (1,17)
0.036 (0,91)
0.004 (0,10)
0.180 (4,57) MAX
LEADS ***
100
132
DIM
MAX
MIN
0.890 (22,61)
0.870 (22,10)
0.766 (19,46)
0.734 (18,64)
0.912 (23,16)
0.888 (22,56)
0.600 (15,24)
1.090 (27,69)
1.070 (27,18)
0.966 (24,54)
0.934 (23,72)
1.112 (28,25)
1.088 (27,64)
0.800 (20,32)
”D”
MAX
MIN
”D1”
MAX
MIN
”D2”
”D3”
NOM
4040045/C 11/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-069
30
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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