SMJ320C6413ZTSA500 [TI]
Fixed-Point Digital Signal Processors; 定点数字信号处理器
| 型号： | SMJ320C6413ZTSA500 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Fixed-Point Digital Signal Processors |
| 文件： | 总140页 (文件大小：1932K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMS320C6413, TMS320C6410
Fixed-Point Digital Signal
Processors
Data Manual
Literature Number: SPRS247E
April 2004 − Revised May 2005
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
This page intentionally left blank
Revision History
Revision History
This data manual revision history highlights the technical changes made to the SPRS247D device-specific data
manual to make it an SPRS247E revision.
Scope: Applicable updates to the C64x device family, specifically relating to the TMS320C6413 and
TMS320C6410 devices, have been incorporated.
PAGE(s)
ADDS/CHANGES/DELETES
NO.
63
Terminal Functions table:
Host-port data [7:0] pins (I/O/Z) description:
Changed sentence from “Host-Port bus width user-configurable at device reset via a 10-kW resistor pullup/pulldown resistor
on the HD5 pin (I):“ to “Host-Port bus width user-configurable at device reset via a 1-kW pullup/pulldown resistor on the HD5
pin (I):“
78
90
I2C section:
Updated/added “For more detailed information...” paragraph
Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature:
I
Low-level output current, TEST CONDITIONS:
OH,
Moved/added HPI to “Timer, TDO, GPIO, McBSP”
3
April 2004 − Revised May 2005
SPRS247E
Contents
Section
Contents
Page
1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2
Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1
2.2
2.3
GTS and ZTS BGA Packages (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Device Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.1
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4
2.5
CPU (DSP Core) Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Memory Map Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.5.1
L2 Architecture Expanded . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.6
2.7
2.8
2.9
Peripheral Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
EDMA Channel Synchronization Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Interrupt Sources and Interrupt Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Signal Groups Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3
4
4
Device Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
3.12
Device Configuration at Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Peripheral Configuration at Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Peripheral Selection After Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Peripheral Configuration Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Device Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
JTAG ID Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Multiplexed Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Debugging Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Configuration Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.12.1
3.12.2
Device and Development-Support Tool Nomenclature . . . . . . . . . . . . . . . . . . . . . 68
Documentation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Peripherals Detailed Description (Device-Specific) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
4.1
4.2
4.3
Clock PLL and Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Host-Port Interface (HPI) Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Multichannel Audio Serial Port (McASP) Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
4.3.1
McASP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
4.4
4.5
4.6
I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
General-Purpose Input/Output (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Power-Down Modes Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
4.6.1
4.6.2
Triggering, Wake-up, and Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
C64x Power-Down Mode with an Emulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
4.7
Power-Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
4.7.1 Power-Supply Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
4.8
4.9
Power-Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Peripheral Power-Down Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
SPRS247E
April 2004 − Revised May 2005
Contents
Page
Section
4.10
IEEE 1149.1 JTAG Compatibility Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
EMIF Device Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Bootmode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
4.11
4.12
4.13
5
Device Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.1
5.2
5.3
Absolute Maximum Ratings Over Operating Case Temperature Range . . . . . . . . . . . . . . . . . . 89
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case
Temperature (Unless Otherwise Noted) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
5.4
Recommended Clock and Control Signal Transition Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6
7
Parameter Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.1
6.2
6.3
Signal Transition Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Signal Transition Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Timing Parameters and Board Routing Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Peripheral Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
Input and Output Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Asynchronous Memory Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Programmable Synchronous Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Synchronous DRAM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
HOLD/HOLDA Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
BUSREQ Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Multichannel Audio Serial Port (McASP) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Inter-Integrated Circuits (I2C) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Host-Port Interface (HPI) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Multichannel Buffered Serial Port (McBSP) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
General-Purpose Input/Output (GPIO) Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
JTAG Test-Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
7.9
7.10
7.11
7.12
7.13
7.14
7.15
8
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
8.1
8.2
Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
5
April 2004 − Revised May 2005
SPRS247E
Figures
Figure
List of Figures
Page
2−1
2−2
2−3
2−4
2−5
2−6
2−7
GTS and ZTS BGA Packages (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
TMS320C64xE CPU (DSP Core) Data Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
TMS320C6413 L2 Architecture Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
TMS320C6410 L2 Architecture Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
CPU and Peripheral Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Peripheral Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3−1
3−2
3−3
3−4
3−5
3−6
Peripheral Configuration Register (PERCFG) [Address Location: 0x01B3F000] . . . . . . . . . . . . . . . . . . 46
Peripheral Enable/Disable Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
PCFGLOCK Register Diagram [Address Location: 0x01B3 F018] − Read/Write Accesses . . . . . . . . 49
Device Status Register (DEVSTAT) Description − 0x01B3 F004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
JTAG ID Register Description − TMS320C6413/C6410 Register Value − 0x0007 902F . . . . . . . . . . . . 51
Configuration Example A
(HPI16 + 2 McASPs + 2 McBSPs +2 I2Cs + EMIF + 3 Timers + GPIO) . . . . . . . . . . . . . . . . . . . . . . . . 54
3−7
TMS320C6413/C6410 DSP Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
4−1
4−2
4−3
4−4
4−5
4−6
4−7
4−8
External PLL Circuitry for Either PLL Multiply Modes or x1 (Bypass) Mode . . . . . . . . . . . . . . . . . . . . . . 72
McASP0 and McASP1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
I2Cx Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
GPIO Enable Register (GPEN) [Hex Address: 01B0 0000] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
GPIO Direction Register (GPDIR) [Hex Address: 01B0 0004] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Power-Down Mode Logic† . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
PWRD Field of the CSR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Schottky Diode Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6−1
6−2
6−3
6−4
Test Load Circuit for AC Timing Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Input and Output Voltage Reference Levels for AC Timing Measurements . . . . . . . . . . . . . . . . . . . . . . 91
Rise and Fall Transition Time Voltage Reference Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Board-Level Input/Output Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
7−1
7−2
7−3
7−4
7−5
7−6
7−7
7−8
CLKIN Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
CLKOUT4 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
CLKOUT6 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
AECLKIN Timing for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
AECLKOUT1 Timing for the EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
AECLKOUT2 Timing for the EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Asynchronous Memory Read Timing for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Asynchronous Memory Write Timing for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
6
SPRS247E
April 2004 − Revised May 2005
Figures
7−9
Programmable Synchronous Interface Read Timing for EMIFA
(With Read Latency = 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
7−10
7−11
Programmable Synchronous Interface Write Timing for EMIFA
(With Write Latency = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Programmable Synchronous Interface Write Timing for EMIFA
(With Write Latency = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
7−12
7−13
7−14
7−15
7−16
7−17
7−18
7−19
7−20
7−21
7−22
7−23
7−24
7−25
7−26
7−27
7−28
7−29
7−30
7−31
7−32
7−33
7−34
7−35
7−36
7−37
7−38
7−39
7−40
7−41
7−42
7−43
7−44
SDRAM Read Command (CAS Latency 3) for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
SDRAM Write Command for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
SDRAM ACTV Command for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
SDRAM DCAB Command for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
SDRAM DEAC Command for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
SDRAM REFR Command for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
SDRAM MRS Command for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
SDRAM Self-Refresh Timing for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
HOLD/HOLDA Timing for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
BUSREQ Timing for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
External/NMI Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
McASP Input Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
McASP Output Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
I2C Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
I2C Transmit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
HPI16 Read Timing (HAS Not Used, Tied High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
HPI16 Read Timing (HAS Used) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
HPI16 Write Timing (HAS Not Used, Tied High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
HPI16 Write Timing (HAS Used) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
HPI32 Read Timing (HAS Not Used, Tied High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
HPI32 Read Timing (HAS Used) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
HPI32 Write Timing (HAS Not Used, Tied High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
HPI32 Write Timing (HAS Used) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
McBSP Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
FSR Timing When GSYNC = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 128
McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 129
McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 130
McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
GPIO Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
JTAG Test-Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
7
April 2004 − Revised May 2005
SPRS247E
Tables
Table
List of Tables
Page
2−1
2−2
2−3
2−4
2−5
2−6
2−7
2−8
Characteristics of the C6413 and C6410 Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
TMS320C6413/C6410 Memory Map Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
EMIFA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
L2 Cache Registers (C64x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Quick DMA (QDMA) and Pseudo Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
EDMA Registers (C64x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
EDMA Parameter RAM (C64x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Interrupt Selector Registers (C64x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Device Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
McBSP 0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
McBSP 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Timer 0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Timer 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Timer 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
HPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
GP0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
McASP0 and McASP1 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
McASP0 Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
McASP1 Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
I2C0 and I2C1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
TMS320C6413/C6410 EDMA Channel Synchronization Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
C6413/C6410 DSP Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2−9
2−10
2−11
2−12
2−13
2−14
2−15
2−16
2−17
2−18
2−19
2−20
2−21
2−22
3−1
C6413/C6410 Device Configuration Pins (TOUT1/LENDIAN, AEA[22:19], TOUT0/HPI_EN,
HD5, CLKINSEL, and OSC_DIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3−2
3−3
3−4
3−5
3−6
3−7
3−8
3−9
TOUT0/HPI_EN and HD5 Peripheral Selection (HPI or McASP1 and Select GP0 Pins) . . . . . . . . . . . 45
Peripheral Configuration (PERCFG) Register Selection Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . 47
PCFGLOCK Register Selection Bit Descriptions − Read Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
PCFGLOCK Register Selection Bit Descriptions − Write Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Device Status (DEVSTAT) Register Selection Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
JTAG ID Register Selection Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
C6413/C6410 Device Multiplexed Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4−1
4−2
TMS320C6413 PLL Multiply Factor Options, Clock Frequency Ranges,
and Typical Lock Time for −500 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
TMS320C6410 PLL Multiply Factor Options, Clock Frequency Ranges,
and Typical Lock Time for −400 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
4−3
4−4
Crystal and Tank Circuit Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Characteristics of the Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6−1
7−1
Board-Level Timing Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Timing Requirements for External Crystal Oscillator Input (OSCIN and OSCOUT) . . . . . . . . . . . . . . . 93
8
SPRS247E
April 2004 − Revised May 2005
Tables
Page
Table
7−2
7−3
7−4
7−5
7−6
Timing Requirements for CLKIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Switching Characteristics Over Recommended Operating Conditions for CLKOUT4 . . . . . . . . . . . . . . 94
Switching Characteristics Over Recommended Operating Conditions for CLKOUT6 . . . . . . . . . . . . . . 94
Timing Requirements for AECLKIN for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Switching Characteristics Over Recommended Operating Conditions for AECLKOUT1
for the EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
7−7
Switching Characteristics Over Recommended Operating Conditions for AECLKOUT2
for the EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
7−8
7−9
Timing Requirements for Asynchronous Memory Cycles for EMIFA Module . . . . . . . . . . . . . . . . . . . . . 97
Switching Characteristics Over Recommended Operating Conditions for Asynchronous
Memory Cycles for EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
7−10
7−11
Timing Requirements for Programmable Synchronous Interface Cycles for EMIFA Module . . . . . . . 100
Switching Characteristics Over Recommended Operating Conditions for Programmable Synchronous
Interface Cycles for EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7−12
7−13
Timing Requirements for Synchronous DRAM Cycles for EMIFA Module . . . . . . . . . . . . . . . . . . . . . . 104
Switching Characteristics Over Recommended Operating Conditions for Synchronous DRAM
Cycles for EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
7−14
7−15
Timing Requirements for the HOLD/HOLDA Cycles for EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . 110
Switching Characteristics Over Recommended Operating Conditions for the HOLD/HOLDA
Cycles for EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
7−16
Switching Characteristics Over Recommended Operating Conditions for the BUSREQ
Cycles for EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
7−17
7−18
7−19
7−20
7−21
7−22
7−23
7−24
7−25
Timing Requirements for Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Switching Characteristics Over Recommended Operating Conditions During Reset . . . . . . . . . . . . . 112
Timing Requirements for External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Timing Requirements for McASP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Switching Characteristics Over Recommended Operating Conditions for McASP . . . . . . . . . . . . . . . 115
Timing Requirements for I2C Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Switching Characteristics for I2C Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Timing Requirements for Host-Port Interface Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Switching Characteristics Over Recommended Operating Conditions During Host-Port
Interface Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
7−26
7−27
7−28
7−29
Timing Requirements for McBSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Switching Characteristics Over Recommended Operating Conditions for McBSP . . . . . . . . . . . . . . . 126
Timing Requirements for FSR When GSYNC = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Timing Requirements for McBSP as SPI Master or Slave:
CLKSTP = 10b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
7−30
7−31
7−32
7−33
7−34
Switching Characteristics Over Recommended Operating Conditions for McBSP as
SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Timing Requirements for McBSP as SPI Master or Slave:
CLKSTP = 11b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Switching Characteristics Over Recommended Operating Conditions for McBSP as
SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Timing Requirements for McBSP as SPI Master or Slave:
CLKSTP = 10b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Switching Characteristics Over Recommended Operating Conditions for McBSP as
SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
7−35
Timing Requirements for McBSP as SPI Master or Slave:
CLKSTP = 11b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
9
April 2004 − Revised May 2005
SPRS247E
Tables
7−36
Switching Characteristics Over Recommended Operating Conditions for McBSP as
SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
7−37
7−38
7−39
7−40
7−41
7−42
Timing Requirements for Timer Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Switching Characteristics Over Recommended Operating Conditions for Timer Outputs . . . . . . . . . 132
Timing Requirements for GPIO Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs . . . . . . . . . 133
Timing Requirements for JTAG Test Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port . . . . . . . . 134
8−1
8−2
Thermal Resistance Characteristics (S-PBGA Package) [GTS] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Thermal Resistance Characteristics (S-PBGA Package) [ZTS] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
10
SPRS247E
April 2004 − Revised May 2005
Features
1
Features
D
High-Performance Fixed-Point Digital
Signal Processor (TMS320C6413/C6410)
− TMS320C6413
D
L1/L2 Memory Architecture
− 128K-Bit (16K-Byte) L1P Program Cache
(Direct Mapped)
− 2-ns Instruction Cycle Time
− 500-MHz Clock Rate
− 4000 MIPS
− 128K-Bit (16K-Byte) L1D Data Cache
(2-Way Set-Associative)
− 2M-Bit (256K-Byte) L2 Unified Mapped
RAM/Cache [C6413]
− TMS320C6410
− 2.5-ns Instruction Cycle Time
− 400-MHz Clock Rate
− 3200 MIPS
(Flexible RAM/Cache Allocation)
− 1M-Bit (128K-Byte) L2 Unified Mapped
RAM/Cache [C6410]
− Eight 32-Bit Instructions/Cycle
− Fully Software-Compatible With C64x™
− Extended Temperature Devices Available
(Flexible RAM/Cache Allocation)
D
D
Endianess: Little Endian, Big Endian
32-Bit External Memory Interface (EMIF)
− Glueless Interface to Asynchronous
Memories (SRAM and EPROM) and
Synchronous Memories (SDRAM,
SBSRAM, ZBT SRAM, and FIFO)
− 1024M-Byte Total Addressable External
Memory Space
D
VelociTI.2™ Extensions to VelociTI™
Advanced Very-Long-Instruction-Word
(VLIW) TMS320C64x™ DSP Core
− Eight Highly Independent Functional
Units With VelociTI.2™ Extensions:
− Six ALUs (32-/40-Bit), Each Supports
Single 32-Bit, Dual 16-Bit, or Quad
8-Bit Arithmetic per Clock Cycle
− Two Multipliers Support
D
Enhanced Direct-Memory-Access (EDMA)
Controller (64 Independent Channels)
D
D
Host-Port Interface (HPI) [32-/16-Bit]
Four 16 x 16-Bit Multiplies
(32-Bit Results) per Clock Cycle or
Eight 8 x 8-Bit Multiplies
Two Multichannel Audio Serial Ports
(McASPs) - with Six Serial Data Pins each
(16-Bit Results) per Clock Cycle
− Load-Store Architecture With
Non-Aligned Support
− 64 32-Bit General-Purpose Registers
− Instruction Packing Reduces Code Size
− All Instructions Conditional
2
D
Two Inter-Integrated Circuit (I C) Buses
− Additional GPIO Capability
D
D
D
D
D
D
Two Multichannel Buffered Serial Ports
Three 32-Bit General-Purpose Timers
Sixteen General-Purpose I/O (GPIO) Pins
Flexible PLL Clock Generator
D
D
Instruction Set Features
− Byte-Addressable (8-/16-/32-/64-Bit Data)
− 8-Bit Overflow Protection
− Bit-Field Extract, Set, Clear
− Normalization, Saturation, Bit-Counting
− VelociTI.2™ Increased Orthogonality
VelociTI.2™ Extensions to VelociTI™
Advanced Very-Long-Instruction-Word
(VLIW) TMS320C64x™ DSP Core
On-Chip Fundamental Oscillator
†
IEEE-1149.1 (JTAG )
Boundary-Scan-Compatible
D
288-Pin Ball Grid Array (BGA) Packages
(GTS and ZTS Suffixes), 1.0-mm Ball Pitch
D
D
0.13-µm/6-Level Cu Metal Process (CMOS)
3.3-V I/Os, 1.2-V Internal
VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
†
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
11
April 2004 − Revised May 2005
SPRS247E
Functional Overview
2
Functional Overview
2.1
GTS and ZTS BGA Packages (Bottom View)
GTS and ZTS 288-PIN BALL GRID ARRAY (BGA) PACKAGES
(BOTTOM VIEW)
AB
Y
AA
W
U
V
T
R
P
N
M
K
L
J
H
F
G
E
D
B
C
A
1
3
5
7
9
11 13 15 17 19 21
10 12 14 16 18 20 22
2
4
6
8
Figure 2−1. GTS and ZTS BGA Packages (Bottom View)
12
SPRS247E
April 2004 − Revised May 2005
Description
2.2
Description
The TMS320C64x™ DSPs (including the TMS320C6413, TMS320C6410 devices) are the
highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The TMS320C6413
and TMS320C6410 (C6413 and C6410) devices are based on the second-generation high-performance,
advanced VelociTI™ very-long-instruction-word (VLIW) architecture (VelociTI.2™) developed by Texas
Instruments (TI). The high-performance, lower-cost C6413/C6410 DSPs enable customers to reduce system
costs for telecom, medical, industrial, office, and photo lab equipment. The C64x™ is a code-compatible
member of the C6000™ DSP platform.
With performance of up to 4000 million instructions per second (MIPS) at a clock rate of 500 MHz, the C6413
device offers cost-effective solutions to high-performance DSP programming challenges.
With performance of up to 3200 million instructions per second (MIPS) at a clock rate of 400 MHz, the C6410
device offers cost-effective solutions to high-performance DSP programming challenges. The C6410 device
also provides excellent value for packet telephony and for other cost−sensitive applications demanding high
performance.
The C6413/C6410 DSP possesses the operational flexibility of high-speed controllers and the numerical
capability of array processors. The C64x™ DSP core processor has 64 general-purpose registers of 32-bit
word length and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic
logic units (ALUs)— with VelociTI.2™ extensions. The VelociTI.2™ extensions in the eight functional units
include new instructions to accelerate the performance in video and imaging applications and extend the
parallelism of the VelociTI™ architecture. The C6413 can produce four 16-bit multiply-accumulates (MACs)
per cycle for a total of 2000 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of
4000 MMACS. The C6410 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of
1600 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 3200 MMACS. The
C6413/C6410 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip
peripherals similar to the other C6000™ DSP platform devices.
The C6413/C6410 uses a two-level cache-based architecture and has a powerful and diverse set of
peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache
(L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 2-Mbit
memory space that is shared between program and data space [for C6413 device] and the Level 2
memory/cache (L2) consists of an 1-Mbit memory space that is shared between program and data space [for
C6410 device]. L2 memory can be configured as mapped memory, cache, or combinations of the two. The
peripheral set includes: two multichannel buffered audio serial ports (McASPs); two inter-integrated circuit bus
modules (I2Cs) ; two multichannel buffered serial ports (McBSPs); three 32-bit general-purpose timers; a
user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a 16-pin general-purpose input/output
port (GP0) with programmable interrupt/event generation modes; and a 32-bit glueless external memory
interface (EMIFA), which is capable of interfacing to synchronous and asynchronous memories and
peripherals.
Each McASP port supports one transmit and one receive clock zone, with six serial data pins which can be
individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin
from 2 to 32 time slots. The C6413/C6410 has sufficient bandwidth to support all six serial data pins
transmitting a 192-kHz stereo signal. Serial data in each zone may be transmitted and received on multiple
2
serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I S)
format.
In addition, the McASP transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3, CP-430
encoded data channels simultaneously, with a single RAM containing the full implementation of user data and
channel status fields.
McASP also provides extensive error-checking and recovery features, such as the bad clock detection circuit
for each high-frequency master clock which verifies that the master clock is within a programmed frequency
range.
TMS320C6000, and C6000 are trademarks of Texas Instruments.
13
April 2004 − Revised May 2005
SPRS247E
Device Characteristics
The I2C ports on the TMS320C6413/C6410 allows the DSP to easily control peripheral devices and
communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may
be used to communicate with serial peripheral interface (SPI) mode peripheral devices.
The C6413/C6410 has a complete set of development tools which includes: a new C compiler, an assembly
optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into
source code execution.
2.3
Device Characteristics
Table 2−1, provides an overview of the C6413 and C6410 DSPs. The tables show significant features of the
C6413 and C6410 devices, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and
the package type with pin count.
Table 2−1. Characteristics of the C6413 and C6410 Processors
HARDWARE FEATURES
C6413 AND C6410
EMIFA (32-bit bus width)
(clock source = AECLKIN, CLKOUT4, or CLKOUT6)
1
EDMA (64 independent channels)
McASPs (use Peripheral Clock and AUXCLK)
I2Cs (use Peripheral Clock)
1
Peripherals
2
2
Not all peripherals pins
are available at the
HPI (32- or 16-bit user selectable)
1 (HPI16 or HPI32)
same time (For more
detail, see the Device
Configuration section).
McBSPs
2
(internal clock source = CPU/4 clock frequency)
32-Bit Timers
(internal clock source = CPU/8 clock frequency)
3
General-Purpose Input/Output Port (GP0)
16
288K (C6413)
160K (C6410)
Size (Bytes)
16K-Byte (16KB) L1 Program (L1P) Cache
16KB L1 Data (L1D) Cache
256KB Unified Mapped RAM/Cache (L2) [C6413]
128KB Unified Mapped RAM/Cache (L2) [C6410]
On-Chip Memory
Organization
CPU ID + CPU Rev ID
JTAG BSDL_ID
Control Status Register (CSR.[31:16])
0x0C01
JTAGID register (address location: 0x01B3F008)
0x0007902F
500 (C6413)
400 (C6410)
Frequency
MHz
ns
2 ns (C6413-500, C6413 A−500)
[500 MHz CPU, 100 MHz EMIF ]
2.5 ns (C6410-400, C6410 A−400)
[400 MHz CPU, 100 MHz EMIF ]
†
Cycle Time
†
Core (V)
I/O (V)
1.2 V
3.3 V
Voltage
Bypass (x1), x5, x6, x7, x8, x9, x10, x11, x12, x16,
x18, x19, x20, x21, x22, and x24
PLL Options
CLKIN frequency multiplier
BGA Package
23 x 23 mm
288-Pin Flip-Chip Plastic BGA (GTS and ZTS)
Process Technology
µm
0.13 µm
Product Preview (PP), Advance Information (AI),
or Production Data (PD)
‡
Product Status
PD
†
‡
On this C64x™ device, the rated EMIF speed affects only the SDRAM interface on the EMIF. For more detailed information, see the EMIF device
speed portion of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard
warranty. Production processing does not necessarily include testing of all parameters.
14
SPRS247E
April 2004 − Revised May 2005
Functional Block Diagram
2.3.1
Functional Block Diagram
Figure 2−2 shows the functional block diagram of the C6413/C6410 device.
32
TMS320C6413/C6410
SDRAM
SBSRAM
EMIF A
L1P Cache
Direct-Mapped
16K Bytes Total
ZBT SRAM
FIFO
Timer 2
Timer 1
Timer 0
SRAM
C64x DSP Core
ROM/FLASH
I/O Devices
Instruction Fetch
Control
Registers
Instruction Dispatch
Advanced Instruction Packet
Control
Logic
McBSP0
McBSP1
Instruction Decode
Data Path A
Data Path B
Test
A Register File
A31−A16
B Register File
B31−B16
Advanced
In-Circuit
Emulation
A15−A0
B15−B0
McASP0
.L1 .S1 .M1 .D1
.D2 .M2 .S2 .L2
Interrupt
Control
L2
Cache
Memory
Enhanced
DMA
Controller
(edma)
McASP1
§
256KBytes
L1D Cache 2-Way Set-Associative
16K Bytes Total
HPI16
or
HPI32
Power-Down
Logic
OSCILLATOR
and PLL
(x1, x5 − x12, x16,
x18, x19 − x22, x24)
I2C0
I2C1
16
‡
Boot Configuration
GP0
†
McBSPs: Framing Chips − H.100, MVIP, SCSA, T1, E1; AC97 Devices; SPI Devices; Codecs
GP0[15:8] pins are muxed with the HPI HD[15:8] pins and GP0[2:1] pins are muxed with CLKOUT6 and CLKOUT4,
respectively.
‡
§
Note: the C6413 device has 256K-Bytes L2 Cache Memory; the C6410 device has only 128K-Bytes L2 Cache Memory.
Figure 2−2. Functional Block Diagram
15
April 2004 − Revised May 2005
SPRS247E
CPU (DSP Core) Description
2.4
CPU (DSP Core) Description
The CPU fetches VelociTI™ advanced very-long instruction words (VLIWs) (256 bits wide) to supply up to
eight 32-bit instructions to the eight functional units during every clock cycle. The VelociTI™ VLIW architecture
features controls by which all eight units do not have to be supplied with instructions if they are not ready to
execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute
packet as the previous instruction, or whether it should be executed in the following clock as a part of the next
execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The
variable-length execute packets are a key memory-saving feature, distinguishing the C64x CPUs from other
VLIW architectures. The C64x™ VelociTI.2™ extensions add enhancements to the TMS320C62x™ DSP
VelociTI™ architecture. These enhancements include:
•
•
•
•
•
•
Register file enhancements
Data path extensions
Quad 8-bit and dual 16-bit extensions with data flow enhancements
Additional functional unit hardware
Increased orthogonality of the instruction set
Additional instructions that reduce code size and increase register flexibility
The CPU features two sets of functional units. Each set contains four units and a register file. One set contains
functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register
files each contain 32 32-bit registers for a total of 64 general-purpose registers. In addition to supporting the
packed 16-bit and 32-/40-bit fixed-point data types found in the C62x™ VelociTI™ VLIW architecture, the
C64x™ register files also support packed 8-bit data and 64-bit fixed-point data types. The two sets of functional
units, along with two register files, compose sides A and B of the CPU [see the functional block and CPU (DSP
core) diagram, and Figure 2−3]. The four functional units on each side of the CPU can freely share the 32
registers belonging to that side. Additionally, each side features a “data cross path”—a single data bus
connected to all the registers on the other side, by which the two sets of functional units can access data from
the register files on the opposite side. The C64x CPU pipelines data-cross-path accesses over multiple clock
cycles. This allows the same register to be used as a data-cross-path operand by multiple functional units in
the same execute packet. All functional units in the C64x CPU can access operands via the data cross path.
Register access by functional units on the same side of the CPU as the register file can service all the units
in a single clock cycle. On the C64x CPU, a delay clock is introduced whenever an instruction attempts to read
a register via a data cross path if that register was updated in the previous clock cycle.
In addition to the C62x™ DSP fixed-point instructions, the C64x™ DSP includes a comprehensive collection
of quad 8-bit and dual 16-bit instruction set extensions. These VelociTI.2™ extensions allow the C64x CPU
to operate directly on packed data to streamline data flow and increase instruction set efficiency.
Another key feature of the C64x CPU is the load/store architecture, where all instructions operate on registers
(as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data
transfers between the register files and the memory. The data address driven by the .D units allows data
addresses generated from one register file to be used to load or store data to or from the other register file.
The C64x .D units can load and store bytes (8 bits), half-words (16 bits), and words (32 bits) with a single
instruction. And with the new data path extensions, the C64x .D unit can load and store doublewords (64 bits)
with a single instruction. Furthermore, the non-aligned load and store instructions allow the .D units to access
words and doublewords on any byte boundary. The C64x CPU supports a variety of indirect addressing modes
using either linear- or circular-addressing with 5- or 15-bit offsets. All instructions are conditional, and most
can access any one of the 64 registers. Some registers, however, are singled out to support specific
addressing modes or to hold the condition for conditional instructions (if the condition is not automatically
“true”).
TMS320C62x and C62x are trademarks of Texas Instruments.
16
SPRS247E
April 2004 − Revised May 2005
CPU (DSP Core) Description
The two .M functional units perform all multiplication operations. Each of the C64x .M units can perform two
16 × 16-bit multiplies or four 8 ×8-bit multiplies per clock cycle. The .M unit can also perform 16 ×32-bit multiply
operations, dual 16 × 16-bit multiplies with add/subtract operations, and quad 8 × 8-bit multiplies with add
operations. In addition to standard multiplies, the C64x .M units include bit-count, rotate, Galois field multiplies,
and bidirectional variable shift hardware.
The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results
available every clock cycle. The arithmetic and logical functions on the C64x CPU include single 32-bit, dual
16-bit, and quad 8-bit operations.
The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory.
The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least
significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous
execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain,
effectively placing the instructions that follow it in the next execute packet. A C64x™ DSP device enhancement
now allows execute packets to cross fetch-packet boundaries. In the TMS320C62x™/TMS320C67x™ DSP
devices, if an execute packet crosses the fetch-packet boundary (256 bits wide), the assembler places it in
the next fetch packet, while the remainder of the current fetch packet is padded with NOP instructions. In the
C64x™ DSP device, the execute boundary restrictions have been removed, thereby, eliminating all of the
NOPs added to pad the fetch packet, and thus, decreasing the overall code size. The number of execute
packets within a fetch packet can vary from one to eight. Execute packets are dispatched to their respective
functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the
execute packets from the current fetch packet have been dispatched. After decoding, the instructions
simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock
cycle. While most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes,
half-words, or doublewords. All load and store instructions are byte-, half-word-, word-, or
doubleword-addressable.
For more details on the C64x CPU functional units enhancements, see the following documents:
•
•
TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189)
TMS320C64x Technical Overview (literature number SPRU395)
TMS320C67x is a trademark of Texas Instruments.
17
April 2004 − Revised May 2005
SPRS247E
CPU (DSP Core) Description
src1
.L1
src2
dst
8
long dst
long src
8
32 MSBs
32 LSBs
ST1b (Store Data)
ST1a (Store Data)
8
long src
long dst
dst
8
Register
File A
(A0−A31)
src1
.S1
Data Path A
src2
See Note A
long dst
dst
See Note A
src1
.M1
src2
32 MSBs
32 LSBs
LD1b (Load Data)
LD1a (Load Data)
dst
DA1 (Address)
src1
.D1
.D2
src2
2X
1X
src2
src1
dst
DA2 (Address)
32 LSBs
32 MSBs
LD2a (Load Data)
LD2b (Load Data)
src2
src1
dst
.M2
See Note A
See Note A
long dst
Register
src2
File B
Data Path B
.S2
(B0− B31)
src1
dst
long dst
long src
8
8
32 MSBs
32 LSBs
ST2a (Store Data)
ST2b (Store Data)
8
long src
long dst
dst
8
src2
.L2
src1
Control Register
File
NOTE A: For the .M functional units, the long dst is 32 MSBs and the dst is 32 LSBs.
Figure 2−3. TMS320C64x™ CPU (DSP Core) Data Paths
18
SPRS247E
April 2004 − Revised May 2005
Memory Map Summary
2.5
Memory Map Summary
Table 2−2 shows the memory map address ranges of the C6413 and C6410 devices. Internal memory is
always located at address 0 and can be used as both program and data memory. The external memory
address ranges in the C6413/C6410 device begin at the hex address location 0x8000 0000 for EMIFA.
Table 2−2. TMS320C6413/C6410 Memory Map Summary
BLOCK SIZE
MEMORY BLOCK DESCRIPTION
Internal RAM (L2) [C6413]
HEX ADDRESS RANGE
(BYTES)
256K
0000 0000 – 0003 FFFF
0004 0000 – 000F FFFF
0000 0000 – 0001 FFFF
0002 0000 – 000F FFFF
0010 0000 – 00FF FFFF
0100 0000 – 017F FFFF
0180 0000 – 0183 FFFF
0184 0000 – 0187 FFFF
0188 0000 – 018B FFFF
018C 0000 – 018F FFFF
0190 0000 – 0193 FFFF
0194 0000 – 0197 FFFF
0198 0000 – 019B FFFF
019C 0000 – 019F FFFF
01A0 0000 – 01A3 FFFF
01A4 0000 – 01AB FFFF
01AC 0000 – 01AF FFFF
01B0 0000 – 01B3 EFFF
01B3 F000 – 01B3 FFFF
01B4 0000 – 01B4 3FFF
01B4 4000 – 01B4 7FFF
01B4 8000 – 01B4 BFFF
01B4 C000 – 01B4 FFFF
01B5 0000 – 01B5 3FFF
01B5 4000 – 01B7 FFFF
01B8 0000 – 01B9 FFFF
01BA 0000 – 01BB FFFF
01BC 0000 – 01BF FFFF
01C0 0000 – 01C8 3FFF
01C8 4000 – 01FF FFFF
0200 0000 – 0200 0033
0200 0034 – 2FFF FFFF
3000 0000 – 33FF FFFF
3400 0000 – 37FF FFFF
3800 0000 – 3BFF FFFF
3C00 0000 – 3C0F FFFF
Reserved [C6413]
Internal RAM (L2) [C6410]
Reserved [C6410]
Reserved
1024K minus 256K
128K
1024K minus 128K
15M
Reserved
8M
External Memory Interface A (EMIFA) Registers
L2 Registers
256K
256K
HPI Registers
256K
McBSP 0 Registers
McBSP 1 Registers
Timer 0 Registers
Timer 1 Registers
Interrupt Selector Registers
EDMA RAM and EDMA Registers
Reserved
256K
256K
256K
256K
256K
256K
512K
Timer 2 Registers
GP0 Registers
256K
256K minus 4K
4K
Device Configuration Registers
I2C0 Data and Control Registers
I2C1 Data and Control Registers
Reserved
16K
16K
16K
McASP0 Control Registers
McASP1 Control Registers
Reserved
16K
16K
176K
Reserved
128K
Reserved
128K
Emulation
256K
Reserved
528K
Reserved
3.5M
QDMA Registers
Reserved
52
928M minus 52
64M
McBSP 0 Data
McBSP 1 Data
64M
Reserved
64M
McASP0 Data
1M
19
April 2004 − Revised May 2005
SPRS247E
Memory Map Summary
Table 2−2. TMS320C6413/C6410 Memory Map Summary (Continued)
BLOCK SIZE
(BYTES)
MEMORY BLOCK DESCRIPTION
HEX ADDRESS RANGE
McASP1 Data
Reserved
1M
3C10 0000 – 3C1F FFFF
3C20 0000 – 3FFF FFFF
4000 0000 – 7FFF FFFF
8000 0000 – 8FFF FFFF
9000 0000 – 9FFF FFFF
A000 0000 – AFFF FFFF
B000 0000 – BFFF FFFF
C000 0000 – FFFF FFFF
62M
Reserved
1G
EMIFA CE0
EMIFA CE1
EMIFA CE2
EMIFA CE3
Reserved
256M
256M
256M
256M
1G
20
SPRS247E
April 2004 − Revised May 2005
Memory Map Summary
2.5.1
L2 Architecture Expanded
Figure 2−4 and Figure 2−5 show the detail of the L2 architecture on the TMS320C6413 and TMS320C6410
devices, respectively . For more information on the L2MODE bits, see the cache configuration (CCFG) register
bit field descriptions in the TMS320C64x Two-Level Internal Memory Reference Guide (literature number
SPRU610).
L2MODE
010
L2 Memory
Block Base Address
000
001
011
111
0x0000 0000
128K-Byte SRAM
0x0002 0000
64K-Byte RAM
0x0003 0000
0x0003 8000
32K-Byte RAM
32K-Byte RAM
0x0003 FFFF
0x0004 0000
Figure 2−4. TMS320C6413 L2 Architecture Memory Configuration
21
April 2004 − Revised May 2005
SPRS247E
Memory Map Summary
†
L2MODE
L2 Memory
Block Base Address
0x0000 0000
000
001 010
011
64K-Byte RAM
0x0001 0000
0x0001 8000
32K-Byte RAM
32K-Byte RAM
0x0001 FFFF
0x0002 0000
†
The L2MODE = 111b is not supported on the C6410 device.
Figure 2−5. TMS320C6410 L2 Architecture Memory Configuration
22
SPRS247E
April 2004 − Revised May 2005
Peripheral Register Descriptions
2.6
Peripheral Register Descriptions
Table 2−3 through Table 2−20 identify the peripheral registers for the C6413/C6410 device by their register
names, acronyms, and hex address or hex address range. For more detailed information on the register
contents, bit names and their descriptions, see the specific peripheral reference guide listed in the
TMS320C6000 DSP Peripherals Overview Reference Guide (literature number SPRU190).
Table 2−3. EMIFA Registers
HEX ADDRESS RANGE
ACRONYM
GBLCTL
CECTL1
CECTL0
−
REGISTER NAME
EMIFA global control
COMMENTS
0180 0000
0180 0004
EMIFA CE1 space control
EMIFA CE0 space control
Reserved
0180 0008
0180 000C
0180 0010
CECTL2
CECTL3
SDCTL
SDTIM
SDEXT
−
EMIFA CE2 space control
EMIFA CE3 space control
EMIFA SDRAM control
0180 0014
0180 0018
0180 001C
EMIFA SDRAM refresh control
EMIFA SDRAM extension
Reserved
0180 0020
0180 0024 − 0180 003C
0180 0040
PDTCTL
CESEC1
CESEC0
−
Peripheral device transfer (PDT) control
EMIFA CE1 space secondary control
EMIFA CE0 space secondary control
Reserved
0180 0044
0180 0048
0180 004C
0180 0050
CESEC2
CESEC3
–
EMIFA CE2 space secondary control
EMIFA CE3 space secondary control
Reserved
0180 0054
0180 0058 − 0183 FFFF
Table 2−4. L2 Cache Registers (C64x)
HEX ADDRESS RANGE
0184 0000
ACRONYM
REGISTER NAME
Cache configuration register
Reserved
COMMENTS
CCFG
0184 0004 − 0184 0FFC
0184 1000
−
EDMAWEIGHT L2 EDMA access control register
0184 1004 − 0184 1FFC
0184 2000
−
Reserved
L2ALLOC0
L2ALLOC1
L2ALLOC2
L2ALLOC3
−
L2 allocation register 0
0184 2004
L2 allocation register 1
0184 2008
L2 allocation register 2
0184 200C
L2 allocation register 3
0184 2010 − 0184 3FFC
0184 4000
Reserved
L2WBAR
L2WWC
L2WIBAR
L2WIWC
L2IBAR
L2 writeback base address register
L2 writeback word count register
L2 writeback invalidate base address register
L2 writeback invalidate word count register
L2 invalidate base address register
L2 invalidate word count register
L1P invalidate base address register
L1P invalidate word count register
L1D writeback invalidate base address register
0184 4004
0184 4010
0184 4014
0184 4018
0184 401C
L2IWC
0184 4020
L1PIBAR
L1PIWC
L1DWIBAR
0184 4024
0184 4030
23
April 2004 − Revised May 2005
SPRS247E
Peripheral Register Descriptions
Table 2−4. L2 Cache Registers (C64x) (Continued)
HEX ADDRESS RANGE
0184 4034
ACRONYM
REGISTER NAME
COMMENTS
L1DWIWC
−
L1D writeback invalidate word count register
Reserved
0184 4038 − 0184 4044
0184 4048
L1DIBAR
L1DIWC
−
L1D invalidate base address register
L1D invalidate word count register
Reserved
0184 404C
0184 4050 − 0184 4FFC
0184 5000
L2WB
L2WBINV
−
L2 writeback all register
L2 writeback invalidate all register
Reserved
0184 5004
0184 5008 − 0184 7FFC
MAR0 to
MAR127
0184 8000 − 0184 81FC
Reserved
0184 8200
0184 8204
0184 8208
0184 820C
0184 8210
0184 8214
0184 8218
0184 821C
0184 8220
0184 8224
0184 8228
0184 822C
0184 8230
0184 8234
0184 8238
0184 823C
0184 8240
0184 8244
0184 8248
0184 824C
0184 8250
0184 8254
0184 8258
0184 825C
0184 8260
0184 8264
0184 8268
0184 826C
0184 8270
0184 8274
0184 8278
0184 827C
0184 8280
MAR128
MAR129
MAR130
MAR131
MAR132
MAR133
MAR134
MAR135
MAR136
MAR137
MAR138
MAR139
MAR140
MAR141
MAR142
MAR143
MAR144
MAR145
MAR146
MAR147
MAR148
MAR149
MAR150
MAR151
MAR152
MAR153
MAR154
MAR155
MAR156
MAR157
MAR158
MAR159
MAR160
Controls EMIFA CE0 range 8000 0000 − 80FF FFFF
Controls EMIFA CE0 range 8100 0000 − 81FF FFFF
Controls EMIFA CE0 range 8200 0000 − 82FF FFFF
Controls EMIFA CE0 range 8300 0000 − 83FF FFFF
Controls EMIFA CE0 range 8400 0000 − 84FF FFFF
Controls EMIFA CE0 range 8500 0000 − 85FF FFFF
Controls EMIFA CE0 range 8600 0000 − 86FF FFFF
Controls EMIFA CE0 range 8700 0000 − 87FF FFFF
Controls EMIFA CE0 range 8800 0000 − 88FF FFFF
Controls EMIFA CE0 range 8900 0000 − 89FF FFFF
Controls EMIFA CE0 range 8A00 0000 − 8AFF FFFF
Controls EMIFA CE0 range 8B00 0000 − 8BFF FFFF
Controls EMIFA CE0 range 8C00 0000 − 8CFF FFFF
Controls EMIFA CE0 range 8D00 0000 − 8DFF FFFF
Controls EMIFA CE0 range 8E00 0000 − 8EFF FFFF
Controls EMIFA CE0 range 8F00 0000 − 8FFF FFFF
Controls EMIFA CE1 range 9000 0000 − 90FF FFFF
Controls EMIFA CE1 range 9100 0000 − 91FF FFFF
Controls EMIFA CE1 range 9200 0000 − 92FF FFFF
Controls EMIFA CE1 range 9300 0000 − 93FF FFFF
Controls EMIFA CE1 range 9400 0000 − 94FF FFFF
Controls EMIFA CE1 range 9500 0000 − 95FF FFFF
Controls EMIFA CE1 range 9600 0000 − 96FF FFFF
Controls EMIFA CE1 range 9700 0000 − 97FF FFFF
Controls EMIFA CE1 range 9800 0000 − 98FF FFFF
Controls EMIFA CE1 range 9900 0000 − 99FF FFFF
Controls EMIFA CE1 range 9A00 0000 − 9AFF FFFF
Controls EMIFA CE1 range 9B00 0000 − 9BFF FFFF
Controls EMIFA CE1 range 9C00 0000 − 9CFF FFFF
Controls EMIFA CE1 range 9D00 0000 − 9DFF FFFF
Controls EMIFA CE1 range 9E00 0000 − 9EFF FFFF
Controls EMIFA CE1 range 9F00 0000 − 9FFF FFFF
Controls EMIFA CE2 range A000 0000 − A0FF FFFF
24
SPRS247E
April 2004 − Revised May 2005
Peripheral Register Descriptions
Table 2−4. L2 Cache Registers (C64x) (Continued)
HEX ADDRESS RANGE
0184 8284
0184 8288
0184 828C
0184 8290
0184 8294
0184 8298
0184 829C
0184 82A0
0184 82A4
0184 82A8
0184 82AC
0184 82B0
0184 82B4
0184 82B8
0184 82BC
0184 82C0
0184 82C4
0184 82C8
0184 82CC
0184 82D0
0184 82D4
0184 82D8
0184 82DC
0184 82E0
0184 82E4
0184 82E8
0184 82EC
0184 82F0
0184 82F4
0184 82F8
0184 82FC
ACRONYM
REGISTER NAME
COMMENTS
MAR161
MAR162
MAR163
MAR164
MAR165
MAR166
MAR167
MAR168
MAR169
MAR170
MAR171
MAR172
MAR173
MAR174
MAR175
MAR176
MAR177
MAR178
MAR179
MAR180
MAR181
MAR182
MAR183
MAR184
MAR185
MAR186
MAR187
MAR188
MAR189
MAR190
MAR191
Controls EMIFA CE2 range A100 0000 − A1FF FFFF
Controls EMIFA CE2 range A200 0000 − A2FF FFFF
Controls EMIFA CE2 range A300 0000 − A3FF FFFF
Controls EMIFA CE2 range A400 0000 − A4FF FFFF
Controls EMIFA CE2 range A500 0000 − A5FF FFFF
Controls EMIFA CE2 range A600 0000 − A6FF FFFF
Controls EMIFA CE2 range A700 0000 − A7FF FFFF
Controls EMIFA CE2 range A800 0000 − A8FF FFFF
Controls EMIFA CE2 range A900 0000 − A9FF FFFF
Controls EMIFA CE2 range AA00 0000 − AAFF FFFF
Controls EMIFA CE2 range AB00 0000 − ABFF FFFF
Controls EMIFA CE2 range AC00 0000 − ACFF FFFF
Controls EMIFA CE2 range AD00 0000 − ADFF FFFF
Controls EMIFA CE2 range AE00 0000 − AEFF FFFF
Controls EMIFA CE2 range AF00 0000 − AFFF FFFF
Controls EMIFA CE3 range B000 0000 − B0FF FFFF
Controls EMIFA CE3 range B100 0000 − B1FF FFFF
Controls EMIFA CE3 range B200 0000 − B2FF FFFF
Controls EMIFA CE3 range B300 0000 − B3FF FFFF
Controls EMIFA CE3 range B400 0000 − B4FF FFFF
Controls EMIFA CE3 range B500 0000 − B5FF FFFF
Controls EMIFA CE3 range B600 0000 − B6FF FFFF
Controls EMIFA CE3 range B700 0000 − B7FF FFFF
Controls EMIFA CE3 range B800 0000 − B8FF FFFF
Controls EMIFA CE3 range B900 0000 − B9FF FFFF
Controls EMIFA CE3 range BA00 0000 − BAFF FFFF
Controls EMIFA CE3 range BB00 0000 − BBFF FFFF
Controls EMIFA CE3 range BC00 0000 − BCFF FFFF
Controls EMIFA CE3 range BD00 0000 − BDFF FFFF
Controls EMIFA CE3 range BE00 0000 − BEFF FFFF
Controls EMIFA CE3 range BF00 0000 − BFFF FFFF
MAR192 to
MAR255
0184 8300 −0184 83FC
0184 8400 −0187 FFFF
Reserved
Reserved
−
25
April 2004 − Revised May 2005
SPRS247E
Peripheral Register Descriptions
Table 2−5. Quick DMA (QDMA) and Pseudo Registers
HEX ADDRESS RANGE
0200 0000
ACRONYM
REGISTER NAME
QDMA options parameter register
QOPT
QSRC
QCNT
QDST
QIDX
0200 0004
QDMA source address register
QDMA frame count register
QDMA destination address register
QDMA index register
0200 0008
0200 000C
0200 0010
0200 0014 − 0200 001C
0200 0020
Reserved
QSOPT
QSSRC
QSCNT
QSDST
QSIDX
QDMA pseudo options register
QDMA psuedo source address register
QDMA psuedo frame count register
QDMA destination address register
QDMA psuedo index register
0200 0024
0200 0028
0200 002C
0200 0030
Table 2−6. EDMA Registers (C64x)
HEX ADDRESS RANGE
01A0 0800 − 01A0 FF98
01A0 FF9C
ACRONYM
−
REGISTER NAME
Reserved
EPRH
CIPRH
CIERH
CCERH
ERH
Event polarity high register
Channel interrupt pending high register
Channel interrupt enable high register
Channel chain enable high register
Event high register
01A0 FFA4
01A0 FFA8
01A0 FFAC
01A0 FFB0
01A0 FFB4
EERH
ECRH
ESRH
PQAR0
PQAR1
PQAR2
PQAR3
EPRL
PQSR
CIPRL
CIERL
CCERL
ERL
Event enable high register
Event clear high register
01A0 FFB8
01A0 FFBC
Event set high register
01A0 FFC0
Priority queue allocation register 0
Priority queue allocation register 1
Priority queue allocation register 2
Priority queue allocation register 3
Event polarity low register
Priority queue status register
Channel interrupt pending low register
Channel interrupt enable low register
Channel chain enable low register
Event low register
01A0 FFC4
01A0 FFC8
01A0 FFCC
01A0 FFDC
01A0 FFE0
01A0 FFE4
01A0 FFE8
01A0 FFEC
01A0 FFF0
01A0 FFF4
EERL
ECRL
ESRL
–
Event enable low register
01A0 FFF8
Event clear low register
01A0 FFFC
Event set low register
01A1 0000 − 01A3 FFFF
Reserved
26
SPRS247E
April 2004 − Revised May 2005
Peripheral Register Descriptions
†
Table 2−7. EDMA Parameter RAM (C64x)
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
Parameters for Event 0 (6 words)
COMMENTS
Parameters for Event 0
(6 words) or Reload/Link
Parameters for other Event
01A0 0000 − 01A0 0017
−
01A0 0018 − 01A0 002F
01A0 0030 − 01A0 0047
01A0 0048 − 01A0 005F
01A0 0060 − 01A0 0077
01A0 0078 − 01A0 008F
01A0 0090 − 01A0 00A7
01A0 00A8 − 01A0 00BF
01A0 00C0 − 01A0 00D7
01A0 00D8 − 01A0 00EF
01A0 00F0 − 01A0 00107
01A0 0108 − 01A0 011F
01A0 0120 − 01A0 0137
01A0 0138 − 01A0 014F
01A0 0150 − 01A0 0167
01A0 0168 − 01A0 017F
01A0 0150 − 01A0 0197
01A0 0168 − 01A0 01AF
...
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
Parameters for Event 1 (6 words)
Parameters for Event 2 (6 words)
Parameters for Event 3 (6 words)
Parameters for Event 4 (6 words)
Parameters for Event 5 (6 words)
Parameters for Event 6 (6 words)
Parameters for Event 7 (6 words)
Parameters for Event 8 (6 words)
Parameters for Event 9 (6 words)
Parameters for Event 10 (6 words)
Parameters for Event 11 (6 words)
Parameters for Event 12 (6 words)
Parameters for Event 13 (6 words)
Parameters for Event 14 (6 words)
Parameters for Event 15 (6 words)
Parameters for Event 16 (6 words)
Parameters for Event 17 (6 words)
...
01A0 05D0 − 01A0 05E7
01A0 05E8 − 01A0 05FF
−
−
Parameters for Event 62 (6 words)
Parameters for Event 63 (6 words)
Reload/Link Parameters for
other Event 0−15
01A0 0600 − 01A0 0617
−
−
Reload/link parameters for Event 0 (6 words)
01A0 0618 − 01A0 062F
...
Reload/link parameters for Event 1 (6 words)
...
01A0 07E0 − 01A0 07F7
01A0 07F8 − 01A0 080F
01A0 0810 − 01A0 0827
...
−
−
−
Reload/link parameters for Event 20 (6 words)
Reload/link parameters for Event 21 (6 words)
Reload/link parameters for Event 22 (6 words)
...
01A0 13C8 − 01A0 13DF
01A0 13E0 − 01A0 13F7
01A0 13F8 − 01A0 13FF
01A0 1400 − 01A3 FFFF
−
−
−
−
Reload/link parameters for Event 147 (6 words)
Reload/link parameters for Event 148 (6 words)
Scratch pad area (2 words)
Reserved
†
The C6413/C6410 device has 213 EDMA parameters total: 64-Event/Reload channels and 149-Reload only parameter sets [six (6) words each]
that can be used to reload/link EDMA transfers.
27
April 2004 − Revised May 2005
SPRS247E
Peripheral Register Descriptions
Table 2−8. Interrupt Selector Registers (C64x)
HEX ADDRESS RANGE
ACRONYM
MUXH
REGISTER NAME
COMMENTS
Selects which interrupts drive CPU
interrupts 10−15 (INT10−INT15)
019C 0000
Interrupt multiplexer high
Interrupt multiplexer low
Selects which interrupts drive CPU
interrupts 4−9 (INT04−INT09)
019C 0004
MUXL
Sets the polarity of the external
interrupts (EXT_INT4−EXT_INT7)
019C 0008
EXTPOL
External interrupt polarity
Reserved
019C 000C − 019F FFFF
−
Table 2−9. Device Configuration Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
Enables or disables specific
peripherals. This register is also
used for power-down of disabled
peripherals.
01B3 F000
PERCFG
DEVSTAT
Peripheral Configuration Register
Read-only. Provides status of
the User’s device configuration
on reset.
01B3 F004
01B3 F008
Device Status Register
Read-only. Provides 32-bit
JTAG ID of the device.
JTAGID
JTAG Identification Register
Reserved
01B3 F00C − 01B3 F014
01B3 F018
−
PCFGLOCK Peripheral Configuration Lock Register
Reserved
01B3 F01C − 01B3 FFFF
−
28
SPRS247E
April 2004 − Revised May 2005
Peripheral Register Descriptions
Table 2−10. McBSP 0 Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
The CPU and EDMA controller
can only read this register; they
cannot write to it.
018C 0000
DRR0
McBSP0 data receive register via Configuration Bus
0x3000 0000 − 0x33FF FFFF
018C 0004
DRR0
DXR0
McBSP0 data receive register via Peripheral Bus
McBSP0 data transmit register via Configuration Bus
McBSP0 data transmit register via Peripheral Bus
McBSP0 serial port control register
0x3000 0000 − 0x33FF FFFF
018C 0008
DXR0
SPCR0
RCR0
018C 000C
McBSP0 receive control register
018C 0010
XCR0
McBSP0 transmit control register
018C 0014
SRGR0
MCR0
McBSP0 sample rate generator register
018C 0018
McBSP0 multichannel control register
018C 001C
RCERE00
XCERE00
PCR0
McBSP0 enhanced receive channel enable register 0
McBSP0 enhanced transmit channel enable register 0
McBSP0 pin control register
018C 0020
018C 0024
018C 0028
RCERE10
XCERE10
RCERE20
XCERE20
RCERE30
XCERE30
–
McBSP0 enhanced receive channel enable register 1
McBSP0 enhanced transmit channel enable register 1
McBSP0 enhanced receive channel enable register 2
McBSP0 enhanced transmit channel enable register 2
McBSP0 enhanced receive channel enable register 3
McBSP0 enhanced transmit channel enable register 3
Reserved
018C 002C
018C 0030
018C 0034
018C 0038
018C 003C
018C 0040 − 018F FFFF
Table 2−11. McBSP 1 Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
The CPU and EDMA controller
can only read this register; they
cannot write to it.
0190 0000
DRR1
McBSP1 data receive register via Configuration Bus
0x3400 0000 − 0x37FF FFFF
0190 0004
DRR1
DXR1
McBSP1 data receive register via peripheral bus
McBSP1 data transmit register via configuration bus
McBSP1 data transmit register via peripheral bus
McBSP1 serial port control register
0x3400 0000 − 0x37FF FFFF
0190 0008
DXR1
SPCR1
RCR1
0190 000C
McBSP1 receive control register
0190 0010
XCR1
McBSP1 transmit control register
0190 0014
SRGR1
MCR1
McBSP1 sample rate generator register
0190 0018
McBSP1 multichannel control register
0190 001C
RCERE01
XCERE01
PCR1
McBSP1 enhanced receive channel enable register 0
McBSP1 enhanced transmit channel enable register 0
McBSP1 pin control register
0190 0020
0190 0024
0190 0028
RCERE11
XCERE11
RCERE21
XCERE21
RCERE31
XCERE31
–
McBSP1 enhanced receive channel enable register 1
McBSP1 enhanced transmit channel enable register 1
McBSP1 enhanced receive channel enable register 2
McBSP1 enhanced transmit channel enable register 2
McBSP1 enhanced receive channel enable register 3
McBSP1 enhanced transmit channel enable register 3
Reserved
0190 002C
0190 0030
0190 0034
0190 0038
0190 003C
0190 0040 − 0193 FFFF
29
April 2004 − Revised May 2005
SPRS247E
Peripheral Register Descriptions
Table 2−12. Timer 0 Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
Determines the operating mode of the timer, monitors the
timer status, and controls the function of the TOUT pin.
0194 0000
CTL0
PRD0
Timer 0 control register
Timer 0 period register
Contains the number of timer input clock cycles to count.
This number controls the TSTAT signal frequency.
0194 0004
0194 0008
CNT0
Timer 0 counter register
Reserved
Contains the current value of the incrementing counter.
0194 000C − 0197 FFFF
−
Table 2−13. Timer 1 Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
Determines the operating mode of the timer, monitors the
timer status, and controls the function of the TOUT pin.
0198 0000
CTL1
Timer 1 control register
Timer 1 period register
Contains the number of timer input clock cycles to count.
This number controls the TSTAT signal frequency.
0198 0004
PRD1
0198 0008
CNT1
Timer 1 counter register
Reserved
Contains the current value of the incrementing counter.
0198 000C − 019B FFFF
−
Table 2−14. Timer 2 Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
Determines the operating mode of the timer, monitors the
timer status.
01AC 0000
CTL2
Timer 2 control register
Timer 2 period register
Contains the number of timer input clock cycles to count.
This number controls the TSTAT signal frequency.
01AC 0004
PRD2
01AC 0008
CNT2
Timer 2 counter register
Reserved
Contains the current value of the incrementing counter.
01AC 000C − 01AF FFFF
−
30
SPRS247E
April 2004 − Revised May 2005
Peripheral Register Descriptions
Table 2−15. HPI Registers
HEX ADDRESS RANGE
ACRONYM
HPID
REGISTER NAME
COMMENTS
−
HPI data register
Host read/write access only
0188 0000
HPIC
HPI control register
HPIC has both Host/CPU read/write access
HPIA has both Host/CPU read/write access
HPIA
(HPIAW)
HPI address register
(Write)
0188 0004
†
HPIA
(HPIAR)
HPI address register
(Read)
0188 0008
†
0188 000C − 0189 FFFF
018A 0000
−
Reserved
HPI transfer request control
register
HPI_TRCTL
018A 0004 − 018B FFFF
−
Reserved
†
Host access to the HPIA register updates both the HPIAW and HPIAR registers. The CPU can access HPIAW and HPIAR independently.
Table 2−16. GP0 Registers
HEX ADDRESS RANGE
01B0 0000
ACRONYM
GPEN
GPDIR
GPVAL
−
REGISTER NAME
GP0 enable register
01B0 0004
GP0 direction register
GP0 value register
01B0 0008
01B0 000C
Reserved
01B0 0010
GPDH
GPHM
GPDL
GPLM
GPGC
GPPOL
−
GP0 delta high register
GP0 high mask register
GP0 delta low register
GP0 low mask register
GP0 global control register
GP0 interrupt polarity register
Reserved
01B0 0014
01B0 0018
01B0 001C
01B0 0020
01B0 0024
01B0 0028 − 01B3 EFFF
31
April 2004 − Revised May 2005
SPRS247E
Peripheral Register Descriptions
Table 2−17. McASP0 and McASP1 Control Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
Peripheral Identification register
[Register value: 0x0010 0101]
Power down and emulation management register
Reserved
McASP0
McASP1
01B4 C000
01B5 0000
PID
01B4 C004
01B4 C008
01B4 C00C
01B4 C010
01B4 C014
01B4 C018
01B5 0004
01B5 0008
01B5 000C
01B5 0010
01B5 0014
01B5 0018
PWRDEMU
−
−
Reserved
PFUNC
PDIR
Pin function register
Pin direction register
PDOUT
Pin data out register
Pin data in / data set register
Read returns: PDIN
Writes affect: PDSET
01B4 C01C
01B5 001C
PDIN/PDSET
01B4 C020
01B5 0020
PDCLR
−
Pin data clear register
Reserved
01B4 C024 − 01B4 C040
01B4 C044
01B5 0024 − 01B5 0040
01B5 0044
GBLCTL
AMUTE
DLBCTL
DITCTL
−
Global control register
Mute control register
Digital Loop-back control register
DIT mode control register
Reserved
01B4 C048
01B5 0048
01B4 C04C
01B5 004C
01B4 C050
01B5 0050
01B4 C054 − 01B4 C05C
01B5 0054 − 01B5 005C
Alias of GBLCTL containing only Receiver Reset bits,
allows transmit to be reset independently from receive.
01B4 C060
01B5 0060
RGBLCTL
01B4 C064
01B4 C068
01B5 0064
01B5 0068
RMASK
RFMT
Receiver format unit bit mask register
Receive bit stream format register
Receive frame sync control register
Receive clock control register
High-frequency receive clock control register
Receive TDM slot 0−31 register
Receiver interrupt control register
Status register − Receiver
01B4 C06C
01B5 006C
AFSRCTL
ACLKRCTL
AHCLKRCTL
RTDM
01B4 C070
01B5 0070
01B4 C074
01B5 0074
01B4 C078
01B5 0078
01B4 C07C
01B5 007C
RINTCTL
RSTAT
01B4 C080
01B5 0080
01B4 C084
01B5 0084
RSLOT
Current receive TDM slot register
Receiver clock check control register
Reserved
01B4 C088
01B5 0088
RCLKCHK
−
01B4 C08C − 01B4 C09C
01B5 008C − 01B5 009C
Alias of GBLCTL containing only Transmitter Reset bits,
allows transmit to be reset independently from receive.
01B4 C0A0
01B5 00A0
XGBLCTL
01B4 C0A4
01B4 C0A8
01B4 C0AC
01B4 C0B0
01B4 C0B4
01B4 C0B8
01B4 C0BC
01B4 C0C0
01B4 C0C4
01B4 C0C8
01B5 00A4
01B5 00A8
01B5 00AC
01B5 00B0
01B5 00B4
01B5 00B8
01B5 00BC
01B5 00C0
01B5 00C4
01B5 00C8
XMASK
XFMT
Transmit format unit bit mask register
Transmit bit stream format register
Transmit frame sync control register
Transmit clock control register
AFSXCTL
ACLKXCTL
AHCLKXCTL
XTDM
High-frequency Transmit clock control register
Transmit TDM slot 0−31 register
Transmit interrupt control register
Status register − Transmitter
XINTCTL
XSTAT
XSLOT
Current transmit TDM slot
XCLKCHK
Transmit clock check control register
32
SPRS247E
April 2004 − Revised May 2005
Peripheral Register Descriptions
Table 2−17. McASP0 and McASP1 Control Registers (Continued)
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
McASP0
McASP1
01B5 00CC − 01B5 00FC
01B5 0100
01B4 C0CC − 01B4 C0FC
01B4 C100
−
Reserved
DITCSRA0
DITCSRA1
DITCSRA2
DITCSRA3
DITCSRA4
DITCSRA5
DITCSRB0
DITCSRB1
DITCSRB2
DITCSRB3
DITCSRB4
DITCSRB5
DITUDRA0
DITUDRA1
DITUDRA2
DITUDRA3
DITUDRA4
DITUDRA5
DITUDRB0
DITUDRB1
DITUDRB2
DITUDRB3
DITUDRB4
DITUDRB5
−
Left (even TDM slot) channel status register file
Left (even TDM slot) channel status register file
Left (even TDM slot) channel status register file
Left (even TDM slot) channel status register file
Left (even TDM slot) channel status register file
Left (even TDM slot) channel status register file
Right (odd TDM slot) channel status register file
Right (odd TDM slot) channel status register file
Right (odd TDM slot) channel status register file
Right (odd TDM slot) channel status register file
Right (odd TDM slot) channel status register file
Right (odd TDM slot) channel status register file
Left (even TDM slot) user data register file
Left (even TDM slot) user data register file
Left (even TDM slot) user data register file
Left (even TDM slot) user data register file
Left (even TDM slot) user data register file
Left (even TDM slot) user data register file
Right (odd TDM slot) user data register file
Right (odd TDM slot) user data register file
Right (odd TDM slot) user data register file
Right (odd TDM slot) user data register file
Right (odd TDM slot) user data register file
Right (odd TDM slot) user data register file
Reserved
01B4 C104
01B5 0104
01B4 C108
01B5 0108
01B4 C10C
01B4 C110
01B5 010C
01B5 0110
01B4 C114
01B5 0114
01B4 C118
01B5 0118
01B4 C11C
01B4 C120
01B5 011C
01B5 0120
01B4 C124
01B5 0124
01B4 C128
01B5 0128
01B4 C12C
01B4 C130
01B5 012C
01B5 0130
01B4 C134
01B5 0134
01B4 C138
01B5 0138
01B4 C13C
01B4 C140
01B5 013C
01B5 0140
01B4 C144
01B5 0144
01B4 C148
01B5 0148
01B4 C14C
01B4 C150
01B5 014C
01B5 0150
01B4 C154
01B5 0154
01B4 C158
01B5 0158
01B4 C15C
01B4 C160 − 01B4 C17C
01B4 C180
01B5 015C
01B5 0160 − 01B5 017C
01B5 0180
SRCTL0
SRCTL1
SRCTL2
SRCTL3
SRCTL4
SRCTL5
−
Serializer 0 control register
01B4 C184
01B5 0184
Serializer 1 control register
01B4 C188
01B5 0188
Serializer 2 control register
01B4 C18C
01B4 C190
01B5 018C
01B5 0190
Serializer 3 control register
Serializer 4 control register
01B4 C194
01B5 0194
Serializer 5 control register
01B4 C198
01B5 0198
Reserved
01B4 C19C
01B4 C1A0 − 01B4 C1FC
01B4 C200
01B5 019C
01B5 01A0 − 01B5 01FC
01B5 0200
−
Reserved
−
Reserved
XBUF0
Transmit Buffer for Serializer 0
01B4 C204
01B5 0204
XBUF1
Transmit Buffer for Serializer 1
01B4 C208
01B5 0208
XBUF2
Transmit Buffer for Serializer 2
01B4 C20C
01B4 C210
01B5 020C
01B5 0210
XBUF3
Transmit Buffer for Serializer 3
XBUF4
Transmit Buffer for Serializer 4
01B4 C214
01B5 0214
XBUF5
Transmit Buffer for Serializer 5
33
April 2004 − Revised May 2005
SPRS247E
Peripheral Register Descriptions
Table 2−17. McASP0 and McASP1 Control Registers (Continued)
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
McASP0
01B4 C218
McASP1
01B5 0218
−
−
Reserved
Reserved
Reserved
01B4 C21C
01B5 021C
01B4 C220 − 01B4 C27C
01B4 C280
01B5 0220 − 01B5 027C
01B5 0280
−
RBUF0
RBUF1
RBUF2
RBUF3
RBUF4
RBUF5
−
Receive Buffer for Serializer 0
Receive Buffer for Serializer 1
Receive Buffer for Serializer 2
Receive Buffer for Serializer 3
Receive Buffer for Serializer 4
Receive Buffer for Serializer 5
Reserved
01B4 C284
01B5 0284
01B4 C288
01B5 0288
01B4 C28C
01B5 028C
01B4 C290
01B5 0290
01B4 C294
01B5 0294
01B4 C298
01B5 0298
01B4 C29C
01B5 029C
−
Reserved
01B4 C2A0 − 01B4 FFFF
01B5 02A0 − 01B5 3FFF
−
Reserved
Table 2−18. McASP0 Data Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
(Used when RSEL or XSEL
bits = 0 [these bits are located
in the RFMT or XFMT
McASPx receive buffers or McASPx transmit buffers via
the Peripheral Data Bus.
3C00 0000 − 3C0F FFFF
RBUF/XBUFx
registers, respectively].)
Table 2−19. McASP1 Data Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
(Used when RSEL or XSEL
bits = 0 [these bits are located
in the RFMT or XFMT
McASPx receive buffers or McASPx transmit buffers via
the Peripheral Data Bus.
3C10 0000 − 3C1F FFFF
RBUF/XBUFx
registers, respectively].)
34
SPRS247E
April 2004 − Revised May 2005
Peripheral Register Descriptions
Table 2−20. I2C0 and I2C1 Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
I2C0
I2C1
01B4 0000
01B4 0004
01B4 0008
01B4 000C
01B4 0010
01B4 0014
01B4 0018
01B4 001C
01B4 0020
01B4 0024
01B4 0028
01B4 002C
01B4 0030
01B4 4000
01B4 4004
01B4 4008
01B4 400C
01B4 4010
01B4 4014
01B4 4018
01B4 401C
01B4 4020
01B4 4024
01B4 4028
01B4 402C
01B4 4030
I2COARx
I2CIMRx
I2Cx own address register
I2Cx interrupt mask/status register
I2Cx interrupt status register
I2Cx clock low-time divider register
I2Cx clock high-time divider register
I2Cx data count register
I2CSTRx
I2CCLKLx
I2CCLKHx
I2CCNTx
I2CDRRx
I2CSARx
I2CDXRx
I2CMDRx
I2CIVRx
I2Cx data receive register
I2Cx slave address register
I2Cx data transmit register
I2Cx mode register
I2Cx interrupt vector register
I2Cx Extended mode register
I2Cx prescaler register
I2CEMDRx
I2CPSCx
I2Cx Peripheral Identification register 1
[Value: 0x0000 0105]
01B4 0034
01B4 0038
01B4 4034
01B4 4038
I2CPID1x
I2CPID2x
I2Cx Peripheral Identification register 2
[Value: 0x0000 0005]
01B4 003C − 01B4 0044
01B4 0048
01B4 403C − 01B4 4044
01B4 4048
−
Reserved
I2CPFUNCx
I2CPDIRx
I2CPDINx
I2CPDOUTx
I2CPDSETx
I2CPDCLRx
−
I2Cx pin function register
I2Cx pin direction register
I2Cx pin data in register
I2Cx pin data out register
I2Cx pin data set register
I2Cx pin data clear register
Reserved
01B4 004C
01B4 404C
01B4 0050
01B4 4050
01B4 0054
01B4 4054
01B4 0058
01B4 4058
01B4 005C
01B4 405C
01B4 0060 − 01B4 3FFF
01B4 4060 − 01B4 7FFF
35
April 2004 − Revised May 2005
SPRS247E
EDMA Channel Synchronization Events
2.7
EDMA Channel Synchronization Events
The C64x EDMA supports up to 64 EDMA channels which service peripheral devices and external memory.
Table 2−21 lists the source of C64x EDMA synchronization events associated with each of the programmable
EDMA channels. For the C6413/C6410 device, the association of an event to a channel is fixed; each of the
EDMA channels has one specific event associated with it. These specific events are captured in the EDMA
event registers (ERL, ERH) even if the events are disabled by the EDMA event enable registers (EERL,
EERH). The priority of each event can be specified independently in the transfer parameters stored in the
EDMA parameter RAM. For more detailed information on the EDMA module and how EDMA events are
enabled, captured, processed, linked, chained, and cleared, etc., see the TMS320C6000 DSP Enhanced
Direct Memory Access (EDMA) Controller Reference Guide (literature number SPRU234).
†
Table 2−21. TMS320C6413/C6410 EDMA Channel Synchronization Events
EDMA
CHANNEL
EVENT NAME
EVENT DESCRIPTION
0
1
DSP_INT
TINT0
HPI-to-DSP interrupt
Timer 0 interrupt
2
TINT1
Timer 1 interrupt
3
SD_INTA
GPINT4/EXT_INT4
GPINT5/EXT_INT5
GPINT6/EXT_INT6
GPINT7/EXT_INT7
GPINT0
GPINT1
GPINT2
GPINT3
XEVT0
EMIFA SDRAM timer interrupt
GP0 event 4/External interrupt pin 4
GP0 event 5/External interrupt pin 5
GP0 event 6/External interrupt pin 6
GP0 event 7/External interrupt pin 7
GP0 event 0
4
5
6
7
8
9
GP0 event 1
10
11
12
13
14
15
16−18
19
20−27
28
29
30−31
32
33
34
35
36
37
38
39
40
GP0 event 2
GP0 event 3
McBSP0 transmit event
McBSP0 receive event
McBSP1 transmit event
McBSP1 receive event
None
REVT0
XEVT1
REVT1
–
TINT2
Timer 2 interrupt
–
None
–
None
–
None
–
None
AXEVTE0
AXEVTO0
AXEVT0
AREVTE0
AREVTO0
AREVT0
AXEVTE1
AXEVTO1
AXEVT1
McASP0 transmit even event
McASP0 transmit odd event
McASP0 transmit event
McASP0 receive even event
McASP0 receive odd event
McASP0 receive event
McASP1 transmit even event
McASP1 transmit odd event
McASP1 transmit event
†
In addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate transfer
completion events. For more detailed information on EDMA event-transfer chaining, see the TMS320C6000 DSP Enhanced Direct Memory
Access (EDMA) Controller Reference Guide (literature number SPRU234).
36
SPRS247E
April 2004 − Revised May 2005
Interrupt Sources and Interrupt Selector
†
Table 2−21. TMS320C6413/C6410 EDMA Channel Synchronization Events (Continued)
EDMA
CHANNEL
EVENT NAME
EVENT DESCRIPTION
41
42
AREVTE1
AREVTO1
AREVT1
ICREVT0
ICXEVT0
ICREVT1
ICXEVT1
GPINT8
GPINT9
GPINT10
GPINT11
GPINT12
GPINT13
GPINT14
GPINT15
–
McASP1 receive even event
McASP1 receive odd event
McASP1 receive event
I2C0 receive event
I2C0 transmit event
I2C1 receive event
I2C1 transmit event
GP0 event 8
43
44
45
46
47
48
49
GP0 event 9
50
GP0 event 10
51
GP0 event 11
52
GP0 event 12
53
GP0 event 13
54
GP0 event 14
55
GP0 event 15
56−63
None
†
In addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate transfer
completion events. For more detailed information on EDMA event-transfer chaining, see the TMS320C6000 DSP Enhanced Direct Memory
Access (EDMA) Controller Reference Guide (literature number SPRU234).
2.8
Interrupt Sources and Interrupt Selector
The C64x DSP core supports 16 prioritized interrupts, which are listed in Table 2−22. The highest-priority
interrupt is INT_00 (dedicated to RESET) while the lowest-priority interrupt is INT_15. The first four interrupts
(INT_00−INT_03) are non-maskable and fixed. The remaining interrupts (INT_04−INT_15) are maskable and
default to the interrupt source specified in Table 2−22. The interrupt source for interrupts 4−15 can be
programmed by modifying the selector value (binary value) in the corresponding fields of the Interrupt Selector
Control registers: MUXH (address 0x019C0000) and MUXL (address 0x019C0004).
37
April 2004 − Revised May 2005
SPRS247E
Interrupt Sources and Interrupt Selector
Table 2−22. C6413/C6410 DSP Interrupts
INTERRUPT
CPU
SELECTOR
INTERRUPT
VALUE
(BINARY)
SELECTOR
INTERRUPT
NUMBER
INTERRUPT SOURCE
EVENT
CONTROL
REGISTER
†
INT_00
INT_01
INT_02
INT_03
INT_04
INT_05
INT_06
INT_07
INT_08
INT_09
INT_10
−
−
RESET
NMI
†
†
†
‡
‡
‡
‡
‡
‡
‡
−
−
−
−
Reserved
Reserved
GPINT4/EXT_INT4
GPINT5/EXT_INT5
GPINT6/EXT_INT6
GPINT7/EXT_INT7
EDMA_INT
EMU_DTDMA
SD_INTA
EMU_RTDXRX
EMU_RTDXTX
DSP_INT
TINT0
Reserved. Do not use.
−
−
Reserved. Do not use.
MUXL[4:0]
00100
00101
00110
00111
01000
01001
00011
01010
01011
00000
00001
00010
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
GP0 interrupt 4/External interrupt pin 4
GP0 interrupt 5/External interrupt pin 5
GP0 interrupt 6/External interrupt pin 6
GP0 interrupt 7/External interrupt pin 7
EDMA channel (0 through 63) interrupt
EMU DTDMA
MUXL[9:5]
MUXL[14:10]
MUXL[20:16]
MUXL[25:21]
MUXL[30:26]
MUXH[4:0]
EMIFA SDRAM timer interrupt
EMU real-time data exchange (RTDX) receive
EMU RTDX transmit
‡
‡
INT_11
MUXH[9:5]
INT_12
MUXH[14:10]
‡
‡
‡
INT_13
MUXH[20:16]
HPI-to-DSP interrupt
INT_14
MUXH[25:21]
Timer 0 interrupt
INT_15
MUXH[30:26]
TINT1
Timer 1 interrupt
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
XINT0
McBSP0 transmit interrupt
McBSP0 receive interrupt
McBSP1 transmit interrupt
McBSP1 receive interrupt
GP0 interrupt 0
RINT0
XINT1
RINT1
GPINT0
Reserved
Reserved
TINT2
Reserved. Do not use.
Reserved. Do not use.
Timer 2 interrupt
Reserved
Reserved
ICINT0
Reserved. Do not use.
Reserved. Do not use.
I2C0 interrupt
ICINT1
I2C1 interrupt
AXINT1
McASP1 transmit interrupt
McASP1 receive interrupt
Reserved. Do not use.
ARINT1
Reserved
Reserved
AXINT0
Reserved. Do not use.
McASP0 transmit interrupt
McASP0 receive interrupt
Reserved. Do not use.
ARINT0
Reserved
Reserved
Reserved. Do not use.
†
‡
Interrupts INT_00 through INT_03 are non-maskable and fixed.
Interrupts INT_04 through INT_15 are programmable by modifying the binary selector values in the Interrupt Selector Control registers fields.
Table 2−22 shows the default interrupt sources for Interrupts INT_04 through INT_15. For more detailed information on interrupt sources and
selection, see the TMS320C6000 DSP Interrupt Selector Reference Guide (literature number SPRU646).
38
SPRS247E
April 2004 − Revised May 2005
Signal Groups Description
2.9
Signal Groups Description
CLKINSEL
RESET
NMI
GP0[7]/EXT_INT7
GP0[6]/EXT_INT6
GP0[5]/EXT_INT5
CLKIN
†
CLKOUT4/GP0[1]
‡
†
Reset and
Interrupts
CLKOUT6/GP0[2]
‡
CLKMODE3
CLKMODE2
CLKMODE1
CLKMODE0
PLLV
‡
‡
GP0[4]/EXT_INT4
Clock/PLL
and
Oscillator
OSCIN
OSCOUT
OSCV
DD
OSCV
SS
OSC_DIS
RSV
RSV
RSV
RSV
RSV
RwSV
w
w
RSV
RSV
RSV
TMS
TDO
TDI
TCK
TRST
EMU0
EMU1
EMU2
EMU3
EMU4
EMU5
EMU6
EMU7
EMU8
EMU9
EMU10
EMU11
Reserved
IEEE Standard
1149.1
(JTAG)
Emulation
Control/Status
‡
§
GP0[7]/EXT_INT7
HD15/GP0[15]
‡
§
GP0[6]/EXT_INT6
HD14/GP0[14]
‡
§
GP0[5]/EXT_INT5
HD13/GP0[13]
‡
§
GP0[4]/EXT_INT4
HD12/GP0[12]
GP0
§
GP0[3]
HD11/GP0[11]
†
§
CLKOUT6/GP0[2]
HD10/GP0[10]
†
§
CLKOUT4/GP0[1]
HD9/GP0[9]
§
GP0[0]
HD8/GP0[8]
General-Purpose Input/Output 0 (GP0) Port
†
These pins are muxed with the GP0 pins and by default these signals function as clocks (CLKOUT4 or CLKOUT6). To use these muxed
pins as GPIO signals, the appropriate GPIO register bits (GPxEN and GPxDIR) must be properly enabled and configured. For more
details, see the Device Configurations section of this data sheet.
These pins are GP0 pins that can also function as external interrupt sources (EXT_INT[7:4]). Default after reset is EXT_INTx or GPIO
as input-only.
‡
§
These pins are muxed with the HPI peripheral pins and by default these signals function as HPI. For more details on these muxed pins,
see the Device Configurations section of this data sheet.
Figure 2−6. CPU and Peripheral Signals
39
April 2004 − Revised May 2005
SPRS247E
Signal Groups Description
32
Data
AED[31:0]
AECLKIN
AECLKOUT1
ACE3
ACE2
AECLKOUT2
ASDCKE
AARE/ASDCAS/ASADS/ASRE
Memory Map
Space Select
External
Memory I/F
Control
ACE1
ACE0
AAOE/ASDRAS/ASOE
AAWE/ASDWE/ASWE
AARDY
20
Address
AEA[22:3]
ASOE3
APDT
ABE3
ABE2
ABE1
ABE0
Byte Enables
AHOLD
Bus
Arbitration
AHOLDA
ABUSREQ
EMIFA (32-bit)
HD[31,30]
†
HPI
†
HD[29:16]/McASP1
32
(Host-Port Interface)
†
Data
HD[15:8]/GP0[15:8]
HD[7:0]
†
HAS/ACLKR1[1]
†
†
HR/W/AFSR1[3]
HCNTL0/AFSR1[1]
Register Select
†
HCS/ACLKR1[2]
HCNTL1
†
Control
HDS1/ACLKR1[3]
HDS2
HRDY
HINT
Half-Word
Select
†
HHWIL/AFSR1[2]
(HPI16 ONLY)
†
These HPI pins are muxed with the McASP1 or GP0 peripherals. By default, these signals function as HPI and no function,
respectively. For more details on these muxed pins, see the Device Configurations section of this data sheet.
Figure 2−7. Peripheral Signals
40
SPRS247E
April 2004 − Revised May 2005
Signal Groups Description
McBSP1
Transmit
McBSP0
Transmit
CLKX0
FSX0
DX0
CLKX1
FSX1
DX1
CLKR1
FSR1
DR1
CLKR0
FSR0
Receive
Clock
Receive
Clock
DR0
CLKS0
CLKS1
McBSPs
(Multichannel Buffered
Serial Ports)
TOUT1/LENDIAN
TOUT0
TINP0
Timer 0
Timers
Timer 1
TINP1
Timer 2
SCL1
SDA1
SCL0
SDA0
I2C1
I2C0
I2Cs
Figure 2−7. Peripheral Signals (Continued)
41
April 2004 − Revised May 2005
SPRS247E
Signal Groups Description
(Transmit/Receive Data Pins)
(Transmit/Receive Data Pins)
AXR0[0]
AXR0[1]
AXR0[2]
AXR0[3]
AXR0[4]
AXR0[5]
6-Serial Ports
Flexible
Partitioning
Tx, Rx, OFF
(Transmit Bit Clock)
(Receive Bit Clock)
Transmit
Clock
Generator
Receive Clock
Generator
ACLKX0
ACLKR0
AHCLKR0
AHCLKX0
(Receive Master Clock)
(Transmit Master Clock)
Transmit
Clock Check
Circuit
Receive Clock
Check Circuit
Receive
Frame Sync
Transmit
Frame Sync
AFSR0
(Receive Frame Sync or
Left/Right Clock)
AFSX0
(Transmit Frame Sync or
Left/Right Clock)
AMUTE0
Error Detect
(see Note A)
Auto Mute
Logic
AMUTEIN0
McASP0
(Multichannel Audio Serial Port 0)
NOTES: A. The McASPs’ Error Detect function detects underruns, overruns, early/late frame syncs, DMA errors, and external mute input.
B. Bolded and italicized text within parentheses denotes the function of the pins in an audio system.
Figure 2−7. Peripheral Signals (Continued)
42
SPRS247E
April 2004 − Revised May 2005
Signal Groups Description
(Transmit/Receive Data Pins)
(Transmit/Receive Data Pins)
HD16/AXR1[0]
HD17/AXR1[1]
HD18/AXR1[2]
HD19/AXR1[3]
HD20/AXR1[4]
HD21/AXR1[5]
6-Serial Ports
Flexible
Partitioning
Tx, Rx, OFF
(Receive Bit Clock)
AFCMUX[1:0]
(PERCFG[10:9])
HD25/ACLKR1
(Transmit Bit Clock)
HAS/ACLKR1[1]
HCS/ACLKR1[2]
HDS1/ACLKR1[3]
Transmit
Clock
Generator
HD24/ACLKX1
Receive Clock
Generator
HD27/AHCLKX1
(Transmit Master Clock)
HD26/AHCLKR1
(Receive Master Clock)
Transmit
Clock Check
Circuit
Receive Clock
Check Circuit
HD23/AFSR1
HCNTL0/AFSR1[1]
Receive
Transmit
HD22/AFSX1
(Transmit Frame Sync or
Left/Right Clock)
HHWIL/AFSR1[2]
HR/W/AFSR1[3]
Frame Sync
Frame Sync
AFCMUX[1:0]
(PERCFG[10:9])
HD28/AMUTE1
HD29/AMUTEIN1
Error Detect
(see Note A)
Auto Mute
Logic
(Receive Frame Sync or
Left/Right Clock)
McASP1
(Multichannel Audio Serial Port 1)
NOTES: A. The McASPs’ Error Detect function detects underruns, overruns, early/late frame syncs, DMA errors, and external mute input.
B. Bolded and italicized text within parentheses denotes the function of the pins in an audio system.
Figure 2−7. Peripheral Signals (Continued)
43
April 2004 − Revised May 2005
SPRS247E
Device Configurations
3
Device Configurations
On the C6413/C6410 device, bootmode and certain device configurations/peripheral selections are
determined at device reset, while other device configurations/peripheral selections are software-configurable
via the peripheral configurations register (PERCFG) [address location 0x01B3F000] after device reset.
3.1
Device Configuration at Device Reset
Table 3−1 describes the C6413/C6410 device configuration pins. The logic level of the AEA[22:19],
TOUT1/LENDIAN, TOUT0/HPI_EN, and HD5 pins is latched at reset to determine the device configuration.
The logic level on the device configuration pins can be set by using external pullup/pulldown resistors or by
using some control device (e.g., FPGA/CPLD) to intelligently drive these pins. When using a control device,
care should be taken to ensure there is no contention on the lines when the device is out of reset. The
CLKINSEL and OSC_DIS configuration pins should remain driven to the correct levels during device operation
and must only be changed when RESET is low. The device configuration pins are sampled during reset and
are driven after the reset is removed. At this time, the control device should ensure it has stopped driving the
device configuration pins of the DSP to again avoid contention.
Table 3−1. C6413/C6410 Device Configuration Pins (TOUT1/LENDIAN, AEA[22:19], TOUT0/HPI_EN,
HD5, CLKINSEL, and OSC_DIS)
CONFIGURATION
PIN
†
NO.
IPD/IPU
FUNCTIONAL DESCRIPTION
Device Endian mode (LEND)
TOUT1/LENDIAN
AA1
IPU
0
1
–
−
System operates in Big Endian mode
System operates in Little Endian mode (default)
Bootmode [1:0]
00 – No boot (default mode)
[M21,
N21]
01 − HPI boot (based on HPI_EN pin)
10 − Reserved
11 − EMIFA 8-bit ROM boot
AEA[22:21]
IPD
IPD
EMIFA input clock select
Clock mode select for EMIFA (AECLKIN_SEL[1:0])
00 – AECLKIN (default mode)
01 − CPU/4 Clock Rate
[P22,
N22]
AEA[20:19]
10 − CPU/6 Clock Rate
11 − Reserved
HPI, McASP1, GP0[15:8] select
Selects whether the HPI peripheral or McASP1 peripheral, and GP0[15:8] pins are
functionally enabled
0
–
HPI is enabled and the McASP1 peripheral and GP0 [15:8] pins are disabled
(default mode);
[HPI32, if HD5 = 1; HPI16 if HD5 = 0]
HPI I is disabled and the McASP1 peripheral and GP0 [15:8] pins are enabled
TOUT0/HPI_EN
AA2
IPD
1
−
For more detail on the peripherals (McASP1 and GP0[15:8] pins) muxed with HPI, see the
Table 3−2.
HPI peripheral bus width (HPI_WIDTH) select
0
−
HPI operates as an HPI16.
(HPI bus is 16 bits wide. HD[15:0] pins are used for HPI and the remaining
HD[31:16] muxed
pins function as McASP1 peripheral pins or are reserved pins in the Hi-Z state.)
HD5
Y13
IPU
1
−
HPI operates as an HPI32.
(HPI bus is 32 bits wide. All HD[31:0] pins are used for host-port operations.)
For more detail on the peripherals (McASP1 and GP0[15:8] pins) muxed with HPI, see the
Table 3−2.
44
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April 2004 − Revised May 2005
Device Configurations
Table 3−1. C6413/C6410 Device Configuration Pins (TOUT1/LENDIAN, AEA[22:19], TOUT0/HPI_EN,
HD5, CLKINSEL, and OSC_DIS) (Continued)
CONFIGURATION
†
NO.
IPD/IPU
FUNCTIONAL DESCRIPTION
PIN
PLL input clock source select
Selects whether the PLL input clock is CLKIN [pin high] or directly from the crystal oscillator
(OSCIN and OSCOUT) [pin low]. For proper device operation, this pin must be used in
conjunction with the OSC_DIS pin.
0
−
Oscillator pads (OSCIN, OSCOUT directly from the crystal oscillator)
For proper device operation, OSC_DIS must be 0
CLKIN square wave (default)
CLKINSEL
A11
IPU
1
−
For proper device operation, OSC_DIS must be 1
This pin must be pulled to the correct level even after reset.
Oscillator disable
Selects whether the Oscillator is enabled or disabled. For proper device operation, this pin
must follow the CLKINSEL pin operation.
0
1
−
−
OSC enabled
OSC disabled (default)
OSC_DIS
B7
IPU
This pin must be pulled to the correct level even after reset.
†
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
3.2
Peripheral Configuration at Device Reset
Some C6413/C6410 peripherals share the same pins (internally muxed) and are mutually exclusive (i.e., HPI,
general-purpose input/output 0 pins GP0[15:8], and McASP1).
•
HPI, McASP1, and GP0 peripherals
The TOUT0/HPI_EN (AA2 pin) is latched at reset. This pin selects whether the HPI peripheral or McASP1
peripheral, and GP0[15:8] pins are functionally enabled (see Table 3−2).
†
Table 3−2. TOUT0/HPI_EN and HD5 Peripheral Selection (HPI or McASP1 and Select GP0 Pins)
PERIPHERAL SELECTION
PERIPHERALS SELECTED
HD5
[HPI_WIDTH]
(Y13)
DESCRIPTION
HPI_EN
(AA2)
HPI
McASP1
GP0 [15:8]
HPI_EN = 0, HD5 = 0
HPI16 is enabled and McASP1 peripheral is enabled
and GP0 [15:8] pins are disabled. All multiplexed
HPI/McASP1 pins function as McASP1 pins. All
multiplexed HPI/GP0 are reserved pins in the Hi-Z state.
‡
0
0
0
1
16-bit HPI
Available
N/A
N/A
HPI_EN = 0, HD5 = 1
HPI32 is enabled and McASP1 peripheral and GP0
[15:8] pins are disabled. All multiplexed HPI/McASP1
and HPI/GP0 pins function as HPI pins.
‡
‡
32-bit HPI
N/A
HPI_EN = 1, HD5 = x (don’t care)
HPI is disabled and the McASP1 peripheral and GP0
[15:8] pins are enabled. All multiplexed HPI/McASP1
and HPI/GP0 pins function as McASP1 and GP0 pins,
respectively. To use the GP0 pins, the appropriate bits
in the GP0EN and GP0DIR registers need to be set. All
standalone HPI pins are reserved pins in the Hi-Z state
‡
1
x
N/A
Available
Available
†
‡
The TOUT0/HPI_EN pin has an internal pulldown that enables the HPI by default. The TOUT0/HPI_EN pin can disable the HPI via an external
pullup resistor or be driven high during reset. The TOUT0/HPI_EN pin is not software-controllable.
N/A = Not available
45
April 2004 − Revised May 2005
SPRS247E
Device Configurations
3.3
Peripheral Selection After Device Reset
HPI, McBSP1, McBSP0, McASP1, McASP0, I2C1, and I2C0
The C6413/C6410 device has designated registers for peripheral configuration (PERCFG), device status
(DEVSTAT), and JTAG identification (JTAGID). These registers are part of the Device Configuration module
and are mapped to a 4K block memory starting at 0x01B3F000. The CPU accesses these registers via the
CFGBUS.
The peripheral configuration register (PERCFG), allows the user to control the peripheral selection of the
McASP1, McASP0, I2C1, and I2C0 peripherals. For more detailed information on the PERCFG register
control bits, see Figure 3−1 and Table 3−3.
31
23
15
28
27
24
16
8
†
†
Reserved
R-0
Reserved
R-0
†
Reserved
R-0
11
3
10
2
9
†
†
Reserved
R-0
AFCMUX[1:0]
R/W-0
MCASP1EN
R/W-0
7
6
Reserved
R-0
5
4
1
0
†
†
I2C1EN
R/W-0
Reserved
R-0
Reserved
R-0
I2C0EN
R/W-0
MCBSP1EN
MCBSP0EN
R-1
MCASP0EN
R/W-0
R-1
Legend: R = Read only; R/W = Read/Write; -n = value after reset
†
For proper device operation, all reserved bits have to be written with “0”.
Figure 3−1. Peripheral Configuration Register (PERCFG) [Address Location: 0x01B3F000]
46
SPRS247E
April 2004 − Revised May 2005
Device Configurations
Table 3−3. Peripheral Configuration (PERCFG) Register Selection Bit Descriptions
BIT
NAME
DESCRIPTION
31:11
Reserved
Reserved. Read-only, for proper device operation, all reserved bits have to be written with “0”.
Clocks and frame syncs select bits.
Determines which of the clock and frame sync pairs are input to McASP1.
00 = ACLKR1, AFSR1 pins (default).
01 = ACLKR1[1], AFSR1[1] pins
10 = ACLKR1[2], AFSR1[2] pins
11 = ACLKR1[3], AFSR1[3] pins
10:9
AFCMUX[1:0]
MCASP1EN
[designed for multiple non-simultaneous I2S sources with different clock sources].
McASP1 select bit.
Selects whether the McASP1 peripheral is enabled or disabled (default).
(This feature allows power savings by disabling the peripheral when not in use.)
8
0
1
=
=
McASP1 is disabled and the module is powered down [default].
McASP1 is enabled.
Inter-integrated circuit 1 (I2C1) enable bit.
Selects whether I2C1 peripheral is enabled or disabled (default).
(This feature allows power savings by disabling the peripheral when not in use.)
7
6:4
3
I2C1EN
Reserved
I2C0EN
0
1
=
=
I2C1 is disabled, and the module is powered down (default).
I2C1 is enabled.
Reserved. Read-only, for proper device operation, all reserved bits have to be written with “0”.
Inter-integrated circuit 0 (I2C0) enable bit.
Selects whether I2C0 peripheral is enabled or disabled (default).
(This feature allows power savings by disabling the peripheral when not in use.)
0
1
=
=
I2C0 is disabled, and the module is powered down (default).
I2C0 is enabled.
McBSP1 enable bit.
This bit is read-only as a “1” (McBSP1 always enabled).
2
1
MCBSP1EN
MCBSP0EN
McBSP0 enable bit .
This bit is read-only as a “1” (McBSP0 always enabled).
McASP0 select bit.
Selects whether the McASP0 peripheral is enabled or disabled.
(This feature allows power savings by disabling the peripheral when not in use.)
0
MCASP0EN
0
1
=
=
McASP0 is disabled.
McASP0 is enabled.
47
April 2004 − Revised May 2005
SPRS247E
Device Configurations
3.4
Peripheral Configuration Lock
By default, the McASP1, McASP0, I2C1, and I2C0 peripherals are disabled on power up. In order to use these
peripherals on the C6413/C6410 device, the peripheral must first be enabled in the Peripheral Configuration
register (PERCFG). Software muxed pins should not be programmed to switch functionalities during
run-time. Care should also be taken to ensure that no accesses are being performed before disabling
the peripherals. To help minimize power consumption in the C6413/C6410 device, unused peripherals may
be disabled..
Figure 3−2 shows the flow needed to enable (or disable) a given peripheral on the C6413/C6410 device.
Unlock the PERCFG Register
Using the PCFGLOCK Register
Write to
PERCFG Register
to Enable/Disable Peripherals
Read from
PERCFG Register
Wait 128 CPU Cycles Before
Accessing Enabled Peripherals
Figure 3−2. Peripheral Enable/Disable Flow Diagram
A 32-bit key (value = 0x10C0010C) must be written to the Peripheral Configuration Lock register
(PCFGLOCK) in order to unlock access to the PERCFG register. Reading the PCFGLOCK register
determines whether the PERCFG register is currently locked (LOCKSTAT bit = 1) or unlocked (LOCKSTAT
bit = 0), see Figure 3−3. A peripheral can only be enabled when the PERCFG register is “unlocked”
(LOCKSTAT bit = 0).
48
SPRS247E
April 2004 − Revised May 2005
Device Configurations
Read Accesses
31
1
0
Reserved
R-0
LOCKSTAT
R-1
Write Accesses
31
0
LOCK
W-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Figure 3−3. PCFGLOCK Register Diagram [Address Location: 0x01B3 F018] − Read/Write Accesses
Table 3−4. PCFGLOCK Register Selection Bit Descriptions − Read Accesses
BIT
NAME
DESCRIPTION
31:1
Reserved
Reserved. Read-only, writes have no effect.
Lock status bit.
Determines whether the PERCFG register is locked or unlocked.
0
1
=
=
Unlocked, read accesses to the PERCFG register allowed.
Locked, write accesses to the PERCFG register do not modify the register state [default].
0
LOCKSTAT
Reads are unaffected by Lock Status.
Table 3−5. PCFGLOCK Register Selection Bit Descriptions − Write Accesses
BIT
NAME
DESCRIPTION
Lock bits.
0x10C0010C = Unlocks PERCFG register accesses.
31:0
LOCK
Any write to the PERCFG register will automatically relock the register. In order to avoid the unnecessary
overhead of multiple unlock/enable sequences, all peripherals should be enabled with a single write to the
PERCFG register with the necessary enable bits set.
Prior to waiting 128 CPU cycles, the PERCFG register should be read. There is no direct correlation between
the CPU issuing a write to the PERCFG register and the write actually occurring. Reading the PERCFG
register after the write is issued forces the CPU to wait for the write to the PERCFG register to occur.
Once a peripheral is enabled, the DSP (or other peripherals such as the HPI) must wait a minimum of 128 CPU
cycles before accessing the enabled peripheral. The user must ensure that no accesses are performed to a
peripheral while it is disabled.
In addition to the normal usage, the PCFGLOCK register can be used to override the power saver settings
specified in the PERCFG register. When the power saver feature is disabled (PCFGLOCK written with
0xC0100C01), all peripherals controlled by PERCFG are enabled. If the power saver is returned to normal
operation (PCFGLOCK written with 0x0C01C010), then the peripherals return to the operating condition
specified by PERCFG. Turning off the power saver settings will add a worst-case 50 mW of power to the overall
DSP power consumption.
Note: overriding the settings of the PERCFG register will not cause a conflict on the multiplexed pins. For
example, with the HPI and McASP1 peripherals, the HPI will still have control over the multiplexed pins
provided the TOUT0/HPI_EN pin was “0” at reset.
49
April 2004 − Revised May 2005
SPRS247E
Device Configurations
3.5
Device Status Register Description
The device status register depicts the status of the device peripheral selection. Once set, these bits will remain
set until a device reset; therefore, these bits should be masked when reading the DEVSTAT register since their
values can change. For the actual register bit names and their associated bit field descriptions, see Figure 3−4
and Table 3−6.
31
23
24
Reserved
R-100x0111
19
18
Reserved
R-1
17
16
CLKINSEL
R-x
PLLM
R-xxxxx
13
OSC EXT RES
R-x
9
15
7
14
12
CLKMODE3
R-x
11
Reserved
R-0
10
8
Reserved
R-000
HPI-WIDTH
R-x
Reserved
R-0
HPI_EN
R-x
6
5
4
3
2
1
0
CLKMODE2
R-x
CLKMODE1
R-x
CLKMODE0
R-x
LENDIAN
R-x
BOOTMODE1 BOOTMODE0 AECLKINSEL1 AECLKINSEL0
R-x R-x R-x R-x
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Figure 3−4. Device Status Register (DEVSTAT) Description − 0x01B3 F004
Table 3−6. Device Status (DEVSTAT) Register Selection Bit Descriptions
BIT
NAME
DESCRIPTION
31:24
Reserved
Reserved. Read-only, writes have no effect.
PLL multiply factor status bits.
Shows the status of the PLL multiply mode selected; whether the CPU clock frequency equals the input
clock frequency x1 (Bypass), x5, x6, x7, x8, x9, x10, x11, x12, x16, x18, x19, x20, x21, x22, or x24.
For more detailed information on the PLL multiply factors, see the Clock PLL and Oscillator section of this
data sheet.
23:19
PLLM
18
17
Reserved
Reserved. Read-only, writes have no effect.
Oscillator external resistor status bit.
Shows the status internal or external of the OSC bias resistor.
OSC EXT RES
0
1
=
=
Normal functional mode with internal bias resistor.
Normal functional mode with external bias resistor [default; internally tied high].
PLL input clock select status bit.
Shows the status of whether the PLL input clock is CLKIN [pin high] or directly from the crystal oscillator
(OSCIN and OSCOUT) [pin low]
16
CLKINSEL
0
1
=
=
Crystal oscillator (OSCIN and OSCOUT).
CLKIN (default).
15:13
11
Reserved
Reserved
Reserved. Read-only, writes have no effect.
Reserved. Read-only, writes have no effect.
HPI bus width control bit.
Shows the status of whether the HPI bus operates in 32-bit mode or in 16-bit mode (default).
10
9
HPI_WIDTH
Reserved
0
1
=
=
HPI operates in 16-bit mode. (default).
HPI operates in 32-bit mode.
Reserved. Read-only, writes have no effect.
HPI_EN pin status bit.
Shows the status at device reset of the HPI_EN pin, which controls the HPI peripheral as enabled [default]
or disabled.
8
HPI_EN
0
1
=
=
HPI_EN pin is low, meaning the HPI peripheral is enabled (default).
HPI_EN pin is high, meaning the HPI peripheral is disabled.
50
SPRS247E
April 2004 − Revised May 2005
Device Configurations
Table 3−6. Device Status (DEVSTAT) Register Selection Bit Descriptions (Continued)
BIT
NAME
DESCRIPTION
Clock mode select status bits
Shows the status (”1 or 0”) of the CLKMODE[3:0] select bits:
12
CLKMODE3
7
6
5
CLKMODE2
CLKMODE1
CLKMODE0
Clock mode select for CPU clock frequency (CLKMODE[3:0]), for example:
0000– Bypass (x1) (default mode)
For more details on the CLKMODE pins and the PLL multiply factors, see the Clock PLL section of this
data sheet.
Device Endian mode (LENDIAN)
Shows the status of whether the system is operating in Big Endian mode or Little Endian mode (default).
4
LENDIAN
0
1
–
−
System is operating in Big Endian mode
System is operating in Little Endian mode (default)
Bootmode configuration bits (AEA[22:21] pins)
Shows the status of what device bootmode configuration is operational.
Bootmode [1:0]
3
2
1
0
BOOTMODE1
BOOTMODE0
AECLKINSEL1
AECLKINSEL0
00 – No boot (default mode)
01 − HPI boot (based on HPI_EN pin)
10 − Reserved
11 − EMIFA 8-bit ROM boot
EMIFA input clock select (AEA[20:19] pins)
Shows the status of what clock mode is enabled or disabled for the EMIF.
Clock mode select for EMIFA (AECLKIN_SEL[1:0])
00 – AECLKIN (default mode)
01 − CPU/4 Clock Rate
10 − CPU/6 Clock Rate
11 − Reserved
3.6
JTAG ID Register Description
The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. For the
C6413/C6410 device, the JTAG ID register resides at address location 0x01B3 F008. The register hex value
for the C6413/C6410 device is: 0x0007 902F. For the actual register bit names and their associated bit field
descriptions, see Figure 3−5 and Table 3−7.
31−28
27−12
11−1
0
VARIANT (4-Bit)
R-0000
PART NUMBER (16-Bit)
R-0000 0000 1000 0100
MANUFACTURER (11-Bit)
R-0000 0010 111
LSB
R-1
Legend: R = Read only; -n = value after reset
Figure 3−5. JTAG ID Register Description − TMS320C6413/C6410 Register Value − 0x0007 902F
Table 3−7. JTAG ID Register Selection Bit Descriptions
BIT
31:28
27:12
11−1
0
NAME
VARIANT
DESCRIPTION
Variant (4-Bit) value. C6413/C6410 value: 0000.
PART NUMBER
MANUFACTURER
LSB
Part Number (16-Bit) value. C6413/C6410 value: 0000 0000 1000 0100.
Manufacturer (11-Bit) value. C6413/C6410 value: 0000 0010 111.
LSB. This bit is read as a “1” for C6413/C6410.
51
April 2004 − Revised May 2005
SPRS247E
Device Configurations
3.7
Multiplexed Pins
Multiplexed pins are pins that are shared by more than one peripheral and are internally multiplexed. Some
of these pins are configured by software, and the others are configured by external pullup/pulldown resistors
only at reset. Those muxed pins that are configured by software should not be programmed to switch
functionalities during run-time. Those muxed pins that are configured by external pullup/pulldown resistors
are mutually exclusive; only one peripheral has primary control of the function of these pins after reset.
Table 3−8 identifies the multiplexed pins on the C6413/C6410 device; shows the default (primary) function and
the default settings after reset; and describes the pins, registers, etc. necessary to configure specific
multiplexed functions.
Table 3−8. C6413/C6410 Device Multiplexed Pins
MULTIPLEXED PINS
NAME
DEFAULT
FUNCTION
DEFAULT
SETTING
†
IPD/IPU
DESCRIPTION
NO.
These pins are software-configurable. To use
these pins as GPIO pins, the GPxEN bits in the
GPIO Enable Register and the GPxDIR bits in
the GPIO Direction Register must be properly
configured.
CLKOUT4/GP0[1]
A2
IPU
CLKOUT4
CLKOUT6
GP1EN = 0 (disabled)
GP2EN = 0 (disabled)
GPxEN = 1:
GPxDIR = 0:
GPxDIR = 1:
GPx pin enabled
GPx pin is an input
GPx pin is an output
CLKOUT6/GP0[2]
B3
IPU
HCNTL0/AFSR1[1]
HHWIL/AFSR1[2]
HR/W/AFSR1[3]
HAS/ACLKR1[1]
HCS/ACLKR1[2]
HDS1/ACLKR1[3]
HD29/AMUTEIN1
HD28/AMUTE1
HD27/AHCLKX1
HD26/AHCLKR1
HD25/ACLKR1
HD24/ACLKX1
HD23/AFSR1
Y6
Y7
By default, HPI32 is enabled upon reset
(McASP1 is disabled).
To enable the McASP1 peripheral, the
TOUT0/HPI_EN pin must be high at reset either
via an external pullup (PU) resistor (1 kΩ) or
driven by a control device (disabling the HPI).
AA5
Y5
AA11
AB11
W11
W10
Y4
HPI pin
function
TOUT0/HPI_EN = 0,
HD5 = 1
(32-Bit HPI enabled)
or the McASP1 peripheral pins can be used if the
HPI is used as a 16-bit width [HPI_EN = 0,
HD5 = 0].
IPU
HHWIL pin
(HPI16 only)
McASP1 pins disabled.
The clocks and frame syncs select bits
(AFCMUX[1:0]) located in the PERCFG register
determine which of the clock and frame sync
pairs are input to McASP1. For more detailed
information, see the Device Configuration
section of this data sheet.
AB4
AA9
AA4
AB9
AB5
HD22/AFSX1
By default, HPI32 is enabled upon reset
(McASP1 is disabled).
To enable the McASP1 peripheral, the
TOUT0/HPI_EN pin must be high at reset either
via an external pullup (PU) resistor (1 kΩ) or
driven by a control device (disabling the HPI).
HD21/AXR1[5]
HD20/AXR1[4]
HD19/AXR1[3]
HD18/AXR1[2]
HD17/AXR1[1]
HD16/AXR1[0]
Y9
AB8
AA6
AB7
AA7
AB6
TOUT0/HPI_EN = 0,
HD5 = 1
(32-Bit HPI enabled)
HPI pin
function
IPU
or the McASP1 peripheral pins can be used if the
HPI is used as a 16-bit width [HPI_EN = 0,
HD5 = 0].
McASP1 pins disabled.
McASP1 pin direction is controlled by the
PDIR[x] bits in the McASP1PDIR register.
McASP1PDIR = 0 input, = 1 output
52
SPRS247E
April 2004 − Revised May 2005
Configuration Examples
Table 3−8. C6413/C6410 Device Multiplexed Pins (Continued)
MULTIPLEXED PINS
NAME
DEFAULT
FUNCTION
DEFAULT
SETTING
†
IPD/IPU
DESCRIPTION
NO.
Y12
HD15/GP0[15]
By default, HPI is enabled upon reset (GP0[15:9]
pins are disabled).
HD14/GP0[14]
AA12
AB13
Y14
To use GP0[15:9] as GPIO pins, the HPI needs
to be disabled (HPI_EN = 1, HD5 = x (don’t care)),
the GPxEN bits in the GPIO Enable Register and
the GPxDIR bits in the GPIO Direction Register
must be properly configured.
]
HD13/GP0[13
HPI_EN = 0, HD5 = 1
(32-Bit HPI enabled)
HD12/GP0[12]
HD11/GP0[11]
HD10/GP0[10]
HD9/GP0[9]
HPI pin
function
IPU
AB14
AA15
Y16
GPIO pins disabled.
GPxEN = 1:
GPxDIR = 0:
GPxDIR = 1:
GPx pin enabled
GPx pin is an input
GPx pin is an output
HD8/GP0[8]
AB16
‡
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
3.8
Debugging Considerations
It is recommended that external connections be provided to device configuration pins, including
TOUT1/LENDIAN, AEA[22:19], TOUT0/HPI_EN, CLKINSEL, and OSC_DIS. Although internal
pullup/pulldown resistors exist on these pins, providing external connectivity adds convenience to the user
in debugging and flexibility in switching operating modes.
Internal pullup/pulldown resistors also exist on the non-configuration pins on the AEA bus (AEA[18:3]). Do not
oppose the internal pullup/pulldown resistors on these non-configuration pins with external pullup/pulldown
resistors. If an external controller provides signals to these non-configuration pins, these signals must be
driven to the default state of the pins at reset, or not be driven at all.
For the internal pullup/pulldown resistors for all device pins, see the terminal functions table.
3.9
Configuration Examples
Figure 3−6 illustrates an example of peripheral selections/options that are configurable on the C6413/C610
device.
53
April 2004 − Revised May 2005
SPRS247E
Configuration Examples
32
AED[31:0]
CLKOUT4, CLKOUT6,
PLLV, CLKIN,
CLKMODE[3:0], OSC_DIS,
CLKINSEL, OSCIN,
Clock and
System
EMIFA
AECLKIN, AARDY, AHOLD
AEA[22:3], ACE[3:0], ABE[3:0],
AECLKOUT1, AECLKOUT2,
ASDCKE, ASOE3, APDT,
AHOLDA, ABUSREQ,
OSCOUT, OSCV
,
DD
OSCV
SS
AARE/ASDCAS/ASADS/ASRE,
AAOE/ASDRAS/ASOE,
AAWE/ASDWE/ASWE
AHCLKX0, AFSX0,
ACLKX0, AMUTE0,
AMUTEIN0,
AHCLKR0, AFSR0,
ACLKR0
McASP0
TIMER2
TIMER1
TIMER0
AXR0[5:0]
TINP1
AHCLKX1, AFSX1,
ACLKX1, AMUTE1,
AMUTEIN1, AHCLKR1,
AFSR1, AFSR1[1],
AFSR1[2], AFSR1[3],
ACLKR1, ACLKR1[1],
ACLKR1[2], ACLKR1[3]
TOUT1/LENDIAN
TINP0
McASP1
AXR1[5:0]
TOUT0
16
HD[15:0]
GP0
and
EXT_INT
HPI
(16-Bit)
GP0[ 3:0]
GP0[7:4]
HCNTL0, HCNTL1,
HHWIL, HAS, HR/W,
HCS, HDS1, HDS2
CLKR0, FSR0, DR0,
CLKS0, DX0, FSX0,
CLKX0
SCL0
SDA0
McBSP0
McBSP1
I2C0
I2C1
CLKR1, FSR1, DR1,
CLKS1, DX1, FSX1,
CLKX1
SCL1
SDA1
PERCFG Register Value:
External Pins:
0x0000_018F [CPU/4 option [default] and AFSR1, ACLKR1 pins selected]
TOUT0/HPI_EN = 0; HD5 = 0 (IPU)
Figure 3−6. Configuration Example A
(HPI16 + 2 McASPs + 2 McBSPs +2 I2Cs + EMIF + 3 Timers + GPIO)
54
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Terminal Functions
3.10 Terminal Functions
The terminal functions table (Table 3−9) identifies the external signal names, the associated pin (ball) numbers
along with the mechanical package designator, the pin type (I, O/Z, or I/O/Z), whether the pin has any internal
pullup/pulldown resistors and a functional pin description. For more detailed information on device
configuration, peripheral selection, multiplexed/shared pins, and debugging considerations, see the Device
Configurations section of this data sheet.
55
April 2004 − Revised May 2005
SPRS247E
Terminal Functions
Table 3−9. Terminal Functions
SIGNAL
NAME
IPD/
IPU
†
DESCRIPTION
TYPE
‡
NO.
CLOCK/PLL CONFIGURATION
CLKIN
A12
A2
I
IPD
IPU
Clock Input. This clock is the input to the on-chip PLL.
Clock output at 1/4 of the device speed (O/Z) [default] or this pin can be programmed as
a GP0 1 pin (I/O/Z).
§
CLKOUT4/GP0[1]
I/O/Z
I/O/Z
Clock output at 1/6 of the device speed (O/Z) [default] or this pin can be programmed as
a GP0 2 pin (I/O/Z).
§
CLKOUT6/GP0[2]
B3
IPU
IPU
CLKIN select. Selects whether the PLL input clock is CLKIN [pin high] or directly from
the crystal oscillator (OSCIN and OSCOUT) [pin low].
For proper device operation, this pin must be used in conjunction with the OSC_DIS
pin.
CLKINSEL
A11
I
CLKMODE3
CLKMODE2
CLKMODE1
CLKMODE0
C11
B10
A13
C13
C12
A6
I
I
IPD
IPD
IPD
IPD
Clock mode selects
•
Selects whether the CPU clock frequency = input clock frequency x1 (Bypass), x5,
x6, x7, x8, x9, x10, x11, x12, x16, x18, x19, x20, x21, x22, or x24.
For more details on the CLKMODE pins and the PLL multiply factors, see the Clock
PLL section of this data sheet.
I
I
¶
PLLV
A
I
PLL voltage supply
OSCIN
—
—
Crystal oscillator Input (XI)
Crystal oscillator output (XO)
OSCOUT
A7
O
Power for crystal oscillator (1.2 V), Do not connect to board power 1.4 V; for optimum
OSCV
OSCV
B6
C6
S
—
—
performance, connected internally. If CLKIN is used instead of the oscillator, then this
DD
SS
pin can be left open or connected to CV
.
DD
Ground for crystal oscillator, Do not connect to board ground; for optimum
performance, connected internally. If CLKIN is used instead of the oscillator, then this
GND
pin can be left open or connected to V
.
SS
Oscillator disable select.
For proper device operation, this pin must follow the CLKINSEL pin operation.
OSC_DIS
B7
I
IPU
0
1
−
−
OSC enabled; CLKINSEL must be 0
OSC disabled (default); CLKINSEL must be 1
JTAG EMULATION
JTAG test-port mode select
JTAG test-port data out
JTAG test-port data in
JTAG test-port clock
TMS
TDO
TDI
U3
T4
T1
T2
I
IPU
IPU
IPU
IPU
O/Z
I
I
TCK
JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see the IEEE 1149.1 JTAG
compatibility statement portion of this data sheet.
TRST
U1
I
IPD
#
EMU0
R1
T3
I/O/Z
I/O/Z
IPU
IPU
Emulation pin 0
#
EMU1
Emulation pin 1
†
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog Signal
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
PLLV is not part of external voltage supply. See the Clock PLL and Oscillator section for information on how to connect this pin.
The EMU0 and EMU1 pins are internally pulled up with 30-kΩ resistors; therefore, for emulation and normal operation, no external
pullup/pulldown resistors are necessary. However, for boundary scan operation, pull down the EMU1 and EMU0 pins with a dedicated 1-kΩ
resistor.
‡
§
¶
#
56
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April 2004 − Revised May 2005
Terminal Functions
Table 3−9. Terminal Functions (Continued)
IPD/
IPU
†
NAME
NO.
DESCRIPTION
TYPE
‡
JTAG EMULATION (CONTINUED)
EMU2
EMU3
EMU4
EMU5
EMU6
EMU7
EMU8
EMU9
EMU10
EMU11
R2
U2
R3
P2
R4
V2
V1
V3
W3
W2
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
Emulation pin 2. Reserved for future use, leave unconnected.
Emulation pin 3. Reserved for future use, leave unconnected.
Emulation pin 4. Reserved for future use, leave unconnected.
Emulation pin 5. Reserved for future use, leave unconnected.
Emulation pin 6. Reserved for future use, leave unconnected.
Emulation pin 7. Reserved for future use, leave unconnected.
Emulation pin 8. Reserved for future use, leave unconnected.
Emulation pin 9. Reserved for future use, leave unconnected.
Emulation pin 10. Reserved for future use, leave unconnected.
Emulation pin 11. Reserved for future use, leave unconnected.
RESETS, INTERRUPTS, AND GENERAL-PURPOSE INPUT/OUTPUTS
RESET
NMI
C9
B9
I
I
Device reset
IPD
IPU
Nonmaskable interrupt, edge-driven (rising edge)
GP0[7]/EXT_INT7
GP0[6]/EXT_INT6
GP0[5]/EXT_INT5
GP0[4]/EXT_INT4
Y1
C4
B4
A4
I/O/Z
I/O/Z
I/O/Z
I/O/Z
General-purpose input/output (GPIO) pins (I/O/Z) or external interrupts (input only).
The default after reset setting is GPIO enabled as input-only.
IPU
IPU
IPU
•
When these pins function as External Interrupts [by selecting the corresponding
interrupt enable register bit (IER.[7:4])], they are edge-driven and the polarity can be
independently selected via the External Interrupt Polarity Register bits
(EXTPOL.[3:0]).
HD15/GP0[15]
HD14/GP0[14]
Y12
AA12
AB13
Y14
]
HD13/GP0[13
Host-port data pins (I/O/Z) [default] or General-purpose input/output (GP0) [15:8] pins
(I/O/Z)
HD12/GP0[12]
HD11/GP0[11]
HD10/GP0[10]
HD9/GP0[9]
HD8/GP0[8]
GP0[3]
I/O/Z
IPU
AB14
AA15
Y16
GP0 [3:0] pins (I/O/Z)
Clock output at 1/6 of the device speed (O/Z) [default] or this pin can be programmed as
a GP0 2 pin (I/O/Z).
AB16
B13
Clock output at 1/4 of the device speed (O/Z) [default] or this pin can be programmed as
a GP0 1 pin (I/O/Z).
I/O/Z
I/O/Z
I/O/Z
I/O/Z
IPD
IPU
IPU
IPD
§
CLKOUT6/GP0[2]
CLKOUT4/GP0[1]
B3
§
A2
GP0[0]
D13
†
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog Signal
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
‡
§
These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
57
April 2004 − Revised May 2005
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Terminal Functions
Table 3−9. Terminal Functions (Continued)
IPD/
IPU
†
NAME
NO.
DESCRIPTION
TYPE
‡
EMIFA (32-BIT) − CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY
ACE3
ACE2
ACE1
ACE0
ABE3
ABE2
ABE1
ABE0
APDT
H19
N20
R20
F20
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
EMIFA memory space enables
•
•
Enabled by bits 28 through 31 of the word address
Only one pin is asserted during any external data access
AB21
P21
A22
D16
T19
EMIFA byte-enable control
•
Decoded from the low-order address bits. The number of address bits or byte
enables used depends on the width of external memory.
•
•
Byte-write enables for most types of memory
Can be directly connected to SDRAM read and write mask signal (SDQM)
EMIFA peripheral data transfer, allows direct transfer between external peripherals
EMIFA (32-BIT) − BUS ARBITRATION
AHOLDA
AHOLD
J21
J22
R19
O
I
IPU
EMIFA hold-request-acknowledge to the host
EMIFA hold request from the host
EMIFA bus request output
IPU
IPU
ABUSREQ
O
EMIFA (32-BIT) − ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL
EMIFA external input clock. The EMIFA input clock (AECLKIN, CPU/4 clock, or CPU/6
AECLKIN
K22
I
IPD
clock) is selected at reset via the pullup/pulldown resistors on the AEA[20:19] pins.
AECLKIN is the default for the EMIFA input clock.
EMIFA output clock 2. Programmable to be EMIFA input clock (AECLKIN, CPU/4 clock,
or CPU/6 clock) frequency divided-by-1, -2, or -4.
AECLKOUT2
AECLKOUT1
U22
F22
O/Z
O/Z
IPD
IPD
EMIFA output clock 1 [at EMIFA input clock (AECLKIN, CPU/4 clock, or CPU/6 clock)
frequency].
EMIFA asynchronous memory read-enable/SDRAM column-address
strobe/programmable synchronous interface-address strobe or read-enable
AARE/
ASDCAS/
ASADS/ASRE
•
For programmable synchronous interface, the RENEN field in the CE Space
Secondary Control Register (CExSEC) selects between ASADS and ASRE:
If RENEN = 0, then the ASADS/ASRE signal functions as the ASADS signal.
If RENEN = 1, then the ASADS/ASRE signal functions as the ASRE signal.
D20
E20
O/Z
O/Z
IPU
IPU
AAOE/
ASDRAS/
ASOE
EMIFA asynchronous memory output-enable/SDRAM row-address
strobe/programmable synchronous interface output-enable
AAWE/
ASDWE/
ASWE
EMIFA asynchronous memory write-enable/SDRAM write-enable/programmable
synchronous interface write-enable
C20
K21
O/Z
O/Z
IPU
IPU
EMIFA SDRAM clock-enable (used for self-refresh mode).
ASDCKE
ASOE3
•
If SDRAM is not in system, ASDCKE can be used as a general-purpose output.
P19
L21
O/Z
I
IPU
IPU
EMIFA synchronous memory output-enable for ACE3 (for glueless FIFO interface)
Asynchronous memory ready input
AARDY
†
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog Signal
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
‡
§
These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
58
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April 2004 − Revised May 2005
Terminal Functions
Table 3−9. Terminal Functions (Continued)
IPD/
IPU
†
NAME
NO.
DESCRIPTION
TYPE
‡
EMIFA (32-BIT) − ADDRESS
AEA22
AEA21
AEA20
AEA19
AEA18
AEA17
AEA16
AEA15
AEA14
AEA13
AEA12
AEA11
AEA10
AEA9
M21
N21
P22
N22
H22
H21
J20
I/O/Z
IPD
EMIFA external address (word address)
Note: EMIF address numbering for the C6413/C6410 devices starts with AEA3 to
maintain signal name compatibility with other C64x™ devices (e.g., C6411, C6414,
C6415, and C6416) [see the 64-bit EMIF adressing scheme in the TMS320C6000 DSP
External Memory Interface (EMIF) Reference Guide (literature number SPRU266)].
•
Also controls initialization of DSP modes at reset (I) via pullup/pulldown resistors
− Boot mode (AEA[22:21]):
H20
G20
K20
B21
B22
D21
D22
E21
E22
F21
M20
J19
00 – No boot (default mode)
01 − HPI boot (based on HPI_EN pin)
10 − Reserved
11 − EMIFA 8-bit ROM boot
− EMIF clock select
O/Z
IPD
− AEA[20:19]: Clock mode select for EMIFA (AECLKIN_SEL[1:0])
00 – AECLKIN (default mode)
01 − CPU/4 Clock Rate
AEA8
AEA7
10 − CPU/6 Clock Rate
11 − Reserved
AEA6
AEA5
For more details, see the Device Configurations section of this data sheet.
AEA4
AEA3
L20
EMIFA (32-BIT) − DATA
AED31
AED30
AED29
AED28
AED27
AED26
AED25
AED24
AED23
AED22
AED21
AED20
AED19
AED18
AED17
AED16
AED15
W21
W22
V20
W20
AA22
Y20
AA21
AB22
P20
I/O/Z
IPU
EMIFA external data
R22
R21
U21
V21
T20
V22
U20
A18
AED14
D17
†
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog Signal
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
‡
§
These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
59
April 2004 − Revised May 2005
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Terminal Functions
Table 3−9. Terminal Functions (Continued)
IPD/
IPU
†
NAME
NO.
DESCRIPTION
TYPE
‡
EMIFA (32-BIT) − DATA (CONTINUED)
AED13
AED12
AED11
AED10
AED9
AED8
AED7
AED6
AED5
AED4
AED3
AED2
AED1
AED0
B18
C18
A19
C19
B19
A21
D15
A15
B15
C15
A16
C16
B16
C17
I/O/Z
IPU
EMIFA external data
TIMER 2
−
No external pins. The timer 2 peripheral pins are not pinned out as external pins.
TIMER 1
Timer 1 output (O/Z) or device endian mode (I).
Also controls initialization of DSP modes at reset via pullup/pulldown resistors
− Device Endian mode
TOUT1/LENDIAN
TINP1
AA1
AB1
I/O/Z
I
IPU
IPD
0
1
–
−
Big Endian
Little Endian (default)
For more details on LENDIAN, see the Device Configurations section of this data sheet.
Timer 1 or general-purpose input
TIMER 0
Timer 0 output pin and HPI enable HPI_EN pin function
The HPI_EN pin function selects whether the HPI peripheral or McASP1 peripheral,
and GP0[15:8] pins are functionally enabled
0
–
HPI is enabled and the McASP1 peripheral and GP0 [15:8] pins are disabled
(default mode); [HPI32, if HD5 = 1; HPI16 if HD5 = 0]
HPI I is disabled and the McASP1 peripheral and GP0 [15:8] pins are
enabled
TOUT0/HPI_EN
TINP0
AA2
AB2
I/O/Z
IPD
IPD
1
−
For more details, see the Device Configurations section of this data sheet.
I
Timer 0 or general-purpose input
INTER-INTEGRATED CIRCUIT 1 (I2C1)
SCL1
SDA1
AA18
AA19
I/O/Z
I/O/Z
—
I2C1 clock. When the I2C module is used, use an external pullup resistor on this pin.
I2C1 data. When I2C is used, ensure there is an external pullup resistors on this pin.
—
INTER-INTEGRATED CIRCUIT 0 (I2C0)
SCL0
AB18
AB19
I/O/Z
I/O/Z
—
I2C0 clock. When I2C is used, ensure there is an external pullup resistors on this pin.
I2C0 data. When I2C is used, ensure there is an external pullup resistors on this pin.
SDA0
—
†
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog Signal
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
‡
§
These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
60
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April 2004 − Revised May 2005
Terminal Functions
Table 3−9. Terminal Functions (Continued)
IPD/
IPU
†
NAME
NO.
DESCRIPTION
TYPE
‡
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)
CLKR1
FSR1
DR1
G3
G2
F1
I/O/Z
I/O/Z
I
IPD
IPD
IPD
IPD
IPD
IPD
IPD
McBSP1 receive clock
McBSP1 receive frame sync
McBSP1 receive data
CLKS1
DX1
G1
H2
H3
H1
I
McBSP1 external clock source (as opposed to internal)
McBSP1 transmit data
O/Z
I/O/Z
I/O/Z
FSX1
CLKX1
McBSP1 transmit frame sync
McBSP1 transmit clock
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)
CLKR0
FSR0
DR0
C2
D1
D2
D3
E2
E4
E3
I/O/Z
I/O/Z
I
IPD
IPD
IPD
IPD
IPD
IPD
IPD
McBSP0 receive clock
McBSP0 receive frame sync
McBSP0 receive data
CLKS0
DX0
I
McBSP0 external clock source (as opposed to internal)
McBSP0 transmit data
O/Z
I/O/Z
I/O/Z
FSX0
CLKX0
McBSP0 transmit frame sync
McBSP0 transmit clock
MULTICHANNEL AUDIO SERIAL PORT 0 (McASP0)
AHCLKX0
AFSX0
N1
M2
M1
K4
J4
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
McASP0 transmit high-frequency master clock.
McASP0 transmit frame sync or left/right clock (LRCLK).
McASP0 transmit bit clock.
ACLKX0
AMUTE0
AMUTEIN0
AHCLKR0
AFSR0
McASP0 mute output.
McASP0 mute input.
L1
I/O/Z
I/O/Z
I/O/Z
McASP0 receive high-frequency master clock.
McASP0 receive frame sync or left/right clock (LRCLK).
McASP0 receive bit clock.
K2
K1
P3
N3
M3
L3
ACLKR0
AXR0[5]
AXR0[4]
AXR0[3]
AXR0[2]
AXR0[1]
McASP0 TX/RX data pin [5].
McASP0 TX/RX data pin [4].
McASP0 TX/RX data pins [3].
I/O/Z
IPD
McASP0 TX/RX data pin [2].
K3
L2
McASP0 TX/RX data pin [1].
AXR0[0]
McASP0 TX/RX data pins[0].
†
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog Signal
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
‡
§
These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
61
April 2004 − Revised May 2005
SPRS247E
Terminal Functions
Table 3−9. Terminal Functions (Continued)
IPD/
IPU
†
NAME
NO.
DESCRIPTION
TYPE
‡
MCASP1
Host control − selects between control, address, or data registers (I) [default] or
McASP1 receive frame sync input 1 (I).
HCNTL0/AFSR1[1]
HHWIL/AFSR1[2]
Y6
Y7
Host half-word select − first or second half-word (not necessarily high or low order)
[For HPI16 bus width selection only] (I) [default] oror McASP1 receive frame sync
input 2 (I) .
I
IPU
HR/W/AFSR1[3]
HAS/ACLKR1[1]
HCS/ACLKR1[2]
HDS1/ACLKR1[3]
AA5
Y5
Host read or write select (I) [default] or McASP1 receive frame sync input 3 (I).
Host address strobe (I) [default] or McASP1 receive clock input 1 (I).
Host chip select (I) [default] or McASP1 receive clock input 2 (I).
Host data strobe 1 (I) [default] or McASP1 receive clock input 3 (I).
AA11
AB11
Host-port data pin 27 (I/O/Z) [default] or McASP1 transmit high-frequency master clock
(I/O/Z).
HD27/AHCLKX1
HD22/AFSX1
Y4
I/O/Z
I/O/Z
IPU
IPU
Host-port data pin 22 (I/O/Z) [default] or McASP1 transmit frame sync or left/right clock
(LRCLK) (I/O/Z) .
AB5
HD24/ACLKX1
HD28/AMUTE1
HD29/AMUTEIN1
AA4
W10
W11
I/O/Z
I/O/Z
I
IPU
IPU
IPU
Host-port data pin 24 (I/O/Z) [default] or McASP1 transmit bit clock (I/O/Z).
Host-port data pin 28 (I/O/Z) [default] or McASP1 mute output (I/O/Z).
Host-port data pin 29 (I/O/Z) [default] or McASP1 mute input (I).
Host-port data pin 26 (I/O/Z) [default] or McASP1 receive high-frequency master clock
(I/O/Z).
HD26/AHCLKR1
HD23/AFSR1
AB4
AB9
I/O/Z
IPU
Host-port data pin 23 (I/O/Z) [default] or McASP1 receive frame sync or left/right clock
(LRCLK) (I/O/Z).
I/O/Z
I/O/Z
IPU
IPU
HD25/ACLKR1
HD21/AXR1[5]
HD20/AXR1[4]
HD19/AXR1[3]
HD18/AXR1[2]
HD17/AXR1[1]
HD16/AXR1[0]
AA9
Y9
Host-port data pin 25 (I/O/Z) [default] or McASP1 receive bit clock (I/O/Z).
AB8
AA6
AB7
AA7
AB6
I/O/Z
IPU
Host-port data pins [21:16] (I/O/Z) [default] or McASP1 TX/RX data pins [5:0] (I/O/Z).
HOST-PORT INTERFACE (HPI)
HINT
AA8
W7
O/Z
I
IPU
IPU
Host interrupt from DSP to host (O)
HCNTL1
Host control − selects between control, address, or data registers (I)
Host control − selects between control, address, or data registers (I) [default] or
McASP1 receive frame sync input 1 (I).
HCNTL0/AFSR1[1]
HHWIL/AFSR1[2]
Y6
Y7
Host half-word select − first or second half-word (not necessarily high or low order)
[For HPI16 bus width selection only] (I) [default] or McASP1 receive frame sync
input 2 (I).
I
IPU
HR/W/AFSR1[3]
HAS/ACLKR1[1]
HCS/ACLKR1[2]
HDS1/ACLKR1[3]
HDS2
AA5
Y5
Host read or write select (I) [default] or McASP1 receive frame sync input 3 (I).
Host address strobe (I) [default] or McASP1 receive clock input 1 (I).
Host chip select (I) [default] or McASP1 receive clock input 2 (I).
Host data strobe 1 (I) [default] or McASP1 receive clock input 3 (I).
Host data strobe 2 (I)
AA11
AB11
AB12
Y10
I
IPU
IPU
HRDY
O/Z
Host ready from DSP to host (O)
†
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog Signal
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
‡
§
These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
62
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Terminal Functions
Table 3−9. Terminal Functions (Continued)
IPD/
IPU
†
NAME
NO.
DESCRIPTION
TYPE
‡
HOST-PORT INTERFACE (HPI) (CONTINUED)
HD31
HD30
Y8
I/O/Z
I/O/Z
I
IPU
IPU
IPU
IPU
Host-port data pin 31 (I/O/Z)
Y11
W11
W10
Host-port data pin 30 (I/O/Z)
HD29/AMUTEIN1
HD28/AMUTE1
Host-port data pin 29 (I/O/Z) [default] or McASP1 mute input (I).
I/O/Z
Host-port data pin 28 (I/O/Z) [default] or McASP1 mute output (I/O/Z).
Host-port data pin 27 (I/O/Z) [default] or McASP1 transmit high-frequency master clock
(I/O/Z).
HD27/AHCLKX1
HD26/AHCLKR1
Y4
I/O/Z
I/O/Z
IPU
IPU
Host-port data pin 26 (I/O/Z) [default] or McASP1 receive high-frequency master clock
(I/O/Z).
AB4
HD25/ACLKR1
HD24/ACLKX1
AA9
AA4
I/O/Z
I/O/Z
IPU
IPU
Host-port data pin 25 (I/O/Z) [default] or McASP1 receive bit clock (I/O/Z).
Host-port data pin 24 (I/O/Z) [default] or McASP1 transmit bit clock (I/O/Z).
Host-port data pin 23 (I/O/Z) [default] or McASP1 receive frame sync or left/right clock
(LRCLK) (I/O/Z).
HD23/AFSR1
HD22/AFSX1
AB9
AB5
I/O/Z
I/O/Z
IPU
IPU
Host-port data pin 22 (I/O/Z) [default] or McASP1 transmit frame sync or left/right clock
(LRCLK) (I/O/Z).
HD21/AXR1[5]
HD20/AXR1[4]
HD19/AXR1[3]
HD18/AXR1[2]
HD17/AXR1[1]
HD16/AXR1[0]
HD15/GP0[15]
HD14/GP0[14]
Y9
AB8
AA6
I/O/Z
IPU
Host-port data [21:16] pin (I/O/Z) [default] or McASP1 TX/RX data pins [5:0] (I/O/Z).
AB7
AA7
AB6
Y12
AA12
AB13
Y14
]
HD13/GP0[13
HD12/GP0[12]
HD11/GP0[11]
HD10/GP0[10]
HD9/GP0[9]
HD8/GP0[8]
HD7
Host-port data [15:8] pins (I/O/Z) [default] or General-purpose input/output (GP0) [15:8]
pins (I/O/Z).
I/O/Z
IPU
AB14
AA15
Y16
AB16
W12
AA13
Y13
Host-port data [7:0] pins (I/O/Z)
HD6
Host-Port bus width user-configurable at device reset via a 1-kΩ pullup/
pulldown resistor on the HD5 pin (I):
HD5
HD4
AA14
AB15
AA16
Y15
I/O/Z
IPU
HD5 pin = 0: HPI operates as an HPI16.
(HPI bus is 16 bits wide. HD[15:0] pins are used and the remaining HD[31:16] pins
are reserved pins in the high-impedance state.)
HD3
HD2
HD1
HD5 pin = 1: HPI operates as an HPI32.
HD0
W15
(HPI bus is 32 bits wide. All HD[31:0] pins are used for host-port operations.)
†
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog Signal
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
‡
§
These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
63
April 2004 − Revised May 2005
SPRS247E
Terminal Functions
Table 3−9. Terminal Functions (Continued)
SIGNAL
NAME
IPD/
IPU
†
DESCRIPTION
TYPE
‡
NO.
RESERVED FOR TEST
Reserved. This pin must be connected directly to CV for proper device operation.
RSV
RSV
RSV
U4
F3
A
A
—
—
DD
Reserved. This pin must be connected directly to DV for proper device operation.
DD
C8
I
IPD
—
Reserved. This pin must be connected directly to V for proper device operation.
SS
B11
B12
C10
D7
A
I
—
O
IPU
—
RSV
Reserved (leave unconnected, do not connect to power or ground)
O/Z
O/Z
D8
—
SUPPLY VOLTAGE PINS
A3
A5
A8
A9
A14
A17
A20
B1
C22
E1
G22
J1
DV
S
3.3-V supply voltage
DD
M22
P1
T22
W1
Y2
Y17
Y19
Y22
AB3
AB10
AB17
AB20
†
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog Signal
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
‡
64
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April 2004 − Revised May 2005
Terminal Functions
Table 3−9. Terminal Functions (Continued)
SIGNAL
NAME
IPD/
IPU
†
DESCRIPTION
TYPE
‡
NO.
SUPPLY VOLTAGE PINS (CONTINUED)
D5
D6
D9
D11
D12
D14
D18
E19
F19
G4
H4
CV
S
1.2-V supply voltage (-400, -500 devices)
DD
L19
M4
M19
N4
V4
V19
W5
W9
W13
W16
W18
GROUND PINS
A1
A10
B2
B5
B8
B14
B17
B20
C1
V
SS
GND
Ground pins
C3
C5
C7
†
‡
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog Signal
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
65
April 2004 − Revised May 2005
SPRS247E
Terminal Functions
Table 3−9. Terminal Functions (Continued)
SIGNAL
NAME
IPD/
IPU
†
DESCRIPTION
TYPE
‡
NO.
GROUND PINS (CONTINUED)
C14
C21
D4
D10
D19
F2
F4
G19
G21
J2
J3
K19
L4
L22
N2
N19
P4
V
SS
GND
Ground pins
T21
U19
W4
W6
W8
W14
W17
W19
Y3
Y18
Y21
AA3
AA10
AA17
AA20
†
‡
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog Signal
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
66
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Development Support
3.11 Development Support
In case the customer would like to develop their own features and software on the TMS320C6413/C6410
device, TI offers an extensive line of development tools for the TMS320C6000™ DSP platform, including tools
to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully
integrate and debug software and hardware modules. The tool’s support documentation is electronically
available within the Code Composer Studio™ Integrated Development Environment (IDE).
The following products support development of C6000™ DSP-based applications:
Software Development Tools:
Code Composer Studio™ Integrated Development Environment (IDE): including Editor
C/C++/Assembly Code Generation, and Debug plus additional development tools
Scalable, Real-Time Foundation Software (DSP/BIOS™), which provides the basic run-time target software
needed to support any DSP application.
Hardware Development Tools:
Extended Development System (XDS™) Emulator (supports C6000™ DSP multiprocessor system debug)
EVM (Evaluation Module)
For a complete listing of development-support tools for the TMS320C6000™ DSP platform, visit the Texas
Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). For
information on pricing and availability, contact the nearest TI field sales office or authorized distributor.
Code Composer Studio, DSP/BIOS, and XDS are trademarks of Texas Instruments.
67
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Device Support
3.12 Device Support
3.12.1 Device and Development-Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all DSP
devices and support tools. Each DSP commercial family member has one of three prefixes: TMX, TMP, or TMS
(e.g., TMS320C6412GDK600). Texas Instruments recommends two of three possible prefix designators for
its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development
from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).
Device development evolutionary flow:
TMX Experimental device that is not necessarily representative of the final device’s electrical
specifications.
TMP Final silicon die that conforms to the device’s electrical specifications but has not completed quality
and reliability verification.
TMS Fully qualified production device.
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal qualification
testing.
TMDS Fully qualified development-support product.
TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:
“Developmental product is intended for internal evaluation purposes.”
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI’s standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package
type (for example, GTS), the temperature range (for example, “A” is the extended temperature range), and
the device speed range in megahertz (for example, -500 is 500 MHz). Figure 3−7 provides a legend for
reading the complete device name for any TMS320C6000™ DSP platform member.
The ZTS package, like the GTS package, is a 288-ball plastic BGA only with PB-free balls. For device part
numbers and further ordering information for TMS320C6413/C6410 in the GTS and ZTS package types, see
the TI website (http://www.ti.com) or contact your TI sales representative.
68
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Device Support
( A )
TMS 320 C6413 GTS
500
PREFIX
DEVICE SPEED RANGE
TMX= Experimental device
500 (500-MHz CPU, 100-MHz EMIF) [C6413]
400 (400-MHz CPU, 100-MHz EMIF) [C6410]
TMP= Prototype device
TMS= Qualified device
SMX= Experimental device, MIL
SMJ = MIL-PRF-38535, QML
SM = High Rel (non-38535)
†
TEMPERATURE RANGE (DEFAULT: 0°C TO 90°C)
Blank = 0°C to 90°C, commercial temperature
A
=
−40°C to 105°C, extended temperature
DEVICE FAMILY
320 = TMS320t DSP family
‡§
PACKAGE TYPE
GTS = 288-pin plastic BGA
ZTS = 288-pin plastic BGA, with Pb-free soldered balls
¶
DEVICE
C64x DSP:
6413
6410
†
The extended temperature “A version” devices may have different operating conditions than the commercial temperature devices.
For more details, see the recommended operating conditions portion of this data sheet.
‡
§
BGA
=
Ball Grid Array
The ZTS mechanical package designator represents the version of the GTS package with Pb-free balls. For more detailed
information, see the Mechanical Data section of this document.
For actual device part numbers (P/Ns) and ordering information, see the TI website (www.ti.com).
¶
Figure 3−7. TMS320C6413/C6410 DSP Device Nomenclature
For additional information, see the TMS320C6413, TMS320C6410 Digital Signal Processors Silicon Errata
(literature number SPRZ219)
69
April 2004 − Revised May 2005
SPRS247E
Device Support
3.12.2 Documentation Support
Extensive documentation supports all TMS320™ DSP family generations of devices from product
announcement through applications development. The types of documentation available include: data
sheets, such as this document, with design specifications; complete user’s reference guides for all devices
and tools; technical briefs; development-support tools; on-line help; and hardware and software applications.
The following is a brief, descriptive list of support documentation specific to the C6000™ DSP devices:
The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the
C6000™ DSP CPU (core) architecture, instruction set, pipeline, and associated interrupts.
The TMS320C6000 DSP Peripherals Overview Reference Guide (literature number SPRU190) provides an
overview and briefly describes the functionality of the peripherals available on the C6000™ DSP platform of
devices. This document also includes a table listing the peripherals available on the C6000 devices along with
literature numbers and hyperlinks to the associated peripheral documents.
The TMS320C64x Technical Overview (literature number SPRU395) gives an introduction to the C64x™
digital signal processor, and discusses the application areas that are enhanced by the C64x™ DSP
VelociTI.2™ VLIW architecture.
The TMS320C6000 DSP Multichannel Audio Serial Port (McASP) Reference Guide (literature number
SPRU041) describes the functionality of the McASP peripheral.
TMS320C6000 DSP Inter-Integrated Circuit (I2C) Module Reference Guide (literature number SPRU175)
describes the functionality of the I2C peripherals available on the C6413/C6410 device except for the
additional interrupt and new GPIO capability. For more detailed information on the additional interrupt and
GPIO capability, see the I2C section of this data manual and the TMS320C6410/C6413 DSP Inter-Integrated
Circuit (I2C) Module Reference Guide (literature number SPRZ221).
The TMS320C6413, TMS320C6410 Digital Signal Processors Silicon Errata (literature number SPRZ219)
describes the known exceptions to the functional specifications for particular silicon revisions of the
TMS320C6413 and TMS320C6410 devices.
The Using IBIS Models for Timing Analysis application report (literature number SPRA839) describes how to
properly use IBIS models to attain accurate timing analysis for a given system.
The tools support documentation is electronically available within the Code Composer Studio™ Integrated
Development Environment (IDE). For a complete listing of C6000™ DSP latest documentation, visit the Texas
Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL).
TMS320 is a trademark of Texas Instruments.
70
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Peripherals Detailed Description (Device-Specific)
4
Peripherals Detailed Description (Device-Specific)
4.1
Clock PLL and Oscillator
Most of the internal C64x™ DSP clocks are generated from a single source through the CLKIN pin. This source
clock either drives the PLL, which multiplies the source clock frequency to generate the internal CPU clock,
or bypasses the PLL to become the internal CPU clock.
To use the PLL to generate the CPU clock, the external PLL filter circuit must be properly designed. Figure 4−1
shows the external PLL circuitry for either x1 (PLL bypass) or other PLL multiply modes.
To minimize the clock jitter, a single clean power supply should power both the C64x™ DSP device and the
external clock oscillator circuit. The minimum CLKIN rise and fall times should also be observed. For the input
clock timing requirements, see the input and output clocks electricals section.
Rise/fall times, duty cycles (high/low pulse durations), and the load capacitance of the external clock source
must meet the DSP requirements in this data sheet (see the electrical characteristics over recommended
ranges of supply voltage and operating case temperature table and the input and output clocks electricals
section).
71
April 2004 − Revised May 2005
SPRS247E
Clock PLL and Oscillator
3.3 V
CPU Clock
C1
C2
Peripheral Bus, EDMA
Clock
EMI
Filter
/2
/8
/4
/6
10 µF 0.1 µF
Timer Internal Clock
CLKOUT4, Peripheral Clock
CLKOUT6
PLLV
CLKMODE0
CLKMODE1
CLKMODE2
CLKMODE3
PLLMULT
PLL
x5, x6−x12, x16,
x18−x22, x24
00 01 10
PLLCLK
1
0
/4
/2
CLKINSEL
CLKIN
EK2RATE
00 01 10
EMIF
(GBLCTL.[19,18])
C5
470 pF
‡
OSCV
DD
1
AUXCLK
for McASPs
OSCIN
†
C7
0
†
Osc.
‡
†
R
OSCOUT
†
†
C8
R
B
S
‡
OSCV
SS
C6
470 pF
OSC_DIS
AECLKIN
AEA[20:19]
Internal to C6413/10
(For the PLL options, CLKMODE pins setup, and PLL clock frequency ranges,
see Table 4−1 and Table 4−2.)
ECLKOUT1 ECLKOUT2
†
‡
Exact values for these components depend on choice of crystal. For recommended crystal and component values, see Table 4−3.
Do not connect any of these nodes to board power or ground if the oscillator is used. They are internally connected for proper operation.
If CLKIN is being used instead of the oscillator, then OSCV and OSCV may either be left open, or OSCV may be tied to CV and
DD
SS
DD
DD
OSCV may be tied to ground.
SS
NOTES: A. Place all PLL external components (C1, C2, and the EMI Filter) as close to the C6000™ DSP device as possible. For the best
performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or
components other than the ones shown.
B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (C1, C2, and the EMI
Filter).
C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DV
.
DD
D. EMI filter manufacturer TDK part number ACF451832-333, -223, -153, -103. Panasonic part number EXCCET103U.
E. If CLKIN is used instead of OSCIN, tie OSCIN to Ground to minimize noise and current. (Do not leave OSCIN floating.)
Figure 4−1. External PLL Circuitry for Either PLL Multiply Modes or x1 (Bypass) Mode
72
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Clock PLL and Oscillator
For proper C6413/C6410 device operation, the CLKINSEL pin must be used in conjunction with the OSC_DIS
pin. The OSC_DIS pin must follow the CLKINSEL pin operation. For more details on these two configuration
pins, see the Device Configuration at Device Reset section of this data sheet.
Table 4−1. TMS320C6413 PLL Multiply Factor Options, Clock Frequency Ranges,
†
and Typical Lock Time for −500 Devices
GTS and ZTS PACKAGES − 23 x 23 mm BGA
CPU CLOCK
FREQUENCY
RANGE
CPU CLOCK
FREQUENCY
RANGE
CLKIN
RANGE
(MHz)
OSCIN
RANGE
(MHz)
TYPICAL
CLKMODE
(PLL MULTIPLY FACTORS)
CLKMODE[3:0]
LOCK TIME
‡
(µs)
(MHz)
(MHz)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Bypass (x1)
x5
12−100
28−100
23−83
20−71
17−63
15−56
14−50
12−45
12−42
12−31
12−28
12−26
12−25
12−24
12−23
12−21
12−100
140−500
140−500
140−500
140−500
140−500
140−500
140−500
144−500
192−500
216−500
228−500
240−500
252−500
264−500
288−500
12−30
28−30
23−30
20−30
17−30
15−30
14−30
12−30
12−30
12−30
12−28
12−26
12−25
12−24
12−23
12−21
12−30
N/A
140−150
140−180
140−210
140−240
140−270
140−300
140−330
144−360
192−480
216−500
228−500
240−500
252−500
264−500
288−500
x6
x7
x8
x9
x10
x11
x12
x16
x18
x19
x20
x21
x22
x24
75
†
‡
Use external pullup resistors on the CLKMODE pins (CLKMODE1 and CLKMODE0) to set the C6413/C6410 device to one of the valid PLL
multiply clock modes (x5, x6, x7, x8, x9, x10, x11, x12, x16, x18, x19, x20, x21, x22, or x24). With internal pulldown resistors on the CLKMODE
pins (CLKMODE3, CLKMODE2, CLKMODE1, CLKMODE0), the default clock mode is x1 (bypass).
Under some operating conditions, the maximum PLL lock time may vary by as much as 150% from the specified typical value. For example, if
the typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs.
73
April 2004 − Revised May 2005
SPRS247E
Clock PLL and Oscillator
Table 4−2. TMS320C6410 PLL Multiply Factor Options, Clock Frequency Ranges,
†
and Typical Lock Time for −400 Devices
GTS and ZTS PACKAGES − 23 x 23 mm BGA
CPU CLOCK
CLKIN
CPU CLOCK
FREQUENCY
RANGE
OSCIN
RANGE
(MHz)
TYPICAL
CLKMODE
(PLL MULTIPLY FACTORS)
FREQUENCY
RANGE
CLKMODE[3:0]
RANGE
(MHz)
LOCK TIME
‡
(µs)
(MHz)
(MHz)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Bypass (x1)
x5
12−100
28−80
23−67
20−57
17−50
15−44
14−40
12−36
12−33
12−25
12−22
12−21
12−20
12−19
12−18
12−17
12−100
140−400
140−400
140−400
140−400
140−400
140−400
140−400
144−400
192−400
216−400
228−400
240−400
252−400
264−400
288−400
12−30
28−30
23−30
20−30
17−30
15−30
14−30
12−30
12−30
12−25
12−22
12−21
12−20
12−19
12−18
12−17
12−30
N/A
140−150
140−180
140−210
140−240
140−270
140−300
140−330
144−360
192−400
216−400
228−400
240−400
252−400
264−400
288−400
x6
x7
x8
x9
x10
x11
x12
x16
x18
x19
x20
x21
x22
x24
75
†
‡
Use external pullup resistors on the CLKMODE pins (CLKMODE1 and CLKMODE0) to set the C6413/C6410 device to one of the valid PLL
multiply clock modes (x5, x6, x7, x8, x9, x10, x11, x12, x16, x18, x19, x20, x21, x22, or x24). With internal pulldown resistors on the CLKMODE
pins (CLKMODE3, CLKMODE2, CLKMODE1, CLKMODE0), the default clock mode is x1 (bypass).
Under some operating conditions, the maximum PLL lock time may vary by as much as 150% from the specified typical value. For example, if
the typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs.
For the lowest jitter on the oscillator circuit, it is recommended that a pair of 470-pF capacitors be connected
between isolated (not directly connected to the board supply) OSCV and OSCV pins. This helps to cancel
DD
SS
out switching noise from other circuits on the DSP device.
Table 4−3 shows a recommended crystal and tank circuit values for the C6413/C6410 PLL circuitry.
Table 4−3. Crystal and Tank Circuit Recommendations
Components
RECOMMENDED PART NUMBERS or VALUES
MANUFACTURER
1AS245766AHA (SMD-49)
24.576 MHz
1AF245766AAA (AT-49)
1AS225796AG (SMD-49)
1AF225796A (AT-49)
1 MΩ
Crystal
KDS™ Diashinku Corp.
22.5792 MHz
R
R
—
—
B
S
0 Ω
C7
C8
8 pF
—
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Host-Port Interface (HPI) Peripheral
4.2
Host-Port Interface (HPI) Peripheral
The TMS320C6413/C6410 device includes a user-configurable 16-bit or 32-bit Host-port interface
(HPI16/HPI32). On the C6413/C6410 device the HPI peripheral pins are muxed with the McASP1 and GP0
peripheral pins. By default, the HPI peripheral pin functions are enabled. For more detailed information on the
C6413/C6410 device pin muxing, see the Device Configurations section of this data sheet.
The HPI peripheral can be disabled or enabled at reset through the HPI enable function of the TOUT0/HPI_EN
pin. The HPI is enabled when the TOUT0/HPI_EN pin is sampled low at reset and it is disabled if the pin is
sample high at reset. The TOUT0/HPI_EN pin has an internal pulldown that enables the HPI by default.
However, the HPI can be disabled via an external pullup resistor or by having an external device such as an
FPGA/CPLD drive that pin high at reset. In the latter case, the external device should ensure it has stopped
driving this pin to avoid contention. The HPI enable function can only be set a reset and cannot be changed
via software.
The HD5 pin controls the HPI_WIDTH, allowing the user to configure the HPI as a 16-bit or 32-bit peripheral.
For more details on HPI peripheral configuration and the associated pins, see the Device Configurations
section of this data sheet.
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Multichannel Audio Serial Port (McASP) Peripheral
4.3
Multichannel Audio Serial Port (McASP) Peripheral
The TMS320C6413/C6410 device includes two multichannel audio serial port (McASP) interface peripheral
(McASP0 and McASP1). On the C6413/C6410 device the McASP1 peripheral pins are muxed with the HPI
peripheral pins. By default, the HPI peripheral pin functions are enabled. For the C6413/C6410 device
McASP1 is a standalone peripheral, not muxed. For more detailed information on the C6413/C6410 device
pin muxing, see the Device Configurations section of this data sheet.
The McASP is a serial port optimized for the needs of multichannel audio applications.
The McASP consists of a transmit and receive section. These sections can operate completely independently
with different data formats, separate master clocks, bit clocks, and frame syncs or alternatively, the transmit
and receive sections may be synchronized. The McASP module also includes a pool of 16 shift registers that
may be configured to operate as either transmit data, receive data, or general-purpose I/O (GPIO).
The transmit section of the McASP can transmit data in either a time-division-multiplexed (TDM) synchronous
serial format or in a digital audio interface (DIT) format where the bit stream is encoded for S/PDIF, AES-3,
IEC-60958, CP-430 transmission. The receive section of the McASP supports the TDM synchronous serial
format.
The McASP can support one transmit data format (either a TDM format or DIT format) and one receive format
at a time. All transmit shift registers use the same format and all receive shift registers use the same format.
However, the transmit and receive formats need not be the same.
Both the transmit and receive sections of the McASP also support burst mode which is useful for non-audio
data (for example, passing control information between two DSPs).
The McASP peripheral has additional capability for flexible clock generation, and error detection/handling, as
well as error management.
For more detailed information on and the functionality of the McASP peripheral, see the TMS320C6000 DSP
Multichannel Audio Serial Port (McASP) Reference Guide (literature number SPRU041).
4.3.1
McASP Block Diagram
Figure 4−2 illustrates the major blocks along with external signals of the TMS320C6413/C6410 McASP
peripheral; and shows the 6 serial data [AXRx] pins. The McASP also includes full general-purpose I/O (GPIO)
control, so any pins not needed for serial transfers can be used for general-purpose I/O.
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Multichannel Audio Serial Port (McASP) Peripheral
McASPx
Transmit
Frame Sync
Generator
DIT
RAM
AFSXx
Transmit
Clock Check
(High-
Transmit
Clock
Generator
AHCLKXx
ACLKXx
Frequency)
AMUTEx
AMUTEINx
Error
Detect
Receive
Clock Check
(High-
Receive
Clock
Generator
AHCLKRx
ACLKRx
†
Frequency)
Transmit
Data
Formatter
Receive
Frame Sync
Generator
†
AFSRx
Serializer 0
AXRx[0]
AXRx[1]
AXRx[2]
AXRx[3]
AXRx[4]
AXRx[5]
Serializer 1
Serializer 2
Serializer 3
Serializer 4
Serializer 5
Serializer 6
Serializer 7
Receive
Data
Formatter
GPIO
Control
†
‡
On the C6413/C6410 device, the McASP1 peripheral has some additional pins muxed with AFSR1 and with ACLKR1 pins (i.e.,
AFSR1[1], AFSR1[2], AFSR1[3] and ACLKR1[1]. ACLKR1[2], ACLKR1[3], respectively).
On the C6413/C6410 device, the McASP0 peripheral is standalone, not muxed and the McASP1 peripheral is muxed with the HPI
peripheral. For more detailed information on multiplexed pins, see the Device Configurations section of this data sheet.
‡
Figure 4−2. McASP0 and McASP1 Configuration
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I2C
4.4
I2C
The TMS320C6413/C6410 device includes two I2C peripheral modules (I2C0 and I2C1). NOTE: when using
the I2C modules (any mode), ensure there are external pullup resistors on the SDAx and SCLx pins.
One of the I2C modules on the TMS320C6413/C6410 may be used by the DSP to control local peripherals
ICs (DACs, ADCs, etc.) while the other module may be used to communicate with other controllers in a system
or to implement a user interface.
The I2Cx port supports:
•
•
•
•
•
•
•
•
Compatible with Philips I2C Specification Revision 2.1 (January 2000)
Fast Mode up to 400 Kbps (no fail-safe I/O buffers)
Noise Filter to remove noise 50 ns or less
7- and 10-Bit Device Addressing Modes
Multi-Master (Transmit/Receive) and Slave (Transmit/Receive) Functionality
Events: DMA, Interrupt, or Polling
Slew-Rate Limited Open-Drain Output Buffers
General-purpose input and output (GPIO) functionality for I2C pins
For more detailed information on C6413/6410 I2C additional features, such as GPIO capability, etc., see the
TMS320C6000 DSP Inter−Integrated Circuit (I2C) Module Reference Guide (literature number SPRU175)
and the TMS320C6410/C6413/C6418 DSP Inter−Integrated Circuit (I2C) Module Reference Guide (literature
number SPRZ221) addendum.
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General-Purpose Input/Output (GPIO)
Figure 4−3 is a block diagram of the I2C0 and I2C1 modules.
I2Cx Module
Peripheral Clock
(CPU/4)
Clock
Prescale
I2CPSCx
Control
Own
SCL
I2COARx
Address
Noise
Filter
I2C Clock
Bit Clock
Generator
Slave
I2CSARx
Address
GPIO Control
I2CCLKHx
I2CCLKLx
I2CMDRx
I2CCNTx
Mode
Pin
Function
I2CPFUNCx
Data
Count
Pin
Direction
I2CPDIRx
Extended
Mode
I2CEMDRx
Transmit
I2CXSRx
Pin Data
In
I2CPDINx
Transmit
Shift
Pin Data
Out
I2CPDOUTx
I2CPDSETx
I2CPDCLRx
Transmit
Buffer
Interrupt/DMA
I2CIERx
I2CDXRx
Pin Data
Set
Interrupt
Enable
Pin Data
Clear
Receive
Interrupt
Status
I2CSTRx
Receive
Buffer
I2CDRRx
SDA
Interrupt
Source
Noise
Filter
I2CISRCx
I2C Data
Receive
Shift
I2CRSRx
NOTE A: Shading denotes control/status registers.
Figure 4−3. I2Cx Module Block Diagram
4.5
General-Purpose Input/Output (GPIO)
On the C6413/C6410 device the GPIO peripheral pins GP0[15:9] are muxed with the HPI peripheral pins
HD[15:9], respectively. By default, the HPI peripheral pin functions are enabled [TOUT0/HPI_EN pin internall
pulled low]. For more detailed information on device/peripheral configuration and the C6413/C6410 device
pin muxing, see the Device Configurations section of this data sheet.
To use the GP0[15:0] software-configurable GPIO pins, the GPxEN bits in the GP Enable (GPEN) Register
and the GPxDIR bits in the GP Direction (GPDIR) Register must be properly configured.
GPxEN =
GPxDIR =
GPxDIR =
1
0
1
GP[x] pin is enabled
GP[x] pin is an input
GP[x] pin is an output
where “x” represents one of the 15 through 0 GPIO pins
Figure 4−4 shows the GPIO enable bits in the GPEN register for the C6413/C6410 device. To use any of the
GPx pins as general-purpose input/output functions, the corresponding GPxEN bit must be set to “1”
(enabled). Default values are device-specific, so refer to Figure 4−4 for the C6413/C6410 default
configuration.
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General-Purpose Input/Output (GPIO)
31
24 23
Reserved
R-0
16
15
GP15 GP14 GP13 GP12 GP11 GP10
EN EN EN EN EN EN
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GP9
EN
GP8
EN
GP7
EN
GP6
EN
GP5
EN
GP4
EN
GP3
EN
GP2
EN
GP1
EN
GP0
EN
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-1
Legend: R/W = Readable/Writeable; -n = value after reset, -x = undefined value after reset
Figure 4−4. GPIO Enable Register (GPEN) [Hex Address: 01B0 0000]
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General-Purpose Input/Output (GPIO)
Figure 4−5 shows the GPIO direction bits in the GPDIR register. This register determines if a given GPIO pin
is an input or an output providing the corresponding GPxEN bit is enabled (set to “1”) in the GPEN register.
By default, all the GPIO pins are configured as input pins.
31
24 23
Reserved
R-0
16
15
14
13
12
11
9
8
6
4
3
1
0
10
7
5
2
GP15 GP14 GP13 GP12 GP11 GP10
DIR DIR DIR DIR DIR DIR
GP9
DIR
GP8
DIR
GP7
DIR
GP6
DIR
GP5
DIR
GP4
DIR
GP3
DIR
GP2
DIR
GP1
DIR
GP0
DIR
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
Legend: R/W = Readable/Writeable; -n = value after reset, -x = undefined value after reset
Figure 4−5. GPIO Direction Register (GPDIR) [Hex Address: 01B0 0004]
For more detailed information on general-purpose inputs/outputs (GPIOs), see the TMS320C6000 DSP
General-Purpose Input/Output (GPIO) Reference Guide (literature number SPRU584).
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Power-Down Modes Logic
4.6 Power-Down Modes Logic
Figure 4−6 shows the power-down mode logic on the C6413/C6410.
CLKOUT4
CLKOUT6
Internal Clock Tree
Clock
Distribution
and Dividers
PD1
PD2
IFR
Power-
Clock
PLL
Internal
Peripherals
IER
Down
Logic
CSR
PWRD
CPU
PD3
TMS320C6413/C6410
CLKIN
RESET
†
External input clocks, with the exception of CLKIN, are not gated by the power-down mode logic.
†
Figure 4−6. Power-Down Mode Logic
Note: to further save power, the PERCFG register can be used to disable unused peripherals. For more
detailed information on disabling peripherals using the PERCFG register, see the Device Configurations
section of this data sheet.
4.6.1
Triggering, Wake-up, and Effects
The power-down modes and their wake-up methods are programmed by setting the PWRD field (bits 15−10)
of the control status register (CSR). The PWRD field of the CSR is shown in Figure 4−7 and described in
Table 4−4. When writing to the CSR, all bits of the PWRD field should be set at the same time. Logic 0 should
be used when writing to the reserved bit (bit 15) of the PWRD field. The CSR is discussed in detail in the
TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189).
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Power-Down Modes Logic
31
16
15
14
13
12
11
10
9
8
0
Enable or
Non-Enabled
Interrupt Wake
Enabled
Interrupt Wake
Reserved
R/W-0
PD3
PD2
PD1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
7
Legend: R/W−x = Read/write reset value
NOTE: The shadowed bits are not part of the power-down logic discussion and therefore are not covered here. For information on these other
bit fields in the CSR register, see the TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189).
Figure 4−7. PWRD Field of the CSR Register
A delay of up to nine clock cycles may occur after the instruction that sets the PWRD bits in the CSR before the
PD mode takes effect. As best practice, NOPs should be padded after the PWRD bits are set in the CSR to
account for this delay.
If PD1 mode is terminated by a non-enabled interrupt, the program execution returns to the instruction where
PD1 took effect. If PD1 mode is terminated by an enabled interrupt, the interrupt service routine will be executed
first, then the program execution returns to the instruction where PD1 took effect. In the case with an enabled
interrupt, the GIE bit in the CSR and the NMIE bit in the interrupt enable register (IER) must also be set in order
for the interrupt service routine to execute; otherwise, execution returns to the instruction where PD1 took effect
upon PD1 mode termination by an enabled interrupt.
PD2 and PD3 modes can only be aborted by device reset. Table 4−4 summarizes all the power-down modes.
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Power-Supply Sequencing
Table 4−4. Characteristics of the Power-Down Modes
PRWD FIELD
(BITS 15−10)
POWER-DOWN
WAKE-UP METHOD
—
EFFECT ON CHIP’S OPERATION
MODE
000000
001001
No power-down
—
CPU halted (except for the interrupt logic)
PD1
Wake by an enabled interrupt
Power-down mode blocks the internal clock inputs at the
boundary of the CPU, preventing most of the CPU’s logic from
switching. During PD1, EDMA transactions can proceed between
peripherals and internal memory.
Wake by an enabled or
non-enabled interrupt
010001
011010
PD1
Output clock from PLL is halted, stopping the internal clock
structure from switching and resulting in the entire chip being
halted. All register and internal RAM contents are preserved. All
functional I/O “freeze” in the last state when the PLL clock is
turned off.
†
PD2
Wake by a device reset
Input clock to the PLL stops generating clocks. All register and
internal RAM contents are preserved. All functional I/O “freeze” in
the last state when the PLL clock is turned off. Following reset, the
PLL needs time to re-lock, just as it does following power-up.
Wake-up from PD3 takes longer than wake-up from PD2 because
the PLL needs to be re-locked, just as it does following power-up.
†
011100
PD3
Wake by a device reset
All others
Reserved
—
—
†
When entering PD2 and PD3, all functional I/O remains in the previous state. However, for peripherals which are asynchronous in nature or
peripherals with an external clock source, output signals may transition in response to stimulus on the inputs. Under these conditions,
peripherals will not operate according to specifications.
4.6.2
C64x Power-Down Mode with an Emulator
If user power-down modes are programmed, and an emulator is attached, the modes will be masked to allow
the emulator access to the system. This condition prevails until the emulator is reset or the cable is removed
from the header. If power measurements are to be performed when in a power-down mode, the emulator cable
should be removed.
When the DSP is in power-down mode PD2 or PD3, emulation logic will force any emulation execution
command (such as Step or Run) to spin in IDLE. For this reason, PC writes (such as loading code) will fail.
A DSP reset will be required to get the DSP out of PD2/PD3.
4.7
Power-Supply Sequencing
TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However,
systems should be designed to ensure that neither supply is powered up for extended periods of time
(>1 second) if the other supply is below the proper operating voltage.
4.7.1
Power-Supply Design Considerations
A dual-power supply with simultaneous sequencing can be used to eliminate the delay between core and I/O
power up. A Schottky diode can also be used to tie the core rail to the I/O rail (see Figure 4−8).
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Power-Supply Sequencing
I/O Supply
DV
CV
DD
Schottky
Diode
C6000
DSP
Core Supply
DD
V
SS
GND
Figure 4−8. Schottky Diode Diagram
Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize
inductance and resistance in the power delivery path. Additionally, when designing for high-performance
applications utilizing the C6000™ platform of DSPs, the PC board should include separate power planes for
core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors.
TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However,
systems should be designed to ensure that neither supply is powered up for extended periods of time if the
other supply is below the proper operating voltage.
4.8
Power-Supply Decoupling
In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as
possible close to the DSP. Assuming 0603 caps, the user should be able to fit a total of 60 caps, 30 for the
core supply and 30 for the I/O supply. These caps need to be close to the DSP power pins, no more than
1.25 cm maximum distance to be effective. Physically smaller caps, such as 0402, are better because of their
lower parasitic inductance. Proper capacitance values are also important. Small bypass caps (near 560 pF)
should be closest to the power pins. Medium bypass caps (220 nF or as large as can be obtained in a small
package) should be next closest. TI recommends no less than 8 small and 8 medium caps per supply (32 total)
be placed immediately next to the BGA vias, using the “interior” BGA space and at least the corners of the
“exterior”.
Eight larger caps (4 for each supply) can be placed further away for bulk decoupling. Large bulk caps (on the
order of 100 µF) should be furthest away (but still as close as possible). No less than 4 large caps per supply
(8 total) should be placed outside of the BGA.
Any cap selection needs to be evaluated from a yield/manufacturing point-of-view. As with the selection of any
component, verification of capacitor availability over the product’s production lifetime should be considered.
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Peripheral Power-Down Operation
4.9
Peripheral Power-Down Operation
The C6413/C6410 device can be powered down in two ways:
•
•
Power-down due to software configuration − relates to the default state of the peripheral configuration bits
in the PERCFG register.
Power-down during run-time via software configuration
On the C6413/C6410 device, the HPI, McASP1, and GP0 peripherals pin muxing is controlled (selected) at
the pin level during chip reset (e.g., HPI_EN and HD5 pins). If McASP1 pin muxing is selected, then the
MCASP1EN bit in the peripheral configuration register (PERCFG.8) must be configured properly to enable
the McASP1 peripheral.
The McASP1, McASP0, I2C1, and I2C0 peripheral functions are selected via the peripheral configuration
(PERCFG) register bits.
For more detailed information on the peripheral configuration pins and the PERCFG register bits, see the
Device Configurations section of this document.
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IEEE 1149.1 JTAG Compatibility Statement
4.10 IEEE 1149.1 JTAG Compatibility Statement
The TMS320C6413/C6410 DSP requires that both TRST and RESET be asserted upon power up to be
properly initialized. While RESET initializes the DSP core, TRST initializes the DSP’s emulation logic. Both
resets are required for proper operation.
Note: TRST is synchronous and must be clocked by TCLK; otherwise, BSCAN may not respond as expected
after TRST is asserted.
While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for the
DSP to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG port interface
and DSP’s emulation logic in the reset state. TRST only needs to be released when it is necessary to use a
JTAG controller to debug the DSP or exercise the DSP’s boundary scan functionality. RESET must be
released in order for boundary-scan JTAG to read the variant field of IDCODE correctly. Other boundary-scan
instructions work correctly independent of current state of RESET.
For maximum reliability, the TMS320C6413/C6410 DSP includes an internal pulldown (IPD) on the TRST pin
to ensure that TRST will always be asserted upon power up and the DSP’s internal emulation logic will always
be properly initialized. JTAG controllers from Texas Instruments actively drive TRST high. However, some
third-party JTAG controllers may not drive TRST high but expect the use of a pullup resistor on TRST. When
using this type of JTAG controller, assert TRST to intialize the DSP after powerup and externally drive TRST
high before attempting any emulation or boundary scan operations.
Following the release of RESET, the low-to-high transition of TRST must occur to latch the state of EMU1 and
EMU0. The EMU[1:0] pins configure the device for either Boundary Scan mode or Normal/Emulation mode.
For more detailed information, see the terminal functions section of this data sheet.
Note: The DESIGN_WARNING section of the TMS320C6413/C6410 BSDL file contains information and
constraints regarding proper device operation while in Boundary Scan Mode.
For more detailed information on the C6413/C6410 JTAG emulation, see the TMS320C6000 DSP Designing
for JTAG Emulation Reference Guide (literature number SPRU641).
4.11 EMIF Device Speed
The rated EMIF speed of these devices only applies to the SDRAM interface when in a system that meets the
following requirements:
•
•
•
•
1 chip-enable (CE) space (maximum of 2 chips) of SDRAM connected to EMIF
up to 1 CE space of buffers connected to EMIF
EMIF trace lengths between 1 and 3 inches
143-MHz SDRAM for 100-MHz operation
Other configurations may be possible, but timing analysis must be done to verify all AC timings are met.
Verification of AC timings is mandatory when using configurations other than those specified above. TI
recommends utilizing I/O buffer information specification (IBIS) to analyze all AC timings.
To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS Models
for Timing Analysis application report (literature number SPRA839).
To maintain signal integrity, serial termination resistors should be inserted into all EMIF output signal lines (see
the Terminal Functions table for the EMIF output signals).
For more detailed information on the C6413/C6410 EMIF peripheral, see the TMS320C6000 DSP External
Memory Interface (EMIF) Reference Guide (literature number SPRU266).
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Bootmode
4.12 Bootmode
The C6413/C6410 device resets using the active-low signal RESET. While RESET is low, the device is held
in reset and is initialized to the prescribed reset state. Refer to reset timing for reset timing characteristics and
states of device pins during reset. The release of RESET starts the processor running with the prescribed
device configuration and boot mode.
The C6413/C6410 has three types of boot modes:
•
Host boot
If host boot is selected, upon release of RESET, the CPU is internally “stalled” while the remainder of the
device is released. During this period, an external host can initialize the CPU’s memory space as
necessary through the host interface, including internal configuration registers, such as those that control
the EMIF or other peripherals. For the C6413/C6410 device, the HPI peripheral is used for host boot
providing the TOUT0/HPI_EN pin is low, enabling the HPI peripheral [default]. Once the host is finished
with all necessary initialization, it must set the DSPINT bit in the HPIC register to complete the boot
process. This transition causes the boot configuration logic to bring the CPU out of the “stalled” state. The
CPU then begins execution from address 0. The DSPINT condition is not latched by the CPU, because it
occurs while the CPU is still internally “stalled”. Also, DSPINT brings the CPU out of the “stalled” state only
if the host boot process is selected. All memory may be written to and read by the host. This allows for the
host to verify what it sends to the DSP if required. After the CPU is out of the “stalled” state, the CPU needs
to clear the DSPINT, otherwise, no more DSPINTs can be received.
•
•
EMIF boot (using default ROM timings)
Upon the release of RESET, the 1K-Byte ROM code located in the beginning of CE1 is copied to address 0
by the EDMA using the default ROM timings, while the CPU is internally “stalled”. The data should be
stored in the endian format that the system is using. In this case, the EMIF automatically assembles
consecutive 8-bit bytes to form the 32-bit instruction words to be copied. The transfer is automatically done
by the EDMA as a single-frame block transfer from the ROM to address 0. After completion of the block
transfer, the CPU is released from the “stalled” state and starts running from address 0.
No boot
With no boot, the CPU begins direct execution from the memory located at address 0. Note: operation is
undefined if invalid code is located at address 0.
4.13 Reset
A hardware reset (RESET) is required to place the DSP into a known good state out of power-up. The RESET
signal can be asserted (pulled low) prior to ramping the core and I/O voltages or after the core and I/O voltages
have reached their proper operating conditions. As a best practice, reset should be held low during power-up.
Prior to deasserting RESET (low-to-high transition), the core and I/O voltages should be at their proper
operating conditions and CLKIN should also be running at the correct frequency.
88
SPRS247E
April 2004 − Revised May 2005
Device Electrical Specifications
5
Device Electrical Specifications
5.1
Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise
Noted)†
Supply voltage ranges:
CV (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 1.8 V
DD
DV (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V
DD
Input voltage range:
Output voltage range:
V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V
I
V
O
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V
Operating case temperature range, T : (default) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0_C to 90_C
C
(A version) [GTSA and ZTSA] . . . . . . . . . . . . . . . . . −40_C to 105_C
Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65_C to 150_C
stg
Package Temperature Cycling:
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40_C to 125_C
Number of Cycles (GTS, GTSA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000
Number of Cycles (ZTS, ZTSA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to V
SS
.
5.2
Recommended Operating Conditions
MIN
1.14
3.14
0
NOM
1.2
3.3
0
MAX
1.26
3.46
0
UNIT
V
‡
CV
DV
Supply voltage, Core (-400, -500 device)
Supply voltage, I/O
DD
V
DD
V
V
V
V
Supply ground
V
SS
High-level input voltage
Low-level input voltage
2
V
IH
IL
0.8
V
§
§
Maximum voltage during overshoot/undershoot
Commercial temperature devices
−1.0
4.3
V
OS
0
90
_C
_C
(GTS and ZTS)
T
C
Operating case temperature
Extended temperature devices
(GTSA and ZTSA)
−40
105
‡
§
Future variants of the C64x DSPs may operate at voltages ranging from 0.9 V to 1.4 V to provide a range of system power/performance options.
TI highly recommends that users design-in a supply that can handle multiple voltages within this range (i.e., 1.2 V, 1.25 V, 1.3 V, 1.35 V, 1.4 V
with 3% tolerances) by implementing simple board changes such as reference resistor values or input pin configuration modifications. Examples
of such supplies include the PT4660, PT5500, PT5520, PT6440, and PT6930 series from Power Trends, a subsidiary of Texas Instruments. Not
incorporating a flexible supply may limit the system’s ability to easily adapt to future versions of C64x devices.
The absolute maximum ratings should not be exceeded for more than 30% of the cycle period.
89
April 2004 − Revised May 2005
SPRS247E
Device Electrical Specifications
5.3
Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating
Case Temperature (Unless Otherwise Noted)
†
PARAMETER
High-level output voltage
Low-level output voltage
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
V
V
DV = MIN,
I
I
= MAX
= MAX
2.4
OH
DD
OH
OL
DV = MIN,
0.4
10
V
OL
DD
V = V to DV no opposing internal
I
SS
DD
uA
uA
uA
resistor
V = V to DV opposing internal
I
SS
DD
50
100
150
I
I
Input current
‡
pullup resistor
V = V to DV opposing internal
I
SS
DD
−150
−100
−50
‡
pulldown resistor
EMIF, CLKOUT4, CLKOUT6, EMUx
Timer, TDO, GPIO, McBSP, HPI
EMIF, CLKOUT4, CLKOUT6, EMUx
Timer, TDO, GPIO, McBSP, HPI
SCL1, SDA1, SCL0, and SDA0
−16
−8
16
8
mA
mA
mA
mA
mA
uA
I
I
High-level output current
OH
Low-level output current
Off-state output current
OL
3
I
I
V
O
= DV or 0 V
10
OZ
DD
CV = 1.2 V, CPU clock = 500 MHz
568
465
140
132
mA
mA
mA
mA
pF
DD
§
Core supply current
CDD
CV = 1.2 V, CPU clock = 400 MHz
DD
DV = 3.3 V, CPU clock = 500 MHz
DD
§
I
I/O supply current
DDD
DV = 3.3 V, CPU clock = 400 MHz
DD
C
C
Input capacitance
Output capacitance
10
10
i
pF
o
†
‡
§
For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table.
Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor.
Measured with average activity (50% high/50% low power) at 25°C case temperature and 100-MHz EMIF for -500 and -400 speeds. This model
represents a device performing high-DSP-activity operations 50% of the time, and the remainder performing low-DSP-activity operations. The
high/low-DSP-activity models are defined as follows:
High-DSP-Activity Model:
CPU: 8 instructions/cycle with 2 LDDW instructions [L1 Data Memory: 128 bits/cycle via LDDW instructions;
L1 Program Memory: 256 bits/cycle; L2/EMIF EDMA: 50% writes, 50% reads to/from SDRAM (50% bit-switching)]
McBSP: 2 channels at E1 rate
Timers: 2 timers at maximum rate
Low-DSP-Activity Model:
CPU: 2 instructions/cycle with 1 LDH instruction [L1 Data Memory: 16 bits/cycle; L1 Program Memory: 256 bits per 4 cycles;
L2/EMIF EDMA: None]
McBSP: 2 channels at E1 rate
Timers: 2 timers at maximum rate
The actual current draw is highly application-dependent. For more details on core and I/O activity, refer to the TMS320C6410/13 Power
Consumption Summary application report (literature number SPRAA59).
5.4
Recommended Clock and Control Signal Transition Behavior
All clocks and control signals must transition between V and V (or between V and V ) in a monotonic
IH
IL
IL
IH
manner.
90
SPRS247E
April 2004 − Revised May 2005
Device Electrical Specifications
6
Parameter Information
Tester Pin Electronics
Data Sheet Timing Reference Point
42 Ω
3.5 nH
Output
Under
Test
Transmission Line
Z0 = 50 Ω
(see note)
Device Pin
(see note)
4.0 pF
1.85 pF
NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects
must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect.
The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from
the data sheet timings.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
Figure 6−1. Test Load Circuit for AC Timing Measurements
The load capacitance value stated is only for characterization and measurement of AC timing signals. This
load capacitance value does not indicate the maximum load the device is capable of driving.
6.1
Signal Transition Levels
All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels.
V
ref
= 1.5 V
Figure 6−2. Input and Output Voltage Reference Levels for AC Timing Measurements
All rise and fall transition timing parameters are referenced to V MAX and V MIN for input clocks, V MAX
IL
IH
OL
and V MIN for output clocks.
OH
V
ref
= V MIN (or V MIN)
IH OH
V
ref
= V MAX (or V MAX)
IL OL
Figure 6−3. Rise and Fall Transition Time Voltage Reference Levels
6.2
Signal Transition Rates
All timings are tested with an input edge rate of 4 Volts per nanosecond (4 V/ns).
91
April 2004 − Revised May 2005
SPRS247E
Device Electrical Specifications
6.3
Timing Parameters and Board Routing Analysis
The timing parameter values specified in this data sheet do not include delays by board routings. As a good
board design practice, such delays must always be taken into account. Timing values may be adjusted by
increasing/decreasing such delays. TI recommends utilizing the available I/O buffer information specification
(IBIS) models to analyze the timing characteristics correctly. To properly use IBIS models to attain accurate
timing analysis for a given system, see the Using IBIS Models for Timing Analysis application report (literature
number SPRA839). If needed, external logic hardware such as buffers may be used to compensate any timing
differences.
For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external device
and from the external device to the DSP. This round-trip delay tends to negatively impact the input setup time
margin, but also tends to improve the input hold time margins (see Table 6−1 and Figure 6−4).
Figure 6−4 represents a general transfer between the DSP and an external device. The figure also represents
board route delays and how they are perceived by the DSP and the external device.
Table 6−1. Board-Level Timing Example (see Figure 6−4)
NO.
1
DESCRIPTION
Clock route delay
2
Minimum DSP hold time
3
Minimum DSP setup time
External device hold time requirement
External device setup time requirement
Control signal route delay
External device hold time
4
5
6
7
8
External device access time
DSP hold time requirement
DSP setup time requirement
Data route delay
9
10
11
ECLKOUTx
(Output from DSP)
1
ECLKOUTx
(Input to External Device)
2
3
†
Control Signals
(Output from DSP)
4
5
6
Control Signals
(Input to External Device)
7
8
‡
Data Signals
(Output from External Device)
9
10
11
‡
Data Signals
(Input to DSP)
† Control signals include data for Writes.
‡ Data signals are generated during Reads from an external device.
Figure 6−4. Board-Level Input/Output Timings
92
SPRS247E
April 2004 − Revised May 2005
Peripheral Electrical Specifications
7
Peripheral Electrical Specifications
Input and Output Clocks
7.1
Table 7−1. Timing Requirements for External Crystal Oscillator Input (OSCIN and OSCOUT)
−400
−500
NO.
UNIT
MIN
MAX
1
f
Input oscillator frequency
12
30
MHz
OSC
†
The PLL multiplier factors (x5, x6, x7, x8, x9, x10, x11, x12, x16, x18, x19, x20, x21, x24) further limit the MIN and MAX values for CLKIN and
OSCIN. For more details on these limitations, see Table 4−1 and Table 4−2 of the Clock PLL and Oscillator section of this data sheet.
†‡§
Table 7−2. Timing Requirements for CLKIN
(see Figure 7−1)
−400
−500
NO.
UNIT
PLL MULT MODE
x1 (BYPASS)
MIN
MIN
MAX
MAX
†
†
1
2
3
4
5
t
t
t
t
t
Cycle time, CLKIN
10
83.3
10
83.3
ns
ns
ns
ns
ns
c(CLKIN)
w(CLKINH)
w(CLKINL)
t(CLKIN)
Pulse duration, CLKIN high
Pulse duration, CLKIN low
Transition time, CLKIN
Period jitter, CLKIN
0.45C
0.45C
0.45C
0.45C
5
1
0.02C
0.02C
J(CLKIN)
†
The PLL multiplier factors (x5, x6, x7, x8, x9, x10, x11, x12, x16, x18, x19, x20, x21, x24) further limit the MIN and MAX values for CLKIN and
OSCIN. For more details on these limitations, see Table 4−1 and Table 4−2 of the Clock PLL and Oscillator section of this data sheet.
‡
§
The reference points for the rise and fall transitions are measured at V MAX and V MIN.
IL
IH
C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns.
1
5
4
2
CLKIN
3
4
Figure 7−1. CLKIN Timing
93
April 2004 − Revised May 2005
SPRS247E
Input and Output Clocks
†‡§
Table 7−3. Switching Characteristics Over Recommended Operating Conditions for CLKOUT4
(see Figure 7−2)
−400
−500
NO.
PARAMETER
UNIT
MIN
MAX
1
2
3
4
t
t
t
t
Cycle time, CLKOUT4
4P − 0.7
2P − 0.7
2P − 0.7
4P + 0.7
2P + 0.7
2P + 0.7
1
ns
ns
ns
ns
c(CKO4)
w(CKO4H)
w(CKO4L)
t(CKO4)
Pulse duration, CLKOUT4 high
Pulse duration, CLKOUT4 low
Transition time, CLKOUT4
†
‡
§
The reference points for the rise and fall transitions are measured at V MAX and V MIN.
PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns.
P = 1/CPU clock frequency in nanoseconds (ns)
OL
OH
4
1
2
CLKOUT4
3
4
Figure 7−2. CLKOUT4 Timing
†‡§
Table 7−4. Switching Characteristics Over Recommended Operating Conditions for CLKOUT6
(see Figure 7−3)
−400
−500
NO.
PARAMETER
UNIT
MIN
MAX
1
2
3
4
t
t
t
t
Cycle time, CLKOUT6
6P − 0.7
3P − 0.7
3P − 0.7
6P + 0.7
3P + 0.7
3P + 0.7
1
ns
ns
ns
ns
c(CKO6)
w(CKO6H)
w(CKO6L)
t(CKO6)
Pulse duration, CLKOUT6 high
Pulse duration, CLKOUT6 low
Transition time, CLKOUT6
†
‡
§
The reference points for the rise and fall transitions are measured at V MAX and V MIN.
PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns.
P = 1/CPU clock frequency in nanoseconds (ns)
OL
OH
4
1
2
CLKOUT6
3
4
Figure 7−3. CLKOUT6 Timing
94
SPRS247E
April 2004 − Revised May 2005
Input and Output Clocks
†‡§
Table 7−5. Timing Requirements for AECLKIN for EMIFA
(see Figure 7−4)
−400
−500
NO.
UNIT
MIN
MAX
¶
1
2
3
4
5
t
t
t
t
t
Cycle time, AECLKIN
6
16P
ns
ns
ns
ns
ns
c(EKI)
Pulse duration, AECLKIN high
Pulse duration, AECLKIN low
Transition time, AECLKIN
Period jitter, AECLKIN
2.7
2.7
w(EKIH)
w(EKIL)
t(EKI)
3
0.02E
J(EKI)
†
‡
§
¶
P = 1/CPU clock frequency in ns. For example, when running parts at 500 MHz, use P = 2 ns.
The reference points for the rise and fall transitions are measured at V MAX and V MIN.
E = the EMIF input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA.
Minimum AECLKIN cycle times must be met, even when AECLKIN is generated by an internal clock source. Minimum AECLKIN times are based
on internal logic speed; the maximum useable speed of the EMIF may be lower due to AC timing requirements. 100-MHz operation is achievable
if the requirements of the EMIF Device Speed section are met.
IL
IH
1
5
4
2
AECLKIN
3
4
Figure 7−4. AECLKIN Timing for EMIFA
Table 7−6. Switching Characteristics Over Recommended Operating Conditions for AECLKOUT1 for the
§#||
EMIFA Module
(see Figure 7−5)
−400
−500
NO.
PARAMETER
UNIT
MIN
E − 0.7
MAX
1
2
3
4
5
6
t
t
t
t
t
t
Cycle time, AECLKOUT1
E + 0.7
ns
ns
ns
ns
ns
ns
c(EKO1)
Pulse duration, AECLKOUT1 high
Pulse duration, AECLKOUT1 low
Transition time, AECLKOUT1
EH − 0.7 EH + 0.7
EL − 0.7 EL + 0.7
1
w(EKO1H)
w(EKO1L)
t(EKO1)
Delay time, AECLKIN high to AECLKOUT1 high
Delay time, AECLKIN low to AECLKOUT1 low
1
1
8
8
d(EKIH-EKO1H)
d(EKIL-EKO1L)
§
#
||
E = the EMIF input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) period in ns.
The reference points for the rise and fall transitions are measured at V MAX and V MIN.
EH is the high period of E (EMIF input clock period) in ns and EL is the low period of E (EMIF input clock period) in ns for EMIFA.
OL
OH
AECLKIN
6
3
1
4
4
5
2
AECLKOUT1
Figure 7−5. AECLKOUT1 Timing for the EMIFA Module
95
April 2004 − Revised May 2005
SPRS247E
Input and Output Clocks
Table 7−7. Switching Characteristics Over Recommended Operating Conditions for AECLKOUT2 for the
†‡
EMIFA Module (see Figure 7−6)
−400
−500
NO.
PARAMETER
Cycle time, AECLKOUT2
UNIT
MIN
NE − 0.7
MAX
1
2
3
4
5
6
t
t
t
t
t
t
NE + 0.7
ns
ns
ns
ns
ns
ns
c(EKO2)
Pulse duration, AECLKOUT2 high
0.5NE − 0.7
0.5NE − 0.7
0.5NE + 0.7
w(EKO2H)
w(EKO2L)
Pulse duration, AECLKOUT2 low
0.5NE + 0.7
Transition time, AECLKOUT2
1
8
8
t(EKO2)
Delay time, ECLKIN high to AECLKOUT2 high
Delay time, ECLKIN high to AECLKOUT2 low
1
1
d(EKIH-EKO2H)
d(EKIH-EKO2L)
†
‡
The reference points for the rise and fall transitions are measured at V MAX and V MIN.
E = the EMIF input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA.
N = the EMIF input clock divider; N = 1, 2, or 4.
OL
OH
5
6
AECLKIN
3
1
4
4
2
AECLKOUT2
Figure 7−6. AECLKOUT2 Timing for the EMIFA Module
96
SPRS247E
April 2004 − Revised May 2005
Asynchronous Memory Timing
7.2
Asynchronous Memory Timing
†‡
Table 7−8. Timing Requirements for Asynchronous Memory Cycles for EMIFA Module
(see Figure 7−7 and Figure 7−8)
−400
−500
NO.
UNIT
MIN MAX
3
4
6
7
t
t
t
t
Setup time, AEDx valid before AARE high
Hold time, AEDx valid after AARE high
6.5
1
ns
ns
ns
ns
su(EDV-AREH)
h(AREH-EDV)
Setup time, AARDY valid before AECLKOUTx high
Hold time, AARDY valid after AECLKOUTx high
3
su(ARDY-EKO1H)
h(EKO1H-ARDY)
3
†
‡
To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. The ARDY signal is recognized in
the cycle for which the setup and hold time is met. The ARDY signal is only recognized two cycles before the end of the programmed strobe time
and while ARDY is low, the strobe time is extended cycle-by-cycle. When ARDY is recognized low, the end of the strobe time is two cycles after
ARDY is recognized high To use ARDY as an asynchronous input, the pulse width of the ARDY signal should be wide enough (e.g., pulse width
= 2E) to ensure setup and hold time is met.
RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are
programmed via the EMIF CE space control registers.
Table 7−9. Switching Characteristics Over Recommended Operating Conditions for Asynchronous
द
Memory Cycles for EMIFA Module
(see Figure 7−7 and Figure 7−8)
−400
−500
NO.
PARAMETER
UNIT
MIN
MAX
7
1
2
t
t
t
t
t
t
Output setup time, select signals valid to AARE low
Output hold time, AARE high to select signals invalid
Delay time, AECLKOUTx high to AARE valid
RS * E − 1.5
RH * E − 1.9
1
ns
ns
ns
ns
ns
ns
osu(SELV-AREL)
oh(AREH-SELIV)
d(EKO1H-AREV)
osu(SELV-AWEL)
oh(AWEH-SELIV)
d(EKO1H-AWEV)
5
8
Output setup time, select signals valid to AAWE low
Output hold time, AAWE high to select signals invalid
Delay time, AECLKOUTx high to AAWE valid
WS * E − 1.7
WH * E − 1.8
1.3
9
10
7.1
‡
RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are
programmed via the EMIF CE space control registers.
E = ECLKOUT1 period in ns for EMIFA
§
¶
Select signals for EMIFA include: ACEx, ABE[3.:0], AEA[22:3], AAOE; and for EMIFA writes, include AED[31:0].
97
April 2004 − Revised May 2005
SPRS247E
Asynchronous Memory Timing
Setup = 2
Strobe = 3
Not Ready
Hold = 2
AECLKOUTx
ACEx
2
2
1
1
1
ABE[3:0]
BE
2
AEA[22:3]
Address
3
4
2
AED[31:0]
1
5
Read Data
†
AAOE/ASDRAS/ASOE
5
†
AARE/ASDCAS/ASADS/ASRE
†
AAWE/ASDWE/ASWE
7
7
6
6
AARDY
†
AOE/SDRAS/SOE, ARE/SDCAS/SADS/SRE, and AWE/SDWE/SWE operate as AOE (identified under select signals), ARE, and AWE,
respectively, during asynchronous memory accesses.
Figure 7−7. Asynchronous Memory Read Timing for EMIFA
98
SPRS247E
April 2004 − Revised May 2005
Asynchronous Memory Timing
Setup = 2
Hold = 2
Strobe = 3
Not Ready
AECLKOUTx
ACEx
9
9
8
8
8
8
ABE[3:0]
BE
9
9
AEA[22:3]
AED[31:0]
Address
Write Data
†
AAOE/ASDRAS/ASOE
†
AARE/ASDCAS/ASADS/ASRE
10
10
†
AAWE/ASDWE/ASWE
7
7
6
6
AARDY
†
AOE/SDRAS/SOE, ARE/SDCAS/SADS/SRE, and AWE/SDWE/SWE operate as AOE (identified under select signals), ARE, and AWE,
respectively, during asynchronous memory accesses.
Figure 7−8. Asynchronous Memory Write Timing for EMIFA
99
April 2004 − Revised May 2005
SPRS247E
Programmable Synchronous Interface Timing
7.3
Programmable Synchronous Interface Timing
Table 7−10. Timing Requirements for Programmable Synchronous Interface Cycles for EMIFA Module
(see Figure 7−9)
−400
−500
NO.
UNIT
MIN
3.1
MAX
6
7
t
t
Setup time, read AEDx valid before AECLKOUTx high
Hold time, read AEDx valid after AECLKOUTx high
ns
ns
su(EDV-EKOxH)
1.5
h(EKOxH-EDV)
Table 7−11. Switching Characteristics Over Recommended Operating Conditions for Programmable
†
Synchronous Interface Cycles for EMIFA Module (see Figure 7−9−Figure 7−11)
−400
−500
NO.
PARAMETER
UNIT
MIN
MAX
6.4
1
2
t
t
t
t
t
t
t
t
t
t
Delay time, AECLKOUTx high to ACEx valid
Delay time, AECLKOUTx high to ABEx valid
Delay time, AECLKOUTx high to ABEx invalid
Delay time, AECLKOUTx high to AEAx valid
Delay time, AECLKOUTx high to AEAx invalid
Delay time, AECLKOUTx high to ASADS/ASRE valid
Delay time, AECLKOUTx high to, ASOE valid
Delay time, AECLKOUTx high to AEDx valid
Delay time, AECLKOUTx high to AEDx invalid
Delay time, AECLKOUTx high to ASWE valid
1.3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
d(EKOxH-CEV)
d(EKOxH-BEV)
d(EKOxH-BEIV)
d(EKOxH-EAV)
d(EKOxH-EAIV)
d(EKOxH-ADSV)
d(EKOxH-OEV)
d(EKOxH-EDV)
d(EKOxH-EDIV)
d(EKOxH-WEV)
6.4
3
1.3
4
6.4
5
1.3
1.3
1.3
8
6.4
6.4
6.4
9
10
11
12
1.3
1.3
6.4
†
The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC):
−
−
−
Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency
Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency
ACEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has been issued
(CEEXT = 0). For synchronous FIFO interface with glue, ACEx is active when ASOE is active (CEEXT = 1).
Function of ASADS/ASRE (RENEN): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect cycles
(RENEN = 0). For FIFO interface, ASADS/ASRE acts as ASRE with NO deselect cycles (RENEN = 1).
−
−
Synchronization clock (SNCCLK): Synchronized to AECLKOUT1 or AECLKOUT2
100
SPRS247E
April 2004 − Revised May 2005
Programmable Synchronous Interface Timing
READ latency = 2
AECLKOUTx
1
2
1
ACEx
3
ABE[3:0]
BE1
BE2
BE3
BE4
4
5
AEA[22:3]
AED[31:0]
EA1
EA2
EA3
EA4
6
7
Q1
Q2
Q3
Q4
8
9
8
AARE/ASDCAS/ASADS/
§
ASRE
9
§
AAOE/ASDRAS/ASOE
§
AAWE/ASDWE/ASWE
†
‡
The read latency and the length of CEx assertion are programmable via the SYNCRL and CEEXT fields, respectively, in the EMIFA CE Space
Secondary Control register (CExSEC). In this figure, SYNCRL = 2 and CEEXT = 0.
The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC):
−
−
−
Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency
Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency
ACEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has been issued
(CEEXT = 0). For synchronous FIFO interface with glue, ACEx is active when ASOE is active (CEEXT = 1).
Function of ASADS/ASRE (RENEN): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect cycles
(RENEN = 0). For FIFO interface, ASADS/ASRE acts as ASRE with NO deselect cycles (RENEN = 1).
Synchronization clock (SNCCLK): Synchronized to AECLKOUT1 or AECLKOUT2
−
−
§
AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and AAWE/ASDWE/ASWE operate as ASADS/ASRE, ASOE, and ASWE,
respectively, during programmable synchronous interface accesses.
Figure 7−9. Programmable Synchronous Interface Read Timing for EMIFA
†‡
(With Read Latency = 2)
101
April 2004 − Revised May 2005
SPRS247E
Programmable Synchronous Interface Timing
AECLKOUTx
1
2
1
3
ACEx
ABE[3:0]
AEA[22:3]
BE1
BE2
EA2
Q2
BE3
EA3
Q3
BE4
EA4
Q4
5
4
EA1
10
Q1
10
11
AED[31:0]
8
8
§
AARE/ASDCAS/ASADS/ASRE
§
AAOE/ASDRAS/ASOE
12
12
§
AAWE/ASDWE/ASWE
†
‡
The write latency and the length of ACEx assertion are programmable via the SYNCWL and CEEXT fields, respectively, in the EMIFA CE Space
Secondary Control register (CExSEC). In this figure, SYNCWL = 0 and CEEXT = 0.
The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC):
−
−
−
Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency
Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency
ACEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has been issued
(CEEXT = 0). For synchronous FIFO interface with glue, ACEx is active when ASOE is active (CEEXT = 1).
Function of ASADS/ASRE (RENEN): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect cycles
(RENEN = 0). For FIFO interface, ASADS/ASRE acts as ASRE with NO deselect cycles (RENEN = 1).
Synchronization clock (SNCCLK): Synchronized to AECLKOUT1 or AECLKOUT2
−
−
§
AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and AAWE/ASDWE/ASWE operate as ASADS/ASRE, ASOE, and ASWE,
respectively, during programmable synchronous interface accesses.
Figure 7−10. Programmable Synchronous Interface Write Timing for EMIFA
†‡§
(With Write Latency = 0)
102
SPRS247E
April 2004 − Revised May 2005
Programmable Synchronous Interface Timing
Write
Latency =
‡
1
AECLKOUTx
1
1
3
ACEx
2
ABE[3:0]
BE1
BE2
BE3
BE4
EA4
Q3
5
4
AEA[22:3]
EA1
10
EA2
10
EA3
Q2
11
8
AED[31:0]
Q1
Q4
8
AARE/ASDCAS/ASADS/
§
ASRE
§
AAOE/ASDRAS/ASOE
12
12
§
AAWE/ASDWE/ASWE
†
‡
The write latency and the length of ACEx assertion are programmable via the SYNCWL and CEEXT fields, respectively, in the EMIFA CE Space
Secondary Control register (CExSEC). In this figure, SYNCWL = 1 and CEEXT = 0.
The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC):
−
−
−
Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency
Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency
ACEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has been issued
(CEEXT = 0). For synchronous FIFO interface with glue, ACEx is active when ASOE is active (CEEXT = 1).
Function of ASADS/ASRE (RENEN): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect cycles
(RENEN = 0). For FIFO interface, ASADS/ASRE acts as ASRE with NO deselect cycles (RENEN = 1).
Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2
−
−
§
AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and AAWE/ASDWE/ASWE operate as ASADS/ASRE, ASOE, and ASWE,
respectively, during programmable synchronous interface accesses.
Figure 7−11. Programmable Synchronous Interface Write Timing for EMIFA
†‡
(With Write Latency = 1)
103
April 2004 − Revised May 2005
SPRS247E
Synchronous DRAM Timing
7.4
Synchronous DRAM Timing
Table 7−12. Timing Requirements for Synchronous DRAM Cycles for EMIFA Module (see Figure 7−12)
−400
−500
NO.
UNIT
MIN MAX
6
7
t
t
Setup time, read AEDx valid before AECLKOUTx high
Hold time, read AEDx valid after AECLKOUTx high
2.1
2.5
ns
ns
su(EDV-EKO1H)
h(EKO1H-EDV)
Table 7−13. Switching Characteristics Over Recommended Operating Conditions for Synchronous DRAM
Cycles for EMIFA Module (see Figure 7−12−Figure 7−19)
−400
−500
NO.
PARAMETER
UNIT
MIN
MAX
6.4
1
2
t
t
t
t
t
t
t
t
t
t
t
t
Delay time, AECLKOUTx high to ACEx valid
Delay time, AECLKOUTx high to ABEx valid
Delay time, AECLKOUTx high to ABEx invalid
Delay time, AECLKOUTx high to AEAx valid
Delay time, AECLKOUTx high to AEAx invalid
Delay time, AECLKOUTx high to ASDCAS valid
Delay time, AECLKOUTx high to AEDx valid
Delay time, AECLKOUTx high to AEDx invalid
Delay time, AECLKOUTx high to ASDWE valid
Delay time, AECLKOUTx high to ASDRAS valid
Delay time, AECLKOUTx high to ASDCKE valid
Delay time, AECLKOUTx high to PDT valid
1.3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
d(EKO1H-CEV)
d(EKO1H-BEV)
d(EKO1H-BEIV)
d(EKO1H-EAV)
d(EKO1H-EAIV)
d(EKO1H-CASV)
d(EKO1H-EDV)
d(EKO1H-EDIV)
d(EKO1H-WEV)
d(EKO1H-RAS)
d(EKO1H-ACKEV)
6.4
3
1.3
4
6.4
5
1.3
1.3
8
6.4
6.4
9
10
11
12
13
14
1.3
1.3
1.3
1.3
1.3
6.4
6.4
6.4
6.4
d(EKO1H-PDTV)
104
SPRS247E
April 2004 − Revised May 2005
Synchronous DRAM Timing
READ
AECLKOUTx
ACEx
1
4
1
2
3
ABE[3:0]
BE1
BE2
BE3
BE4
5
5
5
Bank
AEA[22:14]
AEA[12:3]
4
Column
4
AEA13
6
7
D2
AED[31:0]
D1
D3
D4
†
AAOE/ASDRAS/ASOE
8
8
AARE/ASDCAS/ASADS/
†
ASRE
†
AAWE/ASDWE/ASWE
14
14
‡
PDT
†
‡
AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS,
respectively, during SDRAM accesses.
PDT signal is only asserted when the EDMA is in PDT mode (set the PDTS bit to 1 in the EDMA options parameter RAM). For PDT read, data
is not latched into EMIF. The PDTRL field in the PDT control register (PDTCTL) configures the latency of the PDT signal with respect to the data
phase of a read transaction. The latency of the PDT signal for a read can be programmed to 0, 1, 2, or 3 by setting PDTRL to 00, 01, 10, or 11,
respectively. PDTRL equals 00 (zero latency) in Figure 7−12.
Figure 7−12. SDRAM Read Command (CAS Latency 3) for EMIFA
105
April 2004 − Revised May 2005
SPRS247E
Synchronous DRAM Timing
WRITE
AECLKOUTx
ACEx
1
2
4
4
4
9
2
4
5
5
5
9
3
ABE[3:0]
BE1
BE2
BE3
BE4
Bank
AEA[22:14]
Column
AEA[12:3]
AEA13
10
AED[31:0]
D1
D2
D3
D4
†
AAOE/ASDRAS/ASOE
8
8
AARE/ASDCAS/ASADS/
†
ASRE
11
14
11
†
AAWE/ASDWE/ASWE
14
‡
PDT
†
AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as AsDCAS, ASDWE, and ASDRAS, respectively,
during SDRAM accesses.
PDT signal is only asserted when the EDMA is in PDT mode (set the PDTD bit to 1 in the EDMA options parameter RAM). For PDT write, data
is not driven (in High-Z). The PDTWL field in the PDT control register (PDTCTL) configures the latency of the PDT signal with respect to the data
phase of a write transaction. The latency of the PDT signal for a write transaction can be programmed to 0, 1, 2, or 3 by setting PDTWL to 00,
01, 10, or 11, respectively. PDTWL equals 00 (zero latency) in Figure 7−13.
‡
Figure 7−13. SDRAM Write Command for EMIFA
106
SPRS247E
April 2004 − Revised May 2005
Synchronous DRAM Timing
ACTV
AECLKOUTx
1
4
1
ACEx
ABE[3:0]
5
5
5
Bank Activate
AEA[22:14]
AEA[12:3]
4
Row Address
4
Row Address
AEA13
AED[31:0]
12
12
†
AAOE/ASDRAS/ASOE
AARE/ASDCAS/ASADS/
†
ASRE
†
AAWE/ASDWE/ASWE
†
AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS,
respectively, during SDRAM accesses.
Figure 7−14. SDRAM ACTV Command for EMIFA
DCAB
AECLKOUTx
1
1
ACEx
ABE[3:0]
AEA[22:14, 12:3]
4
12
11
5
12
11
AEA13
AED[31:0]
†
AAOE/ASDRAS/ASOE
AARE/ASDCAS/ASADS/
†
ASRE
†
AAWE/ASDWE/ASWE
†
AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS,
respectively, during SDRAM accesses.
Figure 7−15. SDRAM DCAB Command for EMIFA
107
April 2004 − Revised May 2005
SPRS247E
Synchronous DRAM Timing
DEAC
AECLKOUTx
1
1
ACEx
ABE[7:0]
4
5
AEA[22:14]
AEA[12:3]
Bank
4
5
AEA13
AED[31:0]
12
11
12
11
†
AAOE/ASDRAS/ASOE
AARE/ASDCAS/ASADS/
†
ASRE
†
AAWE/ASDWE/ASWE
†
AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS,
respectively, during SDRAM accesses.
Figure 7−16. SDRAM DEAC Command for EMIFA
REFR
AECLKOUTx
1
1
ACEx
ABE[3:0]
AEA[22:14, 12:3]
AEA13
AED[31:0]]
12
8
12
8
†
AAOE/ASDRAS/ASOE
AARE/ASDCAS/ASADS/
†
ASRE
†
AAWE/ASDWE/ASWE
†
AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS,
respectively, during SDRAM accesses.
Figure 7−17. SDRAM REFR Command for EMIFA
108
SPRS247E
April 2004 − Revised May 2005
Synchronous DRAM Timing
MRS
AECLKOUTx
1
4
1
5
ACEx
ABE[3:0]
AEA[22:3]
AED[31:0]
MRS value
12
8
12
8
AAOE/ASDRAS/
†
ASOE
AARE/ASDCAS/ASADS/
†
ASRE
11
11
†
AAWE/ASDWE/ASWE
†
AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS,
respectively, during SDRAM accesses.
Figure 7−18. SDRAM MRS Command for EMIFA
≥ TRAS cycles
End Self-Refresh
Self Refresh
AECLKOUTx
ACEx
ABE[3:0]
AEA[22:14, 12:3]
AEA13
AED[31:0]
†
AAOE/ASDRAS/ASOE
†
AARE/ASDCAS/ASADS/ASRE
†
AAWE/ASDWE/ASWE
13
13
ASDCKE
†
AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS,
respectively, during SDRAM accesses.
Figure 7−19. SDRAM Self-Refresh Timing for EMIFA
109
April 2004 − Revised May 2005
SPRS247E
HOLD/HOLDA Timing
7.5
HOLD/HOLDA Timing
†
Table 7−14. Timing Requirements for the HOLD/HOLDA Cycles for EMIFA Module (see Figure 7−20)
−400
−500
NO.
UNIT
ns
MIN MAX
3
t
Hold time, HOLD low after HOLDA low
E
h(HOLDAL-HOLDL)
†
E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA.
Table 7−15. Switching Characteristics Over Recommended Operating Conditions for the HOLD/HOLDA
†‡§
Cycles for EMIFA Module
(see Figure 7−20)
−400
−500
NO.
PARAMETER
UNIT
MIN
MAX
¶
1
2
4
5
6
7
t
t
t
t
t
t
Delay time, HOLD low to EMIFA Bus high impedance
Delay time, EMIF Bus high impedance to HOLDA low
Delay time, HOLD high to EMIF Bus low impedance
Delay time, EMIFA Bus low impedance to HOLDA high
Delay time, HOLD low to AECLKOUTx high impedance
Delay time, HOLD high to AECLKOUTx low impedance
2E
0
ns
ns
ns
ns
ns
ns
d(HOLDL-EMHZ)
d(EMHZ-HOLDAL)
d(HOLDH-EMLZ)
d(EMLZ-HOLDAH)
d(HOLDL-EKOHZ)
d(HOLDH-EKOLZ)
2E
7E
2E
0
2E
¶
2E
2E
7E
†
‡
E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA.
EMIFA Bus consists of: ACE[3:0], ABE[3:0], AED[31:0], AEA[22:3], AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and
AAWE/ASDWE/ASWE , ASDCKE, ASOE3, and APDT.
The EKxHZ bits in the EMIF Global Control register (GBLCTL) determine the state of the ECLKOUTx signals during HOLDA. If EKxHZ = 0,
ECLKOUTx continues clocking during Hold mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during Hold mode, as shown in Figure 7−20.
All pending EMIF transactions are allowed to complete before HOLDA is asserted. If no bus transactions are occurring, then the minimum delay
time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.
§
¶
External Requestor
DSP Owns Bus
DSP Owns Bus
Owns Bus
3
HOLD
2
5
HOLDA
1
4
7
†
EMIF Bus
C6413/C6410
C6413/C6410
‡
AECLKOUTx
(EKxHZ = 0)
6
‡
AECLKOUTx
(EKxHZ = 1)
†
‡
EMIFA Bus consists of: ACE[3:0], ABE[3:0], AED[31:0], AEA[22:3], AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and
AAWE/ASDWE/ASWE, ASDCKE, ASOE3, and APDT.
The EKxHZ bits in the EMIF Global Control register (GBLCTL) determine the state of the ECLKOUTx signals during HOLDA. If EKxHZ = 0,
ECLKOUTx continues clocking during Hold mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during Hold mode, as shown in Figure 7−20.
Figure 7−20. HOLD/HOLDA Timing for EMIFA
110
SPRS247E
April 2004 − Revised May 2005
BUSREQ Timing
7.6
BUSREQ Timing
Table 7−16. Switching Characteristics Over Recommended Operating Conditions for the BUSREQ Cycles
for EMIFA Module (see Figure 7−21)
−400
−500
NO.
PARAMETER
UNIT
MIN
MAX
1
t
Delay time, AECLKOUTx high to ABUSREQ valid
0.6
7.1
ns
d(AEKO1H-ABUSRV)
AECLKOUTx
1
1
ABUSREQ
Figure 7−21. BUSREQ Timing for EMIFA
111
April 2004 − Revised May 2005
SPRS247E
Reset Timing
7.7
Reset Timing
Table 7−17. Timing Requirements for Reset (see Figure 7−22)
−400
−500
NO.
UNIT
MIN
MAX
¶
1
t
t
t
Width of the RESET pulse
250
µs
ns
ns
w(RST)
su(boot)
h(boot)
†
‡
16
17
Setup time, boot configuration bits valid before RESET high
4E or 4C
†
§
Hold time, boot configuration bits valid after RESET high
4P
†
‡
AEA[22:19], LENDIAN, BOOTMODE[1:0], and AECLKIN_SEL[1:0] are the boot configuration pins during device reset.
E = 1/ECLKIN clock frequency in ns. C = 1/CLKIN clock frequency in ns.
Select the MIN parameter value, whichever value is larger.
P = 1/CPU clock frequency in ns. For example, when running parts at 500 MHz, use P = 2 ns.
The device must be reset after the oscillator has stabilized. If RESETz is low during power-up, it can be kept low until the oscillator has stabilized.
Note: a device reset does not affect the state of the oscillator.
§
¶
§#
Table 7−18. Switching Characteristics Over Recommended Operating Conditions During Reset
(see Figure 7−22)
k
−400, −500
NO.
PARAMETER
UNIT
MIN
2E
MAX
3P + 20E
8P + 20E
2
3
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Delay time, RESET low to ECLKIN synchronized internally
Delay time, RESET high to ECLKIN synchronized internally
Delay time, RESET low to ECLKOUT1 high impedance
Delay time, RESET high to ECLKOUT1 valid
Delay time, RESET low to EMIF Z high impedance
Delay time, RESET high to EMIF Z valid
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
d(RSTL-ECKI)
2E
d(RSTH-ECKI)
4
2E
d(RSTL-ECKO1HZ)
d(RSTH-ECKO1V)
d(RSTL-EMIFZHZ)
d(RSTH-EMIFZV)
d(RSTL-EMIFHIV)
d(RSTH-EMIFHV)
d(RSTL-EMIFLIV)
d(RSTH-EMIFLV)
d(RSTL-HIGHIV)
d(RSTH-HIGHV)
d(RSTL-ZHZ)
5
8P + 20E
3P + 4E
6
2E
16E
2E
7
8P + 20E
8
Delay time, RESET low to EMIF high group invalid
Delay time, RESET high to EMIF high group valid
Delay time, RESET low to EMIF low group invalid
Delay time, RESET high to EMIF low group valid
Delay time, RESET low to high group invalid
9
8P + 20E
8P + 20E
11P
10
11
12
13
14
15
2E
0
Delay time, RESET high to high group valid
Delay time, RESET low to Z group high impedance
Delay time, RESET high to Z group valid
0
2P
8P
d(RSTH-ZV)
41032 x
OSCIN
||¶
18
t
Delay time, Internal oscillator startup time
CLKINSEL = 0
ns
d(OSCSTART)
§
¶
P = 1/CPU clock frequency in ns. For example, when running parts at 500 MHz, use P = 2 ns.
The device must be reset after the oscillator has stabilized. If RESETz is low during power-up, it can be kept low until the oscillator has stabilized.
Note: a device reset does not affect the state of the oscillator.
E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA.
Assuming core power supply has stabilized at recommended operating conditions.
#
||
kEMIF Z group consists of:
AEA[22:3], AED[31:0], ACE[3:0], ABE[3:0], AARE/ASDCAS/ASADS/ASRE,AAWE/ASDWE/ASWE,
and AAOE/ASDRAS/ASOE, ASOE3, ASDCKE, APDT., and AECLKOUT1
EMIF high group consists of: AHOLDA (when the corresponding HOLD input is high)
EMIF low group consists of: ABUSREQ; AHOLDA (when the corresponding HOLD input is low)
High group consists of:
Z group consists of:
HRDY (when HPI is enabled, otherwise in Z group)
CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKS0, CLKS1, DR0, DR1, CLKR0, CLKR1, FSR0, FSR1,
TOUT0/HPI_EN, TOUT1/LENDIAN, GP0[7:0], HD[7:0], HD[15:8]/GP0[15:8], HD[21:16]/AXR1[5:0],
HD22/AFSX1, HD23/AFSR1, HD24/ACLKX1, HD25/ACLKR1, HD26/AHCLKR1, HD27/AHCLKX1,
HD28/AMUTE1, HD29/AMUTEIN1, HD30, HD31, HRDY, HDS2, HDS1/ACLKR1[3], HCS/ACLKR1[2],
HAS/ACLKR1[1], HR/W/AFSR1[3], HHWIL/AFSR1[2] (16-bit HPI mode only), HCNTL0/AFSR1[1], HCNTL1,
HINT,, ACLKR0, AFSR0, AHCLKR0, AMUTEIN0, AMUTE0, AXR0[5:0], SDA1, SCL1, SDA0, SCL0,
TDO, and EMU[11:0]
112
SPRS247E
April 2004 − Revised May 2005
Reset Timing
CLKOUT4
CLKOUT6
1
RESET
2
4
3
5
AECLKIN
AECLKOUT1
AECLKOUT2
6
7
†‡
EMIF Z Group
9
8
†
EMIF High Group
11
13
10
†
EMIF Low Group
12
14
†
High Group
15
†‡
Z Group
17
16
Boot and Device
Configuration Inputs
§
†
EMIF Z group consists of:
AEA[22:3], AED[31:0], ACE[3:0], ABE[3:0], AARE/ASDCAS/ASADS/ASRE,AAWE/ASDWE/ASWE,
and AAOE/ASDRAS/ASOE, ASOE3, ASDCKE, APDT., and AECLKOUT1
EMIF high group consists of: AHOLDA (when the corresponding HOLD input is high)
EMIF low group consists of: ABUSREQ; AHOLDA (when the corresponding HOLD input is low)
High group consists of:
Z group consists of:
HRDY (when HPI is enabled, otherwise in Z group)
CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKS0, CLKS1, DR0, DR1, CLKR0, CLKR1, FSR0, FSR1,
TOUT0/HPI_EN, TOUT1/LENDIAN, GP0[7:0], HD[7:0], HD[15:8]/GP0[15:8], HD[21:16]/AXR1[5:0],
HD22/AFSX1, HD23/AFSR1, HD24/ACLKX1, HD25/ACLKR1, HD26/AHCLKR1, HD27/AHCLKX1,
HD28/AMUTE1, HD29/AMUTEIN1, HD30, HD31, HRDY, HDS2, HDS1/ACLKR1[3], HCS/ACLKR1[2],
HAS/ACLKR1[1], HR/W/AFSR1[3], HHWIL/AFSR1[2] (16-bit HPI mode only), HCNTL0/AFSR1[1], HCNTL1,
HINT,, ACLKR0, AFSR0, AHCLKR0, AMUTEIN0, AMUTE0, AXR0[5:0], SDA1,
SCL1, SDA0, SCL0, TDO, and EMU[11:0]
‡
§
If AEA[22:19], LENDIAN, BOOTMODE[1:0], and AECLKIN_SEL[1:0] pins are actively driven, care must be taken to ensure no timing contention
between parameters 6, 7, 14, 15, 16, and 17.
Boot and Device Configurations Inputs (during reset) include: AEA[22:19], LENDIAN, BOOTMODE[1:0], and AECLKIN_SEL[1:0].
†
Figure 7−22. Reset Timing
113
April 2004 − Revised May 2005
SPRS247E
External Interrupt Timing
7.8
External Interrupt Timing
†
Table 7−19. Timing Requirements for External Interrupts (see Figure 7−23)
−400
−500
NO.
UNIT
MIN MAX
Width of the NMI interrupt pulse low
Width of the EXT_INT interrupt pulse low
Width of the NMI interrupt pulse high
Width of the EXT_INT interrupt pulse high
4P
8P
4P
8P
ns
ns
ns
ns
1
2
t
t
w(ILOW)
w(IHIGH)
†
P = 1/CPU clock frequency in ns. For example, when running parts at 500 MHz, use P = 2 ns.
2
1
EXT_INTx, NMI
Figure 7−23. External/NMI Interrupt Timing
114
SPRS247E
April 2004 − Revised May 2005
Multichannel Audio Serial Port (McASP) Timing
7.9
Multichannel Audio Serial Port (McASP) Timing
Table 7−20. Timing Requirements for McASP (see Figure 7−24 and Figure 7−25)
−400
−500
NO.
UNIT
MIN
20
MAX
1
2
3
4
t
t
t
t
Cycle time, AHCLKR/X
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
c(AHCKRX)
w(AHCKRX)
c(CKRX)
Pulse duration, AHCLKR/X high or low
Cycle time, ACLKR/X
10
ACLKR/X ext
ACLKR/X ext
ACLKR/X int
ACLKR/X ext
ACLKR/X int
ACLKR/X ext
ACLKR/X int
ACLKR/X ext
ACLKR/X int
ACLKR/X ext
25
Pulse duration, ACLKR/X high or low
12.25
w(CKRX)
5
5
5
5
5
5
5
5
5
6
7
8
t
t
t
t
Setup time, AFSR/X input valid before ACLKR/X latches data
Hold time, AFSR/X input valid after ACLKR/X latches data
Setup time, AXR input valid before ACLKR/X latches data
Hold time, AXR input valid after ACLKR/X latches data
su(FRXC-KRX)
h(CKRX-FRX)
su(AXR-CKRX)
h(CKRX-AXR)
Table 7−21. Switching Characteristics Over Recommended Operating Conditions for McASP
(see Figure 7−24 and Figure 7−25)
−400
−500
NO.
PARAMETER
UNIT
MIN
20
MAX
9
t
t
t
t
Cycle time, AHCLKR/X
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
c(AHCKRX)
w(AHCKRX)
c(CKRX)
10
11
12
Pulse duration, AHCLKR/X high or low
Cycle time, ACLKR/X
10
33
16.5
−1
2
ACLKR/X int
ACLKR/X int
ACLKR/X int
ACLKR/X ext
ACLKR/X int
ACLKR/X ext
ACLKR/X int
ACLKR/X ext
Pulse duration, ACLKR/X high or low
w(CKRX)
5
13
14
15
t
t
t
Delay time, ACLKR/X transmit edge to AFSX/R output valid
Delay time, ACLKR/X transmit edge to AXR output valid
d(CKRX-FRX)
12
5
−1
2
d(CKRX-AXRV)
dis(CKRX−AXRHZ)
12
10
10
0
Disable time, AXR high impedance following last data bit from
ACLKR/X transmit edge
0
115
April 2004 − Revised May 2005
SPRS247E
Multichannel Audio Serial Port (McASP) Timing
2
1
2
AHCLKR/X (Falling Edge Polarity)
AHCLKR/X (Rising Edge Polarity)
4
3
4
ACLKR/X (Falling Edge Polarity)
ACLKR/X (Rising Edge Polarity)
6
5
AFSR/X (Bit Width, 0 Bit Delay)
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay)
AFSR/X (Slot Width, 0 Bit Delay)
AFSR/X (Slot Width, 1 Bit Delay)
AFSR/X (Slot Width, 2 Bit Delay)
8
7
AXR[n] (Data In/Receive)
A0 A1
A30 A31 B0 B1
B30 B31 C0 C1 C2 C3
C31
Figure 7−24. McASP Input Timings
116
SPRS247E
April 2004 − Revised May 2005
Multichannel Audio Serial Port (McASP) Timing
10
10
9
AHCLKR/X (Falling Edge Polarity)
AHCLKR/X (Rising Edge Polarity)
12
11
12
ACLKR/X (Falling Edge Polarity)
ACLKR/X (Rising Edge Polarity)
13
13
13
13
AFSR/X (Bit Width, 0 Bit Delay)
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay)
AFSR/X (Slot Width, 0 Bit Delay)
AFSR/X (Slot Width, 1 Bit Delay)
AFSR/X (Slot Width, 2 Bit Delay)
AXR[n] (Data Out/Transmit)
13
13
13
14
14
14
14
15
14
14
A0 A1
A30 A31 B0 B1
B30 B31 C0 C1 C2 C3
C31
Figure 7−25. McASP Output Timings
117
April 2004 − Revised May 2005
SPRS247E
Inter-Integrated Circuits (I2C) Timing
7.10 Inter-Integrated Circuits (I2C) Timing
†
Table 7−22. Timing Requirements for I2C Timings (see Figure 7−26)
−400
−500
STANDARD
MODE
FAST
MODE
NO.
UNIT
MIN MAX
MIN MAX
1
2
t
t
Cycle time, SCL
10
2.5
µs
µs
c(SCL)
Setup time, SCL high before SDA low (for a repeated START
condition)
4.7
0.6
0.6
su(SCLH-SDAL)
Hold time, SCL low after SDA low (for a START and a repeated
START condition)
3
t
4
µs
h(SCLL-SDAL)
4
5
t
t
t
t
t
t
t
t
t
t
t
Pulse duration, SCL low
4.7
4
1.3
0.6
µs
µs
ns
µs
µs
ns
ns
ns
ns
µs
ns
pF
w(SCLL)
Pulse duration, SCL high
w(SCLH)
‡
6
Setup time, SDA valid before SCL high
250
100
su(SDAV-SDLH)
h(SDA-SDLL)
w(SDAH)
r(SDA)
2
§
§
¶
7
Hold time, SDA valid after SCL low (For I C bus™ devices)
0
0
0.9
8
Pulse duration, SDA high between STOP and START conditions
Rise time, SDA
4.7
1.3
#
9
1000 20 + 0.1C
300
300
300
300
b
b
b
b
#
#
#
10
11
12
13
14
15
Rise time, SCL
1000 20 + 0.1C
300 20 + 0.1C
300 20 + 0.1C
r(SCL)
Fall time, SDA
f(SDA)
Fall time, SCL
f(SCL)
Setup time, SCL high before SDA high (for STOP condition)
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
4
0.6
0
su(SCLH-SDAH)
50
w(SP)
#
C
400
400
b
†
‡
The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down.
2
2
A Fast-mode I C-bus™ device can be used in a Standard-mode I C-bus™ system, but the requirement t
≥ 250 ns must then be met.
su(SDA−SCLH)
This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period
of the SCL signal, it must output the next data bit to the SDA line t max + t
I C-Bus Specification) before the SCL line is released.
= 1000 + 250 = 1250 ns (according to the Standard-mode
r
su(SDA−SCLH)
2
§
A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V
region of the falling edge of SCL.
of the SCL signal) to bridge the undefined
] of the SCL signal.
IHmin
¶
#
The maximum t
has only to be met if the device does not stretch the low period [t
h(SDA−SCLL)
w(SCLL)
C = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
b
11
9
SDA
6
8
14
4
13
5
10
SCL
1
12
3
2
7
3
Stop
Start
Repeated
Start
Stop
Figure 7−26. I2C Receive Timings
118
SPRS247E
April 2004 − Revised May 2005
Inter-Integrated Circuits (I2C) Timing
†
Table 7−23. Switching Characteristics for I2C Timings (see Figure 7−27)
−400
−500
STANDARD
MODE
FAST
MODE
NO.
PARAMETER
UNIT
MIN MAX
MIN MAX
16
17
t
t
Cycle time, SCL
10
2.5
0.6
µs
µs
c(SCL)
Delay time, SCL high to SDA low (for a repeated START condition)
4.7
d(SCLH-SDAL)
Delay time, SDA low to SCL low (for a START and a repeated
START condition)
18
t
4
0.6
µs
d(SDAL-SCLL)
19
20
21
22
23
24
25
26
27
28
29
t
t
t
t
t
t
t
t
t
t
Pulse duration, SCL low
4.7
4
1.3
0.6
µs
µs
ns
µs
µs
ns
ns
ns
ns
µs
pF
w(SCLL)
Pulse duration, SCL high
w(SCLH)
d(SDAV-SDLH)
v(SDLL-SDAV)
w(SDAH)
r(SDA)
Delay time, SDA valid to SCL high
250
0
100
2
Valid time, SDA valid after SCL low (For I C bus™ devices)
0
0.9
Pulse duration, SDA high between STOP and START conditions
4.7
1.3
†
Rise time, SDA
1000 20 + 0.1C
300
300
300
300
b
b
b
b
†
†
†
Rise time, SCL
1000 20 + 0.1C
r(SCL)
Fall time, SDA
300 20 + 0.1C
300 20 + 0.1C
f(SDA)
Fall time, SCL
f(SCL)
Delay time, SCL high to SDA high (for STOP condition)
Capacitance for each I2C pin
4
0.6
d(SCLH-SDAH)
C
10
10
p
†
C = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
b
26
24
SDA
21
23
19
28
20
25
SCL
16
27
18
17
22
18
Stop
Start
Repeated
Start
Stop
Figure 7−27. I2C Transmit Timings
119
April 2004 − Revised May 2005
SPRS247E
Host-Port Interface (HPI) Timing
7.11 Host-Port Interface (HPI) Timing
†‡
Table 7−24. Timing Requirements for Host-Port Interface Cycles (see Figure 7−28 through Figure 7−35)
−400
−500
NO.
UNIT
MIN
5
MAX
§
1
2
t
t
t
t
t
t
t
t
Setup time, select signals valid before HSTROBE low
ns
ns
ns
ns
ns
ns
ns
ns
su(SELV-HSTBL)
h(HSTBL-SELV)
w(HSTBL)
§
Hold time, select signals valid after HSTROBE low
2.4
¶
3
Pulse duration, HSTROBE low
4P
4
Pulse duration, HSTROBE high between consecutive accesses
4P
5
w(HSTBH)
§
10
11
12
13
Setup time, select signals valid before HAS low
su(SELV-HASL)
h(HASL-SELV)
su(HDV-HSTBH)
h(HSTBH-HDV)
§
Hold time, select signals valid after HAS low
2
Setup time, host data valid before HSTROBE high
Hold time, host data valid after HSTROBE high
5
2.8
Hold time, HSTROBE low after HRDY low. HSTROBE should not be
inactivated until HRDY is active (low); otherwise, HPI writes will not complete
properly.
14
t
2
ns
h(HRDYL-HSTBL)
18
19
t
t
Setup time, HAS low before HSTROBE low
Hold time, HAS low after HSTROBE low
2
ns
ns
su(HASL-HSTBL)
2.1
h(HSTBL-HASL)
†
‡
§
¶
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
P = 1/CPU clock frequency in ns. For example, when running parts at 500 MHz, use P = 2 ns.
Select signals include: HCNTL[1:0] and HR/W. For HPI16 mode only, select signals also include HHWIL.
Select the parameter value of 4P or 12.5 ns, whichever is larger.
Table 7−25. Switching Characteristics Over Recommended Operating Conditions During Host-Port
†‡
Interface Cycles (see Figure 7−28 through Figure 7−35)
−400
−500
NO.
PARAMETER
UNIT
MIN
1.3
2
MAX
#
6
7
t
t
t
t
t
Delay time, HSTROBE low to HRDY high
4P + 8
ns
ns
ns
ns
ns
d(HSTBL-HRDYH)
Delay time, HSTROBE low to HD low impedance for an HPI read
Delay time, HD valid to HRDY low
d(HSTBL-HDLZ)
8
−3
d(HDV-HRDYL)
oh(HSTBH-HDV)
d(HSTBH-HDHZ)
9
Output hold time, HD valid after HSTROBE high
Delay time, HSTROBE high to HD high impedance
1.5
15
12
2P + 8 or
0P + 8
16
t
Delay time, HSTROBE low to HD valid (HPI16 mode, 2nd half-word only)
ns
d(HSTBL-HDV)
||
†
‡
#
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
P = 1/CPU clock frequency in ns. For example, when running parts at 500 MHz, use P = 2 ns.
This parameter is used during HPID reads and writes. For reads, at the beginning of a word transfer (HPI32) or the first half-word transfer (HPI16)
on the falling edge of HSTROBE, the HPI sends the request to the EDMA internal address generation hardware, and HRDY remains high until
the EDMA internal address generation hardware loads the requested data into HPID. For writes, HRDY goes high if the internal write buffer is
full.
||
If preceeding HSTROBE high pulse width > 6P, then this parameter value can be 0P + 8 ns.
120
SPRS247E
April 2004 − Revised May 2005
Host-Port Interface (HPI) Timing
HAS
HCNTL[1:0]
HR/W
1
1
1
1
2
2
2
2
2
2
1
1
HHWIL
4
3
3
†
HSTROBE
HCS
15
9
15
9
7
16
2nd half-word
HD[15:0] (output)
HRDY
1st half-word
6
8
†
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 7−28. HPI16 Read Timing (HAS Not Used, Tied High)
†
HAS
19
11
19
11
10
10
10
10
HCNTL[1:0]
HR/W
11
11
11
11
10
10
HHWIL
4
3
‡
HSTROBE
18
18
HCS
15
15
7
9
16
9
HD[15:0] (output)
HRDY
1st half-word
2nd half-word
6
8
†
‡
For correct operation, strobe the HAS signal only once per HSTROBE active cycle.
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 7−29. HPI16 Read Timing (HAS Used)
121
April 2004 − Revised May 2005
SPRS247E
Host-Port Interface (HPI) Timing
HAS
1
1
2
2
2
2
2
2
3
HCNTL[1:0]
HR/W
1
1
1
1
HHWIL
3
4
†
HSTROBE
HCS
12
12
13
2nd half-word
13
HD[15:0] (input)
1st half-word
6
14
HRDY
†
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 7−30. HPI16 Write Timing (HAS Not Used, Tied High)
19
11
19
†
HAS
11
11
11
10
10
10
10
10
10
HCNTL[1:0]
HR/W
11
11
HHWIL
3
4
‡
HSTROBE
18
12
18
HCS
12
13
2nd half-word
13
HD[15:0] (input)
1st half-word
6
14
HRDY
†
‡
For correct operation, strobe the HAS signal only once per HSTROBE active cycle.
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 7−31. HPI16 Write Timing (HAS Used)
122
SPRS247E
April 2004 − Revised May 2005
Host-Port Interface (HPI) Timing
HAS
HCNTL[1:0]
HR/W
1
1
2
2
3
†
HSTROBE
HCS
7
9
15
HD[31:0] (output)
HRDY
6
8
†
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 7−32. HPI32 Read Timing (HAS Not Used, Tied High)
19
†
HAS
11
10
HCNTL[1:0]
11
10
HR/W
18
3
‡
HSTROBE
HCS
7
9
15
HD[31:0] (output)
HRDY
6
8
†
‡
For correct operation, strobe the HAS signal only once per HSTROBE active cycle.
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 7−33. HPI32 Read Timing (HAS Used)
123
April 2004 − Revised May 2005
SPRS247E
Host-Port Interface (HPI) Timing
HAS
HCNTL[1:0]
HR/W
1
1
2
2
3
†
HSTROBE
HCS
12
13
HD[31:0] (input)
6
14
HRDY
†
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 7−34. HPI32 Write Timing (HAS Not Used, Tied High)
19
†
HAS
11
10
HCNTL[1:0]
11
10
HR/W
3
18
‡
HSTROBE
HCS
12
13
HD[31:0] (input)
6
14
HRDY
†
‡
For correct operation, strobe the HAS signal only once per HSTROBE active cycle.
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 7−35. HPI32 Write Timing (HAS Used)
124
SPRS247E
April 2004 − Revised May 2005
Multichannel Buffered Serial Port (McBSP) Timing
7.12 Multichannel Buffered Serial Port (McBSP) Timing
†‡
Table 7−26. Timing Requirements for McBSP (see Figure 7−36)
−400
−500
NO.
UNIT
MIN
4P or 6.67
MAX
‡§
2
3
t
t
Cycle time, CLKR/X
CLKR/X ext
CLKR/X ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
ns
ns
c(CKRX)
¶
Pulse duration, CLKR/X high or CLKR/X low
0.5t
− 1
w(CKRX)
c(CKRX)
9
5
6
t
t
t
t
t
t
Setup time, external FSR high before CLKR low
Hold time, external FSR high after CLKR low
Setup time, DR valid before CLKR low
ns
ns
ns
ns
ns
ns
su(FRH-CKRL)
h(CKRL-FRH)
su(DRV-CKRL)
h(CKRL-DRV)
su(FXH-CKXL)
h(CKXL-FXH)
1.3
6
3
8
7
0.9
3
8
Hold time, DR valid after CLKR low
3.1
9
10
11
Setup time, external FSX high before CLKX low
Hold time, external FSX high after CLKX low
1.3
6
3
†
‡
§
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
P = 1/CPU clock frequency in ns. For example, when running parts at 500 MHz, use P = 2 ns.
Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. The
minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing
requirements.
¶
This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.
125
April 2004 − Revised May 2005
SPRS247E
Multichannel Buffered Serial Port (McBSP) Timing
†‡
Table 7−27. Switching Characteristics Over Recommended Operating Conditions for McBSP
(see Figure 7−36)
−400
−500
NO.
PARAMETER
UNIT
MIN
MAX
Delay time, CLKS high to CLKR/X high for internal CLKR/X generated
from CLKS input
1
t
1.4
10
ns
d(CKSH-CKRXH)
§¶#
2
3
4
t
t
t
Cycle time, CLKR/X
CLKR/X int
CLKR/X int
CLKR int
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
4P or 6.67
ns
ns
ns
c(CKRX)
||
||
Pulse duration, CLKR/X high or CLKR/X low
Delay time, CLKR high to internal FSR valid
C − 1
C + 1
w(CKRX)
−2.1
−1.7
3
d(CKRH-FRV)
3
9
t
t
t
Delay time, CLKX high to internal FSX valid
ns
ns
ns
d(CKXH-FXV)
dis(CKXH-DXHZ)
d(CKXH-DXV)
1.7
9
4
−3.9
Disable time, DX high impedance following last data bit
from CLKX high
12
13
2
9
−3.9 + D1k
2.0 + D1k
4 + D2k
9 + D2k
Delay time, CLKX high to DX valid
Delay time, FSX high to DX valid
h
h
FSX int
FSX ext
−2.3 + D1
5.6 + D2
14
t
ns
d(FXH-DXV)
ONLY applies when in data
delay 0 (XDATDLY = 00b) mode
h
h
1.9 + D1
9 + D2
†
‡
§
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
Minimum delay times also represent minimum output hold times.
Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times are based
on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements.
P = 1/CPU clock frequency in ns. For example, when running parts at 500 MHz, use P = 2 ns.
Use whichever value is greater.
¶
#
||
C = H or L
S = sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)
=
sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see ¶ footnote above).
kExtra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 4P, D2 = 8P
hExtra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 4P, D2 = 8P
126
SPRS247E
April 2004 − Revised May 2005
Multichannel Buffered Serial Port (McBSP) Timing
CLKS
1
2
3
3
CLKR
FSR (int)
FSR (ext)
DR
4
4
5
6
7
8
Bit(n-1)
(n-2)
(n-3)
2
3
3
CLKX
9
FSX (int)
11
10
FSX (ext)
FSX (XDATDLY=00b)
†
13
14
13
†
12
DX
Bit 0
Bit(n-1)
(n-2)
(n-3)
†
Parameter No. 13 applies to the first data bit only when XDATDLY ≠ 0
Figure 7−36. McBSP Timing
Table 7−28. Timing Requirements for FSR When GSYNC = 1 (see Figure 7−37)
−400
−500
NO.
UNIT
MIN MAX
1
2
t
t
Setup time, FSR high before CLKS high
Hold time, FSR high after CLKS high
4
4
ns
ns
su(FRH-CKSH)
h(CKSH-FRH)
CLKS
1
2
FSR external
CLKR/X (no need to resync)
CLKR/X (needs resync)
Figure 7−37. FSR Timing When GSYNC = 1
127
April 2004 − Revised May 2005
SPRS247E
Multichannel Buffered Serial Port (McBSP) Timing
Table 7−29. Timing Requirements for McBSP as SPI Master or Slave:
†‡
CLKSTP = 10b, CLKXP = 0 (see Figure 7−38)
−400
−500
NO.
UNIT
MASTER
SLAVE
MIN MAX
MIN
12
4
MAX
4
5
t
t
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
2 − 12P
5 + 24P
ns
ns
su(DRV-CKXL)
h(CKXL-DRV)
†
‡
P = 1/CPU clock frequency in ns. For example, when running parts at 500 MHz, use P = 2 ns.
For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
Table 7−30. Switching Characteristics Over Recommended Operating Conditions for McBSP as
†‡
SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 (see Figure 7−38)
−400
−500
NO.
PARAMETER
UNIT
§
MASTER
MIN MAX
SLAVE
MIN
MAX
¶
1
2
3
t
t
t
Hold time, FSX low after CLKX low
T − 2 T + 3
L − 2 L + 3
ns
ns
ns
h(CKXL-FXL)
d(FXL-CKXH)
d(CKXH-DXV)
#
Delay time, FSX low to CLKX high
Delay time, CLKX high to DX valid
−2
4
12P + 2.8 20P + 17
Disable time, DX high impedance following last data bit from
CLKX low
6
t
L − 2 L + 3
ns
dis(CKXL-DXHZ)
Disable time, DX high impedance following last data bit from
FSX high
7
8
t
t
4P + 3 12P + 17
ns
ns
dis(FXH-DXHZ)
Delay time, FSX low to DX valid
8P + 1.8 16P + 17
d(FXL-DXV)
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 500 MHz, use P = 2 ns.
For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)
=
Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP
¶
#
FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock
(CLKX).
CLKX
1
2
8
FSX
7
6
3
DX
DR
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
4
5
Bit 0
(n-2)
(n-3)
(n-4)
Figure 7−38. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
128
SPRS247E
April 2004 − Revised May 2005
Multichannel Buffered Serial Port (McBSP) Timing
Table 7−31. Timing Requirements for McBSP as SPI Master or Slave:
†‡
CLKSTP = 11b, CLKXP = 0 (see Figure 7−39)
−400
−500
NO.
UNIT
MASTER
SLAVE
MIN MAX
MIN
12
4
MAX
4
5
t
t
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
2 − 12P
ns
ns
su(DRV-CKXH)
5 + 24P
h(CKXH-DRV)
†
‡
P = 1/CPU clock frequency in ns. For example, when running parts at 500 MHz, use P = 2 ns.
For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
Table 7−32. Switching Characteristics Over Recommended Operating Conditions for McBSP as
†‡
SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 (see Figure 7−39)
−400
−500
NO.
PARAMETER
UNIT
§
MASTER
SLAVE
MIN MAX
MIN
MAX
¶
1
2
3
t
t
t
Hold time, FSX low after CLKX low
L − 2 L + 3
T − 2 T + 3
ns
ns
ns
h(CKXL-FXL)
d(FXL-CKXH)
d(CKXL-DXV)
#
Delay time, FSX low to CLKX high
Delay time, CLKX low to DX valid
−2
4
12P + 2.8 20P + 17
12P + 3 20P + 17
Disable time, DX high impedance following last data bit from
CLKX low
6
7
t
t
−2
4
ns
ns
dis(CKXL-DXHZ)
d(FXL-DXV)
Delay time, FSX low to DX valid
H − 2 H + 4
8P + 2 16P + 17
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 500 MHz, use P = 2 ns.
For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)
=
Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP
¶
#
FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock
(CLKX).
CLKX
1
2
7
FSX
DX
6
3
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-3)
(n-4)
4
5
DR
Bit 0
(n-2)
(n-4)
Figure 7−39. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
129
April 2004 − Revised May 2005
SPRS247E
Multichannel Buffered Serial Port (McBSP) Timing
Table 7−33. Timing Requirements for McBSP as SPI Master or Slave:
†‡
CLKSTP = 10b, CLKXP = 1 (see Figure 7−40)
−400
−500
NO.
UNIT
MASTER
SLAVE
MIN MAX
MIN
12
4
MAX
4
5
t
t
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
2 − 12P
ns
ns
su(DRV-CKXH)
5 + 24P
h(CKXH-DRV)
†
‡
P = 1/CPU clock frequency in ns. For example, when running parts at 500 MHz, use P = 2 ns.
For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
Table 7−34. Switching Characteristics Over Recommended Operating Conditions for McBSP as
†‡
SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 (see Figure 7−40)
−400
−500
NO.
PARAMETER
UNIT
§
MASTER
SLAVE
MIN MAX
MIN
MAX
¶
1
2
3
t
t
t
Hold time, FSX low after CLKX high
T − 2 T + 3
H − 2 H + 3
ns
ns
ns
h(CKXH-FXL)
d(FXL-CKXL)
d(CKXL-DXV)
#
Delay time, FSX low to CLKX low
Delay time, CLKX low to DX valid
−2
4
12P + 2.8 20P + 17
Disable time, DX high impedance following last data bit from
CLKX high
6
t
H − 2 H + 3
ns
dis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit from
FSX high
7
8
t
t
4P + 3 12P + 17
8P + 2 16P + 17
ns
ns
dis(FXH-DXHZ)
Delay time, FSX low to DX valid
d(FXL-DXV)
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 500 MHz, use P = 2 ns.
For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)
=
Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP
¶
#
FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock
(CLKX).
CLKX
1
2
8
FSX
7
6
3
DX
DR
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
4
5
Bit 0
(n-2)
(n-3)
(n-4)
Figure 7−40. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
130
SPRS247E
April 2004 − Revised May 2005
Multichannel Buffered Serial Port (McBSP) Timing
Table 7−35. Timing Requirements for McBSP as SPI Master or Slave:
†‡
CLKSTP = 11b, CLKXP = 1 (see Figure 7−41)
−400
−500
NO.
UNIT
MASTER
SLAVE
MIN MAX
MIN
12
4
MAX
4
5
t
t
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
2 − 12P
ns
ns
su(DRV-CKXH)
5 + 24P
h(CKXH-DRV)
†
‡
P = 1/CPU clock frequency in ns. For example, when running parts at 500 MHz, use P = 2 ns.
For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
Table 7−36. Switching Characteristics Over Recommended Operating Conditions for McBSP as
†‡
SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 (see Figure 7−41)
−400
−500
NO.
PARAMETER
UNIT
§
MASTER
SLAVE
MIN MAX
MIN
MAX
¶
1
2
3
t
t
t
Hold time, FSX low after CLKX high
H − 2 H + 3
T − 2 T + 1
ns
ns
ns
h(CKXH-FXL)
d(FXL-CKXL)
d(CKXH-DXV)
#
Delay time, FSX low to CLKX low
Delay time, CLKX high to DX valid
−2
4
12P + 2.8 20P + 17
12P + 3 20P + 17
Disable time, DX high impedance following last data bit from
CLKX high
6
7
t
t
−2
4
ns
ns
dis(CKXH-DXHZ)
d(FXL-DXV)
Delay time, FSX low to DX valid
L − 2 L + 4
8P + 2 16P + 17
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 500 MHz, use P = 2 ns.
For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)
=
Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP
¶
#
FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock
(CLKX).
CLKX
1
2
FSX
DX
7
6
3
Bit 0
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
4
5
DR
(n-2)
(n-3)
(n-4)
Figure 7−41. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
131
April 2004 − Revised May 2005
SPRS247E
Timer Timing
7.13 Timer Timing
†
Table 7−37. Timing Requirements for Timer Inputs (see Figure 7−42)
−400
−500
NO.
UNIT
MIN
MAX
1
2
t
t
Pulse duration, TINP high
Pulse duration, TINP low
8P
8P
ns
ns
w(TINPH)
w(TINPL)
†
P = 1/CPU clock frequency in ns. For example, when running parts at 500 MHz, use P = 2 ns.
†
Table 7−38. Switching Characteristics Over Recommended Operating Conditions for Timer Outputs
(see Figure 7−42)
−400
−500
NO.
PARAMETER
UNIT
MIN
8P−3
8P−3
MAX
3
4
t
t
Pulse duration, TOUT high
Pulse duration, TOUT low
ns
ns
w(TOUTH)
w(TOUTL)
†
P = 1/CPU clock frequency in ns. For example, when running parts at 500 MHz, use P = 2 ns.
2
1
TINPx
4
3
TOUTx
Figure 7−42. Timer Timing
132
SPRS247E
April 2004 − Revised May 2005
General-Purpose Input/Output (GPIO) Port Timing
7.14 General-Purpose Input/Output (GPIO) Port Timing
†‡
Table 7−39. Timing Requirements for GPIO Inputs (see Figure 7−43)
−400
−500
NO.
UNIT
MIN
MAX
1
2
t
t
Pulse duration, GPIx high
Pulse duration, GPIx low
8P
8P
ns
ns
w(GPIH)
w(GPIL)
†
‡
P = 1/CPU clock frequency in ns. For example, when running parts at 500 MHz, use P = 2 ns.
The pulse width given is sufficient to generate a CPU interrupt or an EDMA event. However, if a user wants to have the DSP recognize the GPIx
changes through software polling of the GPIO register, the GPIx duration must be extended to at least 12P to allow the DSP enough time to access
the GPIO register through the CFGBUS.
†
Table 7−40. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs
(see Figure 7−43)
−400
−500
NO.
PARAMETER
UNIT
MIN
MAX
§
3
4
t
t
Pulse duration, GPOx high
Pulse duration, GPOx low
24P − 8
ns
ns
w(GPOH)
§
24P − 8
w(GPOL)
†
§
P = 1/CPU clock frequency in ns. For example, when running parts at 500 MHz, use P = 2 ns.
This parameter value should not be used as a maximum performance specification. Actual performance of back-to-back accesses of the GPIO
is dependent upon internal bus activity.
2
1
GPIx
4
3
GPOx
Figure 7−43. GPIO Port Timing
133
April 2004 − Revised May 2005
SPRS247E
JTAG Test-Port Timing
7.15 JTAG Test-Port Timing
Table 7−41. Timing Requirements for JTAG Test Port (see Figure 7−44)
−400
−500
NO.
UNIT
MIN
MAX
1
3
4
t
t
t
Cycle time, TCK
35
10
9
ns
ns
ns
c(TCK)
Setup time, TDI/TMS/TRST valid before TCK high
Hold time, TDI/TMS/TRST valid after TCK high
su(TDIV-TCKH)
h(TCKH-TDIV)
Table 7−42. Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port
(see Figure 7−44)
−400
−500
NO.
PARAMETER
Delay time, TCK low to TDO valid
UNIT
ns
MIN
MAX
2
t
0
18
d(TCKL-TDOV)
1
TCK
TDO
2
2
4
3
TDI/TMS/TRST
Figure 7−44. JTAG Test-Port Timing
134
SPRS247E
April 2004 − Revised May 2005
Mechanical Data
8
Mechanical Data
Thermal Data
8.1
The following tables show the thermal resistance characteristics for the PBGA − GTS and ZTS mechanical
packages.
Table 8−1. Thermal Resistance Characteristics (S-PBGA Package) [GTS]
†
‡
NO.
°C/W
5.60
9.37
20.8
16.8
15.4
14.1
1.87
1.98
2.03
2.12
11.1
10.4
10.3
10.1
Board Type
Air Flow (m/s )
1
2
3
4
5
6
RΘ
RΘ
Junction-to-case
Junction-to-board
JEDEC Low-K Test Card
JEDEC High-K Test Card
JEDEC High-K Test Card
JEDEC High-K Test Card
JEDEC High-K Test Card
JEDEC High-K Test Card
JEDEC High-K Test Card
JEDEC High-K Test Card
JEDEC High-K Test Card
JEDEC High-K Test Card
JEDEC High-K Test Card
JEDEC High-K Test Card
JEDEC High-K Test Card
JEDEC High-K Test Card
N/A
N/A
0.00
0.5
JC
JB
RΘ
Junction-to-free air
Junction-to-package top
Junction-to-board
JA
1.0
2.00
0.00
0.5
7
8
Psi
Psi
JT
1.0
2.00
0.00
0.5
JB
1.0
2.00
†
‡
Board types are as defined by JEDEC. Reference JEDEC Standard JESD51−9. Test Boards for Area Array Surface Mount Package Thermal
Measurements.
m/s = meters per second
Table 8−2. Thermal Resistance Characteristics (S-PBGA Package) [ZTS]
†
‡
NO.
1
°C/W
5.60
9.37
20.8
16.8
15.4
14.1
1.87
1.98
2.03
2.12
11.1
10.4
10.3
10.1
Board Type
Air Flow (m/s )
RΘ
RΘ
Junction-to-case
Junction-to-board
JEDEC Low-K Test Card
JEDEC High-K Test Card
JEDEC High-K Test Card
JEDEC High-K Test Card
JEDEC High-K Test Card
JEDEC High-K Test Card
JEDEC High-K Test Card
JEDEC High-K Test Card
JEDEC High-K Test Card
JEDEC High-K Test Card
JEDEC High-K Test Card
JEDEC High-K Test Card
JEDEC High-K Test Card
JEDEC High-K Test Card
N/A
N/A
0.00
0.5
JC
2
JB
3
4
RΘ
Junction-to-free air
Junction-to-package top
Junction-to-board
JA
5
1.0
6
2.00
0.00
0.5
7
8
Psi
Psi
JT
1.0
2.00
0.00
0.5
JB
1.0
2.00
†
‡
Board types are as defined by JEDEC. Reference JEDEC Standard JESD51−9. Test Boards for Area Array Surface Mount Package Thermal
Measurements.
m/s = meters per second
135
April 2004 − Revised May 2005
SPRS247E
Mechanical Data
8.2
Packaging Information
The following packaging information reflects the most current released data available for the designated
device(s). This data is subject to change without notice and without revision of this document.
136
SPRS247E
April 2004 − Revised May 2005
PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
GTS
ZTS
TMS320C6410GTS400
TMS320C6410ZTS400
TMS320C6410ZTSA400
TMS320C6413GTS500
TMS320C6413GTSA500
TMS320C6413ZTS500
TMS320C6413ZTSA500
TMX320C6410GTS
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FCBGA
FCBGA
FCBGA
FCBGA
FCBGA
FCBGA
FCBGA
FCBGA
FCBGA
288
288
288
288
288
288
288
288
288
60
60
60
60
60
60
60
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
SNPB
SNAGCU
SNAGCU
SNPB
Level-4-220C-72HR
Level-4-260C-72HR
Level-4-260C-72HR
Level-4-220C-72HR
Level-4-220C-72HR
Level-4-260C-72HR
Level-4-260C-72HR
Call TI
ZTS
GTS
GTS
ZTS
SNPB
SNAGCU
SNAGCU
Call TI
ZTS
GTS
GTS
TMX320C6413GTS
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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