SMJ320VC5416 [TI]
Fixed-Point Digital Signal Processor; 定点数字信号处理器
| 型号： | SMJ320VC5416 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Fixed-Point Digital Signal Processor |
| 文件： | 总92页 (文件大小：1138K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SMJ320VC5416 Fixed-Point
Digital Signal Processor
Data Manual
Literature Number: SGUS035A
April 2003 – Revised July 2003
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production processing
does not necessarily include testing of all parameters.
Printed on Recycled Paper
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deems necessary to support this warranty. Except where mandated by government requirements, testing of all
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Copyright 2003, Texas Instruments Incorporated
REVISION HISTORY
REVISION
DATE
PRODUCT STATUS
HIGHLIGHTS
*
March 2003
Production Data
Production Data
Original
A
July 2003
Limit changes
iii
iv
Contents
Contents
Section
Page
1
2
SMJ320VC5416 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.1
2.2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.2.1
Pin Assignments for the HFG Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.3
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1.1
3.1.2
3.1.3
Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Extended Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2
3.3
3.4
3.5
On-Chip ROM With Bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
On-Chip RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
On-Chip Memory Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5.1
Relocatable Interrupt Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.6
On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.6.1
3.6.2
3.6.3
Software-Programmable Wait-State Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Programmable Bank-Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Bus Holders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.7
Parallel I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.7.1
3.7.2
Enhanced 8-/16-Bit Host-Port Interface (HPI8/16) . . . . . . . . . . . . . . . . . . . . . . . . . 19
HPI Nonmultiplexed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.8
3.9
3.10
3.11
3.12
Multichannel Buffered Serial Ports (McBSPs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Hardware Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Enhanced External Parallel Interface (XIO2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.12.1
3.12.2
3.12.3
3.12.4
3.12.5
3.12.6
3.12.7
3.12.8
3.12.9
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
DMA External Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
DMA Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
DMA Priority Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
DMA Source/Destination Address Modification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
DMA in Autoinitialization Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
DMA Transfer Counting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
DMA Transfer in Doubleword Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
DMA Channel Index Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.12.10 DMA Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.12.11 DMA Controller Synchronization Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
General-Purpose I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.13
3.13.1
3.13.2
McBSP Pins as General-Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
HPI Data Pins as General-Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.14
3.15
3.16
3.17
Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
McBSP Control Registers and Subaddresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
DMA Subbank Addressed Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
v
April 2003 – Revised July 2003
SGUS035A
Contents
3.18
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4
5
Documentation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.1
5.2
5.3
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Electrical Characteristics Over Recommended Operating Case Temperature Range
(Unless Otherwise Noted) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.4
5.5
5.6
5.7
Package Thermal Resistance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Timing Parameter Symbology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Internal Oscillator With External Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Clock Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.7.1
5.7.2
Divide-By-Two and Divide-By-Four Clock Options . . . . . . . . . . . . . . . . . . . . . . . . . 46
Multiply-By-N Clock Option (PLL Enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.8
Memory and Parallel I/O Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.8.1
5.8.2
5.8.3
5.8.4
Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
I/O Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
I/O Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.9
Ready Timing for Externally Generated Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
HOLD and HOLDA Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Reset, BIO, Interrupt, and MP/MC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timings . . . . . . . . . . . . . . . 64
External Flag (XF) and TOUT Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Multichannel Buffered Serial Port (McBSP) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
5.10
5.11
5.12
5.13
5.14
5.14.1
5.14.2
5.14.3
McBSP Transmit and Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
McBSP General-Purpose I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
McBSP as SPI Master or Slave Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.15
Host-Port Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
5.15.1
5.15.2
HPI8 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
HPI16 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.1 Ceramic Quad Flatpack Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
vi
SGUS035A
April 2003 – Revised July 2003
Figures
List of Figures
Figure
Page
2–1. 164-Pin HFG Ceramic Quad Flatpack (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3–1. SMJ320VC5416 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3–2. Program and Data Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3–3. Extended Program Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3–4. Processor Mode Status (PMST) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3–5. Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h] . . . . . 16
3–6. Software Wait-State Control Register (SWCR) [MMR Address 002Bh] . . . . . . . . . . . . . . . . . . . . . . . . . 17
3–7. Bank-Switching Control Register (BSCR) [MMR Address 0029h] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3–8. Host-Port Interface — Nonmultiplexed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3–9. HPI Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3–10. Multichannel Control Registers (MCR1 and MCR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3–11. Pin Control Register (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3–12. Nonconsecutive Memory Read and I/O Read Bus Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3–13. Consecutive Memory Read Bus Sequence (n = 3 reads) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3–14. Memory Write and I/O Write Bus Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3–15. DMA Transfer Mode Control Register (DMMCRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3–16. On-Chip DMA Memory Map for Program Space (DLAXS = 0 and SLAXS = 0) . . . . . . . . . . . . . . . . . 30
3–17. On-Chip DMA Memory Map for Data and IO Space (DLAXS = 0 and SLAXS = 0) . . . . . . . . . . . . . . 31
3–18. DMPREC Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3–19. General-Purpose I/O Control Register (GPIOCR) [MMR Address 003Ch] . . . . . . . . . . . . . . . . . . . . . 34
3–20. General-Purpose I/O Status Register (GPIOSR) [MMR Address 003Dh] . . . . . . . . . . . . . . . . . . . . . . 34
3–21. Device ID Register (CSIDR) [MMR Address 003Eh] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3–22. IFR and IMR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5–1. 3.3-V Test Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5–2. Internal Divide-by-Two Clock Option With External Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5–3. External Divide-by-Two Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5–4. Multiply-by-One Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5–5. Nonconsecutive Mode Memory Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5–6. Consecutive Mode Memory Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5–7. Memory Write (MSTRB = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5–8. Parallel I/O Port Read (IOSTRB = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5–9. Parallel I/O Port Write (IOSTRB = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5–10. Memory Read With Externally Generated Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5–11. Memory Write With Externally Generated Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5–12. I/O Read With Externally Generated Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5–13. I/O Write With Externally Generated Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5–14. HOLD and HOLDA Timings (HM = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5–15. Reset and BIO Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5–16. Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5–17. MP/MC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
vii
April 2003 – Revised July 2003
SGUS035A
Figures
5–18. Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timings . . . . . . . . . . . . . . . . . . . . . . 64
5–19. External Flag (XF) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5–20. TOUT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5–21. McBSP Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5–22. McBSP Transmit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5–23. McBSP General-Purpose I/O Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5–24. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . . 70
5–25. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . . 71
5–26. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . . 72
5–27. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . . 73
5–28. Using HDS to Control Accesses (HCS Always Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5–29. Using HCS to Control Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5–30. HINT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5–31. GPIOx Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5–32. Nonmultiplexed Read Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5–33. Nonmultiplexed Write Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5–34. HRDY Relative to CLKOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6–1. SMJ320VC5416 164-Pin Ceramic Quad Flatpack (HFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
viii
SGUS035A
April 2003 – Revised July 2003
Tables
List of Tables
Table
Page
2–1. Terminal Assignments for the SMJ320VC5416HFG (164-Pin CQFP Package)† . . . . . . . . . . . . . . . . . . 3
2–2. Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3–1. Standard On-Chip ROM Layout† . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3–2. Processor Mode Status (PMST) Register Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3–3. Software Wait-State Register (SWWSR) Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3–4. Software Wait-State Control Register (SWCR) Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3–5. Bank-Switching Control Register (BSCR) Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3–6. Bus Holder Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3–7. Sample Rate Input Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3–8. Clock Mode Settings at Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3–9. DMD Section of the DMMCRn Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3–10. DMA Reload Register Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3–11. DMA Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3–12. DMA Synchronization Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3–13. DMA Channel Interrupt Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3–14. CPU Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3–15. Peripheral Memory-Mapped Registers for Each DSP Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3–16. McBSP Control Registers and Subaddresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3–17. DMA Subbank Addressed Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3–18. Interrupt Locations and Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5–1. Thermal Resistance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5–2. Input Clock Frequency Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5–3. Clock Mode Pin Settings for the Divide-By-2 and By Divide-by-4 Clock Options . . . . . . . . . . . . . . . . . 46
5–4. Divide-By-2 and Divide-by-4 Clock Options Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5–5. Divide-By-2 and Divide-by-4 Clock Options Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5–6. Multiply-By-N Clock Option Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5–7. Multiply-By-N Clock Option Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5–8. Memory Read Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5–9. Memory Read Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5–10. Memory Write Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5–11. I/O Read Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5–12. I/O Read Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5–13. I/O Write Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5–14. Ready Timing Requirements for Externally Generated Wait States† . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5–15. Ready Switching Characteristics for Externally Generated Wait States† . . . . . . . . . . . . . . . . . . . . . . . 55
5–16. HOLD and HOLDA Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5–17. HOLD and HOLDA Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5–18. Reset, BIO, Interrupt, and MP/MC Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5–19. Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Switching Characteristics . . . . . . 64
5–20. External Flag (XF) and TOUT Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5–21. McBSP Transmit and Receive Timing Requirements† . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
5–22. McBSP Transmit and Receive Switching Characteristics† . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5–23. McBSP General-Purpose I/O Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5–24. McBSP General-Purpose I/O Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5–25. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)† . . . . . . . . . . . 70
5–26. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)† . . . . . . . 70
ix
April 2003 – Revised July 2003
SGUS035A
Tables
5–27. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)† . . . . . . . . . . . 71
5–28. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)† . . . . . . . 71
5–29. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)† . . . . . . . . . . . 72
5–30. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)† . . . . . . . 72
5–31. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)† . . . . . . . . . . . 73
5–32. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)† . . . . . . . 73
5–33. HPI8 Mode Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
5–34. HPI8 Mode Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
5–35. HPI16 Mode Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5–36. HPI16 Mode Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
x
SGUS035A
April 2003 – Revised July 2003
Features
1
SMJ320VC5416 Features
D
D
Processed to MIL-PRF-38535 (QML)
D
D
D
D
D
D
Instructions With a 32-Bit Long Word
Operand
Advanced Multibus Architecture With Three
Separate 16-Bit Data Memory Buses and
One Program Memory Bus
Instructions With Two- or Three-Operand
Reads
D
D
40-Bit Arithmetic Logic Unit (ALU)
Including a 40-Bit Barrel Shifter and Two
Independent 40-Bit Accumulators
Arithmetic Instructions With Parallel Store
and Parallel Load
Conditional Store Instructions
Fast Return From Interrupt
17 x 17-Bit Parallel Multiplier Coupled to a
40-Bit Dedicated Adder for Non-Pipelined
Single-Cycle Multiply/Accumulate (MAC)
Operation
On-Chip Peripherals
– Software-Programmable Wait-State
Generator and Programmable
Bank-Switching
– On-Chip Programmable Phase-Locked
Loop (PLL) Clock Generator With
External Clock Source
– One 16-Bit Timer
– Six-Channel Direct Memory Access
(DMA) Controller
– Three Multichannel Buffered Serial Ports
(McBSPs)
– 8/16-Bit Enhanced Parallel Host-Port
Interface (HPI8/16)
D
D
D
Compare, Select, and Store Unit (CSSU) for
the Add/Compare Selection of the Viterbi
Operator
Exponent Encoder to Compute an
Exponent Value of a 40-Bit Accumulator
Value in a Single Cycle
Two Address Generators With Eight
Auxiliary Registers and Two Auxiliary
Register Arithmetic Units (ARAUs)
D
D
Data Bus With a Bus Holder Feature
Extended Addressing Mode for 8M x 16-Bit
Maximum Addressable External Program
Space
D
Power Consumption Control With IDLE1,
IDLE2, and IDLE3 Instructions With
Power-Down Modes
D
128K x 16-Bit On-Chip RAM Composed of:
– Eight Blocks of 8K x 16-Bit On-Chip
Dual-Access Program/Data RAM
– Eight Blocks of 8K x 16-Bit On-Chip
Single-Access Program RAM
D
D
CLKOUT Off Control to Disable CLKOUT
On-Chip Scan-Based Emulation Logic,
†
IEEE Std 1149.1 (JTAG) Boundary Scan
Logic
D
D
D
D
D
164-Pin Ceramic Quad Flatpack (CQFP)
(HFG Suffix)
D
D
D
16K x 16-Bit On-Chip ROM Configured for
Program Memory
10-ns Single-Cycle Fixed-Point Instruction
Execution Time (100 MIPS)
Enhanced External Parallel Interface (XIO2)
Single-Instruction-Repeat and
Block-Repeat Operations for Program Code
3.3-V I/O Supply Voltage
1.5-V Core Supply Voltage
D
Block-Memory-Move Instructions for Better
Program and Data Management
–55°C to 115°C Operating Temperature
Range, QML Processing
†
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
1
April 2003 – Revised July 2003
SGUS035A
Introduction
2
Introduction
This section describes the main features of the SMJ320VC5416, lists the pin assignments, and describes the
function of each pin. This data manual also provides a detailed description section, electrical specifications,
parameter measurement information, and mechanical data about the available packaging.
NOTE: This data manual is designed to be used in conjunction with the TMS320C54x DSP Functional
Overview (literature number SPRU307).
2.1 Description
The SMJ320VC5416 fixed-point, digital signal processor (DSP) (hereafter referred to as the 5416 unless
otherwise specified) is based on an advanced modified Harvard architecture that has one program memory
bus and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree
of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The
basis of the operational flexibility and speed of this DSP is a highly specialized instruction set.
Separate program and data spaces allow simultaneous access to program instructions and data, providing
a high degree of parallelism. Two read operations and one write operation can be performed in a single cycle.
Instructions with parallel store and application-specific instructions can fully utilize this architecture. In
addition, data can be transferred between data and program spaces. Such parallelism supports a powerful
set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle.
The 5416 also includes the control mechanisms to manage interrupts, repeated operations, and function calls.
2.2 Pin Assignments
Figure 2–1 provides the pin assignments for the 164-pin ceramic quad flatpack (CQFP) package.
Table 2–2 lists terminal names, terminal functions, and operating modes for the SMJ320VC5416.
2
SGUS035A
April 2003 – Revised July 2003
Introduction
†
Table 2–1. Terminal Assignments for the SMJ320VC5416HFG (164-Pin CQFP Package)
PIN NUMBER
PIN NAME
PIN NUMBER
42
PIN NAME
PIN NUMBER
83
PIN NAME
PIN NUMBER
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
PIN NAME
A19
1
V
SS
V
SS
V
SS
2
NC
A22
NC
43
BCLKR1
HCNTL0
84
BCLKX1
BFSX1
BDX1
A20
3
44
85
NC
4
45
V
SS
86
V
SS
DV
5
V
46
BCLKR0
BCLKR2
BFSR0
BFSR2
BDR0
87
DV
DD
SS
DV
DD
D6
6
47
88
CLKMD1
CLKMD2
CLKMD3
HPI16
DD
A10
7
48
89
D7
D8
8
HD7
A11
A12
A13
A14
A15
NC
49
90
9
50
91
D9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
51
HCNTL1
92
HD2
D10
D11
52
V
93
TOUT
SS
BDR2
CV
53
94
EMU0
V
SS
CV
54
95
EMU1/OFF
TDO
DD
DD
D12
55
BCLKX0
BCLKX2
NC
96
CV
DD
HAS
56
97
V
HD4
D13
D14
D15
HD5
SS
TDI
CV
57
98
V
58
V
SS
99
SS
CV
DD
59
HINT
NC
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
TRST
TCK
DD
HCS
60
HR/W
READY
PS
61
CV
TMS
V
SS
DD
62
BFSX0
BFSX2
HRDY
V
NC
SS
NC
CV
63
HDS1
CV
64
V
DD
DD
HPIENA
SS
HDS2
DV
DS
65
DV
DD
V
SS
66
V
SS
V
SS
CV
DD
A0
A1
CV
IS
R/W
67
HD0
BDX0
BDX2
DD
68
CLKOUT
HD3
X1
MSTRB
IOSTRB
MSC
69
DD
A2
70
CV
DD
IACK
71
X2/CLKIN
RS
V
SS
A3
XF
72
V
SS
HOLDA
IAQ
73
HBIL
NMI
D0
HD6
A4
A5
A6
A7
A8
A9
74
D1
HOLD
BIO
75
INT0
INT1
INT2
INT3
NC
D2
76
D3
MP/MC
77
D4
DV
78
D5
DD
NC
79
A16
V
SS
80
CV
V
SS
CV
DD
A21
DD
HD1
NC
BDR1
81
A17
A18
BFSR1
82
V
SS
is the ground for both the I/O pins and the
†
DV
is the power supply for the I/O pins while CV
DD
is the power supply for the core CPU, and V
SS
DD
core CPU.
3
April 2003 – Revised July 2003
SGUS035A
Introduction
2.2.1 Pin Assignments for the HFG Package
The SMJ320VC5416HFG 164-pin ceramic quad flatpack (CQFP) pin assignments are shown in Figure 2–1.
†‡
HFG PACKAGE
(TOP VIEW)
V
1
2
3
4
5
6
7
8
A18
A17
SS
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
NC
A22
NC
V
A16
D5
SS
V
SS
DD
D4
D3
D2
D1
D0
RS
X2/CLKIN
X1
HD3
DV
A10
HD7
A11
A12
A13
A14
A15
NC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
CV
HAS
V
CLKOUT
DD
CV
DD
V
SS
SS
CV
HPIENA
DD
HCS
HR/W
READY
PS
CV
NC
DD
V
TMS
SS
CV
TCK
TRST
DD
DS
V
CV
TDI
SS
DD
98
97
96
95
IS
R/W
MSTRB
IOSTRB
MSC
V
TDO
SS
EMU1/OFF
94
93
92
91
90
89
88
87
86
85
84
EMU0
TOUT
HD2
HPI16
CLKMD3
CLKMD2
CLKMD1
30
31
32
33
34
35
36
37
38
39
XF
HOLDA
IAQ
HOLD
BIO
MP/MC
DV
BDX1
DV
DD
DD
NC
V
BFSX1
SS
40
41
BCLKX1
BDR1
V
83
BFSR1
SS
NC – No internal connection
†
‡
NC = No connection
DV is the power supply for the I/O pins while CV
is the power supply for the core CPU, and V
DD SS
is the ground for both the I/O pins and the
DD
core CPU.
Figure 2–1. 164-Pin HFG Ceramic Quad Flatpack (Top View)
4
SGUS035A
April 2003 – Revised July 2003
Introduction
2.3 Signal Descriptions
Table 2–2 lists each signal, function, and operating mode(s) grouped by function. See Section 2.2 for exact
pin locations based on package type.
Table 2–2. Signal Descriptions
TERMINAL
NAME
†
I/O
DESCRIPTION
DATA SIGNALS
‡§
I/O/Z
A22 (MSB)
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
Parallel address bus A22 [most significant bit (MSB)] through A0 [least significant bit (LSB)]. The sixteen LSB
lines, A0 to A15, are multiplexed to address external memory (program, data) or I/O. The seven MSB lines, A16
to A22, address external program space memory. A22–A0 is placed in the high-impedance state in the hold
mode. A22–A0 also goes into the high-impedance state when OFF is low.
A17–A0areinputsinHPI16mode. Thesepinscanbeusedtoaddressinternalmemoryviathehost-portinterface
(HPI) when the HPI16 pin is high. These pins also have Schmitt trigger inputs.
The address bus has a bus holder feature that eliminates passive components and the power dissipation
associated with them. The bus holder keeps the address bus at the previous logic level when the bus goes into
a high-impedance state.
A8
A7
A6
A5
A4
A3
A2
A1
A0
(LSB)
‡§
I/O/Z
D15 (MSB)
D14
D13
D12
D11
D10
D9
Parallel data bus D15 (MSB) through D0 (LSB). D15–D0 is multiplexed to transfer data between the core CPU
and external data/program memory or I/O devices or HPI in HPI16 mode (when HPI16 pin is high). D15–D0 is
placedinthehigh-impedancestatewhennotoutputtingdataorwhenRSorHOLDisasserted.D15–D0alsogoes
into the high-impedance state when OFF is low. These pins also have Schmitt trigger inputs.
Thedata bus has a bus holder feature that eliminates passive components and the power dissipation associated
with them. The bus holder keeps the data bus at the previous logic level when the bus goes into the
high-impedance state. The bus holders on the data bus can be enabled/disabled under software control.
D8
D7
D6
D5
D4
D3
D2
D1
D0
(LSB)
†
‡
§
¶
#
I = Input, O = Output, Z = High-impedance, S = Supply
These pins have Schmitt trigger inputs.
This pin has an internal bus holder controlled by way of the BSCR register.
This pin has an internal pullup resistor.
This pin has an internal pulldown resistor.
5
April 2003 – Revised July 2003
SGUS035A
Introduction
Table 2–2. Signal Descriptions (Continued)
DESCRIPTION
TERMINAL
NAME
†
I/O
INITIALIZATION, INTERRUPT AND RESET OPERATIONS
Interrupt acknowledge signal. IACK indicates receipt of an interrupt and that the program counter is fetching the
interrupt vector location designated by A15–A0. IACK also goes into the high-impedance state when OFF is low.
IACK
O/Z
I
‡
INT0
INT1
INT2
INT3
‡
External user interrupt inputs. INT0–INT3 are maskable and are prioritized by the interrupt mask register (IMR)
and the interrupt mode bit. INT0 –INT3 can be polled and reset by way of the interrupt flag register (IFR).
‡
‡
Nonmaskableinterrupt. NMI is an external interrupt that cannot be masked by way of the INTM or the IMR. When
NMI is activated, the processor traps to the appropriate vector location.
‡
NMI
I
I
Reset. RS causes the digital signal processor (DSP) to terminate execution and forces the program counter to
0FF80h.WhenRSisbroughttoahighlevel, executionbeginsatlocation0FF80hofprogrammemory. RSaffects
various registers and status bits.
‡
RS
Microprocessor/microcomputer mode select. If active low at reset, microcomputer mode is selected, and the
internal program ROM is mapped into the upper 16K words of program memory space. If the pin is driven high
during reset, microprocessor mode is selected, and the on-chip ROM is removed from program space. This pin
is only sampled at reset, and the MP/MC bit of the processor mode status (PMST) register can override the mode
that is selected at reset.
MP/MC
I
MULTIPROCESSING SIGNALS
Branch control. A branch can be conditionally executed when BIO is active. If low, the processor executes the
conditional instruction. The BIO condition is sampled during the decode phase of the pipeline for the XC
instruction, and all other instructions sample BIO during the read phase of the pipeline.
‡
BIO
I
External flag output (latched software-programmable signal). XF is set high by the SSBX XF instruction, set low
by RSBX XF instruction or by loading ST1. XF is used for signaling other processors in multiprocessor
configurationsor used as a general-purpose output pin. XF goes into the high-impedance state when OFF is low,
and is set high at reset.
XF
O/Z
MEMORY CONTROL SIGNALS
Data, program, and I/O space select signals. DS, PS, and IS are always high unless driven low for
communicating to a particular external space. Active period corresponds to valid address information. DS, PS,
and IS are placed into the high-impedance state in the hold mode; these signals also go into the high-impedance
state when OFF is low.
DS
PS
IS
O/Z
O/Z
I
Memory strobe signal. MSTRB is always high unless low-level asserted to indicate an external bus access to
data or program memory. MSTRB is placed in the high-impedance state in the hold mode; it also goes into the
high-impedance state when OFF is low.
MSTRB
READY
R/W
Data ready. READY indicates that an external device is prepared for a bus transaction to be completed. If the
device is not ready (READY is low), the processor waits one cycle and checks READY again. Note that the
processor performs ready detection if at least two software wait states are programmed. The READY signal is
not sampled until the completion of the software wait states.
Read/write signal. R/W indicates transfer direction during communication to an external device. R/W is normally
in the read mode (high), unless it is asserted low when the DSP performs a write operation. R/W is placed in the
high-impedance state in the hold mode; and it also goes into the high-impedance state when OFF is low.
O/Z
I/O strobe signal. IOSTRB is always high unless low-level asserted to indicate an external bus access to an I/O
device. IOSTRB is placed in the high-impedance state in the hold mode; it also goes into the high-impedance
state when OFF is low.
IOSTRB
HOLD
O/Z
I
Hold input. HOLD is asserted to request control of the address, data, and control lines. When acknowledged by
the 5416, these lines go into the high-impedance state.
†
‡
§
¶
#
I = Input, O = Output, Z = High-impedance, S = Supply
These pins have Schmitt trigger inputs.
This pin has an internal bus holder controlled by way of the BSCR register.
This pin has an internal pullup resistor.
This pin has an internal pulldown resistor.
6
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April 2003 – Revised July 2003
Introduction
Table 2–2. Signal Descriptions (Continued)
DESCRIPTION
TERMINAL
NAME
†
I/O
MEMORY CONTROL SIGNALS (CONTINUED)
Hold acknowledge. HOLDA indicates to the external circuitry that the processor is in a hold state and that the
address, data, and control lines are in the high-impedance state, allowing them to be available to the external
circuitry. HOLDA also goes into the high-impedance state when OFF is low. This pin is driven high during reset.
HOLDA
O/Z
Microstate complete. MSC indicates completion of all software wait states. When two or more software wait
states are enabled, the MSC pin goes active at the beginning of the first software wait state and goes inactive
high at the beginning of the last software wait state. If connected to the READY input, MSC forces one external
wait state after the last internal wait state is completed. MSC also goes into the high-impedance state when OFF
is low.
MSC
IAQ
O/Z
O/Z
Instruction acquisition signal. IAQ is asserted (active low) when there is an instruction address on the address
bus and goes into the high-impedance state when OFF is low.
TIMER SIGNALS
Clock output signal. CLKOUT can represent the machine-cycle rate of the CPU divided by 1, 2, 3, or 4 as
configured in the bank-switching control register (BSCR). Following reset, CLKOUT represents the
machine-cycle rate divided by 4.
CLKOUT
O/Z
I
Clock mode select signals. CLKMD1–CLKMD3 allow the selection and configuration of different clock modes
such as crystal, external clock, and PLL mode. The external CLKMD1–CLKMD3 pins are sampled to determine
the desired clock generation mode while RS is low. Following reset, the clock generation mode can be
reconfigured by writing to the internal clock mode register in software.
‡
‡
‡
CLKMD1
CLKMD2
CLKMD3
Clock/oscillator input. If the internal oscillator is not being used, X2/CLKIN functions as the clock input. (This is
revision-dependent, see Section 3.10 for additional information.)
‡
X2/CLKIN
X1
I
Output pin from the internal oscillator for the crystal. If the internal oscillator is not used, X1 should be left
unconnected. X1 does not go into the high-impedance state when OFF is low. (This is revision-dependent, see
Section 3.10 for additional information.)
O
Timer output. TOUT signals a pulse when the on-chip timer counts down past zero. The pulse is one CLKOUT
cycle wide. TOUT also goes into the high-impedance state when OFF is low.
TOUT
O/Z
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP #0), MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP #1),
AND MULTICHANNEL BUFFERED SERIAL PORT 2 (McBSP #2) SIGNALS
‡
‡
‡
BCLKR0
BCLKR1
BCLKR2
Receive clock input. BCLKR can be configured as an input or an output; it is configured as an input following
reset. BCLKR serves as the serial shift clock for the buffered serial port receiver.
I/O/Z
I
BDR0
BDR1
BDR2
Serial data receive input
BFSR0
BFSR1
BFSR2
Frame synchronization pulse for receive input. BFSR can be configured as an input or an output; it is configured
as an input following reset. The BFSR pulse initiates the receive data process over BDR.
I/O/Z
I/O/Z
O/Z
I/O/Z
‡
‡
‡
BCLKX0
BCLKX1
BCLKX2
Transmit clock. BCLKX serves as the serial shift clock for the McBSP transmitter. BCLKX can be configured as
aninputoranoutput, andisconfiguredasaninputfollowingreset. BCLKXentersthehigh-impedancestatewhen
OFF goes low.
BDX0
BDX1
BDX2
Serial data transmit output. BDX is placed in the high-impedance state when not transmitting, when RS is
asserted, or when OFF is low.
BFSX0
BFSX1
BFSX2
Frame synchronization pulse for transmit input/output. The BFSX pulse initiates the data transmit process over
BDX. BFSX can be configured as an input or an output, and is configured as an input following reset. BFSX goes
into the high-impedance state when OFF is low.
†
‡
§
¶
#
I = Input, O = Output, Z = High-impedance, S = Supply
These pins have Schmitt trigger inputs.
This pin has an internal bus holder controlled by way of the BSCR register.
This pin has an internal pullup resistor.
This pin has an internal pulldown resistor.
7
April 2003 – Revised July 2003
SGUS035A
Introduction
Table 2–2. Signal Descriptions (Continued)
DESCRIPTION
TERMINAL
NAME
†
I/O
HOST-PORT INTERFACE SIGNALS
Parallel bidirectional data bus. The HPI data bus is used by a host device bus to exchange information with the
HPI registers. These pins can also be used as general-purpose I/O pins. HD0–HD7 is placed in the
high-impedance state when not outputting data or when OFF is low. The HPI data bus includes bus holders to
reduce the static power dissipation caused by floating, unused pins. When the HPI data bus is not being driven
by the 5416, the bus holders keep the pins at the previous logic level. The HPI data bus holders are disabled
at reset and can be enabled/disabled via the HBH bit of the BSCR. These pins also have Schmitt trigger inputs.
‡§
HD0–HD7
I/O/Z
¶
¶
HCNTL0
HCNTL1
Control inputs. HCNTL0 and HCNTL1 select a host access to one of the three HPI registers. The control inputs
have internal pullups that are only enabled when HPIENA = 0. These pins are not used when HPI16 = 1.
I
Byte identification. HBIL identifies the first or second byte of transfer. The HPIL input has an internal pullup
resistor that is only enabled when HPIENA = 0. This pin is not used when HPI16 = 1.
¶
HBIL
I
Chip select. HCS is the select input for the HPI and must be driven low during accesses. The chip select input
has an internal pullup resistor that is only enabled when HPIENA = 0.
‡¶
HCS
I
‡¶
‡¶
HDS1
HDS2
Data strobe. HDS1 and HDS2 are driven by the host read and write strobes to control the transfer. The strobe
inputs have internal pullup resistors that are only enabled when HPIENA = 0.
I
I
Address strobe. Host with multiplexed address and data pins requires HAS to latch the address in the HPIA
register. HAS input has an internal pullup resistor that is only enabled when HPIENA = 0.
‡¶
HAS
Read/write. HR/W controls the direction of the HPI transfer. HR/W has an internal pullup resistor that is only
enabled when HPIENA = 0.
¶
HR/W
I
Ready output. HRDY goes into the high-impedance state when OFF is low. The ready output informs the host
when the HPI is ready for the next transfer. This pin is driven high during reset.
HRDY
HINT
O/Z
O/Z
Interrupt output. This output is used to interrupt the host. When the DSP is in reset, HINT is driven high. HINT
goes into the high-impedance state when OFF is low. This pin is not used when HPI16 = 1.
HPI module select. HPIENA must be tied to DV
DD
to have HPI selected. If HPIENA is left open or connected to
ground, the HPI module is not selected, internal pullup for the HPI input pins are enabled, and the HPI data bus
has holders set. HPIENA is provided with an internal pulldown resistor that is always active. HPIENA is sampled
when RS goes high and is ignored until RS goes low again. This pin should never be changed while reset is high
#
HPIENA
I
I
#
HPI16
HPI16 mode selection
SUPPLY PINS
CV
CV
DV
DV
S
S
S
S
Ground. Dedicated ground for the core CPU
SS
+V . Dedicated power supply for the core CPU
DD
DD
SS
DD
Ground. Dedicated ground for I/O pins
+V . Dedicated power supply for I/O pins
DD
†
‡
§
¶
#
I = Input, O = Output, Z = High-impedance, S = Supply
These pins have Schmitt trigger inputs.
This pin has an internal bus holder controlled by way of the BSCR register.
This pin has an internal pullup resistor.
This pin has an internal pulldown resistor.
8
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Introduction
Table 2–2. Signal Descriptions (Continued)
TERMINAL
NAME
†
I/O
DESCRIPTION
TEST PINS
IEEE standard 1149.1 test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The changes
on test access port (TAP) of input signals TMS and TDI are clocked into the TAP controller, instruction register,
or selected test data register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur on the
falling edge of TCK.
‡¶
TCK
I
I
IEEE standard 1149.1 test data input. Pin with internal pullup device. TDI is clocked into the selected register
(instruction or data) on a rising edge of TCK.
¶
TDI
IEEE standard 1149.1 test data output. The contents of the selected register (instruction or data) are shifted out
of TDO on the falling edge of TCK. TDO is in the high-impedance state except when the scanning of data is in
progress. TDO also goes into the high-impedance state when OFF is low.
TDO
TMS
O/Z
IEEE standard 1149.1 test mode select. Pin with internal pullup device. This serial control input is clocked into
the TAP controller on the rising edge of TCK.
¶
I
I
IEEE standard 1149.1 test reset. TRST, when high, gives the IEEE standard 1149.1 scan system control of the
operations of the device. If TRST is not connected or driven low, the device operates in its functional mode, and
the IEEE standard 1149.1 signals are ignored. Pin with internal pulldown device.
#
TRST
Emulator 0 pin. When TRST is driven low, EMU0 must be high for activation of the OFF condition. When TRST
is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as input/output by way
of the IEEE standard 1149.1 scan system.
EMU0
I/O/Z
Emulator 1 pin/disable all outputs. When TRST is driven high, EMU1/OFF is used as an interrupt to or from the
emulator system and is defined as input/output by way of IEEE standard 1149.1 scan system. When TRST is
driven low, EMU1/OFF is configured as OFF. The EMU1/OFF signal, when active low, puts all output drivers into
the high-impedance state. Note that OFF is used exclusively for testing and emulation purposes (not for
multiprocessing applications). Therefore, for the OFF condition, the following apply:
TRST = low,
EMU1/OFF
I/O/Z
EMU0 = high
EMU1/OFF = low
†
‡
§
¶
#
I = Input, O = Output, Z = High-impedance, S = Supply
These pins have Schmitt trigger inputs.
This pin has an internal bus holder controlled by way of the BSCR register.
This pin has an internal pullup resistor.
This pin has an internal pulldown resistor.
9
April 2003 – Revised July 2003
SGUS035A
Functional Overview
3
Functional Overview
The following functional overview is based on the block diagram in Figure 3–1.
P, C, D, E Buses and Control Signals
64K RAM
Dual Access
Program/Data
64K RAM
Single Access
Program
16K Program
ROM
54X cLEAD
MBus
GPIO
RHEA
Bridge
TI BUS
RHEA Bus
McBSP1
XIO
Enhanced XIO
McBSP2
McBSP3
16HPI
16 HPI
xDMA
logic
RHEAbus
TIMER
APLL
JTAG
Clocks
Figure 3–1. SMJ320VC5416 Functional Block Diagram
3.1 Memory
The 5416 device provides both on-chip ROM and RAM memories to aid in system performance and
integration.
3.1.1 Data Memory
The data memory space addresses up to 64K of 16-bit words. The device automatically accesses the on-chip
RAM when addressing within its bounds. When an address is generated outside the RAM bounds, the device
automatically generates an external access.
The advantages of operating from on-chip memory are as follows:
•
•
•
•
Higher performance because no wait states are required
Higher performance because of better flow within the pipeline of the central arithmetic logic unit (CALU)
Lower cost than external memory
Lower power than external memory
The advantage of operating from off-chip memory is the ability to access a larger address space.
10
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April 2003 – Revised July 2003
Functional Overview
3.1.2 Program Memory
Software can configure their memory cells to reside inside or outside of the program address map. When the
cells are mapped into program space, the device automatically accesses them when their addresses are
within bounds. When the program-address generation (PAGEN) logic generates an address outside its
bounds, the device automatically generates an external access. The advantages of operating from on-chip
memory are as follows:
•
•
•
Higher performance because no wait states are required
Lower cost than external memory
Lower power than external memory
The advantage of operating from off-chip memory is the ability to access a larger address space.
3.1.3 Extended Program Memory
The 5416 uses a paged extended memory scheme in program space to allow access of up to 8192K of
program memory. In order to implement this scheme, the 5416 includes several features which are also
present on C548/549/5410:
•
•
•
Twenty-three address lines, instead of sixteen
An extra memory-mapped register, the XPC
Six extra instructions for addressing extended program space
Program memory in the 5416 is organized into 128 pages that are each 64K in length.
The value of the XPC register defines the page selection. This register is memory-mapped into data space
to address 001Eh. At a hardware reset, the XPC is initialized to 0.
3.2 On-Chip ROM With Bootloader
The 5416 features a 16K-word× 16-bit on-chip maskable ROM that can only be mapped into program memory
space.
Customers can arrange to have the ROM of the 5416 programmed with contents unique to any particular
application.
A bootloader is available in the standard 5416 on-chip ROM. This bootloader can be used to automatically
transfer user code from an external source to anywhere in the program memory at power up. If MP/MC of the
device is sampled low during a hardware reset, execution begins at location FF80h of the on-chip ROM. This
location contains a branch instruction to the start of the bootloader program.
The standard 5416 devices provide different ways to download the code to accommodate various system
requirements:
•
•
•
•
•
Parallel from 8-bit or 16-bit-wide EPROM
Parallel from I/O space, 8-bit or 16-bit mode
Serial boot from serial ports, 8-bit or 16-bit mode
Host-port interface boot
Warm boot
11
April 2003 – Revised July 2003
SGUS035A
Functional Overview
The standard on-chip ROM layout is shown in Table 3–1.
Table 3–1. Standard On-Chip ROM Layout
†
ADDRESS RANGE
C000h–D4FFh
D500h–F7FFh
F800h–FBFFh
FC00h–FCFFh
FD00h–FDFFh
FE00h–FEFFh
FF00h–FF7Fh
FF80h–FFFFh
DESCRIPTION
ROM tables for the GSM EFR speech codec
Reserved
Bootloader
µ-Law expansion table
A-Law expansion table
Sine look-up table
†
Reserved
Interrupt vector table
†
In the 5416 ROM, 128 words are reserved for factory device-testing purposes. Application code
to be implemented in on-chip ROM must reserve these 128 words at addresses FF00h–FF7Fh
in program space.
3.3 On-Chip RAM
The 5416 device contains 64K-word × 16-bit of on-chip dual-access RAM (DARAM) and 64K-word × 16-bit
of on-chip single-access RAM (SARAM).
The DARAM is composed of eight blocks of 8K words each. Each block in the DARAM can support two reads
in one cycle, or a read and a write in one cycle. Four blocks of DARAM are located in the address range
0080h–7FFFh in data space, and can be mapped into program/data space by setting the OVLY bit to one. The
otherfourblocksofDARAMarelocatedintheaddressrange18000h–1FFFFhinprogramspace. TheDARAM
located in the address range 18000h–1FFFFh in program space can be mapped into data space by setting
the DROM bit to one.
The SARAM is composed of eight blocks of 8K words each. Each of these eight blocks is a single-access
memory. For example, an instruction word can be fetched from one SARAM block in the same cycle as a data
word is written to another SARAM block. The SARAM is located in the address range 28000h–2FFFFh, and
38000h–3FFFFh in program space.
3.4 On-Chip Memory Security
The 5416 device has a maskable option to protect the contents of on-chip memories. When the ROM protect
bit is set, no externally originating instruction can access the on-chip memory spaces; HPI writes have no
restriction, but HPI reads are restricted to 4000h – 5FFFh.
12
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Functional Overview
3.5 Memory Map
Page 0 Program
Page 0 Program
Data
Hex
Hex
Hex
0000
0000
0000
Reserved
(OVLY = 1)
External
(OVLY = 0)
Reserved
(OVLY = 1)
External
(OVLY = 0)
Memory-Mapped
Registers
005F
007F
0080
007F
0080
0060
007F
0080
Scratch-Pad
RAM
On-Chip
DARAM0–3
(OVLY = 1)
External
(OVLY = 0)
On-Chip
DARAM0–3
(OVLY = 1)
External
(OVLY = 0)
On-Chip
DARAM0–3
(32K x 16-bit)
7FFF
8000
BFFF
C000
7FFF
8000
7FFF
8000
External
External
On-Chip
DARAM4–7
(DROM=1)
or
External
(DROM=0)
On-Chip ROM
(4K x 16-bit)
FF7F
FF80
FEFF
FF00
FF7F
FF80
FFFF
Interrupts
(External)
Reserved
Interrupts
(On-Chip)
FFFF
FFFF
MP/MC= 1
(Microprocessor Mode)
MP/MC= 0
(Microcomputer Mode)
Address ranges for on-chip DARAM in data memory are:
DARAM0: 0080h–1FFFh;
DARAM1: 2000h–3FFFh
DARAM2: 4000h–5FFFh;
DARAM4: 8000h–9FFFh;
DARAM6: C000h–DFFFh;
DARAM3: 6000h–7FFFh
DARAM5: A000h–BFFFh
DARAM7: E000h–FFFFh
Figure 3–2. Program and Data Memory Map
Hex
7F0000
Hex
010000
Program
Program
Hex
020000
Hex
030000
Hex
040000
Program
Program
Program
On-Chip
DARAM0–3
(OVLY=1)
External
On-Chip
DARAM0–3
(OVLY=1)
External
On-Chip
DARAM0–3
(OVLY=1)
External
On-Chip
DARAM0–3
(OVLY=1)
External
On-Chip
DARAM0–3
(OVLY=1)
External
(OVLY=0)
(OVLY=0)
(OVLY=0)
(OVLY=0)
(OVLY=0)
7F7FFF
7F8000
017FFF
018000
027FFF
028000
037FFF
038000
047FFF
048000
......
On-Chip
DARAM4–7
(MP/MC=0)
External
On-Chip
SARAM0–3
(MP/MC=0)
External
On-Chip
SARAM4–7
(MP/MC=0)
External
External
External
(MP/MC=1)
(MP/MC=1)
(MP/MC=1)
7FFFFF
01FFFF
02FFFF
03FFFF
04FFFF
Page 1
XPC=1
Page 2
XPC=2
Page 127
XPC=7Fh
Page 3
XPC=3
Page 4
XPC=4
Address ranges for on-chip DARAM in program memory are:
DARAM4: 018000h–019FFFh;
DARAM6: 01C000h–01DFFFh;
SARAM0: 028000h–029FFFh;
SARAM2: 02C000h–02DFFFh;
SARAM4: 038000h–039FFFh;
SARAM6: 03C000h–03DFFFh;
DARAM5: 01A000h–01BFFFh
DARAM7: 01E000h–01FFFFh
SARAM1: 02A000h–02BFFFh
SARAM3: 02E000h–02FFFFh
SARAM5: 03A000h–03BFFFh
SARAM7: 03E000h–03FFFFh
Address ranges for on-chip SARAM in program memory are:
Figure 3–3. Extended Program Memory Map
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Functional Overview
3.5.1 Relocatable Interrupt Vector Table
The reset, interrupt, and trap vectors are addressed in program space. These vectors are soft — meaning that
the processor, when taking the trap, loads the program counter (PC) with the trap address and executes the
code at the vector location. Four words, either two 1-word instructions or one 2-word instruction, are reserved
at each vector location to accommodate a delayed branch instruction which allows branching to the
appropriate interrupt service routine without the overhead.
At device reset, the reset, interrupt, and trap vectors are mapped to address FF80h in program space.
However, these vectors can be remapped to the beginning of any 128-word page in program space after
device reset. This is done by loading the interrupt vector pointer (IPTR) bits in the PMST register with the
appropriate 128-word page boundary address. After loading IPTR, any user interrupt or trap vector is mapped
to the new 128-word page.
NOTE: The hardware reset (RS) vector cannot be remapped because the hardware reset loads the IPTR
with 1s. Therefore, the reset vector is always fetched at location FF80h in program space.
15
7
6
5
4
3
2
1
0
CLK
OFF
IPTR
MP/MC
OVLY
AVIS
DROM
SMUL
SST
R/W-1FF
MP/MC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
Pin
LEGEND: R = Read, W = Write
Figure 3–4. Processor Mode Status (PMST) Register
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Functional Overview
Table 3–2. Processor Mode Status (PMST) Register Bit Fields
BIT
RESET
VALUE
FUNCTION
NO.
NAME
Interrupt vector pointer. The 9-bit IPTR field points to the 128-word program page where the interrupt
vectors reside. The interrupt vectors can be remapped to RAM for boot-loaded operations. At reset, these
bits are all set to 1; the reset vector always resides at address FF80h in program memory space. The
RESET instruction does not affect this field.
15–7
IPTR
1FFh
Microprocessor/microcomputer mode. MP/MC enables/disables the on-chip ROM to be addressable in
program memory space.
-
-
MP/MC = 0: The on-chip ROM is enabled and addressable.
MP/MC = 1: The on-chip ROM is not available.
MP/MC
pin
6
5
MP/MC
MP/MC is set to the value corresponding to the logic level on the MP/MC pin when sampled at reset. This
pin is not sampled again until the next reset. The RESET instruction does not affect this bit. This bit can
also be set or cleared by software.
RAM overlay. OVLY enables on-chip dual-access data RAM blocks to be mapped into program space.
The values for the OVLY bit are:
-
-
OVLY = 0: The on-chip RAM is addressable in data space but not in program space.
OVLY
0
OVLY = 1: The on-chip RAM is mapped into program space and data space. Data page 0 (addresses
0h to 7Fh), however, is not mapped into program space.
Address visibility mode. AVIS enables/disables the internal program address to be visible at the
address pins.
-
-
AVIS = 0: The external address lines do not change with the internal program address. Control and
data lines are not affected and the address bus is driven with the last address on the bus.
4
3
AVIS
0
0
AVIS = 1: This mode allows the internal program address to appear at the pins of the 5416 so that
the internal program address can be traced. Also, it allows the interrupt vector to be decoded in
conjunction with IACK when the interrupt vectors reside on on-chip memory.
DROM enables on-chip DARAM4–7 to be mapped into data space. The DROM bit values are:
-
-
DROM = 0: The on-chip DARAM4–7 is not mapped into data space.
DROM = 1: The on-chip DARAM4–7 is mapped into data space.
DROM
CLOCKOUT off. When the CLKOFF bit is 1, the output of CLKOUT is disabled and remains at a high
level.
2
1
0
CLKOFF
SMUL
SST
0
Saturation on multiplication. When SMUL = 1, saturation of a multiplication result occurs before
performing the accumulation in a MAC of MAS instruction. The SMUL bit applies only when OVM = 1
and FRCT = 1.
N/A
N/A
Saturation on store. When SST = 1, saturation of the data from the accumulator is enabled before
storing in memory. The saturation is performed after the shift operation.
3.6 On-Chip Peripherals
The 5416 device has the following peripherals:
•
•
•
•
•
•
•
•
Software-programmable wait-state generator
Programmable bank-switching
A host-port interface (HPI8/16)
Three multichannel buffered serial ports (McBSPs)
A hardware timer
A clock generator with a multiple phase-locked loop (PLL)
Enhanced external parallel interface (XIO2)
A DMA controller (DMA)
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Functional Overview
3.6.1 Software-Programmable Wait-State Generator
The software wait-state generator of the 5416 can extend external bus cycles by up to fourteen machine
cycles. Devices that require more than fourteen wait states can be interfaced using the hardware READY line.
When all external accesses are configured for zero wait states, the internal clocks to the wait-state generator
are automatically disabled. Disabling the wait-state generator clocks reduces the power consumption of
the 5416.
The software wait-state register (SWWSR) controls the operation of the wait-state generator. The 14 LSBs
of the SWWSR specify the number of wait states (0 to 7) to be inserted for external memory accesses to five
separate address ranges. This allows a different number of wait states for each of the five address ranges.
Additionally, the software wait-state multiplier (SWSM) bit of the software wait-state control register (SWCR)
defines a multiplication factor of 1 or 2 for the number of wait states. At reset, the wait-state generator is
initialized to provide seven wait states on all external memory accesses. The SWWSR bit fields are shown
in Figure 3–5 and described in Table 3–3.
15
14
12
11
9
8
6
5
3
2
0
XPA
I/O
Data
Data
Program
R/W-111
Program
R/W-111
R/W-0
R/W-111
R/W-111
R/W-111
LEGEND: R=Read, W=Write, 0=Value after reset
Figure 3–5. Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h]
Table 3–3. Software Wait-State Register (SWWSR) Bit Fields
BIT
RESET
VALUE
FUNCTION
NO.
NAME
Extended program address control bit. XPA is used in conjunction with the program space fields
(bits 0 through 5) to select the address range for program space wait states.
15
XPA
0
I/O space. The field value (0–7) corresponds to the base number of wait states for I/O space accesses
within addresses 0000–FFFFh. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for
the base number of wait states.
14–12
11–9
8–6
I/O
111
Upper data space. The field value (0–7) corresponds to the base number of wait states for external
data space accesses within addresses 8000–FFFFh. The SWSM bit of the SWCR defines a
multiplication factor of 1 or 2 for the base number of wait states.
Data
Data
111
111
Lower data space. The field value (0–7) corresponds to the base number of wait states for external
data space accesses within addresses 0000–7FFFh. The SWSM bit of the SWCR defines a
multiplication factor of 1 or 2 for the base number of wait states.
Upper program space. The field value (0–7) corresponds to the base number of wait states for external
program space accesses within the following addresses:
-
-
XPA = 0: xx8000 – xxFFFFh
XPA = 1: 400000h – 7FFFFFh
5–3
2–0
Program
Program
111
111
The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.
Program space. The field value (0–7) corresponds to the base number of wait states for external
program space accesses within the following addresses:
-
-
XPA = 0: xx0000 – xx7FFFh
XPA = 1: 000000 – 3FFFFFh
The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.
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Functional Overview
The software wait-state multiplier bit of the software wait-state control register (SWCR) is used to extend the
base number of wait states selected by the SWWSR. The SWCR bit fields are shown in Figure 3–6 and
described in Table 3–4.
15
1
0
Reserved
R/W-0
SWSM
R/W-0
LEGEND: R = Read, W = Write
Figure 3–6. Software Wait-State Control Register (SWCR) [MMR Address 002Bh]
Table 3–4. Software Wait-State Control Register (SWCR) Bit Fields
PIN
RESET
VALUE
FUNCTION
NO.
NAME
15–1
Reserved
0
These bits are reserved and are unaffected by writes.
Softwarewait-statemultiplier. UsedtomultiplythenumberofwaitstatesdefinedintheSWWSRbyafactor
of 1 or 2.
0
SWSM
0
-
-
SWSM = 0: wait-state base values are unchanged (multiplied by 1).
SWSM = 1: wait-state base values are multiplied by 2 for a maximum of 14 wait states.
3.6.2 Programmable Bank-Switching
Programmable bank-switching logic allows the 5416 to switch between external memory banks without
requiring external wait states for memories that need additional time to turn off. The bank-switching logic
automatically inserts one cycle when accesses cross a 32K-word memory-bank boundary inside program or
data space.
Bank-switching is defined by the bank-switching control register (BSCR), which is memory-mapped at
address 0029h. The bit fields of the BSCR are shown in Figure 3–7 and are described in Table 3–5.
R = Read, W = Write
15
14
DIVFCT
R/W-11
13
12
11
2
1
0
Res
R
CONSEC
R/W-1
IACKOFF
R/W-1
Reserved
R
HBH
BH
R/W-0 R/W-0
Figure 3–7. Bank-Switching Control Register (BSCR) [MMR Address 0029h]
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Functional Overview
Table 3–5. Bank-Switching Control Register (BSCR) Fields
RESET
VALUE
BIT
NAME
FUNCTION
Consecutive bank-switching. Specifies the bank-switching mode.
Bank-switching on 32K bank boundaries only. This bit is cleared if fast access is desired for
continuous memory reads (i.e., no starting and trailing cycles between read cycles).
CONSEC = 0:
CONSEC = 1:
†
15
CONSEC
1
Consecutivebank switches on external memory reads. Each read cycle consists of 3 cycles:
starting cycle, read cycle, and trailing cycle.
CLKOUT output divide factor. The CLKOUT output is driven by an on-chip source having a frequency
equal to 1/(DIVFCT+1) of the DSP clock.
DIVFCT = 00: CLKOUT is not divided.
13–14 DIVFCT
11
DIVFCT = 01: CLKOUT is divided by 2 from the DSP clock.
DIVFCT = 10: CLKOUT is divided by 3 from the DSP clock.
DIVFCT = 11: CLKOUT is divided by 4 from the DSP clock (default value following reset).
IACK signal output off. Controls the output of the IACK signal. IACKOFF is set to 1 at reset.
IACKOFF = 0: The IACK signal output off function is disabled.
IACKOFF = 1: The IACK signal output off function is enabled.
Reserved
12
IACKOFF
1
11–3
Rsvd
HBH
–
HPI bus holder. Controls the HPI bus holder. HBH is cleared to 0 at reset.
HBH = 0:
The bus holder is disabled except when HPI16 = 1.
2
0
Thebus holder is enabled. When not driven, the HPI data bus, HD[7:0] is held in the previous
logic level.
HBH = 1:
Bus holder. Controls the bus holder. BH is cleared to 0 at reset.
BH = 0:
BH = 1:
Reserved
The bus holder is disabled.
1
0
BH
0
Thebusholderisenabled. Whennotdriven, thedatabus, D[15:0]isheldinthepreviouslogic
level.
Rsvd
–
†
For additional information, see Section 3.11 of this document.
The 5416 has an internal register that holds the MSB of the last address used for a read or write operation
in program or data space. In the non-consecutive bank switches (CONSEC = 0), if the MSB of the address
used for the current read does not match that contained in this internal register, the MSTRB (memory strobe)
signal is not asserted for one CLKOUT cycle. During this extra cycle, the address bus switches to the new
address. The contents of the internal register are replaced with the MSB for the read of the current address.
If the MSB of the address used for the current read matches the bits in the register, a normal read cycle occurs.
In non-consecutive bank switches (CONSEC = 0), if repeated reads are performed from the same memory
bank, no extra cycles are inserted. When a read is performed from a different memory bank, memory conflicts
are avoided by inserting an extra cycle. For more information, see Section 3.11 of this document.
The bank-switching mechanism automatically inserts one extra cycle in the following cases:
•
•
•
•
A memory read followed by another memory read from a different memory bank.
A program-memory read followed by a data-memory read.
A data-memory read followed by a program-memory read.
A program-memory read followed by another program-memory read from a different page.
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Functional Overview
3.6.3 Bus Holders
The 5416 has two bus holder control bits, BH (BSCR[1]) and HBH (BSCR[2]), to control the bus keepers of
theaddressbus(A[17–0]), databus(D[15–0]), andtheHPIdatabus(HD[7–0]). Buskeeperenabling/disabling
is described in Table 3–5.
Table 3–6. Bus Holder Control Bits
HPI16 PIN
BH
0
HBH
D[15–0]
OFF
OFF
ON
A[17–0]
OFF
OFF
OFF
OFF
OFF
ON
HD[7–0]
OFF
ON
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
OFF
ON
1
ON
0
OFF
OFF
ON
ON
0
ON
1
OFF
ON
ON
1
ON
ON
3.7 Parallel I/O Ports
The 5416 has a total of 64K I/O ports. These ports can be addressed by the PORTR instruction or the PORTW
instruction. The IS signal indicates a read/write operation through an I/O port. The 5416 can interface easily
with external devices through the I/O ports while requiring minimal off-chip address-decoding circuits.
3.7.1 Enhanced 8-/16-Bit Host-Port Interface (HPI8/16)
The 5416 host-port interface, also referred to as the HPI8/16, is an enhanced version of the standard 8-bit HPI
found on earlier TMS320C54x DSPs (542, 545, 548, and 549). The 5416 HPI can be used to interface to
an 8-bit or 16-bit host. When the address and data buses for external I/O is not used (to interface to external
devices in program/data/IO spaces), the 5416 HPI can be configured as an HPI16 to interface to a 16-bit host.
This configuration can be accomplished by connecting the HPI16 pin to logic “1”.
When the HPI16 pin is connected to a logic “0”, the 5416 HPI is configured as an HPI8. The HPI8 is an 8-bit
parallel port for interprocessor communication. The features of the HPI8 include:
Standard features:
•
•
•
Sequential transfers (with autoincrement) or random-access transfers
Host interrupt and C54x interrupt capability
Multiple data strobes and control pins for interface flexibility
The HPI8 interface consists of an 8-bit bidirectional data bus and various control signals. Sixteen-bit transfers
are accomplished in two parts with the HBIL input designating high or low byte. The host communicates with
the HPI8 through three dedicated registers — the HPI address register (HPIA), the HPI data register (HPID),
and the HPI control register (HPIC). The HPIA and HPID registers are only accessible by the host, and the
HPIC register is accessible by both the host and the 5416.
Enhanced features:
•
•
Access to entire on-chip RAM through DMA bus
Capability to continue transferring during emulation stop
TMS320C54x and C54x are trademarks of Texas Instruments.
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April 2003 – Revised July 2003
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Functional Overview
The HPI16 is an enhanced 16-bit version of the TMS320C54x DSP 8-bit host-port interface (HPI8). The
HPI16 is designed to allow a 16-bit host to access the DSP on-chip memory, with the host acting as the master
of the interface. Some of the features of the HPI16 include:
•
•
•
•
16-bit bidirectional data bus
Multiple data strobes and control signals to allow glueless interfacing to a variety of hosts
Only nonmultiplexed address/data modes are supported
18-bit address bus used in nonmultiplexed mode to allow access to all internal memory (including internal
extended address pages)
•
•
HRDY signal to hold off host accesses due to DMA latency
The HPI16 acts as a slave to a 16-bit host processor and allows access to the on-chip memory of the DSP.
NOTE: Only the nonmultiplexed mode is supported when the 5416 HPI is configured as a
HPI16 (see Figure 3–8).
The 5416 HPI functions as a slave and enables the host processor to access the on-chip memory. A major
enhancement to the 5416 HPI over previous versions is that it allows host access to the entire on-chip memory
range of the DSP. The host and the DSP both have access to the on-chip RAM at all times and host accesses
are always synchronized to the DSP clock. If the host and the DSP contend for access to the same location,
the host has priority, and the DSP waits for one cycle. Note that since host accesses are always synchronized
to the 5416 clock, an active input clock (CLKIN) is required for HPI accesses during IDLE states, and host
accesses are not allowed while the 5416 reset pin is asserted.
3.7.2 HPI Nonmultiplexed Mode
In nonmultiplexed mode, a host with separate address/data buses can access the HPI16 data register (HPID)
via the HD 16-bit bidirectional data bus, and the address register (HPIA) via the 18-bit HA address bus. The
host initiates the access with the strobe signals (HDS1, HDS2, HCS) and controls the direction of the access
with the HR/W signal. The HPI16 can stall host accesses via the HRDY signal. Note that the HPIC register
is not available in nonmultiplexed mode since there are no HCNTL signals available. All host accesses initiate
a DMA read or write access. Figure 3–8 shows a block diagram of the HPI16 in nonmultiplexed mode.
HOST
HPI16
PPD[15:0]
DATA[15:0]
HPID[15:0]
HINT
DMA
Address[17:0]
HCNTL0
V
CC
HCNTL1
HBIL
HAS
R/W
HR/W
54xx
CPU
Data Strobes
HDS1, HDS2, HCS
HRDY
READY
Figure 3–8. Host-Port Interface — Nonmultiplexed Mode
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Functional Overview
Address (Hex)
000 0000
Reserved
000 005F
000 0060
Scratch-Pad
RAM
000 007F
000 0080
DARAM0 –
DARAM3
000 7FFF
000 8000
Reserved
001 7FFF
001 8000
DARAM4 –
DARAM7
001 FFFF
002 0000
Reserved
002 7FFF
002 8000
SARAM0 –
SARAM3
002 FFFF
003 0000
Reserved
003 7FFF
003 8000
SARAM4 –
SARAM7
003 FFFF
004 0000
Reserved
07F FFFF
Figure 3–9. HPI Memory Map
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Functional Overview
3.8 Multichannel Buffered Serial Ports (McBSPs)
The 5416 device provides three high-speed, full-duplex, multichannel buffered serial ports that allow direct
interface to other C54x/LC54x devices, codecs, and other devices in a system. The McBSPs are based on
the standard serial-port interface found on other 54x devices. Like their predecessors, the McBSPs provide:
•
•
•
Full-duplex communication
Double-buffer data registers, which allow a continuous data stream
Independent framing and clocking for receive and transmit
In addition, the McBSPs have the following capabilities:
•
Direct interface to:
–
–
–
–
–
–
T1/E1 framers
MVIP switching compatible and ST-BUS compliant devices
IOM-2 compliant devices
AC97-compliant devices
IIS-compliant devices
Serial peripheral interface
•
•
•
•
•
Multichannel transmit and receive of up to 128 channels
A wide selection of data sizes, including 8, 12, 16, 20, 24, or 32 bits
µ-law and A-law companding
Programmable polarity for both frame synchronization and data clocks
Programmable internal clock and frame generation
The McBSP consists of a data path and control path. The six pins, BDX, BDR, BFSX, BFSR, BCLKX, and
BCLKR, connect the control and data paths to external devices. The implemented pins can be programmed
as general-purpose I/O pins if they are not used for serial communication.
The data is communicated to devices interfacing to the McBSP by way of the data transmit (BDX) pin for
transmit and the data receive (BDR) pin for receive. The CPU or DMA reads the received data from the data
receive register (DRR) and writes the data to be transmitted to the data transmit register (DXR). Data written
to the DXR is shifted out to BDX by way of the transmit shift register (XSR). Similarly, receive data on the BDR
pin is shifted into the receive shift register (RSR) and copied into the receive buffer register (RBR). RBR is then
copied to DRR, which can be read by the CPU or DMA. This allows internal data movement and external data
communications simultaneously.
Control information in the form of clocking and frame synchronization is communicated by way of BCLKX,
BCLKR, BFSX, and BFSR. The device communicates to the McBSP by way of 16-bit-wide control registers
accessible via the internal peripheral bus.
The control block consists of internal clock generation, frame synchronization signal generation, and their
control, and multichannel selection. This control block sends notification of important events to the CPU and
DMA by way of two interrupt signals, XINT and RINT, and two event signals, XEVT and REVT.
The on-chip companding hardware allows compression and expansion of data in either µ-law or A-law format.
When companding is used, transmitted data is encoded according to the specified companding law and
received data is decoded to 2s complement format.
The sample rate generator provides the McBSP with several means of selecting clocking and framing for both
the receiver and transmitter. Both the receiver and transmitter can select clocking and framing independently.
The McBSP allows the multiple channels to be independently selected for the transmitter and receiver. When
multiplechannelsareselected, eachframerepresentsatime-divisionmultiplexed(TDM)datastream. Inusing
time-division multiplexed data streams, the CPU may only need to process a few of them. Thus, to save
memory and bus bandwidth, multichannel selection allows independent enabling of particular channels for
transmission and reception. All 128 channels in a bit stream consisting of a maximum of 128 channels can
be enabled.
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Functional Overview
15
15
10
10
9
8
7
6
5
4
2
1
0
Reserved
R
XMCME
R/W
XPBBLK
R/W
XPABLK
R/W
XCBLK
R
XMCM
R/W
9
8
7
6
5
4
2
1
0
Reserved
R
RMCME
R/W
RPBBLK
R/W
RPABLK
R/W
RCBLK
R
Resvd RMCM
R/W
R
LEGEND: R = Read, W = Write
Figure 3–10. Multichannel Control Registers (MCR1 and MCR2)
The 5416 McBSP has two working modes:
•
•
In the first mode, when (R/X)MCME = 0, it is comparable with the McBSPs used in the 5410 where the
normal 32-channel selection is enabled (default).
In the second mode, when (R/X)MCME = 1, it has 128-channel selection capability. Multichannel control
register Bit 9, (R/X)MCME, is used as the 128-channel selection enable bit. Once (R/X)MCME = 1, twelve
new registers ((R/X)CERC – (R/X)CERH) are used to enable the 128-channel selection.
The clock stop mode (CLKSTP) in the McBSP provides compatibility with the serial port interface protocol.
Clock stop mode works with only single-phase frames and one word per frame. The word sizes supported by
the McBSP are programmable for 8-, 12-, 16-, 20-, 24-, or 32-bit operation. When the McBSP is configured
to operate in SPI mode, both the transmitter and the receiver operate together as a master or as a slave.
Although the BCLKS pin is not available on the 5416 HFG package, the 5416 is capable of synchronization
to external clock sources. BCLKX or BCLKR can be used by the sample rate generator for external
synchronization. The sample rate clock mode extended (SCLKME) bit field is located in the PCR to
accommodate this option.
15
14
13
XIOEN
RW
12
RIOEN
RW
11
10
FSRM
RW
9
8
Reserved
RW
FSXM
RW
CLKXM
RW
CLKRM
RW
7
6
5
4
3
2
1
0
SCLKME
RW
CLKS STAT
RW
DX STAT
RW
DR STAT
RW
FSXP
RW
FSRP
RW
CLKXP
RW
CLKRP
RW
Legend: R = Read, W = Write
Figure 3–11. Pin Control Register (PCR)
The selection of sample rate input clock is made by the combination of the CLKSM (bit 13 in SRGR2) bit value
and the SCLKME bit value as shown in Table 3–7.
Table 3–7. Sample Rate Input Clock Selection
SCLKME
CLKSM
SAMPLE RATE CLOCK MODE
0
0
Reserved (CLKS pin unavailable)
0
1
1
1
0
1
CPU clock
BCLKR
BCLKX
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Functional Overview
When the SCLKME bit is cleared to 0, the CLKSM bit is used, as before, to select either the CPU clock or the
CLKS pin (not bonded out on the 5416 device package) as the sample rate input clock. Setting the SCLKME
bit to 1 enables the CLKSM bit to select between the BCLKR pin or BCLKX pin for the sample rate input clock.
When either the BCLKR or CLKX is configured this way, the output buffer for the selected pin is automatically
disabled. For example, with SCLKME = 1 and CLKSM = 0, the BCLKR pin is configured as the input of the
sample rate generator. Both the transmitter and receiver circuits can be synchronized to the sample rate
generator output by setting the CLKXM and CLKRM bits of the pin configuration register (PCR) to 1. Note that
the sample rate generator output will only be driven on the BCLKX pin since the BCLKR output buffer is
automatically disabled.
The McBSP is fully static and operates at arbitrary low clock frequencies. For maximum operating frequency,
see Section 5.14.
3.9 Hardware Timer
The 5416 device features a 16-bit timing circuit with a 4-bit prescaler. The timer counter is decremented by
one every CLKOUT cycle. Each time the counter decrements to 0, a timer interrupt is generated. The timer
can be stopped, restarted, reset, or disabled by specific status bits.
3.10 Clock Generator
The clock generator provides clocks to the 5416 device, and consists of a phase-locked loop (PLL) circuit. The
clock generator requires a reference clock input, which can be provided from an external clock source. The
reference clock input is then divided by two (DIV mode) to generate clocks for the 5416 device, or the PLL
circuit can be used (PLL mode) to generate the device clock by multiplying the reference clock frequency by
a scale factor, allowing use of a clock source with a lower frequency than that of the CPU. The PLL is an
adaptive circuit that, once synchronized, locks onto and tracks an input clock signal.
When the PLL is initially started, it enters a transitional mode during which the PLL acquires lock with the input
signal. Once the PLL is locked, it continues to track and maintain synchronization with the input signal. Then,
other internal clock circuitry allows the synthesis of new clock frequencies for use as master clock for the 5416
device.
This clock generator allows system designers to select the clock source. The sources that drive the clock
generator are:
•
A crystal resonator circuit. The crystal resonator circuit is connected across the X1 and X2/CLKIN pins
of the 5416 to enable the internal oscillator.
•
An external clock. The external clock source is directly connected to the X2/CLKIN pin, and X1 is left
unconnected.
NOTE: The crystal oscillator function is not supported by all die revisions of the 5416 device.
See the TMS320VC5416 Silicon Errata (literature number SPRZ172) to verify which die
revisions support this functionality.
The software-programmable PLL features a high level of flexibility, and includes a clock scaler that provides
various clock multiplier ratios, capability to directly enable and disable the PLL, and a PLL lock timer that can
be used to delay switching to PLL clocking mode of the device until lock is achieved. Devices that have a
built-in software-programmable PLL can be configured in one of two clock modes:
•
•
PLL mode. The input clock (X2/CLKIN) is multiplied by 1 of 31 possible ratios.
DIV (divider) mode. The input clock is divided by 2 or 4. Note that when DIV mode is used, the PLL can
be completely disabled in order to minimize power dissipation.
The software-programmable PLL is controlled using the 16-bit memory-mapped (address 0058h) clock mode
register (CLKMD). The CLKMD register is used to define the clock configuration of the PLL clock module. Note
that upon reset, the CLKMD register is initialized with a predetermined value dependent only upon the state
of the CLKMD1 – CLKMD3 pins. For more programming information, see the TMS320C54x DSP Reference
Set, Volume 1: CPU and Peripherals (literature number SPRU131). The CLKMD pin configured clock options
are shown in Table 3–8.
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Functional Overview
Table 3–8. Clock Mode Settings at Reset
CLKMD RESET
†
CLOCK MODE
CLKMD1
CLKMD2
CLKMD3
VALUE
0000h
9007h
4007h
1007h
F007h
0000h
F000h
—
0
0
0
1
1
1
1
0
0
0
1
0
1
1
0
1
0
1
0
0
0
1
1
1
1/2 (PLL disabled)
PLL x 10
PLL x 5
PLL x 2
PLL x 1
1/2 (PLL disabled)
1/4 (PLL disabled)
Reserved (Bypass mode)
†
The external CLKMD1–CLKMD3 pins are sampled to determine the desired clock generation mode
whileRSislow. Followingreset, theclockgenerationmodecanbereconfiguredbywritingtotheinternal
clock mode register in software.
3.11 Enhanced External Parallel Interface (XIO2)
The 5416 external interface has been redesigned to include several improvements, including: simplification
of the bus sequence, more immunity to bus contention when transitioning between read and write operations,
the ability for external memory access to the DMA controller, and optimization of the power-down modes.
The bus sequence on the 5416 still maintains all of the same interface signals as on previous 54x devices,
but the signal sequence has been simplified. Most external accesses now require 3 cycles composed of a
leading cycle, an active (read or write) cycle, and a trailing cycle. The leading and trailing cycles provide
additional immunity against bus contention when switching between read operations and write operations. To
maintain high-speed read access, a consecutive read mode that performs single-cycle reads as on previous
54x devices is available.
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Functional Overview
Figure 3–12 shows the bus sequence for three cases: all I/O reads, memory reads in nonconsecutive mode,
or single memory reads in consecutive mode. The accesses shown in Figure 3–12 always require 3 CLKOUT
cycles to complete.
CLKOUT
A[22:0]
D[15:0]
R/W
READ
MSTRB or IOSTRB
PS/DS/IS
Leading
Cycle
Read
Cycle
Trailing
Cycle
Figure 3–12. Nonconsecutive Memory Read and I/O Read Bus Sequence
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Functional Overview
Figure 3–13 shows the bus sequence for repeated memory reads in consecutive mode. The accesses shown
in Figure 3–13 require (2 + n) CLKOUT cycles to complete, where n is the number of consecutive reads
performed.
CLKOUT
A[22:0]
D[15:0]
R/W
READ
READ
READ
MSTRB
PS/DS
Leading
Cycle
Read
Cycle
Read
Cycle
Read
Cycle
Trailing
Cycle
Figure 3–13. Consecutive Memory Read Bus Sequence (n = 3 reads)
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Figure 3–14 shows the bus sequence for all memory writes and I/O writes. The accesses shown in
Figure 3–14 always require 3 CLKOUT cycles to complete.
CLKOUT
A[22:0]
D[15:0]
R/W
WRITE
MSTRB or IOSTRB
PS/DS/IS
Leading
Cycle
Write
Cycle
Trailing
Cycle
Figure 3–14. Memory Write and I/O Write Bus Sequence
The enhanced interface also provides the ability for DMA transfers to extend to external memory. For more
information on DMA capability, see the DMA sections that follow.
The enhanced interface improves the low-power performance already present on the TMS320C5000 DSP
platformbyswitchingofftheinternalclockstotheinterfacewhenitisnotbeingused. Thispower-savingfeature
is automatic, requires no software setup, and causes no latency in the operation of the interface.
Additional features integrated in the enhanced interface are the ability to automatically insert bank-switching
cycles when crossing 32K memory boundaries (see Section 3.6.2), the ability to program up to 14 wait states
through software (see Section 3.6.1), and the ability to divide down CLKOUT by a factor of 1, 2, 3, or 4. Dividing
down CLKOUT provides an alternative to wait states when interfacing to slower external memory or peripheral
devices. While inserting wait states extends the bus sequence during read or write accesses, it does not slow
down the bus signal sequences at the beginning and the end of the access. Dividing down CLKOUT provides
a method of slowing the entire bus sequence when necessary. The CLKOUT divide-down factor is controlled
through the DIVFCT field in the bank-switching control register (BSCR) (see Table 3–5).
3.12 DMA Controller
The 5416 direct memory access (DMA) controller transfers data between points in the memory map without
intervention by the CPU. The DMA allows movements of data to and from internal program/data memory,
internal peripherals (such as the McBSPs), or external memory devices to occur in the background of CPU
operation. The DMA has six independent programmable channels, allowing six different contexts for DMA
operation.
TMS320C5000 is a trademark of Texas Instruments.
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Functional Overview
3.12.1 Features
The DMA has the following features:
•
•
•
•
•
The DMA operates independently of the CPU.
The DMA has six channels. The DMA can keep track of the contexts of six independent block transfers.
The DMA has higher priority than the CPU for both internal and external accesses.
Each channel has independently programmable priorities.
Each channel’s source and destination address registers can have configurable indexes through memory
on each read and write transfer, respectively. The address may remain constant, be post-incremented,
be post-decremented, or be adjusted by a programmable value.
•
•
•
Each read or write internal transfer may be initialized by selected events.
On completion of a half- or entire-block transfer, each DMA channel may send an interrupt to the CPU.
The DMA can perform double-word internal transfers (a 32-bit transfer of two 16-bit words).
3.12.2 DMA External Access
The 5416 DMA supports external accesses to data, I/O, and extended program memory. These overlay pages
are only visible to the DMA controller. A maximum of two DMA channels can be used for external memory
accesses. The DMA external accesses require a minimum of 8 cycles for external writes and a minimum of
11 cycles for external reads assuming the XIO02 is in consecutive mode (CONSEC = 1), wait state is set to
two, and CLKOUT is not divided (DIVFCT = 00).
The control of the bus is arbitrated between the CPU and the DMA. While the DMA or CPU is in control of the
external bus, the other will be held-off via wait states until the current transfer is complete. The DMA takes
precedence over XIO requests.
•
Only two channels are available for external accesses. (One for external reads and one for external
writes.)
•
•
•
•
•
Single-word (16-bit) transfers are supported for external accesses.
The DMA does not support transfers from the peripherals to external memory.
The DMA does not support transfers from external memory to the peripherals.
The DMA does not support external-to-external accesses.
The DMA does not support synchronized external accesses.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CT
AUTO
INIT
DINM IMOD
SLAXS
SIND
DMS
DLAXS
DIND
DMD
MOD
Figure 3–15. DMA Transfer Mode Control Register (DMMCRn)
These new bit fields were created to allow the user to define the space-select for the DMA (internal/external).
The functions of the DLAXS and SLAXS bits are as follows:
DLAXS(DMMCRn[5]) Destination
SLAXS(DMMCRn[11]) Source
0 = No external access (default internal)
1 = External access
0 = No external access (default internal)
1 = External access
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Functional Overview
Table 3–9 lists the DMD bit values and their corresponding destination space.
Table 3–9. DMD Section of the DMMCRn Register
DMD
DESTINATION SPACE
00
PS
DS
01
10
I/O
11
Reserved
For the CPU external access, software can configure the memory cells to reside inside or outside the program
address map. When the cells are mapped into program space, the device automatically accesses them when
their addresses are within bounds. When the address generation logic generates an address outside its
bounds, the device automatically generates an external access.
3.12.3 DMA Memory Map
The DMA memory map, shown in Figure 3–16, allows the DMA transfer to be unaffected by the status of the
MP/MC, DROM, and OVLY bits.
Program
Program
Program
Program
Reserved
Hex
0x0000
Hex
010000
Hex
xx0000
Hex
0000
005F
0060
On-Chip
DARAM0
8K Words
DLAXS = 0
SLAXS = 0
1FFF
2000
On-Chip
DARAM1
8K Words
3FFF
4000
Reserved
Reserved
On-Chip
DARAM2
8K Words
5FFF
6000
On-Chip
DARAM3
8K Words
0x7FFF
0x8000
017FFF
018000
7FFF
8000
Reserved
On-Chip
DARAM 4
8K Words
On-Chip
SARAM 0/4
8K Words
019FFF
01A000
0x9FFF
0xA000
On-Chip
DARAM 5
8K Words
On-Chip
SARAM 1/5
8K Words
01BFFF
01C000
0xBFFF
0xC000
On-Chip
DARAM 6
8K Words
On-Chip
SARAM 2/6
8K Words
Reserved
01DFFF
01E000
0xDFFF
0xE000
On-Chip
DARAM 7
8K Words
On-Chip
SARAM 3/7
8K Words
xxFFFF
01FFFF
FFFF
0xFFFF
Page 1
Page 2 – 3
Page 0
Page 4 – 127
Figure 3–16. On-Chip DMA Memory Map for Program Space (DLAXS = 0 and SLAXS = 0)
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Functional Overview
Data Space (0000 – 005F)
Hex
Data Space
I/O Space
Hex
0000
0000
001F
0020
0021
0022
0000
Reserved
Data Space
(See Breakout)
DRR20
DRR10
DXR20
005F
0060
0023
0024
002F
0030
0031
0032
0033
DXR10
Scratch-Pad
RAM
Reserved
DRR22
DRR12
DXR22
DXR12
007F
0080
On-Chip
DARAM0
8K Words
1FFF
2000
On-Chip
DARAM1
8K Words
0034
0035
0036
0037
Reserved
RCERA2
XCERA2
3FFF
4000
On-Chip
DARAM2
8K Words
0038
0039
Reserved
Reserved
5FFF
6000
003A
RECRA0
XECRA0
On-Chip
DARAM3
8K Words
003B
003C
003F
0040
0041
Reserved
DRR21
7FFF
8000
On-Chip
DARAM4
8K Words
DRR11
DXR21
DXR11
0042
0043
9FFF
A000
On-Chip
DARAM5
8K Words
0044
0049
004A
Reserved
RCERA1
BFFF
C000
On-Chip
DARAM6
8K Words
004B
XCERA1
004C
005F
Reserved
DFFF
E000
On-Chip
DARAM7
8K Words
FFFF
FFFF
Figure 3–17. On-Chip DMA Memory Map for Data and IO Space (DLAXS = 0 and SLAXS = 0)
3.12.4 DMA Priority Level
Each DMA channel can be independently assigned high- or low-priority relative to each other. Multiple DMA
channels that are assigned to the same priority level are handled in a round-robin manner.
3.12.5 DMA Source/Destination Address Modification
The DMA provides flexible address-indexing modes for easy implementation of data management schemes
such as autobuffering and circular buffers. Source and destination addresses can be indexed separately and
can be post-incremented, post-decremented, or post-incremented with a specified index offset.
3.12.6 DMA in Autoinitialization Mode
The DMA can automatically reinitialize itself after completion of a block transfer. Some of the DMA registers
can be preloaded for the next block transfer through the DMA reload registers (DMGSA, DMGDA, DMGCR,
and DMGFR). Autoinitialization allows:
•
Continuous operation: Normally, the CPU would have to reinitialize the DMA immediately after the
completion of the current block transfers, but with the reload registers, it can reinitialize these values for
the next block transfer any time after the current block transfer begins.
•
Repetitiveoperation:TheCPUdoesnotpreloadthereloadregisterwithnewvaluesforeachblocktransfer
but only loads them on the first block transfer.
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Functional Overview
The 5416 DMA has been enhanced to expand the DMA reload register sets. Each DMA channel now has its
ownDMAreloadregisterset. Forexample, theDMAreloadregistersetforchannel0hasDMGSA0, DMGDA0,
DMGCR0, and DMGFR0 while DMA channel 1 has DMGSA1, DMGDA1, DMGCR1, and DMGFR1, etc.
To utilize the additional DMA reload registers, the AUTOIX bit is added to the DMPREC register as shown in
Figure 3–18.
15
14
13
8
7
6
5
0
FREE AUTOIX
DPRC[5:0]
IOSEL
DE[5:0]
Figure 3–18. DMPREC Register
Table 3–10. DMA Reload Register Selection
AUTOIX
0 (default)
1
DMA RELOAD REGISTER USAGE IN AUTO INIT MODE
All DMA channels use DMGSA0, DMGDA0, DMGCR0 and DMGFR0
Each DMA channel uses its own set of reload registers
3.12.7 DMA Transfer Counting
The DMA channel element count register (DMCTRx) and the frame count register (DMFRCx) contain bit fields
that represent the number of frames and the number of elements per frame to be transferred.
•
Frame count. This 8-bit value defines the total number of frames in the block transfer. The maximum
number of frames per block transfer is 128 (FRAME COUNT= 0FFh). The counter is decremented upon
the last read transfer in a frame transfer. Once the last frame is transferred, the selected 8-bit counter is
reloaded with the DMA global frame reload register (DMGFR) if the AUTOINIT bit is set to 1. A frame count
of 0 (default value) means the block transfer contains a single frame.
•
Element count. This 16-bit value defines the number of elements per frame. This counter is decremented
after the read transfer of each element. The maximum number of elements per frame is 65536
(DMCTRn=0FFFFh). Inautoinitializationmode, oncethelastframeistransferred, thecounterisreloaded
with the DMA global count reload register (DMGCR).
3.12.8 DMA Transfer in Doubleword Mode
Doubleword mode allows the DMA to transfer 32-bit words in any index mode. In doubleword mode, two
consecutive 16-bit transfers are initiated and the source and destination addresses are automatically updated
following each transfer. In this mode, each 32-bit word is considered to be one element.
3.12.9 DMA Channel Index Registers
The particular DMA channel index register is selected by way of the SIND and DIND fields in the DMA transfer
mode control register (DMMCRn). Unlike basic address adjustment, in conjunction with the frame index
DMFRI0andDMFRI1, theDMAallowsdifferentadjustmentamountsdependingonwhetherornottheelement
transfer is the last in the current frame. The normal adjustment value (element index) is contained in the
element index registers DMIDX0 and DMIDX1. The adjustment value (frame index) for the end of the frame,
is determined by the selected DMA frame index register, either DMFRI0 or DMFRI1.
The element index and the frame index affect address adjustment as follows:
•
Element index: For all except the last transfer in the frame, the element index determines the amount to
be added to the DMA channel for the source/destination address register (DMSRCx/DMDSTx) as
selected by the SIND/DIND bits.
•
Frame index: If the transfer is the last in a frame, frame index is used for address adjustment as selected
by the SIND/DIND bits. This occurs in both single-frame and multiframe transfers.
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Functional Overview
3.12.10 DMA Interrupts
The ability of the DMA to interrupt the CPU based on the status of the data transfer is configurable and is
determined by the IMOD and DINM bits in the DMA transfer mode control register (DMMCRn). The available
modes are shown in Table 3–11.
Table 3–11. DMA Interrupts
MODE
ABU (non-decrement)
ABU (non-decrement)
Multiframe
DINM
IMOD
INTERRUPT
1
1
1
1
0
0
0
1
0
1
X
X
At full buffer only
At half buffer and full buffer
At block transfer complete (DMCTRn = DMSEFCn[7:0] = 0)
At end of frame and end of block (DMCTRn = 0)
No interrupt generated
Multiframe
Either
Either
No interrupt generated
3.12.11 DMA Controller Synchronization Events
The transfers associated with each DMA channel can be synchronized to one of several events. The DSYN
bit field of the DMSEFCn register selects the synchronization event for a channel. The list of possible events
and the DSYN values are shown in Table 3–12.
Table 3–12. DMA Synchronization Events
DSYN VALUE
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
DMA SYNCHRONIZATION EVENT
No synchronization used
McBSP0 receive event
McBSP0 transmit event
McBSP2 receive event
McBSP2 transmit event
McBSP1 receive event
McBSP1 transmit event
McBSP0 receive event – ABIS mode
McBSP0 transmit event – ABIS mode
McBSP2 receive event – ABIS mode
McBSP2 transmit event – ABIS mode
McBSP1 receive event – ABIS mode
McBSP1 transmit event – ABIS mode
Timer interrupt event
1000b
1001b
1010b
1011b
1100b
1101b
1110b
INT3 goes active
1111b
Reserved
The DMA controller can generate a CPU interrupt for each of the six channels. However, due to a limit on the
number of internal CPU interrupt inputs, channels 0, 1, 2, and 3 are multiplexed with other interrupt sources.
DMA channels 0, 1, 2, and 3 share an interrupt line with the receive and transmit portions of the McBSP. When
the 5416 is reset, the interrupts from these three DMA channels are deselected. The INTSEL bit field in the
DMPREC register can be used to select these interrupts, as shown in Table 3–13.
Table 3–13. DMA Channel Interrupt Selection
INTSEL Value
00b (reset)
01b
IMR/IFR[6]
BRINT2
BRINT2
DMAC0
IMR/IFR[7]
BXINT2
IMR/IFR[10]
BRINT1
IMR/IFR[11]
BXINT1
BXINT2
DMAC2
DMAC3
10b
DMAC1
DMAC2
DMAC3
11b
Reserved
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Functional Overview
3.13 General-Purpose I/O Pins
In addition to the standard BIO and XF pins, the 5416 has pins that can be configured for general-purpose
I/O. These pins are:
•
•
18 McBSP pins — BCLKX0/1/2, BCLKR0/1/2, BDR0/1/2, BFSX0/1/2, BFSR0/1/2, BDX0/1/2
8 HPI data pins—HD0–HD7
The general-purpose I/O function of these pins is only available when the primary pin function is not required.
3.13.1 McBSP Pins as General-Purpose I/O
When the receive or transmit portion of a McBSP is in reset, its pins can be configured as general-purpose
inputs or outputs. For more details on this feature, see Section 3.8.
3.13.2 HPI Data Pins as General-Purpose I/O
The 8-bit bidirectional data bus of the HPI can be used as general-purpose input/output (GPIO) pins when the
HPI is disabled (HPIENA = 0) or when the HPI is used in HPI16 mode (HPI16 = 1). Two memory-mapped
registers are used to control the GPIO function of the HPI data pins—the general-purpose I/O control register
(GPIOCR) and the general-purpose I/O status register (GPIOSR). The GPIOCR is shown in Figure 3–19.
15
8
7
6
5
4
3
2
1
0
DIR2
Reserved
0
DIR7
R/W-0
DIR6
R/W-0
DIR5
R/W-0
DIR4
R/W-0
DIR3
R/W-0
DIR1
R/W-0
DIR0
R/W-0
R/W-0
Figure 3–19. General-Purpose I/O Control Register (GPIOCR) [MMR Address 003Ch]
The direction bits (DIRx) are used to configure HD0–HD7 as inputs or outputs.
The status of the GPIO pins can be monitored using the bits of the GPIOSR. The GPIOSR is shown in
Figure 3–20.
15
8
7
6
5
4
3
2
1
0
Reserved
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IO0
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Figure 3–20. General-Purpose I/O Status Register (GPIOSR) [MMR Address 003Dh]
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Functional Overview
3.14 Device ID Register
Aread-onlymemory-mappedregisterhasbeenaddedtothe5416toallowuserapplicationsoftwaretoidentify
on which device the program is being executed.
15–8
Chip ID
R
7
4
3
0
Chip Revision
R
SUBSYSID
R
Bits 15:8: Chip_ID (hex code of 16)
Bits 7:4: Chip_Revision ID
Bits 3:0: Subsystem_ID (0000b for single core device)
Figure 3–21. Device ID Register (CSIDR) [MMR Address 003Eh]
3.15 Memory-Mapped Registers
The 5416 has 27 memory-mapped CPU registers, which are mapped in data memory space address 0h to
1Fh. Each 5416 device also has a set of memory-mapped registers associated with peripherals. Table 3–14
gives a list of CPU memory-mapped registers (MMRs) available on 5416. Table 3–15 shows additional
peripheral MMRs associated with the 5416.
Table 3–14. CPU Memory-Mapped Registers
ADDRESS
NAME
DESCRIPTION
DEC
0
HEX
0
IMR
IFR
—
Interrupt mask register
Interrupt flag register
Reserved for testing
Status register 0
1
1
2–5
6
2–5
6
ST0
ST1
AL
7
7
Status register 1
8
8
Accumulator A low word (15–0)
AH
9
9
Accumulator A high word (31–16)
Accumulator A guard bits (39–32)
Accumulator B low word (15–0)
Accumulator B high word (31–16)
Accumulator B guard bits (39–32)
Temporary register
AG
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
A
BL
B
BH
C
BG
D
TREG
TRN
AR0
AR1
AR2
AR3
AR4
AR5
AR6
AR7
SP
E
F
Transition register
10
11
12
13
14
15
16
17
18
19
1A
1B
Auxiliary register 0
Auxiliary register 1
Auxiliary register 2
Auxiliary register 3
Auxiliary register 4
Auxiliary register 5
Auxiliary register 6
Auxiliary register 7
Stack pointer register
BK
Circular buffer size register
Block repeat counter
BRC
RSA
Block repeat start address
35
April 2003 – Revised July 2003
SGUS035A
Functional Overview
Table 3–14. CPU Memory-Mapped Registers (Continued)
ADDRESS
NAME
DESCRIPTION
DEC
28
HEX
REA
PMST
XPC
—
1C
1D
1E
1F
Block repeat end address
Processor mode status (PMST) register
Extended program page register
Reserved
29
30
31
36
SGUS035A
April 2003 – Revised July 2003
Functional Overview
Table 3–15. Peripheral Memory-Mapped Registers for Each DSP Subsystem
ADDRESS
NAME
DRR20
DESCRIPTION
DEC
HEX
32
33
20
McBSP 0 Data Receive Register 2
McBSP 0 Data Receive Register 1
McBSP 0 Data Transmit Register 2
McBSP 0 Data Transmit Register 1
Timer Register
DRR10
DXR20
DXR10
TIM
21
34
22
35
23
36
24
PRD
37
25
Timer Period Register
TCR
38
26
Timer Control Register
—
39
27
Reserved
SWWSR
BSCR
—
40
28
Software Wait-State Register
Bank-Switching Control Register
Reserved
41
29
42
2A
SWCR
HPIC
43
2B
Software Wait-State Control Register
44
2C
HPI Control Register (HMODE = 0 only)
Reserved
—
45–47
48
2D–2F
30
DRR22
DRR12
DXR22
DXR12
SPSA2
SPSD2
—
McBSP 2 Data Receive Register 2
McBSP 2 Data Receive Register 1
McBSP 2 Data Transmit Register 2
McBSP 2 Data Transmit Register 1
49
31
50
32
51
33
†
†
52
34
McBSP 2 Subbank Address Register
†
53
35
McBSP 2 Subbank Data Register
Reserved
54–55
56
36–37
38
SPSA0
SPSD0
—
McBSP 0 Subbank Address Register
†
57
39
McBSP 0 Subbank Data Register
Reserved
58–59
60
3A–3B
3C
GPIOCR
GPIOSR
CSIDR
—
General-Purpose I/O Control Register
General-Purpose I/O Status Register
Device ID Register
61
3D
62
3E
63
3F
Reserved
DRR21
DRR11
DXR21
DXR11
—
64
40
McBSP 1 Data Receive Register 2
McBSP 1 Data Receive Register 1
McBSP 1 Data Transmit Register 2
McBSP 1 Data Transmit Register 1
Reserved
65
41
66
42
67
43
68–71
72
44–47
48
†
McBSP 1 Subbank Address Register
SPSA1
SPSD1
—
†
73
49
McBSP 1 Subbank Data Register
Reserved
74–83
84
4A–53
54
DMPREC
DMSA
DMSDI
DMSDN
CLKMD
—
DMA Priority and Enable Control Register
‡
85
55
DMA Subbank Address Register
‡
86
56
DMA Subbank Data Register with Autoincrement
‡
DMA Subbank Data Register
87
57
88
58
Clock Mode Register (CLKMD)
Reserved
89–95
59–5F
†
‡
See Table 3–16 for a detailed description of the McBSP control registers and their subaddresses.
See Table 3–17 for a detailed description of the DMA subbank addressed registers.
37
April 2003 – Revised July 2003
SGUS035A
Functional Overview
3.16 McBSP Control Registers and Subaddresses
The control registers for the multichannel buffered serial port (McBSP) are accessed using the subbank
addressing scheme. This allows a set or subbank of registers to be accessed through a single memory
location. TheMcBSPsubbankaddressregister(SPSA)isusedasapointertoselectaparticularregisterwithin
the subbank. The McBSP data register (SPSDx) is used to access (read or write) the selected register.
Table 3–16 shows the McBSP control registers and their corresponding subaddresses.
Table 3–16. McBSP Control Registers and Subaddresses
McBSP0
McBSP1
McBSP2
SUB-
ADDRESS
DESCRIPTION
NAME
ADDRESS
39h
NAME
ADDRESS
49h
NAME
ADDRESS
35h
SPCR10
SPCR20
RCR10
SPCR11
SPCR21
RCR11
SPCR12
SPCR22
RCR12
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
Serial port control register 1
39h
49h
35h
Serial port control register 2
39h
49h
35h
Receive control register 1
RCR20
39h
RCR21
49h
RCR22
35h
Receive control register 2
XCR10
39h
XCR11
49h
XCR12
35h
Transmit control register 1
XCR20
39h
XCR21
49h
XCR22
35h
Transmit control register 2
SRGR10
SRGR20
MCR10
MCR20
RCERA0
RCERB0
XCERA0
XCERB0
PCR0
39h
SRGR11
SRGR21
MCR11
MCR21
RCERA1
RCERB1
XCERA1
XCERB1
PCR1
49h
SRGR12
SRGR22
MCR12
MCR22
RCERA2
RCERA2
XCERA2
XCERA2
PCR2
35h
Sample rate generator register 1
Sample rate generator register 2
Multichannel register 1
39h
49h
35h
39h
49h
35h
39h
49h
35h
Multichannel register 2
39h
49h
35h
Receive channel enable register partition A
Receive channel enable register partition B
Transmit channel enable register partition A
Transmit channel enable register partition B
Pin control register
39h
49h
35h
39h
49h
35h
39h
49h
35h
39h
49h
35h
Additional channel enable register for
128-channel selection
RCERC0
RCERD0
XCERC0
XCERD0
RCERE0
RCERF0
XCERE0
XCERF0
RCERG0
RCERH0
XCERG0
XCERH0
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
RCERC1
RCERD1
XCERC1
XCERD1
RCERE1
RCERF1
XCERE1
XCERF1
RCERG1
RCERH1
XCERG1
XCERH1
49h
49h
49h
49h
49h
49h
49h
49h
49h
49h
49h
49h
RCERC2
RCERD2
XCERC2
XCERD2
RCERE2
RCERF2
XCERE2
XCERF2
RCERG2
RCERH2
XCERG2
XCERH2
35h
35h
35h
35h
35h
35h
35h
35h
35h
35h
35h
35h
010h
011h
012h
013h
014h
015h
016h
017h
018h
019h
01Ah
01Bh
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
38
SGUS035A
April 2003 – Revised July 2003
Functional Overview
3.17 DMA Subbank Addressed Registers
The direct memory access (DMA) controller has several control registers associated with it. The main control
register (DMPREC) is a standard memory-mapped register. However, the other registers are accessed using
the subbank addressing scheme. This allows a set or subbank of registers to be accessed through a single
memory location. The DMA subbank address (DMSA) register is used as a pointer to select a particular
register within the subbank, while the DMA subbank data (DMSD) register or the DMA subbank data register
with autoincrement (DMSDI) is used to access (read or write) the selected register.
When the DMSDI register is used to access the subbank, the subbank address is automatically
postincrementedsothatasubsequentaccessaffectsthenextregisterwithinthesubbank. Thisautoincrement
feature is intended for efficient, successive accesses to several control registers. If the autoincrement feature
is not required, the DMSDN register should be used to access the subbank. Table 3–17 shows the DMA
controller subbank addressed registers and their corresponding subaddresses.
Table 3–17. DMA Subbank Addressed Registers
SUB-
NAME
ADDRESS
DESCRIPTION
ADDRESS
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
DMSRC0
DMDST0
DMCTR0
DMSFC0
DMMCR0
DMSRC1
DMDST1
DMCTR1
DMSFC1
DMMCR1
DMSRC2
DMDST2
DMCTR2
DMSFC2
DMMCR2
DMSRC3
DMDST3
DMCTR3
DMSFC3
DMMCR3
DMSRC4
DMDST4
DMCTR4
DMSFC4
DMMCR4
DMSRC5
DMDST5
DMCTR5
DMSFC5
DMMCR5
DMSRCP
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
DMA channel 0 source address register
DMA channel 0 destination address register
DMA channel 0 element count register
DMA channel 0 sync select and frame count register
DMA channel 0 transfer mode control register
DMA channel 1 source address register
DMA channel 1 destination address register
DMA channel 1 element count register
DMA channel 1 sync select and frame count register
DMA channel 1 transfer mode control register
DMA channel 2 source address register
DMA channel 2 destination address register
DMA channel 2 element count register
DMA channel 2 sync select and frame count register
DMA channel 2 transfer mode control register
DMA channel 3 source address register
DMA channel 3 destination address register
DMA channel 3 element count register
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
DMA channel 3 sync select and frame count register
DMA channel 3 transfer mode control register
DMA channel 4 source address register
DMA channel 4 destination address register
DMA channel 4 element count register
DMA channel 4 sync select and frame count register
DMA channel 4 transfer mode control register
DMA channel 5 source address register
DMA channel 5 destination address register
DMA channel 5 element count register
DMA channel 5 sync select and frame count register
DMA channel 5 transfer mode control register
DMA source program page address (common channel)
39
April 2003 – Revised July 2003
SGUS035A
Functional Overview
Table 3–17. DMA Subbank Addressed Registers (Continued)
SUB-
NAME
ADDRESS
DESCRIPTION
ADDRESS
DMDSTP
DMIDX0
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
3Dh
DMA destination program page address (common channel)
DMA element index address register 0
DMIDX1
DMA element index address register 1
DMFRI0
DMA frame index register 0
DMFRI1
DMA frame index register 1
DMGSA0
DMGDA0
DMGCR0
DMGFR0
XSRCDP
XDSTDP
DMGSA1
DMGDA1
DMGCR1
DMGFR1
DMGSA2
DMGDA2
DMGCR2
DMGFR2
DMGSA3
DMGDA3
DMGCR3
DMGFR3
DMGSA4
DMGDA4
DMGCR4
DMGFR4
DMGSA5
DMGDA5
DMGCR5
DMGFR5
DMA global source address reload register, channel 0
DMA global destination address reload register, channel 0
DMA global count reload register, channel 0
DMA global frame count reload register, channel 0
DMA extended source data page (currently not supported)
DMA extended destination data page (currently not supported)
DMA global source address reload register, channel 1
DMA global destination address reload register, channel 1
DMA global count reload register, channel 1
DMA global frame count reload register, channel 1
DMA global source address reload register, channel 2
DMA global destination address reload register, channel 2
DMA global count reload register, channel 2
DMA global frame count reload register, channel 2
DMA global source address reload register, channel 3
DMA global destination address reload register, channel 3
DMA global count reload register, channel 3
DMA global frame count reload register, channel 3
DMA global source address reload register, channel 4
DMA global destination address reload register, channel 4
DMA global count reload register, channel 4
DMA global frame count reload register, channel 4
DMA global source address reload register, channel 5
DMA global destination address reload register, channel 5
DMA global count reload register, channel 5
DMA global frame count reload register, channel 5
40
SGUS035A
April 2003 – Revised July 2003
Functional Overview
3.18 Interrupts
Vector-relative locations and priorities for all internal and external interrupts are shown in Table 3–18.
Table 3–18. Interrupt Locations and Priorities
LOCATION
PRIORITY
NAME
FUNCTION
DECIMAL
0
HEX
00
RS, SINTR
NMI, SINT16
SINT17
1
2
Reset (hardware and software reset)
Nonmaskable interrupt
4
04
8
08
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3
Software interrupt #17
SINT18
12
0C
10
Software interrupt #18
SINT19
16
Software interrupt #19
SINT20
20
14
Software interrupt #20
SINT21
24
18
Software interrupt #21
SINT22
28
1C
20
Software interrupt #22
SINT23
32
Software interrupt #23
SINT24
36
24
Software interrupt #24
SINT25
40
28
Software interrupt #25
SINT26
44
2C
30
Software interrupt #26
SINT27
48
Software interrupt #27
SINT28
52
34
Software interrupt #28
SINT29
56
38
Software interrupt #29
SINT30
60
3C
40
Software interrupt #30
INT0, SINT0
INT1, SINT1
INT2, SINT2
TINT, SINT3
RINT0, SINT4
XINT0, SINT5
RINT2, SINT6
XINT2, SINT7
INT3, SINT8
HINT, SINT9
64
External user interrupt #0
External user interrupt #1
External user interrupt #2
Timer interrupt
68
44
4
72
48
5
76
4C
50
6
80
7
McBSP #0 receive interrupt (default)
McBSP #0 transmit interrupt (default)
McBSP #2 receive interrupt (default)
McBSP #2 transmit interrupt (default)
External user interrupt #3
HPI interrupt
84
54
8
88
58
9
92
5C
60
10
11
12
13
14
15
16
—
96
100
104
108
112
116
120–127
64
RINT1, SINT10
XINT1, SINT11
DMAC4,SINT12
DMAC5,SINT13
Reserved
68
McBSP #1 receive interrupt (default)
McBSP #1 transmit interrupt (default)
DMA channel 4 (default)
DMA channel 5 (default)
Reserved
6C
70
74
78–7F
The bit layout of the interrupt flag register (IFR) and the interrupt mask register (IMR) is shown in Figure 3–22.
15–14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Resvd DMAC5 DMAC4 XINT1 RINT1 HINT
INT3
XINT2 RINT2 XINT0 RINT0
TINT
INT2
INT1
INT0
Figure 3–22. IFR and IMR
41
April 2003 – Revised July 2003
SGUS035A
Documentation Support
4
Documentation Support
Extensive documentation supports all TMS320 DSP family of devices from product announcement through
applications development. The following types of documentation are available to support the design and use
of the C5000 platform of DSPs:
•
•
•
•
•
TMS320C54x DSP Functional Overview (literature number SPRU307)
Device-specific data sheets
Complete user’s guides
Development support tools
Hardware and software application reports
The five-volume TMS320C54x DSP Reference Set (literature number SPRU210) consists of:
•
•
•
•
•
Volume 1: CPU and Peripherals (literature number SPRU131)
Volume 2: Mnemonic Instruction Set (literature number SPRU172)
Volume 3: Algebraic Instruction Set (literature number SPRU179)
Volume 4: Applications Guide (literature number SPRU173)
Volume 5: Enhanced Peripherals (literature number SPRU302)
The reference set describes in detail the TMS320C54x DSP products currently available and the hardware
and software applications, including algorithms, for fixed-point TMS320 DSP family of devices.
A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal
processing research and education. The TMS320 DSP newsletter, Details on Signal Processing, is
published quarterly and distributed to update TMS320 DSP customers on product information.
Information regarding TI DSP products is also available on the Worldwide Web at http://www.ti.com uniform
resource locator (URL).
TMS320 and C5000 are trademarks of Texas Instruments.
42
SGUS035A
April 2003 – Revised July 2003
Electrical Specifications
5
Electrical Specifications
This section provides the absolute maximum ratings and the recommended operating conditions for the
SMJ320VC5416 DSP.
5.1 Absolute Maximum Ratings
The list of absolute maximum ratings are specified over operating case temperature. Stresses beyond those
listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated
under Section 5.2 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability. All voltage values are with respect to DV . Figure 5–1 provides the test load circuit
SS
values for a 3.3-V device.
Supply voltage I/O range, DV
Supply voltage core range, CV
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.0 V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 2.0 V
DD
Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.5 V
Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.5 V
Thermal resistance, Junction-to-Case, Θ
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.82°C/W
JC
Operating case temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 115°C
C
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C
stg
5.2 Recommended Operating Conditions
MIN
2.75
1.45
NOM
3.3
MAX
3.6
UNIT
V
DV
CV
Device supply voltage, I/O
DD
DD
Device supply voltage, core (VC5416-100)
1.5
1.65
V
DV
CV
,
SS
SS
Supply voltage, GND
0
V
RS, INTn, NMI, X2/CLKIN,
CLKMDn, BCLKRn, BCLKXn,
HCS, HDS1, HDS2, HAS,
TRST, BIO, Dn, An, HDn, TCK
2.4
2
DV
DV
+ 0.3*
DD
DD
V
IH
High-level input voltage, I/O
V
DV
= 2.75 V to 3.6 V
DD
All other inputs
+ 0.3*
X2/CLKIN
–0.3*
–0.3*
0.42
V
Low-level input voltage
V
IL
All other inputs
0.8
–8
8
†
I
I
High-level output current
mA
mA
°C
OH
†
Low-level output current
Operating case temperature
* Not production tested.
OL
T
C
–55
115
†
Note that maximum output currents are DC values only. Transient currents may exceed these values.
43
April 2003 – Revised July 2003
SGUS035A
Electrical Specifications
5.3 Electrical Characteristics Over Recommended Operating Case Temperature
Range (Unless Otherwise Noted)
†
TYP
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
DV
DV
= 2.75 V to 3 V, I = MAX
2.2
DD
DD
OH
= MAX
‡
V
V
High-level output voltage
V
OH
= 3 V to 3.6 V, I
2.4
OH
‡
Low-level output voltage
I
= MAX
0.4
40
V
OL
OL
X2/CLKIN
–40
–10
µA
TRST, HPI16
HPIENA
With internal pulldown
800
400
10
With internal pulldown, RS = 0
With internal pullups
–10
Input current
(V = DV to DV
§
I
I
TMS, TCK, TDI, HPI
–400
)
µA
I
SS DD
A[17:0], D[15:0],
HD[7:0]
Bus holders enabled, DV
DD
= MAXk
–275
–5
275
5
All other input-only pins
¶
#
I
I
Supply current, core CPU
Supply current, pins
CV
DV
= 1.6 V, f = 100 ,
T = 25°C
C
60
mA
mA
DDC
DD
DD
x
¶
||
40
= 3.0 V, f = 100 MHz,
T = 25°C
C
DDP
x
IDLE2
PLL × 1 mode, 20 MHz input
2
1
Supply current,
standby
T
T
= 25°C
I
mA
C
DD
IDLE3 Divide-by-two
mode, CLKIN stopped
= 115°C
38
C
C
C
Input capacitance
Output capacitance
15
15
pF
pF
i
o
†
‡
All values are typical unless otherwise specified.
All input and output voltage levels except RS, INT0–INT3, NMI, X2/CLKIN, CLKMD1–CLKMD3, BCLKRn, BCLKXn, HCS, HAS, HDS1, HDS2,
BIO, TCK, TRST, Dn, An, HDn are LVTTL-compatible.
§
¶
#
HPI input signals except for HPIENA and HPI16, when HPIENA = 0.
Clock mode: PLL × 1 with external source
This value was obtained with 50% usage of MAC and 50% usage of NOP instructions. Actual operating current varies with program being
executed.
This value was obtained with single-cycle external writes, CLKOFF = 0 and load = 15 pF. For more details on how this calculation is performed,
refer to the Calculation of TMS320LC54x Power Dissipation application report (literature number SPRA164).
||
kV
≤ V ≤ V
or V
≤ V ≤ V
IH(MAX)
IL(MIN)
I
IL(MAX)
IH(MIN)
I
I
OL
50 Ω
Output
Under
Test
Tester Pin
Electronics
V
Load
C
T
I
OH
Where:
I
= 1.5 mA (all outputs)
= 300 µA (all outputs)
= 1.5 V
OL
I
OH
V
Load
C
= 20-pF typical load circuit capacitance
T
Figure 5–1. 3.3-V Test Load Circuit
44
SGUS035A
April 2003 – Revised July 2003
Electrical Specifications
5.4 Package Thermal Resistance Characteristics
Table 5–1 provides the estimated thermal resistance characteristics for the recommended package types
used on the SMJ320VC5416 DSP.
Table 5–1. Thermal Resistance Characteristics
PARAMETER
HFG PACKAGE
UNIT
R
1.82
°C/W
ΘJC
5.5 Timing Parameter Symbology
Timing parameter symbols used in the timing requirements and switching characteristics tables are created
in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related
terminology have been abbreviated as follows:
Lowercase subscripts and their meanings:
Letters and symbols and their meanings:
a
access time
H
L
High
c
cycle time (period)
delay time
Low
d
V
Z
Valid
dis
en
f
disable time
High impedance
enable time
fall time
h
hold time
r
rise time
su
t
setup time
transition time
valid time
v
w
X
pulse duration (width)
Unknown, changing, or don’t care level
5.6 Internal Oscillator With External Crystal
The internal oscillator is enabled by selecting the appropriate clock mode at reset (this is device-dependent;
see Section 3.10) and connecting a crystal or ceramic resonator across X1 and X2/CLKIN. The CPU clock
frequency is one-half, one-fourth, or a multiple of the oscillator frequency. The multiply ratio is determined by
the bit settings in the CLKMD register.
The crystal should be in fundamental-mode operation, and parallel resonant, with an effective series
resistance of 30 Ω maximum and power dissipation of 1 mW. The connection of the required circuit, consisting
of the crystal and two load capacitors, is shown in Figure 5–2. The load capacitors, C and C , should be
1
2
chosen such that the equation below is satisfied. C (recommended value of 10 pF) in the equation is the load
L
specified for the crystal.
C1C2
CL +
(C1 ) C2)
Table 5–2. Input Clock Frequency Characteristics
MIN
MAX
UNIT
†
10
‡
20
f
x
Input clock frequency
MHz
†
‡
This device utilizes a fully static design and therefore can operate with t
approaching ∞.
c(CI)
It is recommended that the PLL multiply by N clocking option be used for maximum frequency operation.
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April 2003 – Revised July 2003
SGUS035A
Electrical Specifications
X1
X2/CLKIN
Crystal
C1
C2
Figure 5–2. Internal Divide-by-Two Clock Option With External Crystal
5.7 Clock Options
The frequency of the reference clock provided at the CLKIN pin can be divided by a factor of two or four or
multiplied by one of several values to generate the internal machine cycle.
5.7.1 Divide-By-Two and Divide-By-Four Clock Options
The frequency of the reference clock provided at the X2/CLKIN pin can be divided by a factor of two or four
to generate the internal machine cycle. The selection of the clock mode is described in Section 3.10.
When an external clock source is used, the frequency injected must conform to specifications listed in
Table 5–4.
An external frequency source can be used by applying an input clock to X2/CLKIN with X1 left unconnected.
Table 5–3 shows the configuration options for the CLKMD pins that generate the external divide-by-2 or
divide-by-4 clock option.
Table 5–3. Clock Mode Pin Settings for the Divide-By-2 and By Divide-by-4 Clock Options
CLKMD1
CLKMD2
CLKMD3
CLOCK MODE
0
1
1
0
0
1
0
1
1
1/2, PLL disabled
1/4, PLL disabled
1/2, PLL disabled
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SGUS035A
April 2003 – Revised July 2003
Electrical Specifications
Table 5–4 and Table 5–5 assume testing over recommended operating conditions and H = 0.5t
Figure 5–3).
(see
c(CO)
Table 5–4. Divide-By-2 and Divide-by-4 Clock Options Timing Requirements
5416-100
UNIT
MIN
MAX
t
t
t
t
t
Cycle time, X2/CLKIN
20
ns
ns
ns
ns
ns
c(CI)
Fall time, X2/CLKIN
4*
4*
f(CI)
Rise time, X2/CLKIN
r(CI)
Pulse duration, X2/CLKIN low
Pulse duration, X2/CLKIN high
4*
4*
w(CIL)
w(CIH)
* Not production tested.
Table 5–5. Divide-By-2 and Divide-by-4 Clock Options Switching Characteristics
5416-100
PARAMETER
UNIT
MIN
TYP
MAX
†
‡
t
Cycle time, CLKOUT
10
ns
ns
ns
ns
ns
ns
c(CO)
t
Delay time, X2/CLKIN high to CLKOUT high/low
Fall time, CLKOUT
4
7
11
2*
d(CIH-CO)
t
f(CO)
t
t
t
Rise time, CLKOUT
2*
r(CO)
Pulse duration, CLKOUT low
Pulse duration, CLKOUT high
H –3*
H
H
H + 1*
H + 1*
w(COL)
w(COH)
H – 2*
* Not production tested.
†
‡
It is recommended that the PLL clocking option be used for maximum frequency operation.
This device utilizes a fully static design and therefore can operate with t
approaching ∞.
c(CI)
t
t
r(CI)
w(CIH)
t
t
f(CI)
w(CIL)
t
c(CI)
X2/CLKIN
t
w(COH)
t
f(CO)
t
c(CO)
t
r(CO)
t
d(CIH-CO)
t
w(COL)
CLKOUT
NOTE A: The CLKOUT timing in this diagram assumes the CLKOUT divide factor (DIVFCT field in the BSCR) is configured as 00 (CLKOUT not
divided). DIVFCT is configured as CLKOUT divided-by-4 mode following reset.
Figure 5–3. External Divide-by-Two Clock Timing
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April 2003 – Revised July 2003
SGUS035A
Electrical Specifications
5.7.2 Multiply-By-N Clock Option (PLL Enabled)
The frequency of the reference clock provided at the X2/CLKIN pin can be multiplied by a factor of N to
generate the internal machine cycle. The selection of the clock mode and the value of N is described in
Section 3.10. Following reset, the software PLL can be programmed for the desired multiplication factor. Refer
to the TMS320C54x DSP Reference Set, Volume 1: CPU and Peripherals (literature number SPRU131) for
detailed information on programming the PLL.
When an external clock source is used, the external frequency injected must conform to specifications listed
in Table 5–6.
Table 5–6 and Table 5–7 assume testing over recommended operating conditions and H = 0.5t
Figure 5–4).
(see
c(CO)
Table 5–6. Multiply-By-N Clock Option Timing Requirements
5416-100
UNIT
MIN
20
MAX
200
†
Integer PLL multiplier N (N = 1–15)
†
PLL multiplier N = x.5
PLL multiplier N = x.25, x.75
20
100
50
t
Cycle time, X2/CLKIN
ns
c(CI)
†
20
t
t
t
t
Fall time, X2/CLKIN
4*
4*
ns
ns
ns
ns
f(CI)
Rise time, X2/CLKIN
r(CI)
Pulse duration, X2/CLKIN low
Pulse duration, X2/CLKIN high
4*
4*
w(CIL)
w(CIH)
* Not production tested.
†
N is the multiplication factor.
Table 5–7. Multiply-By-N Clock Option Switching Characteristics
5416-100
TYP
PARAMETER
UNIT
MIN
10
4
MAX
t
Cycle time, CLKOUT
ns
ns
ns
ns
ns
ns
ms
c(CO)
t
Delay time, X2/CLKIN high/low to CLKOUT high/low
Fall time, CLKOUT
7
11
2*
d(CI-CO)
t
f(CO)
r(CO)
w(COL)
w(COH)
p
t
t
t
t
Rise time, CLKOUT
2*
Pulse duration, CLKOUT low
Pulse duration, CLKOUT high
Transitory phase, PLL lock-up time
H – 3*
H – 2*
H
H
H + 1*
H + 1*
30*
* Not production tested.
t
t
f(CI)
w(CIH)
t
t
r(CI)
w(CIL)
t
c(CI)
X2/CLKIN
t
d(CI-CO)
t
f(CO)
t
w(COH)
t
c(CO)
t
w(COL)
t
t
r(CO)
p
Unstable
CLKOUT
NOTE A: The CLKOUT timing in this diagram assumes the CLKOUT divide factor (DIVFCT field in the BSCR) is configured as 00 (CLKOUT not
divided). DIVFCT is configured as CLKOUT divided-by-4 mode following reset.
Figure 5–4. Multiply-by-One Clock Timing
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Electrical Specifications
5.8 Memory and Parallel I/O Interface Timing
5.8.1 Memory Read
External memory reads can be performed in consecutive or nonconsecutive mode under control of the
CONSEC bit in the BSCR. Table 5–8 and Table 5–9 assume testing over recommended operating conditions
with MSTRB = 0 and H = 0.5t
(see Figure 5–5 and Figure 5–6).
c(CO)
Table 5–8. Memory Read Timing Requirements
5416-100
UNIT
MIN
MAX
†
t
t
t
t
Access time, read data access from address valid, first read access
4H–9
2H–9
ns
ns
ns
ns
a(A)M1
a(A)M2
su(D)R
h(D)R
†
Access time, read data access from address valid, consecutive read accesses
Setup time, read data valid before CLKOUT low
7
0
Hold time, read data valid after CLKOUT low
†
Address,R/W, PS, DS, and IS timings are all included in timings referenced as address.
Table 5–9. Memory Read Switching Characteristics
5416-100
PARAMETER
UNIT
MIN
– 1*
– 1*
– 1*
MAX
†
t
Delay time, CLKOUT low to address valid
Delay time, CLKOUT low to MSTRB low
Delay time, CLKOUT low to MSTRB high
4
4
ns
ns
ns
d(CLKL-A)
t
d(CLKL-MSL)
t
4*
d(CLKL-MSH)
* Not production tested.
†
Address,R/W, PS, DS, and IS timings are all included in timings referenced as address.
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April 2003 – Revised July 2003
SGUS035A
Electrical Specifications
CLKOUT
t
d(CLKL-A)
†
A[22:0]
t
d(CLKL-MSL)
t
d(CLKL-MSH)
t
a(A)M1
D[15:0]
MSTRB
t
su(D)R
t
h(D)R
†
R/W
†
PS/DS
†
Address,R/W, PS, DS, and IS timings are all included in timings referenced as address.
Figure 5–5. Nonconsecutive Mode Memory Reads
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SGUS035A
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Electrical Specifications
CLKOUT
t
d(CLKL-A)
t
t
t
d(CLKL-MSL)
d(CLKL-A)
d(CLKL-A)
†
A[22:0]
t
t
d(CLKL-MSH)
a(A)M1
t
a(A)M2
D[15:0]
MSTRB
t
t
su(D)R
su(D)R
t
t
h(D)R
h(D)R
†
R/W
†
PS/DS
†
Address,R/W, PS, DS, and IS timings are all included in timings referenced as address.
Figure 5–6. Consecutive Mode Memory Reads
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April 2003 – Revised July 2003
SGUS035A
Electrical Specifications
5.8.2 Memory Write
Table 5–10 assumes testing over recommended operating conditions with MSTRB = 0 and H = 0.5t
Figure 5–7).
(see
c(CO)
Table 5–10. Memory Write Switching Characteristics
5416-100
MIN
PARAMETER
UNIT
MAX
†
t
Delay time, CLKOUT low to address valid
– 1*
4
ns
ns
ns
ns
ns
ns
ns
ns
d(CLKL-A)
†
t
Setup time, address valid before MSTRB low
Delay time, CLKOUT low to data valid
Setup time, data valid before MSTRB high
Hold time, data valid after MSTRB high
Delay time, CLKOUT low to MSTRB low
Pulse duration, MSTRB low
2H – 3
su(A)MSL
t
– 1*
2H – 5
2H – 5*
– 1*
4
2H + 6
2H + 6*
4
d(CLKL-D)W
t
su(D)MSH
t
h(D)MSH
t
d(CLKL-MSL)
t
2H – 3.2*
– 1*
w(SL)MS
t
Delay time, CLKOUT low to MSTRB high
4*
d(CLKL-MSH)
* Not production tested.
†
Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.
CLKOUT
t
d(CLKL-A)
t
d(CLKL-A)
t
d(CLKL-D)W
t
su(A)MSL
†
A[22:0]
t
su(D)MSH
t
h(D)MSH
D[15:0]
t
d(CLKL-MSL)
t
d(CLKL-MSH)
t
w(SL)MS
MSTRB
†
R/W
†
PS/DS
†
Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.
Figure 5–7. Memory Write (MSTRB = 0)
52
SGUS035A
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Electrical Specifications
5.8.3 I/O Read
Table 5–11 and Table 5–12 assume testing over recommended operating conditions, IOSTRB = 0, and
H = 0.5t (see Figure 5–8).
c(CO)
Table 5–11. I/O Read Timing Requirements
5416-100
MIN MAX
4H – 9
UNIT
†
t
t
t
Access time, read data access from address valid, first read access
ns
ns
ns
a(A)M1
su(D)R
h(D)R
Setup time, read data valid before CLKOUT low
Hold time, read data valid after CLKOUT low
7
0
†
Address R/W, PS, DS, and IS timings are included in timings referenced as address.
Table 5–12. I/O Read Switching Characteristics
5416-100
MIN MAX
PARAMETER
UNIT
†
t
Delay time, CLKOUT low to address valid
Delay time, CLKOUT low to IOSTRB low
Delay time, CLKOUT low to IOSTRB high
– 1*
– 1*
– 1*
4
4
4
ns
ns
ns
d(CLKL-A)
t
d(CLKL-IOSL)
t
d(CLKL-IOSH)
* Not production tested.
†
Address R/W, PS, DS, and IS timings are included in timings referenced as address.
CLKOUT
t
t
d(CLKL-A)
d(CLKL-A)
t
d(CLKL-IOSL)
t
d(CLKL-IOSH)
†
A[22:0]
t
a(A)M1
t
su(D)R
t
h(D)R
D[15:0]
IOSTRB
†
R/W
†
IS
†
Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.
Figure 5–8. Parallel I/O Port Read (IOSTRB = 0)
53
April 2003 – Revised July 2003
SGUS035A
Electrical Specifications
5.8.4 I/O Write
Table 5–13 assumes testing over recommended operating conditions, IOSTRB = 0, and H = 0.5t
Figure 5–9).
(see
c(CO)
Table 5–13. I/O Write Switching Characteristics
5416-100
PARAMETER
UNIT
ns
MIN
– 1*
MAX
†
t
Delay time, CLKOUT low to address valid
4
d(CLKL-A)
†
t
Setup time, address valid before IOSTRB low
Delay time, CLKOUT low to write data valid
Setup time, data valid before IOSTRB high
Hold time, data valid after IOSTRB high
Delay time, CLKOUT low to IOSTRB low
Pulse duration, IOSTRB low
2H – 3
– 1*
ns
ns
ns
ns
ns
ns
ns
su(A)IOSL
t
4
d(CLKL-D)W
t
2H – 5 2H + 6*
2H – 5* 2H + 6*
su(D)IOSH
t
h(D)IOSH
t
t
t
– 1*
2H – 2*
– 1*
4
d(CLKL-IOSL)
w(SL)IOS
Delay time, CLKOUT low to IOSTRB high
4
d(CLKL-IOSH)
* Not production tested.
†
Address R/W, PS, DS, and IS timings are included in timings referenced as address.
CLKOUT
t
t
d(CLKL-A)
d(CLKL-A)
†
A[22:0]
t
d(CLKL-D)W
t
d(CLKL-D)W
t
su(A)IOSL
D[15:0]
t
su(D)IOSH
t
d(CLKL-IOSH)
t
h(D)IOSH
t
d(CLKL-IOSL)
IOSTRB
t
w(SL)IOS
†
R/W
†
IS
†
Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.
Figure 5–9. Parallel I/O Port Write (IOSTRB = 0)
54
SGUS035A
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Electrical Specifications
5.9 Ready Timing for Externally Generated Wait States
Table 5–14 and Table 5–15 assume testing over recommended operating conditions and H = 0.5t
Figure 5–10, Figure 5–11, Figure 5–12, and Figure 5–13).
(see
c(CO)
†
Table 5–14. Ready Timing Requirements for Externally Generated Wait States
5416-100
UNIT
MIN
7
MAX
t
t
t
t
t
t
Setup time, READY before CLKOUT low
Hold time, READY after CLKOUT low
ns
ns
ns
ns
ns
ns
su(RDY)
0
h(RDY)
‡
Valid time, READY after MSTRB low
4H – 6.2*
4H – 6*
v(RDY)MSTRB
h(RDY)MSTRB
v(RDY)IOSTRB
h(RDY)IOSTRB
‡
Hold time, READY after MSTRB low
4H*
4H*
‡
Valid time, READY after IOSTRB low
‡
Hold time, READY after IOSTRB low
* Not production tested.
†
Thehardwarewaitstatescanbeusedonlyinconjunctionwiththesoftwarewaitstatestoextendthebuscycles.TogeneratewaitstatesbyREADY,
at least two software wait states must be programmed. READY is not sampled until the completion of the internal software wait states.
These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT.
‡
†
Table 5–15. Ready Switching Characteristics for Externally Generated Wait States
5416-100
PARAMETER
UNIT
MIN
–1*
–1*
MAX
t
Delay time, CLKOUT low to MSC low
Delay time, CLKOUT low to MSC high
4
ns
ns
d(MSCL)
t
4
d(MSCH)
* Not production tested.
†
Thehardwarewaitstatescanbeusedonlyinconjunctionwiththesoftwarewaitstatestoextendthebuscycles.TogeneratewaitstatesbyREADY,
at least two software wait states must be programmed. READY is not sampled until the completion of the internal software wait states.
55
April 2003 – Revised July 2003
SGUS035A
Electrical Specifications
CLKOUT
A[22:0]
D[15:0]
t
su(RDY)
t
h(RDY)
READY
MSTRB
MSC
t
v(RDY)MSTRB
t
h(RDY)MSTRB
t
d(MSCL)
t
d(MSCH)
Leading
Cycle
Wait States
Generated
Internally
Wait
States
Generated
by READY
Trailing
Cycle
Figure 5–10. Memory Read With Externally Generated Wait States
56
SGUS035A
April 2003 – Revised July 2003
Electrical Specifications
CLKOUT
A[22:0]
D[15:0]
t
su(RDY)
t
h(RDY)
READY
MSTRB
MSC
t
v(RDY)MSTRB
t
h(RDY)MSTRB
t
d(MSCL)
t
d(MSCH)
Leading
Cycle
Wait
States
Generated
by READY
Wait
States
Generated
Internally
Trailing
Cycle
Figure 5–11. Memory Write With Externally Generated Wait States
57
April 2003 – Revised July 2003
SGUS035A
Electrical Specifications
CLKOUT
A[22:0]
D[15:0]
t
su(RDY)
t
h(RDY)
READY
IOSTRB
MSC
t
v(RDY)IOSTRB
t
h(RDY)IOSTRB
t
d(MSCL)
t
d(MSCH)
Leading
Cycle
Wait States
Generated
Internally
Wait
States
Generated
by READY
Trailing
Cycle
Figure 5–12. I/O Read With Externally Generated Wait States
58
SGUS035A
April 2003 – Revised July 2003
Electrical Specifications
CLKOUT
A[22:0]
D[15:0]
t
su(RDY)
t
h(RDY)
READY
IOSTRB
MSC
t
v(RDY)IOSTRB
t
h(RDY)IOSTRB
t
d(MSCL)
t
d(MSCH)
Leading
Cycle
Wait
States
Generated
Internally
Trailing
Cycle
Wait
States
Generated
by READY
Figure 5–13. I/O Write With Externally Generated Wait States
59
April 2003 – Revised July 2003
SGUS035A
Electrical Specifications
5.10 HOLD and HOLDA Timings
Table 5–16 and Table 5–17 assume testing over recommended operating conditions and H = 0.5t
Figure 5–14).
(see
c(CO)
Table 5–16. HOLD and HOLDA Timing Requirements
5416-100
UNIT
MIN
4H+8*
7
MAX
t
t
Pulse duration, HOLD low duration
ns
ns
w(HOLD)
†
Setup time, HOLD before CLKOUT low
su(HOLD)
* Not production tested.
Table 5–17. HOLD and HOLDA Switching Characteristics
5416-100
PARAMETER
UNIT
MIN
MAX
3*
t
t
t
t
t
t
Disable time, Address, PS, DS, IS high impedance from CLKOUT low
Disable time, R/W high impedance from CLKOUT low
Disable time, MSTRB, IOSTRB high impedance from CLKOUT low
Enable time, Address, PS, DS, IS valid from CLKOUT low
Enable time, R/W enabled from CLKOUT low
ns
ns
ns
ns
ns
ns
dis(CLKL-A)
dis(CLKL-RW)
dis(CLKL-S)
en(CLKL-A)
en(CLKL-RW)
en(CLKL-S)
3*
3*
2H+3*
2H+3*
2H+3*
Enable time, MSTRB, IOSTRB enabled from CLKOUT low
2
– 1*
4
ns
ns
ns
Valid time, HOLDA low after CLKOUT low
t
t
v(HOLDA)
– 1*
4*
Valid time, HOLDA high after CLKOUT low
Pulse duration, HOLDA low duration
2H–3*
w(HOLDA)
* Not production tested.
†
This input can be driven from an asynchronous source, therefore, there are no specific timing requirements with respect to CLKOUT, however,
if this timing is met, the input will be recognized on the CLKOUT edge referenced.
60
SGUS035A
April 2003 – Revised July 2003
Electrical Specifications
CLKOUT
HOLD
t
t
su(HOLD)
su(HOLD)
t
w(HOLD)
t
t
v(HOLDA)
v(HOLDA)
w(HOLDA)
t
HOLDA
t
t
en(CLKL–A)
dis(CLKL–A)
A[22:0]
PS, DS, IS
D[15:0]
R/W
t
t
t
t
dis(CLKL–RW)
dis(CLKL–S)
dis(CLKL–S)
en(CLKL–RW)
t
en(CLKL–S)
MSTRB
IOSTRB
t
en(CLKL–S)
Figure 5–14. HOLD and HOLDA Timings (HM = 1)
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April 2003 – Revised July 2003
SGUS035A
Electrical Specifications
5.11 Reset, BIO, Interrupt, and MP/MC Timings
Table 5–18 assumes testing over recommended operating conditions and H = 0.5t
Figure 5–16, and Figure 5–17).
(see Figure 5–15,
c(CO)
Table 5–18. Reset, BIO, Interrupt, and MP/MC Timing Requirements
5416-100
UNIT
MIN
2*
MAX
#
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Hold time, RS after CLKOUT low
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
h(RS)
#
Hold time, BIO after CLKOUT low
Hold time, INTn, NMI, after CLKOUT low
4
h(BIO)
†#
0
h(INT)
#
Hold time, MP/MC after CLKOUT low
‡§
4*
h(MPMC)
w(RSL)
Pulse duration, RS low
4H+3*
2H+3*
4H*
2H+2*
4H*
2H+2*
4H*
7*
Pulse duration, BIO low, synchronous
Pulse duration, BIO low, asynchronous
w(BIO)S
w(BIO)A
w(INTH)S
w(INTH)A
w(INTL)S
w(INTL)A
w(INTL)WKP
su(RS)
Pulse duration, INTn, NMI high (synchronous)
Pulse duration, INTn, NMI high (asynchronous)
Pulse duration, INTn, NMI low (synchronous)
Pulse duration, INTn, NMI low (asynchronous)
Pulse duration, INTn, NMI low for IDLE2/IDLE3 wakeup
¶#
Setup time, RS before X2/CLKIN low
Setup time, BIO before CLKOUT low
3*
#
7
su(BIO)
#
Setup time, INTn, NMI, RS before CLKOUT low
7
su(INT)
#
Setup time, MP/MC before CLKOUT low
5*
su(MPMC)
* Not production tested.
†
The external interrupts (INT0–INT3, NMI) are synchronized to the core CPU by way of a two-flip-flop synchronizer that samples these inputs
with consecutive falling edges of CLKOUT. The input to the interrupt pins is required to represent a 1–0–0 sequence at the timing that is
corresponding to three CLKOUTs sampling sequence.
IfthePLLmodeisselected,thenatpower-onsequence,oratwakeupfromIDLE3,RSmustbeheldlowforatleast50µstoensuresynchronization
and lock-in of the PLL.
‡
§
¶
#
Note that RS may cause a change in clock frequency, therefore changing the value of H.
The diagram assumes clock mode is divide-by-2 and the CLKOUT divide factor is set to no-divide mode (DIVFCT=00 field in the BSCR).
Theseinputs can be driven from an asynchronous source, therefore, there are no specific timing requirements with respect to CLKOUT, however,
if setup and hold timings are met, the input will be recognized on the CLKOUT edge referenced.
62
SGUS035A
April 2003 – Revised July 2003
Electrical Specifications
X2/CLKIN
RS, INTn, NMI
CLKOUT
t
su(RS)
t
w(RSL)
t
su(INT)
t
h(RS)
t
su(BIO)
t
h(BIO)
BIO
t
w(BIO)S
Figure 5–15. Reset and BIO Timings
CLKOUT
t
t
t
su(INT)
su(INT)
h(INT)
INTn, NMI
t
w(INTH)A
t
w(INTL)A
Figure 5–16. Interrupt Timing
CLKOUT
RS
t
h(MPMC)
t
su(MPMC)
MP/MC
Figure 5–17. MP/MC Timing
63
April 2003 – Revised July 2003
SGUS035A
Electrical Specifications
5.12 Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timings
Table 5–19 assumes testing over recommended operating conditions and H = 0.5t
(see Figure 5–18).
c(CO)
Table 5–19. Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Switching Characteristics
5416-100
PARAMETER
UNIT
MIN
– 1*
MAX
t
Delay time, CLKOUT low to IAQ low
4
ns
ns
ns
ns
ns
ns
ns
d(CLKL-IAQL)
t
Delay time, CLKOUT low to IAQ high
Delay time, CLKOUT low to IACK low
Delay time, CLKOUT low to IACK high
Delay time, CLKOUT low to address valid
Pulse duration, IAQ low
– 1*
4
4
4
4
d(CLKL-IAQH)
t
– 1.2*
– 1*
d(CLKL-IACKL)
t
d(CLKL-IACKH)
d(CLKL-A)
w(IAQL)
t
t
t
– 1*
2H – 2*
2H – 3*
Pulse duration, IACK low
w(IACKL)
* Not production tested.
CLKOUT
t
d(CLKL–A)
t
d(CLKL–A)
A[22:0]
t
t
t
d(CLKL–IAQH)
d(CLKL–IACKH)
d(CLKL–IAQL)
t
w(IAQL)
IAQ
t
d(CLKL–IACKL)
t
w(IACKL)
IACK
Figure 5–18. Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timings
64
SGUS035A
April 2003 – Revised July 2003
Electrical Specifications
5.13 External Flag (XF) and TOUT Timings
Table 5–20 assumes testing over recommended operating conditions and H = 0.5t
Figure 5–20).
(see Figure 5–19 and
c(CO)
Table 5–20. External Flag (XF) and TOUT Switching Characteristics
5416-100
PARAMETER
UNIT
MIN
– 1*
MAX
Delay time, CLKOUT low to XF high
4
t
ns
d(XF)
Delay time, CLKOUT low to XF low
Delay time, CLKOUT low to TOUT high
Delay time, CLKOUT low to TOUT low
Pulse duration, TOUT
– 1*
4
4*
4
t
t
t
– 1*
ns
ns
ns
d(TOUTH)
d(TOUTL)
w(TOUT)
– 1*
2H – 4*
* Not production tested.
CLKOUT
t
d(XF)
XF
Figure 5–19. External Flag (XF) Timing
CLKOUT
TOUT
t
t
d(TOUTL)
d(TOUTH)
t
w(TOUT)
Figure 5–20. TOUT Timing
65
April 2003 – Revised July 2003
SGUS035A
Electrical Specifications
5.14 Multichannel Buffered Serial Port (McBSP) Timing
5.14.1 McBSP Transmit and Receive Timings
Table 5–21 and Table 5–22 assume testing over recommended operating conditions (see Figure 5–21 and
Figure 5–22).
†
Table 5–21. McBSP Transmit and Receive Timing Requirements
5416-100
UNIT
MIN
MAX
‡
§
t
t
Cycle time, BCLKR/X
BCLKR/X ext
BCLKR/X ext
BCLKR int
BCLKR ext
BCLKR int
BCLKR ext
BCLKR int
BCLKR ext
BCLKR int
BCLKR ext
BCLKX int
BCLKX ext
BCLKX int
BCLKX ext
BCLKR/X ext
BCLKR/X ext
4P
ns
ns
c(BCKRX)
‡
§
Pulse duration, BCLKR/X high or BCLKR/X low
2P–1*
w(BCKRX)
8
1
1
2
7
1
2
3
8
1
0
2
t
t
t
t
t
t
Setup time, external BFSR high before BCLKR low
Hold time, external BFSR high after BCLKR low
Setup time, BDR valid before BCLKR low
ns
ns
ns
ns
ns
ns
su(BFRH-BCKRL)
h(BCKRL-BFRH)
su(BDRV-BCKRL)
h(BCKRL-BDRV)
su(BFXH-BCKXL)
h(BCKXL-BFXH)
Hold time, BDR valid after BCLKR low
Setup time, external BFSX high before BCLKX low
Hold time, external BFSX high after BCLKX low
t
t
Rise time, BCKR/X
Fall time, BCKR/X
6*
6*
ns
ns
r(BCKRX)
f(BCKRX)
* Not production tested.
†
‡
CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
Note that in some cases, for example when driving another 54x device McBSP, maximum serial port clocking rates may not be achievable at
maximum CPU clock frequency due to transmitted data timings and corresponding receive timing requirements. A separate detailed timing
analysis should be performed for each specific McBSP interface.
§
P = 1 / (2 * processor clock)
66
SGUS035A
April 2003 – Revised July 2003
Electrical Specifications
†
Table 5–22. McBSP Transmit and Receive Switching Characteristics
5416-100
PARAMETER
UNIT
MIN MAX
#
‡
§
§
t
t
t
Cycle time, BCLKR/X
BCLKR/X int
BCLKR/X int
4P
D – 1*
C – 1*
ns
ns
c(BCKRX)
#
§
§
3
Pulse duration, BCLKR/X high
D + 1*
w(BCKRXH)
w(BCKRXL)
#
Pulse duration, BCLKR/X low
BCLKR/X int
BCLKR int
BCLKR ext
BCLKX int
BCLKX ext
BCLKX int
BCLKX ext
BCLKX int
BCLKX ext
BCLKX int
BCLKX ext
BFSX int
C + 1*
ns
ns
ns
– 3*
0*
t
t
Delay time, BCLKR high to internal BFSR valid
Delay time, BCLKX high to internal BFSX valid
d(BCKRH-BFRV)
d(BCKXH-BFXV)
11
5
– 1*
3*
ns
ns
11
6*
Disable time, BCLKX high to BDX high impedance following last data
bit of transfer
t
dis(BCKXH-BDXHZ)
10*
10
20
20
30
7*
¶
– 1*
DXENA = 0
Delay time, BCLKX high to BDX valid
DXENA = 1
3*
t
ns
ns
d(BCKXH-BDXV)
¶
– 1*
2.8*
¶
–1.2*
Delay time, BFSX high to BDX valid
ONLY applies when in data delay 0 (XDATDLY = 00b) mode
t
d(BFXH-BDXV)
BFSX ext
3*
11*
* Not production tested.
†
‡
§
CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
P = 1 / (2 * processor clock)
T
C
D
=
=
=
BCLKRX period = (1 + CLKGDV) * 2P
BCLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even
BCLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2P when CLKGDV is even
¶
#
Minimum delay times also represent minimum output hold times.
Note that in some cases, for example when driving another 54x device McBSP, maximum serial port clocking rates may not be achievable at
maximum CPU clock frequency due to transmitted data timings and corresponding receive timing requirements. A separate detailed timing
analysis should be performed for each specific McBSP interface.
t
c(BCKRX)
t
w(BCKRXH)
w(BCKRXL)
t
t
r(BCKRX)
f(BCKRX)
t
BCLKR
BFSR (int)
BFSR (ext)
BDR
t
d(BCKRH-BFRV)
t
d(BCKRH-BFRV)
t
su(BFRH-BCKRL)
t
h(BCKRL-BFRH)
t
su(BDRV-BCKRL)
t
h(BCKRL-BDRV)
(n-2)
(n-3)
Bit(n-1)
Figure 5–21. McBSP Receive Timings
67
April 2003 – Revised July 2003
SGUS035A
Electrical Specifications
t
c(BCKRX)
t
t
w(BCKRXH)
t
t
f(BCKRX)
r(BCKRX)
w(BCKRXL)
BCLKX
t
d(BCKXH-BFXV)
BFSX (int)
BFSX (ext)
t
h(BCKXL-BFXH)
t
su(BFXH-BCKXL)
BFSX
(XDATDLY=00b)
t
d(BCKXH-BDXV)
t
d(BFXH-BDXV)
t
t
dis(BCKXH-BDXHZ)
d(BCKXH-BDXV)
BDX
Bit 0
Bit(n-1)
(n-2)
(n-3)
Figure 5–22. McBSP Transmit Timings
68
SGUS035A
April 2003 – Revised July 2003
Electrical Specifications
5.14.2 McBSP General-Purpose I/O Timing
Table 5–23 and Table 5–24 assume testing over recommended operating conditions (see Figure 5–23).
Table 5–23. McBSP General-Purpose I/O Timing Requirements
5416-100
UNIT
MIN
7
MAX
†
t
t
Setup time, BGPIOx input mode before CLKOUT high
ns
ns
su(BGPIO-COH)
†
Hold time, BGPIOx input mode after CLKOUT high
0
h(COH-BGPIO)
†
BGPIOx refers to BCLKRx, BFSRx, BDRx, BCLKXx, or BFSXx when configured as a general-purpose input.
Table 5–24. McBSP General-Purpose I/O Switching Characteristics
5416-100
PARAMETER
UNIT
MIN
MAX
‡
t
Delay time, CLKOUT high to BGPIOx output mode
– 2*
4
ns
d(COH-BGPIO)
* Not production tested.
‡
BGPIOx refers to BCLKRx, BFSRx, BCLKXx, BFSXx, or BDXx when configured as a general-purpose output.
t
t
su(BGPIO-COH)
d(COH-BGPIO)
CLKOUT
t
h(COH-BGPIO)
BGPIOx Input
†
Mode
BGPIOx Output
‡
Mode
†
‡
BGPIOx refers to BCLKRx, BFSRx, BDRx, BCLKXx, or BFSXx when configured as a general-purpose input.
BGPIOx refers to BCLKRx, BFSRx, BCLKXx, BFSXx, or BDXx when configured as a general-purpose output.
Figure 5–23. McBSP General-Purpose I/O Timings
69
April 2003 – Revised July 2003
SGUS035A
Electrical Specifications
5.14.3 McBSP as SPI Master or Slave Timing
Table 5–25 to Table 5–32 assume testing over recommended operating conditions (see Figure 5–24,
Figure 5–25, Figure 5–26, and Figure 5–27).
†
Table 5–25. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
5416-100
MASTER
SLAVE
MIN MAX
UNIT
MIN
12
4
MAX
‡
t
t
Setup time, BDR valid before BCLKX low
Hold time, BDR valid after BCLKX low
2.2 – 6P*
ns
ns
su(BDRV-BCKXL)
‡
5 + 12P*
h(BCKXL-BDRV)
* Not production tested.
†
‡
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
P = 1 / (2 * processor clock)
†
Table 5–26. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
5416-100
§
MASTER
SLAVE
MIN MAX
PARAMETER
UNIT
MIN
MAX
¶
t
Hold time, BFSX low after BCLKX low
T – 3*
T + 4
ns
ns
ns
h(BCKXL-BFXL)
d(BFXL-BCKXH)
d(BCKXH-BDXV)
#
t
t
Delay time, BFSX low to BCLKX high
C – 4* C + 3*
– 4*
‡
‡
Delay time, BCLKX high to BDX valid
5
6P + 2*
10P + 17
Disable time, BDX high impedance following last data bit from
BCLKX low
t
C – 2* C + 3*
ns
dis(BCKXL-BDXHZ)
Disable time, BDX high impedance following last data bit from
BFSX high
‡
‡
‡
‡
t
t
2P– 4*
6P + 17*
ns
ns
dis(BFXH-BDXHZ)
Delay time, BFSX low to BDX valid
4P+ 2*
8P + 17*
d(BFXL-BDXV)
* Not production tested.
†
‡
§
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
P = 1 / (2 * processor clock)
T
C
=
=
BCLKX period = (1 + CLKGDV) * 2P
BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even
¶
FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
#
MSB
LSB
BCLKX
BFSX
t
h(BCKXL-BFXL)
t
d(BFXL-BCKXH)
t
dis(BFXH-BDXHZ)
t
d(BFXL-BDXV)
t
t
d(BCKXH-BDXV)
(n-2)
dis(BCKXL-BDXHZ)
BDX
BDR
Bit 0
Bit(n-1)
(n-3)
(n-4)
t
su(BDRV-BCLXL)
t
h(BCKXL-BDRV)
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 5–24. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
70
SGUS035A
April 2003 – Revised July 2003
Electrical Specifications
†
Table 5–27. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
5416-100
MASTER
SLAVE
MIN MAX
UNIT
MIN
12
4
MAX
‡
t
t
Setup time, BDR valid before BCLKX low
Hold time, BDR valid after BCLKX high
2.2 – 6P*
5 + 12P*
ns
ns
su(BDRV-BCKXL)
‡
h(BCKXH-BDRV)
* Not production tested.
†
‡
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
P = 1 / (2 * processor clock)
†
Table 5–28. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
5416-100
§
MASTER
SLAVE
MIN
PARAMETER
UNIT
MIN
MAX
MAX
¶
t
Hold time, BFSX low after BCLKX low
C –3*
C + 4
ns
ns
ns
h(BCKXL-BFXL)
d(BFXL-BCKXH)
d(BCKXL-BDXV)
#
t
t
Delay time, BFSX low to BCLKX high
Delay time, BCLKX low to BDX valid
T – 4* T + 3*
‡
‡
‡
‡
‡
‡
– 4*
5
6P + 2*
10P + 17
10P + 17*
8P + 17*
Disable time, BDX high impedance following last data bit from
BCLKX low
t
– 2*
4* 6P – 4*
ns
ns
dis(BCKXL-BDXHZ)
t
Delay time, BFSX low to BDX valid
D – 2* D + 4* 4P + 2*
d(BFXL-BDXV)
* Not production tested.
†
‡
§
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
P = 1 / (2 * processor clock)
T
C
D
=
=
=
BCLKX period = (1 + CLKGDV) * 2P
BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even
BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2P when CLKGDV is even
¶
FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
#
MSB
LSB
BCLKX
t
t
d(BFXL-BCKXH)
h(BCKXL-BFXL)
BFSX
t
t
t
d(BCKXL-BDXV)
d(BFXL-BDXV)
dis(BCKXL-BDXHZ)
BDX
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
t
su(BDRV-BCKXL)
t
h(BCKXH-BDRV)
BDR
Bit 0
(n-2)
(n-3)
(n-4)
Figure 5–25. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
71
April 2003 – Revised July 2003
SGUS035A
Electrical Specifications
†
Table 5–29. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
5416-100
MASTER
SLAVE
MIN MAX
UNIT
MIN
12
4
MAX
‡
t
t
Setup time, BDR valid before BCLKX high
Hold time, BDR valid after BCLKX high
2 – 6P*
5 + 12P*
ns
ns
su(BDRV-BCKXH)
‡
h(BCKXH-BDRV)
* Not production tested.
†
‡
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
P = 1 / (2 * processor clock)
†
Table 5–30. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
5416-100
§
MASTER
SLAVE
MIN
PARAMETER
UNIT
MIN
MAX
MAX
¶
t
Hold time, BFSX low after BCLKX high
T – 3*
T + 4
ns
ns
ns
h(BCKXH-BFXL)
d(BFXL-BCKXL)
d(BCKXL-BDXV)
#
t
t
Delay time, BFSX low to BCLKX low
Delay time, BCLKX low to BDX valid
D – 4* D + 3*
– 4*
‡
‡
5
6P + 2*
10P + 17
Disable time, BDX high impedance following last data bit from
BCLKX high
t
D – 2* D + 3*
ns
dis(BCKXH-BDXHZ)
Disable time, BDX high impedance following last data bit from
BFSX high
‡
‡
‡
‡
t
t
2P – 4*
6P + 17*
ns
ns
dis(BFXH-BDXHZ)
Delay time, BFSX low to BDX valid
4P + 2*
8P + 17*
d(BFXL-BDXV)
* Not production tested.
†
‡
§
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
P = 1 / (2 * processor clock)
T
D
=
=
BCLKX period = (1 + CLKGDV) * 2P
BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2P when CLKGDV is even
¶
FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
#
LSB
MSB
BCLKX
BFSX
t
h(BCKXH-BFXL)
t
d(BFXL-BCKXL)
t
t
d(BFXL-BDXV)
dis(BFXH-BDXHZ)
t
t
t
d(BCKXL-BDXV)
dis(BCKXH-BDXHZ)
BDX
BDR
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
t
su(BDRV-BCKXH)
h(BCKXH-BDRV)
(n-2)
Bit 0
(n-3)
(n-4)
Figure 5–26. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
72
SGUS035A
April 2003 – Revised July 2003
Electrical Specifications
†
Table 5–31. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
5416-100
MASTER
SLAVE
MIN MAX
UNIT
MIN
12
4
MAX
‡
t
t
Setup time, BDR valid before BCLKX low
Hold time, BDR valid after BCLKX low
2 – 6P*
5 + 12P*
ns
ns
su(BDRV-BCKXL)
‡
h(BCKXL-BDRV)
* Not production tested.
†
‡
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
P = 1 / (2 * processor clock)
†
Table 5–32. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)
5416-100
§
MASTER
SLAVE
MIN MAX
PARAMETER
UNIT
MIN
MAX
¶
t
Hold time, BFSX low after BCLKX high
D – 3*
D + 4
ns
ns
ns
h(BCKXH-BFXL)
d(BFXL-BCKXL)
d(BCKXH-BDXV)
#
t
t
Delay time, BFSX low to BCLKX low
Delay time, BCLKX high to BDX valid
T – 4* T + 3*
‡
‡
‡
‡
‡
‡
– 4*
5
6P + 2*
10P + 17
10P + 17*
8P + 17*
Disable time, BDX high impedance following last data bit from
BCLKX high
t
– 2*
4* 6P – 4*
ns
ns
dis(BCKXH-BDXHZ)
t
Delay time, BFSX low to BDX valid
C – 2* C + 4* 4P + 2*
d(BFXL-BDXV)
* Not production tested.
†
‡
§
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
P = 1 / (2 * processor clock)
T
C
D
=
=
=
BCLKX period = (1 + CLKGDV) * 2P
BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even
BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2P when CLKGDV is even
¶
FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
#
MSB
LSB
BCLKX
t
t
h(BCKXH-BFXL)
d(BFXL-BCKXL)
BFSX
t
t
t
d(BCKXH-BDXV)
(n-2)
dis(BCKXH-BDXHZ)
d(BFXL-BDXV)
BDX
Bit 0
Bit(n-1)
Bit(n-1)
(n-3)
(n-4)
t
su(BDRV-BCKXL)
t
h(BCKXL-BDRV)
BDR
Bit 0
(n-2)
(n-3)
(n-4)
Figure 5–27. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
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April 2003 – Revised July 2003
SGUS035A
Electrical Specifications
5.15 Host-Port Interface Timing
5.15.1 HPI8 Mode
Table 5–33 and Table 5–34 assume testing over recommended operating conditions and P = 1 / (2 * processor
clock) (see Figure 5–28 through Figure 5–31). In the following tables, DS refers to the logical OR of HCS,
HDS1, and HDS2. HD refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.). HAD stands for HCNTL0,
HCNTL1, and HR/W.
Table 5–33. HPI8 Mode Timing Requirements
5416-100
UNIT
MIN
MAX
Setup time, HBIL valid before DS low (when HAS is not used), or HBIL valid before HAS
low
t
6
ns
su(HBV-DSL)
t
t
t
t
t
t
Hold time, HBIL valid after DS low (when HAS is not used), or HBIL valid after HAS low
Setup time, HAS low before DS low
3
8*
13*
7*
3
ns
ns
ns
ns
ns
ns
h(DSL-HBV)
su(HSL-DSL)
w(DSL)
Pulse duration, DS low
Pulse duration, DS high
w(DSH)
Setup time, HD valid before DS high, HPI write
Hold time, HD valid after DS high, HPI write
su(HDV-DSH)
h(DSH-HDV)W
2
t
Setup time, HDx input valid before CLKOUT high, HDx configured as general-purpose input
Hold time, HDx input valid before CLKOUT high, HDx configured as general-purpose input
6*
0*
ns
ns
su(GPIO-COH)
h(GPIO-COH)
t
* Not production tested.
74
SGUS035A
April 2003 – Revised July 2003
Electrical Specifications
Table 5–34. HPI8 Mode Switching Characteristics
5416-100
PARAMETER
UNIT
MIN
0*
MAX
t
Enable time, HD driven from DS low
Case 1a: Memory accesses when DMAC is active
10*
ns
en(DSL-HD)
36P+10–t
*
w(DSH)
†
in 32-bit mode and t
< 36P
w(DSH)
Case 1b: Memory accesses when DMAC is active
10*
†
in 32-bit mode and t
≥ 36P
w(DSH)
Case 1c: Memory accesses when DMAC is active
18P+10–t
*
w(DSH)
†
in 16-bit mode and t
< I8P
w(DSH)
Delay time, DS low to HD
valid for first byte of an HPI
read
Case 1d: Memory accesses when DMAC is active
t
d(DSL-HDV1)
ns
10*
†
in 16-bit mode and t
≥ I8P
w(DSH)
Case 2a: Memory accesses when DMAC is inactive
10P+10–t
*
w(DSH)
†
< 10P
and t
w(DSH)
Case 2b: Memory accesses when DMAC is inactive
10*
†
and t
≥ 10P
w(DSH)
Case 3: Register accesses
10*
10*
t
d(DSL-HDV2)
Delay time, DS low to HD valid for second byte of an HPI read
Hold time, HD valid after DS high, for a HPI read
Valid time, HD valid after HRDY high
ns
ns
ns
ns
t
0*
h(DSH-HDV)R
t
2*
8*
v(HYH-HDV)
‡
t
Delay time, DS high to HRDY low
d(DSH-HYL)
Case 1a: Memory accesses when DMAC is active
in 16-bit mode
18P+6*
36P+6*
†
Case 1b: Memory accesses when DMAC is active
Delay time, DS high to HRDY
high
t
ns
†
d(DSH-HYH)
in 32-bit mode
‡
†
Case 2: Memory accesses when DMAC is inactive
10P+6*
§
Case 3: Write accesses to HPIC register
6P+6*
6*
9
ns
ns
ns
t
Delay time, HCS low/high to HRDY low/high
Delay time, CLKOUT high to HRDY high
Delay time, CLKOUT high to HINT change
d(HCS-HRDY)
t
d(COH-HYH)
t
6
d(COH-HTX)
Delay time, CLKOUT high to HDx output change. HDx is configured as a
general-purpose output
t
5*
ns
d(COH-GPIO)
* Not production tested.
†
DMAC stands for direct memory access controller (DMAC). The HPI8 shares the internal DMA bus with the DMAC, thus HPI8 access times
are affected by DMAC activity.
‡
§
The HRDY output is always high when the HCS input is high, regardless of DS timings.
This timing applies when writing a one to the DSPINT bit or HINT bit of the HPIC register. All other writes to the HPIC occur asynchronously,
and do not cause HRDY to be deasserted.
75
April 2003 – Revised July 2003
SGUS035A
Electrical Specifications
Second Byte
First Byte
Second Byte
HAS
t
su(HBV-DSL)
t
su(HSL-DSL)
t
h(DSL-HBV)
†
HAD
Valid
Valid
‡
t
su(HBV-DSL)
‡
t
h(DSL-HBV)
HBIL
HCS
t
w(DSH)
t
w(DSL)
HDS
t
d(DSH-HYH)
t
d(DSH-HYL)
HRDY
t
en(DSL-HD)
t
d(DSL-HDV2)
t
d(DSL-HDV1)
Valid
t
h(DSH-HDV)R
HD READ
Valid
Valid
t
su(HDV-DSH)
t
v(HYH-HDV)
Valid
t
h(DSH-HDV)W
HD WRITE
Valid
Valid
t
d(COH-HYH)
Processor
CLK
†
‡
HAD refers to HCNTL0, HCNTL1, and HR/W.
When HAS is not used (HAS always high)
Figure 5–28. Using HDS to Control Accesses (HCS Always Low)
76
SGUS035A
April 2003 – Revised July 2003
Electrical Specifications
Second Byte
First Byte
Second Byte
HCS
HDS
t
d(HCS-HRDY)
HRDY
Figure 5–29. Using HCS to Control Accesses
CLKOUT
t
d(COH-HTX)
HINT
Figure 5–30. HINT Timing
CLKOUT
t
su(GPIO-COH)
t
h(GPIO-COH)
†
†
GPIOx Input Mode
t
d(COH-GPIO)
GPIOx Output Mode
†
GPIOx refers to HD0, HD1, HD2, ...HD7, when the HD bus is configured for general-purpose input/output (I/O).
†
Figure 5–31. GPIOx Timings
77
April 2003 – Revised July 2003
SGUS035A
Electrical Specifications
5.15.2 HPI16 Mode
Table 5–35 and Table 5–36 assume testing over recommended operating conditions and P = 1 / (2 * processor
clock) (see Figure 5–32 through Figure 5–34). In the following tables, DS refers to the logical OR of HCS,
HDS1, and HDS2, and HD refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.). These timings are
shown assuming that HDS is the signal controlling the transfer. See the TMS320C54x DSP Reference Set,
Volume 5: Enhanced Peripherals (literature number SPRU302) for addition information.
Table 5–35. HPI16 Mode Timing Requirements
5416-100
UNIT
MIN
6
MAX
t
t
Setup time, HR/W valid before DS falling edge
Hold time, HR/W valid after DS falling edge
ns
ns
su(HBV-DSL)
5
h(DSL-HBV)
t
t
t
t
t
Setup time, address valid before DS rising edge (write)
Setup time, address valid before DS falling edge (read)
Hold time, address valid after DS rising edge
Pulse duration, DS low
5*
ns
ns
ns
ns
ns
su(HAV-DSH)
su(HAV-DSL)
h(DSH-HAV)
w(DSL)
–(4P – 6)*
1*
30*
Pulse duration, DS high
10*
w(DSH)
Reads 10P + 30*
Writes 10P + 10*
Reads 16P + 30*
Writes 16P + 10*
Reads 24P + 30*
Writes 24P + 10*
8
Memory accesses with no DMA activity.
Cycle time, DS rising edge to
next DS rising edge
t
Memoryaccesses with 16-bit DMA activity.
Memoryaccesses with 32-bit DMA activity.
ns
c(DSH-DSH)
t
t
Setup time, HD valid before DS rising edge
Hold time, HD valid after DS rising edge, write
ns
ns
su(HDV-DSH)W
2
h(DSH-HDV)W
* Not production tested.
78
SGUS035A
April 2003 – Revised July 2003
Electrical Specifications
Table 5–36. HPI16 Mode Switching Characteristics
5416-100
PARAMETER
UNIT
MIN
MAX
10*
t
Delay time, DS low to HD driven
0*
d(DSL-HDD)
Case 1a: Memory accesses initiated immediately following a write
when DMAC is active in 32-bit mode and t was < 26P
48P +
20 – t
*
*
*
w(DSH)
w(DSH)
Case 1b: Memory access not immediately following a write when
DMAC is active in 32-bit mode
24P + 20*
Delay time,
DS low to HD
valid for first
word of an
HPI read
Case 1c: Memory accesses initiated immediately following a write
32P +
20 – t
w(DSH)
when DMAC is active in 16-bit mode and t
w(DSH)
was < 18P
ns
t
d(DSL-HDV1)
Case 1d: Memory accesses not immediately following a write when
DMAC is active in 16-bit mode
16P + 20*
Case 2a: Memory accesses initiated immediately following a write
20P +
20 – t
w(DSH)
when DMAC is inactive and t
w(DSH)
was < 10P
Case 2b: Memory accesses not immediately following a write when
DMAC is inactive
10P + 20*
Memory writes when no DMA is active
10P + 5*
16P + 5*
24P + 5*
7*
Delay
DS high to
HRDY high
time,
Memory writes with one or more 16-bit DMA channels active
Memory writes with one or more 32-bit DMA channels active
t
ns
d(DSH-HYH)
ns
ns
ns
ns
ns
t
Valid time, HD valid after HRDY high
Hold time, HD valid after DS rising edge, read
Delay time, CLKOUT rising edge to HRDY high
Delay time, DS low to HRDY low
v(HYH-HDV)
t
1*
6*
h(DSH-HDV)R
t
5
d(COH-HYH)
t
12*
d(DSL-HYL)
t
Delay time, DS high to HRDY low
12*
d(DSH–HYL)
* Not production tested.
79
April 2003 – Revised July 2003
SGUS035A
Electrical Specifications
HCS
t
w(DSH)
t
c(DSH–DSH)
HDS
t
t
su(HBV–DSL)
w(DSL)
t
su(HBV–DSL)
h(DSL–HBV)
t
t
h(DSL–HBV)
HR/W
t
su(HAV–DSL)
t
h(DSH–HAV)
HA[17:0]
Valid Address
Valid Address
t
h(DSH–HDV)R
t
d(DSL–HDV1)
t
t
h(DSH–HDV)R
d(DSL–HDV1)
Data
HD[15:0]
HRDY
Data
t
d(DSL–HDD)
t
d(DSL–HDD)
t
v(HYH–HDV)
t
v(HYH–HDV)
t
t
d(DSL–HYL)
d(DSL–HYL)
Figure 5–32. Nonmultiplexed Read Timings
80
SGUS035A
April 2003 – Revised July 2003
Electrical Specifications
HCS
HDS
t
w(DSH)
t
c(DSH–DSH)
t
su(HBV–DSL)
t
su(HBV–DSL)
t
t
h(DSL–HBV)
h(DSL–HBV)
HR/W
t
su(HAV–DSH)
t
w(DSL)
t
h(DSH–HAV)
Valid Address
Valid Address
su(HDV–DSH)W
HA[17:0]
HD[15:0]
HRDY
t
t
su(HDV–DSH)W
t
h(DSH–HDV)W
t
h(DSH–HDV)W
Data Valid
Data Valid
t
d(DSH–HYH)
t
d(DSH–HYL)
Figure 5–33. Nonmultiplexed Write Timings
HRDY
t
d(COH–HYH)
CLKOUT
Figure 5–34. HRDY Relative to CLKOUT
81
April 2003 – Revised July 2003
SGUS035A
Mechanical Data
6
Mechanical Data
6.1 Ceramic Quad Flatpack Mechanical Data
HFG (S-CQFP-F164)
CERAMIC QUAD FLATPACK WITH NCTB
1.140 (28,96)
SQ
1.120 (28,45)
0.325 (8,26)
1.000 (25,40)
BSC
Tie Bar Width
”A”
0.275 (6,99)
41
1
42
164
1.520 (38,61)
1.480 (37,59)
2.505 (63,63)
2.485 (63,12)
82
124
83
123
”C”
1.150 (29,21)
BSC 8 Places
”B”
0.061 (1,55)
DIA 4 Places
0.059 (1,50)
0.105 (2,67) MAX
0.018 (0,46) MAX
0.010 (0,25)
0.006 (0,15)
164 X
BRAZE
0.014 (0,36)
0.002 (0,05)
0.040 (1,02)
0.030 (0,76)
0.009 (0,23)
0.004 (0,10)
0.020 (0,51) MAX
DETAIL ”B”
0.130 (3,30) MAX
0,025 (0,64)
DETAIL ”A”
DETAIL ”C”
4040231-9/J 01/99
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Ceramic quad flatpack with flat leads brazed to non-conductive tie bar carrier
D. This package is hermetically sealed with a metal lid.
E. The leads are gold-plated and can be solder-dipped.
F. Leads not shown for clarity purposes
G. Falls within JEDEC MO-113AA (REV D)
Figure 6–1. SMJ320VC5416 164-Pin Ceramic Quad Flatpack (HFG)
82
SGUS035A
April 2003 – Revised July 2003
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