SMJ32C6411 [TI]
FIXED-POINT DIGITAL SIGNAL PROCESSORS; 定点数字信号处理器
| 型号： | SMJ32C6411 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| 文件： | 总133页 (文件大小：2062K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SGUS050A − JANUARY 2004 − REVISED MARCH 2004
ꢀ
ꢀ
Highest-Performance Fixed-Point Digital
Signal Processors (DSPs)
− 2-, 1.67-, 1.39-ns Instruction Cycle Time
− 600-MHz Clock Rate
− Eight 32-Bit Instructions/Cycle
− Twenty-Eight Operations/Cycle
− 4800 MIPS
− Fully Software-Compatible With C62x
− C6414/15/16 Devices Pin-Compatible
ꢀ
Two External Memory Interfaces (EMIFs)
− One 64-Bit (EMIFA), One 16-Bit (EMIFB)
− Glueless Interface to Asynchronous
Memories (SRAM and EPROM) and
Synchronous Memories (SDRAM,
SBSRAM, ZBT SRAM, and FIFO)
− 1280M-Byte Total Addressable External
Memory Space
ꢀ
ꢀ
ꢀ
Enhanced Direct-Memory-Access (EDMA)
Controller (64 Independent Channels)
VelociTI.2 Extensions to VelociTI
Advanced Very-Long-Instruction-Word
(VLIW) TMS320C64x DSP Core
− Eight Highly Independent Functional
Units With VelociTI.2 Extensions:
− Six ALUs (32-/40-Bit), Each Supports
Single 32-Bit, Dual 16-Bit, or Quad
8-Bit Arithmetic per Clock Cycle
− Two Multipliers Support
Host-Port Interface (HPI)
− User-Configurable Bus Width (32-/16-Bit)
32-Bit/33-MHz, 3.3-V PCI Master/Slave
Interface Conforms to PCI Specification 2.2
[C6415/C6416 ]
− Three PCI Bus Address Registers:
Prefetchable Memory
Non-Prefetchable Memory I/O
− Four-Wire Serial EEPROM Interface
− PCI Interrupt Request Under DSP
Program Control
Four 16 x 16-Bit Multiplies
(32-Bit Results) per Clock Cycle or
Eight 8 x 8-Bit Multiplies
(16-Bit Results) per Clock Cycle
− Non-Aligned Load-Store Architecture
− 64 32-Bit General-Purpose Registers
− Instruction Packing Reduces Code Size
− All Instructions Conditional
− DSP Interrupt Via PCI I/O Cycle
ꢀ
Three Multichannel Buffered Serial Ports
− Direct Interface to T1/E1, MVIP, SCSA
Framers
− Up to 256 Channels Each
ꢀ
Instruction Set Features
− Byte-Addressable (8-/16-/32-/64-Bit Data)
− 8-Bit Overflow Protection
− Bit-Field Extract, Set, Clear
− Normalization, Saturation, Bit-Counting
− VelociTI.2 Increased Orthogonality
Viterbi Decoder Coprocessor (VCP) [C6416]
− Supports Over 500 7.95-Kbps AMR
− Programmable Code Parameters
− ST-Bus-Switching-, AC97-Compatible
− Serial Peripheral Interface (SPI)
Compatible (Motorola)
ꢀ
ꢀ
Three 32-Bit General-Purpose Timers
Universal Test and Operations PHY
Interface for ATM (UTOPIA) [C6415/C6416]
− UTOPIA Level 2 Slave ATM Controller
− 8-Bit Transmit and Receive Operations
up to 50 MHz per Direction
ꢀ
ꢀ
Turbo Decoder Coprocessor (TCP) [C6416]
− Supports up to Six 2-Mbps 3GPP
(6 Iterations)
− Programmable Turbo Code and
Decoding Parameters
− User-Defined Cell Format up to 64 Bytes
ꢀ
ꢀ
ꢀ
ꢀ
Sixteen General-Purpose I/O (GPIO) Pins
Flexible PLL Clock Generator
†
IEEE-1149.1 (JTAG )
ꢀ
L1/L2 Memory Architecture
− 128K-Bit (16K-Byte) L1P Program Cache
(Direct Mapped)
− 128K-Bit (16K-Byte) L1D Data Cache
(2-Way Set-Associative)
− 8M-Bit (1024K-Byte) L2 Unified Mapped
RAM/Cache (Flexible Allocation)
Boundary-Scan-Compatible
570-Pin Grid Array (PGA) Package (GAD
Suffix)
ꢀ
0.13-µm/6-Level Cu Metal Process (CMOS)
3.3-V I/Os, 1.4-V Internal
ꢀ
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
C62x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
†
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
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Copyright 2004, Texas Instruments Incorporated
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1
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SGUS050A − JANUARY 2004 − REVISED MARCH 2004
Table of Contents
revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
GAD PGA package (bottom view) . . . . . . . . . . . . . . . . . . . . . 3
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
device compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
functional block and CPU (DSP core) diagram . . . . . . . . . . . 7
CPU (DSP core) description . . . . . . . . . . . . . . . . . . . . . . . . . . 8
memory map summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
peripheral register descriptions . . . . . . . . . . . . . . . . . . . . . . . 13
EDMA channel synchronization events . . . . . . . . . . . . . . . . 26
interrupt sources and interrupt selector . . . . . . . . . . . . . . . . 28
signal groups description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
device configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
multiplexed pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
debugging considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
terminal functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
documentation support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
clock PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
general-purpose input/output (GPIO) . . . . . . . . . . . . . . . . . . 70
bootmode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
absolute maximum ratings over operating case
temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . 76
recommended operating conditions . . . . . . . . . . . . . . . . 76
electrical characteristics over recommended ranges of
supply voltage and operating case temperature . 77
recommended clock and control signal transition
behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
parameter measurement information . . . . . . . . . . . . . . . 78
input and output clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
asynchronous memory timing . . . . . . . . . . . . . . . . . . . . . 84
programmable synchronous interface timing . . . . . . . . 88
synchronous DRAM timing . . . . . . . . . . . . . . . . . . . . . . . . 93
HOLD/HOLDA timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
BUSREQ timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . 107
host-port interface (HPI) timing . . . . . . . . . . . . . . . . . . . 108
peripheral component interconnect (PCI) timing
[C6415 and C6416 only] . . . . . . . . . . . . . . . . . . . . 113
multichannel buffered serial port (McBSP) timing . . . . 116
UTOPIA slave timing [C6415 and C6416 only] . . . . . . 124
timer timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
general-purpose input/output (GPIO) port timing . . . . 128
JTAG test-port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
power-down mode logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
power-supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
power-supply decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
IEEE 1149.1 JTAG compatibility statement . . . . . . . . . . . . . 74
EMIF device speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
2
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SGUS050A − JANUARY 2004 − REVISED MARCH 2004
REVISION HISTORY
This data sheet revision history highlights the technical changes made to the SMJ320C6414, SMJ320C6415, and
SMJ320C6416 device-specific data sheet.
Scope: Applicable updates to the C64x device family, specifically relating to the C6414, C6415, and C6416
devices, have been incorporated.
PAGE(S)
ADDITIONS/CHANGES/DELETIONS
NO.
All
Original release
3, 81, 82, Removed pin A24, changed Cycle-to-cycle jitter to Period jitter.
83
GAD Ceramic PGA package (bottom view)
GAD CERAMIC 570-PIN GRID ARRAY (PGA) PACKAGE
(BOTTOM VIEW)
AD
AB
AC
AA
Y
V
T
W
U
R
N
P
M
L
K
H
F
J
G
E
C
A
D
B
1
3
5
7
9
11 13 15 17 19 21 23
2
4
6
8
10 12
14 16 18 20 22 24
3
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SGUS050A − JANUARY 2004 − REVISED MARCH 2004
description
The TMS320C64x DSPs (including the SMJ320C6414, SMJ320C6415, and SMJ320C6416 devices) are the
highest-performance fixed-point DSP generation in the TMS320C6000 DSP platform. The TMS320C64x
†
(C64x ) device is based on the second-generation high-performance, advanced VelociTI
very-long-instruction-word (VLIW) architecture (VelociTI.2) developed by Texas Instruments (TI), making
these DSPs an excellent choice for multichannel and multifunctional applications. The C64x is a
code-compatible member of the C6000 DSP platform.
With performance of up to 5760 million instructions per second (MIPS) at a clock rate of 720 MHz, the C64x
devices offer cost-effective solutions to high-performance DSP programming challenges. The C64x DSPs
possess the operational flexibility of high-speed controllers and the numerical capability of array processors.
The C64x DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly
independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs)— with
VelociTI.2 extensions. The VelociTI.2 extensions in the eight functional units include new instructions to
accelerate the performance in key applications and extend the parallelism of the VelociTI architecture. The
C64x can produce four 32-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per
second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. The C64x DSP also has
application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other
C6000 DSP platform devices.
The C6416 device has two high-performance embedded coprocessors [Viterbi Decoder Coprocessor (VCP)
and Turbo Decoder Coprocessor (TCP)] that significantly speed up channel-decoding operations on-chip. The
VCP operating at CPU clock divided-by-4 can decode over 500 7.95-Kbps adaptive multi-rate (AMR) [K = 9,
R = 1/3] voice channels. The VCP supports constraint lengths K = 5, 6, 7, 8, and 9, rates R = 1/2, 1/3, and 1/4,
and flexible polynomials, while generating hard decisions or soft decisions. The TCP operating at CPU clock
divided-by-2 can decode up to thirty-six 384-Kbps or six 2-Mbps turbo encoded channels (assuming 6
iterations). The TCP implements the max*log-map algorithm and is designed to support all polynomials and
rates required by Third-Generation Partnership Projects (3GPP and 3GPP2), with fully programmable frame
length and turbo interleaver. Decoding parameters such as the number of iterations and stopping criteria are
also programmable. Communications between the VCP/TCP and the CPU are carried out through the EDMA
controller.
The C64x uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The
Level 1 program cache (L1P) is a 128K-bit direct mapped cache and the Level 1 data cache (L1D) is a 128K-bit
2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 8M-bit memory space that is
shared between program and data space. L2 memory can be configured as mapped memory or combinations
of cache (up to 256K bytes) and mapped memory. The peripheral set includes three multichannel buffered serial
ports (McBSPs); an 8-bit Universal Test and Operations PHY Interface for Asynchronous Transfer Mode (ATM)
Slave [UTOPIA Slave] port (C6415/C6416 only); three 32-bit general-purpose timers; a user-configurable 16-bit
or 32-bit host-port interface (HPI16/HPI32); a peripheral component interconnect (PCI) [C6415/C6416 only];
a general-purpose input/output port (GPIO) with 16 GPIO pins; and two glueless external memory interfaces
‡
(64-bit EMIFA and 16-bit EMIFB ), both of which are capable of interfacing to synchronous and asynchronous
memories and peripherals.
The C64x has a complete set of development tools which includes: an advanced C compiler with C64x-specific
enhancements, an assembly optimizer to simplify programming and scheduling, and a Windows debugger
interface for visibility into source code execution.
TMS320C6000, C64x, and C6000 are trademarks of Texas Instruments.
Windows is a registered trademark of the Microsoft Corporation.
All trademarks are the property of their respective owners.
†
Throughout the remainder of this document, the SMJ320C6414, SMJ320C6415, and SMJ320C6416 shall be referred to as SMJ320C64x or
C64x where generic, and where specific, their individual full device part numbers will be used or abbreviated as C6414, C6415, or C6416.
These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix “A” in front of a signal name indicates it is an EMIFA signal
whereas a prefix “B” in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of
discussion, the prefix “A” or “B” may be omitted from the signal name.
‡
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SGUS050A − JANUARY 2004 − REVISED MARCH 2004
device characteristics
Table 1 provides an overview of the C6414, C6415, and C6416 DSPs. The table shows significant features of
the C64x devices, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package
type with pin count.
Table 1. Characteristics of the C6414, C6415, and C6416 Processors
HARDWARE FEATURES
C6414, C6415, AND C6416
EMIFA (64-bit bus width)
(default clock source = AECLKIN)
1
EMIFB (16-bit bus width)
(default clock source = BECLKIN)
1
Peripherals
EDMA (64 independent channels)
1
Not all peripherals pins
are available at the same
time. (For more details,
see the Device
HPI (32- or 16-bit user selectable)
1 (HPI16 or HPI32)
1 [C6415/C6416 only]
PCI (32-bit) [DeviceID Register value 0xA106]
McBSPs
Configuration section.)
(default internal clock source = CPU/4 clock
frequency)
3
Peripheral performance is
dependent on chip-level
configuration.
UTOPIA (8-bit mode)
1 [C6415/C6416 only]
32-Bit Timers
(default internal clock source = CPU/8 clock
frequency)
3
General-Purpose Input/Output 0 (GP0)
16
VCP
1 (C6416 only)
1 (C6416 only)
1056K
Decoder Coprocessors
On-Chip Memory
TCP
Size (Bytes)
16K-Byte (16KB) L1 Program (L1P) Cache
16KB L1 Data (L1D) Cache
Organization
1024KB Unified Mapped RAM/Cache (L2)
CPU ID + CPU Rev ID
Device_ID
Control Status Register (CSR.[31:16])
0x0C01
DEVICE_REV[19:16] Silicon Revision
Silicon Revision Identification Register
(DEVICE_REV [19:16])
Address: 0x01B0 0200
1111
0001
0010 or 0000
1.03 or earlier
1.03
1.1
Frequency
Cycle Time
MHz
ns
600
1.67 ns (C6414, C6415, C6416) and
(C6414A, C6415A, C6416A)
[600-MHz CPU, 133-MHz EMIFA]
†
Core (V)
1.4 V
3.3 V
Voltage
I/O (V)
PLL Options
CLKIN frequency multiplier
Bypass (x1), x6, x12
570-Pin PGA (GAD)
0.13 µm
PGA Package
33 x 33 mm
Process Technology
µm
Product Preview (PP)
Advance Information (AI)
Production Data (PD)
Product Status
PD
†
On these C64x devices, the rated EMIF speed affects only the SDRAM interface on EMIFA. For more detailed information, see the EMIF
Device Speed section of this data sheet.
5
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SGUS050A − JANUARY 2004 − REVISED MARCH 2004
device compatibility
The C64x generation of devices has a diverse and powerful set of peripherals. The common peripheral set
and pin-compatibility that the C6414, C6415, and C6416 devices offer lead to easier system designs and faster
time to market. Table 2 identifies the peripherals and coprocessors that are available on the C6414, C6415, and
C6416 devices.
The C6414, C6415, and C6416 devices are pin-for-pin compatible, provided the following conditions are met:
ꢀ
All devices are using the same peripherals.
The C6414 is pin-for-pin compatible with the C6415/C6416 when the PCI and UTOPIA peripherals on the
C6415/C6416 are disabled.
The C6415 is pin-for-pin compatible with the C6416 when they are in the same peripheral selection mode.
[For more information on peripheral selection, see the Device Configurations section of this data sheet.]
ꢀ
The BEA[9:7] pins are properly pulled up/down.
[For more details on the device-specific BEA[9:7] pin configurations, see the Terminal Functions table of
this data sheet.]
†‡
Table 2. Peripherals and Coprocessors Available on the C6414, C6415, and C6416 Devices
PERIPHERALS/COPROCESSORS
EMIFA (64-bit bus width)
C6414
C6415
C6416
√
√
√
√
√
√
√
√
√
√
√
√
√
√
EMIFB (16-bit bus width)
EDMA (64 independent channels)
HPI (32- or 16-bit user selectable)
PCI (32-bit) [Specification v2.2]
√
√
√
√
—
√
√
McBSPs (McBSP0, McBSP1, McBSP2)
UTOPIA (8-bit mode) [Specification v1.0]
Timers (32-bit) [TIMER0, TIMER1, TIMER2]
GPIOs (GP[15:0])
√
—
√
√
√
√
√
VCP/TCP Coprocessors
—
—
†
‡
— denotes peripheral/coprocessor is not available on this device.
Not all peripherals pins are available at the same time. (For more details, see the Device Configuration section.)
For more detailed information on the device compatibility and similarities/differences among the C6414, C6415,
and C6416 devices, see the How To Begin Development Today With the TMS320C6414, TMS320C6415, and
TMS320C6416 DSPs application report (literature number SPRA718).
6
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ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
functional block and CPU (DSP core) diagram
C64x Digital Signal Processor
†
VCP
L1P Cache
Direct-Mapped
16K Bytes Total
†
TCP
64
16
SDRAM
EMIF A
EMIF B
SBSRAM
C64x DSP Core
ZBT SRAM
FIFO
Instruction Fetch
Control
Registers
Timer 2
Timer 1
Timer 0
Instruction Dispatch
Advanced Instruction Packet
SRAM
Control
Logic
ROM/FLASH
I/O Devices
Instruction Decode
Data Path A
Data Path B
Test
A Register File
A31−A16
B Register File
B31−B16
Advanced
In-Circuit
Emulation
McBSP2
A15−A0
B15−B0
.L1 .S1 .M1 .D1
.D2 .M2 .S2 .L2
Interrupt
Control
‡
UTOPIA:
UTOPIA
L2
Enhanced
DMA
Controller
(64-channel)
Up to 400 Mbps
Master ATMC
Memory
1024K
Bytes
or
McBSPs:
‡
McBSP1
McBSP0
Framing Chips:
H.100, MVIP,
SCSA, T1, E1
AC97 Devices,
SPI Devices,
Codecs
L1D Cache
2-Way Set-Associative
16K Bytes Total
GPIO[8:0]
16
32
‡
GPIO[15:9]
‡
HPI
or
Boot Configuration
‡
PCI
Power-Down
Logic
PLL
(x1, x6, x12)
Interrupt
Selector
†
‡
VCP and TCP decoder coprocessors are applicable to the C6416 device only.
For the C6415 and C6416 devices, the UTOPIA peripheral is MUXed with McBSP1, and the PCI peripheral is MUXed with the HPI
peripheral and the GPIO[15:9] port. For more details on the multiplexed pins of these peripherals, see the Device Configurations section
of this data sheet.
7
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ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
CPU (DSP core) description
The CPU fetches VelociTI advanced very-long instruction words (VLIWs) (256 bits wide) to supply up to eight
32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture
features controls by which all eight units do not have to be supplied with instructions if they are not ready to
execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute
packet as the previous instruction, or whether it should be executed in the following clock as a part of the next
execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The
variable-length execute packets are a key memory-saving feature, distinguishing the C64x CPUs from other
VLIW architectures. The C64x VelociTI.2 extensions add enhancements to the TMS320C62x DSP
VelociTI architecture. These enhancements include:
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Register file enhancements
Data path extensions
Quad 8-bit and dual 16-bit extensions with data flow enhancements
Additional functional unit hardware
Increased orthogonality of the instruction set
Additional instructions that reduce code size and increase register flexibility
The CPU features two sets of functional units. Each set contains four units and a register file. One set contains
functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files
each contain 32 32-bit registers for a total of 64 general-purpose registers. In addition to supporting the packed
16-bit and 32-/40-bit fixed-point data types found in the C62x VelociTI VLIW architecture, the C64x register
files also support packed 8-bit data and 64-bit fixed-point data types. The two sets of functional units, along with
two register files, compose sides A and B of the CPU [see the functional block and CPU (DSP core) diagram,
and Figure 1]. The four functional units on each side of the CPU can freely share the 32 registers belonging to
that side. Additionally, each side features a “data cross path”—a single data bus connected to all the registers
on the other side, by which the two sets of functional units can access data from the register files on the opposite
side. The C64x CPU pipelines data-cross-path accesses over multiple clock cycles. This allows the same
register to be used as a data-cross-path operand by multiple functional units in the same execute packet. All
functional units in the C64x CPU can access operands via the data cross path. Register access by functional
units on the same side of the CPU as the register file can service all the units in a single clock cycle. On the C64x
CPU, a delay clock is introduced whenever an instruction attempts to read a register via a data cross path if that
register was updated in the previous clock cycle.
In addition to the C62x DSP fixed-point instructions, the C64x DSP includes a comprehensive collection of
quad 8-bit and dual 16-bit instruction set extensions. These VelociTI.2 extensions allow the C64x CPU to
operate directly on packed data to streamline data flow and increase instruction set efficiency.
Another key feature of the C64x CPU is the load/store architecture, where all instructions operate on registers
(as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data
transfers between the register files and the memory. The data address driven by the .D units allows data
addresses generated from one register file to be used to load or store data to or from the other register file. The
C64x .D units can load and store bytes (8 bits), half-words (16 bits), and words (32 bits) with a single instruction.
And with the new data path extensions, the C64x .D unit can load and store doublewords (64 bits) with a single
instruction. Furthermore, the non-aligned load and store instructions allow the .D units to access words and
doublewords on any byte boundary. The C64x CPU supports a variety of indirect addressing modes using either
linear- or circular-addressing with 5- or 15-bit offsets. All instructions are conditional, and most can access any
one of the 64 registers. Some registers, however, are singled out to support specific addressing modes or to
hold the condition for conditional instructions (if the condition is not automatically “true”).
TMS320C62x is a trademark of Texas Instruments.
8
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ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
CPU (DSP core) description (continued)
The two .M functional units perform all multiplication operations. Each of the C64x .M units can perform two
16 × 16-bit multiplies or four 8 × 8-bit multiplies per clock cycle. The .M unit can also perform 16 × 32-bit multiply
operations, dual 16 × 16-bit multiplies with add/subtract operations, and quad 8 × 8-bit multiplies with add
operations. In addition to standard multiplies, the C64x .M units include bit-count, rotate, Galois field multiplies,
and bidirectional variable shift hardware.
The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results
available every clock cycle. The arithmetic and logical functions on the C64x CPU include single 32-bit, dual
16-bit, and quad 8-bit operations.
The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory.
The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least
significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous
execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain,
effectively placing the instructions that follow it in the next execute packet. A C64x DSP device enhancement
now allows execute packets to cross fetch-packet boundaries. In the TMS320C62x/TMS320C67x DSP
devices, if an execute packet crosses the fetch-packet boundary (256 bits wide), the assembler places it in the
next fetch packet, while the remainder of the current fetch packet is padded with NOP instructions. In the C64x
DSP device, the execute boundary restrictions have been removed, thereby, eliminating all of the NOPs added
to pad the fetch packet, and thus, decreasing the overall code size. The number of execute packets within a
fetch packet can vary from one to eight. Execute packets are dispatched to their respective functional units at
the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from
the current fetch packet have been dispatched. After decoding, the instructions simultaneously drive all active
functional units for a maximum execution rate of eight instructions every clock cycle. While most results are
stored in 32-bit registers, they can be subsequently moved to memory as bytes, half-words, words, or
doublewords. All load and store instructions are byte-, half-word-, word-, or doubleword-addressable.
For more details on the C64x CPU functional units enhancements, see the following documents:
The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189)
TMS320C64x Technical Overview (literature number SPRU395)
How To Begin Development Today With the TMS320C6414, TMS320C6415, and TMS320C6416 DSPs
application report (literature number SPRA718)
TMS320C67x is a trademark of Texas Instruments.
9
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ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
CPU (DSP core) description (continued)
src1
.L1
src2
dst
8
long dst
long src
8
32 MSBs
32 LSBs
ST1b (Store Data)
ST1a (Store Data)
8
long src
long dst
dst
8
Register
File A
src1
(A0−A31)
.S1
Data Path A
src2
See Note A
See Note A
long dst
dst
src1
.M1
src2
32 MSBs
32 LSBs
LD1b (Load Data)
LD1a (Load Data)
dst
DA1 (Address)
src1
.D1
.D2
src2
2X
1X
src2
src1
dst
DA2 (Address)
32 LSBs
32 MSBs
LD2a (Load Data)
LD2b (Load Data)
src2
src1
dst
.M2
See Note A
See Note A
long dst
Register
File B
src2
Data Path B
.S2
(B0− B31)
src1
dst
8
long dst
long src
8
32 MSBs
32 LSBs
ST2a (Store Data)
ST2b (Store Data)
8
long src
long dst
dst
8
src2
.L2
src1
Control Register
File
NOTE A: For the .M functional units, the long dst is 32 MSBs and the dst is 32 LSBs.
Figure 1. SMJ320C64x CPU (DSP Core) Data Paths
10
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ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
memory map summary
Table 3 shows the memory map address ranges of the SMJ320C64x device. Internal memory is always located
at address 0 and can be used as both program and data memory. The external memory address ranges in the
C64x device begin at the hex address locations 0x6000 0000 for EMIFB and 0x8000 0000 for EMIFA.
11
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ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
memory map summary (continued)
Table 3. SMJ320C64x Memory Map Summary
MEMORY BLOCK DESCRIPTION
BLOCK SIZE (BYTES)
1M
HEX ADDRESS RANGE
Internal RAM (L2)
0000 0000 – 000F FFFF
0010 0000 – 017F FFFF
0180 0000 – 0183 FFFF
0184 0000 – 0187 FFFF
0188 0000 – 018B FFFF
018C 0000 – 018F FFFF
0190 0000 – 0193 FFFF
0194 0000 – 0197 FFFF
0198 0000 – 019B FFFF
019C 0000 – 019F FFFF
01A0 0000 – 01A3 FFFF
01A4 0000 – 01A7 FFFF
01A8 0000 – 01AB FFFF
01AC 0000 – 01AF FFFF
01B0 0000 – 01B3 FFFF
01B4 0000 – 01B7 FFFF
01B8 0000 – 01BB FFFF
01BC 0000 – 01BF FFFF
01C0 0000 – 01C3 FFFF
01C4 0000 – 01FF FFFF
0200 0000 – 0200 0033
0200 0034 – 2FFF FFFF
3000 0000 – 33FF FFFF
3400 0000 – 37FF FFFF
3800 0000 – 3BFF FFFF
3C00 0000 – 3FFF FFFF
4000 0000 – 4FFF FFFF
5000 0000 – 5FFF FFFF
6000 0000 – 63FF FFFF
6400 0000 – 67FF FFFF
6800 0000 – 6BFF FFFF
6C00 0000 – 6FFF FFFF
7000 0000 – 7FFF FFFF
8000 0000 – 8FFF FFFF
9000 0000 – 9FFF FFFF
A000 0000 – AFFF FFFF
B000 0000 – BFFF FFFF
C000 0000 – FFFF FFFF
Reserved
23M
External Memory Interface A (EMIFA) Registers
L2 Registers
256K
256K
256K
256K
256K
256K
256K
256K
256K
256K
256K
256K
256K
256K
256K
256K
256K
4M – 256K
52
HPI Registers
McBSP 0 Registers
McBSP 1 Registers
Timer 0 Registers
Timer 1 Registers
Interrupt Selector Registers
EDMA RAM and EDMA Registers
McBSP 2 Registers
EMIFB Registers
Timer 2 Registers
GPIO Registers
†
UTOPIA Registers (C6415 and C6416 only)
‡
TCP/VCP Registers (C6416 only)
Reserved
†
PCI Registers (C6415 and C6416 only)
Reserved
QDMA Registers
Reserved
736M – 52
64M
McBSP 0 Data
McBSP 1 Data
64M
McBSP 2 Data
64M
†
UTOPIA Queues (C6415 and C6416 only)
64M
Reserved
256M
256M
64M
‡
TCP/VCP (C6416 only)
EMIFB CE0
EMIFB CE1
EMIFB CE2
EMIFB CE3
Reserved
64M
64M
64M
256M
256M
256M
256M
256M
1G
EMIFA CE0
EMIFA CE1
EMIFA CE2
EMIFA CE3
Reserved
†
‡
For the C6414 device, these memory address locations are reserved. The C6414 device does not support the UTOPIA and PCI peripherals.
Only the C6416 device supports the VCP/TCP Coprocessors. For the C6414 and C6415 devices, these memory address locations are reserved.
12
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ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
peripheral register descriptions
Table 4 through Table 23 identify the peripheral registers for the C6414, C6415, and C6416 devices by their
register names, acronyms, and hex address or hex address range. For more detailed information on the register
contents, bit names and their descriptions, see the specific peripheral reference guide listed in the
TMS320C6000 DSP Peripherals Overview Reference Guide (literature number SPRU190).
Table 4. EMIFA Registers
HEX ADDRESS RANGE
0180 0000
ACRONYM
GBLCTL
CECTL1
CECTL0
−
REGISTER NAME
EMIFA global control
EMIFA CE1 space control
EMIFA CE0 space control
Reserved
0180 0004
0180 0008
0180 000C
0180 0010
CECTL2
CECTL3
SDCTL
SDTIM
SDEXT
−
EMIFA CE2 space control
EMIFA CE3 space control
EMIFA SDRAM control
EMIFA SDRAM refresh control
EMIFA SDRAM extension
Reserved
0180 0014
0180 0018
0180 001C
0180 0020
0180 0024 − 0180 003C
0180 0040
PDTCTL
CESEC1
CESEC0
−
Peripheral device transfer (PDT) control
EMIFA CE1 space secondary control
EMIFA CE0 space secondary control
Reserved
0180 0044
0180 0048
0180 004C
0180 0050
CESEC2
CESEC3
–
EMIFA CE2 space secondary control
EMIFA CE3 space secondary control
Reserved
0180 0054
0180 0058 − 0183 FFFF
Table 5. EMIFB Registers
HEX ADDRESS RANGE
01A8 0000
ACRONYM
GBLCTL
CECTL1
CECTL0
−
REGISTER NAME
EMIFB global control
01A8 0004
EMIFB CE1 space control
EMIFB CE0 space control
Reserved
01A8 0008
01A8 000C
01A8 0010
CECTL2
CECTL3
SDCTL
SDTIM
SDEXT
−
EMIFB CE2 space control
EMIFB CE3 space control
EMIFB SDRAM control
EMIFB SDRAM refresh control
EMIFB SDRAM extension
Reserved
01A8 0014
01A8 0018
01A8 001C
01A8 0020
01A8 0024 − 01A8 003C
01A8 0040
PDTCTL
CESEC1
CESEC0
−
Peripheral device transfer (PDT) control
EMIFB CE1 space secondary control
EMIFB CE0 space secondary control
Reserved
01A8 0044
01A8 0048
01A8 004C
01A8 0050
CESEC2
CESEC3
–
EMIFB CE2 space secondary control
EMIFB CE3 space secondary control
Reserved
01A8 0054
01A8 0058 − 01AB FFFF
13
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ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
peripheral register descriptions (continued)
Table 6. L2 Cache Registers
HEX ADDRESS RANGE
0184 0000
ACRONYM
CCFG
REGISTER NAME
Cache configuration register
Reserved
COMMENTS
0184 0004 − 0184 0FFC
0184 1000
−
EDMAWEIGHT
−
L2 EDMA access control register
Reserved
0184 1004 − 0184 1FFC
0184 2000
L2ALLOC0
L2ALLOC1
L2ALLOC2
L2ALLOC3
−
L2 allocation register 0
L2 allocation register 1
L2 allocation register 2
L2 allocation register 3
Reserved
0184 2004
0184 2008
0184 200C
0184 2010 − 0184 3FFC
0184 4000
L2FBAR
L2FWC
L2CBAR
L2CWC
L1PFBAR
L1PFWC
L1DFBAR
L1DFWC
−
L2 flush base address register
L2 flush word count register
L2 clean base address register
L2 clean word count register
L1P flush base address register
L1P flush word count register
L1D flush base address register
L1D flush word count register
Reserved
0184 4004
0184 4010
0184 4014
0184 4020
0184 4024
0184 4030
0184 4034
0184 4038 − 0184 4FFC
0184 5000
L2FLUSH
L2CLEAN
−
L2 flush register
0184 5004
L2 clean register
0184 5008 − 0184 7FFC
Reserved
MAR0 to
MAR95
0184 8000 − 0184 817C
Reserved
0184 8180
0184 8184
0184 8188
0184 818C
0184 8190
0184 8194
0184 8198
0184 819C
0184 81A0
0184 81A4
0184 81A8
0184 81AC
0184 81B0
0184 81B4
0184 81B8
0184 81BC
MAR96
MAR97
Controls EMIFB CE0 range 6000 0000 − 60FF FFFF
Controls EMIFB CE0 range 6100 0000 − 61FF FFFF
Controls EMIFB CE0 range 6200 0000 − 62FF FFFF
Controls EMIFB CE0 range 6300 0000 − 63FF FFFF
Controls EMIFB CE1 range 6400 0000 − 64FF FFFF
Controls EMIFB CE1 range 6500 0000 − 65FF FFFF
Controls EMIFB CE1 range 6600 0000 − 66FF FFFF
Controls EMIFB CE1 range 6700 0000 − 67FF FFFF
Controls EMIFB CE2 range 6800 0000 − 68FF FFFF
Controls EMIFB CE2 range 6900 0000 − 69FF FFFF
Controls EMIFB CE2 range 6A00 0000 − 6AFF FFFF
Controls EMIFB CE2 range 6B00 0000 − 6BFF FFFF
Controls EMIFB CE3 range 6C00 0000 − 6CFF FFFF
Controls EMIFB CE3 range 6D00 0000 − 6DFF FFFF
Controls EMIFB CE3 range 6E00 0000 − 6EFF FFFF
Controls EMIFB CE3 range 6F00 0000 − 6FFF FFFF
MAR98
MAR99
MAR100
MAR101
MAR102
MAR103
MAR104
MAR105
MAR106
MAR107
MAR108
MAR109
MAR110
MAR111
MAR112 to
MAR127
0184 81C0 − 0184 81FC
Reserved
0184 8200
0184 8204
MAR128
MAR129
Controls EMIFA CE0 range 8000 0000 − 80FF FFFF
Controls EMIFA CE0 range 8100 0000 − 81FF FFFF
14
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ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢊ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢊ ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
Table 6. L2 Cache Registers (Continued)
HEX ADDRESS RANGE
0184 8208
0184 820C
0184 8210
0184 8214
0184 8218
0184 821C
0184 8220
0184 8224
0184 8228
0184 822C
0184 8230
0184 8234
0184 8238
0184 823C
0184 8240
0184 8244
0184 8248
0184 824C
0184 8250
0184 8254
0184 8258
0184 825C
0184 8260
0184 8264
0184 8268
0184 826C
0184 8270
0184 8274
0184 8278
0184 827C
0184 8280
0184 8284
0184 8288
0184 828C
0184 8290
0184 8294
0184 8298
0184 829C
0184 82A0
0184 82A4
0184 82A8
0184 82AC
0184 82B0
0184 82B4
ACRONYM
REGISTER NAME
COMMENTS
MAR130
MAR131
MAR132
MAR133
MAR134
MAR135
MAR136
MAR137
MAR138
MAR139
MAR140
MAR141
MAR142
MAR143
MAR144
MAR145
MAR146
MAR147
MAR148
MAR149
MAR150
MAR151
MAR152
MAR153
MAR154
MAR155
MAR156
MAR157
MAR158
MAR159
MAR160
MAR161
MAR162
MAR163
MAR164
MAR165
MAR166
MAR167
MAR168
MAR169
MAR170
MAR171
MAR172
MAR173
Controls EMIFA CE0 range 8200 0000 − 82FF FFFF
Controls EMIFA CE0 range 8300 0000 − 83FF FFFF
Controls EMIFA CE0 range 8400 0000 − 84FF FFFF
Controls EMIFA CE0 range 8500 0000 − 85FF FFFF
Controls EMIFA CE0 range 8600 0000 − 86FF FFFF
Controls EMIFA CE0 range 8700 0000 − 87FF FFFF
Controls EMIFA CE0 range 8800 0000 − 88FF FFFF
Controls EMIFA CE0 range 8900 0000 − 89FF FFFF
Controls EMIFA CE0 range 8A00 0000 − 8AFF FFFF
Controls EMIFA CE0 range 8B00 0000 − 8BFF FFFF
Controls EMIFA CE0 range 8C00 0000 − 8CFF FFFF
Controls EMIFA CE0 range 8D00 0000 − 8DFF FFFF
Controls EMIFA CE0 range 8E00 0000 − 8EFF FFFF
Controls EMIFA CE0 range 8F00 0000 − 8FFF FFFF
Controls EMIFA CE1 range 9000 0000 − 90FF FFFF
Controls EMIFA CE1 range 9100 0000 − 91FF FFFF
Controls EMIFA CE1 range 9200 0000 − 92FF FFFF
Controls EMIFA CE1 range 9300 0000 − 93FF FFFF
Controls EMIFA CE1 range 9400 0000 − 94FF FFFF
Controls EMIFA CE1 range 9500 0000 − 95FF FFFF
Controls EMIFA CE1 range 9600 0000 − 96FF FFFF
Controls EMIFA CE1 range 9700 0000 − 97FF FFFF
Controls EMIFA CE1 range 9800 0000 − 98FF FFFF
Controls EMIFA CE1 range 9900 0000 − 99FF FFFF
Controls EMIFA CE1 range 9A00 0000 − 9AFF FFFF
Controls EMIFA CE1 range 9B00 0000 − 9BFF FFFF
Controls EMIFA CE1 range 9C00 0000 − 9CFF FFFF
Controls EMIFA CE1 range 9D00 0000 − 9DFF FFFF
Controls EMIFA CE1 range 9E00 0000 − 9EFF FFFF
Controls EMIFA CE1 range 9F00 0000 − 9FFF FFFF
Controls EMIFA CE2 range A000 0000 − A0FF FFFF
Controls EMIFA CE2 range A100 0000 − A1FF FFFF
Controls EMIFA CE2 range A200 0000 − A2FF FFFF
Controls EMIFA CE2 range A300 0000 − A3FF FFFF
Controls EMIFA CE2 range A400 0000 − A4FF FFFF
Controls EMIFA CE2 range A500 0000 − A5FF FFFF
Controls EMIFA CE2 range A600 0000 − A6FF FFFF
Controls EMIFA CE2 range A700 0000 − A7FF FFFF
Controls EMIFA CE2 range A800 0000 − A8FF FFFF
Controls EMIFA CE2 range A900 0000 − A9FF FFFF
Controls EMIFA CE2 range AA00 0000 − AAFF FFFF
Controls EMIFA CE2 range AB00 0000 − ABFF FFFF
Controls EMIFA CE2 range AC00 0000 − ACFF FFFF
Controls EMIFA CE2 range AD00 0000 − ADFF FFFF
15
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ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢋ ꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢇ
ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
Table 6. L2 Cache Registers (Continued)
HEX ADDRESS RANGE
0184 82B8
0184 82BC
0184 82C0
0184 82C4
0184 82C8
0184 82CC
0184 82D0
0184 82D4
0184 82D8
0184 82DC
0184 82E0
0184 82E4
0184 82E8
0184 82EC
0184 82F0
0184 82F4
0184 82F8
0184 82FC
ACRONYM
REGISTER NAME
COMMENTS
MAR174
MAR175
MAR176
MAR177
MAR178
MAR179
MAR180
MAR181
MAR182
MAR183
MAR184
MAR185
MAR186
MAR187
MAR188
MAR189
MAR190
MAR191
Controls EMIFA CE2 range AE00 0000 − AEFF FFFF
Controls EMIFA CE2 range AF00 0000 − AFFF FFFF
Controls EMIFA CE3 range B000 0000 − B0FF FFFF
Controls EMIFA CE3 range B100 0000 − B1FF FFFF
Controls EMIFA CE3 range B200 0000 − B2FF FFFF
Controls EMIFA CE3 range B300 0000 − B3FF FFFF
Controls EMIFA CE3 range B400 0000 − B4FF FFFF
Controls EMIFA CE3 range B500 0000 − B5FF FFFF
Controls EMIFA CE3 range B600 0000 − B6FF FFFF
Controls EMIFA CE3 range B700 0000 − B7FF FFFF
Controls EMIFA CE3 range B800 0000 − B8FF FFFF
Controls EMIFA CE3 range B900 0000 − B9FF FFFF
Controls EMIFA CE3 range BA00 0000 − BAFF FFFF
Controls EMIFA CE3 range BB00 0000 − BBFF FFFF
Controls EMIFA CE3 range BC00 0000 − BCFF FFFF
Controls EMIFA CE3 range BD00 0000 − BDFF FFFF
Controls EMIFA CE3 range BE00 0000 − BEFF FFFF
Controls EMIFA CE3 range BF00 0000 − BFFF FFFF
MAR192 to
MAR255
0184 8300 − 0184 83FC
0184 8400 − 0187 FFFF
Reserved
Reserved
−
16
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ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢊ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢊ ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
peripheral register descriptions (continued)
Table 7. EDMA Registers
HEX ADDRESS RANGE
01A0 FF9C
01A0 FFA4
ACRONYM
EPRH
CIPRH
CIERH
CCERH
ERH
REGISTER NAME
Event polarity high register
Channel interrupt pending high register
Channel interrupt enable high register
Channel chain enable high register
Event high register
01A0 FFA8
01A0 FFAC
01A0 FFB0
01A0 FFB4
EERH
ECRH
ESRH
PQAR0
PQAR1
PQAR2
PQAR3
EPRL
Event enable high register
Event clear high register
01A0 FFB8
01A0 FFBC
01A0 FFC0
01A0 FFC4
01A0 FFC8
01A0 FFCC
01A0 FFDC
01A0 FFE0
Event set high register
Priority queue allocation register 0
Priority queue allocation register 1
Priority queue allocation register 2
Priority queue allocation register 3
Event polarity low register
PQSR
CIPRL
CIERL
CCERL
ERL
Priority queue status register
Channel interrupt pending low register
Channel interrupt enable low register
Channel chain enable low register
Event low register
01A0 FFE4
01A0 FFE8
01A0 FFEC
01A0 FFF0
01A0 FFF4
EERL
Event enable low register
01A0 FFF8
ECRL
ESRL
Event clear low register
01A0 FFFC
01A1 0000 − 01A3 FFFF
Event set low register
–
Reserved
17
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ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢋ ꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢇ
ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
peripheral register descriptions (continued)
†
Table 8. EDMA Parameter RAM
HEX ADDRESS RANGE
01A0 0000 − 01A0 0017
01A0 0018 − 01A0 002F
01A0 0030 − 01A0 0047
01A0 0048 − 01A0 005F
01A0 0060 − 01A0 0077
01A0 0078 − 01A0 008F
01A0 0090 − 01A0 00A7
01A0 00A8 − 01A0 00BF
01A0 00C0 − 01A0 00D7
01A0 00D8 − 01A0 00EF
01A0 00F0 − 01A0 00107
01A0 0108 − 01A0 011F
01A0 0120 − 01A0 0137
01A0 0138 − 01A0 014F
01A0 0150 − 01A0 0167
01A0 0168 − 01A0 017F
01A0 0150 − 01A0 0167
01A0 0168 − 01A0 017F
...
ACRONYM
REGISTER NAME
Parameters for Event 0 (6 words)
Parameters for Event 1 (6 words)
Parameters for Event 2 (6 words)
Parameters for Event 3 (6 words)
Parameters for Event 4 (6 words)
Parameters for Event 5 (6 words)
Parameters for Event 6 (6 words)
Parameters for Event 7 (6 words)
Parameters for Event 8 (6 words)
Parameters for Event 9 (6 words)
Parameters for Event 10 (6 words)
Parameters for Event 11 (6 words)
Parameters for Event 12 (6 words)
Parameters for Event 13 (6 words)
Parameters for Event 14 (6 words)
Parameters for Event 15 (6 words)
Parameters for Event 16 (6 words)
Parameters for Event 17 (6 words)
...
COMMENTS
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
...
...
01A0 05D0 − 01A0 05E7
01A0 05E8 − 01A0 05FF
01A0 0600 − 01A0 0617
01A0 0618 − 01A0 062F
...
−
−
−
−
Parameters for Event 62 (6 words)
Parameters for Event 63 (6 words)
Reload/link parameters for Event M (6 words)
Reload/link parameters for Event N (6 words)
...
01A0 07E0 − 01A0 07F7
01A0 07F8 − 01A0 07FF
−
−
Reload/link parameters for Event Z (6 words)
Scratch pad area (2 words)
†
The C64x device has twenty-one parameter sets [six (6) words each] that can be used to reload/link EDMA transfers.
Table 9. Quick DMA (QDMA) and Pseudo Registers
HEX ADDRESS RANGE
0200 0000
ACRONYM
QOPT
REGISTER NAME
QDMA options parameter register
0200 0004
QSRC
QCNT
QDMA source address register
QDMA frame count register
QDMA destination address register
QDMA index register
0200 0008
0200 000C
QDST
0200 0010
QIDX
0200 0014 − 0200 001C
0200 0020
Reserved
QSOPT
QSSRC
QSCNT
QSDST
QSIDX
QDMA pseudo options register
QDMA pseudo source address register
QDMA pseudo frame count register
QDMA pseudo destination address register
QDMA pseudo index register
0200 0024
0200 0028
0200 002C
0200 0030
18
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢊ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢊ ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
peripheral register descriptions (continued)
Table 10. Interrupt Selector Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
Selects which interrupts drive CPU
interrupts 10−15 (INT10−INT15)
019C 0000
MUXH
Interrupt multiplexer high
Selects which interrupts drive CPU
interrupts 4−9 (INT04−INT09)
019C 0004
MUXL
Interrupt multiplexer low
Sets the polarity of the external
interrupts (EXT_INT4−EXT_INT7)
019C 0008
EXTPOL
−
External interrupt polarity
Reserved
019C 000C − 019C 01FF
Table 11. McBSP 0 Registers
REGISTER NAME
HEX ADDRESS RANGE
ACRONYM
COMMENTS
The CPU and EDMA controller
can only read this register;
they cannot write to it.
018C 0000
DRR0
McBSP0 data receive register via Configuration Bus
0x3000 0000 − 0x33FF FFFF
018C 0004
DRR0
DXR0
McBSP0 data receive register via Peripheral Bus
McBSP0 data transmit register via Configuration Bus
McBSP0 data transmit register via Peripheral Bus
McBSP0 serial port control register
0x3000 0000 − 0x33FF FFFF
018C 0008
DXR0
SPCR0
RCR0
018C 000C
McBSP0 receive control register
018C 0010
XCR0
McBSP0 transmit control register
018C 0014
SRGR0
MCR0
McBSP0 sample rate generator register
018C 0018
McBSP0 multichannel control register
018C 001C
RCERE00
XCERE00
PCR0
McBSP0 enhanced receive channel enable register 0
McBSP0 enhanced transmit channel enable register 0
McBSP0 pin control register
018C 0020
018C 0024
018C 0028
RCERE10
XCERE10
RCERE20
XCERE20
RCERE30
XCERE30
–
McBSP0 enhanced receive channel enable register 1
McBSP0 enhanced transmit channel enable register 1
McBSP0 enhanced receive channel enable register 2
McBSP0 enhanced transmit channel enable register 2
McBSP0 enhanced receive channel enable register 3
McBSP0 enhanced transmit channel enable register 3
Reserved
018C 002C
018C 0030
018C 0034
018C 0038
018C 003C
018C 0040 − 018F FFFF
19
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢋ ꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢇ
ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
peripheral register descriptions (continued)
Table 12. McBSP 1 Registers
REGISTER NAME
HEX ADDRESS RANGE
ACRONYM
COMMENTS
The CPU and EDMA controller
can only read this register;
they cannot write to it.
0190 0000
DRR1
McBSP1 data receive register via Configuration Bus
0x3400 0000 − 0x37FF FFFF
0190 0004
DRR1
DXR1
McBSP1 data receive register via Peripheral Bus
McBSP1 data transmit register via Configuration Bus
McBSP1 data transmit register via Peripheral Bus
McBSP1 serial port control register
0x3400 0000 − 0x37FF FFFF
0190 0008
DXR1
SPCR1
RCR1
0190 000C
McBSP1 receive control register
0190 0010
XCR1
McBSP1 transmit control register
0190 0014
SRGR1
MCR1
McBSP1 sample rate generator register
0190 0018
McBSP1 multichannel control register
0190 001C
RCERE01
XCERE01
PCR1
McBSP1 enhanced receive channel enable register 0
McBSP1 enhanced transmit channel enable register 0
McBSP1 pin control register
0190 0020
0190 0024
0190 0028
RCERE11
XCERE11
RCERE21
XCERE21
RCERE31
XCERE31
–
McBSP1 enhanced receive channel enable register 1
McBSP1 enhanced transmit channel enable register 1
McBSP1 enhanced receive channel enable register 2
McBSP1 enhanced transmit channel enable register 2
McBSP1 enhanced receive channel enable register 3
McBSP1 enhanced transmit channel enable register 3
Reserved
0190 002C
0190 0030
0190 0034
0190 0038
0190 003C
0190 0040 − 0193 FFFF
Table 13. McBSP 2 Registers
REGISTER NAME
HEX ADDRESS RANGE
ACRONYM
COMMENTS
The CPU and EDMA controller
can only read this register;
they cannot write to it.
01A4 0000
DRR2
McBSP2 data receive register via Configuration Bus
0x3800 0000 − 0x3BFF FFFF
01A4 0004
DRR2
DXR2
McBSP2 data receive register via Peripheral Bus
McBSP2 data transmit register via Configuration Bus
McBSP2 data transmit register via Peripheral Bus
McBSP2 serial port control register
0x3800 0000 − 0x3BFF FFFF
01A4 0008
DXR2
SPCR2
RCR2
01A4 000C
McBSP2 receive control register
01A4 0010
XCR2
McBSP2 transmit control register
01A4 0014
SRGR2
MCR2
McBSP2 sample rate generator register
01A4 0018
McBSP2 multichannel control register
01A4 001C
RCERE02
XCERE02
PCR2
McBSP2 enhanced receive channel enable register 0
McBSP2 enhanced transmit channel enable register 0
McBSP2 pin control register
01A4 0020
01A4 0024
01A4 0028
RCERE12
XCERE12
RCERE22
XCERE22
RCERE32
XCERE32
–
McBSP2 enhanced receive channel enable register 1
McBSP2 enhanced transmit channel enable register 1
McBSP2 enhanced receive channel enable register 2
McBSP2 enhanced transmit channel enable register 2
McBSP2 enhanced receive channel enable register 3
McBSP2 enhanced transmit channel enable register 3
Reserved
01A4 002C
01A4 0030
01A4 0034
01A4 0038
01A4 003C
01A4 0040 − 01A7 FFFF
20
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢊ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢊ ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
peripheral register descriptions (continued)
Table 14. Timer 0 Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
Determines the operating
mode of the timer, monitors the
timer status, and controls the
function of the TOUT pin.
0194 0000
CTL0
Timer 0 control register
Timer 0 period register
Contains the number of timer
input clock cycles to count.
This number controls the
TSTAT signal frequency.
0194 0004
PRD0
Contains the current value of
the incrementing counter.
0194 0008
CNT0
−
Timer 0 counter register
Reserved
0194 000C − 0197 FFFF
Table 15. Timer 1 Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
Determines the operating
mode of the timer, monitors the
timer status, and controls the
function of the TOUT pin.
0198 0000
CTL1
Timer 1 control register
Timer 1 period register
Contains the number of timer
input clock cycles to count.
This number controls the
TSTAT signal frequency.
0198 0004
PRD1
Contains the current value of
the incrementing counter.
0198 0008
CNT1
−
Timer 1 counter register
Reserved
0198 000C − 019B FFFF
Table 16. Timer 2 Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
Determines the operating
mode of the timer, monitors the
timer status, and controls the
function of the TOUT pin.
01AC 0000
CTL2
Timer 2 control register
Timer 2 period register
Contains the number of timer
input clock cycles to count.
This number controls the
TSTAT signal frequency.
01AC 0004
PRD2
Contains the current value of
the incrementing counter.
01AC 0008
CNT2
−
Timer 2 counter register
Reserved
01AC 000C − 01AF FFFF
21
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢋ ꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢇ
ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
peripheral register descriptions (continued)
Table 17. HPI Registers
HEX ADDRESS RANGE
−
ACRONYM
REGISTER NAME
COMMENTS
HPID
HPI data register
Host read/write access only
HPIC has both Host/CPU
read/write access
0188 0000
0188 0004
0188 0008
HPIC
HPIA
HPI control register
HPI address register (Write)
HPI address register (Read)
†
(HPIAW)
HPIA has both Host/CPU
read/write access
HPIA
(HPIAR)
†
0188 000C − 0189 FFFF
018A 0000
−
TRCTL
−
Reserved
HPI transfer request control register
Reserved
018A 0004 − 018B FFFF
†
Host access to the HPIA register updates both the HPIAW and HPIAR registers. The CPU can access HPIAW and HPIAR independently.
Table 18. GPIO Registers
HEX ADDRESS RANGE
01B0 0000
ACRONYM
GPEN
GPDIR
GPVAL
−
REGISTER NAME
GPIO enable register
01B0 0004
GPIO direction register
GPIO value register
Reserved
01B0 0008
01B0 000C
01B0 0010
GPDH
GPHM
GPDL
GPLM
GPGC
GPPOL
−
GPIO delta high register
GPIO high mask register
GPIO delta low register
GPIO low mask register
GPIO global control register
GPIO interrupt polarity register
Reserved
01B0 0014
01B0 0018
01B0 001C
01B0 0020
01B0 0024
01B0 0028 − 01B0 01FF
Silicon Revision Identification Register
(For more details, see the device characteristics listed in Table 1.)
01B0 0200
DEVICE_REV
−
01B0 0204 − 01B3 FFFF
Reserved
22
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ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
peripheral register descriptions (continued)
†
Table 19. PCI Peripheral Registers (C6415 and C6416 Only)
HEX ADDRESS RANGE
01C0 0000
ACRONYM
RSTSRC
−
REGISTER NAME
DSP Reset source/status register
01C0 0004
Reserved
01C0 0008
PCIIS
PCIIEN
DSPMA
PCIMA
PCIMC
CDSPA
CPCIA
CCNT
−
PCI interrupt source register
PCI interrupt enable register
DSP master address register
PCI master address register
PCI master control register
Current DSP address register
Current PCI address register
Current byte count register
Reserved
01C0 000C
01C0 0010
01C0 0014
01C0 0018
01C0 001C
01C0 0020
01C0 0024
01C0 0028
01C0 002C − 01C1 FFEF
0x01C1 FFF0
0x01C1 FFF4
0x01C1 FFF8
0x01C1 FFFC
01C2 0000
–
Reserved
HSR
Host status register
HDCR
DSPP
−
Host-to-DSP control register
DSP page register
Reserved
EEADD
EEDAT
EECTL
–
EEPROM address register
EEPROM data register
EEPROM control register
Reserved
01C2 0004
01C2 0008
01C2 000C − 01C2 FFFF
01C3 0000
TRCTL
PCI transfer request control register
01C3 0004 − 01C3 FFFF
–
Reserved
†
These PCI registers are not supported on the C6414 device.
23
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ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
peripheral register descriptions (continued)
†
Table 20. UTOPIA (C6415 and C6416 Only)
HEX ADDRESS RANGE
01B4 0000
ACRONYM
REGISTER NAME
UTOPIA control register
UCR
−
01B4 0004
Reserved
01B4 0008
−
Reserved
01B4 000C
UIER
UIPR
CDR
EIER
EIPR
−
UTOPIA interrupt enable register
UTOPIA interrupt pending register
Clock detect register
Error interrupt enable register
Error interrupt pending register
Reserved
01B4 0010
01B4 0014
01B4 0018
01B4 001C
01B4 0020 − 01B7 FFFF
†
These UTOPIA registers are not supported on the C6414 device.
†
Table 21. UTOPIA QUEUES (C6415 and C6416 Only)
HEX ADDRESS RANGE
3C00 0000
ACRONYM
REGISTER NAME
UTOPIA receive queue
URQ
UXQ
−
3D00 0000
UTOPIA transmit queue
Reserved
3D00 0004 − 3FFF FFFF
†
These UTOPIA registers are not supported on the C6414 device.
24
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢊ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢊ ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
peripheral register descriptions (continued)
†
Table 22. VCP Registers (C6416 Only)
EDMA BUS
HEX ADDRESS RANGE
PERIPHERAL BUS
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
VCP input configuration register 0
5000 0000
5000 0004
5000 0008
5000 000C
5000 0010
5000 0014
01B8 0000
VCPIC0
VCPIC1
VCPIC2
VCPIC3
VCPIC4
VCPIC5
01B8 0004
VCP input configuration register 1
VCP input configuration register 2
VCP input configuration register 3
VCP input configuration register 4
VCP input configuration register 5
01B8 0008
01B8 000C
01B8 0010
01B8 0014
5000 0040
5000 0044
01B8 0024
01B8 0028
VCPOUT0
VCPOUT1
VCP output register 0
VCP output register 1
5000 0080
−
VCPWBM
VCP branch metrics write register
5000 0088
−
VCPRDECS VCP decisions read register
−
−
−
−
−
01B8 0018
01B8 0020
01B8 0040
01B8 0044
01B8 0050
VCPEXE
VCPEND
VCP execution register
VCP endian register
VCP status register 0
VCP status register 1
VCP error register
VCPSTAT0
VCPSTAT1
VCPERR
†
These VCP registers are supported on the C6416 device only.
‡
Table 23. TCP Registers (C6416 Only)
EDMA BUS
HEX ADDRESS RANGE
PERIPHERAL BUS
ACRONYM
REGISTER NAME
TCP input configuration register 0
HEX ADDRESS RANGE
01BA 0000
01BA 0004
01BA 0008
01BA 000C
01BA 0010
01BA 0014
01BA 0018
01BA 001C
01BA 0020
01BA 0024
01BA 0028
01BA 002C
01BA 0030
−
5800 0000
5800 0004
5800 0008
5800 000C
5800 0010
5800 0014
5800 0018
5800 001C
5800 0020
5800 0024
5800 0028
5800 002C
5800 0030
5802 0000
5804 0000
5806 0000
5808 0000
580A 0000
−
TCPIC0
TCPIC1
TCPIC2
TCPIC3
TCPIC4
TCPIC5
TCPIC6
TCPIC7
TCPIC8
TCPIC9
TCPIC10
TCPIC11
TCPOUT
TCPSP
TCP input configuration register 1
TCP input configuration register 2
TCP input configuration register 3
TCP input configuration register 4
TCP input configuration register 5
TCP input configuration register 6
TCP input configuration register 7
TCP input configuration register 8
TCP input configuration register 9
TCP input configuration register 10
TCP input configuration register 11
TCP output parameters register
TCP systematics and parities memory
TCP extrinsic memory
−
TCPEXT
TCPAP
−
TCP apriori memory
−
TCPINTER
TCPHD
TCP interleaver memory
−
TCP hard decisions memory
TCP execution register
01BA 0038
01BA 0040
01BA 0050
01BA 0058
TCPEXE
TCPEND
TCPERR
TCPSTAT
−
TCP endian register
−
TCP error register
−
TCP status register
‡
These TCP registers are supported on the C6416 device only.
25
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ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢋ ꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢇ
ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
EDMA channel synchronization events
The C64x EDMA supports up to 64 EDMA channels which service peripheral devices and external memory.
Table 24 lists the source of C64x EDMA synchronization events associated with each of the programmable
EDMA channels. For the C64x device, the association of an event to a channel is fixed; each of the EDMA
channels has one specific event associated with it. These specific events are captured in the EDMA event
registers (ERL, ERH) even if the events are disabled by the EDMA event enable registers (EERL, EERH). The
priority of each event can be specified independently in the transfer parameters stored in the EDMA parameter
RAM. For more detailed information on the EDMA module and how EDMA events are enabled, captured,
processed, linked, chained, and cleared, etc., see the TMS320C6000 DSP Enhanced Direct Memory Access
(EDMA) Controller Reference Guide (literature number SPRU234).
26
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢊ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢊ ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
EDMA channel synchronization events (continued)
†
Table 24. SMJ320C64x EDMA Channel Synchronization Events
EDMA
CHANNEL
EVENT NAME
EVENT DESCRIPTION
‡
0
1
DSP_INT
TINT0
HPI/PCI-to-DSP interrupt (PCI peripheral supported on C6415 and C6416 only)
Timer 0 interrupt
2
TINT1
Timer 1 interrupt
3
SD_INTA
GPINT4/EXT_INT4
GPINT5/EXT_INT5
GPINT6/EXT_INT6
GPINT7/EXT_INT7
GPINT0
GPINT1
GPINT2
GPINT3
XEVT0
EMIFA SDRAM timer interrupt
GPIO event 4/External interrupt pin 4
GPIO event 5/External interrupt pin 5
GPIO event 6/External interrupt pin 6
GPIO event 7/External interrupt pin 7
GPIO event 0
4
5
6
7
8
9
GPIO event 1
10
11
GPIO event 2
GPIO event 3
12
13
14
15
16
17
18
19
20
21
22−27
28
29
30
31
32
33−39
40
41−47
48
49
50
51
52
53
54
55
56−63
McBSP0 transmit event
McBSP0 receive event
McBSP1 transmit event
McBSP1 receive event
None
REVT0
XEVT1
REVT1
–
XEVT2
McBSP2 transmit event
McBSP2 receive event
Timer 2 interrupt
REVT2
TINT2
SD_INTB
–
EMIFB SDRAM timer interrupt
Reserved, for future expansion
None
–
§
VCP receive event (C6416 only)
VCPREVT
VCPXEVT
TCPREVT
TCPXEVT
UREVT
§
VCP transmit event (C6416 only)
§
TCP receive event (C6416 only)
§
TCP transmit event (C6416 only)
‡
UTOPIA receive event (C6415 and C6416 only)
–
None
‡
UXEVT
UTOPIA transmit event (C6415 and C6416 only)
–
None
GPINT8
GPINT9
GPINT10
GPINT11
GPINT12
GPINT13
GPINT14
GPINT15
–
GPIO event 8
GPIO event 9
GPIO event 10
GPIO event 11
GPIO event 12
GPIO event 13
GPIO event 14
GPIO event 15
None
†
In addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate transfer
completion events. For more detailed information on EDMA event-transfer chaining, see the TMS320C6000 DSP Enhanced Direct Memory
Access (EDMA) Controller Reference Guide (literature number SPRU234).
The PCI and UTOPIA peripherals are not supported on the C6414 device; therefore, these EDMA synchronization events are reserved.
The VCP/TCP EDMA synchronization events are supported on the C6416 only. For the C6414 and C6415 devices, these events are reserved.
‡
§
27
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢋ ꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢇ
ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
interrupt sources and interrupt selector
The C64x DSP core supports 16 prioritized interrupts, which are listed in Table 25. The highest-priority interrupt
is INT_00 (dedicated to RESET) while the lowest-priority interrupt is INT_15. The first four interrupts
(INT_00−INT_03) are non-maskable and fixed. The remaining interrupts (INT_04−INT_15) are maskable and
default to the interrupt source specified in Table 25. The interrupt source for interrupts 4−15 can be programmed
by modifying the selector value (binary value) in the corresponding fields of the Interrupt Selector Control
registers: MUXH (address 0x019C0000) and MUXL (address 0x019C0004).
28
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢊ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢊ ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
interrupt sources and interrupt selector (continued)
Table 25. C64x DSP Interrupts
INTERRUPT
SELECTOR
CONTROL
REGISTER
CPU
INTERRUPT
NUMBER
SELECTOR
INTERRUPT
VALUE
(BINARY)
INTERRUPT SOURCE
EVENT
†
†
†
†
‡
‡
‡
‡
‡
‡
‡
INT_00
INT_01
INT_02
INT_03
INT_04
INT_05
INT_06
INT_07
INT_08
INT_09
INT_10
−
−
RESET
NMI
−
−
−
−
Reserved
Reserved
Reserved. Do not use.
Reserved. Do not use.
−
−
MUXL[4:0]
MUXL[9:5]
MUXL[14:10]
MUXL[20:16]
MUXL[25:21]
MUXL[30:26]
MUXH[4:0]
00100
00101
00110
00111
01000
01001
00011
GPINT4/EXT_INT4 GPIO interrupt 4/External interrupt pin 4
GPINT5/EXT_INT5 GPIO interrupt 5/External interrupt pin 5
GPINT6/EXT_INT6 GPIO interrupt 6/External interrupt pin 6
GPINT7/EXT_INT7 GPIO interrupt 7/External interrupt pin 7
EDMA_INT
EMU_DTDMA
SD_INTA
EDMA channel (0 through 63) interrupt
EMU DTDMA
EMIFA SDRAM timer interrupt
EMU real-time data exchange (RTDX)
receive
‡
INT_11
INT_12
INT_13
MUXH[9:5]
MUXH[14:10]
MUXH[20:16]
01010
01011
00000
EMU_RTDXRX
EMU_RTDXTX
DSP_INT
‡
‡
EMU RTDX transmit
HPI/PCI-to-DSP interrupt
(PCI supported on C6415 and C6416 only)
‡
‡
INT_14
MUXH[25:21]
00001
00010
01100
TINT0
TINT1
Timer 0 interrupt
INT_15
MUXH[30:26]
Timer 1 interrupt
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
XINT0
McBSP0 transmit interrupt
McBSP0 receive interrupt
McBSP1 transmit interrupt
McBSP1 receive interrupt
GPIO interrupt 0
01101
RINT0
01110
XINT1
01111
RINT1
10000
10001
10010
10011
GPINT0
XINT2
McBSP2 transmit interrupt
McBSP2 receive interrupt
Timer 2 interrupt
RINT2
TINT2
10100
10101
10110
SD_INTB
Reserved
Reserved
UINT
EMIFB SDRAM timer interrupt
Reserved. Do not use.
Reserved. Do not use.
UTOPIA interrupt (C6415/C6416 only)
Reserved. Do not use.
VCP interrupt (C6416 only)
TCP interrupt (C6416 only)
10111
11000 − 11101
11110
Reserved
VCPINT
TCPINT
11111
†
‡
Interrupts INT_00 through INT_03 are non-maskable and fixed.
Interrupts INT_04 through INT_15 are programmable by modifying the binary selector values in the Interrupt Selector Control
registers fields. Table 25 shows the default interrupt sources for Interrupts INT_04 through INT_15. For more detailed
information on interrupt sources and selection, see the TMS320C6000 DSP Interrupt Selector Reference Guide (literature
number SPRU646).
29
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢋ ꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢇ
ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
signal groups description
RESET
NMI
CLKIN
†
‡
‡
‡
‡
CLKOUT4/GP1
GP7/EXT_INT7
GP6/EXT_INT6
GP5/EXT_INT5
GP4/EXT_INT4
Reset and
Interrupts
†
CLKOUT6/GP2
Clock/PLL
CLKMODE1
CLKMODE0
PLLV
RSV
RSV
RSV
RSV
RSV
RSV
TMS
TDO
TDI
TCK
Reserved
•
•
•
TRST
EMU0
EMU1
IEEE Standard
1149.1
(JTAG)
Emulation
EMU2
EMU3
EMU4
EMU5
EMU6
EMU7
EMU8
EMU9
EMU10
EMU11
RSV
RSV
RSV
PCI_EN
MCBSP2_EN
Peripheral
Control/Status
Control/Status
‡
‡
‡
‡
§
GP7/EXT_INT7
GP6/EXT_INT6
GP5/EXT_INT5
GP4/EXT_INT4
GP3
GP15/PRST
§
§
GP14/PCLK
GP13/PINTA
§
GP12/PGNT
GPIO
§
GP11/PREQ
†
§
CLKOUT6/GP2
CLKOUT4/GP1
GP0
GP10/PCBE3
†
§
GP9/PIDSEL
†
CLKS2/GP8
General-Purpose Input/Output (GPIO) Port
†
These pins are MUXed with the GPIO port pins and by default these signals function as clocks (CLKOUT4 or CLKOUT6) or McBSP2
clock source (CLKS2). To use these MUXed pins as GPIO signals, the appropriate GPIO register bits (GPxEN and GPxDIR) must be
properly enabled and configured. For more details, see the Device Configurations section of this data sheet.
‡
§
These pins are GPIO pins that can also function as external interrupt sources (EXT_INT[7:4]). Default after reset is EXT_INTx or
GPIO as input-only.
For the C6415 and C6416 devices, these GPIO pins are MUXed with the PCI peripheral pins. By default, these signals are set up to
no function with both the GPIO and PCI pin functions disabled. For more details on these MUXed pins, see the Device
Configurations section of this data sheet. For the C6414 device, the GPIO peripheral pins are not MUXed; the C6414 device does
not support the PCI peripheral.
Figure 2. CPU and Peripheral Signals
30
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢊ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢊ ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
signal groups description (continued)
64
Data
AED[63:0]
AECLKIN
AECLKOUT1
ACE3
ACE2
AECLKOUT2
ASDCKE
Memory Map
Space Select
External
Memory I/F
Control
AARE/ASDCAS/ASADS/ASRE
ACE1
ACE0
AAOE/ASDRAS/ASOE
AAWE/ASDWE/ASWE
AARDY
20
Address
AEA[22:3]
ASOE3
ABE7
ABE6
ABE5
ABE4
ABE3
ABE2
ABE1
ABE0
APDT
Byte Enables
AHOLD
Bus
Arbitration
AHOLDA
ABUSREQ
†
EMIFA (64-bit)
16
Data
BED[15:0]
BECLKIN
BECLKOUT1
BECLKOUT2
BCE3
BCE2
BCE1
BCE0
External
Memory I/F
Control
BARE/BSDCAS/BSADS/BSRE
BAOE/BSDRAS/BSOE
BAWE/BSDWE/BSWE
BARDY
Memory Map
Space Select
20
BSOE3
BPDT
BEA[20:1]
Address
BBE1
BBE0
Byte Enables
EMIFB (16-bit)
BHOLD
Bus
Arbitration
BHOLDA
BBUSREQ
†
†
These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix “A” in front of a signal name indicates it is
an EMIFA signal whereas a prefix “B” in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document,
in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted from the signal name.
Figure 3. Peripheral Signals
31
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢋ ꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢇ
ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
signal groups description (continued)
†
HPI
(Host-Port Interface)
32
Data
HD[31:0]/AD[31:0]
HAS/PPAR
HR/W/PCBE2
HCS/PPERR
HDS1/PSERR
HDS2/PCBE1
HRDY/PIRDY
HCNTL0/PSTOP
HCNTL1/PDEVSEL
Register Select
Control
Half-Word
Select
HHWIL/PTRDY
(HPI16 ONLY)
HINT/PFRAME
32
HD[31:0]/AD[31:0]
Data/Address
Clock
GP14/PCLK
GP9/PIDSEL
HCNTL1/PDEVSEL
HINT/PFRAME
GP13/PINTA
HAS/PPAR
GP15/PRST
GP10/PCBE3
HR/W/PCBE2
HDS2/PCBE1
Command
Byte Enable
Control
§
PCBE0
HRDY/PIRDY
HCNTL0/PSTOP
HHWIL/PTRDY
GP12/PGNT
GP11/PREQ
Arbitration
HDS1/PSERR
HCS/PPERR
Error
DX2/XSP_DO
§
Serial
XSP_CS
EEPROM
CLKX2/XSP_CLK
DR2/XSP_DI
‡
PCI Interface
(C6415 and C6416 Only)
†
‡
For the C6415 and C6416 devices, these HPI pins are MUXed with the PCI peripheral. By default, these signals function as HPI. For
more details on these MUXed pins, see the Device Configurations section of this data sheet. For the C6414 device, these HPI pins are
not MUXed; the C6414 device does not support the PCI peripheral.
For the C6415 and C6416 devices, these PCI pins (excluding PCBE0 and XSP_CS) are MUXed with the HPI, McBSP2, or GPIO
peripherals. By default, these signals function as HPI, McBSP2, and no function, respectively. For more details on these MUXed pins,
see the Device Configurations section of this data sheet. For the C6414 device, the HPI, McBSP2, and GPIO peripheral pins are not
MUXed; the C6414 device does not support the PCI peripheral.
§
For the C6414 device, these pins are “Reserved (leave unconnected, do not connect to power or ground).”
Figure 3. Peripheral Signals (Continued)
32
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢊ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢊ ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
signal groups description (continued)
McBSP1
Transmit
McBSP0
†
CLKX0
FSX0
DX0
CLKX1/URADDR4
†
†
Transmit
FSX1/UXADDR3
DX1/UXADDR4
†
†
†
CLKR1/URADDR2
FSR1/UXADDR2
DR1/UXADDR1
CLKR0
FSR0
Receive
Clock
Receive
Clock
DR0
†
CLKS0
CLKS1/URADDR3
McBSP2
Transmit
†
CLKX2/XSP_CLK
FSX2
†
DX2/XSP_DO
CLKR2
FSR2
Receive
Clock
†
DR2/XSP_DI
McBSPs
(Multichannel Buffered
Serial Ports)
‡
CLKS2/GP8
†
‡
For the C6415 and C6416 devices, these McBSP2 and McBSP1 pins are MUXed with the PCI and UTOPIA peripherals, respectively.
By default, these signals function as McBSP2 and McBSP1, respectively. For more details on these MUXed pins, see the Device
Configurations section of this data sheet.
For the C6414 device, these McBSP2 and McBSP1 peripheral pins are not MUXed; the C6414 device does not support PCI and
UTOPIA peripherals.
The McBSP2 clock source pin (CLKS2, default) is MUXed with the GP8 pin. To use this MUXed pin as the GP8 signal, the appropriate
GPIO register bits (GP8EN and GP8DIR) must be properly enabled and configured. For more details, see the Device Configurations
section of this data sheet.
Figure 3. Peripheral Signals (Continued)
33
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢋ ꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢇ
ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
signal groups description (continued)
UTOPIA (SLAVE) [C6415 and C6416 Only]
URDATA7
URDATA6
URDATA5
URDATA4
URDATA3
URDATA2
UXDATA7
UXDATA6
UXDATA5
UXDATA4
UXDATA3
UXDATA2
Receive
Transmit
URDATA1
URDATA0
UXDATA1
UXDATA0
UXENB
URENB
†
†
CLKX1/URADDR4
DX1/UXADDR4
†
†
†
†
CLKS1/URADDR3
FSX1/UXADDR3
FSR1/UXADDR2
DR1/UXADDR1
UXADDR0
UXCLAV
UXSOC
†
CLKR1/URADDR2
Control/Status
Control/Status
URADDR1
URADDR0
URCLAV
URSOC
Clock
Clock
URCLK
UXCLK
TOUT1
TINP1
TOUT0
TINP0
Timer 0
Timers
Timer 1
Timer 2
TOUT2
TINP2
†
For the C6415 and C6416 devices, these UTOPIA pins are MUXed with the McBSP1 peripheral. By default, these signals function as
McBSP1. For more details on these MUXed pins, see the Device Configurations section of this data sheet.
For the C6414 device, these McBSP1 peripheral pins are not MUXed; the C6414 does not support the UTOPIA peripheral.
Figure 3. Peripheral Signals (Continued)
34
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ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢊ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢊ ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
DEVICE CONFIGURATIONS
The C6414, C6415, and C6416 peripheral selections and other device configurations are determined by
external pullup/pulldown resistors on the following pins (all of which are latched during device reset):
ꢀ
peripherals selection (C6415 and C6416 devices)
−
−
−
BEA11 (UTOPIA_EN)
PCI_EN (for C6415 or C6416, see Table 27 footnotes)
MCBSP2_EN (for C6414 or C6416, see Table 27 footnotes)
The C6414 device does not support the PCI and UTOPIA peripherals; for proper operation of the C6414
device, do not oppose the internal pulldowns (IPDs) on the BEA11, PCI_EN, and MCBSP2_EN pins. (For
IPUs/IPDs on pins, see the Terminal Functions table of this data sheet.)
ꢀ
other device configurations (C64x)
−
−
BEA[20:13, 7]
HD5
peripherals selection
Some C6415/C6416 peripherals share the same pins (internally MUXed) and are mutually exclusive (i.e., HPI,
general-purpose input/output pins GP[15:9], PCI and its internal EEPROM, McBSP1, McBSP2, and UTOPIA).
The VCP/TCP coprocessors (C6416 only) and other C64x peripherals (i.e., the Timers, McBSP0, and the
GP[8:0] pins), are always available.
ꢀ
UTOPIA and McBSP1 peripherals
The UTOPIA_EN pin (BEA11) is latched at reset. For C6415 and C6416 devices, this pin selects whether
the UTOPIA peripheral or McBSP1 peripheral is functionally enabled (see Table 26).
The C6414 device does not support the UTOPIA peripheral; for proper device operation, do not oppose the
internal pulldown (IPD) on the BEA11 pin.
Table 26. UTOPIA_EN Peripheral Selection (McBSP1 and UTOPIA) (C6415/C6416 Only)
PERIPHERAL SELECTION
PERIPHERALS SELECTED
DESCRIPTION
UTOPIA_EN
(BEA11) Pin [F14]
UTOPIA
McBSP1
McBSP1 is enabled and UTOPIA is disabled [default].
0
1
√
This means all multiplexed McBSP1/UTOPIA pins function as McBSP1
and all other standalone UTOPIA pins are tied-off (Hi-Z).
UTOPIA is enabled and McBSP1 is disabled.
This means all multiplexed McBSP1/UTOPIA pins now function as
UTOPIA and all other standalone McBSP1 pins are tied-off (Hi-Z).
√
ꢀ
HPI, GP[15:9], PCI, EEPROM (internal to PCI), and McBSP2 peripherals
The PCI_EN and MCBSP2_EN pins are latched at reset. They determine specific peripheral selection for
the C6415 and C6416 devices, summarized in Table 27.
The C6414 device does not support the PCI peripheral; for proper device operation, do not oppose the
internal pulldowns (IPDs) on the PCI_EN and MCBSP2_EN pins.
35
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ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
DEVICE CONFIGURATIONS (CONTINUED)
Table 27. PCI_EN and MCBSP2_EN Peripheral Selection (HPI, GP[15:9], PCI, and McBSP2)
†
PERIPHERAL SELECTION
PERIPHERALS SELECTED
PCI_EN
Pin [T8]
MCBSP2_EN
Pin [AB4]
EEPROM
(Internal to PCI)
HPI
GP[15:9]
PCI
McBSP2
0
0
1
1
0
1
0
1
√
√
√
√
√
√
‡
√
√
√
√
†
‡
The PCI_EN pin must be driven valid at all times and the user must not switch values throughout device operation.
The MCBSP2_EN pin must be driven valid at all times and the user can switch values throughout device operation.
The only time McBSP2 is disabled is when both PCI_EN = 1 and MCBSP2_EN = 0. This configuration enables, at reset, the auto-initialization
of the PCI peripheral through the PCI internal EEPROM [provided the PCI EEPROM Auto-Initialization pin (BEA13) is pulled up
(EEAI = 1)]. The user can then enable the McBSP2 peripheral (disabling EEPROM) by dynamically changing MCBSP2_EN to a “1” after the
device is initialized (out of reset).
−
If the PCI is disabled (PCI_EN = 0), the HPI peripheral is enabled and GP[15:9] pins can be programmed
as GPIO, provided the GPxEN and GPxDIR bits are properly configured.
This means all multiplexed HPI/PCI pins function as HPI and all standalone PCI pins (PCBE0 and
XSP_CS) are tied-off (Hi-Z). Also, the multiplexed GPIO/PCI pins can be used as GPIO with the
proper software configuration of the GPIO enable and direction registers (for more details, see
Table 29).
−
−
If the PCI is enabled (PCI_EN = 1), the HPI peripheral is disabled.
This means all multiplexed HPI/PCI pins function as PCI. Also, the multiplexed GPIO/PCI pins function
as PCI pins (for more details, see Table 29).
The MCBSP2_EN pin, in combination with the PCI_EN pin, controls the selection of the McBSP2
peripheral and the PCI internal EEPROM (for more details, see Table 27 and its footnotes).
other device configurations
Table 28 describes the C6414, C6415, and C6416 devices configuration pins, which are set up via external
pullup/pulldown resistors through the specified EMIFB address bus pins (BEA[20:13, 11, 9:7]) and the HD5 pin.
For more details on these device configuration pins, see the Terminal Functions table and the Debugging
Considerations section.
36
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢊ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢊ ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
DEVICE CONFIGURATIONS (CONTINUED)
Table 28. Device Configuration Pins (BEA[20:13, 9:7], HD5, and BEA11)
CONFIGURATION
PIN
NO.
FUNCTIONAL DESCRIPTION
Device Endian mode (LEND)
BEA20
E15
0
1
–
−
System operates in Big Endian mode
System operates in Little Endian mode (default)
Bootmode [1:0]
00 – No boot
01 − HPI boot
[D17,
J14]
BEA[19:18]
10 − EMIFB 8-bit ROM boot with default timings (default mode)
11 − Reserved
EMIFA input clock select
Clock mode select for EMIFA (AECLKIN_SEL[1:0])
00 – AECLKIN (default mode)
01 − CPU/4 Clock Rate
10 − CPU/6 Clock Rate
11 − Reserved
[E16,
G15]
BEA[17:16]
BEA[15:14]
EMIFB input clock select
Clock mode select for EMIFB (BECLKIN_SEL[1:0])
00 – BECLKIN (default mode)
01 − CPU/4 Clock Rate
[C18,
F15]
10 − CPU/6 Clock Rate
11 − Reserved
PCI EEPROM Auto-Initialization (EEAI) [C6415 and C6416 devices only]
[The C6414 device does not support the PCI peripheral; for proper device operation, do not oppose the
internal pulldown (IPD) on the BEA13 pin.]
PCI auto-initialization via external EEPROM
0
−
PCI auto-initialization through EEPROM is disabled; the PCI peripheral uses the specified
PCI default values (default).
1
−
PCI auto-initialization through EEPROM is enabled; the PCI peripheral is configured
through EEPROM provided the PCI peripheral pin is enabled (PCI_EN = 1) and the
McBSP2 peripheral pin is disabled (MCBSP2_EN = 0).
BEA13
D16
Note: If the PCI peripheral is disabled (PCI_EN pin = 0), this pin must not be pulled up.
For more information on the PCI EEPROM default values, see the TMS320C6000 DSP Peripheral
Component Interconnect (PCI) Reference Guide (literature number SPRU581).
UTOPIA Enable (UTOPIA_EN) [C6415 and C6416 devices only]
[The C6414 device does not support the UTOPIA peripheral; for proper device operation, do not
oppose the internal pulldown (IPD) on the BEA11 pin.]
UTOPIA peripheral enable (functional)
0
−
UTOPIA peripheral disabled (McBSP1 functions are enabled). [default]
This means all multiplexed McBSP1/UTOPIA pins function as McBSP1 and all other
standalone UTOPIA pins are tied-off (Hi-Z).
BEA11
F14
1
−
UTOPIA peripheral enabled (McBSP1 functions are disabled).
This means all multiplexed McBSP1/UTOPIA pins now function as UTOPIA and all other
standalone McBSP1 pins are tied-off (Hi-Z).
37
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢋ ꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢇ
ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
DEVICE CONFIGURATIONS (CONTINUED)
Table 28. Device Configuration Pins (BEA[20:13, 9:7], HD5, and BEA11) (Continued)
CONFIGURATION
PIN
NO.
FUNCTIONAL DESCRIPTION
C6415 Devices
C6414 Devices
C6416 Devices
†
BEA7
BEA8
BEA9
E14
G14
G13
Do not oppose internal pulldown (IPD) Pullup
Do not oppose IPD
Do not oppose IPD
Do not oppose IPD
†
†
Do not oppose IPD
Do not oppose IPD
Pullup
Pullup
†
For proper device operation, this pin must be externally pulled up with a 1-kΩ resistor.
HPI peripheral bus width (HPI_WIDTH)
0
−
HPI operates as an HPI16.
(HPI bus is 16 bits wide. HD[15:0] pins are used and the remaining HD[31:16] pins are
reserved pins in the Hi-Z state.)
HD5
U4
1
−
HPI operates as an HPI32.
(HPI bus is 32 bits wide. All HD[31:0] pins are used for host-port operations.)
38
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ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢊ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢊ ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
DEVICE CONFIGURATIONS (CONTINUED)
multiplexed pins
Multiplexed pins are pins that are shared by more than one peripheral and are internally multiplexed. Some of
these pins are configured by software, and the others are configured by external pullup/pulldown resistors only
at reset. Those MUXed pins that are configured by software can be programmed to switch functionalities at any
time. Those MUXed pins that are configured by external pullup/pulldown resistors are mutually exclusive; only
one peripheral has primary control of the function of these pins after reset. Table 29 identifies the multiplexed
pins on the C6414, C6415, and C6416 devices; shows the default (primary) function and the default settings
after reset; and describes the pins, registers, etc. necessary to configure specific multiplexed functions.
debugging considerations
It is recommended that external connections be provided to device configuration pins, including
CLKMODE[1:0], BEA[20:13, 11, 9:7], HD5/AD5, PCI_EN, and MCBSP2_EN. Although internal pullup/pulldown
resistors exist on these pins (except for HD5/AD5), providing external connectivity adds convenience to the user
in debugging and flexibility in switching operating modes.
Internal pullup/pulldown resistors also exist on the non-configuration pins on the BEA bus (BEA[12, 10, 6:1]).
Do not oppose the internal pullup/pulldown resistors on these non-configuration pins with external
pullup/pulldown resistors. If an external controller provides signals to these non-configuration pins, these
signals must be driven to the default state of the pins at reset, or not be driven at all.
For the internal pullup/pulldown resistors on the C6414, C6415, and C6416 device pins, see the terminal
functions table.
39
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
DEVICE CONFIGURATIONS (CONTINUED)
†
Table 29. C6414, C6415, and C6416 Device Multiplexed Pins
MULTIPLEXED PINS
NAME
DEFAULT FUNCTION
DEFAULT SETTING
DESCRIPTION
NO.
These pins are software-configurable.
To use these pins as GPIO pins, the
GPxEN bits in the GPIO Enable
Register and the GPxDIR bits in the
GPIO Direction Register must be
properly configured.
‡
CLKOUT4/GP1
CLKOUT6/GP2
Y7
CLKOUT4
GP1EN = 0 (disabled)
‡
T10
W7
CLKOUT6
CLKS2
GP2EN = 0 (disabled)
GP8EN = 0 (disabled)
GPxEN = 1: GPx pin enabled
GPxDIR = 0: GPx pin is an input
GPxDIR = 1: GPx pin is an output
‡
CLKS2/GP8
GP9/PIDSEL
GP10/PCBE3
GP11/PREQ
GP12/PGNT
GP13/PINTA
GP14/PCLK
GP15/PRST
K6
L7
To use GP[15:9] as GPIO pins, the PCI
needs to be disabled (PCI_EN = 0), the
GPxEN bits in the GPIO Enable
Register and the GPxDIR bits in the
GPIO Direction Register must be
properly configured.
H6
GPxEN = 0 (disabled)
PCI_EN = 0 (disabled)
J7
None
†
G4
GPxEN = 1: GPx pin enabled
GPxDIR = 0: GPx pin is an input
GPxDIR = 1: GPx pin is an output
G5
J8
DX1/UXADDR4
FSX1/UXADDR3
FSR1/UXADDR2
DR1/UXADDR1
CLKX1/URADDR4
CLKS1/URADDR3
CLKR1/URADDR2
CLKX2/XSP_CLK
DR2/XSP_DI
Y10
AA11
AA8
V11
T12
Y8
DX1
FSX1
By default, McBSP1 is enabled upon
reset (UTOPIA is disabled).
To enable the UTOPIA peripheral, an
external pullup resistor (1 kΩ) must be
provided on the BEA11 pin (setting
UTOPIA_EN = 1 at reset).
FSR1
UTOPIA_EN (BEA11) = 0
(disabled)
DR1
†
CLKX1
CLKS1
CLKR1
CLKX2
DR2
AB7
W5
Y4
DX2/XSP_DO
R9
§
DX2
HD[31:0]/AD[31:0]
HAS/PPAR
HD[31:0]
HAS
N7
N8
P5
R5
P6
N6
N5
P4
N9
N4
By default, HPI is enabled upon reset
(PCI is disabled).
HCNTL1/PDEVSEL
HCNTL0/PSTOP
HDS1/PSERR
HCNTL1
HCNTL0
HDS1
To enable the PCI peripheral an external
pullup resistor (1 kΩ) must be provided
on the PCI_EN pin (setting PCI_EN = 1
at reset).
†
PCI_EN = 0 (disabled)
HDS2/PCBE1
HDS2
HR/W/PCBE2
HR/W
HWWIL/PTRDY
HINT/PFRAME
HCS/PPERR
HHWIL (HPI16 only)
HINT
HCS
HRDY/PIRDY
HRDY
†
‡
§
For the C6415 and C6416 devices, all other standalone UTOPIA and PCI pins are tied-off internally (pins in Hi-Z) when the peripheral is disabled
[UTOPIA_EN (BEA11) = 0 or PCI_EN = 0].
The C6414 device does not support the PCI and UTOPIA peripherals. These are the only multiplexed pins on the C6414 device, all other pins
are standalone peripheral functions and are not MUXed.
For the HD[31:0]/AD[31:0] multiplexed pins pin numbers, see the Terminal Functions table.
40
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
Terminal Functions
SIGNAL
NAME
IPD/
IPU
†
DESCRIPTION
TYPE
‡
NO.
CLOCK/PLL CONFIGURATION
CLKIN
H4
Y7
I
IPD
IPD
Clock Input. This clock is the input to the on-chip PLL.
Clock output at 1/4 of the device speed (O/Z) [default] or this pin can be programmed as a
GPIO 1 pin (I/O/Z).
§
§
CLKOUT4/GP1
I/O/Z
Clock output at 1/6 of the device speed (O/Z) [default] or this pin can be programmed as a
GPIO 2 pin (I/O/Z).
CLKOUT6/GP2
CLKMODE1
CLKMODE0
T10
K8
I/O/Z
IPD
IPD
IPD
Clock mode select
I
I
•
Selects whether the CPU clock frequency = input clock frequency x1 (Bypass), x6, or x12.
For more details on the CLKMODE pins and the PLL multiply factors, see the Clock PLL
section of this data sheet.
E3
L9
¶
#
A
PLLV
PLL voltage supply
JTAG EMULATION
TMS
TDO
TDI
V14
W16
AA17
Y15
I
IPU
IPU
IPU
IPU
JTAG test-port mode select
JTAG test-port data out
JTAG test-port data in
JTAG test-port clock
O/Z
I
I
TCK
JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see the IEEE 1149.1 JTAG
Compatibility Statement section of this data sheet.
TRST
Y14
I
IPD
EMU11
EMU10
EMU9
EMU8
EMU7
EMU6
EMU5
EMU4
EMU3
EMU2
V15
Y16
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
Emulation pin 11. Reserved for future use, leave unconnected.
Emulation pin 10. Reserved for future use, leave unconnected.
Emulation pin 9. Reserved for future use, leave unconnected.
Emulation pin 8. Reserved for future use, leave unconnected.
Emulation pin 7. Reserved for future use, leave unconnected.
Emulation pin 6. Reserved for future use, leave unconnected.
Emulation pin 5. Reserved for future use, leave unconnected.
Emulation pin 4. Reserved for future use, leave unconnected.
Emulation pin 3. Reserved for future use, leave unconnected.
Emulation pin 2. Reserved for future use, leave unconnected.
Emulation [1:0] pins
T14
U14
AB18
AA16
W15
AB17
W14
AA15
•
Select the device functional mode of operation
EMU[1:0]
Operation
00
01
10
11
Boundary Scan/Normal Mode (see Note)
Reserved
Reserved
Emulation/Normal Mode [default] (see the IEEE 1149.1 JTAG
Compatibility Statement section of this data sheet)
EMU1
EMU0
T13
V13
I/O/Z
IPU
Normal mode refers to the DSPs normal operational mode, when the DSP is free running. The
DSP can be placed in normal operational mode when the EMU[1:0] pins are configured for
either Boundary Scan or Emulation.
Note: When the EMU[1:0] pins are configured for Boundary Scan mode, the internal pulldown
(IPD) on the TRST signal must not be opposed in order to operate in Normal mode.
For the Boundary Scan mode pulldown EMU[1:0] pins with a dedicated 1-kΩ resister.
†
‡
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
PLLV is not part of external voltage supply. See the Clock PLL section for information on how to connect this pin.
A = Analog signal (PLL Filter)
§
¶
#
41
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ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
Terminal Functions (Continued)
SIGNAL
IPD/
†
TYPE
DESCRIPTION
‡
IPU
NAME
NO.
RESETS, INTERRUPTS, AND GENERAL-PURPOSE INPUT/OUTPUTS
RESET
AB5
E6
I
I
Device reset
NMI
IPD
IPU
Nonmaskable interrupt, edge-driven (rising edge)
GP7/EXT_INT7
GP6/EXT_INT6
GP5/EXT_INT5
GP4/EXT_INT4
Y6
General-purpose input/output (GPIO) pins (I/O/Z) or external interrupts (input only). The
default after reset setting is GPIO enabled as input-only.
V8
•
When these pins function as External Interrupts [by selecting the corresponding interrupt
enable register bit (IER.[7:4])], they are edge-driven and the polarity can be
independently selected via the External Interrupt Polarity Register bits (EXTPOL.[3:0]).
I/O/Z
AA5
U9
J8
§
GP15/PRST
General-purpose input/output (GPIO) 15 pin (I/O/Z) or PCI reset (I). No function at default.
GPIO 14 pin (I/O/Z) or PCI clock (I). No function at default.
§
GP14/PCLK
G5
G4
J7
§
GP13/PINTA
GPIO 13 pin (I/O/Z) or PCI interrupt A (O/Z). No function at default.
GPIO 12 pin (I/O/Z) or PCI bus grant (I). No function at default.
§
GP12/PGNT
GP11/PREQ
§
H6
L7
GPIO 11 pin (I/O/Z) or PCI bus request (O/Z). No function at default.
GPIO 10 pin (I/O/Z) or PCI command/byte enable 3 (I/O/Z). No function at default.
GPIO 9 pin (I/O/Z) or PCI initialization device select (I). No function at default.
GPIO 3 pin (I/O/Z). The default after reset setting is GPIO 3 enabled as input-only.
§
GP10/PCBE3
I/O/Z
§
GP9/PIDSEL
GP3
K6
AA6
IPD
IPD
GPIO 0 pin.
The general-purpose I/O 0 pin (GPIO 0) (I/O/Z) can be programmed as GPIO 0 (input only)
[default] or as GPIO 0 (output only) pin or output as a general-purpose interrupt (GP0INT)
signal (output only).
GP0
W8
McBSP2 external clock source (CLKS2) [input only] [default] or this pin can be pro-
grammed as a GPIO 8 pin (I/O/Z).
§¶
CLKS2/GP8
W7
T10
Y7
I/O/Z
I/O/Z
I/O/Z
IPD
IPD
IPD
Clock output at 1/6 of the device speed (O/Z) [default] or this pin can be programmed as a
GPIO 2 pin (I/O/Z).
§¶
§¶
CLKOUT6/GP2
CLKOUT4/GP1
Clock output at 1/4 of the device speed (O/Z) [default] or this pin can be programmed as a
GPIO 1 pin (I/O/Z).
HOST-PORT INTERFACE (HPI) [C64x] or PERIPHERAL COMPONENT INTERCONNECT (PCI) [C6415 or C6416 devices only]
PCI enable pin. This pin controls the selection (enable/disable) of the HPI and GP[15:9], or
PCI peripherals (for the C6415 and C6416 devices). This pin works in conjunction with the
MCBSP2_EN pin to enable/disable other peripherals (for more details, see the Device Con-
figurations section of this data sheet).
PCI_EN
T8
I
IPD
The C6414 device does not support the PCI peripheral; for proper device operation, do not
oppose the internal pulldown (IPD) on this pin.
§
HINT/PFRAME
P4
N8
I/O/Z
I/O/Z
Host interrupt from DSP to host (O) [default] or PCI frame (I/O/Z)
HCNTL1/
Host control − selects between control, address, or data registers (I) [default] or PCI device
select (I/O/Z).
§
PDEVSEL
HCNTL0/
PSTOP
Host control − selects between control, address, or data registers (I) [default] or PCI stop
(I/O/Z)
P5
I/O/Z
§
Host half-word select − first or second half-word (not necessarily high or low order)
[For HPI16 bus width selection only] (I) [default] or PCI target ready (I/O/Z)
§
HHWIL/PTRDY
N5
N6
I/O/Z
I/O/Z
§
HR/W/PCBE2
Host read or write select (I) [default] or PCI command/byte enable 2 (I/O/Z)
†
‡
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
For the C6415 and C6416 devices, these pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
The C6414 device does not support the PCI or UTOPIA peripherals; therefore, these MUXed peripheral pins are standalone peripheral functions
for this device.
§
¶
For the C6414 device, only these pins are multiplexed pins.
42
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ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
Terminal Functions (Continued)
SIGNAL
NAME
IPD/
IPU
†
TYPE
DESCRIPTION
‡
NO.
HOST-PORT INTERFACE (HPI) [C64x] or PERIPHERAL COMPONENT INTERCONNECT (PCI) [C6415 or C6416 devices only]
(CONTINUED)
§
HAS/PPAR
N7
N9
R5
P6
N4
J4
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
Host address strobe (I) [default] or PCI parity (I/O/Z)
§
HCS/PPERR
Host chip select (I) [default] or PCI parity error (I/O/Z)
§
HDS1/PSERR
Host data strobe 1 (I) [default] or PCI system error (I/O/Z)
Host data strobe 2 (I) [default] or PCI command/byte enable 1 (I/O/Z)
Host ready from DSP to host (O) [default] or PCI initiator ready (I/O/Z).
§
HDS2/PCBE1
§
HRDY/PIRDY
§
§
§
§
§
§
§
§
§
§
§
§
§
§
§
§
§
§
§
§
HD31/AD31
HD30/AD30
HD29/AD29
HD28/AD28
HD27/AD27
HD26/AD26
HD25/AD25
HD24/AD24
HD23/AD23
HD22/AD22
HD21/AD21
HD20/AD20
HD19/AD19
HD18/AD18
HD17/AD17
HD16/AD16
HD15/AD15
HD14/AD14
HD13/AD13
HD12/AD12
K7
J5
K4
K5
L6
L8
J6
L5
Host-port data (I/O/Z) [default] (C64x) or PCI data-address bus (I/O/Z) [C6415 and C6416]
M5
M6
M8
L4
As HPI data bus (PCI_EN pin = 0)
•
•
Used for transfer of data, address, and control
Host-Port bus width user-configurable at device reset via a 10-kΩ resistor pullup/pulldown
resistor on the HD5 pin:
M4
M9
M7
P8
R6
R4
P7
R7
T5
T4
P9
T6
R8
U4
U5
T7
U6
V4
V5
HD5 pin = 0: HPI operates as an HPI16.
(HPI bus is 16 bits wide. HD[15:0] pins are used and the remaining HD[31:16] pins are
reserved pins in the high-impedance state.)
I/O/Z
HD5 pin = 1: HPI operates as an HPI32.
(HPI bus is 32 bits wide. All HD[31:0] pins are used for host-port operations.)
As PCI data-address bus (PCI_EN pin = 1) [C6415 and C6416 devices only]
Used for transfer of data and address
§
•
HD11/AD11
HD10/AD10
§
The C6414 device does not support the PCI peripheral; therefore, the HPI peripheral pins are
standalone peripheral functions, not MUXed.
§
§
§
§
§
§
§
§
§
§
HD9/AD9
HD8/AD8
HD7/AD7
HD6/AD6
HD5/AD5
HD4/AD4
HD3/AD3
HD2/AD2
HD1/AD1
HD0/AD0
†
‡
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
For the C6415 and C6416 devices, these pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
The C6414 device does not support the PCI or UTOPIA peripherals; therefore, these MUXed peripheral pins are standalone peripheral functions
for this device.
§
43
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ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
Terminal Functions (Continued)
SIGNAL
IPD/
†
TYPE
DESCRIPTION
‡
IPU
NAME
NO.
HOST-PORT INTERFACE (HPI) [C64x] or PERIPHERAL COMPONENT INTERCONNECT (PCI) [C6415 or C6416 devices only]
(CONTINUED)
PCI command/byte enable 0 (I/O/Z). When PCI is disabled (PCI_EN = 0), this pin is tied-off.
PCBE0
Y3
I/O/Z
O
For the C6414 device this pin is “Reserved (leave unconnected, do not connect to power or
ground).”
PCI serial interface chip select (O). When PCI is disabled (PCI_EN = 0), this pin is tied-off.
For the C6414 device this pin is “Reserved (leave unconnected, do not connect to power or
ground).”
XSP_CS
AA3
IPD
CLKX2/
XSP_CLK
W5
Y4
R9
I/O/Z
I
IPD
IPU
IPU
McBSP2 transmit clock (I/O/Z) [default] or PCI serial interface clock (O).
§
McBSP2 receive data (I) [default] or PCI serial interface data in (I). In PCI mode, this pin is
connected to the output data pin of the serial PROM.
§
DR2/XSP_DI
McBSP2 transmit data (O/Z) [default] or PCI serial interface data out (O). In PCI mode, this pin
is connected to the input data pin of the serial PROM.
§
DX2/XSP_DO
O/Z
§
GP15/PRST
J8
G5
G4
J7
General-purpose input/output (GPIO) 15 pin (I/O/Z) or PCI reset (I). No function at default.
GPIO 14 pin (I/O/Z) or PCI clock (I). No function at default.
§
GP14/PCLK
§
GP13/PINTA
GPIO 13 pin (I/O/Z) or PCI interrupt A (O/Z). No function at default.
GPIO 12 pin (I/O/Z) or PCI bus grant (I). No function at default.
§
§
GP12/PGNT
GP11/PREQ
I/O/Z
H6
L7
K6
GPIO 11 pin (I/O/Z) or PCI bus request (O/Z). No function at default.
GPIO 10 pin (I/O/Z) or PCI command/byte enable 3 (I/O/Z). No function at default.
§
GP10/PCBE3
§
GP9/PIDSEL
GPIO 9 pin (I/O/Z) or PCI initialization device select (I). No function at default.
ꢁ
||
EMIFA (64-bit) − CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY
ACE3
ACE2
ACE1
ACE0
ABE7
ABE6
ABE5
ABE4
ABE3
ABE2
ABE1
ABE0
APDT
K20
L17
J21
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
EMIFA memory space enables
•
•
Enabled by bits 28 through 31 of the word address
Only one pin is asserted during any external data access
K19
P19
U22
T22
R21
M17
M18
H22
L19
L20
EMIFA byte-enable control
•
Decoded from the low-order address bits. The number of address bits or byte enables
used depends on the width of external memory.
•
•
Byte-write enables for most types of memory
Can be directly connected to SDRAM read and write mask signal (SDQM)
EMIFA peripheral data transfer, allows direct transfer between external peripherals
†
‡
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
For the C6415 and C6416 devices, these pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
The C6414 device does not support the PCI or UTOPIA peripherals; therefore, these MUXed peripheral pins are standalone peripheral functions
for this device.
These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix “A” in front of a signal name indicates it is an EMIFA signal
whereas a prefix “B” in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of
discussion, the prefix “A” or “B” may be omitted from the signal name.
§
||
ꢁ To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.
44
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ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢊ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢊ ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
Terminal Functions (Continued)
SIGNAL
NAME
IPD/
IPU
†
TYPE
DESCRIPTION
‡
NO.
ꢁ
||
EMIFA (64-BIT) − BUS ARBITRATION
AHOLDA
AHOLD
M19
U21
P21
O
I
IPU
IPU
IPU
EMIFA hold-request-acknowledge to the host
EMIFA hold request from the host
EMIFA bus request output
ABUSREQ
O
ꢁ
||
EMIFA (64-BIT) − ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL
EMIFA external input clock. The EMIFA input clock (AECLKIN, CPU/4 clock, or CPU/6 clock)
is selected at reset via the pullup/pulldown resistors on the BEA[17:16] pins.
AECLKIN is the default for the EMIFA input clock.
AECLKIN
J19
I
IPD
EMIFA output clock 2. Programmable to be EMIFA input clock (AECLKIN, CPU/4 clock, or
CPU/6 clock) frequency divided-by-1, -2, or -4.
AECLKOUT2
AECLKOUT1
K18
H21
O/Z
O/Z
IPD
IPD
EMIFA output clock 1 [at EMIFA input clock (AECLKIN, CPU/4 clock, or CPU/6 clock)
frequency].
EMIFA asynchronous memory read-enable/SDRAM column-address strobe/programmable
synchronous interface-address strobe or read-enable
AARE/
ASDCAS/
ASADS/ASRE
•
For programmable synchronous interface, the RENEN field in the CE Space Secondary
Control Register (CExSEC) selects between ASADS and ASRE:
L16
J20
O/Z
O/Z
IPU
IPU
If RENEN = 0, then the ASADS/ASRE signal functions as the ASADS signal.
If RENEN = 1, then the ASADS/ASRE signal functions as the ASRE signal.
AAOE/
ASDRAS/
ASOE
EMIFA asynchronous memory output-enable/SDRAM row-address strobe/programmable
synchronous interface output-enable
AAWE/
ASDWE/
ASWE
EMIFA asynchronous memory write-enable/SDRAM write-enable/programmable synchro-
nous interface write-enable
G22
K21
O/Z
O/Z
IPU
IPU
EMIFA SDRAM clock-enable (used for self-refresh mode). [EMIFA module only.]
ASDCKE
•
If SDRAM is not in system, ASDCKE can be used as a general-purpose output.
ASOE3
AARDY
N16
L18
O/Z
I
IPU
IPU
EMIFA synchronous memory output-enable for ACE3 (for glueless FIFO interface)
Asynchronous memory ready input
ꢁ
||
EMIFA (64-BIT) − ADDRESS
AEA22
AEA21
AEA20
AEA19
AEA18
AEA17
AEA16
AEA15
AEA14
AEA13
AEA12
AEA11
R20
P16
T20
R18
V22
R19
T21
P17
N18
P18
P20
N17
O/Z
IPD
EMIFA external address (doubleword address)
†
‡
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix “A” in front of a signal name indicates it is an EMIFA signal
whereas a prefix “B” in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of
discussion, the prefix “A” or “B” may be omitted from the signal name.
||
ꢁ To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.
45
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢋ ꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢇ
ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
Terminal Functions (Continued)
SIGNAL
IPD/
†
TYPE
DESCRIPTION
‡
IPU
NAME
NO.
ꢁ
||
EMIFA (64-BIT) − ADDRESS (CONTINUED)
AEA10
N20
N21
N19
M21
M20
L21
M16
J22
AEA9
AEA8
AEA7
AEA6
AEA5
AEA4
AEA3
O/Z
IPD
EMIFA external address (doubleword address)
ꢁ
||
EMIFA (64-bit) − DATA
AED63
AED62
AED61
AED60
AED59
AED58
AED57
AED56
AED55
AED54
AED53
AED52
AED51
AED50
AED49
AED48
AED47
AED46
AED45
AED44
AED43
AED42
AED41
AED40
AED39
AED38
AED37
AB21
W18
Y19
V17
AA20
AA19
Y18
T15
U16
AB20
AA18
V16
W17
Y17
I/O/Z
IPU
EMIFA external data
U15
AB19
T19
U20
R17
Y22
V21
T18
U19
W21
V20
R16
T17
†
‡
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix “A” in front of a signal name indicates it is an EMIFA signal
whereas a prefix “B” in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of
discussion, the prefix “A” or “B” may be omitted from the signal name.
||
ꢁ To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.
46
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢊ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢊ ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
Terminal Functions (Continued)
SIGNAL
NAME
IPD/
IPU
†
TYPE
DESCRIPTION
‡
NO.
ꢁ
||
EMIFA (64-bit) − DATA (CONTINUED)
AED36
U18
Y21
V19
W20
AA22
D22
G19
F20
H18
E21
F21
G20
K16
J17
AED35
AED34
AED33
AED32
AED31
AED30
AED29
AED28
AED27
AED26
AED25
AED24
AED23
AED22
AED21
AED20
AED19
AED18
AED17
AED16
AED15
AED14
AED13
AED12
AED11
AED10
AED9
E22
G21
J18
H19
H20
K17
F22
F16
E17
H15
C20
D18
G16
F17
D19
E18
J15
I/O/Z
IPU
EMIFA external data
AED8
AED7
AED6
AED5
H16
G17
D20
F18
E19
C21
AED4
AED3
AED2
AED1
AED0
†
‡
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix “A” in front of a signal name indicates it is an EMIFA signal
whereas a prefix “B” in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of
discussion, the prefix “A” or “B” may be omitted from the signal name.
||
ꢁ To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.
47
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢋ ꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢇ
ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
Terminal Functions (Continued)
SIGNAL
IPD/
†
TYPE
DESCRIPTION
‡
IPU
NAME
NO.
ꢁ
||
EMIFB (16-bit) − CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY
BCE3
D11
C9
O/Z
O/Z
O/Z
O/Z
IPU
IPU
IPU
IPU
EMIFB memory space enables
BCE2
BCE1
BCE0
•
•
Enabled by bits 26 through 31 of the word address
Only one pin is asserted during any external data access
H12
G12
EMIFB byte-enable control
BBE1
D12
O/Z
IPU
•
Decoded from the low-order address bits. The number of address bits or byte enables
used depends on the width of external memory.
•
•
Byte-write enables for most types of memory
Can be directly connected to SDRAM read and write mask signal (SDQM)
BBE0
BPDT
E12
E11
O/Z
O/Z
IPU
IPU
EMIFB peripheral data transfer, allows direct transfer between external peripherals
ꢁ
||
EMIFB (16-BIT) − BUS ARBITRATION
BHOLDA
BHOLD
F12
C19
D14
O
I
IPU
IPU
IPU
EMIFB hold-request-acknowledge to the host
EMIFB hold request from the host
EMIFB bus request output
BBUSREQ
O
ꢁ
||
EMIFB (16-BIT) − ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL
EMIFB external input clock. The EMIFB input clock (BECLKIN, CPU/4 clock, or CPU/6 clock)
is selected at reset via the pullup/pulldown resistors on the BEA[15:14] pins.
BECLKIN is the default for the EMIFB input clock.
BECLKIN
E10
I
IPD
EMIFB output clock 2. Programmable to be EMIFB input clock (BECLKIN, CPU/4 clock, or
CPU/6 clock) frequency divided by 1, 2, or 4.
BECLKOUT2
BECLKOUT1
C8
O/Z
O/Z
IPD
IPD
EMIFB output clock 1 [at EMIFB input clock (BECLKIN, CPU/4 clock, or CPU/6 clock)
frequency].
J12
EMIFB asynchronous memory read-enable/SDRAM column-address strobe/programmable
synchronous interface-address strobe or read-enable
BARE/
BSDCAS/
BSADS/BSRE
•
For programmable synchronous interface, the RENEN field in the CE Space Secondary
Control Register (CExSEC) selects between BSADS and BSRE:
C7
O/Z
IPU
If RENEN = 0, then the BSADS/BSRE signal functions as the BSADS signal.
If RENEN = 1, then the BSADS/BSRE signal functions as the BSRE signal.
BAOE/
BSDRAS/
BSOE
EMIFB asynchronous memory output-enable/SDRAM row-address strobe/programmable
synchronous interface output-enable
D10
F11
O/Z
O/Z
IPU
IPU
BAWE/BSDWE/
BSWE
EMIFB asynchronous memory write-enable/SDRAM write-enable/programmable synchro-
nous interface write-enable
BSOE3
BARDY
J13
O/Z
I
IPU
IPU
EMIFB synchronous memory output enable for BCE3 (for glueless FIFO interface)
EMIFB asynchronous memory ready input
G11
†
‡
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix “A” in front of a signal name indicates it is an EMIFA signal
whereas a prefix “B” in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of
discussion, the prefix “A” or “B” may be omitted from the signal name.
||
ꢁ To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.
48
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢊ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢊ ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
Terminal Functions (Continued)
SIGNAL
NAME
IPD/
IPU
†
TYPE
DESCRIPTION
‡
NO.
ꢁ
||
EMIFB (16-BIT) − ADDRESS
EMIFB external address (half-word address) (O/Z)
BEA20
E15
D17
J14
IPU
IPU
•
Also controls initialization of DSP modes at reset (I) via pullup/pulldown resistors
− Device Endian mode
BEA20:
0
1
–
−
Big Endian
Little Endian (default mode)
BEA19
BEA18
BEA17
BEA16
BEA15
BEA14
BEA13
BEA12
BEA11
BEA10
BEA9
− Boot mode
BEA[19:18]: 00 – No boot
01 − HPI boot
E16
G15
C18
F15
D16
H14
F14
C17
G13
G14
E14
H13
C16
D15
E13
D13
F13
10 − EMIFB 8-bit ROM boot with default timings (default mode)
11 − Reserved
− EMIF clock select
BEA[17:16]: Clock mode select for EMIFA (AECLKIN_SEL[1:0])
00 – AECLKIN (default mode)
01 − CPU/4 Clock Rate
10 − CPU/6 Clock Rate
11 − Reserved
BEA[15:14]: Clock mode select for EMIFB (BECLKIN_SEL[1:0])
00 – BECLKIN (default mode)
01 − CPU/4 Clock Rate
10 − CPU/6 Clock Rate
11 − Reserved
− PCI EEPROM Auto-Initialization (EEAI) [C6415 and C6416 devices only]
BEA13:
PCI auto-initialization via external EEPROM
I/O/Z
IPD
If the PCI peripheral is disabled (PCI_EN pin = 0), this pin must not be pulled up.
0
1
−
−
PCI auto-initialization through EEPROM is disabled (default).
PCI auto-initialization through EEPROM is enabled.
BEA8
− UTOPIA Enable (UTOPIA_EN) [C6415 and C6416 devices only]
BEA11: UTOPIA peripheral enable (functional)
BEA7
0
1
−
−
UTOPIA disabled (McBSP1 enabled) [default]
UTOPIA enabled (McBSP1 disabled)
BEA6
The C6414 device does not support the PCI and UTOPIA peripherals; for proper device
operation, do not oppose the internal pulldowns (IPDs) on the BEA13 and BEA11 pins.
BEA5
Also for proper C6414 device operation, do not oppose the IPDs on the BEA7, BEA8,
and BEA9 pins.
BEA4
For proper C6415 device operation, the BEA7 pin must be externally pulled up with a
1-kΩ resistor.
BEA3
BEA2
For proper C6416 device operation, the BEA8 and BEA9 pins must be externally pulled
up with a 1-kΩ resistor.
BEA1
For more details, see the Device Configurations section of this data sheet.
†
‡
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix “A” in front of a signal name indicates it is an EMIFA signal
whereas a prefix “B” in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of
discussion, the prefix “A” or “B” may be omitted from the signal name.
||
ꢁ
T
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m
a
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.
49
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢋ ꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢇ
ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
Terminal Functions (Continued)
SIGNAL
IPD/
†
TYPE
DESCRIPTION
‡
IPU
NAME
NO.
ꢁ
||
EMIFB (16-bit) − DATA
BED15
F8
J10
D7
BED14
BED13
BED12
BED11
BED10
BED9
BED8
BED7
BED6
BED5
BED4
BED3
BED2
BED1
BED0
C5
H10
G9
C6
E8
I/O/Z
IPU
EMIFB external data
E9
F9
G10
J11
D9
D8
H11
F10
MULTICHANNEL BUFFERED SERIAL PORT 2 (McBSP2)
McBSP2 enable pin. This pin works in conjunction with the PCI_EN pin to enable/disable other
peripherals (for more details, see the Device Configurations section of this data sheet).
MCBSP2_EN
AB4
W7
W4
W5
Y4
I
IPD
McBSP2 external clock source (CLKS2) [input only] [default] or this pin can also be
programmed as a GPIO 8 pin (I/O/Z).
§
CLKS2/GP8
I/O/Z
I/O/Z
I/O/Z
I
IPD
McBSP2 receive clock. When McBSP2 is disabled (PCI_EN = 1 and MCBSP2_EN pin = 0),
this pin is tied-off.
CLKR2
CLKX2/
IPD
IPD
IPU
IPU
IPD
IPD
McBSP2 transmit clock (I/O/Z) [default] or PCI serial interface clock (O).
§
XSP_CLK
McBSP2 receive data (I) [default] or PCI serial interface data in (I). In PCI mode, this pin is
connected to the output data pin of the serial PROM.
§
DR2/XSP_DI
McBSP2 transmit data (O/Z) [default] or PCI serial interface data out (O). In PCI mode, this pin
is connected to the input data pin of the serial PROM.
§
DX2/XSP_DO
R9
O/Z
I/O/Z
I/O/Z
McBSP2 receive frame sync. When McBSP2 is disabled (PCI_EN = 1 and MCBSP2_EN pin
= 0), this pin is tied-off.
FSR2
V6
McBSP2 transmit frame sync. When McBSP2 is disabled (PCI_EN = 1 and MCBSP2_EN pin
= 0), this pin is tied-off.
FSX2
U7
†
‡
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
For the C6415 and C6416 devices, these pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
The C6414 device does not support the PCI or UTOPIA peripherals; therefore, these MUXed peripheral pins except CLKS2/GP8 are standalone
peripheral functions for this device.
These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix “A” in front of a signal name indicates it is an EMIFA signal
whereas a prefix “B” in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of
discussion, the prefix “A” or “B” may be omitted from the signal name.
§
||
ꢁ To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.
50
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢊ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢊ ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
Terminal Functions (Continued)
SIGNAL
NAME
IPD/
IPU
†
TYPE
DESCRIPTION
‡
NO.
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)
CLKS1/
URADDR3
McBSP1 external clock source (as opposed to internal) (I) [default] or UTOPIA receive
address 3 pin (I)
Y8
AB7
T12
V11
I
§
§
§
CLKR1/
URADDR2
I/O/Z
I/O/Z
I
McBSP1 receive clock (I/O/Z) [default] or UTOPIA receive address 2 pin (I)
McBSP1 transmit clock (I/O/Z) [default] or UTOPIA receive address 4 pin (I)
McBSP1 receive data (I) [default] or UTOPIA transmit address 1 pin (I)
McBSP1 transmit data (O/Z) [default] or UTOPIA transmit address 4 pin (I)
McBSP1 receive frame sync (I/O/Z) [default] or UTOPIA transmit address 2 pin (I)
CLKX1/
URADDR4
DR1/
UXADDR1
§
§
§
§
DX1/
UXADDR4
Y10
AA8
AA11
I/O/Z
I/O/Z
I/O/Z
FSR1/
UXADDR2
FSX1/
UXADDR3
McBSP1 transmit frame sync (I/O/Z) [default] or UTOPIA transmit address 3 pin (I)
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)
CLKS0
CLKR0
CLKX0
DR0
F4
F5
K9
G6
E4
D3
H7
I
IPD
IPD
IPD
IPU
IPU
IPD
IPD
McBSP0 external clock source (as opposed to internal)
McBSP0 receive clock
I/O/Z
I/O/Z
I
McBSP0 transmit clock
McBSP0 receive data
DX0
O/Z
I/O/Z
I/O/Z
McBSP0 transmit data
FSR0
FSX0
McBSP0 receive frame sync
McBSP0 transmit frame sync
TIMER 2
TOUT2
TINP2
F7
D5
O/Z
I
IPD
IPD
Timer 2 or general-purpose output
Timer 2 or general-purpose input
TIMER 1
TOUT1
TINP1
G8
D6
O/Z
I
IPD
IPD
Timer 1 or general-purpose output
Timer 1 or general-purpose input
TIMER 0
TOUT0
TINP0
H9
E7
O/Z
I
IPD
IPD
Timer 0 or general-purpose output
Timer 0 or general-purpose input
†
‡
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
For the C6415 and C6416 devices, these pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
The C6414 device does not support the PCI or UTOPIA peripherals; therefore, these MUXed peripheral pins are standalone peripheral functions
for this device.
§
51
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢋ ꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢇ
ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
Terminal Functions (Continued)
SIGNAL
IPD/
†
TYPE
DESCRIPTION
‡
IPU
NAME
NO.
UNIVERSAL TEST AND OPERATIONS PHY INTERFACE FOR ASYNCHRONOUS TRANSFER MODE (ATM) [UTOPIA SLAVE]
[C6415 and C6416 devices only]
UTOPIA SLAVE (ATM CONTROLLER) − TRANSMIT INTERFACE
Source clock for UTOPIA transmit driven by Master ATM Controller.
When the UTOPIA peripheral is disabled (UTOPIA_EN [BEA11 pin] = 0), this pin is tied-off.
Y
UXCLK
AB8
I
ꢂ
Transmit cell available status output signal from UTOPIA Slave.
0
1
indicates a complete cell is NOT available for transmit
indicates a complete cell is available for transmit
Y
UXCLAV
AA13
O/Z
When the UTOPIA peripheral is disabled (UTOPIA_EN [BEA11 pin] = 0), this pin is tied-off.
UTOPIA transmit interface enable input signal. Asserted by the Master ATM Controller to indi-
cate that the UTOPIA Slave should put out on the Transmit Data Bus the first byte of valid data
and the UXSOC signal in the next clock cycle.
Y
UXENB
U13
Y12
I
◊
When the UTOPIA peripheral is disabled (UTOPIA_EN [BEA11 pin] = 0), this pin is tied-off.
Transmit Start-of-Cell signal. This signal is output by the UTOPIA Slave on the rising edge of
the UXCLK, indicating that the first valid byte of the cell is available on the 8-bit Transmit Data
Bus (UXDATA[7:0]).
Y
UXSOC
O/Z
When the UTOPIA peripheral is disabled (UTOPIA_EN [BEA11 pin] = 0), this pin is tied-off.
McBSP1 [default] or UTOPIA transmit address pins
As UTOPIA transmit address pins UXADDR[4:0] (I), UTOPIA_EN (BEA11 pin) = 1:
•
5-bit Slave transmit address input pins driven by the Master ATM Controller to identify and
select one of the Slave devices (up to 31 possible) in the ATM System.
DX1/
UXADDR4
Y10
I/O/Z
◊
§
•
UXADDR0 pin is tied off when the UTOPIA peripheral is disabled [UTOPIA_EN
(BEA11 pin) = 0]
For the McBSP1 pin functions (UTOPIA_EN (BEA11 pin) = 0 [default]), see the MULTICHAN-
NEL BUFFERED SERIAL PORT 1 (McBSP1) section of this table.
McBSP1 [default] or UTOPIA transmit address pins
FSX1/
UXADDR3
AA11
AA8
I/O/Z
I/O/Z
◊
◊
§
§
As UTOPIA transmit address pins UXADDR[4:0] (I), UTOPIA_EN (BEA11 pin) = 1:
•
5-bit Slave transmit address input pins driven by the Master ATM Controller to identify and
select one of the Slave devices (up to 31 possible) in the ATM System.
FSR1/
UXADDR2
•
UXADDR0 pin is tied off when the UTOPIA peripheral is disabled [UTOPIA_EN
(BEA11 pin) = 0]
DR1/
UXADDR1
V11
Y9
I
I
◊
◊
§
For the McBSP1 pin functions (UTOPIA_EN (BEA11 pin) = 0 [default]), see the MULTICHAN-
NEL BUFFERED SERIAL PORT 1 (McBSP1) section of this table.
Y
UXADDR0
†
‡
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
For the C6415 and C6416 devices, these pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
The C6414 device does not support the PCI or UTOPIA peripherals; therefore, these MUXed peripheral pins are standalone peripheral functions
for this device.
§
ꢂ For the C6415 and C6416 devices, external pulldowns required: If UTOPIA is selected (BEA11 = 1) and these pins are connected to other devices,
then a 10-kΩ resistor must be used to externally pull down each of these pins. If these pins are “no connects”, then only UXCLK and URCLK
need to be pulled down and other pulldowns are not necessary.
◊ For the C6415 and C6416 devices, external pullups required: If UTOPIA is selected (BEA11 = 1) and these pins are connected to other devices,
then a 10-kΩ resistor must be used to externally pull up each of these pins. If these pins are “no connects”, then the pullups are not necessary.
ΨThe C6414 device does not support the UTOPIA peripheral; therefore, these standalone UTOPIA pins are Reserved (leave unconnected, do
not connect to power or ground) with the exception of UXCLK and URCLK which should be connected to a 10-kΩ pulldown resistor (see the
square [ꢂ ] footnote).
52
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢊ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢊ ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
Terminal Functions (Continued)
SIGNAL
NAME
IPD/
IPU
†
TYPE
DESCRIPTION
‡
NO.
UTOPIA SLAVE (ATM CONTROLLER) − TRANSMIT INTERFACE (CONTINUED)
Y
Y
Y
Y
Y
Y
Y
Y
UXDATA7
UXDATA6
UXDATA5
UXDATA4
UXDATA3
UXDATA2
UXDATA1
UXDATA0
W10
T11
W9
8-bit Transmit Data Bus
Using the Transmit Data Bus, the UTOPIA Slave (on the rising edge of the UXCLK) transmits
the 8-bit ATM cells to the Master ATM Controller.
When the UTOPIA peripheral is disabled (UTOPIA_EN [BEA11 pin] = 0), these pins are tied-
off.
AB6
V10
U10
AA7
V9
O/Z
UTOPIA SLAVE (ATM CONTROLLER) − RECEIVE INTERFACE
Source clock for UTOPIA receive driven by Master ATM Controller.
When the UTOPIA peripheral is disabled (UTOPIA_EN [BEA11 pin] = 0), this pin is tied-off.
Y
URCLK
U12
I
ꢂ
Receive cell available status output signal from UTOPIA Slave.
0
1
indicates NO space is available to receive a cell from Master ATM Controller
indicates space is available to receive a cell from Master ATM Controller
Y
URCLAV
AA14
O/Z
When the UTOPIA peripheral is disabled (UTOPIA_EN [BEA11 pin] = 0), this pin is tied-off.
UTOPIA receive interface enable input signal. Asserted by the Master ATM Controller to indi-
cate to the UTOPIA Slave to sample the Receive Data Bus (URDATA[7:0]) and URSOC signal
in the next clock cycle or thereafter.
Y
URENB
AB16
W13
I
I
◊
When the UTOPIA peripheral is disabled (UTOPIA_EN [BEA11 pin] = 0), this pin is tied-off.
Receive Start-of-Cell signal. This signal is output by the Master ATM Controller to indicate to
the UTOPIA Slave that the first valid byte of the cell is available to sample on the 8-bit Receive
Data Bus (URDATA[7:0]).
Y
URSOC
CLKX1/
ꢂ
When the UTOPIA peripheral is disabled (UTOPIA_EN [BEA11 pin] = 0), this pin is tied-off.
McBSP1 [default] or UTOPIA receive address pins
T12
Y8
I/O/Z
I
◊
◊
◊
§
§
URADDR4
As UTOPIA receive address pins URADDR[4:0] (I), UTOPIA_EN (BEA11 pin) = 1:
CLKS1/
•
5-bit Slave receive address input pins driven by the Master ATM Controller to identify and
select one of the Slave devices (up to 31 possible) in the ATM System.
URADDR3
CLKR1/
URADDR2
AB7
I/O/Z
•
URADDR1 and URADDR0 pins are tied off when the UTOPIA peripheral is disabled
[UTOPIA_EN (BEA11 pin) = 0]
§
Y
Y
URADDR1
U11
AA9
I
I
◊
◊
For the McBSP1 pin functions (UTOPIA_EN (BEA11 pin) = 0 [default]), see the MULTICHAN-
NEL BUFFERED SERIAL PORT 1 (McBSP1) section of this table.
URADDR0
†
‡
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
§
These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
ꢂ External pulldowns required: If UTOPIA is selected (BEA11 = 1) and these pins are connected to other devices, then a 10-kΩ resistor must be
used to externally pull down each of these pins. If these pins are “no connects”, then only UXCLK and URCLK need to be pulled down and other
pulldowns are not necessary.
◊ External pullups required: If UTOPIA is selected (BEA11 = 1) and these pins are connected to other devices, then a 10-kΩ resistor must be used
to externally pull up each of these pins. If these pins are “no connects”, then the pullups are not necessary.
ΨThe C6414 device does not support the UTOPIA peripheral; therefore, these standalone UTOPIA pins are Reserved (leave unconnected, do
not connect to power or ground) with the exception of UXCLK and URCLK which should be connected to a 10-kΩ pulldown resistor (see the
square [ꢂ ] footnote).
53
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢋ ꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢇ
ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
Terminal Functions (Continued)
SIGNAL
IPD/
†
TYPE
DESCRIPTION
‡
IPU
NAME
NO.
UTOPIA SLAVE (ATM CONTROLLER) − RECEIVE INTERFACE (CONTINUED)
Y
URDATA7
URDATA6
URDATA5
URDATA4
URDATA3
URDATA2
URDATA1
URDATA0
AA10
V12
Y
Y
Y
Y
Y
Y
Y
W12
W11
Y11
8-bit Receive Data Bus.
Using the Receive Data Bus, the UTOPIA Slave (on the rising edge of the URCLK) can receive
the 8-bit ATM cell data from the Master ATM Controller.
When the UTOPIA peripheral is disabled (UTOPIA_EN [BEA11 pin] = 0), these pins are tied-
off.
I
AB9
Y13
AA12
RESERVED FOR TEST
C4
H5
H3
N3
P3
RSV
Reserved (leave unconnected, do not connect to power or ground)
†
‡
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
ꢂ External pulldowns required: If UTOPIA is selected (BEA11 = 1) and these pins are connected to other devices, then a 10-kΩ resistor must be
used to externally pull down each of these pins. If these pins are “no connects”, then only UXCLK and URCLK need to be pulled down and other
pulldowns are not necessary.
ΨThe C6414 device does not support the UTOPIA peripheral; therefore, these standalone UTOPIA pins are Reserved (leave unconnected, do
not connect to power or ground) with the exception of UXCLK and URCLK which should be connected to a 10-kΩ pulldown resistor (see the
square [ꢂ ] footnote).
54
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢊ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢊ ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
Terminal Functions (Continued)
SIGNAL
NAME
†
TYPE
DESCRIPTION
SUPPLY VOLTAGE PINS
NO.
AA23
AB10
AB11
AB14
AB15
AB2
AB23
AC10
AC12
AC14
AC16
AC19
AC21
AC22
AC3
AC4
AC6
AC8
B11
B13
B15
B17
B19
B21
B22
B3
3.3-V supply voltage
(see the Power-Supply Decoupling section of this data sheet)
DV
S
DD
B4
B6
B9
C10
C11
C14
C15
C23
D2
D23
F2
F23
F3
G3
H2
J23
†
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
55
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢋ ꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢇ
ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
Terminal Functions (Continued)
SIGNAL
†
TYPE
DESCRIPTION
SUPPLY VOLTAGE PINS (CONTINUED)
NAME
NO.
J3
K2
K22
K3
L22
L23
M2
N23
P2
P22
R22
R23
T2
3.3-V supply voltage
(see the Power-Supply Decoupling section of this data sheet)
DV
S
DD
T3
U23
U3
V2
V3
W23
W3
Y2
A10
A12
A14
A16
A18
A20
A22
A4
A6
A8
1.4 V supply voltage
(see the Power-Supply Decoupling section of this data sheet)
AA1
AB12
AB13
AB24
AC18
AC20
AC5
AD11
AD13
AD15
AD17
CV
S
DD
†
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
56
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢊ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢊ ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
Terminal Functions (Continued)
SIGNAL
NAME
†
TYPE
DESCRIPTION
SUPPLY VOLTAGE PINS (CONTINUED)
NO.
AD19
AD21
AD23
AD3
AD5
AD7
AD9
B20
B24
B5
B7
C1
C12
C13
C2
D24
E1
E23
F24
G1
1.4 V supply voltage
(see the Power-Supply Decoupling section of this data sheet)
CV
S
DD
G23
H24
J1
K10
K12
K14
K24
L1
L11
L13
L15
L3
M10
M12
M14
M22
M24
M3
N1
†
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
57
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢋ ꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢇ
ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
Terminal Functions (Continued)
SIGNAL
†
TYPE
DESCRIPTION
SUPPLY VOLTAGE PINS (CONTINUED
NAME
NO.
N11
N13
N15
N22
P10
P12
P14
P24
R1
1.4 V supply voltage
(see the Power-Supply Decoupling section of this data sheet)
R11
R13
R15
R3
CV
S
DD
T24
U1
V24
W1
Y23
Y24
GROUND PINS
A11
A13
A15
A17
A19
A21
A23
A3
A5
A7
A9
V
SS
GND
Ground pins
AA2
AA21
AA24
AA4
AB1
AB22
AB3
AC1
AC11
AC13
AC15
†
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
58
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢊ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢊ ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
Terminal Functions (Continued)
SIGNAL
NAME
†
TYPE
DESCRIPTION
NO.
GROUND PINS
AC17
AC2
AC23
AC24
AC7
AC9
AD10
AD12
AD14
AD16
AD18
AD2
AD20
AD22
AD4
AD6
AD8
B10
B12
B14
B16
B18
B2
V
SS
GND
Ground pins
B23
B8
C22
C24
C3
D1
D21
D4
E2
E20
E24
E5
F1
F19
F6
G18
†
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
59
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢋ ꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢇ
ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
Terminal Functions (Continued)
SIGNAL
†
TYPE
DESCRIPTION
GROUND PINS (CONTINUED)
NAME
NO.
G2
G24
G7
H1
H17
H23
H8
J16
J2
J24
J9
K1
K11
K13
K15
K23
L10
L12
L14
L2
V
SS
GND
Ground pins
L24
M1
M11
M13
M15
M23
N10
N12
N14
N2
N24
P1
P11
P13
P15
P23
R10
R12
R14
†
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
60
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢊ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢊ ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
Terminal Functions (Continued)
SIGNAL
NAME
†
TYPE
DESCRIPTION
GROUND PINS (CONTINUED)
NO.
R2
R24
T1
T16
T23
T9
U17
U2
U24
U8
V1
V
SS
GND
Ground pins
V18
V23
V7
W19
W2
W24
W6
Y1
Y20
Y5
†
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
61
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢋ ꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢇ
ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
development support
TI offers an extensive line of development tools for the TMS320C6000 DSP platform, including tools to
evaluate the performance of the processors, generate code, develop algorithm implementations, and fully
integrate and debug software and hardware modules.
The following products support development of C6000 DSP-based applications:
Software Development Tools:
Code Composer Studio Integrated Development Environment (IDE): including Editor
C/C++/Assembly Code Generation, and Debug plus additional development tools
Scalable, Real-Time Foundation Software (DSP/BIOS), which provides the basic run-time target software
needed to support any DSP application.
Hardware Development Tools:
Extended Development System (XDS) Emulator (supports C6000 DSP multiprocessor system debug)
EVM (Evaluation Module)
For a complete listing of development-support tools for the TMS320C6000 DSP platform, visit the Texas
Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). For
information on pricing and availability, contact the nearest TI field sales office or authorized distributor.
Code Composer Studio, DSP/BIOS, and XDS are trademarks of Texas Instruments.
62
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢊ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢊ ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
device and development-support tool nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
TMS320 DSP devices and support tools. Each military TMS320 DSP family member has one of three
prefixes: SMX, TMP, or SMJ. Texas Instruments recommends two of three possible prefix designators for
support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from
engineering prototypes (SMX/TMDX) through fully qualified production devices/tools (SMJ/TMDS).
Device development evolutionary flow:
SMX
TMP
SMJ
Preproduction device that is not necessarily representative of the final device’s electrical
specifications
Final silicon die that conforms to the device’s electrical specifications but has not completed
quality and reliability verification
Fully qualified production device
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal qualification
testing.
TMDS
Fully qualified development-support product
SMX and TMP devices and TMDX development-support tools are shipped with appropriate disclaimers
describing their limitations and intended uses. Experimental devices (SMX) may not be representative of a final
product and Texas Instruments reserves the right to change or discontinue these products without notice.
SMJ devices and TMDS development-support tools have been characterized fully, and the quality and reliability
of the device have been demonstrated fully. TI’s standard warranty applies.
Predictions show that preproduction or prototype devices (SMX or TMP) have a greater failure rate than the
standard production devices. Texas Instruments recommends that these devices not be used in any production
system because their expected end-use failure rate still is undefined. Only qualified production devices are to
be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, GAD), the temperature range (for example, blank is the default commercial temperature range),
and the device speed range in megahertz (for example, -6E3 is 600-MHz CPU, 133-MHz EMIFA). Figure 4
provides a legend for reading the complete device name for any SMJ320C64x DSP generation member.
TMS320 is a trademark of Texas Instruments.
63
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ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
device and development-support tool nomenclature (continued)
Table 30. SMJ320C6414/C6415/C6416 Device Part Numbers (P/Ns) and Ordering Information
OPERATING CASE
TEMPERATURE
RANGE
DEVICE ORDERABLE
P/N
DEVICE SPEED, EMIF SPEED,
SILICON REVISION
CV
DV
DD
DD
(CORE VOLTAGE) (I/O VOLTAGE)
C6414
600 MHz/4800 MIPS, 133-MHz EMIFA,
Silicon Rev. 1.1
†
SMJ320C6414DGADW60
1.4 V
1.4 V
3.3 V
3.3 V
−55ꢃ C to 115ꢃ C
−55ꢃ C to 115ꢃ C
600 MHz/4800 MIPS, 133-MHz EMIFA,
Silicon Rev. 1.1
†
SM320C6414DGADW60
C6415
600 MHz/4800 MIPS, 133-MHz EMIFA,
Silicon Rev. 1.1
SMJ320C6415DGADW60
1.4 V
1.4 V
3.3 V
3.3 V
−55ꢃ C to 115ꢃ C
−55ꢃ C to 115ꢃ C
600 MHz/4800 MIPS, 133-MHz EMIFA,
Silicon Rev. 1.1
SM320C6415DGADW60
C6416
600 MHz/4800 MIPS, 133-MHz EMIFA,
Silicon Rev. 1.1
†
SMJ320C6416DGADW60
1.4 V
1.4 V
3.3 V
3.3 V
−55ꢃ C to 115ꢃ C
−55ꢃ C to 115ꢃ C
600 MHz/4800 MIPS, 133-MHz EMIFA,
Silicon Rev. 1.1
†
SM320C6416DGADW60
†
Product Preview
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ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
device and development-support tool nomenclature (continued)
(
)
SMJ 32
C
6415C GAD
6E3
PREFIX
DEVICE SPEED RANGE
300
TMX= Experimental device
TMP= Prototype device
TMS= Qualified device
SMX= Preproduction device, MIL
SMJ = MIL-PRF-38535, QML
SM = Commercial processing
5E0 (500-MHz CPU, 100-MHz EMIF)
6E3 (600-MHz CPU, 133-MHz EMIFA)
7E3 (720-MHz CPU, 133-MHz EMIFA)
60 (600-MHz CPU, 133-MHz EMIFA) military
†
TEMPERATURE RANGE (DEFAULT: 0°C TO 90°C)
Blank = 0°C to 90°C, commercial temperature
‡
A
=
=
−40°C to 105°C, extended temperature
−55°C to 115°C, mil temp
DEVICE FAMILY
3 or 32 or 320
W
=
TMS320ꢄ DSP family
§
PACKAGE TYPE
GLZ = 532-pin plastic BGA
GAD = 570-pin ceramic micro pin PGA
TECHNOLOGY
C = CMOS
¶
DEVICE
C64x DSP:
6411
6414D
6414C
6415C
6416C
6415D
6416D
†
‡
See the Recommended Operating Conditions section of this data sheet for more details.
The extended temperature “A version” devices may have different operating conditions than the commercial temperature devices.
See the Recommended Operating Conditions section of this data sheet for more details.
BGA= Ball Grid Array.
§
¶
PGA= Pin Grid Array.
For the actual device part numbers (P/Ns) and ordering information, see Table 30 of this data sheet.
Figure 4. SMJ320C64x DSP Device Nomenclature (Including the C6414, C6415, and C6416 Devices)
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ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
documentation support
Extensive documentation supports all TMS320 DSP family generations of devices from product
announcement through applications development. The types of documentation available include: data sheets,
such as this document, with design specifications; complete user’s reference guides for all devices and tools;
technical briefs; development-support tools; on-line help; and hardware and software applications. The
following is a brief, descriptive list of support documentation specific to the C6000 DSP devices:
The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the
C6000 DSP CPU (core) architecture, instruction set, pipeline, and associated interrupts.
The TMS320C6000 DSP Peripherals Overview Reference Guide (literature number SPRU190) provides an
overview and briefly describes the functionality of the peripherals available on the C6000 DSP platform of
devices. This document also includes a table listing the peripherals available on the C6000 devices along with
literature numbers and hyperlinks to the associated peripheral documents.
The TMS320C64x Technical Overview (literature number SPRU395) gives an introduction to the C64x digital
signal processor, and discusses the application areas that are enhanced by the C64x DSP VelociTI.2 VLIW
architecture.
The TMS320C6414, TMS320C6415, and TMS320C6416 Digital Signal Processors Silicon Errata (literature
number SPRZ011) describes the known exceptions to the functional specifications for the SMJ320C6414,
SMJ320C6415, and SMJ320C6416 devices.
The TMS320C6414/15/16 Power Consumption Summary application report (literature number SPRA811)
discusses the power consumption for user applications with the SMJ320C6414, SMJ320C6415, and
SMJ320C6416 DSP devices.
The Using IBIS Models for Timing Analysis application report (literature number SPRA839) describes how to
properly use IBIS models to attain accurate timing analysis for a given system.
The tools support documentation is electronically available within the Code Composer Studio Integrated
Development Environment (IDE). For a complete listing of C6000 DSP latest documentation, visit the Texas
Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL).
See the Worldwide Web URL for the How To Begin Development Today With the TMS320C6414,
TMS320C6415, and TMS320C6416 DSPs application report (literature number SPRA718), which describes
in more details the compatibility and similarities/differences among the C6414, C6415, C6416, and C6211
devices.
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ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
clock PLL
Most of the internal C64x DSP clocks are generated from a single source through the CLKIN pin. This source
clock either drives the PLL, which multiplies the source clock frequency to generate the internal CPU clock, or
bypasses the PLL to become the internal CPU clock.
To use the PLL to generate the CPU clock, the external PLL filter circuit must be properly designed. Figure 5
shows the external PLL circuitry for either x1 (PLL bypass) or other PLL multiply modes.
To minimize the clock jitter, a single clean power supply should power both the C64x DSP device and the
external clock oscillator circuit. The minimum CLKIN rise and fall times should also be observed. For the input
clock timing requirements, see the input and output clocks electrical section.
Rise/fall times, duty cycles (high/low pulse durations), and the load capacitance of the external clock source
must meet the DSP requirements in this data sheet (see the electrical characteristics over recommended
ranges of supply voltage and operating case temperature table and the input and output clocks electrical
section). Table 31 lists some examples of compatible CLKIN external clock sources:
Table 31. Compatible CLKIN External Clock Sources
COMPATIBLE PARTS FOR
EXTERNAL CLOCK SOURCES (CLKIN)
PART NUMBER
MANUFACTURER
JITO-2
STA series, ST4100 series
SG-636
Fox Electronix
SaRonix Corporation
Epson America
Oscillators
PLL
342
Corning Frequency Control
Integrated Circuit Systems
ICS525-02
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ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
clock PLL (continued)
3.3 V
CPU Clock
C1
C2
EMI
filter
/2
/8
/4
/6
Peripheral Bus
10 µF 0.1 µF
Timer Internal Clock
PLLV
CLKOUT4,
McBSP Internal Clock
CLKMODE0
CLKMODE1
CLKOUT6
PLLMULT
PLL
x6, x12
ECLKIN_SEL (DEVCFG.[17,16]
and DEVCFG.[15,14])
00 01 10
CLKIN
PLLCLK
1
0
/4
/2
ECLKIN
EK2RATE
(GBLCTL.[19,18])
EMIF
00 01 10
Internal to C64x
(For the PLL Options, CLKMODE Pins Setup, and
PLL Clock Frequency Ranges, see Table 32.)
ECLKOUT1 ECLKOUT2
NOTES: A. Place all PLL external components (C1, C2, and the EMI Filter) as close to the C6000 DSP device as possible. For the best
performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or
components other than the ones shown.
B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (C1, C2, and the EMI
Filter).
C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DV
D. EMI filter manufacturer TDK part number ACF451832-333, -223, -153, -103. Panasonic part number EXCCET103U.
.
DD
Figure 5. External PLL Circuitry for Either PLL Multiply Modes or x1 (Bypass) Mode
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ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
clock PLL (continued)
†‡
Table 32. SMJ320C64x PLL Multiply Factor Options, Clock Frequency Ranges, and Typical Lock Time
GAD PACKAGE − Micro Pin PGA
CLKMODE
CLKMODE1 CLKMODE0 (PLL MULTIPLY
FACTORS)
CLKIN
RANGE
(MHz)
CPU CLOCK
FREQUENCY
RANGE (MHz)
TYPICAL
CLKOUT4
RANGE (MHz)
CLKOUT6
RANGE (MHz)
LOCK TIME
§
(µs)
0
0
1
1
0
1
0
1
Bypass (x1)
x6
30−75
30−75
30−60
−
30−75
180−450
360−720
−
7.5−18.8
45−112.5
90−180
−
5−12.5
30−75
60−120
−
N/A
75
−
x12
Reserved
†
‡
These clock frequency range values are applicable to a C64x−60 speed device..
Use external pullup resistors on the CLKMODE pins (CLKMODE1 and CLKMODE0) to set the C64x device to one of the valid PLL multiply clock
modes (x6 or x12). With internal pulldown resistors on the CLKMODE pins (CLKMODE1, CLKMODE0), the default clock mode is x1 (bypass).
Under some operating conditions, the maximum PLL lock time may vary by as much as 150% from the specified typical value. For example, if
the typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs.
§
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ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
general-purpose input/output (GPIO)
To use the GP[15:0] software-configurable GPIO pins, the GPxEN bits in the GP Enable (GPEN) Register and
the GPxDIR bits in the GP Direction (GPDIR) Register must be properly configured.
GPxEN =
GPxDIR =
GPxDIR =
1
0
1
GP[x] pin is enabled
GP[x] pin is an input
GP[x] pin is an output
where “x” represents one of the 15 through 0 GPIO pins
Figure 6 shows the GPIO enable bits in the GPEN register for the C6414/C6415/C6416 device. To use any of
the GPx pins as general-purpose input/output functions, the corresponding GPxEN bit must be set to “1”
(enabled). Default values are device-specific, so refer to Figure 6 for the C6414/15/16 default configuration.
31
24 23
Reserved
R-0
16
15
GP15 GP14 GP13 GP12 GP11 GP10
EN EN EN EN EN EN
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GP9
EN
GP8
EN
GP7
EN
GP6
EN
GP5
EN
GP4
EN
GP3
EN
GP2
EN
GP1
EN
GP0
EN
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-1
Legend: R/W = Readable/Writable; -n = value after reset, -x = undefined value after reset
Figure 6. GPIO Enable Register (GPEN) [Hex Address: 01B0 0000]
Figure 7 shows the GPIO direction bits in the GPDIR register. This register determines if a given GPIO pin is
an input or an output providing the corresponding GPxEN bit is enabled (set to “1”) in the GPEN register. By
default, all the GPIO pins are configured as input pins.
31
24 23
Reserved
R-0
16
15
14
13
12
11
9
8
6
4
3
1
0
10
7
5
2
GP15 GP14 GP13 GP12 GP11 GP10
DIR DIR DIR DIR DIR DIR
GP9
DIR
GP8
DIR
GP7
DIR
GP6
DIR
GP5
DIR
GP4
DIR
GP3
DIR
GP2
DIR
GP1
DIR
GP0
DIR
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
Legend: R/W = Readable/Writable; -n = value after reset, -x = undefined value after reset
Figure 7. GPIO Direction Register (GPDIR) [Hex Address: 01B0 0004]
For more detailed information on general-purpose inputs/outputs (GPIOs), see the TMS320C6000 DSP
General-Purpose Input/Output (GPIO) Reference Guide (literature number SPRU584).
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ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
power-down mode logic
Figure 8 shows the power-down mode logic on the C6414/C6415/C6416.
CLKOUT4
CLKOUT6
Internal Clock Tree
Clock
Distribution
and Dividers
PD1
PD2
IFR
Power-
Clock
PLL
Internal
Peripherals
IER
Down
Logic
CSR
PWRD
CPU
PD3
SMJ320C6414/15/16
CLKIN
RESET
†
External input clocks, with the exception of CLKIN, are not gated by the power-down mode logic.
†
Figure 8. Power-Down Mode Logic
triggering, wake-up, and effects
The power-down modes and their wake-up methods are programmed by setting the PWRD field (bits 15−10)
of the control status register (CSR). The PWRD field of the CSR is shown in Figure 9 and described in Table 33.
When writing to the CSR, all bits of the PWRD field should be set at the same time. Logic 0 should be used when
writing to the reserved bit (bit 15) of the PWRD field. The CSR is discussed in detail in the TMS320C6000 CPU
and Instruction Set Reference Guide (literature number SPRU189).
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ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
31
16
8
15
14
13
Enabled
12
PD3
R/W-0
11
10
9
Enable or
Non-Enabled
Interrupt Wake
Reserved
R/W-0
PD2
PD1
Interrupt Wake
R/W-0
R/W-0
R/W-0
R/W-0
7
0
Legend: R/W−x = Read/write reset value
NOTE: The shadowed bits are not part of the power-down logic discussion and therefore are not covered here. For information on these other
bit fields in the CSR register, see the TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189).
Figure 9. PWRD Field of the CSR Register
Power-down mode PD1 takes effect eight to nine clock cycles after the instruction that sets the PWRD bits in the
CSR. If PD1 mode is terminated by a non-enabled interrupt, the program execution returns to the instruction where
PD1 took effect. If PD1 mode is terminated by an enabled interrupt, the interrupt service routine will be executed
first, then the program execution returns to the instruction where PD1 took effect.
PD2 and PD3 modes can only be aborted by device reset. Table 33 summarizes all the power-down modes.
Table 33. Characteristics of the Power-Down Modes
PRWD FIELD
(BITS 15−10)
POWER-DOWN
MODE
WAKE-UP METHOD
—
EFFECT ON CHIP’S OPERATION
000000
001001
No power-down
PD1
—
CPU halted (except for the interrupt logic)
Wake by an enabled interrupt
Power-down mode blocks the internal clock inputs at the
boundary of the CPU, preventing most of the CPU’s logic from
switching. During PD1, EDMA transactions can proceed
between peripherals and internal memory.
Wake by an enabled or
non-enabled interrupt
010001
011010
PD1
Output clock from PLL is halted, stopping the internal clock
structure from switching and resulting in the entire chip being
halted. All register and internal RAM contents are preserved. All
functional I/O “freeze” in the last state when the PLL clock is
turned off.
†
PD2
Wake by a device reset
Input clock to the PLL stops generating clocks. All register and
internal RAM contents are preserved. All functional I/O “freeze” in
the last state when the PLL clock is turned off. Following reset, the
PLL needs time to re-lock, just as it does following power-up.
Wake-up from PD3 takes longer than wake-up from PD2 because
the PLL needs to be re-locked, just as it does following power-up.
†
PD3
011100
Wake by a device reset
All others
Reserved
—
—
†
When entering PD2 and PD3, all functional I/O remains in the previous state. However, for peripherals which are asynchronous in nature or
peripherals with an external clock source, output signals may transition in response to stimulus on the inputs. Under these conditions,
peripherals will not operate according to specifications.
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ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
C64x power-down mode with an emulator
If user power-down modes are programmed, and an emulator is attached, the modes will be masked to allow
the emulator access to the system. This condition prevails until the emulator is reset or the cable is removed
from the header. If power measurements are to be performed when in a power-down mode, the emulator cable
should be removed.
When the DSP is in power-down mode PD2 or PD3, emulation logic will force any emulation execution
command (such as Step or Run) to spin in IDLE. For this reason, PC writes (such as loading code) will fail. A DSP
reset will be required to get the DSP out of PD2/PD3.
power-supply sequencing
TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However,
systems should be designed to ensure that neither supply is powered up for extended periods of time
(>1 second) if the other supply is below the proper operating voltage.
power-supply design considerations
A dual-power supply with simultaneous sequencing can be used to eliminate the delay between core and I/O
power up. A Schottky diode can also be used to tie the core rail to the I/O rail (see Figure 10).
I/O Supply
DV
CV
DD
DD
Schottky
Diode
C6000
DSP
Core Supply
V
SS
GND
Figure 10. Schottky Diode Diagram
Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize
inductance and resistance in the power delivery path. Additionally, when designing for high-performance
applications utilizing the C6000 platform of DSPs, the PC board should include separate power planes for
core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors.
power-supply decoupling
In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as possible
close to the DSP. Assuming 0603 caps, the user should be able to fit a total of 60 caps, 30 for the core supply
and 30 for the I/O supply. These caps need to be close to the DSP, no more than 1.25 cm maximum distance
to be effective. Physically smaller caps are better, such as 0402, but need to be evaluated from a
yield/manufacturing point-of-view. Parasitic inductance limits the effectiveness of the decoupling capacitors,
therefore physically smaller capacitors should be used while maintaining the largest available capacitance
value. As with the selection of any component, verification of capacitor availability over the product’s production
lifetime should be considered.
73
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SGUS050A − JANUARY 2004 − REVISED MARCH 2004
IEEE 1149.1 JTAG compatibility statement
The SMJ320C6414/15/16 DSP requires that both TRST and RESET be asserted upon power up to be properly
initialized. While RESET initializes the DSP core, TRST initializes the DSP’s emulation logic. Both resets are
required for proper operation.
While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for the
DSP to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG port interface
and DSP’s emulation logic in the reset state.
TRST only needs to be released when it is necessary to use a JTAG controller to debug the DSP or exercise
the DSP’s boundary scan functionality.
For maximum reliability, the SMJ320C6414/15/16 DSP includes an internal pulldown (IPD) on the TRST pin to
ensure that TRST will always be asserted upon power up and the DSP’s internal emulation logic will always be
properly initialized.
JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG controllers
may not drive TRST high but expect the use of a pullup resistor on TRST.
When using this type of JTAG controller, assert TRST to initialize the DSP after power up and externally drive
TRST high before attempting any emulation or boundary scan operations. Following the release of RESET, the
low-to-high transition of TRST must be “seen” to latch the state of EMU1 and EMU0. The EMU[1:0] pins
configure the device for either Boundary Scan mode or Emulation mode. For more detailed information, see
the terminal functions section of this data sheet.
EMIF device speed
The rated EMIF speed, referring to both EMIFA and EMIFB, of these devices only applies to the SDRAM
interface when in a system that meets the following requirements:
−
−
−
−
−
1 chip-enable (CE) space (maximum of 2 chips) of SDRAM connected to EMIF
up to 1 CE space of buffers connected to EMIF
EMIF trace lengths between 1 and 3 inches
166-MHz SDRAM for 133-MHz operation (applies only to EMIFA)
143-MHz SDRAM for 100-MHz operation
Other configurations may be possible, but timing analysis must be done to verify all AC timings are met.
Verification of AC timings is mandatory when using configurations other than those specified above. TI
recommends utilizing I/O buffer information specification (IBIS) to analyze all AC timings.
To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS Models
for Timing Analysis application report (literature number SPRA839).
To maintain signal integrity, serial termination resistors should be inserted into all EMIF output signal lines (see
the Terminal Functions table for the EMIF output signals).
74
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SGUS050A − JANUARY 2004 − REVISED MARCH 2004
bootmode
The C6414/15/16 device resets using the active-low signal RESET. While RESET is low, the device is held in
reset and is initialized to the prescribed reset state. Refer to reset timing for reset timing characteristics and
states of device pins during reset. The release of RESET starts the processor running with the prescribed device
configuration and boot mode.
The C6414/C6415/C6416 has three types of boot modes:
ꢀ
Host boot
If host boot is selected, upon release of RESET, the CPU is internally “stalled” while the remainder of the
device is released. During this period, an external host can initialize the CPU’s memory space as necessary
through the host interface, including internal configuration registers, such as those that control the EMIF or
other peripherals. For the C6414 device, the HPI peripheral is used for host boot. For the C6415/C6416
device, the HPI peripheral is used for host boot if PCI_EN = 0, and the PCI peripheral is used for host boot if
PCI_EN = 1. Once the host is finished with all necessary initialization, it must set the DSPINT bit in the HPIC
register to complete the boot process. This transition causes the boot configuration logic to bring the CPU
out of the “stalled” state. The CPU then begins execution from address 0. The DSPINT condition is not
latched by the CPU, because it occurs while the CPU is still internally “stalled”. Also, DSPINT brings the CPU
out of the “stalled” state only if the host boot process is selected. All memory may be written to and read by
the host. This allows for the host to verify what it sends to the DSP if required. After the CPU is out of the
“stalled” state, the CPU needs to clear the DSPINT, otherwise, no more DSPINTs can be received.
ꢀ
ꢀ
EMIF boot (using default ROM timings)
Upon the release of RESET, the 1K-Byte ROM code located in the beginning of CE1 is copied to address 0
by the EDMA using the default ROM timings, while the CPU is internally “stalled”. The data should be stored
in the endian format that the system is using. In this case, the EMIF automatically assembles consecutive
8-bit bytes to form the 32-bit instruction words to be copied. The transfer is automatically done by the EDMA
as a single-frame block transfer from the ROM to address 0. After completion of the block transfer, the CPU
is released from the “stalled” state and starts running from address 0.
No boot
With no boot, the CPU begins direct execution from the memory located at address 0. Note: operation is
undefined if invalid code is located at address 0.
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ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
†
absolute maximum ratings over operating case temperature range (unless otherwise noted)
Supply voltage ranges: CV
DV
Input voltage ranges: (except PCI), V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V
(PCI), V [C6415 and C6416 only] . . . . . . . . . . . . . . . . . . . . . −0.5 V to DV
Output voltage ranges: (except PCI), V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 1.8 V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V
DD
DD
I
+ 0.5 V
IP
DD
O
(PCI), V
[C6415 and C6416 only] . . . . . . . . . . . . . . . . . . . . −0.5 V to DV
+ 0.5 V
OP
DD
Operating case temperature ranges, T :
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55ꢃC to 115ꢃC
C
Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65ꢃC to 150ꢃC
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to V
SS
.
recommended operating conditions
MIN
1.36
3.14
0
NOM
1.4
3.3
0
MAX
1.44
3.46
0
UNIT
V
‡
CV
DV
Supply voltage, Core
Supply voltage, I/O
Supply ground
DD
DD
V
V
V
V
V
V
V
V
V
SS
High-level input voltage (except PCI)
2
V
IH
Low-level input voltage (except PCI)
0.8
V
IL
Input voltage (PCI) [C6415 and C6416 only]
High-level input voltage (PCI) [C6415 and C6416 only]
Low-level input voltage (PCI) [C6415 and C6416 only]
Maximum voltage during overshoot/undershoot
−0.5
DV
DV
+ 0.5
V
IP
DD
DD
0.5DV
DD
+ 0.5
V
IHP
ILP
OS
−0.5
0.3DV
DD
V
§
−1.0
§
4.3
V
Operating case tem-
W version
T
C
–55
115
ꢃ
C
perature
‡
Future variants of the C641x DSPs may operate at voltages ranging from 0.9 V to 1.4 V to provide a range of system power/performance options.
TI highly recommends that users design-in a supply that can handle multiple voltages within this range (i.e., 1.2 V, 1.25 V, 1.3 V, 1.35 V, 1.4 V
with 3% tolerances) by implementing simple board changes such as reference resistor values or input pin configuration modifications. Examples
of such supplies include the PT4660, PT5500, PT5520, PT6440, and PT6930 series from Power Trends, a subsidiary of Texas Instruments. Not
incorporating a flexible supply may limit the system’s ability to easily adapt to future versions of C641x devices.
§
The absolute maximum ratings should not be exceeded for more than 30% of the cycle period.
Life vs. Temperature at 600 MHz
12
10
10
9
8
6
4
2
0
8
7
6
Life (yrs)
5
4
3
2
1
100
110
120
130
140
150
Junction Temp (C)
Figure 11. Impact of Elevated Temperature on Device Life
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ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
electrical characteristics over recommended ranges of supply voltage and operating case
temperature (unless otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
V
V
V
High-level output voltage (except PCI)
DV
= MIN, = MAX
I
OH
2.4
V
OH
DD
High-level output voltage (PCI)
[C6415/C6416 only]
¶
I
= −0.5 mA,
DV
DD
= 3.3 V
0.9DV
DD
V
V
V
OHP
OL
OHP
Low-level output voltage (except PCI)
DV
= MIN,
I
= MAX
0.4
DD
OL
Low-level output voltage (PCI)
[C6415/C6416 only]
¶
I
= 1.5 mA,
DV
= 3.3 V
DD
0.1DV
DD
OLP
OLP
V = V
SS
to DV
to DV
no opposing internal
opposing internal
opposing internal
I
DD
DD
DD
10
150
−50
uA
uA
uA
resistor
V = V
pullup resistor
I
SS
50
100
I
Input current (except PCI)
Input leakage current (PCI)
I
‡
V = V to DV
I
SS
−150
−100
‡
pulldown resistor
I
I
0 < V < DV
IP DD
= 3.3 V
10
−16
−8
uA
mA
mA
IP
§
[C6415/C6416 only]
EMIF, CLKOUT4, CLKOUT6, EMUx
Timer, UTOPIA, TDO, GPIO (Excluding
GP[15:9, 2, 1]), McBSP
High-level output current
OH
¶
PCI/HPI
−0.5
mA
mA
EMIF, CLKOUT4, CLKOUT6, EMUx
16
8
Timer, UTOPIA, TDO, GPIO (Excluding
GP[15:9, 2, 1]), McBSP
mA
I
Low-level output current
Off-state output current
OL
¶
PCI/HPI
1.5
mA
uA
mA
mA
pF
I
I
I
V = DV
O DD
or 0 V
10
OZ
#
Core supply current
CV
DV
= 1.4 V, CPU clock = 600 MHz
= 3.3 V, CPU clock = 600 MHz
750
125
CDD
DDD
DD
DD
#
I/O supply current
C
C
Input capacitance
12
12
i
Output capacitance
pF
o
†
‡
§
¶
For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table.
Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor.
PCI input leakage currents include Hi-Z output leakage for all bidirectional buffers with 3-state outputs.
These rated numbers are from the PCI specification version 2.3. The DC specification and AC specification are defined in Tables 4-3 and 4-4,
respectively.
#
Measured with average activity (50% high/50% low power). The actual current draw is highly application-dependent. For more details on core
and I/O activity, refer to the TMS320C6414/15/16 Power Consumption Summary application report (literature number SPRA811).
recommended clock and control signal transition behavior
All clocks and control signals must transition between V and V (or between V and V ) in a monotonic
IH
IL
IL
IH
manner.
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SGUS050A − JANUARY 2004 − REVISED MARCH 2004
PARAMETER MEASUREMENT INFORMATION
Tester Pin Electronics
Data Sheet Timing Reference Point
42 W
3.5 nH
Output
Under
Test
Transmission Line
Z0 = 50 W
(see note)
Device Pin
(see note)
4.0 pF
1.85 pF
NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects
must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect.
The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from
the data sheet timings.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
Figure 12. Test Load Circuit for AC Timing Measurements
The tester load circuit is for characterization and measurement of AC timing signals. This load does not indicate
the maximum load the device is capable of driving.
signal transition levels
All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels.
V
ref
= 1.5 V
Figure 13. Input and Output Voltage Reference Levels for AC Timing Measurements
All rise and fall transition timing parameters are referenced to V MAX and V MIN for input clocks, V MAX
IL
IH
OL
OHP
and V
PCI output clocks.
MIN for output clocks, V
MAX and V
MIN for PCI input clocks, and V
MAX and V
MIN for
OH
ILP
IHP
OLP
V
ref
= V MIN (or V
IH OH
MIN or
MIN)
V
MIN or V
IHP
OHP
V
ref
= V MAX (or V
IL OL
MAX or
MAX)
V
MAX or V
ILP
OLP
Figure 14. Rise and Fall Transition Time Voltage Reference Levels
signal transition rates
All timings are tested with an input edge rate of 4 Volts per nanosecond (4 V/ns).
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SGUS050A − JANUARY 2004 − REVISED MARCH 2004
PARAMETER MEASUREMENT INFORMATION (CONTINUED)
timing parameters and board routing analysis
The timing parameter values specified in this data sheet do not include delays by board routings. As a good
board design practice, such delays must always be taken into account. Timing values may be adjusted by
increasing/decreasing such delays. TI recommends utilizing the available I/O buffer information specification
(IBIS) models to analyze the timing characteristics correctly. If needed, external logic hardware such as buffers
may be used to compensate any timing differences.
For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external device and
from the external device to the DSP. This round-trip delay tends to negatively impact the input setup time margin,
but also tends to improve the input hold time margins (see Table 34 and Figure 15).
Figure 15 represents a general transfer between the DSP and an external device. The figure also represents
board route delays and how they are perceived by the DSP and the external device.
Table 34. Board-Level Timings Example (see Figure 15)
NO.
1
DESCRIPTION
Clock route delay
2
Minimum DSP hold time
3
Minimum DSP setup time
External device hold time requirement
External device setup time requirement
Control signal route delay
External device hold time
4
5
6
7
8
External device access time
DSP hold time requirement
DSP setup time requirement
Data route delay
9
10
11
ECLKOUTx
(Output from DSP)
1
ECLKOUTx
(Input to External Device)
2
3
†
Control Signals
(Output from DSP)
4
5
6
Control Signals
(Input to External Device)
7
8
‡
Data Signals
(Output from External Device)
9
10
11
‡
Data Signals
(Input to DSP)
† Control signals include data for Writes.
‡ Data signals are generated during Reads from an external device.
Figure 15. Board-Level Input/Output Timings
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SGUS050A − JANUARY 2004 − REVISED MARCH 2004
INPUT AND OUTPUT CLOCKS
†‡§
timing requirements for CLKIN
(see Figure 16)
PLL MODE x12
PLL MODE x6
x1 (BYPASS)
NO.
UNIT
MIN
20
MAX
MIN
13.3
MAX
MIN
13.3*
MAX
1
2
3
4
t
t
t
t
Cycle time, CLKIN
33.3
33.3
33.3
ns
ns
ns
ns
c(CLKIN)
w(CLKINH)
w(CLKINL)
t(CLKIN)
Pulse duration, CLKIN high
Pulse duration, CLKIN low
Transition time, CLKIN
0.4C*
0.4C*
0.4C*
0.4C*
0.45C*
0.45C*
5*
5*
1*
*This parameter is not production tested.
†
‡
§
The reference points for the rise and fall transitions are measured at V MAX and V MIN.
For more details on the PLL multiplier factors (x6, x12), see the Clock PLL section of this data sheet.
C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns.
IL
IH
1
4
2
CLKIN
3
4
Figure 16. CLKIN Timing
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SGUS050A − JANUARY 2004 − REVISED MARCH 2004
INPUT AND OUTPUT CLOCKS (CONTINUED)
†‡§
switching characteristics over recommended operating conditions for CLKOUT4
(see Figure 17)
CLKMODE = x1, x6, x12
MIN MAX
175*
NO.
PARAMETER
UNIT
1
2
3
4
t
t
t
t
Period jitter, CLKOUT4
0*
ps
ns
ns
ns
J(CKO4)
w(CKO4H)
w(CKO4L)
t(CKO4)
Pulse duration, CLKOUT4 high
Pulse duration, CLKOUT4 low
Transition time, CLKOUT4
2P − 0.7*
2P − 0.7*
2P + 0.7*
2P + 0.7*
1*
*This parameter is not production tested.
†
‡
§
The reference points for the rise and fall transitions are measured at V
PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns.
P = 1/CPU clock frequency in nanoseconds (ns)
MAX and V MIN.
OH
OL
4
Ideal Clock Period
2
CLKOUT4
1
3
4
Figure 17. CLKOUT4 Timing
†‡§
switching characteristics over recommended operating conditions for CLKOUT6
(see Figure 18)
CLKMODE = x1, x6, x12
MIN MAX
175*
NO.
PARAMETER
UNIT
1
2
3
4
t
t
t
t
Period jitter, CLKOUT6
0*
ps
ns
ns
ns
J(CKO6)
w(CKO6H)
w(CKO6L)
t(CKO6)
Pulse duration, CLKOUT6 high
Pulse duration, CLKOUT6 low
Transition time, CLKOUT6
3P − 0.7*
3P − 0.7*
3P + 0.7*
3P + 0.7*
1*
*This parameter is not production tested.
†
‡
§
The reference points for the rise and fall transitions are measured at V
PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns.
P = 1/CPU clock frequency in nanoseconds (ns)
MAX and V MIN.
OH
OL
4
Ideal Clock Period
2
CLKOUT6
3
1
4
Figure 18. CLKOUT6 Timing
81
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ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
INPUT AND OUTPUT CLOCKS (CONTINUED)
†‡§
timing requirements for ECLKIN for EMIFA and EMIFB
(see Figure 19)
NO.
1
MIN
¶*
MAX
UNIT
ns
t
t
t
t
Cycle time, ECLKIN
6
16P*
c(EKI)
2
Pulse duration, ECLKIN high
Pulse duration, ECLKIN low
Transition time, ECLKIN
2.7*
2.7*
ns
w(EKIH)
w(EKIL)
t(EKI)
3
ns
4
2*
ns
*This parameter is not production tested.
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
The reference points for the rise and fall transitions are measured at V MAX and V MIN.
IL IH
These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are
prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted.
Minimum ECLKIN times are based on internal logic speed; the maximum useable speed of the EMIF may be lower due to AC timing requirements.
On the 7E3 and 6E3 devices, 133-MHz operation is achievable if the requirements of the EMIF Device Speed section are met. On the 5E0 devices,
100-MHz operation is achievable if the requirements of the EMIF Device Speed section are met.
¶
1
4
2
ECLKIN
3
4
Figure 19. ECLKIN Timing for EMIFA and EMIFB
switching characteristics over recommended operating conditions for ECLKOUT1 for EMIFA and
§#||ꢁ
EMIFB modules
(see Figure 20)
NO.
PARAMETER
MIN
MAX
UNIT
ps
ꢂ
1
2
3
4
5
6
t
t
t
t
t
t
Period jitter, ECLKOUT1
0*
175 *
J(EKO1)
Pulse duration, ECLKOUT1 high
Pulse duration, ECLKOUT1 low
Transition time, ECLKOUT1
EH − 0.7* EH + 0.7*
EL − 0.7* EL + 0.7*
1*
ns
w(EKO1H)
w(EKO1L)
ns
ns
t(EKO1)
Delay time, ECLKIN high to ECLKOUT1 high
Delay time, ECLKIN low to ECLKOUT1 low
1*
1*
8*
8*
ns
d(EKIH-EKO1H)
d(EKIL-EKO1L)
ns
*This parameter is not production tested.
§
These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are
prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted.
#
||
The reference points for the rise and fall transitions are measured at V
MAX and V
MIN.
E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB.
OL
OH
ꢁ
E
H
i
s
t
h
e
h
i
g
h
p
e
r
i
o
d
o
f
E
(
E
M
I
F
i
n
p
u
t
c
l
o
c
k
p
e
r
i
o
d
)
i
n
n
s
a
n
d
E
L
i
s
t
h
e
l
o
w
p
e
r
i
o
d
o
f
E
(
E
M
I
F
i
n
p
u
t
c
l
o
c
k
p
e
r
i
o
d
)
i
n
n
s
f
o
r
E
M
I
F
A
o
r
E
M
I
F
B
.
ꢂ This period jitter specification was measured with CPU/4 or CPU/6 as the source of the EMIF input clock.
82
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ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢊ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢊ ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
INPUT AND OUTPUT CLOCKS (CONTINUED)
ECLKIN
Ideal Clock Period
6
3
4
4
5
2
ECLKOUT1
1
Figure 20. ECLKOUT1 Timing for EMIFA and EMIFB Modules
switching characteristics over recommended operating conditions for ECLKOUT2 for the EMIFA
†‡§
and EMIFB modules
(see Figure 21)
NO.
PARAMETER
Period jitter, ECLKOUT2
MIN
0*
MAX
UNIT
ps
¶
175 *
1
2
3
4
5
6
t
t
t
t
J(EKO2)
w(EKO2H)
w(EKO2L)
t(EKO2)
Pulse duration, ECLKOUT2 high
0.5NE − 0.7* 0.5NE + 0.7*
0.5NE − 0.7* 0.5NE + 0.7*
1*
ns
Pulse duration, ECLKOUT2 low
ns
Transition time, ECLKOUT2
ns
t
Delay time, ECLKIN high to ECLKOUT2 high
Delay time, ECLKIN high to ECLKOUT2 low
1*
1*
8*
8*
ns
d(EKIH-EKO2H)
t
ns
d(EKIH-EKO2L)
*This parameter is not production tested.
†
‡
The reference points for the rise and fall transitions are measured at V
MAX and V MIN.
OH
OL
These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are
prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted.
E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB.
N = the EMIF input clock divider; N = 1, 2, or 4.
§
¶
This period jitter specification was measured with CPU/4 or CPU/6 as the source of the EMIF input clock.
5
6
ECLKIN
3
Ideal Clock Period
4
4
2
ECLKOUT2
1
Figure 21. ECLKOUT2 Timing for the EMIFA and EMIFB Modules
83
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ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢋ ꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢇ
ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
ASYNCHRONOUS MEMORY TIMING
†‡§
timing requirements for asynchronous memory cycles for EMIFA module
(see Figure 22 and Figure 23)
NO.
MIN
6.5
1
MAX
UNIT
ns
3
4
6
7
t
t
t
t
Setup time, EDx valid before ARE high
Hold time, EDx valid after ARE high
su(EDV-AREH)
ns
h(AREH-EDV)
Setup time, ARDY valid before ECLKOUTx high
Hold time, ARDY valid after ECLKOUTx high
3
ns
su(ARDY-EKO1H)
h(EKO1H-ARDY)
1
ns
†
To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. The ARDY signal is only recognized
two cycles before the end of the programmed strobe time and while ARDY is low, the strobe time is extended cycle-by-cycle. When ARDY is
recognized low, the end of the strobe time is two cycles after ARDY is recognized high. To use ARDY as an asynchronous input, the pulse width
of the ARDY signal should be wide enough (e.g., pulse width = 2E) to ensure setup and hold time is met.
‡
§
RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are
programmed via the EMIF CE space control registers.
These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a
“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the asynchronous
memory access signals are shown as generic (AOE, ARE, and AWE) instead of AAOE, AARE, and AAWE (for EMIFA) and BAOE, BARE, and
BAWE (for EMIFB)].
switching characteristics over recommended operating conditions for asynchronous memory
द#
cycles for EMIFA module
(see Figure 22 and Figure 23)
NO.
PARAMETER
MIN
RS * E − 2
RH * E − 1.9
1
MAX
UNIT
ns
1
2
t
t
t
t
t
t
Output setup time, select signals valid to ARE low
Output hold time, ARE high to select signals invalid
Delay time, ECLKOUTx high to ARE valid
osu(SELV-AREL)
oh(AREH-SELIV)
d(EKO1H-AREV)
osu(SELV-AWEL)
oh(AWEH-SELIV)
d(EKO1H-AWEV)
ns
5
7
ns
8
Output setup time, select signals valid to AWE low
Output hold time, AWE high to select signals invalid
Delay time, ECLKOUTx high to AWE valid
WS * E − 1.7
WH * E − 1.8
1.3
ns
9
ns
10
7.1
ns
‡
§
RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are
programmed via the EMIF CE space control registers.
These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a
“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the asynchronous
memory access signals are shown as generic (AOE, ARE, and AWE) instead of AAOE, AARE, and AAWE (for EMIFA) and BAOE, BARE, and
BAWE (for EMIFB)].
¶
#
E = ECLKOUT1 period in ns for EMIFA or EMIFB
Select signals for EMIFA include: ACEx, ABE[7:0], AEA[22:3], AAOE; and for EMIFA writes, include AED[63:0].
Select signals EMIFB include: BCEx, BBE[1:0], BEA[20:1], BAOE; and for EMIFB writes, include BED[15:0].
84
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ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢊ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢊ ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
ASYNCHRONOUS MEMORY TIMING (CONTINUED)
†‡§
timing requirements for asynchronous memory cycles for EMIFB module
(see Figure 22 and Figure 23)
NO.
MIN
6.2
1
MAX
UNIT
ns
3
4
6
7
t
t
t
t
Setup time, EDx valid before ARE high
Hold time, EDx valid after ARE high
su(EDV-AREH)
ns
h(AREH-EDV)
Setup time, ARDY valid before ECLKOUTx high
Hold time, ARDY valid after ECLKOUTx high
3
ns
su(ARDY-EKO1H)
h(EKO1H-ARDY)
1.2
ns
†
To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. The ARDY signal is only recognized
two cycles before the end of the programmed strobe time and while ARDY is low, the strobe time is extended cycle-by-cycle. When ARDY is
recognized low, the end of the strobe time is two cycles after ARDY is recognized high. To use ARDY as an asynchronous input, the pulse width
of the ARDY signal should be wide enough (e.g., pulse width = 2E) to ensure setup and hold time is met.
‡
§
RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are
programmed via the EMIF CE space control registers.
These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a
“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the asynchronous
memory access signals are shown as generic (AOE, ARE, and AWE) instead of AAOE, AARE, and AAWE (for EMIFA) and BAOE, BARE, and
BAWE (for EMIFB)].
switching characteristics over recommended operating conditions for asynchronous memory
द#
cycles for EMIFB module
(see Figure 22 and Figure 23)
NO.
PARAMETER
MIN
RS * E − 2
RH * E − 1.7
0.8
MAX
UNIT
ns
1
2
t
t
t
t
t
t
Output setup time, select signals valid to ARE low
Output hold time, ARE high to select signals invalid
Delay time, ECLKOUTx high to ARE valid
osu(SELV-AREL)
oh(AREH-SELIV)
d(EKO1H-AREV)
osu(SELV-AWEL)
oh(AWEH-SELIV)
d(EKO1H-AWEV)
ns
5
6.6
ns
8
Output setup time, select signals valid to AWE low
Output hold time, AWE high to select signals invalid
Delay time, ECLKOUTx high to AWE valid
WS * E − 1.9
WH * E − 1.7
0.9
ns
9
ns
10
6.7
ns
‡
§
RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are
programmed via the EMIF CE space control registers.
These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a
“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the asynchronous
memory access signals are shown as generic (AOE, ARE, and AWE) instead of AAOE, AARE, and AAWE (for EMIFA) and BAOE, BARE, and
BAWE (for EMIFB)].
E = ECLKOUT1 period in ns for EMIFA or EMIFB
Select signals for EMIFA include: ACEx, ABE[7:0], AEA[22:3], AAOE; and for EMIFA writes, include AED[63:0].
Select signals EMIFB include: BCEx, BBE[1:0], BEA[20:1], BAOE; and for EMIFB writes, include BED[15:0].
¶
#
85
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ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢋ ꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢇ
ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
ASYNCHRONOUS MEMORY TIMING (CONTINUED)
Setup = 2
Strobe = 3
Not Ready
Hold = 2
ECLKOUTx
CEx
2
2
1
1
1
BE
ABE[7:0] or BBE[1:0]
2
AEA[22:3] or BEA[20:1]
Address
3
4
2
AED[63:0] or BED[15:0]
1
5
Read Data
‡
AOE/SDRAS/SOE
5
‡
ARE/SDCAS/SADS/SRE
‡
AWE/SDWE/SWE
7
7
6
6
ARDY
†
‡
These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a
“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the asynchronous
memory access signals are shown as generic (AOE, ARE, and AWE) instead of AAOE, AARE, and AAWE (for EMIFA) and BAOE, BARE, and
BAWE (for EMIFB)].
AOE/SDRAS/SOE, ARE/SDCAS/SADS/SRE, and AWE/SDWE/SWE operate as AOE (identified under select signals), ARE, and AWE,
respectively, during asynchronous memory accesses.
†
Figure 22. Asynchronous Memory Read Timing for EMIFA and EMIFB
86
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢊ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢊ ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
ASYNCHRONOUS MEMORY TIMING (CONTINUED)
Setup = 2
Hold = 2
Strobe = 3
Not Ready
ECLKOUTx
CEx
9
9
8
8
8
8
BE
ABE[7:0] or BBE[1:0]
9
9
AEA[22:3] or BEA[20:1]
Address
Write Data
AED[63:0] or BED[15:0]
‡
AOE/SDRAS/SOE
‡
ARE/SDCAS/SADS/SRE
10
10
‡
AWE/SDWE/SWE
7
7
6
6
ARDY
†
‡
These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a
“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the asynchronous
memory access signals are shown as generic (AOE, ARE, and AWE) instead of AAOE, AARE, and AAWE (for EMIFA) and BAOE, BARE, and
BAWE (for EMIFB)].
AOE/SDRAS/SOE, ARE/SDCAS/SADS/SRE, and AWE/SDWE/SWE operate as AOE (identified under select signals), ARE, and AWE,
respectively, during asynchronous memory accesses.
†
Figure 23. Asynchronous Memory Write Timing for EMIFA and EMIFB
87
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ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢋ ꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢇ
ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
PROGRAMMABLE SYNCHRONOUS INTERFACE TIMING
†
timing requirements for programmable synchronous interface cycles for EMIFA module
(see Figure 24)
NO.
6
MIN
2
MAX
UNIT
ns
t
t
Setup time, read EDx valid before ECLKOUTx high
Hold time, read EDx valid after ECLKOUTx high
su(EDV-EKOxH)
7
1.5
ns
h(EKOxH-EDV)
†
These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a
“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the programmable
synchronous interface access signals are shown as generic (SADS/SRE, SOE, and SWE) instead of ASADS/ASRE, ASOE, and ASWE (for
EMIFA) and BSADS/BSRE, BSOE, and BSWE (for EMIFB)].
switching characteristics over recommended operating conditions for programmable
†‡
synchronous interface cycles for EMIFA module (see Figure 24−Figure 26)
NO.
1
PARAMETER
MIN
MAX
4.9
UNIT
ns
t
t
t
t
t
t
t
t
t
t
Delay time, ECLKOUTx high to CEx valid
Delay time, ECLKOUTx high to BEx valid
Delay time, ECLKOUTx high to BEx invalid
Delay time, ECLKOUTx high to EAx valid
Delay time, ECLKOUTx high to EAx invalid
Delay time, ECLKOUTx high to SADS/SRE valid
Delay time, ECLKOUTx high to, SOE valid
Delay time, ECLKOUTx high to EDx valid
Delay time, ECLKOUTx high to EDx invalid
Delay time, ECLKOUTx high to SWE valid
1.3
d(EKOxH-CEV)
d(EKOxH-BEV)
d(EKOxH-BEIV)
d(EKOxH-EAV)
d(EKOxH-EAIV)
d(EKOxH-ADSV)
d(EKOxH-OEV)
d(EKOxH-EDV)
d(EKOxH-EDIV)
d(EKOxH-WEV)
2
5.1
ns
3
1.3
ns
4
4.9
ns
5
1.3
1.3
1.3
ns
8
4.9
4.9
4.9
ns
9
ns
10
11
12
ns
1.3
1.3
ns
4.9
ns
†
‡
These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a
“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the programmable
synchronous interface access signals are shown as generic (SADS/SRE, SOE, and SWE) instead of ASADS/ASRE, ASOE, and ASWE (for
EMIFA) and BSADS/BSRE, BSOE, and BSWE (for EMIFB)].
The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC):
−
−
−
Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency
Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency
CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, CEx goes inactive after the final command has been issued
(CEEXT = 0). For synchronous FIFO interface with glue, CEx is active when SOE is active (CEEXT = 1).
Function of SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, SADS/SRE acts as SADS with deselect cycles
(RENEN = 0). For FIFO interface, SADS/SRE acts as SRE with NO deselect cycles (RENEN = 1).
Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2
−
−
88
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢊ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢊ ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
PROGRAMMABLE SYNCHRONOUS INTERFACE TIMING (CONTINUED)
†
timing requirements for programmable synchronous interface cycles for EMIFB module
(see Figure 24)
NO.
6
MIN
3.1
MAX
UNIT
ns
t
t
Setup time, read EDx valid before ECLKOUTx high
Hold time, read EDx valid after ECLKOUTx high
su(EDV-EKOxH)
7
1.5
ns
h(EKOxH-EDV)
†
These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a
“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the programmable
synchronous interface access signals are shown as generic (SADS/SRE, SOE, and SWE) instead of ASADS/ASRE, ASOE, and ASWE (for
EMIFA) and BSADS/BSRE, BSOE, and BSWE (for EMIFB)].
switching characteristics over recommended operating conditions for programmable
†‡
synchronous interface cycles for EMIFB module (see Figure 24−Figure 26)
NO.
1
PARAMETER
MIN
MAX
6.4
UNIT
ns
t
t
t
t
t
t
t
t
t
t
Delay time, ECLKOUTx high to CEx valid
Delay time, ECLKOUTx high to BEx valid
Delay time, ECLKOUTx high to BEx invalid
Delay time, ECLKOUTx high to EAx valid
Delay time, ECLKOUTx high to EAx invalid
Delay time, ECLKOUTx high to SADS/SRE valid
Delay time, ECLKOUTx high to, SOE valid
Delay time, ECLKOUTx high to EDx valid
Delay time, ECLKOUTx high to EDx invalid
Delay time, ECLKOUTx high to SWE valid
1.3
d(EKOxH-CEV)
d(EKOxH-BEV)
d(EKOxH-BEIV)
d(EKOxH-EAV)
d(EKOxH-EAIV)
d(EKOxH-ADSV)
d(EKOxH-OEV)
d(EKOxH-EDV)
d(EKOxH-EDIV)
d(EKOxH-WEV)
2
6.4
ns
3
1.3
ns
4
6.4
ns
5
1.3
1.3
1.3
ns
8
6.4
6.4
6.4
ns
9
ns
10
11
12
ns
1.3
1.3
ns
6.4
ns
†
‡
These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a
“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the programmable
synchronous interface access signals are shown as generic (SADS/SRE, SOE, and SWE) instead of ASADS/ASRE, ASOE, and ASWE (for
EMIFA) and BSADS/BSRE, BSOE, and BSWE (for EMIFB)].
The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC):
−
−
−
Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency
Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency
CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, CEx goes inactive after the final command has been issued
(CEEXT = 0). For synchronous FIFO interface with glue, CEx is active when SOE is active (CEEXT = 1).
Function of SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, SADS/SRE acts as SADS with deselect cycles
(RENEN = 0). For FIFO interface, SADS/SRE acts as SRE with NO deselect cycles (RENEN = 1).
Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2
−
−
89
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢋ ꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢇ
ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
PROGRAMMABLE SYNCHRONOUS INTERFACE TIMING (CONTINUED)
READ latency = 2
ECLKOUTx
1
2
1
3
5
CEx
BE1
BE2
BE3
EA3
BE4
ABE[7:0] or BBE[1:0]
4
AEA[22:3] or BEA[20:1]
AED[63:0] or BED[15:0]
EA1
8
EA2
EA4
7
6
Q1
Q2
Q3
Q4
8
9
§
ARE/SDCAS/SADS/SRE
9
§
§
AOE/SDRAS/SOE
AWE/SDWE/SWE
†
These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a
“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the programmable
synchronous interface access signals are shown as generic (SADS/SRE, SOE, and SWE) instead of ASADS/ASRE, ASOE, and ASWE (for
EMIFA) and BSADS/BSRE, BSOE, and BSWE (for EMIFB)].
‡
§
The read latency and the length of CEx assertion are programmable via the SYNCRL and CEEXT fields, respectively, in the EMIFx CE Space
Secondary Control register (CExSEC). In this figure, SYNCRL = 2 and CEEXT = 0.
The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC):
−
−
−
Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency
Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency
CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, CEx goes inactive after the final command has been issued
(CEEXT = 0). For synchronous FIFO interface with glue, CEx is active when SOE is active (CEEXT = 1).
Function of SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, SADS/SRE acts as SADS with deselect cycles
(RENEN = 0). For FIFO interface, SADS/SRE acts as SRE with NO deselect cycles (RENEN = 1).
Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2
−
−
¶
ARE/SDCAS/SADS/SRE, AOE/SDRAS/SOE, and AWE/SDWE/SWE operate as SADS/SRE, SOE, and SWE, respectively, during
programmable synchronous interface accesses.
Figure 24. Programmable Synchronous Interface Read Timing for EMIFA and EMIFB
†‡§
(With Read Latency = 2)
90
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢊ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢊ ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
PROGRAMMABLE SYNCHRONOUS INTERFACE TIMING (CONTINUED)
ECLKOUTx
1
1
3
CEx
2
ABE[7:0] or BBE[1:0]
AEA[22:3] or BEA[20:1]
AED[63:0] or BED[15:0]
BE1
BE2
EA2
Q2
BE3
EA3
Q3
BE4
EA4
Q4
5
4
EA1
10
Q1
10
11
12
8
8
¶
ARE/SDCAS/SADS/SRE
AOE/SDRAS/SOE
¶
12
¶
AWE/SDWE/SWE
†
These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a
“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the programmable
synchronous interface access signals are shown as generic (SADS/SRE, SOE, and SWE) instead of ASADS/ASRE, ASOE, and ASWE (for
EMIFA) and BSADS/BSRE, BSOE, and BSWE (for EMIFB)].
‡
§
The write latency and the length of CEx assertion are programmable via the SYNCWL and CEEXT fields, respectively, in the EMIFx CE Space
Secondary Control register (CExSEC). In this figure, SYNCWL = 0 and CEEXT = 0.
The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC):
−
−
−
Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency
Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency
CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, CEx goes inactive after the final command has been issued
(CEEXT = 0). For synchronous FIFO interface with glue, CEx is active when SOE is active (CEEXT = 1).
Function of SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, SADS/SRE acts as SADS with deselect cycles
(RENEN = 0). For FIFO interface, SADS/SRE acts as SRE with NO deselect cycles (RENEN = 1).
Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2
−
−
¶
ARE/SDCAS/SADS/SRE, AOE/SDRAS/SOE, and AWE/SDWE/SWE operate as SADS/SRE, SOE, and SWE, respectively, during
programmable synchronous interface accesses.
Figure 25. Programmable Synchronous Interface Write Timing for EMIFA and EMIFB
†‡§
(With Write Latency = 0)
91
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢋ ꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢇ
ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
PROGRAMMABLE SYNCHRONOUS INTERFACE TIMING (CONTINUED)
Write
Latency =
‡
1
ECLKOUTx
1
1
3
CEx
2
ABE[7:0] or BBE[1:0]
BE1
BE2
EA2
BE3
EA3
Q2
BE4
EA4
Q3
5
4
AEA[22:3] or BEA[20:1]
AED[63:0] or BED[15:0]
EA1
10
10
11
8
Q1
Q4
8
¶
¶
ARE/SDCAS/SADS/SRE
AOE/SDRAS/SOE
12
12
¶
AWE/SDWE/SWE
†
These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a
“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the programmable
synchronous interface access signals are shown as generic (SADS/SRE, SOE, and SWE) instead of ASADS/ASRE, ASOE, and ASWE (for
EMIFA) and BSADS/BSRE, BSOE, and BSWE (for EMIFB)].
‡
§
The write latency and the length of CEx assertion are programmable via the SYNCWL and CEEXT fields, respectively, in the EMIFx CE Space
Secondary Control register (CExSEC). In this figure, SYNCWL = 1 and CEEXT = 0.
The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC):
−
−
−
Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency
Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency
CEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, CEx goes inactive after the final command has been issued
(CEEXT = 0). For synchronous FIFO interface with glue, CEx is active when SOE is active (CEEXT = 1).
Function of SADS/SRE (RENEN): For standard SBSRAM or ZBT SRAM interface, SADS/SRE acts as SADS with deselect cycles
(RENEN = 0). For FIFO interface, SADS/SRE acts as SRE with NO deselect cycles (RENEN = 1).
Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2
−
−
¶
ARE/SDCAS/SADS/SRE, AOE/SDRAS/SOE, and AWE/SDWE/SWE operate as SADS/SRE, SOE, and SWE, respectively, during
programmable synchronous interface accesses.
Figure 26. Programmable Synchronous Interface Write Timing for EMIFA and EMIFB
†‡§
(With Write Latency = 1)
92
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢊ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢊ ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
SYNCHRONOUS DRAM TIMING
†
timing requirements for synchronous DRAM cycles for EMIFA module (see Figure 27)
NO.
6
MIN MAX
UNIT
ns
t
t
Setup time, read EDx valid before ECLKOUTx high
Hold time, read EDx valid after ECLKOUTx high
0.6
1.8
su(EDV-EKO1H)
7
ns
h(EKO1H-EDV)
†
These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a
“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the synchronous DRAM
memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and
BSDCAS, BSDWE, and BSDRAS (for EMIFB)].
switching characteristics over recommended operating conditions for synchronous DRAM cycles
†
for EMIFA module (see Figure 27−Figure 34)
NO.
1
PARAMETER
MIN
MAX
4.9
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
Delay time, ECLKOUTx high to CEx valid
Delay time, ECLKOUTx high to BEx valid
Delay time, ECLKOUTx high to BEx invalid
Delay time, ECLKOUTx high to EAx valid
Delay time, ECLKOUTx high to EAx invalid
Delay time, ECLKOUTx high to SDCAS valid
Delay time, ECLKOUTx high to EDx valid
Delay time, ECLKOUTx high to EDx invalid
Delay time, ECLKOUTx high to SDWE valid
Delay time, ECLKOUTx high to SDRAS valid
Delay time, ECLKOUTx high to ASDCKE valid (EMIFA only)
Delay time, ECLKOUTx high to PDT valid
1.3
d(EKO1H-CEV)
d(EKO1H-BEV)
d(EKO1H-BEIV)
d(EKO1H-EAV)
d(EKO1H-EAIV)
d(EKO1H-CASV)
d(EKO1H-EDV)
d(EKO1H-EDIV)
d(EKO1H-WEV)
d(EKO1H-RAS)
d(EKO1H-ACKEV)
d(EKO1H-PDTV)
2
4.9
3
1.3
4
4.9
5
1.3
1.3
8
4.9
4.9
9
10
11
12
13
14
1.3
1.3
1.3
1.3
1.3
4.9
4.9
4.9
4.9
†
These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a
“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the synchronous DRAM
memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and
BSDCAS, BSDWE, and BSDRAS (for EMIFB)].
93
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢋ ꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢇ
ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
SYNCHRONOUS DRAM TIMING (CONTINUED)
†
timing requirements for synchronous DRAM cycles for EMIFB module (see Figure 27)
NO.
6
MIN MAX
UNIT
ns
t
t
Setup time, read EDx valid before ECLKOUTx high
Hold time, read EDx valid after ECLKOUTx high
2.1
2.5
su(EDV-EKO1H)
7
ns
h(EKO1H-EDV)
†
These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a
“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the synchronous DRAM
memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and
BSDCAS, BSDWE, and BSDRAS (for EMIFB)].
switching characteristics over recommended operating conditions for synchronous DRAM cycles
†
for EMIFB module (see Figure 27−Figure 34)
NO.
1
PARAMETER
MIN
MAX
6.4
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
Delay time, ECLKOUTx high to CEx valid
Delay time, ECLKOUTx high to BEx valid
Delay time, ECLKOUTx high to BEx invalid
Delay time, ECLKOUTx high to EAx valid
Delay time, ECLKOUTx high to EAx invalid
Delay time, ECLKOUTx high to SDCAS valid
Delay time, ECLKOUTx high to EDx valid
Delay time, ECLKOUTx high to EDx invalid
Delay time, ECLKOUTx high to SDWE valid
Delay time, ECLKOUTx high to SDRAS valid
Delay time, ECLKOUTx high to ASDCKE valid (EMIFA only)
Delay time, ECLKOUTx high to PDT valid
1.3
d(EKO1H-CEV)
d(EKO1H-BEV)
d(EKO1H-BEIV)
d(EKO1H-EAV)
d(EKO1H-EAIV)
d(EKO1H-CASV)
d(EKO1H-EDV)
d(EKO1H-EDIV)
d(EKO1H-WEV)
d(EKO1H-RAS)
d(EKO1H-ACKEV)
d(EKO1H-PDTV)
2
6.4
3
1.3
4
6.4
5
1.3
1.3
8
6.4
6.4
9
10
11
12
13
14
1.3
1.3
6.4
6.4
1.3
1.3*
1.3
6.4*
6.4
*This parameter is not production tested.
†
These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a
“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the synchronous DRAM
memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and
BSDCAS, BSDWE, and BSDRAS (for EMIFB)].
94
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢊ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢊ ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
SYNCHRONOUS DRAM TIMING (CONTINUED)
READ
ECLKOUTx
CEx
1
1
2
3
ABE[7:0] or BBE[1:0]
BE1
BE2
BE3
BE4
4
5
5
5
Bank
AEA[22:14] or BEA[20:12]
AEA[12:3] or BEA[10:1]
4
Column
4
AEA13 or BEA11
6
7
D2
AED[63:0] or BED[15:0]
D1
D3
D4
‡
AOE/SDRAS/SOE
8
8
‡
ARE/SDCAS/SADS/SRE
‡
AWE/SDWE/SWE
14
14
§
PDT
†
These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a
“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the synchronous DRAM
memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and
BSDCAS, BSDWE, and BSDRAS (for EMIFB)].
‡
§
ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM
accesses.
PDT signal is only asserted when the EDMA is in PDT mode (set the PDTS bit to 1 in the EDMA options parameter RAM). For PDT read, data
is not latched into EMIF. The PDTRL field in the PDT control register (PDTCTL) configures the latency of the PDT signal with respect to the data
phase of a read transaction. The latency of the PDT signal for a read can be programmed to 0, 1, 2, or 3 by setting PDTRL to 00, 01, 10, or 11,
respectively. PDTRL equals 00 (zero latency) in Figure 27.
†
Figure 27. SDRAM Read Command (CAS Latency 3) for EMIFA and EMIFB
95
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢋ ꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢇ
ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
SYNCHRONOUS DRAM TIMING (CONTINUED)
WRITE
ECLKOUTx
CEx
1
2
4
4
4
9
2
4
5
5
5
9
3
ABE[7:0] or BBE[1:0]
BE1
Bank
BE2
BE3
BE4
AEA[22:14] or BEA[20:12]
Column
AEA[12:3] or BEA[10:1]
AEA13 or BEA11
10
AED[63:0] or BED[15:0]
D1
D2
D3
D4
‡
AOE/SDRAS/SOE
8
8
‡
ARE/SDCAS/SADS/SRE
11
14
11
‡
AWE/SDWE/SWE
PDT
14
§
†
These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a
“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the synchronous DRAM
memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and
BSDCAS, BSDWE, and BSDRAS (for EMIFB)].
‡
§
ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM
accesses.
PDT signal is only asserted when the EDMA is in PDT mode (set the PDTD bit to 1 in the EDMA options parameter RAM). For PDT write, data
is not driven (in High-Z). The PDTWL field in the PDT control register (PDTCTL) configures the latency of the PDT signal with respect to the data
phase of a write transaction. The latency of the PDT signal for a write transaction can be programmed to 0, 1, 2, or 3 by setting PDTWL to 00,
01, 10, or 11, respectively. PDTWL equals 00 (zero latency) in Figure 28.
†
Figure 28. SDRAM Write Command for EMIFA and EMIFB
96
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢊ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢊ ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
SYNCHRONOUS DRAM TIMING (CONTINUED)
ACTV
ECLKOUTx
1
1
CEx
ABE[7:0] or BBE[1:0]
4
5
5
5
Bank Activate
AEA[22:14] or BEA[20:12]
AEA[12:3] or BEA[10:1]
4
Row Address
4
Row Address
AEA13 or BEA11
AED[63:0] or BED[15:0]
12
12
‡
‡
AOE/SDRAS/SOE
ARE/SDCAS/SADS/SRE
‡
AWE/SDWE/SWE
†
‡
These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a
“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the synchronous DRAM
memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and
BSDCAS, BSDWE, and BSDRAS (for EMIFB)].
ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM
accesses.
†
Figure 29. SDRAM ACTV Command for EMIFA and EMFB
97
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢋ ꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢇ
ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
SYNCHRONOUS DRAM TIMING (CONTINUED)
DCAB
ECLKOUTx
1
1
CEx
ABE[7:0] or BBE[1:0]
AEA[22:14, 12:3] or
BEA[20:12, 10:1]
4
12
11
5
12
11
AEA13 or BEA11
AED[63:0] or BED[15:0]
‡
‡
AOE/SDRAS/SOE
ARE/SDCAS/SADS/SRE
‡
AWE/SDWE/SWE
†
‡
These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a
“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the synchronous DRAM
memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and
BSDCAS, BSDWE, and BSDRAS (for EMIFB)].
ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM
accesses.
†
Figure 30. SDRAM DCAB Command for EMIFA and EMIFB
98
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢊ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢊ ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
SYNCHRONOUS DRAM TIMING (CONTINUED)
DEAC
ECLKOUTx
1
1
CEx
ABE[7:0] or BBE[1:0]
4
5
AEA[22:14] or BEA[20:12]
AEA[12:3] or BEA[10:1]
Bank
4
5
AEA13 or BEA11
AED[63:0] or BED[15:0]
12
11
12
11
‡
‡
AOE/SDRAS/SOE
ARE/SDCAS/SADS/SRE
‡
AWE/SDWE/SWE
†
‡
These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a
“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the synchronous DRAM
memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and
BSDCAS, BSDWE, and BSDRAS (for EMIFB)].
ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM
accesses.
†
Figure 31. SDRAM DEAC Command for EMIFA and EMIFB
99
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢋ ꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢇ
ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
SYNCHRONOUS DRAM TIMING (CONTINUED)
REFR
ECLKOUTx
1
1
CEx
ABE[7:0] or BBE[1:0]
AEA[22:14, 12:3] or
BEA[20:12, 10:1]
AEA13 or BEA11
AED[63:0] or BED[15:0]
12
8
12
8
‡
AOE/SDRAS/SOE
‡
‡
ARE/SDCAS/SADS/SRE
AWE/SDWE/SWE
†
‡
These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a
“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the synchronous DRAM
memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and
BSDCAS, BSDWE, and BSDRAS (for EMIFB)].
ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM
accesses.
†
Figure 32. SDRAM REFR Command for EMIFA and EMIFB
100
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢊ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢊ ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
SYNCHRONOUS DRAM TIMING (CONTINUED)
MRS
ECLKOUTx
1
1
5
CEx
ABE[7:0] or BBE[1:0]
4
AEA[22:3] or BEA[20:1]
AED[63:0] or BED[15:0]
MRS value
12
8
12
8
‡
AOE/SDRAS/SOE
‡
ARE/SDCAS/SADS/SRE
11
11
‡
AWE/SDWE/SWE
†
‡
These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a
“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the synchronous DRAM
memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and
BSDCAS, BSDWE, and BSDRAS (for EMIFB)].
ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM
accesses.
†
Figure 33. SDRAM MRS Command for EMIFA and EMIFB
101
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢋ ꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢇ
ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
SYNCHRONOUS DRAM TIMING (CONTINUED)
≥ TRAS cycles
End Self-Refresh
Self Refresh
AECLKOUTx
ACEx
ABE[7:0]
AEA[22:14, 12:3]
AEA13
AED[63:0]
‡
AAOE/ASDRAS/ASOE
AARE/ASDCAS/ASADS/
‡
ASRE
‡
AAWE/ASDWE/ASWE
13
13
ASDCKE
†
‡
These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a
“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the synchronous DRAM
memory access signals are shown as generic ( SDCAS, SDWE, and SDRAS ) instead of ASDCAS, ASDWE, and ASDRAS (for EMIFA) and
BSDCAS, BSDWE, and BSDRAS (for EMIFB)].
AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS,
respectively, during SDRAM accesses.
†
Figure 34. SDRAM Self-Refresh Timing for EMIFA Only
102
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢊ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢊ ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
HOLD/HOLDA TIMING
†
timing requirements for the HOLD/HOLDA cycles for EMIFA and EMIFB modules (see Figure 35)
NO.
MIN MAX
UNIT
3
t
Hold time, HOLD low after HOLDA low
E*
ns
oh(HOLDAL-HOLDL)
*This parameter is not production tested.
†
E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB.
switching characteristics over recommended operating conditions for the HOLD/HOLDA cycles
†‡§
for EMIFA and EMIFB modules
(see Figure 35)
NO.
PARAMETER
MIN
2E*
0*
MAX
UNIT
ns
¶
*
1
2
4
5
6
7
t
t
t
t
t
t
Delay time, HOLD low to EMIF Bus high impedance
Delay time, EMIF Bus high impedance to HOLDA low
Delay time, HOLD high to EMIF Bus low impedance
Delay time, EMIF Bus low impedance to HOLDA high
Delay time, HOLD low to ECLKOUTx high impedance
Delay time, HOLD high to ECLKOUTx low impedance
d(HOLDL-EMHZ)
d(EMHZ-HOLDAL)
d(HOLDH-EMLZ)
d(EMLZ-HOLDAH)
d(HOLDL-EKOHZ)
d(HOLDH-EKOLZ)
2E*
7E*
2E*
ns
2E*
0*
ns
ns
¶
2E*
2E*
*
ns
7E*
ns
*This parameter is not production tested.
†
‡
E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB.
For EMIFA, EMIF Bus consists of: ACE[3:0], ABE[7:0], AED[63:0], AEA[22:3], AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and
AAWE/ASDWE/ASWE , ASDCKE, ASOE3, and APDT.
For EMIFB, EMIF Bus consists of: BCE[3:0], BBE[1:0], BED[15:0], BEA[20:1], BARE/BSDCAS/BSADS/BSRE, BAOE/BSDRAS/BSOE, and
BAWE/BSDWE/BSWE, BSOE3, and BPDT.
The EKxHZ bits in the EMIF Global Control register (GBLCTL) determine the state of the ECLKOUTx signals during HOLDA. If EKxHZ = 0,
ECLKOUTx continues clocking during Hold mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during Hold mode, as shown in Figure 35.
All pending EMIF transactions are allowed to complete before HOLDA is asserted. If no bus transactions are occurring, then the minimum delay
time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.
§
¶
External Requestor
DSP Owns Bus
DSP Owns Bus
Owns Bus
3
HOLD
2
5
HOLDA
1
4
7
†
EMIF Bus
C64x
C64x
‡
ECLKOUTx
(EKxHZ = 0)
6
‡
ECLKOUTx
(EKxHZ = 1)
†
‡
For EMIFA, EMIF Bus consists of: ACE[3:0], ABE[7:0], AED[63:0], AEA[22:3], AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and
AAWE/ASDWE/ASWE, ASDCKE, ASOE3, and APDT.
For EMIFB, EMIF Bus consists of: BCE[3:0], BBE[1:0], BED[15:0], BEA[20:1], BARE/BSDCAS/BSADS/BSRE, BAOE/BSDRAS/BSOE, and
BAWE/BSDWE/BSWE, BSOE3, and BPDT.
The EKxHZ bits in the EMIF Global Control register (GBLCTL) determine the state of the ECLKOUTx signals during HOLDA. If EKxHZ = 0,
ECLKOUTx continues clocking during Hold mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during Hold mode, as shown in Figure 35.
Figure 35. HOLD/HOLDA Timing for EMIFA and EMIFB
103
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢋ ꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢇ
ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
BUSREQ TIMING
switching characteristics over recommended operating conditions for the BUSREQ cycles
for EMIFA and EMIFB modules (see Figure 36)
NO.
1
PARAMETER
MIN
1
MAX UNIT
t
t
Delay time, AECLKOUTx high to ABUSREQ valid
Delay time, BECLKOUTx high to BBUSREQ valid
5.5
5.5
ns
ns
d(AEKO1H-ABUSRV)
2
0.9
d(BEKO1H-BBUSRV)
ECLKOUTx
1
2
1
2
ABUSREQ
BBUSREQ
Figure 36. BUSREQ Timing for EMIFA and EMIFB
104
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢊ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢊ ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
RESET TIMING
timing requirements for reset (see Figure 37)
†
NO.
MIN
10P*
250*
4P*
MAX
UNIT
ns
‡
Width of the RESET pulse (PLL stable)
1
t
w(RST)
§
Width of the RESET pulse (PLL needs to sync up)
µs
¶
16
17
t
t
Setup time, boot configuration bits valid before RESET high
ns
su(boot)
¶
Hold time, boot configuration bits valid after RESET high
4P*
ns
h(boot)
*This parameter is not production tested.
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
This parameter applies to CLKMODE x1 when CLKIN is stable, and applies to CLKMODE x6, x12 when CLKIN and PLL are stable.
This parameter applies to CLKMODE x6, x12 only (it does not apply to CLKMODE x1). The RESET signal is not connected internally to the clock
PLL circuit. The PLL, however, may need up to 250 µs to stabilize following device power up or after PLL configuration has been changed. During
that time, RESET must be asserted to ensure proper device operation. See the clock PLL section for PLL lock times.
EMIFB address pins BEA[20:13, 11, 7] are the boot configuration pins during device reset.
¶
†#||
switching characteristics over recommended operating conditions during reset
(see Figure 37)
NO.
2
PARAMETER
MIN
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Delay time, RESET low to ECLKIN synchronized internally
Delay time, RESET high to ECLKIN synchronized internally
Delay time, RESET low to ECLKOUT1 high impedance
Delay time, RESET high to ECLKOUT1 valid
Delay time, RESET low to EMIF Z high impedance
Delay time, RESET high to EMIF Z valid
2E* 3P + 20E*
2E* 8P + 20E*
2E*
d(RSTL-ECKI)
3
d(RSTH-ECKI)
4
d(RSTL-ECKO1HZ)
d(RSTH-ECKO1V)
d(RSTL-EMIFZHZ)
d(RSTH-EMIFZV)
d(RSTL-EMIFHIV)
d(RSTH-EMIFHV)
d(RSTL-EMIFLIV)
d(RSTH-EMIFLV)
d(RSTL-LOWIV)
d(RSTH-LOWV)
d(RSTL-ZHZ)
5
8P + 20E*
6
2E*
3P + 4E*
7
16E* 8P + 20E*
8
Delay time, RESET low to EMIF high group invalid
Delay time, RESET high to EMIF high group valid
Delay time, RESET low to EMIF low group invalid
Delay time, RESET high to EMIF low group valid
Delay time, RESET low to low group invalid
Delay time, RESET high to low group valid
2E*
9
8P + 20E*
2E*
10
11
12
13
14
15
8P + 20E*
0*
11P*
Delay time, RESET low to Z group high impedance
Delay time, RESET high to Z group valid
0*
2P*
8P*
d(RSTH-ZV)
*This parameter is not production tested.
†
#
||
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB.
EMIF Z group consists of:
AEA[22:3], BEA[20:1], AED[63:0], BED[15:0], CE[3:0], ABE[7:0], BBE[1:0], ARE/SDCAS/SADS/SRE,
AWE/SDWE/SWE, and AOE/SDRAS/SOE, SOE3, ASDCKE, and PDT.
EMIF high group consists of: AHOLDA and BHOLDA (when the corresponding HOLD input is high)
EMIF low group consists of: ABUSREQ and BBUSREQ; AHOLDA and BHOLDA (when the corresponding HOLD input is low)
Low group consists of:
XSP_CS, CLKX2/XSP_CLK, and DX2/XSP_DO; all of which apply only when PCI EEPROM (BEA13)
is enabled (with PCI_EN = 1 and MCBSP2_EN = 0). Otherwise, the CLKX2/XSP_CLK and DX2/XSP_DO
pins are in the Z group. For more details on the PCI configuration pins, see the Device Configurations section
of this data sheet.
Z group consists of:
HD[31:0]/AD[31:0], CLKX0, CLKX1/URADDR4, CLKX2/XSP_CLK, FSX0, FSX1/UXADDR3, FSX2, DX0,
DX1/UXADDR4, DX2/XSP_DO, CLKR0, CLKR1/URADDR2, CLKR2, FSR0, FSR1/UXADDR2, FSR2,
TOUT0, TOUT1, TOUT2, GP[8:0], GP10/PCBE3, HR/W/PCBE2, HDS2/PCBE1, PCBE0, GP13/PINTA,
GP11/PREQ, HDS1/PSERR, HCS/PPERR, HCNTL1/PDEVSEL, HAS/PPAR, HCNTL0/PSTOP,
HHWIL/PTRDY (16-bit HPI mode only), HRDY/PIRDY, HINT/PFRAME, UXDATA[7:0], UXSOC, UXCLAV,
and URCLAV.
105
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ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢋ ꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢇ
ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
RESET TIMING (CONTINUED)
CLKOUT4
CLKOUT6
1
RESET
2
4
3
5
ECLKIN
ECLKOUT1
ECLKOUT2
6
7
‡§
EMIF Z Group
EMIF High Group
EMIF Low Group
9
8
‡
‡
11
13
10
12
14
16
‡
Low Group
15
‡§
Z Group
17
Boot and Device
§¶
Configuration Inputs
†
‡
These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a
“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., ECLKIN, ECLKOUT1,
and ECLKOUT2].
EMIF Z group consists of:
AEA[22:3], BEA[20:1], AED[63:0], BED[15:0], CE[3:0], ABE[7:0], BBE[1:0], ARE/SDCAS/SADS/SRE,
AWE/SDWE/SWE, and AOE/SDRAS/SOE, SOE3, ASDCKE, and PDT.
EMIF high group consists of: AHOLDA and BHOLDA (when the corresponding HOLD input is high)
EMIF low group consists of: ABUSREQ and BBUSREQ; AHOLDA and BHOLDA (when the corresponding HOLD input is low)
Low group consists of:
XSP_CS, CLKX2/XSP_CLK, and DX2/XSP_DO; all of which apply only when PCI EEPROM (BEA13)
is enabled (with PCI_EN = 1 and MCBSP2_EN = 0). Otherwise, the CLKX2/XSP_CLK and DX2/XSP_DO
pins are in the Z group. For more details on the PCI configuration pins, see the Device Configurations section
of this data sheet.
Z group consists of:
HD[31:0]/AD[31:0], CLKX0, CLKX1/URADDR4, CLKX2/XSP_CLK, FSX0, FSX1/UXADDR3, FSX2, DX0,
DX1/UXADDR4, DX2/XSP_DO, CLKR0, CLKR1/URADDR2, CLKR2, FSR0, FSR1/UXADDR2, FSR2,
TOUT0, TOUT1, TOUT2, GP[8:0], GP10/PCBE3, HR/W/PCBE2, HDS2/PCBE1, PCBE0, GP13/PINTA,
GP11/PREQ, HDS1/PSERR, HCS/PPERR, HCNTL1/PDEVSEL, HAS/PPAR, HCNTL0/PSTOP,
HHWIL/PTRDY (16-bit HPI mode only), HRDY/PIRDY, HINT/PFRAME, UXDATA[7:0], UXSOC, UXCLAV,
and URCLAV.
§
¶
If BEA[20:13, 11, 7] and HD5/AD5 pins are actively driven, care must be taken to ensure no timing contention between parameters 6, 7, 14, 15,
16, and 17.
Boot and Device Configurations Inputs (during reset) include: EMIFB address pins BEA[20:13, 11, 7] and HD5/AD5.
The PCI_EN pin must be driven valid at all times and the user must not switch values throughout device operation.
The MCBSP2_EN pin must be driven valid at all times and the user can switch values throughout device operation.
†
Figure 37. Reset Timing
106
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ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
EXTERNAL INTERRUPT TIMING
†
timing requirements for external interrupts (see Figure 38)
MIN
4P*
8P*
4P*
8P*
MAX
Width of the NMI interrupt pulse low
ns
ns
ns
ns
1
2
t
t
w(ILOW)
Width of the EXT_INT interrupt pulse low
Width of the NMI interrupt pulse high
Width of the EXT_INT interrupt pulse high
w(IHIGH)
*This parameter is not production tested.
†
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
2
1
EXT_INTx, NMI
Figure 38. External/NMI Interrupt Timing
107
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ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
HOST-PORT INTERFACE (HPI) TIMING
†‡
timing requirements for host-port interface cycles (see Figure 39 through Figure 46)
NO.
1
MIN
5
MAX
UNIT
ns
§
Setup time, select signals valid before HSTROBE low
t
t
t
t
t
t
t
t
su(SELV-HSTBL)
h(HSTBL-SELV)
w(HSTBL)
§
2
Hold time, select signals valid after HSTROBE low
2.4
ns
¶
4P *
3
Pulse duration, HSTROBE low
ns
4
Pulse duration, HSTROBE high between consecutive accesses
4P*
5
ns
w(HSTBH)
§
10
11
12
13
Setup time, select signals valid before HAS low
ns
su(SELV-HASL)
h(HASL-SELV)
su(HDV-HSTBH)
h(HSTBH-HDV)
§
Hold time, select signals valid after HAS low
2
ns
Setup time, host data valid before HSTROBE high
Hold time, host data valid after HSTROBE high
5
ns
2.8
ns
Hold time, HSTROBE low after HRDY low. HSTROBE should not be
inactivated until HRDY is active (low); otherwise, HPI writes will not complete
properly.
14
t
2*
ns
h(HRDYL-HSTBL)
18
19
t
t
Setup time, HAS low before HSTROBE low
Hold time, HAS low after HSTROBE low
2
ns
ns
su(HASL-HSTBL)
2.1
h(HSTBL-HASL)
*This parameter is not production tested.
†
‡
§
¶
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
Select signals include: HCNTL[1:0] and HR/W. For HPI16 mode only, select signals also include HHWIL.
Select the parameter value of 4P or 12.5 ns, whichever is greater.
switching characteristics over recommended operating conditions during host-port interface
†‡
cycles (see Figure 39 through Figure 46)
NO.
PARAMETER
MIN
MAX
UNIT
#
6
t
Delay time, HSTROBE low to HRDY high
1.3
4P + 8
ns
d(HSTBL-HRDYH)
Delay time, HSTROBE low to HD low impedance for an
HPI read
7
t
2*
ns
d(HSTBL-HDLZ)
8
9
t
Delay time, HD valid to HRDY low
−3
ns
ns
ns
ns
d(HDV-HRDYL)
t
Output hold time, HD valid after HSTROBE high
Delay time, HSTROBE high to HD high impedance
Delay time, HSTROBE low to HD valid (HPI16 only)
1.5
oh(HSTBH-HDV)
15
16
t
12*
d(HSTBH-HDHZ)
t
4P + 8
d(HSTBL-HDV)
*This parameter is not production tested.
†
‡
#
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
This parameter is used during HPID reads and writes. For reads, at the beginning of a word transfer (HPI32) or the first half-word transfer (HPI16)
on the falling edge of HSTROBE, the HPI sends the request to the EDMA internal address generation hardware, and HRDY remains high until
the EDMA internal address generation hardware loads the requested data into HPID. For writes, HRDY goes high if the internal write buffer is
full.
108
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ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
HOST-PORT INTERFACE (HPI) TIMING (CONTINUED)
HAS
HCNTL[1:0]
HR/W
1
1
1
1
2
2
2
2
2
2
1
1
HHWIL
4
3
3
†
HSTROBE
HCS
15
9
15
9
7
16
HD[15:0] (output)
HRDY
1st half-word
2nd half-word
6
8
†
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 39. HPI16 Read Timing (HAS Not Used, Tied High)
†
HAS
19
11
19
11
10
10
10
10
HCNTL[1:0]
HR/W
11
11
11
11
10
10
HHWIL
4
3
‡
HSTROBE
18
18
HCS
15
15
7
9
16
9
HD[15:0] (output)
HRDY
1st half-word
2nd half-word
6
8
†
‡
For correct operation, strobe the HAS signal only once per HSTROBE active cycle.
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 40. HPI16 Read Timing (HAS Used)
109
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ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
HOST-PORT INTERFACE (HPI) TIMING (CONTINUED)
HAS
HCNTL[1:0]
HR/W
1
1
2
2
2
2
2
2
3
1
1
1
1
HHWIL
3
4
†
HSTROBE
HCS
12
12
13
2nd half-word
13
HD[15:0] (input)
1st half-word
6
14
HRDY
†
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 41. HPI16 Write Timing (HAS Not Used, Tied High)
19
11
19
†
HAS
11
11
11
10
10
10
10
10
10
HCNTL[1:0]
HR/W
11
11
HHWIL
3
4
‡
HSTROBE
18
12
18
HCS
12
13
13
HD[15:0] (input)
1st half-word
2nd half-word
6
14
HRDY
†
‡
For correct operation, strobe the HAS signal only once per HSTROBE active cycle.
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 42. HPI16 Write Timing (HAS Used)
110
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ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
HOST-PORT INTERFACE (HPI) TIMING (CONTINUED)
HAS
HCNTL[1:0]
HR/W
1
1
2
2
3
†
HSTROBE
HCS
7
9
15
HD[31:0] (output)
HRDY
6
8
†
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 43. HPI32 Read Timing (HAS Not Used, Tied High)
19
†
HAS
11
11
10
10
HCNTL[1:0]
HR/W
18
3
‡
HSTROBE
HCS
7
9
15
HD[31:0] (output)
HRDY
6
8
†
‡
For correct operation, strobe the HAS signal only once per HSTROBE active cycle.
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 44. HPI32 Read Timing (HAS Used)
111
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ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
HOST-PORT INTERFACE (HPI) TIMING (CONTINUED)
HAS
HCNTL[1:0]
HR/W
1
1
2
2
3
†
HSTROBE
HCS
12
13
HD[31:0] (input)
6
14
HRDY
†
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 45. HPI32 Write Timing (HAS Not Used, Tied High)
19
†
HAS
11
10
10
HCNTL[1:0]
HR/W
11
3
18
‡
HSTROBE
HCS
12
13
HD[31:0] (input)
6
14
HRDY
†
‡
For correct operation, strobe the HAS signal only once per HSTROBE active cycle.
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 46. HPI32 Write Timing (HAS Used)
112
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ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
PERIPHERAL COMPONENT INTERCONNECT (PCI) TIMING [C6415 AND C6416 ONLY]
†‡
timing requirements for PCLK (see Figure 47)
NO.
1
MIN
MAX UNIT
§
t
t
t
t
Cycle time, PCLK
30 (or 8P )*
ns
ns
c(PCLK)
2
Pulse duration, PCLK high
Pulse duration, PCLK low
∆v/∆t slew rate, PCLK
11*
11*
1*
w(PCLKH)
w(PCLKL)
sr(PCLK)
3
ns
4
4* V/ns
*This parameter is not production tested.
†
‡
§
For 3.3-V operation, the reference points for the rise and fall transitions are measured at V
P = 1/CPU clock frequency in ns. For example when running parts at 600 MHz, use P = 1.67 ns.
Select the parameter value of 30 ns or 8P, whichever is greater.
MAX and V
IHP
MIN.
ILP
0.4 DV
Peak to Peak for
3.3V signaling
V MIN
DD
1
4
2
PCLK
3
4
Figure 47. PCLK Timing
timing requirements for PCI reset (see Figure 48)
NO.
MIN
MAX UNIT
1
2
t
t
Pulse duration, PRST
1*
ms
w(PRST)
Setup time, PCLK active before PRST high
100*
µs
su(PCLKA-PRSTH)
*This parameter is not production tested.
PCLK
PRST
1
2
Figure 48. PCI Reset (PRST) Timing
113
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ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢋ ꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢇ
ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
PERIPHERAL COMPONENT INTERCONNECT (PCI) TIMING [C6415 AND C6416 ONLY]
(CONTINUED)
timing requirements for PCI inputs (see Figure 49)
NO.
5
MIN
7
MAX UNIT
t
t
Setup time, input valid before PCLK high
Hold time, input valid after PCLK high
ns
ns
su(IV-PCLKH)
6
0
h(IV-PCLKH)
switching characteristics over recommended operating conditions for PCI outputs (see Figure 49)
NO.
1
PARAMETER
MIN
MAX UNIT
t
t
t
t
Delay time, PCLK high to output valid
11
ns
ns
ns
ns
d(PCLKH-OV)
d(PCLKH-OIV)
d(PCLKH-OLZ)
d(PCLKH-OHZ)
2
Delay time, PCLK high to output invalid
Delay time, PCLK high to output low impedance
Delay time, PCLK high to output high impedance
2
3
2*
4
28*
*This parameter is not production tested.
PCLK
PCI Output
PCI Input
1
2
Valid
3
4
Valid
5
6
Figure 49. PCI Input/Output Timing
114
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ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢊ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢊ ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
PERIPHERAL COMPONENT INTERCONNECT (PCI) TIMING [C6415 AND C6416 ONLY]
(CONTINUED)
timing requirements for serial EEPROM interface (see Figure 50)
NO.
8
MIN
50*
0*
MAX UNIT
t
t
Setup time, XSP_DI valid before XSP_CLK high
Hold time, XSP_DI valid after XSP_CLK high
ns
ns
su(DIV-CLKH)
9
h(CLKH-DIV)
*This parameter is not production tested.
†
switching characteristics over recommended operating conditions for serial EEPROM interface
(see Figure 50)
NO.
1
PARAMETER
Pulse duration, XSP_CS low
MIN
TYP
4092P
0
MAX UNIT
t
t
t
t
t
t
t
ns
ns
ns
ns
ns
ns
ns
w(CSL)
2
Delay time, XSP_CLK low to XSP_CS low
Delay time, XSP_CS high to XSP_CLK high
Pulse duration, XSP_CLK high
d(CLKL-CSL)
d(CSH-CLKH)
w(CLKH)
3
2046P
2046P
2046P
2046P
2046P
4
5
Pulse duration, XSP_CLK low
w(CLKL)
6
Output setup time, XSP_DO valid after XSP_CLK high
Output hold time, XSP_DO valid after XSP_CLK high
osu(DOV-CLKH)
oh(CLKH-DOV)
7
†
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
2
1
XSP_CS
3
4
5
XSP_CLK
7
6
XSP_DO
9
8
XSP_DI
Figure 50. PCI Serial EEPROM Interface Timing
115
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ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING
†
timing requirements for McBSP (see Figure 51)
NO.
2
MIN
MAX
UNIT
ns
‡
t
t
Cycle time, CLKR/X
CLKR/X ext
CLKR/X ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
6.67 *
0.5t
c(CKRX)
§
−1 *
3
Pulse duration, CLKR/X high or CLKR/X low
ns
w(CKRX)
c(CKRX)
9
1.3
6
5
6
t
t
t
t
t
t
Setup time, external FSR high before CLKR low
Hold time, external FSR high after CLKR low
Setup time, DR valid before CLKR low
ns
ns
ns
ns
ns
ns
su(FRH-CKRL)
h(CKRL-FRH)
su(DRV-CKRL)
h(CKRL-DRV)
su(FXH-CKXL)
h(CKXL-FXH)
3
8
7
0.9
3
8
Hold time, DR valid after CLKR low
3.1
9
10
11
Setup time, external FSX high before CLKX low
Hold time, external FSX high after CLKX low
1.3
6
3
*This parameter is not production tested.
†
‡
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
Minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and ac timing
requirements.
§
This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.
116
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ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢊ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢊ ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED)
†‡
switching characteristics over recommended operating conditions for McBSP (see Figure 51)
NO.
PARAMETER
MIN
MAX
UNIT
Delay time, CLKS high to CLKR/X high for internal CLKR/X generated
from CLKS input
1
t
1.4
10
ns
d(CKSH-CKRXH)
§
2
3
4
t
t
t
Cycle time, CLKR/X
CLKR/X int
CLKR/X int
CLKR int
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
6.67 *
ns
ns
ns
c(CKRX)
¶
¶
Pulse duration, CLKR/X high or CLKR/X low
Delay time, CLKR high to internal FSR valid
C − 1 *
C + 1 *
w(CKRX)
−2.1
−1.7
1.7
3
3
d(CKRH-FRV)
9
t
t
t
Delay time, CLKX high to internal FSX valid
ns
ns
ns
d(CKXH-FXV)
dis(CKXH-DXHZ)
d(CKXH-DXV)
9
−3.9*
−2.1*
4*
9*
Disable time, DX high impedance following last data bit
from CLKX high
12
13
#
#
−3.9 + D1
−2.1 + D1
4 + D2
9 + D2
Delay time, CLKX high to DX valid
Delay time, FSX high to DX valid
#
#
FSX int
FSX ext
−2.3
1.9
5.6
9
14
t
ns
d(FXH-DXV)
ONLY applies when in data
delay 0 (XDATDLY = 00b) mode
*This parameter is not production tested.
†
‡
§
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
Minimum delay times also represent minimum output hold times.
Minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing
requirements.
C = H or L
¶
S = sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)
=
sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see ¶ footnote above).
Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
#
if DXENA = 1, then D1 = 4P, D2 = 8P
117
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢋ ꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢇ
ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED)
CLKS
1
2
3
3
CLKR
4
4
FSR (int)
5
6
FSR (ext)
7
8
DR
Bit(n-1)
(n-2)
(n-3)
2
3
3
CLKX
9
FSX (int)
11
10
FSX (ext)
FSX (XDATDLY=00b)
13
(n-2)
14
13
12
DX
Bit 0
Bit(n-1)
(n-3)
Figure 51. McBSP Timing
118
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢊ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢊ ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED)
timing requirements for FSR when GSYNC = 1 (see Figure 52)
NO.
1
MIN
4*
MAX
UNIT
ns
t
t
Setup time, FSR high before CLKS high
Hold time, FSR high after CLKS high
su(FRH-CKSH)
2
4*
ns
h(CKSH-FRH)
*This parameter is not production tested.
CLKS
1
2
FSR external
CLKR/X (no need to resync)
CLKR/X (needs resync)
Figure 52. FSR Timing When GSYNC = 1
†‡
timing requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 (see Figure 53)
MASTER
SLAVE
MIN MAX
NO.
UNIT
MIN
12
4
MAX
4
5
t
t
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
2 − 12P
5 + 24P
ns
ns
su(DRV-CKXL)
h(CKXL-DRV)
†
‡
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
119
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢋ ꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢇ
ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
switching characteristics over recommended operating conditions for McBSP as SPI Master or
†‡
Slave: CLKSTP = 10b, CLKXP = 0 (see Figure 53)
§
MASTER
SLAVE
MIN
NO.
PARAMETER
UNIT
MIN MAX
MAX
¶
1
2
3
t
t
t
Hold time, FSX low after CLKX low
T − 2 T + 3
L − 2* L + 3*
ns
ns
ns
h(CKXL-FXL)
d(FXL-CKXH)
d(CKXH-DXV)
#
Delay time, FSX low to CLKX high
Delay time, CLKX high to DX valid
−2
4
12P + 2.8 20P + 17
Disable time, DX high impedance following last data bit
from CLKX low
6
t
L − 2* L + 3*
ns
dis(CKXL-DXHZ)
Disable time, DX high impedance following last data bit
from FSX high
7
8
t
t
4P + 3* 12P + 17*
8P + 1.8 16P + 17
ns
ns
dis(FXH-DXHZ)
Delay time, FSX low to DX valid
d(FXL-DXV)
*This parameter is not production tested.
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)
=
Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP
¶
#
FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock
(CLKX).
CLKX
1
2
8
FSX
7
6
3
DX
DR
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
4
5
Bit 0
(n-2)
(n-3)
(n-4)
Figure 53. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
120
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢊ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢊ ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED)
†‡
timing requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 (see Figure 54)
MASTER
SLAVE
MIN MAX
NO.
UNIT
MIN
12*
4*
MAX
4
5
t
t
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
2 − 12P*
5 + 24P*
ns
ns
su(DRV-CKXH)
h(CKXH-DRV)
*This parameter is not production tested.
†
‡
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI Master or
†‡
Slave: CLKSTP = 11b, CLKXP = 0 (see Figure 54)
§
MASTER
SLAVE
MIN
NO.
PARAMETER
UNIT
MIN MAX
MAX
¶
1
2
3
t
t
t
Hold time, FSX low after CLKX low
L − 2* L + 3*
T − 2* T + 3*
ns
ns
ns
h(CKXL-FXL)
d(FXL-CKXH)
d(CKXL-DXV)
#
Delay time, FSX low to CLKX high
Delay time, CLKX low to DX valid
−2*
4* 12P + 4* 20P + 17*
Disable time, DX high impedance following last data bit
from CLKX low
6
t
−2*
4* 12P + 3* 20P + 17*
ns
ns
dis(CKXL-DXHZ)
7
t
Delay time, FSX low to DX valid
H − 2* H + 4*
8P + 2* 16P + 17*
d(FXL-DXV)
*This parameter is not production tested.
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)
=
Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP
¶
#
FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock
(CLKX).
CLKX
1
2
7
FSX
DX
6
3
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-3)
(n-4)
4
5
DR
Bit 0
(n-2)
(n-4)
Figure 54. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
121
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢋ ꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢇ
ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED)
†‡
timing requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 (see Figure 55)
MASTER
SLAVE
MIN MAX
NO.
UNIT
MIN
12*
4*
MAX
4
5
t
t
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
2 − 12P*
5 + 24P*
ns
ns
su(DRV-CKXH)
h(CKXH-DRV)
*This parameter is not production tested.
†
‡
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI Master or
†‡
Slave: CLKSTP = 10b, CLKXP = 1 (see Figure 55)
§
MASTER
SLAVE
MIN
NO.
PARAMETER
UNIT
MIN MAX
MAX
¶
1
2
3
t
t
t
Hold time, FSX low after CLKX high
T − 2* T + 3*
H − 2* H + 3*
ns
ns
ns
h(CKXH-FXL)
d(FXL-CKXL)
d(CKXL-DXV)
#
Delay time, FSX low to CLKX low
Delay time, CLKX low to DX valid
−2*
4* 12P + 4* 20P + 17*
Disable time, DX high impedance following last data bit
from CLKX high
6
t
H − 2* H + 3*
ns
dis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit
from FSX high
7
8
t
t
4P + 3* 12P + 17*
8P + 2* 16P + 17*
ns
ns
dis(FXH-DXHZ)
Delay time, FSX low to DX valid
d(FXL-DXV)
*This parameter is not production tested.
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)
=
Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP
¶
#
FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock
(CLKX).
CLKX
1
2
8
FSX
7
6
3
DX
DR
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
4
5
Bit 0
(n-2)
(n-3)
(n-4)
Figure 55. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
122
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢊ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢊ ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED)
†‡
timing requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 (see Figure 56)
MASTER
SLAVE
MIN MAX
NO.
UNIT
MIN
12*
4*
MAX
4
5
t
t
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
2 − 12P*
5 + 24P*
ns
ns
su(DRV-CKXH)
h(CKXH-DRV)
*This parameter is not production tested.
†
‡
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI Master or
†‡
Slave: CLKSTP = 11b, CLKXP = 1 (see Figure 56)
§
MASTER
SLAVE
MIN
NO.
PARAMETER
UNIT
MIN MAX
MAX
¶
1
2
3
t
t
t
Hold time, FSX low after CLKX high
H − 2* H + 3*
T − 2* T + 1*
ns
ns
ns
h(CKXH-FXL)
d(FXL-CKXL)
d(CKXH-DXV)
#
Delay time, FSX low to CLKX low
Delay time, CLKX high to DX valid
−2*
4* 12P + 4* 20P + 17*
Disable time, DX high impedance following last data bit
from CLKX high
6
t
−2*
4* 12P + 3* 20P + 17*
ns
ns
dis(CKXH-DXHZ)
7
t
Delay time, FSX low to DX valid
L − 2* L + 4*
8P + 2* 16P + 17*
d(FXL-DXV)
*This parameter is not production tested.
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)
=
Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP
¶
#
FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock
(CLKX).
CLKX
1
2
FSX
DX
7
6
3
Bit 0
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
4
5
DR
(n-2)
(n-3)
(n-4)
Figure 56. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
123
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ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢋ ꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢇ
ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
UTOPIA SLAVE TIMING [C6415 AND C6416 ONLY]
†
timing requirements for UXCLK (see Figure 57)
NO.
1
MIN
MAX
UNIT
ns
t
t
t
t
Cycle time, UXCLK
20*
c(UXCK)
w(UXCKH)
w(UXCKL)
t(UXCK)
2
Pulse duration, UXCLK high
Pulse duration, UXCLK low
Transition time, UXCLK
0.4t
0.4t
*
*
0.6t
*
*
ns
c(UXCK)
c(UXCK)
3
0.6t
ns
c(UXCK)
c(UXCK)
2*
4
ns
*This parameter is not production tested.
†
The reference points for the rise and fall transitions are measured at V MAX and V MIN.
IL
IH
1
4
2
UXCLK
3
4
Figure 57. UXCLK Timing
†
timing requirements for URCLK (see Figure 58)
NO.
MIN
MAX
UNIT
ns
1
2
3
4
t
t
t
t
Cycle time, URCLK
20*
c(URCK)
w(URCKH)
w(URCKL)
t(URCK)
Pulse duration, URCLK high
Pulse duration, URCLK low
Transition time, URCLK
0.4t
0.4t
*
*
0.6t
0.6t
*
*
ns
c(URCK)
c(URCK)
ns
c(URCK)
c(URCK)
2*
ns
*This parameter is not production tested.
†
The reference points for the rise and fall transitions are measured at V MAX and V MIN.
IL
IH
1
4
2
URCLK
3
4
Figure 58. URCLK Timing
124
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ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢊ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢊ ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
UTOPIA SLAVE TIMING [C6415 AND C6416 ONLY] (CONTINUED)
timing requirements for UTOPIA Slave transmit (see Figure 59)
NO.
2
MIN
4
MAX
UNIT
ns
t
t
t
t
Setup time, UXADDR valid before UXCLK high
Hold time, UXADDR valid after UXCLK high
Setup time, UXENB low before UXCLK high
Hold time, UXENB low after UXCLK high
su(UXAV-UXCH)
3
1
ns
h(UXCH-UXAV)
8
4
ns
su(UXENBL-UXCH)
h(UXCH-UXENBL)
9
1
ns
switching characteristics over recommended operating conditions for UTOPIA Slave transmit
(see Figure 59)
NO.
1
PARAMETER
MIN
3
MAX
12
UNIT
ns
t
t
t
t
t
t
Delay time, UXCLK high to UXDATA valid
Delay time, UXCLK high to UXCLAV driven active value
Delay time, UXCLK high to UXCLAV driven inactive low
Delay time, UXCLK high to UXCLAV going Hi-Z
Pulse duration (low), UXCLAV low to UXCLAV Hi-Z
Delay time, UXCLK high to UXSOC valid
d(UXCH-UXDV)
4
3
12
ns
d(UXCH-UXCLAV)
d(UXCH-UXCLAVL)
d(UXCH-UXCLAVHZ)
w(UXCLAVL-UXCLAVHZ)
d(UXCH-UXSV)
5
3*
9*
3*
3
12*
ns
6
18.5*
ns
7
ns
10
12
ns
*This parameter is not production tested.
UXCLK
1
3
P45
P46
N
P47
0x1F
N
P48
H1
UXDATA[7:0]
UXADDR[4:0]
2
0 x1F
N
0x1F
N + 1
7
0x1F
6
4
5
N
8
UXCLAV
UXENB
UXSOC
9
10
†
The UTOPIA Slave module has signals that are middle-level signals indicating a high-impedance state (i.e., the UXCLAV and
UXSOC signals).
†
Figure 59. UTOPIA Slave Transmit Timing
125
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢋ ꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢇ
ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
UTOPIA SLAVE TIMING [C6415 AND C6416 ONLY] (CONTINUED)
timing requirements for UTOPIA Slave receive (see Figure 60)
NO.
1
MIN
4
MAX
UNIT
ns
t
t
t
t
Setup time, URDATA valid before URCLK high
Hold time, URDATA valid after URCLK high
Setup time, URADDR valid before URCLK high
Hold time, URADDR valid after URCLK high
su(URDV-URCH)
h(URCH-URDV)
su(URAV-URCH)
h(URCH-URAV)
2
1
ns
3
4
ns
4
1
ns
9
t
t
t
t
Setup time, URENB low before URCLK high
Hold time, URENB low after URCLK high
Setup time, URSOC high before URCLK high
Hold time, URSOC high after URCLK high
4
1
4
1
ns
ns
ns
ns
su(URENBL-URCH)
h(URCH-URENBL)
su(URSH-URCH)
h(URCH-URSH)
10
11
12
switching characteristics over recommended operating conditions for UTOPIA Slave receive
(see Figure 60)
NO.
PARAMETER
MIN
MAX
UNIT
5
t
t
t
t
Delay time, URCLK high to URCLAV driven active value
3
12
ns
d(URCH-URCLAV)
6
7
8
Delay time, URCLK high to URCLAV driven inactive low
Delay time, URCLK high to URCLAV going Hi-Z
Pulse duration (low), URCLAV low to URCLAV Hi-Z
3*
9*
3*
12*
ns
ns
ns
d(URCH-URCLAVL)
d(URCH-URCLAVHZ)
w(URCLAVL-URCLAVHZ)
18.5*
*This parameter is not production tested.
URCLK
2
1
URDATA[7:0]
URADDR[4:0]
P48
0x1F
N
H1
H2
H3
4
5
3
N
N+1
0x1F
N+2
8
0x1F
7
6
URCLAV
URENB
URSOC
N+1
N+2
10
9
11
12
†
The UTOPIA Slave module has signals that are middle-level signals indicating a high-impedance state (i.e., the URCLAV and
URSOC signals).
†
Figure 60. UTOPIA Slave Receive Timing
126
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢊ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢊ ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
TIMER TIMING
†
timing requirements for timer inputs (see Figure 61)
NO.
MIN
8P*
8P*
MAX
UNIT
ns
1
2
t
t
Pulse duration, TINP high
Pulse duration, TINP low
w(TINPH)
ns
w(TINPL)
*This parameter is not production tested.
†
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
†
switching characteristics over recommended operating conditions for timer outputs
(see Figure 61)
NO.
3
PARAMETER
MIN
8P−3*
8P−3*
MAX
UNIT
ns
t
t
Pulse duration, TOUT high
Pulse duration, TOUT low
w(TOUTH)
4
ns
w(TOUTL)
*This parameter is not production tested.
†
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
2
1
TINPx
4
3
TOUTx
Figure 61. Timer Timing
127
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢋ ꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢇ
ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORT TIMING
†‡
timing requirements for GPIO inputs (see Figure 62)
NO.
1
MIN
8P*
8P*
MAX
UNIT
ns
t
t
Pulse duration, GPIx high
Pulse duration, GPIx low
w(GPIH)
2
ns
w(GPIL)
*This parameter is not production tested.
†
‡
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
The pulse width given is sufficient to generate a CPU interrupt or an EDMA event. However, if a user wants to have the DSP recognize the GPIx
changes through software polling of the GPIO register, the GPIx duration must be extended to at least 12P to allow the DSP enough time to access
the GPIO register through the CFGBUS.
†
switching characteristics over recommended operating conditions for GPIO outputs
(see Figure 62)
NO.
3
PARAMETER
MIN
32P*
32P*
MAX
UNIT
ns
t
t
Pulse duration, GPOx high
Pulse duration, GPOx low
w(GPOH)
4
ns
w(GPOL)
*This parameter is not production tested.
†
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
2
1
GPIx
4
3
GPOx
Figure 62. GPIO Port Timing
128
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈ ꢊ ꢀꢁ ꢂ ꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢋ ꢊ ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢇ
ꢌ ꢍꢎ ꢏꢐꢑꢒꢓ ꢍ ꢔꢕ ꢐꢍ ꢖꢍ ꢕꢗꢘ ꢀꢍ ꢖ ꢔꢗꢘ ꢒꢙ ꢓ ꢆꢏ ꢀ ꢀꢓ ꢙ ꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
JTAG TEST-PORT TIMING
timing requirements for JTAG test port (see Figure 63)
NO.
MIN
35*
10*
9*
MAX
UNIT
ns
1
3
4
t
t
t
Cycle time, TCK
c(TCK)
Setup time, TDI/TMS/TRST valid before TCK high
Hold time, TDI/TMS/TRST valid after TCK high
ns
su(TDIV-TCKH)
h(TCKH-TDIV)
ns
*This parameter is not production tested.
switching characteristics over recommended operating conditions for JTAG test port
(see Figure 63)
NO.
PARAMETER
MIN
MAX
UNIT
2
t
Delay time, TCK low to TDO valid
–3*
18*
ns
d(TCKL-TDOV)
*This parameter is not production tested.
1
TCK
TDO
2
2
4
3
TDI/TMS/TRST
Figure 63. JTAG Test-Port Timing
129
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇ ꢈ ꢉꢈꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇ ꢈꢉ ꢋ ꢊ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢇ
ꢌ ꢍ ꢎꢏ ꢐꢑꢒ ꢓꢍ ꢔ ꢕ ꢐꢍ ꢖ ꢍ ꢕꢗꢘ ꢀ ꢍ ꢖꢔ ꢗꢘ ꢒ ꢙꢓ ꢆꢏ ꢀꢀꢓ ꢙꢀ
SGUS050A − JANUARY 2004 − REVISED MARCH 2004
MECHANICAL DATA
GAD (S-CPGA-P570)
CERAMIC PIN GRID ARRAY
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Flip chip application only
D. This package is hermetically sealed with a metal lid.
thermal resistance characteristics (S-CPGA package)
NO
°C/W
20.96
16.5
10.9
7.69
9
1
2
3
4
5
6
RΘ
RΘ
RΘ
RΘ
RΘ
RΘ
Junction-to-free air (Low K JEDEC PCB)
JA
JA
JC
JC
JB
JB
Junction-to-free air (High K JEDEC PCB)
Junction-to-case (High K JEDEC PCB with heat sink on lid)
Junction-to-case (High K JEDEC PCB with heat sink on body)
Junction-to-board (High K JEDEC PCB)
Junction-to-board (High K JEDEC PCB with thermal compound on top of the die)
2.93
130
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
5962-0324501QXA
SM320C6415DGADW60
SMJ320C6415DGADW60
ACTIVE
ACTIVE
ACTIVE
FCPGA
FCPGA
FCPGA
GAD
570
570
570
1
8
1
TBD
TBD
TBD
Call TI
Call TI
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
GAD
GAD
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
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Use of such information may require a license from a third party under the patents or other intellectual property
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Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
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Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
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Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
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Amplifiers
amplifier.ti.com
www.ti.com/audio
Data Converters
dataconverter.ti.com
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www.ti.com/automotive
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dsp.ti.com
Broadband
Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
Logic
interface.ti.com
logic.ti.com
Power Mgmt
Microcontrollers
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
Telephony
Video & Imaging
Wireless
www.ti.com/wireless
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Post Office Box 655303 Dallas, Texas 75265
Copyright 2005, Texas Instruments Incorporated
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