SMJ44C256-12FQ [TI]
SMJ44C256-12FQ;
| 型号： | SMJ44C256-12FQ |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SMJ44C256-12FQ |
| 文件： | 总21页 (文件大小：515K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SMJ44C256
262144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY
SGMS034C – MAY 1989 – REVISED JUNE 1995
Organization . . . 262144 Words × 4 Bits
3-State Unlatched Output
Low Power Dissipation
Single 5-V Supply (10% Tolerance)
Processed to MIL-STD-833, Class B
Packaging Offered:
Performance Ranges:
– 20-Pin 300-Mil Ceramic DIP (JD Suffix)
– 20-Lead Ceramic Surface-Mount Package
(HJ Suffix)
– 20-Pin Ceramic Flat Pack (HK Suffix)
– 20-Terminal Leadless Ceramic
Surface-Mount Package (FQ Suffix)
– 20-Terminal Low-Profile Leadless
Ceramic Surface-Mount Package
(HL Suffix)
ACCESS ACCESS ACCESS READ
TIME
TIME
TIME
OR
t
t
t
a(CA)
WRITE
CYCLE
(MIN)
a(R)
a(C)
(t
RAC
)
(t
CAC
)
(t
CAA
)
(MAX)
(MAX)
(MAX)
SMJ44C256-80 80 ns
SMJ44C256-10 100 ns
SMJ44C256-12 120 ns
SMJ44C256-15 150 ns
20 ns
25 ns
30 ns
40 ns
40 ns
45 ns
55 ns
70 ns
150 ns
190 ns
220 ns
260 ns
– 20-Pin Ceramic Zig Zag In-Line Package
(SV Suffix)
Enhanced Page Mode Operation With
CAS-Before-RAS (CBR) Refresh
Operating Free-Air Temperature Range
Long Refresh Period
– 55°C to 125°C
512-Cycle Refresh in 8 ms (Max)
All Inputs and Clocks are TTL Compatible
JD PACKAGE
(TOP VIEW)
HJ PACKAGE
(TOP VIEW)
PIN NOMENCLATURE
A0–A8
CAS
Address Inputs
Column Address Strobe
Data In/Data Out
Data Output Enable
Row Address Strobe
Test Function
DQ1
DQ2
W
RAS
TF
1
2
3
4
5
26
25
24
23
22
V
SS
DQ1
DQ2
W
RAS
TF
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
SS
DQ1–DQ4
G
DQ4
DQ3
CAS
G
DQ4
DQ3
CAS
G
A8
A7
A6
A5
A4
RAS
TF
V
V
W
5-V Supply
Ground
Write Enable
CC
SS
A0
A1
A2
A3
9
18
17
16
15
14
A8
A7
A6
A5
A4
10
11
12
13
FQ/HL PACKAGES
(TOP VIEW)
SV PACKAGE
(TOP VIEW)
V
CC
V
CC
DQ1
DQ2
W
RAS
TF
1
2
3
4
5
26
25
24
23
22
V
SS
G
DQ3
1
2
4
6
8
CAS
DQ4
DQ1
W
DQ4
DQ3
CAS
G
HK PACKAGE
(TOP VIEW)
3
V
5
SS
DQ2
RAS
A0
7
V
DQ1
DQ2
W
RAS
TF
A0
A1
A2
A3
1
20
19
18
17
16
15
14
13
12
11
SS
9
10 TF
12 A1
14 A3
16 A4
18 A6
20 A8
DQ4
DQ3
CAS
G
A8
A7
A6
A5
A4
2
11
13
15
17
19
3
9
A0
A1
A2
A3
18
17
16
15
14
A8
A7
A6
A5
A4
A2
10
11
12
13
4
V
CC
A5
A7
5
6
V
7
CC
8
9
V
10
CC
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ44C256
262144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY
SGMS034C – MAY 1989 – REVISED JUNE 1995
description
The SMJ44C256 series is a set of high-speed, 1048576-bit dynamic random access memories (DRAMs),
organized as 262 144 words of four bits each. These devices employ EPIC (Enhanced Performance
Implanted CMOS) technology for high performance, reliability, and low power.
These devices feature maximum RAS access times of 80 ns, 100 ns,120 ns, and 150 ns. Maximum power
dissipation is as low as 305 mW operating and 16.5 mW standby on 150-ns devices.
TheEPICtechnologypermitsoperationfromasingle5-Vsupply, reducingsystempowersupplyanddecoupling
requirements, and easing board layout. I
–1 V can be tolerated, minimizing system noise considerations.
peaks are 140 mA typical, and an input voltage undershoot of
CC
All inputs and outputs, including clocks, are compatible with Series 54/174 TTL. All addresses and data-in lines
are latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
The SMJ44C256 is offered in 20-pin ceramic dual-in-line packages (JD suffix) and 20/26-terminal ceramic
leadless carriers (FQ/HL suffixes), 20/26-pin leaded carrier (HJ suffix), a 20-pin flatpack (HK suffix), and a
20-pin ceramic zig-zag in-line package (SV suffix). They are specified for operation from –55°C to125°C.
†
logic symbol
RAM 256K × 4
6
7
A0
A1
A2
A3
A4
A5
A6
A7
A8
20D9/21D0
8
9
11
12
13
14
15
0
A
262 143
20D17/21D8
C20[ROW]
G23/[REFRESH ROW]
24[PWR DWN]
C21/[COLUMN]
G24
4
RAS
CAS
17
&
23C22
24,25EN
3
W
G
23,21D
G25
16
1
DQ1
A,22D
26
A,Z26
2
18
19
DQ2
DQ3
DQ4
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the JD package.
EPIC is a trademark of Texas Instruments Incorporated.
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ44C256
262144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY
SGMS034C – MAY 1989 – REVISED JUNE 1995
functional block diagram
RAS CAS
W
G
Timing and Control
Row
Address
Buffers
(9)
256K
Array
Row
Decode
256K
Array
A0
A1
A2
A3
A4
A5
A6
A7
A8
Sense Amplifiers
Data
In
4
Column
Address
Buffers
(9)
Reg
I/O
Buffers
4 of 8
Column Decode
Selection
Data
Out
Reg
4
4
Sense Amplifiers
256K
Array
Row
Decode
256K
Array
DQ1–DQ4
operation
enhanced page mode
Page-mode operation allows faster memory access by keeping the same row address while selecting random
column addresses. The time for row-address setup and hold and address multiplex is eliminated. The maximum
number of columns that can be accessed is determined by the maximum RAS low time and the CAS page cycle
time used. With minimum CAS page cycle time, all 512 columns specified by column addresses A0 through A8
can be accessed without intervening RAS cycles.
Unlike conventional page mode DRAMs, the column-address buffers in this device are activated on the falling
edge of RAS. The buffers act as transparent or flow-through latches while CAS is high. The column address
latches to the first CAS falling edge. This feature allows the SMJ44C256 to operate at a wider data bandwidth
than conventional page mode parts, since data retrieval begins as soon as column address is valid rather than
when CAS goes low. This performance improvement is referred to as enhanced page mode. Valid column
address can be presented immediately after t
(row address hold time) has been satisfied, usually well in
h(RA)
advance of the falling edge of CAS. In this case, data is obtained after t
maximum (access time from CAS
a(C)
low), if t
maximum (access time from column address) has been satisfied. In the event that column
a(CA)
addresses for the next page cycle are valid at the time CAS goes high, access time for the next cycle is
determined by the later occurrence of t or t (access time from rising edge of CAS).
a(C)
a(CP)
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ44C256
262144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY
SGMS034C – MAY 1989 – REVISED JUNE 1995
address (A0 through A8)
Eighteen address bits are required to decode 1 of 262144 storage cell locations. Nine row-address bits are set
up on pins A0 through A8 and latched onto the chip by RAS. Nine column-address bits are set up on pins A0
through A8 and latched onto the chip by CAS. All addresses must be stable on or before the falling edges of
RAS and CAS. RAS is similar to a chip enable in that it activates the sense amplifiers as well as the row decoder.
In the SMJ44C256, CAS is used as a chip select, activating the output buffer as well as latching the address
bits into the column-address buffers.
write enable (W)
The read or write mode is selected through W. A logic high on the W input selects the read mode and a logic
low selects the write mode. The write-enable terminal can be driven from the standard TTL circuits without a
pullup resistor. The data input is disabled when the read mode is selected. When W goes low prior to CAS
(early-write), data out remains in the high-impedance state for the entire cycle, permitting a write operation with
G grounded.
data in (DQ1–DQ4)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling edge
of CAS or W strobes data into the on-chip data latch. In an early-write cycle, W is brought low prior to CAS and
the data is strobed in by CAS with setup and hold times referenced to this signal. In a delayed-write or
read-modify-write cycle, CAS is already low, the data is strobed in by W with setup and hold times referenced
to this signal. In a delayed-write or read-modify-write cycle, G must be high to bring the output buffers to the
high-impedance state prior to applying data to the I/O lines.
data out (DQ1–DQ4)
The 3-state output buffer provides direct TTL compatibility (no pullup resistor required) with a fanout of two
Series 54 TTL loads. Data out is the same polarity as data in. The output is in the high-impedance (floating) state
until CAS and G are brought low. In a read cycle the output becomes valid after the access time interval t
a(C)
thatbeginswiththenegativetransitionofCASaslongast
andt
aresatisfied. Theoutputbecomesvalid
a(R)
a(CA)
after the access time has elapsed and remains valid while CAS and G are low. CAS or G going high returns it
toahigh-impedancestate.ThisisaccomplishedbybringingGhighpriortoapplyingdata,thussatisfyingt
.
d(GHD)
output enable (G)
G controls the impedance of the output buffers. When G is high, the buffers remain in the high-impedance state.
Bringing G low during a normal cycle activates the output buffers, putting them in the low-impedance state. It
is necessary for both G and CAS to be brought low for the output buffers, to go into the low-impedance state.
Once in the low-impedance state, they remain in the low-impedance state until either G or CAS is brought high.
refresh
A refresh operation must be performed at least once every 8 ms to retain data. This can be achieved by strobing
each of the 512 rows (A0–A8). A normal read or write cycle refreshes all bits in each row that is selected. A
RAS-only operation can be used by holding CAS at the high (inactive) level, conserving power as the output
buffer remains in the high-impedance state. Externally generated addresses must be used for a RAS-only
refresh. Hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished
by holding CAS at V after a read operation and cycling RAS after a specified precharge period, similar to a
IL
RAS-only refresh cycle.
CBR refresh
CBR refresh is utilized by bringing CAS low earlier than RAS [see parameter t
] and holding it low after
d(CLRL)R
RAS falls [see parameter t
]. For successive CBR refresh cycles, CAS can remain low while cycling
d(RLCH)R
RAS. The external address is ignored and the refresh address is generated internally. The external address is
also ignored during the hidden refresh option.
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ44C256
262144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY
SGMS034C – MAY 1989 – REVISED JUNE 1995
power up
To achieve proper device operation, an initial pause of 200 µs followed by a minimum of eight initialization
(refresh) cycles is required after power-up to the full V level.
CC
test function pin
During normal device operation the TF pin must either be disconnected or biased at a voltage less than or equal
to V
.
CC
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 7 V
CC
Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Operating free-air temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to V
.
SS
recommended operating conditions
MIN NOM
MAX
UNIT
V
V
V
V
T
Supply voltage
4.5
5
0
5.5
V
V
V
V
CC
SS
IH
Supply voltage
High-level input voltage
Low-level input voltage (see Note 2)
Operating free-air temperature
2.4
– 1
6.5
0.8
IL
– 55
°C
°C
A
T
C
Case temperature
125
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ44C256
262144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY
SGMS034C – MAY 1989 – REVISED JUNE 1995
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
’44C256-80
’44C256-10
’44C256-12
’44C256-15
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
High-level output
voltage
V
V
I
I
= – 5 mA
= 4.2 mA
2.4
2.4
2.4
2.4
V
V
OH
OH
Low-level output
voltage
0.4
± 10
± 10
0.4
± 10
± 10
0.4
± 10
± 10
0.4
± 10
± 10
OL
OL
V
= 5 V,
V = 0 V to 6.5 V,
I
Input current
(leakage)
CC
All other pins = 0 V to V
I
I
µA
µA
CC
= 0 to V
V
= 5.5 V,
V
,
CC
Output current
(leakage)
CC
CAS high
O
I
O
Read- or
write-cycle
current
V
= 5.5 V,
CC
I
80
3
70
3
60
3
55
3
mA
mA
CC1
t
= minimum
c(rdW)
After 1 memory cycle,
RAS and CAS high,
I
Standby current
CC2
V
IH
= 2.4 V
V
= 5.5 V,
CC
Average refresh
current
(RAS only, or
CBR)
t
= minimum,
c(rdW)
I
I
RAS cycling,
75
50
65
45
55
35
50
30
mA
mA
CC3
CAS high (RAS only),
RAS low after CAS low (CBR)
V
= 5.5 V, = minimum,
t
Average page
current
CC
RAS low,
c(P)
CAS cycling
CC4
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 3)
HL/JD/FQ
MIN MAX
HJ
MIN
HK
MIN
SV
MIN
PARAMETER
UNIT
MAX
MAX
8
MAX
C
C
C
C
Input capacitance, address inputs
Input capacitance, strobe inputs
Input capacitance, write-enable input
Output capacitance
6
7
7
7
7
7
7
9
9
8
7
8
pF
pF
pF
pF
i(A)
i(RC)
i(W)
O
8
7
10
NOTE 3: Capacitance is sampled only at initial design and after any major change. Samples are tested at 0 V and 25°C with a 1-MHz signal
applied to the pin under test. All other pins are open.
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ44C256
262144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY
SGMS034C – MAY 1989 – REVISED JUNE 1995
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Figure 1)
’44C256-80
MIN MAX
’44C256-10
MIN MAX
’44C256-12
MIN MAX
’44C256-15
MIN MAX
ALT.
SYMBOL
PARAMETER
UNIT
t
t
t
t
Access time from CAS low
Access time from column-address
Access time from RAS low
Access time from G low
t
20
40
80
20
25
45
30
55
40
70
ns
ns
ns
ns
a(C)
CAC
t
a(CA)
a(RL)
a(G)
AA
t
100
25
120
30
150
40
RAC
GAC
t
Access time from CAS high column
precharge
t
t
t
t
40
20
20
50
25
25
60
30
30
75
35
35
ns
ns
ns
a(CP)
CPA
Output disable time after CAS high
(see Note 4)
t
dis(CH)
OFF
Output disable time after G high
(see Note 4)
t
dis(G)
GOFF
NOTE 4:
t
and t are specified when the output is no longer driven. The outputs are disabled by bringing either G or CAS high.
dis(G)
dis(CH)
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Note 5)
’44C256-80
’44C256-10
’44C256-12
’44C256-15
ALT.
SYMBOL
PARAMETER
UNIT
MIN
150
150
MAX
MIN
190
190
MAX
MIN
220
220
MAX
MIN
260
260
MAX
t
t
Cycle time, read (see Note 6)
Cycle time, write
t
ns
ns
c(rd)
RC
t
c(W)
WC
Cycle time,read-write/read-
modify-write
t
t
t
225
50
270
55
305
65
355
80
ns
ns
c(rdW)
RWC
Cycle time, page-mode read
or write (see Note 7)
t
c(P)
PC
Cycle time, page-mode read-
modify-write
t
t
t
t
115
10
135
10
150
15
175
25
ns
ns
ns
c(PM)
w(CH)
w(CL)
PRWC
Pulse duration, CAS high
t
CP
Pulse duration, CAS low
(see Note 8)
t
20
10 000
10 000
25
10 000
10 000
30
10 000
10 000
40
10 000
10 000
CAS
Pulse duration, RAS high
(precharge)
t
t
60
80
80
90
100
150
ns
ns
w(RH)
w(RL)
RP
Pulse duration,
nonpage mode RAS low
(see Note 9)
t
t
100
120
RAS
Pulse duration,
page mode RAS low
(see Note 9)
t
t
80 100 000
100 100 000
120 100 000
150 100 000
ns
w(RL)P
RASP
t
t
Pulse duration, write low
t
15
5
15
5
20
5
25
5
ns
ns
w(WL)
WP
Setup time, column address
before CAS low
t
su(CA)
ASC
NOTES: 5. Timing measurements in this table are referenced to V max and V min.
IL IH
6. All cycle times assume t = 5 ns.
t
7. To assure t
min, t
should be ≥ t
.
w(CH)
c(P)
su(CA)
8. In a read-modify-write cycle, t
and t
must be observed. Depending on the user’s transition times, this can require
must be observed. Depending on the user’s transition times, this can require
d(CLWL)
w(CL)
su(WCH)
and t
su(WRH)
additional CAS low time [t
9. In a read-modify-write cycle, t
].
d(RLWL)
].
additional RAS low time [t
w(RL)
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ44C256
262144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY
SGMS034C – MAY 1989 – REVISED JUNE 1995
timing requirements over recommended ranges of supply voltage and operating temperature
(continued) (see Note 5)
’44C256-80
’44C256-10
’44C256-12
’44C256-15
ALT.
SYMBOL
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Setup time, row address
before RAS low
t
t
0
0
0
0
ns
su(RA)
ASR
Setup time, data before
W low (see Note 10)
t
t
t
t
0
0
0
0
0
0
0
0
0
0
0
0
ns
ns
ns
su(D)
DS
Setup time, W high before CAS low
t
RCS
su(rd)
Setup time, W low before CAS low
(see Note 11)
t
su(WCL)
WCS
t
t
Setup time, W low before CAS high
Setup time, W low before RAS high
t
t
20
20
25
25
30
30
40
40
ns
ns
su(WCH)
CWL
su(WRH)
RWL
Hold time, column address after CAS
low (see Note 10)
t
t
t
t
t
15
15
60
15
20
15
70
20
20
15
80
25
25
15
ns
ns
ns
ns
h(CA)
h(RA)
h(RLCA)
h(D)
CAH
RAH
Hold time, row address after RAS
low
t
Hold time, column address after RAS
low (see Note 12)
t
100
30
AR
Hold time, data after CAS low
(see Note 10)
t
DH
Hold time, data after RAS low
(see Note 12)
t
t
t
t
60
20
0
70
25
0
85
30
0
110
40
0
ns
ns
ns
h(RLD)
DHR
Hold time, G high after W low
t
GH
h(WLGL)
h(CHrd)
Hold time, W high after CAS high
(see Note 14)
t
t
RCH
Hold time, W high after RAS high
(see Note 14)
t
t
t
10
15
65
10
20
75
10
25
90
10
30
ns
ns
ns
h(RHrd)
h(CLW)
h(RLW)
RRH
Hold time, W low after CAS low
(see Note 11)
t
WCH
WCR
Hold time, W low after RAS low
(see Note 12)
t
105
t
t
t
Delay time, RAS low to CAS high
Delay time, CAS high to RAS low
Delay time, CAS low to RAS high
t
80
0
100
0
120
0
150
0
ns
ns
ns
d(RLCH)
d(CHRL)
d(CLRH)
CSH
CRP
RSH
t
t
20
25
30
40
Delay time, CAS low to W low
(see Note 15)
t
t
t
t
60
30
20
70
30
20
80
30
20
90
30
25
ns
ns
ns
d(CLWL)
d(RLCL)
d(RLCA)
CWD
Delay time, RAS low to CAS low
(see Note 13)
t
60
40
75
55
90
65
110
80
RCD
Delay time, RAS low to column
address (see Note 13)
t
RAD
NOTES: 5. Timing measurements in this table are referenced to V max and V min.
IL
IH
10. Referenced to the later of CAS or W in write operations.
11. Early-write operation only
12. The minimum value is measured when t
is set to t min as a reference.
d(RLCL)
d(RLCL)
13. Maximum value specified only to assure access time.
14. Either t or t must be satisfied for a read cycle.
h(RHrd)
h(CHrd)
15. Read-modify-write operation only
8
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SMJ44C256
262144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY
SGMS034C – MAY 1989 – REVISED JUNE 1995
timing requirements over recommended ranges of supply voltage and operating temperature
(continued) (see Note 5)
’44C256-80
’44C256-10
’44C256-12
’44C256-15
ALT.
SYMBOL
PARAMETER
UNIT
ns
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Delay time, column address to
RAS high
t
t
t
t
t
40
45
55
70
d(CARH)
d(CACH)
d(RLWL)
d(CAWL)
RAL
CAL
Delay time, column address to
CAS high
t
40
130
80
45
150
95
55
170
105
70
200
120
ns
Delay time, RAS low to W low
(see Note 15)
t
ns
RWD
Delay time, column address to W
low (see Note 15)
t
ns
AWD
Delay time, G high before data at
DQ
t
t
t
t
20
20
20
25
25
25
30
30
25
40
40
30
ns
ns
ns
d(GHD)
GDD
Delay time, G low to RAS high
t
d(GLRH)
d(RLCH)R
GSR
Delay time, RAS low to CAS high
(see Note 16)
t
CHR
Delay time, CAS low to RAS low
(see Note 16)
t
t
t
t
10
0
10
0
10
0
15
0
ns
ns
d(CLRL)R
CSR
Delay time, RAS high to CAS low
(see Note 16)
d(RHCL)R
RPC
t
t
Refresh time interval
t
8
8
8
8
ms
ns
rf
REF
Transition time (see Note 17)
t
T
t
NOTES: 5. Timing measurements in this table are referenced to V max and V min.
IL IH
15. Read-modify-write operation only
16. CBR refresh only
17. System transition times (rise and fall) are to be a minimum of 3 ns and a maximum of 50 ns.
PARAMETER MEASUREMENT INFORMATION
1.31 V
5 V
R
= 218 Ω
R
R
= 828 Ω
= 295 Ω
L
1
2
Output Under Test
Output Under Test
C
= 80 pF
L
(See Note A)
C
= 80 pF
L
(See Note A)
(a) LOAD CIRCUIT
(b) ALTERNATE LOAD CIRCUIT
NOTE A: C includes probe and fixture capacitance.
L
Figure 1. Load Circuits for Timing Parameters
9
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SMJ44C256
262144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY
SGMS034C – MAY 1989 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
tc(rd)
c(rd)
t
w(RL)
RAS
CAS
t
w(RH)
t
d(CLRH)
t
d(RLCL)
t
d(CHRL)
t
d(RLCH)
t
t
t
w(CL)
t
d(RLCA)
t
w(CH)
t
su(CA)
t
h(RA)
t
d(CACH)
t
t
su(RA)
d(CARH)
t
h(RLCA)
A0–A8
Row
Column
Don’t Care
t
h(RHrd)
t
h(CA)
t
t
h(CHrd)
su(rd)
W
Don’t Care
Don’t Care
t
a(C)
t
a(CA)
t
dis(CH)
See Note A
DQ1–DQ4
Hi-Z
Valid
t
a(RL)
t
dis(G)
t
a(G)
t
d(GLRH)
G
Don’t Care
Don’t Care
NOTE B: Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 2. Read-Cycle Timing
10
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SMJ44C256
262144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY
SGMS034C – MAY 1989 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
t
c(W)
t
w(RL)
RAS
CAS
t
t
d(CLRH)
w(RH)
t
d(CHRL)
t
t
t
d(RLCL)
t
d(RLCH)
t
w(CL)
t
t
w(CH)
su(CA)
t
t
d(CACH)
su(RA)
t
t
h(RA)
d(CARH)
t
h(RLCA)
A0–A8
Row
Column
Don’t Care
t
d(RLCA)
t
h(CA)
t
su(WCH)
t
su(WRH)
t
h(RLW)
t
h(CLW)
su(WCL)
t
W
Don’t Care
Don’t Care
t
w(WL)
t
h(RLD)
t
t
h(D)
su(D)
DQ1–DQ4
Valid Data
Don’t Care
G
Don’t Care
Figure 3. Early-Write-Cycle Timing
11
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SMJ44C256
262144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY
SGMS034C – MAY 1989 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
t
c(W)
t
w(RL)
RAS
CAS
t
d(CLRH)
t
w(RH)
t
t
t
d(RLCL)
t
d(CHRL)
t
d(RLCH)
t
w(CL)
t
t
w(CH)
h(RLCA)
t
su(CA)
t
t
h(RA)
d(CACH)
t
t
su(RA)
d(CARH)
A0–A8
Row
Column
h(CA)
Don’t Care
t
t
su(WCH)
t
d(RLCA)
t
su(WRH)
W
Don’t Care
t
Don’t Care
t
su(D)
w(WL)
h(D)
t
t
h(RLD)
t
h(RLW)
DQ1–DQ4
Don’t Care
Valid Data
Don’t Care
t
t
h(WLGL)
d(GHD)
G
Don’t Care
Figure 4. Write-Cycle Timing
12
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ44C256
262144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY
SGMS034C – MAY 1989 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
t
c(rdW)
t
w(RL)
RAS
CAS
t
t
t
t
w(RH)
w(CL)
t
t
d(RLCL)
d(CHRL)
t
h(RA)
t
w(CH)
t
t
su(RA)
su(CA)
d(RLCA)
t
t
h(CA)
A0–A8
Column
Row
Don’t Care
su(WCH)
t
t
h(RLCA)
t
d(RLWL)
t
su(WRH)
t
su(rd)
t
w(WL)
W
Don’t Care
Don’t Care
t
d(CAWL)
t
d(CLWL)
t
su(D)
t
a(C)
t
h(D)
t
a(CA)
See Note A
DQ1–
DQ4
Don’t Care
Valid Out
Valid In
Don’t Care
t
a(R)
t
dis(G)
t
a(G)
t
d(GHD)
G
Don’t Care
Don’t Care
t
h(WLGL)
NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 5. Read-Write-/Read-Modify-Write-Cycle Timing
13
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SMJ44C256
262144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY
SGMS034C – MAY 1989 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
t
w(RH)
t
w(RL)P
RAS
CAS
t
t
c(P)
d(RLCL)
t
t
d(CLRH)
d(RLCH)
t
t
w(CH)
t
w(CL)
d(CHRL)
t
su(RA)
t
su(CA)
t
d(CACH)
t
h(RLCA)
t
t
t
d(CARH)
h(RA)
h(CA)
A0–A8
Row
Column
Don’t Care
Column
Don’t Care
t
d(RLCA)
t
h(CHrd)
t
t
su(rd)
h(RHrd)
t
W
a(C)
t
a(CA)
(see Note A)
t
a(CA)
t
t
dis(CH)
a(R)
t
a(CP)
(see Note C)
See Note A
See Note A
DQ1–DQ4
Valid Out
Valid Out
t
t
a(G)
dis(G)
t
t
a(G)
dis(G)
Don’t Care
Don’t Care
G
Don’t Care
NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
B. A write-cycle or read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write timing
specifications are not violated.
C. Access time is t
- or t
-dependent.
a(CA)
a(CP)
Figure 6. Enhanced-Page-Mode Read-Cycle Timing
14
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ44C256
262144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY
SGMS034C – MAY 1989 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
t
w(RH)
t
w(RL)P
RAS
CAS
t
t
c(P)
d(RLCH)
d(RLCL)
t
t
w(CH)
t
d(CLRH)
t
d(CHRL)
t
w(CL)
t
su(RA)
t
t
su(CA)
d(CACH)
t
h(CA)
t
t
h(RA)
d(CARH)
t
h(RLCA)
A0–A8
Row
Column
Column
Don’t Care
t
d(RLCA)
t
t
su(WCH)
h(RLW)
t
su(WCH)
t
su(WRH)
t
w(WL)
W
Don’t Care
Don’t Care
Don’t Care
t
t
h(D)
(see Note B)
su(D)
(see Note B)
t
h(WLGL)
t
su(D)
(see Note B)
t
h(D)
(see Note B)
t
h(RLD)
DQ1–DQ4
Valid Data In
Valid In
Don’t Care
t
d(GHD)
t
t
d(GHD)
h(WLGL)
G
Don’t Care
Don’t Care
NOTES: A. A read cycle or a read-modify-write cycle can be intermixed with the write cycles as long as the read and read-modify-write timing
specifications are not violated.
B. Referenced to CAS or W, whichever occurs last.
Figure 7. Enhanced-Page-Mode Write-Cycle Timing (see Note A)
15
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ44C256
262144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY
SGMS034C – MAY 1989 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
t
w(RH)
t
w(RL)P
RAS
CAS
t
d(RLCH)
t
d(CLRH)
t
d(RLCL)
t
d(CHRL)
t
c(PM)
t
w(CL)
t
su(RA)
t
t
w(CH)
h(RLCA)
t
su(CA)
t
t
h(CA)
d(RLCA)
A0–A8
Row
Column
Column
Don’t Care
t
d(CLWL)
t
t
su(WCH)
h(RA)
t
d(CAWL)
d(RLWL)
t
t
su(WRH)
w(WL)
t
W
t
a(C)
t
su(rd)
t
a(CP)
t
h(WLGL)
t
a(CA)
t
h(D)
t
a(R)
t
su(D)
See Note A
Valid Out
See Note A
Valid
Out
Valid In
DQ1–DQ4
Don’t Care
Don’t Care
t
a(G)
t
d(GHD)
t
dis(G)
G
t
h(WLGL)
NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
B. A read or write cycle can be intermixed with read-modify-write cycles as long as the read and write timing specifications are not
violated.
Figure 8. Enhanced-Page-Mode Read-Modify-Write-Cycle Timing (see Note B)
16
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ44C256
262144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY
SGMS034C – MAY 1989 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
t
c(rd)
t
w(RL)
RAS
t
w(RH)
t
d(CHRL)
t
t
t
d(RHCL)R
CAS
A0–A8
W
Don’t Care
Don’t Care
t
su(RA)
t
h(RA)
Row
Don’t Care
Row
Don’t Care
Don’t Care
Don’t Care
DQ1–DQ4
G
Figure 9. RAS-Only Refresh Timing
17
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ44C256
262144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY
SGMS034C – MAY 1989 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
Refresh Cycle
Refresh Cycle
t
w(RH)
Memory Cycle
t
w(RH)
t
t
w(RL)
w(RL)
RAS
CAS
t
d(RLCH)R
t
w(CL)
t
su(RA)
t
h(RA)
t
su(CA)
t
h(CA)
Don’t Care
A0–A8
Row
Col
t
h(RHrd)
t
su(rd)
Don’t Care
W
t
a(C)
a(CA)
t
t
dis(CH)
t
a(R)
DQ1–DQ4
Valid Data
t
t
dis(G)
a(G)
G
Figure 10. Hidden-Refresh-Cycle (Enhanced Page Mode) Timing
18
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ44C256
262144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY
SGMS034C – MAY 1989 – REVISED JUNE 1995
PARAMETER MEASUREMENT INFORMATION
t
c(rd)
t
w(RH)
t
w(RL)
RAS
t
d(RHCL)R
t
t
t
d(CLRL)R
CAS
t
d(RLCH)R
A0–A8
Don’t Care
DQ1–DQ4
Hi-Z
G
Don’t Care
W
Don’t Care
Figure 11. Automatic CBR Refresh-Cycle Timing
19
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SMJ44C256
262144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY
SGMS034C – MAY 1989 – REVISED JUNE 1995
20
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
IMPORTANT NOTICE
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product or service without notice, and advises its customers to obtain the latest version of relevant information
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TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED
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Copyright 1995, Texas Instruments Incorporated
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SMJ44C256-15JDL
256KX4 FAST PAGE DRAM, 150ns, CDIP20, 0.300 INCH, HERMETIC SEALED, SIDE BRAZED, CERAMIC, DIP-20
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