SMJ4C1024-80HL [TI]
1048576 BY 1-BIT DYNAMIC RANDOM-ACCESS MEMORY; 1048576 BY 1位动态随机存取存储器
| 型号： | SMJ4C1024-80HL |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1048576 BY 1-BIT DYNAMIC RANDOM-ACCESS MEMORY |
| 文件： | 总27页 (文件大小：414K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SMJ4C1024
1048576 BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS023E – DECEMBER 1988 – REVISED MARCH 1996
HJ PACKAGE
(TOP VIEW)
JD PACKAGE
(TOP VIEW)
Organization . . . 1048576 × 1-Bit
Processed to MIL-STD-883, Class B
Single 5-V Supply (10% Tolerance)
D
W
RAS
TF
1
2
3
4
5
20
19
18
17
16
V
SS
Q
CAS
NC
A9
D
W
RAS
TF
A0
A1
V
SS
Q
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
Performance Ranges:
CAS
A9
A8
A7
A6
A5
A4
ACCESS ACCESS ACCESS
READ
OR
WRITE
CYCLE
(MIN)
TIME
TIME
TIME
NC
t
t
t
a(R)
a(C)
a(CA)
(t
(t
RAC
)
(t
CAC
)
)
AA
(MAX)
(MAX)
(MAX)
A2
A3
A0
A1
A2
A3
6
15
14
13
12
11
A8
A7
A6
A5
A4
’4C1024-80
’4C1024-10
’4C1024-12
’4C1024-15
80 ns
100 ns
120 ns
150 ns
20 ns
25 ns
30 ns
40 ns
40 ns
45 ns
55 ns
70 ns
150 ns
190 ns
220 ns
260 ns
7
V
CC
8
9
Enhanced Page-Mode Operation for Faster
Memory Access
– Higher Data Bandwidth Than
Conventional Page Mode Parts
– Random Single-Bit Access Within a Row
With a Column Address
V
10
CC
HK PACKAGE
(TOP VIEW)
V
D
W
RAS
TF
NC
A0
A1
A2
A3
1
20
19
18
17
16
15
14
13
12
11
SS
Q
2
CAS
NC
A9
A8
A7
A6
A5
A4
3
One of TI’s CMOS Megabit Dynamic
Random-Access Memory (DRAM) Family
Including SMJ44C256 — 256K × 4
Enhanced Page Mode
4
5
6
7
CAS-Before-RAS (CBR) Refresh
8
9
Long Refresh Period
V
10
CC
512-Cycle Refresh in 8 ms (Max)
3-State Unlatched Output
Low Power Dissipation
FQ/HL PACKAGES
(TOP VIEW)
SV PACKAGE
(SIDE VIEW)
A9
Q
D
RAS
NC
A0
D
W
RAS
TF
10 11
V
SS
Q
CAS
NC
A9
1
All Inputs/Outputs and Clocks Are
TTL-Compatible
CAS
2
4
9
8
7
6
12
13
14
15
3
V
SS
5
Packaging Offered:
– 20/26-Pin J-Leaded Ceramic Surface
Mount Package (HJ Suffix)
– 18-Pin 300-Mil Ceramic Dual-In-Line
Package (JD Suffix)
– 20-Pin Ceramic Flatpack (HK Suffix)
– 20/26-Terminal Leadless Ceramic
Surface Mount Package (FQ/HL Suffixes)
– 20-Pin Ceramic Zig-Zag In-Line Package
(SV Suffix)
W
6
7
TF
NC
A1
A3
A4
A6
A8
8
NC
9
10
12
14
16
18
20
11
13
15
17
19
A2
V
CC
A5
A7
A0
A1
A2
A3
5
4
3
2
1
16
17
18
19
20
A8
A7
A6
A5
A4
V
CC
Operating Temperature Range
– 55°C to 125°C
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ4C1024
1048576 BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS023E – DECEMBER 1988 – REVISED MARCH 1996
PIN NOMENCLATURE
A0–A9
CAS
D
Address Inputs
Column Address Strobe
Data In
NC
Q
No Internal Connection
Data Out
RAS
TF
Row Address Strobe
Test Function
5-V Supply
Ground
Write Enable
V
CC
V
SS
W
description
The SMJ4C1024 is a 1048576-bit DRAM organized as 1048576 words of one bit each. It employs technology
for high performance, reliability, and low power at a low cost.
This device features maximum RAS access times of 80 ns, 100 ns, 120 ns, and 150 ns. Maximum power
dissipation is as low as 305 mW operating and 16.5 mW standby on 150-ns devices.
I
peaks are typIcally 140 mA and a –1 V input voltage undershoot can be tolerated, minimizing system noise.
DD
All inputs and outputs, including clocks, are compatible with series 54 TTL. All addresses and data-in lines are
latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
The SMJ4C1024 is offered in an 18-pin ceramic dual-in-line package (JD suffix), a 20/26-terminal leadless
ceramic carrier package (FQ/HL suffixes), a 20/26-pin J-leaded carrier package (HJ suffix), a 20-pin flatpack
(HK suffix), and a 20-pin ceramic zig-zag in-line package (SV suffix). They are characterized for operation from
– 55°C to 125°C.
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ4C1024
1048576 BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS023E – DECEMBER 1988 – REVISED MARCH 1996
†
logic symbol
RAM 1024K × 1
20D10/21D0
5
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
6
7
8
10
11
12
13
14
15
0
A
1 048 575
20D19/21D9
C20 [ROW]
G23 [REFRESH ROW]
3
RAS
CAS
24 [PWR DWN]
C21 [COL]
G24
&
16
23C22
24EN
2
1
W
D
23,21D
A, 22D
17
A
Q
†
This symbol is in accordance with ANSI/IEEE Std. 91-1984 and IEC Publication 617-12.
The pin numbers shown are for the 18-pin JD package.
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ4C1024
1048576 BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS023E – DECEMBER 1988 – REVISED MARCH 1996
functional block diagram
RAS
CAS
W
Timing and Control
Row
Address
Buffers
(10)
256K
Array
Sense Amplifiers
Row
Decode Array
256K
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
Data In
Reg.
D
Q
I/O
Buffers
1 of 8
Column
Address
Buffers
(10)
Column Decode
Data
Out Reg.
Selection
Sense Amplifiers
256K
Array
Row
Decode Array
256K
operation
enhanced page mode
Enhancedpage-modeoperationallowsfastermemoryaccessbykeepingthesamerowaddresswhileselecting
random column addresses. The time for row-address setup and hold and for address multiplexing is eliminated.
The maximum number of columns that can be accessed is determined by the maximum RAS low time and the
CAS page-cycle time used. With minimum CAS page-cycle time, all 1024 columns specified by column
addresses A0 through A9 can be accessed without intervening RAS cycles.
Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling
edge of RAS. The buffers act as transparent or flow-through latches while CAS is high. The falling edge of CAS
latches the column addresses. This feature lets the SMJ4C1024 operate at a higher data bandwidth than
conventional page-mode parts, since data retrieval begins as soon as the column address is valid rather than
when CAS goes low. This performance improvement is referred to as enhanced page mode. A valid column
address can be presented immediately after the row-address hold time has been satisfied, usually well in
advance of the falling edge of CAS. In this case, data is obtained after t
maximum (access time from CAS
a(C)
low) if t
maximum (access time from column address) has been satisfied. If the column addresses for the
a(CA)
next page cycle are valid at the same time CAS goes high, access time for the next cycle is determined by the
later occurrence of t or t (access time from rising edge of CAS).
a(CA)
a(CP)
address (A0–A9)
Twenty address bits are required to decode one of 1048576 storage cell locations. Ten row-address bits are
set up on inputs A0 through A9 and latched onto the chip by RAS. The ten column-address bits are set up on
pinsA0throughA9andlatchedontothechipbyCAS. Alladdressesmustbestableonorbeforethefallingedges
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ4C1024
1048576 BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS023E – DECEMBER 1988 – REVISED MARCH 1996
address (A0–A9) (continued)
of RAS and CAS. RAS is similar to a chip enable in that it activates the sense amplifiers as well as the row
decoder. CAS is used as a chip select to activate the output buffer as well as to latch the address bits into the
column-address buffer.
write enable (W)
The read or write mode is selected through W. A logic high on the W input selects the read mode and a logic
low selects the write mode. The write-enable pin can be driven from standard TTL circuits without a pullup
resistor. The data input is disabled when the read mode is selected. When W goes low prior to CAS (early write),
data out remains in the high-impedance state for the entire cycle, permitting common input/output operation.
data in (D)
Data-in is written during a write or a read-modify-write cycle. Depending on the mode of operation, the falling
edge of CAS or W strobes data into the on-chip latch. In an early-write cycle, W is brought low prior to CAS,
and the data is strobed in by CAS with setup and hold times referenced to this signal. In a delayed-write or a
read-modify-write cycle, CAS is already low, and the data is strobed in by W with setup and hold times
referenced to this signal.
data out (Q)
The 3-state output buffers provide direct TTL compatibility (no pullup resistor required) with a fanout of two
series 54 TTL loads. Data out is the same polarity as data in. The output is in the high-impedance (floating) state
until CAS is brought low. In a read cycle, the output becomes valid after the access time t
. The access time
a(C)
fromCASlow(t
)beginswiththenegativetransitionofCASaslongast
andt
aresatisfied.Theoutput
a(C)
a(R)
a(CA)
becomes valid after the access time has elapsed and remains valid while CAS is low; when CAS goes high, the
output returns to a high-impedance state. In a delayed-write or read-modify-write cycle, the output follows the
sequence for the read cycle.
refresh
A refresh operation must be performed at least once every 8 ms to retain data. This can be achieved by strobing
each of the 512 rows (A0–A8). A normal read or write cycle refreshes all bits in each selected row. A RAS-only
operation can be used by holding CASatthehigh(inactive)level, conservingpowerastheoutputbufferremains
in the high-impedance state. Externally generated addresses must be used for a RAS-only refresh. Hidden
refresh can be performed while maintaining valid data at the output pin. This is accomplished by holding CAS
at V after a read operation and cycling RAS after a specified precharge period, similar to a RAS-only refresh
IL
cycle.
CAS-before-RAS (CBR) refresh
CBR refresh is used by bringing CAS low earlier than RAS (see parameter t
) and holding it low after
d(CLRL)R
RAS falls (parameter t
). For successive CBR refresh cycles, CAS can remain low while cycling RAS.
d(RLCH)R
The external address is ignored and the refresh address is generated internally. The external address is also
ignored during the hidden refresh cycles.
power up
To achieve proper device operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles
is required after full V
level is achieved.
CC
test function (TF) pin
During normal device operation, TF must be disconnected or biased at a voltage ≤ V
.
CC
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ4C1024
1048576 BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS023E – DECEMBER 1988 – REVISED MARCH 1996
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
Voltage range on V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
CC
Short-circuit output current, I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
OS
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Operating free-air temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to V
.
SS
recommended operating conditions
MIN NOM
MAX
5.5
UNIT
V
V
V
T
Supply voltage
4.5
2.4
5
V
V
V
CC
IH
IL
High-level input voltage
6.5
Low-level input voltage (see Note 2)
Minimum operating free-air temperature
– 1
0.8
– 55
°C
°C
A
T
C
Maximum operating case temperature
125
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ4C1024
1048576 BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS023E – DECEMBER 1988 – REVISED MARCH 1996
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
’4C1024-80
’4C1024-10
’4C1024-12
’4C1024-15
TEST
CONDITIONS
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
High-level
output voltage
V
V
I
I
= – 5 mA
2.4
2.4
2.4
2.4
V
V
OH
OH
Low-level
output voltage
= 4.2 mA
0.4
0.4
0.4
0.4
OL
OL
Input current
(leakage)
V
= 5.5 V,
V = 0 V to 6.5 V,
I
CC
All other pins = 0 V to V
I
± 10
± 10
± 10
± 10
µA
I
CC
= 0 V to V
Output
current
(leakage)
V
= 5.5 V,
V
,
CC
CC
CAS high
O
I
O
± 10
75
3
± 10
70
3
± 10
60
3
± 10
55
3
µA
mA
mA
Read- or
write-cycle
current
I
V
CC
= 5.5 V,
Minimum cycle
CC1
CC2
After one memory cycle,
RAS and CAS high,
Standby
current
I
V
IH
= 2.4 V
Average
refresh
current
(RAS only or
CBR)
V
= 5.5 V,
Minimum cycle,
CC
RAS cycling,
I
I
70
50
65
45
55
35
50
30
mA
mA
CC3
CAS high (RAS only),
RAS low after CAS low (CBR)
V
= 5.5 V,
t
= minimum,
Average page
current
CC
RAS low,
PC
CAS cycling
CC4
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 3)
HL/JD/FQ
MIN MAX
HJ
MIN
HK
MIN
SV
MIN
PARAMETER
UNIT
MAX
MAX
MAX
C
C
C
C
C
Input capacitance, address inputs
Input capacitance, data input
Input capacitance, strobe inputs
Input capacitance, write-enable input
Output capacitance
6
5
7
7
7
7
5
7
7
9
8
6
9
7
8
7
8
pF
pF
pF
pF
pF
i(A)
i(D)
i(RC)
i(W)
o
8
7
10
NOTE 3: Capacitance is sampled only at initial design and after any major change. Samples are tested at 0 V and 25°C with a 1-MHz signal
applied to the pin under test. All other pins are open.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Figure 1)
’4C1024-80
MIN MAX
’4C1024-10
MIN MAX
’4C1024-12
MIN MAX
’4C1024-15
MIN MAX
ALT.
SYMBOL
PARAMETER
UNIT
t
t
t
t
Access time from CAS low
t
20
40
80
40
25
45
30
55
40
70
ns
ns
ns
ns
a(C)
CAC
Access time from column address
Access time from RAS low
t
a(CA)
a(R)
AA
t
100
40
120
60
150
75
RAC
Access time from column precharge
t
t
a(CP)
CPA
Output disable time after CAS high
(see Note 4)
t
20
25
30
35
ns
dis(CH)
OFF
NOTE 4:
t
is specified when the output is no longer driven. The output is disabled by bringing CAS high.
dis(CH)
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ4C1024
1048576 BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS023E – DECEMBER 1988 – REVISED MARCH 1996
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Note 5)
’4C1024-80
’4C1024-10
’4C1024-12
’4C1024-15
ALT.
SYMBOL
UNIT
MIN
150
150
175
MAX
MIN
190
190
220
MAX
MIN
220
220
265
MAX
MIN
260
260
315
MAX
Cycle time, read
(see Note 6)
t
t
t
t
ns
ns
ns
c(rd)
RC
Cycle time, write
t
WC
c(W)
Cycle time,
read-write/read-modify-write
t
c(rdW)
RWC
Cycle time, page-mode read
or write (see Note 7)
t
t
50
55
65
80
ns
c(P)
PC
Cycle time, page-mode
read-modify-write
t
t
t
t
75
10
20
85
10
25
110
15
135
25
ns
ns
ns
c(PM)
w(CH)
w(CL)
PRWC
Pulse duration, CAS high
t
CP
Pulse duration, CAS low
(see Note 8)
t
10000
10000
10000
10000
30
10000
10000
40
10000
10000
CAS
Pulse duration, RAS high
(precharge)
t
t
60
80
80
90
100
150
ns
ns
w(RH)
w(RL)
RP
Pulse duration, nonpage
mode, RAS low
(see Note 9)
t
t
100
120
RAS
Pulse duration, page mode,
RAS low (see Note 9)
t
t
t
t
80 100000
100 100000
120 100000
150 100000
ns
ns
ns
w(RL)P
w(WL)
su(CA)
RASP
Pulse duration, write
t
15
0
15
3
20
3
25
3
WP
Setup time, column address
before CAS low
t
ASC
ASR
Setup time, row address
before RAS low
t
t
t
t
t
t
t
t
t
0
0
0
0
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
su(RA)
su(D)
Setup time, data
(see Note 10)
t
DS
Setup time, read before CAS
low
t
0
0
0
0
su(rd)
RCS
Setup time, W low before
CAS low (see Note 11)
t
0
0
0
0
su(WCL)
su(WCH)
su(WRH)
h(CA)
WCS
Setup time, W low before
CAS high
t
t
20
20
15
12
25
25
20
15
30
30
20
15
40
40
25
20
CWL
RWL
Setup time, W low before
RAS high
Hold time, column address
after CAS low
t
CAH
Hold time, row address after
RAS low
t
h(RA)
RAH
NOTES: 5. Timing measurements in this table are referenced to V max and V min.
IL IH
6. All cycle times assume t = 5 ns.
t
7. To assure t
min, t
should be ≥ t
.
w(CH)
su(WCH)
c(P)
su(CA)
8. In a read-modify-write cycle, t
and t
must be observed.
must be observed.
d(CLWL)
d(RLWL)
9. In a read-modify-write cycle, t
and t
su(WRH)
10. Referenced to the later of CAS or W in write operations
11. Early write operation only
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ4C1024
1048576 BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS023E – DECEMBER 1988 – REVISED MARCH 1996
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Note 5) (continued)
’4C1024-80
’4C1024-10
’4C1024-12
’4C1024-15
ALT.
SYMBOL
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
100
30
MAX
Hold time, column address after
RAS low (see Note 12)
t
t
t
t
60
70
80
ns
ns
ns
h(RLCA)
AR
Hold time, data (see Note 10)
t
15
20
25
h(D)
DH
Hold time, data after RAS low
(see Note 12)
t
t
t
60
70
85
110
h(RLD)
DHR
RCH
RRH
Hold time, read after CAS high
(see Note 13)
t
t
t
t
0
10
15
60
0
10
20
70
0
10
25
85
0
10
ns
ns
ns
ns
h(CHrd)
h(RHrd)
h(CLW)
h(RLW)
Hold time, read after RAS high
(see Note 13)
Hold time, write after CAS low
(see Note 11)
t
t
30
WCH
Hold time, write after RAS low
(see Note 12)
100
WCR
t
t
t
Delay time, RAS low to CAS high
Delay time, CAS high to RAS low
Delay time, CAS low to RAS high
t
80
0
100
0
120
0
150
0
ns
ns
ns
d(RLCH)
d(CHRL)
d(CLRH)
CSH
CRP
RSH
t
t
20
25
30
40
Delay time, CAS low to W low
(see Note 14)
t
t
t
t
t
t
t
t
t
t
20
22
17
40
40
80
40
20
25
28
40
28
50
33
ns
ns
ns
ns
ns
ns
ns
ns
ns
d(CLWL)
d(RLCL)
d(RLCA)
d(CARH)
d(CACH)
d(RLWL)
d(CAWL)
d(RLCH)R
d(CLRL)R
CWD
Delay time, RAS low to CAS low
(see Note 15)
t
60
40
75
55
90
65
110
80
RCD
Delay time, RAS low to column
address (see Note 15)
t
20
20
25
RAD
Delay time, column address to RAS
high
t
45
55
70
RAL
Delay time, column address to CAS
high
t
45
55
70
CAL
Delay time, RAS low to W low
(see Note 14)
t
100
45
130
65
160
80
RWD
Delay time, column address to W
low (see Note 14)
t
AWD
Delay time, RAS low to CAS high
(see Note 16)
t
25
25
30
CHR
Delay time, CAS low to RAS low
(see Note 16)
t
t
10
0
10
0
10
0
15
0
CSR
t
t
t
Delay time, RAS high to CAS low
Refresh time interval
ns
ms
ns
d(RHCL)R
RPC
t
8
8
8
8
rf
t
REF
—
Transition time (see Note 17)
—
—
—
—
NOTES: 5. Timing measurements in this table are referenced to V max and V min.
IL
IH
10. Referenced to the later of CAS or W in write operations.
11. Early-write operation only
12. The minimum value is measured when t
is set t min as a reference.
d(RLCL)
d(RLCL)
must be satisfied for a read cycle.
13. Either t
or t
h(RHrd)
h(CHrd)
14. Read-modify-write operation only
15. Maximum value specified only to assure access time.
16. CBR refresh only
17. Transition times (rise and fall) for RAS and CAS are to be minimum of 3 ns and a maximum of 50 ns.
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ4C1024
1048576 BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS023E – DECEMBER 1988 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
V
1.31 V
R
= 218 Ω
I
/I
L
OH OL
Output Under Test
Output Under Test
C
= 80 pF
C
= 80 pF
L
L
(see Note A)
(see Note A)
(a) LOAD CIRCUIT
NOTE A: C includes probe and fixture capacitance.
(b) ALTERNATE LOAD CIRCUIT
L
Figure 1. Load Circuits for Timing Parameters
10
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ4C1024
1048576 BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS023E – DECEMBER 1988 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
t
c(rd)
t
w(RL)
RAS
t
t
t
t
d(CLRH)
w(RH)
t
d(RLCL)
t
d(CHRL)
t
d(RLCH)
t
w(CL)
CAS
t
d(RLCA)
t
w(CH)
t
t
t
su(CA)
t
h(RA)
d(CACH)
d(CARH)
t
su(RA)
t
h(RLCA)
A0–A9
Row
Column
Don’t Care
t
t
h(CA)
h(RHrd)
t
su(rd)
t
h(CHrd)
W
Q
Don’t Care
Don’t Care
t
a(C)
t
dis(CH)
t
a(CA)
Valid
Hi-Z
See Note A
t
a(R)
NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 2. Read-Cycle Timing
11
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ4C1024
1048576 BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS023E – DECEMBER 1988 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
t
c(W)
t
w(RL)
RAS
CAS
t
t
t
d(CLRH)
t
w(RH)
t
d(RLCL)
t
w(CL)
t
d(CHRL)
t
d(RLCH)
t
su(RA)
t
w(CH)
t
d(CACH)
t
t
d(CARH)
h(RA)
t
su(CA)
t
h(RLCA)
A0–A9
Row
Column
Don’t Care
t
h(CA)
t
d(RLCA)
t
su(WCH)
t
su(WRH)
t
h(RLW)
t
h(CLW)
t
su(WCL)
W
Don’t Care
Don’t Care
t
w(WL)
t
su(D)
t
h(D)
t
h(RLD)
D
Q
Valid Data
Don’t Care
Hi-Z
Figure 3. Early-Write-Cycle Timing
12
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ4C1024
1048576 BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS023E – DECEMBER 1988 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
t
c(W)
t
w(RL)
RAS
CAS
t
d(CLRH)
t
t
t
w(RH)
d(CHRL)
t
d(RLCL)
t
t
d(RLCH)
t
w(CL)
t
t
w(CH)
su(CA)
t
t
h(RA)
d(CARH)
t
d(CACH)
t
su(RA)
t
h(RLCA)
Row
Column
Don’t Care
A0–A9
t
h(CA)
t
d(RLCA)
t
su(WCH)
t
su(WRH)
Don’t Care
Don’t Care
W
t
h(RLW)
t
w(WL)
t
h(D)
t
su(D)
t
h(RLD)
Don’t Care
Valid Data
Don’t Care
D
Q
t
dis(CH)
Not Valid
Figure 4. Write-Cycle Timing
13
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ4C1024
1048576 BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS023E – DECEMBER 1988 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
t
c(rdW)
t
w(RL)
RAS
CAS
t
w(RH)
t
t
w(CL)
t
t
d(CHRL)
t
d(RLCL)
t
d(RLCA)
t
t
w(CH)
h(RA)
t
su(CA)
t
su(RA)
t
t
t
h(RLCA)
A0–A9
Row
Column
Don’t Care
t
t
d(CAWL)
su(WCH)
t
su(WRH)
t
d(CLWL)
t
w(WL)
t
su(rd)
t
h(CA)
W
Don’t Care
Don’t Care
t
d(RLWL)
t
su(D)
D
Q
Don’t Care
Valid In
Don’t Care
dis(CH)
t
h(D)
t
See Note A
Hi-Z
Valid Out
t
a(C)
a(CA)
t
t
a(R)
NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 5. Read-Write-/Read-Modify-Write-Cycle Timing
14
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ4C1024
1048576 BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS023E – DECEMBER 1988 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
t
w(RH)
t
w(RL)P
RAS
t
d(RLCL)
t
d(CHRL)
t
c(P)
t
d(RLCH)
t
w(CH)
t
t
d(CLRH)
w(CL)
CAS
t
h(CA)
t
h(RLCA)
t
d(CACH)
t
su(RA)
t
su(CA)
t
d(CARH)
t
h(RA)
A0–A9
Row
Column
Column
Don’t Care
h(RHrd)
t
t
d(RLCA)
See Note C
t
h(CHrd)
t
su(rd)
t
a(CA)
W
t
a(C)
t
a(CP)
(see Note C)
t
a(CA)
t
dis(CH)
t
a(R)
Valid
Out
See Note A
Valid
Out
Q
See Note A
NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
B. Awritecycleoraread-modifycyclecanbemixedwiththereadcyclesaslongasthewriteandread-modify-writetimingspecifications
are not violated.
C. Access time is t
or t
dependent.
a(CA)
a(CP)
Figure 6. Enhanced-Page-Mode Read-Cycle Timing
15
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ4C1024
1048576 BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS023E – DECEMBER 1988 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
t
w(RH)
t
w(RL)P
RAS
CAS
t
t
d(CLRH)
d(RLCH)
t
w(CL)
t
t
d(CHRL)
c(P)
t
d(RLCL)
t
w(CH)
t
su(CA)
t
t
h(RLCA)
d(CACH)
t
t
h(RA)
d(CARH)
t
h(CA)
t
su(RA)
A0–A9
Row
Column
Column
Don’t Care
t
su(WCH)
t
su(WCH)
t
d(RLCA)
t
w(WL)
t
su(WRH)
t
h(RLW)
W
Don’t Care
Don’t Care
Don’t Care
t
h(D)
(see Note B)
h(D)
t
t
h(RLD)
t
su(D)
(see Note B)
t
su(D)
Valid
In
D
Q
Valid Data In
Don’t Care
Hi-Z
NOTES: A. A read cycle or a read-modify-write cycle can be intermixed with write cycles as long as read and read-modify-write timing
specifications are not violated.
B. Referenced to CAS or W, whichever occurs last.
Figure 7. Enhanced-Page-Mode Write-Cycle Timing
16
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ4C1024
1048576 BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS023E – DECEMBER 1988 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
t
w(RH)
t
w(RL)P
RAS
CAS
t
t
c(PM)
t
t
d(CLRH)
d(RLCH)
w(CH)
t
d(CHRL)
t
d(RLCL)
t
w(CL)
t
su(CA)
t
h(RLCA)
t
d(RLCA)
t
h(RA)
su(RA)
t
h(CA)
t
A0–A9
Row
Column
Column
Don’t Care
t
su(rd)
t
t
su(WCH)
d(CLWL)
t
d(CAWL)
t
t
su(WRH)
w(WL)
t
d(RLWL)
W
Don’t Care
t
h(D)
t
su(D)
D
Don’t Care
Valid
Valid
Don’t Care
t
a(C)
t
a(CA)
t
dis(CH)
t
a(R)
t
a(CP)
See Note A
See Note A
Valid
Out
Valid
Out
Q
NOTES: A. Output can go from high-impedance state to an invalid-data state prior to the specified access time.
B. A read or a write cycle can be intermixed with read-modify-write cycles as long as the read and write timing specifications are
not violated.
Figure 8. Enhanced-Page-Mode Read-Modify-Write-Cycle Timing
17
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ4C1024
1048576 BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS023E – DECEMBER 1988 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
t
c(rd)
t
w(RL)
RAS
CAS
t
t
t
w(RH)
t
d(RHCL)R
Don’t Care
t
t
d(CHRL)
su(RA)
t
h(RA)
Don’t Care
Row
Don’t Care
Row
A0–A9
W
D
Don’t Care
Don’t Care
Q
Hi-Z
Figure 9. RAS-Only Refresh-Cycle Timing
18
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ4C1024
1048576 BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS023E – DECEMBER 1988 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
Refresh Cycle
Memory Cycle
Refresh Cycle
w(RH)
t
t
w(RH)
t
w(RL)
t
w(RL)
RAS
CAS
t
d(RLCH)R
t
w(CL)
t
h(CA)
t
su(CA)
t
h(RA)
t
su(RA)
A0–A9
Row
Col
Don’t Care
t
h(RHrd)
t
su(rd)
W
D
Don’t Care
Don’t Care
t
a(C)
t
t
dis(CH)
a(CA)
t
a(R)
Valid Data
Q
Figure 10. Hidden-Refresh-Cycle Timing
19
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ4C1024
1048576 BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS023E – DECEMBER 1988 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
t
c(rd)
t
w(RH)
t
w(RL)
RAS
t
d(CLRL)R
t
d(RLCH)R
t
d(RHCL)R
t
t
CAS
A0–A9
Don’t Care
Don’t Care
Hi-Z
D
Q
Figure 11. Automatic-CBR-Refresh-Cycle Timing
20
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ4C1024
1048576 BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS023E – DECEMBER 1988 – REVISED MARCH 1996
MECHANICAL DATA
HJ (R-CDCC-J20)
J-LEADED CERAMIC CHIP CARRIER
0.685 (17,40)
0.665 (16,89)
0.608 (15,44)
0.592 (15,04)
0.048 (1,22)
0.028 (0,71)
4 Places
20
11
0.338 (8,59)
0.322 (8,18)
1
10
0.056 (1,42)
0.044 (1,12)
0.102 (2,59)
0.080 (2,03)
0.010 (0,25)
0.006 (0,15)
0.137 (3,48)
0.114 (2,90)
0.022 (0,56)
0.012 (0,30)
0.308 (7,82)
0.264 (6,71)
0.050 (1,27)
0.035 (0,89)
Radius
0.025 (0,64)
4040144-2/B 10/94
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals will be gold plated.
21
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ4C1024
1048576 BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS023E – DECEMBER 1988 – REVISED MARCH 1996
MECHANICAL DATA
HK (R-CDFP-F20)
CERAMIC DUAL FLATPACK
0.035 (0,89)
0.025 (0,64)
0.010 (0,25)
0.004 (0,10)
0.095 (2,41)
0.075 (1,91)
0.310 (7,87)
0.290 (7,37)
Lid
0.120 (3,05)
0.090 (2,29)
1
20
0.050 (1,27)
0.680 (17,27)
0.660 (16,76)
0.021 (0,53)
0.015 (0,38)
10
11
0.390 (9,91)
0.370 (9,40)
0.315 (8,00)
0.295 (7,49)
4040174/C 08/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
22
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ4C1024
1048576 BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS023E – DECEMBER 1988 – REVISED MARCH 1996
MECHANICAL DATA
FQ (R-CDCC-N20)
LEADLESS CERAMIC CHIP CARRIER
0.685 (17,40)
0.665 (16,89)
0.030 (0,76) MIN
0.357 (9,07)
0.343 (8,71)
0.092 (2,34)
0.069 (1,75)
0.028 (0,71)
0.022 (0,56)
10
11
0.008 (0,20) RAD TYP
0.608 (15,44)
0.592 (15,04)
0.050 (1,27)
1
20
0.090 (2,29) TYP
0.050 (1,27) TYP
4040143/B 10/94
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
23
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ4C1024
1048576 BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS023E – DECEMBER 1988 – REVISED MARCH 1996
MECHANICAL DATA
HL (R-CDCC-N20/26)
LEADLESS CERAMIC CHIP CARRIER
0.685 (17,40)
0.665 (16,89)
0.030 (0,76) MIN
0.357 (9,07)
0.343 (8,71)
0.080 (2,03)
0.065 (1,65)
11
10
0.028 (0,71)
0.022 (0,56)
0.008 (0,20) RAD TYP
0.608 (15,44)
0.592 (15,04)
0.050 (1,27)
20
1
0.090 (2,29) TYP
0.050 (1,27) TYP
4040145/B 4/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
24
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ4C1024
1048576 BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS023E – DECEMBER 1988 – REVISED MARCH 1996
MECHANICAL DATA
SV (R-CZIP-T**)
CERAMIC ZIG-ZAG PACKAGE
20 PIN SHOWN
0.130 (3,30)
0.100 (2,54)
A
B
Seating Plane
0.200 (5,08)
0.125 (3,18)
0.050 (1,27)
0.015 (0,38)
0.015 (0,38)
0.008 (0,20)
0.060 (1,52)
0.040 (1,02)
0.100 (2,54)
19
0.115 (2,92)
0.085 (2,16)
1
PINS **
20
24
28
DIM
C
1.065
1.265
1.465
0.023 (0,58)
A MAX
(27,05) (32,13) (37,21)
0.015 (0,38)
1.035 1.235 1.435
(26,29) (31,37) (36,45)
A MIN
B MAX
B MIN
C MAX
C MIN
0.380
(9,65)
0.465
(11,81) (11,81)
0.465
0.355
(9,02)
0.440
(11,18) (11,18)
0.440
2
4
6
8
10
12
14
16
18
20
0.910
1.110 1.310
0.375 (9,53)
0.355 (9,02)
(23,11) (28,19) (33,27)
0.070 (1,78)
0.040 (1,02)
0.890 1.090 1.290
(22,61) (27,69) (32,77)
4040002/C 08/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
25
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMJ4C1024
1048576 BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS023E – DECEMBER 1988 – REVISED MARCH 1996
MECHANICAL DATA
JD (R-CDIP-T**)
CERAMIC SIDE-BRAZE DUAL-IN-LINE PACKAGE
20 PIN SHOWN
A
PINS **
16
18
20
24
DIM
20
11
0.810
0.910
1.010
1.100
A MAX
(20,57) (23,11) (25,65) (27,94)
0.290 (7,37)
TYP
1
10
0.065 (1,65)
0.045 (1,14)
0.175 (4,45)
0.140 (3,56)
0.320 (8,13)
0.290 (7,37)
0.075 (1,91) MAX 4 Places
Seating Plane
0.020 (0,51) MIN
0.125 (3,18) MIN
0°–15°
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0.012 (0,30)
0.008 (0,20)
4040086/C 08/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
26
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明