SMQ320C32_09 [TI]
DIGITAL SIGNAL PROCESSOR;
| 型号： | SMQ320C32_09 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DIGITAL SIGNAL PROCESSOR |
| 文件： | 总43页 (文件大小：577K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SMQ320C32
DIGITAL SIGNAL PROCESSOR
SGUS027B – APRIL 1998 – REVISED MARCH 1999
Military Operating Temperature Range
144-Pin Plastic Quad Flatpack
– 55°C to 125°C; QML Processing
(PCM Suffix) 5 V
High-Performance Floating-Point Digital
Signal Processor (DSP)
SMQ320C32-50 (5 V)
– 40-ns Instruction Cycle Time
– 275 MOPS
Eight Extended-Precision Registers
Two Address Generators With Eight
Auxiliary Registers and Two Auxiliary
Register Arithmetic Units (ARAUs)
Two Low-Power Modes
– 50 MFLOPS
– 25 MIPS
Two- and Three-Operand Instructions
SMQ320C32-60 (5 V)
– 33-ns Instruction Cycle Time
– 330 MOPS
– 60 MFLOPS
– 30 MIPS
Parallel Arithmetic Logic Unit (ALU) and
Multiplier Execution in a Single Cycle
Block-Repeat Capability
Zero-Overhead Loops With Single-Cycle
Branches
32-Bit High-Performance CPU
Conditional Calls and Returns
16-/32-Bit Integer and 32-/40-Bit
Floating-Point Operations
Interlocked Instructions for
Multiprocessing Support
32-Bit Instruction Word, 24-Bit Addresses
One External Pin, PRGW, That Configures
the External-Program-Memory Width to
16 or 32 Bits
Two 256 × 32-Bit Single-Cycle, Dual-Access
On-Chip RAM Blocks
Flexible Boot-Program Loader
Two Sets of Memory Strobes (STRB0 and
STRB1) and One I/O Strobe (IOSTRB)
Allow Zero-Glue Logic Interface to Two
Banks of Memory and One Bank of External
Peripherals
On-Chip Memory-Mapped Peripherals:
– One Serial Port
– Two 32-Bit Timers
– Two-Channel Direct Memory Access
(DMA) Coprocessor With Configurable
Priorities
Separate Bus-Control Registers for Each
Strobe-Control Wait-State Generation,
External Memory Width, and Data Type Size
Enhanced External Memory Interface That
Supports 8-/16-/32-Bit-Wide External RAM
for Data Access and Program Execution
From 16-/32-Bit-Wide External RAM
STRB0 and STRB1 Memory Strobes Handle
8-, 16-, or 32-Bit External Data Accesses
(Reads and Writes)
SMJ320C30 and SMJ320C31 Object Code
Compatible
Multiprocessor Support Through the HOLD
and HOLDA Signals Is Valid for All Strobes
Fabricated Using 0.7-µm Enhanced
Performance Implanted CMOS (EPIC )
Technology by Texas Instruments
description
The SMQ320C32 is a member of the ’320C3x generation of digital signal processors from Texas Instruments.
The SMQ320C32 is an enhanced 32-bit floating-point processor manufactured in 0.7-µm triple-level-metal
CMOS technology. The enhancements to the ’320C3x architecture include a variable-width external-memory
interface, faster instruction cycle time, power-down modes, two-channel DMA coprocessor with configurable
priorities, flexible bootloader, relocatable interrupt-vector table, and edge- or level-triggered interrupts.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1999, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMQ320C32
DIGITAL SIGNAL PROCESSOR
SGUS027B – APRIL 1998 – REVISED MARCH 1999
description (continued)
The internal busing and special digital signal processing instruction set of the SMQ320C32 have the speed and
flexibility to execute up to 50 million floating-point operations per second (MFLOPS). The SMQ320C32
optimizes speed by implementing functions in hardware that other processors implement through software or
microcode. This hardware-intensive approach provides performance previously unavailable on a single chip.
†
PCM PACKAGE
(TOP VIEW)
DR0
1
H3
H1
D0
D1
D2
D3
DV
D4
D5
D6
D7
D8
D9
108
107
106
105
104
103
102
101
100
99
DV
FSR0
2
DD
3
CLKR0
CLKX0
FSX0
DX0
4
5
6
7
DD
8
IV
SS
9
SHZ
TCLK0
TCLK1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
98
97
DV
DD
96
EMU3
EMU0
95
V
V
SSL
SSL
94
V
V
DDL
DDL
93
DV
CV
D10
SS
SS
92
EMU1
EMU2
91
90
V
DV
SSL
MCBL/MP
DD
D11
IV
89
88
CV
DV
SS
SS
SS
D12
87
86
A23
A22
A21
A20
A19
A18
V
V
DDL
DDL
85
84
D13
D14
D15
D16
D17
83
82
81
80
DV
A17
DD
79
DV
DD
78
A16
A15
A14
A13
D18
D19
D20
D21
77
76
75
74
CV
DV
DV
CV
SS
SS
SS
SS
73
†
NC=No internal connection
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMQ320C32
DIGITAL SIGNAL PROCESSOR
SGUS027B – APRIL 1998 – REVISED MARCH 1999
Pin Assignments
PIN
PIN
PIN
PIN
PIN
NUMBER
1
NAME
DR0
DV
NUMBER
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
NAME
NUMBER
NAME
NUMBER
88
NAME
NUMBER
117
NAME
A17
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
DV
DD
D31
IV
RDY
SS
D11
DV
2
A16
A15
A14
A13
89
118
IV
SS
DD
3
FSR0
CLKR0
CLKX0
FSX0
DX0
D30
D29
D28
D27
D26
90
119
IOSTRB
DD
D10
4
91
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
STRB0_B3/A
STRB0_B2/A
STRB0_B1
STRB0_B0
–1
5
92
CV
DV
SS
SS
–2
6
CV
DV
NC
93
SS
7
94
V
SSL
V
SSL
SS
8
IV
SS
IV
SS
95
V
V
DDL
9
SHZ
A12
DV
D25
DV
96
D9
D8
D7
D6
D5
D4
DV
D3
D2
D1
D0
H1
H3
NC
DDL
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
TCLK0
TCLK1
97
STRB1_B3/A
DD
DD
–1
A11
A10
A9
D24
D23
D22
NC
98
V
SSL
STRB1_B2/A
DV
DV
99
DD
–2
EMU3
EMU0
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
DD
A8
STRB1_B1
STRB1_B0
R/W
V
V
A7
CV
DV
DDL
SS
SS
DD
A6
DDL
EMU1
EMU2
DV
A5
A4
A3
D21
D20
D19
D18
PRGW
DD
RESET
V
CV
DV
SSL
MCBL/MP
SS
SS
CV
DV
V
V
DV
DD
XF0
XF1
IACK
INT0
INT1
INT2
INT3
NC
SS
SS
DDL
D17
D16
D15
D14
D13
DDL
A23
A22
A21
A20
A19
A18
A2
CV
DV
A1
V
SUBS
CV
DV
SS
SS
SS
SS
CLKIN
HOLDA
HOLD
V
V
V
V
SSL
DDL
SSL
DDL
DV
A0
D12
DV
DD
DD
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMQ320C32
DIGITAL SIGNAL PROCESSOR
SGUS027B – APRIL 1998 – REVISED MARCH 1999
pin functions
This section provides signal descriptions for the SMQ320C32 device. The following table lists each signal
(grouped by function), the number of pins, operating modes, and a brief signal description.
Pin Functions
CONDITIONS
PIN
WHEN
†
TYPE
DESCRIPTION
SIGNAL IS
IN HIGH Z
NAME
NO.
‡
EXTERNAL BUS INTERFACE (70 PINS)
D31–D0
32
24
I/O/Z 32-bit data port of the external bus interface
S
H
H
R
R
A23–A0
O/Z
O/Z
O/Z
O/Z
24-bit address port of the external bus interface
S
S
S
S
Read/write for external memory interface. R/W is high when a read is performed
and low when a write is performed over the parallel interface.
R/W
1
1
1
H
H
H
R
IOSTRB
STRB0_B3/A
External peripheral I/O strobe for the external memory interface
External memory-access strobe 0, byte enable 3 for 32-bit external memory
interface and address pin for 8-bit and 16-bit external memory interface
–1
–2
External memory-access strobe 0, byte enable 2 for 32-bit external memory
interface and address pin for 8-bit external memory interface
STRB0_B2/A
STRB0_B1
STRB0_B0
STRB1_B3/A
STRB1_B2/A
STRB1_B1
STRB1_B0
RDY
1
1
1
1
1
1
1
1
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
I
S
S
S
S
S
S
S
H
H
H
H
H
H
H
External memory-access strobe 0, byte enable 1 for the external memory
interface
External memory-access strobe 0, byte enable 0 for the external memory
interface
External memory-access strobe 1, byte enable 3 for 32-bit external memory
interface and address pin for 8-bit and 16-bit external memory interface
–1
–2
External memory-access strobe 1, byte enable 2 for 32-bit external memory
interface and address pin for 8-bit external memory interface
External memory-access strobe 1, byte enable 1 for the external memory
interface
External memory-access strobe 1, byte enable 0 for the external memory
interface
Ready. RDY indicates that the external device ispreparedforanexternalmemory
interface transaction to complete.
Holdsignalforexternalmemoryinterface. WhenHOLDisalogiclow, anyongoing
transaction is completed. A23–A0, D31–D0, IOSTRB, STRB0_Bx, STRB1_Bx,
and R/W are placed in the high-impedance state, and all transactions over the
external memory interface are held until HOLD becomes a logic high or the
NOHOLD bit of the STRB0 bus-control register is set.
HOLD
1
I
Hold acknowledge for external memory interface. HOLDA is generated in
response to a logic low on HOLD. HOLDA indicates that A23–A0, D31–D0,
IOSTRB, STRB0_Bx, STRB1_Bx, and R/W are in the high-impedance state and
that all transactions over the memory are held. HOLDA is high in response to a
logic high of HOLD or when the NOHOLD bit of the external bus-control register
is set.
HOLDA
PRGW
1
1
O/Z
S
Program memory width select. When PRGW is a logic low, program is fetched as
a single 32-bit word. When PRGW is a logic high, two 16-bit program fetches are
performed to fetch a single 32-bit instruction word. The status of PRGW at device
reset affects the reset value of the STRB0 and STRB1 bus-control register.
I
†
‡
§
I = input, O = output, Z = high-impedance state
S = SHZ active, H = HOLD active, R = RESET active
Recommended decoupling capacitor is 0.1 µF.
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMQ320C32
DIGITAL SIGNAL PROCESSOR
SGUS027B – APRIL 1998 – REVISED MARCH 1999
Pin Functions (Continued)
DESCRIPTION
CONDITIONS
WHEN
PIN
†
TYPE
SIGNAL IS
NAME
NO.
‡
IN HIGH Z
CONTROL SIGNALS (9 PINS)
Reset. When RESET is a logic low, the device is in the reset condition. When
RESET becomes a logic high, execution begins from the location specified by the
reset vector.
RESET
1
4
I
I
INT3–INT0
External interrupts
CONTROL SIGNALS (9 PINS) (CONTINUED)
Interrupt acknowledge. IACK is set to a logic high by the IACK instruction. This
signal can be used to indicate the beginning or end of an interrupt-service routine.
IACK
1
1
2
O/Z
I
S
MCBL/MP
XF1–XF0
Microcomputer bootloader/microprocessor mode
Externalflags. XF1 and XF0 are usedasgeneral-purposeI/Os or used to support
interlocked-processor instructions.
I/O/Z
S
R
SERIAL PORT SIGNALS (6 PINS)
Serial port 0 transmit clock. CLKX0 is the serial shift clock for the serial port 0
transmitter.
CLKX0
DX0
1
1
1
I/O/Z
S
S
S
R
R
R
I/O/Z Data transmit output. Serial port 0 transmits serial data on DX0.
Frame-synchronization pulse for transmit. The FSX0 pulse initiates the
transmit-data process over DX0.
FSX0
I/O/Z
Serial port 0 receive clock. CLKR0 is the serial shift clock for the serial port 0
receiver.
CLKR0
DR0
1
1
1
I/O/Z
S
S
S
R
R
R
I/O/Z Data receive. Serial port 0 receives serial data on DR0.
Frame-synchronization pulse for receive. The FSR0 pulse initiates the
receive-data process over DR0.
FSR0
I/O/Z
TIMER SIGNALS (2 PINS)
Timer clock 0. As an input, TCLK0 is used by timer 0 to count external pulses. As
an output, TCLK0 outputs pulses generated by timer 0.
TCLK0
TCLK1
1
1
I/O/Z
S
S
R
R
Timer clock 1. As an input, TCLK1 is used by timer 1 to count external pulses. As
an output, TCLK1 outputs pulses generated by timer 1.
I/O/Z
CLOCK SIGNALS (3 PINS)
CLKIN
H1
1
1
1
I
Input to the internal oscillator from an external clock source
External H1 clock. H1 has a period equal to twice CLKIN.
External H3 clock. H3 has a period equal to twice CLKIN.
RESERVED (5 PINS)
O/Z
O/Z
S
S
H3
EMU0–EMU2
EMU3
3
1
I
Reserved for emulation. Use 18 kΩ–22 kΩ pullup resistors to 5 V.
Reserved for emulation
O/Z
S
Shutdown high impedance. When active, SHZ shuts down the ’C32 and places
all3-stateI/Opinsinthehigh-impedancestate.SHZisusedforboard-leveltesting
to ensure that no dual drive conditions occur. CAUTION: A low on SHZ corrupts
’C32 memory and register contents. Reset the device with SHZ high to restore it
to a known operating condition.
SHZ
1
I
†
‡
§
I = input, O = output, Z = high-impedance state
S = SHZ active, H = HOLD active, R = RESET active
Recommended decoupling capacitor is 0.1 µF.
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMQ320C32
DIGITAL SIGNAL PROCESSOR
SGUS027B – APRIL 1998 – REVISED MARCH 1999
Pin Functions (Continued)
DESCRIPTION
CONDITIONS
WHEN
PIN
†
TYPE
SIGNAL IS
NAME
NO.
‡
IN HIGH Z
POWER/GROUND
CV
DV
7
7
I
I
I
I
I
I
I
Ground
Ground
Ground
SS
SS
IV
SS
4
§
§
DV
12
8
5 V supply
dc
DD
DDL
SSL
V
V
V
5 V supply
dc
6
Ground
1
Substrate, tie to ground
SUBS
†
‡
§
I = input, O = output, Z = high-impedance state
S = SHZ active, H = HOLD active, R = RESET active
Recommended decoupling capacitor is 0.1 µF.
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMQ320C32
DIGITAL SIGNAL PROCESSOR
SGUS027B – APRIL 1998 – REVISED MARCH 1999
functional block diagram
Program
Cache
(64 × 32)
RAM
Block 0
(256 × 32)
RAM
Block 1
(256 × 32)
Boot
ROM
24
32
24
32
24
32
32 24
A23 – A0
D31 – D0
R / W
32
PDATA Bus
PADDR Bus
IR
PC
RDY
External
Memory
Interface
24
HOLD
HOLDA
PRGW
DDATA Bus
RESET
INT(3-0)
IACK
DADDR1 Bus
DADDR2 Bus
XF(1,0)
H1
DMADATA Bus
H3
DMAADDR Bus
MCBL / MP
CLKIN
V
DD
Multiplexer
STRB0_B3/A
STRB0_B2/A
STRB0_B1
STRB0_B0
–1
V
SS
–2
DMA Controller
DMA Channel 0
STRB0
STRB0 Control Reg.
STRB1
SHZ
EMU0–3
STRB1_B3/A
STRB1_B2/A
STRB1_B1
STRB1_B0
–1
Global-Contol Register
Multiplexer
–2
Source-Address Register
Destination-Address Reg.
Transfer-Counter Reg.
STRB1 Control Reg.
IOSTRB
CPU1
CPU2
REG1
REG2
IOSTRB
IOSTRB Control Reg.
DMA Channel 1
Global-Control Register
Serial Port
Source-Address Register
Destination-Address Reg.
Transfer-Counter Reg.
FSX0
32
32
40
40
DX0
Serial Port-
32-Bit
Barrel
Shifter
Control Reg.
CLKX0
FSR0
DR0
Multiplier
Receive/Transmit
(R/X)Timer Register
ALU
40
40
Data-Transmit
Register
CLKR0
40
40
Data-Receive
Register
40
Extended-
Precision
Registers
(R0–R7)
40
32
Timer 0
DISP0, IR0, IR1
Global-Control
Register
TCLK0
Timer-Period
Register
ARAU0
ARAU1
BK
Timer-Counter
Register
24
24
24
24
Auxiliary
Registers
(AR0 – AR7)
Timer 1
32
32
Global-Control
Register
32
32
Timer-Period
Register
TCLK1
32
32
Timer-Counter
Register
Other
Registers
(12)
operation
Operation of the SMQ320C32 is identical to the ’320C30 and ’320C31 digital signal processors, with the
exception of an enhanced external memory interface and the addition of two CPU power-management modes.
external memory interface
The SMQ320C32 has a configurable external memory interface with a 24-bit address bus, a 32-bit data bus,
and three independent multi-function strobes. The flexibility of this unique interface enables product designers
to minimize external memory-chip count.
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMQ320C32
DIGITAL SIGNAL PROCESSOR
SGUS027B – APRIL 1998 – REVISED MARCH 1999
external memory interface (continued)
Up to three mutually exclusive memory areas—one program area and two data areas—can be implemented.
Each memory area configuration is independent of the physical memory width and independent of the other
memory areas configurations. See Figure 1.
8-/16-/32-Bit Data in
’C32
8-/16-/32-Bit-Wide Memory
STRB0
STRB1
IOSTRB
32-Bit Program in 16-/32-Bit-
Wide Memory
32-Bit
CPU
PRGW Pin
8-/16-/32-Bit Data in
8-/16-/32-Bit-Wide Memory
32-Bit Program in 16-/32-Bit-
Wide Memory
Memory
Interface
Strobe-
Control
32-Bit Data in 32-Bit-Wide
Memory
Registers
32-Bit Program in 32-Bit-
Wide Memory
Figure 1. ’C32 External Memory Interface
The SMQ320C32 external memory configuration is controlled by a combination of hardware configuration and
memory-mapped control registers and can be reconfigured dynamically. The signals that control external
memory configuration are the PRGW, STRB0, STRB1, and IOSTRB. The signals work as follows:
The SMQ320C32 is a 32-bit microprocessor, that is, the CPU operates on 32-bit program words. The
external memory interface provides the capability of fetching instructions as either 32-bit words or two 16-bit
half words from consecutive addresses. Program memory width is 16 bits if the PRGW signal is high,
32 bits if the PRGW signal is low.
STRB0 and STRB1 are sets of control signals, four signals each, that are mapped to specific ranges of
external memory addresses. When an address within one of these ranges is accessed by a read or write
instruction (CPU or DMA), the corresponding set of control signals is activated. Figure 8 illustrates the
SMQ320C32 memory map, showing the address ranges for which the strobe signals become active.
The behavior of the STRB0 and STRB1 control signals is determined by the contents of the STRB0 and STRB1
control registers.
The STRB0 and STRB1 control registers each have a field that specifies the physical memory width (8, 16, or
32 bits) of the external memory address ranges they control. Another field specifies the data width (8, 16, or
32 bits) of the data contained in those addresses. The values in these fields are not required to match. For
example, a 32-bit-wide physical memory space can be configured to segment each 32-bit word into four
consecutive 8-bit locations, each having its own address.
Each control signal set has two pins (STRBx_B2/A and STRBx_B3/A ) that can act as either byte-enable
–2
–1
(chip-select) pins or address pins, and two dedicated byte-enable (chip-select) pins (STRBx_B0 and
STRBx_B1). The pins’ functions are determined by the physical memory width specified in the corresponding
control register:
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMQ320C32
DIGITAL SIGNAL PROCESSOR
SGUS027B – APRIL 1998 – REVISED MARCH 1999
external memory interface (continued)
For 8-bit-wide physical memory, the STRBx_B2/A and STRBx_B3/A pins function as address pins
–2
–1
(least significant address bits) and the STRBx_B0 pin functions as a byte-enable (chip-select) pin.
STRBx_B1 is unused. See Figure 2.
8-Bit Data Bus
8
8
Data
A14
A13
Data
A14
.
A12
.
.
.
A3
A2
A1
A0
A1
A0
STRB0_B3/A
–1
–2
CS
STRB0_B2/A
NC
STRB0_B1
STRB0_B0
Figure 2. ’C32 With 8-Bit-Wide External Memory
For 16-bit-wide physical memory, the STRBx_B3/A pin functions as an address pin (least significant
–1
address bits). The STRBx_B0 and STRBx_B1 pins function as byte-enable (chip-select) pins.
STRBx_B2/A is unused. See Figure 3.
–2
16-Bit Data Bus
16
8
8
Data
A14
A13
.
Data
Data
A14
.
A14
.
.
.
.
A2
A1
A0
A3
A2
A1
A0
A3
A2
A1
A0
CS
CS
STRB0_B3/A
STRB0_B2/ A
–1
–2
NC
STRB0_B1
STRB0_B0
Figure 3. ’C32 With 16-Bit-Wide External Memory
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMQ320C32
DIGITAL SIGNAL PROCESSOR
SGUS027B – APRIL 1998 – REVISED MARCH 1999
external memory interface (continued)
For 32-bit-wide physical memory, all STRB0 and STRB1 pins function as byte-enable (chip-select) pins.
See Figure 4.
32-Bit Data Bus
32
8
8
8
8
Data
Data
Data
Data
Data
A14
A14
A14
A14
A14
A13
.
.
A13
A13
A13
A13
.
.
.
.
.
.
.
.
A2
A1
A0
A2
A1
A0
A2
A1
A0
A2
A1
A0
A2
A1
A0
CS
CS
CS
CS
STRB0_B3/A
STRB0_B2/A
–1
–2
STRB0_B1
STRB0_B0
Figure 4. ’C32 With 32-Bit-Wide External Memory
For more detailed information and examples, see TMS320C32 Addendum to the TMS320C3x User’s Guide
(literature number SPRU132B) and Interfacing Memory to the SMQ320C32 DSP Application Report (literature
number SPRA040).
The IOSTRB control signal, like STRB0 and STRB1, is also mapped to a specific range of addresses but
itisasinglesignalthatcanaccessonly32-bitdatafrom32-bit-widememory. Itsrangeofaddressesappears
in Figure 8, the SMQ320C32’s memory map. The IOSTRB bus timing is different from the STRB0 and
STRB1 bus timings to accommodate slower I/O peripherals.
examples
Figure 5 and Figure 6 show examples of external memory configurations that can be implemented using the
SMQ320C32’s external memory interface. The first example has a 32-bit-wide external memory with 8- and
16-bit data areas and a 32-bit program area.
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SMQ320C32
DIGITAL SIGNAL PROCESSOR
SGUS027B – APRIL 1998 – REVISED MARCH 1999
examples (continued)
32-Bit-Wide Memory
8-Bit Data
8-Bit Data
8-Bit Data
8-Bit Data
320C32
32-Bit Program
16-Bit Data
16-Bit Data
8
32
8
8
8
32-Bit-Wide Data Bus
Figure 5. ’C32 With 32-Bit-Wide External Memory Configured With 8- and 16-Bit Data Areas and 32-Bit
Program Memory
Figure 6 shows a configuration that can be implemented with a 16-bit external memory. Note that 32-bit data
and program words can be stored and retrieved as half words.
16-Bit-Wide Memory
8-Bit Data
8-Bit Data
320C32
32-Bit Program
16-Bit Data
16
8
8
16-Bit-Wide Data Bus
Figure 6. ’C32 With 16-Bit-Wide External Memory Configured With 8- and 16-Bit Data Areas and a 32-Bit
Program Area
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SMQ320C32
DIGITAL SIGNAL PROCESSOR
SGUS027B – APRIL 1998 – REVISED MARCH 1999
examples (continued)
Figure 7showsonepossibleconfigurationthatcanbeimplementedwith8-bitexternalmemory. Programwords,
which are 32-bit, cannot be executed from 8-bit-wide memory.
8-Bit-Wide Memory
8-Bit Data
320C32
16-Bit Data
8
8
8-Bit-Wide Data Bus
Figure 7. ’C32 With 8-Bit-Wide External Memory Configured With 8- and 16-Bit Data Areas
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SMQ320C32
DIGITAL SIGNAL PROCESSOR
SGUS027B – APRIL 1998 – REVISED MARCH 1999
memory map
Figure 8 depicts the memory map for the SMQ320C32. See the TMS320C32 Addendum to the TMS320C3x
User’s Guide (literature number SPRU132B) for a detailed description of this memory mapping.
0h
0h
Reserved for
Boot-Loader Operations
Reset-Vector Location
FFFh
Boot 1
1000h
1001h
External Memory
STRB0 Active
(8.192M Words)
External Memory
STRB0 Active
(8.188M Words)
7FFFFFh
800000h
7FFFFFh
800000h
Reserved
(32K Words)
Reserved
(32K Words)
807FFFh
808000h
807FFFh
808000h
Peripheral-Bus
Memory-Mapped Registers
(6K-Word Internal)
Peripheral-Bus
Memory-Mapped Registers
(6K-Word Internal)
8097FFh
809800h
8097FFh
809800h
Reserved
(26K Words)
Reserved
(26K Words)
80FFFFh
810000h
80FFFFh
810000h
Boot 2
810001h
External Memory
IOSTRB Active (128K)
(128K Words)
External Memory
IOSTRB Active (128K)
(128K Words)
82FFFFh
830000h
82FFFFh
830000h
Reserved
Reserved
(314.5K Words)
(319.5K Words)
87FDFFh
87FE00h
87FDFFh
87FE00h
Internal Memory
RAM Block 0
RAM Block 0 (256-Word Internal)
(256-Word Internal)
87FEFFh
87FF00h
87FEFFh
87FF00h
Internal Memory
RAM Block 1
(256-Word Internal)
RAM Block 1 (256-Word Internal)
87FFFFh
880000h
87FFFFh
880000h
External Memory
STRB0 Active
(512K Words)
External Memory
STRB0 Active
(512K Words)
8FFFFFh
900000h
8FFFFFh
900000h
Boot 3
External Memory
STRB1 Active
(7.168M Words)
900001h
External Memory
STRB1 Active
(7.168M Words)
FFFFFFh
FFFFFFh
Microprocessor Mode
Microcomputer/Boot-LoaderMode
Figure 8. SMQ320C32 Memory Map
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SMQ320C32
DIGITAL SIGNAL PROCESSOR
SGUS027B – APRIL 1998 – REVISED MARCH 1999
power management
The SMQ320C32 CPU has two power-management modes, IDLE2 and LOPOWER (low power). In IDLE2
mode, no instructions are executed and the CPU, peripherals, and memory retain their previous state while the
external bus output pins are idle. During IDLE2 mode, the H1 clock signal is held high while the H3 clock signal
is held low until one of the four external interrupts is asserted. In the LOPOWER mode, the CPU continues to
execute instructions and the DMA continues to perform transfers, but at a reduced clock rate of the CLKIN
frequency divided by 16 (that is, SMQ320C32 with a 32-MHz CLKIN frequency performs the same as a 2-MHz
SMQ320C32 with an instruction cycle time of 1000 ns or 1 MHz.
bootloader
The SMQ320C32 flexible bootloader loads programs from the serial port, EPROM, or other standard
non-volatile memory device. The boot-loader functionality of the SMQ320C32 is equivalent to that of the
’320C31, and has added modes to handle the data-type sizes and memory widths supported by the external
memory interface. The memory-bootload supports data transfers with and without handshaking. The
handshake mode allows synchronous transfer of programs by using two pins as data-acknowledge and
data-ready signals.
peripherals
The SMQ320C32 peripherals are comprised of one serial port, two timers, and two DMA channels. The serial
port and timers are functionally identical to those in the ’320C31 peripherals. The SMQ320C32 two-channel
DMA coprocessor has user-configurable priorities: CPU, DMA, or rotating between CPU and DMA.
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SMQ320C32
DIGITAL SIGNAL PROCESSOR
SGUS027B – APRIL 1998 – REVISED MARCH 1999
peripherals (continued)
Figure 9 shows the SMQ320C32’s peripheral-bus control-register mapping.
DMA 0 Global Control
DMA 0 Source Address
DMA 0 Destination Address
DMA 0 Transfer Counter
DMA 1 Global Control
DMA 1 Source Address
DMA 1 Destination Address
DMA 1 Transfer Counter
Timer 0 Global Control
Timer 0 Counter
808000h
808004h
808006h
808008h
808009h
808010h
808014h
808016h
808018h
808020h
808024h
808028h
808030h
808034h
808038h
808040h
Timer 0 Period
Timer 1 Global Control
Timer 1 Counter
Timer 1 Period Register
Serial Port Global Control
FSX/DX/CLKX Port Control
FSR/DR/CLKR Port Control
R/X Timer Control
808042h
808043h
808044h
808045h
808046h
R/X Timer Counter
R/X Timer Period
Data Transmit
808048h
Data Receive
Reserved
80804Ch
808050h
80805Fh
808060h
IOSTRB-BusControl
STRB0-BusControl
STRB1-BusControl
Reserved
808064h
808068h
808069h
8097FFh
Figure 9. Peripheral-Bus Memory-Mapped Registers
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SMQ320C32
DIGITAL SIGNAL PROCESSOR
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interrupts
To reduce external logic and simplify the interface, the external interrupts can be either edge- or level-triggered.
Unlike the fixed interrupt-trap vector-table location of the ’320C30 and ’320C31 devices, the SMQ320C32 has
a user-relocatable interrupt-trap vector table. The interrupt-trap vector table must start on a 256-word boundary.
The interrupt and trap vector locations memory mapping is illustrated in Figure 10. The reset vector is fixed to
address 0h as shown in Figure 8.
EA (ITTP) + 00h
EA (ITTP) + 01h
EA (ITTP) + 02h
EA (ITTP) + 03h
EA (ITTP) + 04h
EA (ITTP) + 05h
EA (ITTP) + 06h
EA (ITTP) + 07h
EA (ITTP) + 08h
EA (ITTP) + 09h
EA (ITTP) + 0Ah
EA (ITTP) + 0Bh
EA (ITTP) + 0Ch
EA (ITTP) + 0Dh
EA (ITTP) + 1Fh
EA (ITTP) + 20h
Reserved
INT0
INT1
INT2
INT3
XINT0
RINT0
Reserved
Reserved
TINT0
TINT1
DINT0
DINT1
Reserved
TRAP0
.
.
.
.
EA (ITTP) + 3Bh
EA (ITTP) + 3Ch
EA (ITTP) + 3Dh
EA (ITTP) + 3Eh
EA (ITTP) + 3Fh
TRAP27
TRAP28
TRAP29
TRAP30
TRAP31
Figure 10. Reset, Interrupt, and Trap Vector/Branches Memory-Map Locations
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SMQ320C32
DIGITAL SIGNAL PROCESSOR
SGUS027B – APRIL 1998 – REVISED MARCH 1999
†
absolute maximum ratings over specified temperature ranges (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
CC
Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Output voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
O
Continuous power dissipation (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.95 W
Operating case temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
C
Storage temperature, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to V
.
SS
2. This value calculated for the ’C32-40. Actual operating power is less. This value was obtained under specially produced worst-case
test conditions which are not sustained during normal device operation. These conditions consist of continuous parallel writes of
a checkerboard pattern to the external bus at the maximum rate possible. See normal (I ) current specification in the electrical
DD
characteristics table and see the Calculation of TMS320C30 Power Dissipation Application Report (literature number SPRA020).
recommended operating conditions (see Note 3)
‡
MIN
NOM
MAX
UNIT
V
V
V
Supply voltage (DV , V
)
4.75
5
0
5.25
DD
DD DDL
Supply voltage (CV , V
, IV , DV , V
)
V
SS
SS SSL SS SS SUBS
CLKIN
2.6
2
V
V
+ 0.3*
V
DD
V
IH
High-level input voltage
All other inputs
+ 0.3*
V
DD
V
Low-level input voltage
High-level output current
Low-level output current
– 0.3*
0.8
V
IL
I
I
– 300
2
µA
mA
°C
OH
OL
T
C
Operating case temperature (see Note 4)
– 55
125
‡
All nominal values are at V = 5 V, T (ambient-air temperature)= 25°C.
DD
A
* This parameter is not production tested.
NOTE 3: All input and output voltage levels are TTL compatible.
NOTE 4:
T
C
MAX at maximum rated operating conditions at any point on case. T MIN at initial (time zero) power-up.
C
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SMQ320C32
DIGITAL SIGNAL PROCESSOR
SGUS027B – APRIL 1998 – REVISED MARCH 1999
electrical characteristics over recommended ranges of supply voltage (unless otherwise
†
noted)
PARAMETER
High-level output voltage
TEST CONDITIONS
MIN NOM
MAX
UNIT
V
V
V
V
V
V
= MIN,
= MIN,
= MAX
I
I
= MAX
= MAX
2.4
3
OH
DD
DD
DD
OH
Low-level output voltage
High-impedance state output current
Input current
0.3
0.8
20
V
OL
OL
I
I
– 20
– 10
µA
µA
OZ
V = V
I
to V
DD
10
I
SS
‡
‡
f = 50 MHz
x
200
225
50
425
475
T
= 25 °C,
V
= MAX,
A
DD
mA
‡
f = MAX
x
I
Supply current (see Note 5)
f = 60 MHz
x
DD
Standby
CLKIN
IDLE2,
CLKIN shut off
µA
25
15*
20*
C
C
Input capacitance
Output capacitance
pF
pF
All other
inputs
I
o
†
‡
All nominal values are at V
= 5 V, T = 25°C.
A
DD
f is the input clock frequency.
x
* This parameter is not production tested.
NOTE 5: Actual operating current is less than this maximum value (see Note 2).
PARAMETER MEASUREMENT INFORMATION
I
OL
Output
Under
Test
Tester Pin
Electronics
V
Load
C
T
I
OH
Where: I
I
= 2 mA (all outputs)
= 300 µA (all outputs)
OL
OH
V
= Selected to emulate 50-Ω termination (typical value = 1.54 V)
Load
C
= 80-pF typical load-circuit capacitance
T
Figure 11. Test Load Circuit
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SMQ320C32
DIGITAL SIGNAL PROCESSOR
SGUS027B – APRIL 1998 – REVISED MARCH 1999
PARAMETER MEASUREMENT INFORMATION (CONTINUED)
signal-transition levels
TTL-level outputs are driven to a minimum logic-high level of 2.4 V and to a maximum logic-low level of 0.6 V.
Output transition times are specified in the following paragraph.
For a high-to-low transition on a TTL-compatible output signal, the level at which the output is said to be no
longer high is 2 V and the level at which the output is said to be low is 1 V. For a low-to-high transition, the level
at which the output is said to be no longer low is 1 V and the level at which the output is said to be high is 2 V
(see Figure 12).
2.4 V
2 V
1 V
0.6 V
Figure 12. TTL-Level Outputs
Transition times for TTL-compatible inputs are specified as follows. For a high-to-low transition on an input
signal, the level at which the input is said to be no longer high is 2 V and the level at which the input is said to
be low is 0.8 V. For a low-to-high transition on an input signal, the level at which the input is said to be no longer
low is 0.8 V and the level at which the input is said to be high is 2 V (see Figure 13).
2 V
0.8 V
Figure 13. TTL-Level Inputs
19
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SMQ320C32
DIGITAL SIGNAL PROCESSOR
SGUS027B – APRIL 1998 – REVISED MARCH 1999
PARAMETER MEASUREMENT INFORMATION (CONTINUED)
timing parameter symbology
Timing parameter symbols used in this document are in accordance with JEDEC Standard 100-A. Unless
otherwise noted, in order to shorten the symbols, pin names and other related terminology have been
abbreviated as follows:
A23–A0 when the physical-memory-width-bit field of the STRBx control register is set to 32 bits
A23–A0 and STRBx_B3/A when the physical-memory-width-bit field of the STRBx control register is
–1
A
set to 16 bits
A23–A0, STRBx_B3/A
control register is set to 8 bits
and STRBx_B2/A when the physical-memory-width-bit field of the STRBx
–2
–1,
CI
CLKIN
RDY RDY
D
H
D(31–0)
H1, H3
IOS IOSTRB
P
t
t
c(H)
Q
c(CI)
RW R/W
STRBx_B(3–0) when the physical-memory-width-bit field of the STRBx control register is set to 32 bits
S
STRBx_B(1–0) when the physical-memory-width-bit field of the STRBx control register is set to 16 bits
STRBx_B0 when the physical-memory-width-bit field of the STRBx control register is set to 8 bits
XF
XF0 or XF1
20
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SMQ320C32
DIGITAL SIGNAL PROCESSOR
SGUS027B – APRIL 1998 – REVISED MARCH 1999
timings for CLKIN [Q = t
] (see Figure 14)
c(CI)
’320C32-50
’320C32-60
TEST
CONDITIONS
NO.
UNIT
MIN
MAX
MIN
MAX
†
1
2
3
4
5
t
t
t
t
t
Fall time, CLKIN
5*
4*
ns
ns
ns
ns
ns
f(CI)
†
Pulse duration, CLKIN low
Pulse duration, CLKIN high
Rise time, CLKIN
Q = min
Q = min
7
6
w(CIL)
†
8
6†
w(CIH)
†
5*
4*
r(CI)
†
Cycle time, CLKIN
20
303 16.67
303
c(CI)
†
Minimum CLKIN high-pulse duration at 3.3 MHz is 10 ns.
* This parameter is not production tested.
5
4
1
CLKIN
3
2
Figure 14. CLKIN Timing
switching characteristics for H1 and H3 over recommended operating conditions (unless
otherwise noted) (see Figure 15)
’320C32-50
’320C32-60
TEST
CONDITIONS
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
6
t
t
t
t
t
t
Fall time, H1/H3
3
3
ns
ns
ns
ns
ns
ns
f(H)
7
Pulse duration, H1/H3 low
Pulse duration, H1/H3 high
Rise time, H1/H3
Q–5
Q–6
Q–4
Q–5
w(HL)
w(HH)
r(H)
8
9
3
4
3
4
9.1
10
Delay time, H1/H3 low to H1/H3 high
Cycle time, H1/H3
0*
0*
d(HL-HH)
c(H)
40
606 33.33
606
* This parameter is not production tested.
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SMQ320C32
DIGITAL SIGNAL PROCESSOR
SGUS027B – APRIL 1998 – REVISED MARCH 1999
switching characteristics for H1 and H3 (see Figure 15) (continued)
10
6
9
H1
8
7
9.1
9.1
H3
8
9
6
7
10
Figure 15. H1/H3 Timing
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SMQ320C32
DIGITAL SIGNAL PROCESSOR
SGUS027B – APRIL 1998 – REVISED MARCH 1999
memory-read-cycle and memory-write-cycle timing (STRBx) (see Figure 16 and Figure 17)
’320C32-50
’320C32-60
NO.
UNIT
MIN
0*
0*
0*
0*
10
0
MAX
MIN
0*
0*
0*
0*
10
0
MAX
11
12
13
14
15
16
17
18
19
20
21
22
t
t
t
t
t
t
t
t
t
t
t
t
Delay time, H1 low to STRBx low
Delay time, H1 low to STRBx high
Delay time, H1 high to R/W low (read)
Delay time, H1 low to A valid
9
9
9
9
7
7
8
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
d(H1L-SL)
d(H1L-SH)
d(H1H-RWL)
d(H1L-A)
su(D)R
Setup time, D valid before H1 low (read)
Hold time, D after H1 low (read)
h(D)R
Setup time, RDY before H1 low
19
0
17
0
su(RDY)
h(RDY)
Hold time, RDY after H1 low
Delay time, H1 high to R/W high (write)
Valid time, D after H1 low (write)
9
8
d(H1H-RWH)
v(D)W
14
12
Hold time, D after H1 high (write)
Delay time, H1 high to A valid on back-to-back write cycles
0*
0*
h(D)W
9
8
d(H1H-A)
* This parameter is not production tested.
H3
H1
11
14
12
†
STRBx
R/W
15
13
A
D
16
18
17
RDY
†
STRBx remains low during back-to-back operations.
Figure 16. Memory-Read-Cycle Timing
23
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SMQ320C32
DIGITAL SIGNAL PROCESSOR
SGUS027B – APRIL 1998 – REVISED MARCH 1999
memory-read-cycle and memory-write-cycle timing (STRBx) (see Figure 16 and Figure 17)
(continued)
H3
H1
11
12
STRBx
13
19
R/W
A
22
14
20
21
D
18
RDY
17
Figure 17. Memory-Write-Cycle Timing
24
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMQ320C32
DIGITAL SIGNAL PROCESSOR
SGUS027B – APRIL 1998 – REVISED MARCH 1999
memory-read-cycle timing using IOSTRB (see Figure 18)
’320C32-50
’320C32-60
NO.
UNIT
MIN
0*
0*
0*
0*
10
0
MAX
MIN
0*
0*
0*
0*
9
MAX
11.1
12.1
13.1
14.1
15.1
16.1
17.1
18.1
t
t
t
t
t
t
t
t
Delay time, H3 low to IOSTRB low
Delay time, H3 low to IOSTRB high
Delay time, H1 low to R/W high
Delay time, H1 low to A valid
Setup time, D before H1 high
Hold time, D after H1 high
9
9
9
9
8
8
8
8
ns
ns
ns
ns
ns
ns
ns
ns
d(H3L-IOSL)
d(H3L-IOSH)
d(H1L-RWL)
d(H1L-A)
su(D)R
0
h(D)R
Setup time, RDY before H1 high
Hold time, RDY after H1 high
8
7
su(RDY)
0
0
h(RDY)
* This parameter is not production tested.
H3
H1
11.1
12.1
IOSTRB
R/W
13.1
†
23
14.1
A
D
15.1
16.1
17.1
18.1
RDY
†
See Figure 19 and accompanying table
Figure 18. Memory-Read-Cycle Timing Using IOSTRB
25
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SMQ320C32
DIGITAL SIGNAL PROCESSOR
SGUS027B – APRIL 1998 – REVISED MARCH 1999
memory-write-cycle timing using IOSTRB (see Figure 19)
’320C32-50
’320C32-60
NO.
UNIT
MIN
MAX
MIN
MAX
23
24
25
t
t
t
Delay time, H1 low to R/W low
Valid time, D after H1 high
Hold time, D after H1 low
0*
9
0*
8
ns
ns
ns
d(H1L-RWH)
14
12
v(D)W
0
0
h(D)W
* This parameter is not production tested.
H3
H1
†
11.1
†
12.1
IOSTRB
†
13.1
†
23
R/W
†
14.1
A
D
24
25
†
17.1
†
18.1
RDY
†
See Figure 18 and accompanying table
Figure 19. Memory-Write-Cycle Timing Using IOSTRB
26
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMQ320C32
DIGITAL SIGNAL PROCESSOR
SGUS027B – APRIL 1998 – REVISED MARCH 1999
timing for XF0 and XF1 when executing LDFI or LDII (see Figure 20)
’320C32-50
’320C32-60
NO.
UNIT
MIN
MAX
MIN
MAX
11
38
39
40
t
t
t
Delay time, H3 high to XF0 low
Setup time, XF1 before H1 low
Hold time, XF1 after H1 low
12
ns
ns
ns
d(H3H-XF0L)
9
0
8
0
su(XF1)
h(XF1)
Fetch
LDFI or LDII
Decode
Read
Execute
H3
H1
STRBx
R/W
A
D
RDY
38
XF0
XF1
39
40
Figure 20. XF0 and XF1 When Executing LDFI or LDII
27
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMQ320C32
DIGITAL SIGNAL PROCESSOR
SGUS027B – APRIL 1998 – REVISED MARCH 1999
†
timing for XF0 when executing STFI or STII (see Figure 21)
’320C32-50
MIN MAX
12
’320C32-60
MIN MAX
11
NO.
UNIT
41
t
Delay time, H3 high to XF0 high
ns
d(H3H-XF0H)
†
XF0 is always set high at the beginning of the execute phase of the interlock-store instruction. When no pipeline conflicts occur, the address of
the store is driven at the beginning of the execute phase of the interlock-store instruction. However, if a pipeline conflict prevents the store from
executing, the address of the store is not driven until the store can execute.
Fetch
STFI or STII
Decode
Read
Execute
H3
H1
STRBx
R/W
A
D
RDY
XF0
41
Figure 21. XF0 When Executing a STFI or STII
28
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMQ320C32
DIGITAL SIGNAL PROCESSOR
SGUS027B – APRIL 1998 – REVISED MARCH 1999
timing for XF0 and XF1 when executing SIGI (see Figure 22)
’320C32-50
’320C32-60
NO.
UNIT
MIN
MAX
MIN
MAX
41.1
42
t
t
t
t
Delay time, H3 high to XF0 low
Delay time, H3 high to XF0 high
Setup time, XF1 before H1 low
Hold time, XF1 after H1 low
12
12
11
11
ns
ns
ns
ns
d(H3H-XF0L)
d(H3H-XF0H)
su(XF1)
43
9
0
8
0
44
h(XF1)
Fetch
SIGI
Decode
Read
Execute
H3
H1
41.1
42
43
XF0
44
XF1
Figure 22. XF0 and XF1 When Executing SIGI
timing for loading XF register when configured as an output pin (see Figure 23)
’320C32-50
’320C32-60
MIN MAX
11
NO.
45
UNIT
MIN
MAX
t
Valid time, H3 high to XF valid
12
ns
v(H3H-XF)
Fetch Load
Instruction
Decode
Read
Execute
H3
H1
†
1 or 0
OUTXF Bit
45
XFx
†
OUTXFx represents either bit 2 or 6 of the IOF register.
Figure 23. Loading XF Register When Configured as an Output Pin
29
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMQ320C32
DIGITAL SIGNAL PROCESSOR
SGUS027B – APRIL 1998 – REVISED MARCH 1999
timing of XF changing from output to input mode (see Figure 24)
’320C32-50
MIN MAX MIN
12*
’320C32-60
MAX
11*
NO.
UNIT
46
47
48
t
t
t
Hold time, XF after H3 high
Setup time, XF before H1 low
Hold time, XF after H1 low
ns
ns
ns
h(H3H-XF01)
9
8
0
su(XF)
0
h(XF)
* This parameter is not production tested.
Buffers Go
from Ouput
to Input
Synchronizer
Execute
Load of IOF
H3
Value on Pin
Seen in IOF
Delay
H1
47
48
†
I/OXFx Bit
46
XFx
Output
†
INXFx Bit
Data
Sampled
Data
Seen
†
I/OXFx represents either bit 1 or bit 5 of the IOF register, and INXFx represents either bit 3 or bit 7 of the IOF register.
Figure 24. Change of XF From Output to Input Mode
30
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMQ320C32
DIGITAL SIGNAL PROCESSOR
SGUS027B – APRIL 1998 – REVISED MARCH 1999
timing of XF changing from input to output mode (see Figure 25)
’320C32-50
MIN MAX
17
’320C32-60
MIN MAX
15
NO.
UNIT
49
t
Delay time, H3 high to XF switching from input to output
ns
d(H3H-XFIO)
Execution of
Load of IOF
H3
H1
†
I/OXFx Bit
49
XFx
I/OXFx represents either bit 1 or bit 5 of the IOF register.
†
Figure 25. Change of XF From Input to Output Mode
31
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMQ320C32
DIGITAL SIGNAL PROCESSOR
SGUS027B – APRIL 1998 – REVISED MARCH 1999
timing for RESET [Q = t
] (see Figure 26)
c(CI)
’320C32-50
’320C32-60
NO.
UNIT
MIN
10
2
MAX
MIN
17
2
MAX
50
51
52
t
t
t
Setup time, RESET before CLKIN low
Delay time, CLKIN high to H1 high
Delay time, CLKIN high to H1 low
Q*
10
10
Q*
10
10
ns
ns
ns
su(RESET)
d(CLKINH-H1H)
d(CLKINH-H1L)
2
2
Setup time, RESET high before H1 low and after ten H1 clock
cycles
53
t
7
6
ns
su(RESETH-H1L)
54
55
t
t
t
t
t
t
t
Delay time, CLKIN high to H3 low
2
2
10
10
12*
9*
2
2
10
10
11*
9*
ns
ns
ns
ns
ns
ns
ns
d(CLKINH-H3L)
d(CLKINH-H3H)
dis(H1H-D)
Delay time, CLKIN high to H3 high
56
Disable time, H1 low to D in the high-impedance state
Disable time, H3 low to A in the high-impedance state
Delay time, H3 high to control signals high
Delay time, H1 low to R/W high
57
dis(H3HL-A)
58.1
58.2
59
8*
7*
d(H3H-CONTROLH)
d(H1H-RWH)
8*
7*
Delay time, H1 high to IACK high
8*
7*
d(H1H-IACKH)
Disable time, RESET low to asynchronous reset signals in
the high-impedance state
60
t
17*
14*
ns
dis(RESETL-ASYNCH)
* This parameter is not production tested.
CLKIN
50
†‡
RESET
51
54
52
53
H1
H3
10 H1 Clock Cycles
56
55
§
§
D
A
57
58.1
Control
¶
Signals
58.2
R/W
59
IACK
60
Asynchronous
Reset Signals
#
†
‡
§
RESETisanasynchronousinputandcanbeassertedatanypointduringaclockcycle. Ifthespecifiedtimingsaremet, theexactsequenceshown
occurs; otherwise, an additional delay of one clock cycle can occur.
TheR/Woutputisplacedinthehigh-impedancestateduringresetandcanbeprovidedwitharesistivepullup, nominally18–22kΩ,ifundesirable
spurious writes can occur when these outputs go low.
In microprocessor mode (MCBL /MP = 0), reset vector is fetched twice with seven software wait states each. In microcomputer mode
(MCBL / MP = 1), the reset vector is fetched two times, with no software wait states.
Control signals include STRBx and IOSTRB.
¶
#
Asynchronous reset signals include XF0/1, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, and TCLKx.
Figure 26. RESET Timing
32
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMQ320C32
DIGITAL SIGNAL PROCESSOR
SGUS027B – APRIL 1998 – REVISED MARCH 1999
timing for INT3 –INT0 interrupt response [P = t
] (see Figure 27)
c(H)
’320C32-50
’320C32-60
NO.
UNIT
MIN
MAX
MIN
MAX
61
t
t
t
Setup time, INT3–INT0 before H1 low
10
8
ns
ns
ns
su(INT)
w(INT)
w(INT)
Pulseduration of interrupt to assure only one interrupt seen for level-triggered
interrupts
62.1
62.2
P
2P*
P
2P*
Pulse duration of interrupt for edge-triggered interrupts
P*
P*
* This parameter is not production tested.
Reset or
Interrupt
Vector Read
Fetch First
Instruction of
Service Routine
H3
H1
61
INT3–INT0 Pin
62.1
INT3–INT0 Flag
62.2
A
Vector
Address
First
Instruction
Address
D
Figure 27. INT3–INT0 Interrupt-Response Timing
33
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMQ320C32
DIGITAL SIGNAL PROCESSOR
SGUS027B – APRIL 1998 – REVISED MARCH 1999
timing for IACK (see Notes 6, 7, and Figure 28)
’320C32-50
MIN MAX
’320C32-60
MIN MAX
NO.
UNIT
63
64
t
t
Delay time, H1 high to IACK low
Delay time, H1 high to IACK high
7
6
ns
ns
d(H1H-IACKL)
7
6
d(H1H-IACKH)
NOTES: 6. IACK is active for the entire duration of the bus cycle and is extended if the bus cycle utilizes wait states.
7. IACK goes active on the first half-cycle (H1 rising) of the decode phase of the IACK instruction and goes inactive at the first half-cycle
(H1 rising) of the read phase of the IACK instruction. Because of pipeline conflicts, IACK remains low for one cycle even if thedecode
phase of the IACK instruction is extended.
Decode IACK
Instruction
Fetch IACK
Instruction
IACK Data
Read
H3
H1
63
64
IACK
A
D
Figure 28. IACK Timing
34
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMQ320C32
DIGITAL SIGNAL PROCESSOR
SGUS027B – APRIL 1998 – REVISED MARCH 19998
serial-port timing
serial-port timing [P = t
] (see Figure 29 and Figure 30)
c(H)
’320C32-50
MIN
’320C32-60
UNIT
NO.
MAX
MIN
MAX
Delay time, H1 high to internal
CLKX/R high/low
65
66
t
t
10
8
ns
ns
d(H1-SCK)
CLKX/R ext
2.6P
2P
2.6P
2P
Cycle time,
CLKX/R
c(SCK)
32
(2 )P
32
CLKX/R int
(2 )P
CLKX/R ext
CLKX/R int [t
P + 10
/2]–5
P + 10
/2]–5
Pulse duration,
CLKX/R high/low
67
t
ns
w(SCK)
[t
/2]+5 [t
c(SCK)
[t
/2]+5
c(SCK)
c(SCK)
c(SCK)
68
69
t
t
Rise time, CLKX/R
Fall time, CLKX/R
6
6
5
5
ns
ns
r(SCK)
f(SCK)
CLKX ext
CLKX int
CLKR ext
CLKR int
CLKR ext
CLKR int
24
16
20
15
Delay time, CLKX
to DX valid
70
71
72
t
t
t
ns
ns
ns
d(DX)
su(DR)
h(DR)
9
8
Setup time, DR
before CLKR low
17
7
15
6
Hold time, DR
from CLKR low
0
0
Delay time, CLKX
to internal FSX
high/low
CLKX ext
CLKX int
22
15
20
14
73
74
75
t
t
t
ns
ns
ns
d(FSX)
su(FSR)
h(FS)
CLKR ext
CLKR int
7
7
6
6
Setup time, FSR
before CLKR low
Hold time, FSX/R
input from
CLKX/R low
CLKX/R ext
CLKX/R int
CLKX ext
7
0
6
0
Setup time,
external FSX
before CLKX high
8–P
21–P
[t
/2]–10*
/2*
8–P
21–P
[t
/2]–10*
c(SCK)
c(SCK)
76
77
t
t
ns
ns
su(FSX)
*
/2
CLKX int
t
t
c(SCK)
c(SCK)
Delay time, CLKX
to first DX bit, FSX
precedes CLKX
high
CLKX ext
CLKX int
24*
14*
24*
20*
12*
20*
d(CH-DX)V
Delay time, FSX to first DX bit,
CLKX precedes FSX
78
79
t
t
ns
ns
d(FSX-DX)V
Delay time, CLKX high to DX in
the high-impedance state
following last data bit
14*
12*
d(DXZ)
* This parameter is not production tested.
35
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMQ320C32
DIGITAL SIGNAL PROCESSOR
SGUS027B – APRIL 1998 – REVISED MARCH 19998
serial-port timing
66
65
H1
65
67
67
72
CLKX/R
69
68
79
77
70
Bit n-1
Bit n-2
Bit 0
DX
DR
71
Bit n-1
Bit n-2
FSR
74
73
73
75
FSX(INT)
FSX(EXT)
75
76
NOTES: A. Timing diagrams show operations with CLKXP = CLKRP = FSXP = FSRP = 0.
B. Timing diagrams depend upon the length of the serial-port word, where n = 8, 16, 24, or 32 bits, respectively.
Figure 29. Fixed Data-Rate-Mode Timing
CLKX/R
73
FSX(INT)
78
76
FSX(EXT)
DX
70
79
77
Bit n-1
75
Bit n-2
Bit n-3
Bit 0
FSR
DR
74
Bit n-1
Bit n-2
Bit n-3
71
72
NOTES: A. Timing diagrams show operation with CLKXP = CLKRP = FSXP = FSRP = 0.
B. Timing diagrams depend upon the length of the serial-port word, where n = 8, 16, 24, or 32 bits, respectively.
C. The timings that are not specified expressly for the variable data-rate mode are the same as those that are specified for the fixed
data-rate mode.
Figure 30. Variable Data-Rate-Mode Timing
36
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMQ320C32
DIGITAL SIGNAL PROCESSOR
SGUS027B – APRIL 1998 – REVISED MARCH 19998
timing for HOLD/HOLDA [P = t
] (see Note 8 and Figure 31)
c(H)
’320C32-50
’320C32-60
NO.
UNIT
MIN
10
MAX
MIN
8
MAX
80
81
t
t
t
t
t
t
Setup time, HOLD before H1 low
Valid time, HOLDA after H1 low
ns
ns
ns
ns
ns
ns
su(HOLD)
v(HOLDA)
w(HOLD)
0*
7
0*
6
82
Pulse duration, HOLD low
2P
2P
83
Pulse duration, HOLDA low
P–5*
0*
P–5*
0*
w(HOLDA)
d(H1L-SH)H
d(H1H-IOS)H
84
Delay time, H1 low to STRBx high for a HOLD
Delay time, H1 high to IOSTRB high for a HOLD
7*
7*
6*
6*
84.1
0*
0*
Disable time, H1 low to STRBx or IOSTRB (in the high-impedance
state)
85
t
0*
8*
0*
7*
ns
dis(H1L-S)
86
87
88
89
90
91
t
t
t
t
t
t
Enable time, H1 low to STRBx or IOSTRB active
Disable time, H1 low to R/W in the high-impedance state
Enable time, H1 low to R/W (active)
0*
0*
0*
0*
0*
0*
7*
8*
0*
0*
0*
0*
0*
0*
6*
7*
ns
ns
ns
ns
ns
ns
en(H1L-S)
dis(H1L-RW)
en(H1L-RW)
dis(H1L-A)
en(H1L-A)
dis(H1H-D)
7*
6*
Disable time, H1 low to A in the high-impedance state
Enable time, H1 low to A valid
8*
7*
12*
8*
11*
7*
Disable time, H1 high to D disabled in the high-impedance state
* This parameter is not production tested.
NOTE 8: HOLD is an asynchronous input and can be asserted at any point during a clock cycle. If the specified timings are met, the exact
sequenceshownoccurs;otherwise, anadditionaldelay of one clock cycle can occur. TheNOHOLDbitoftheprimary-bit-controlregister
overwrites the HOLD signal.
H3
H1
80
80
82
HOLD
81
81
83
HOLDA
(see Note A)
84
85
86
STRBx
IOSTRB
R/W
A
85
86
88
84.1
87
90
89
91
D
Write Data
NOTE A: HOLDA goes low in response to HOLD going low and continues to remain low until one H1 cycle after HOLD goes back high.
Figure 31. HOLD/HOLDA Timing
37
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMQ320C32
DIGITAL SIGNAL PROCESSOR
SGUS027B – APRIL 1998 – REVISED MARCH 19998
timing of peripheral pin configured as general-purpose I/O (see Figure 32)
’320C32-50
MIN MAX
’320C32-60
MIN MAX
NO.
UNIT
92
93
94
t
t
t
Setup time, general-purpose input before H1 low
Hold time, general-purpose input after H1 low
Delay time, general-purpose output after H1 high
9
8
ns
ns
ns
su(GPIOH1L)
h(GPIOH1L)
d(GPIOH1H)
0
0
10
8
H3
H1
93
94
92
94
Peripheral Pin
(see Note A)
NOTE A: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLKx. The modes of these pins are defined by the contents
of internal control registers associated with each peripheral.
Figure 32. Peripheral-Pin General-Purpose I/O Timing
timing of peripheral pin changing from general-purpose output to input mode (see Figure 33)
’320C32-50
’320C32-60
NO.
UNIT
MIN
MAX
12*
MIN
MAX
95
96
97
t
t
t
Hold time, after H1 high
11*
ns
ns
ns
h(H1H)
Setup time, peripheral pin before H1 low
Hold time, peripheral pin after H1 low
9
0
8
0
su(GPI0H1L)
h(GPIOH1L)
* This parameter is not production tested.
Value on
Pin Seen
in
Execute Store
of Peripheral
Control
Buffers
Go From
Output to Input
Synchronizer Delay
Peripheral
Control Register
Register
H3
H1
I/O
96
Control Bit
97
95
Peripheral Pin
(see Note A)
Output
Data Bit
Data Sampled
Data
Seen
NOTE A: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLKx. The modes of these pins are defined by the contents
of internal control registers associated with each peripheral.
Figure 33. Timing of Peripheral Pin Changing From General-Purpose Output to Input Mode
38
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMQ320C32
DIGITAL SIGNAL PROCESSOR
SGUS027B – APRIL 1998 – REVISED MARCH 19998
timing of peripheral pin changing from general-purpose input to output mode (see Figure 34)
’320C32-50
MIN MAX
10
’320C32-60
MIN MAX
NO.
UNIT
98
t
Delay time, H1 high to peripheral pin switching from input to output
8
ns
d(GPIOH1H)
Execution of Store of
Peripheral Control
Register
H3
H1
I/O Control Bit
98
Peripheral Pin
(see Note A)
NOTE A: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLKx. The modes of these pins are defined by the contents
of internal control registers associated with each peripheral.
Figure 34. Timing of Peripheral Pin Changing From General-Purpose Input-to-Output Mode
39
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMQ320C32
DIGITAL SIGNAL PROCESSOR
SGUS027B – APRIL 1998 – REVISED MARCH 19998
timing for timer pin [P = t
] (see Figure 35)
c(H)
’320C32-50
’320C32-60
NO.
UNIT
MIN
MAX
MIN
MAX
Setup time, TCLK external
before H1 low
99
t
t
t
8
6
ns
ns
ns
su(TCLKH1L)
h(TCLKH1L)
d(TCLKH1H)
Hold time, TCLK external after
H1 low
100
101
0
0
Delay time, H1 high to TCLK
internal valid
9
8
Cycle time,
TCLK cycle
time
TCLK external
TCLK internal
2.6P*
2P
2.6P*
2P
102
103
t
t
ns
ns
c(TCLK)
w(TCLK)
32
(2 )P*
32
(2 )P*
Pulse duration,
TCLK
high / low
TCLK external
TCLK internal [t
P + 10*
/2]–5 [t
P + 10*
/2]–5 [t
/2]+5 [t
c(TCLK)
/2]+5
c(TCLK)
c(TCLK)
c(TCLK)
* This parameter is not production tested.
NOTE: Timing parameters 99 and 100 are applicable for a synchronous input clock. Timing parameters 102 and 103 are applicable for an
asynchronous input clock.
H3
H1
100
99
101
101
TCLKx
103
102
Figure 35. Timing for Timer Pin
40
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMQ320C32
DIGITAL SIGNAL PROCESSOR
SGUS027B – APRIL 1998 – REVISED MARCH 19998
timing for SHZ pin [Q = t
] (see Figure 36)
c(CI)
’320C32-50
’320C32-60
NO.
UNIT
MIN
MAX
2Q*
MIN
MAX
2Q*
104
t
Disable time, SHZ low to all O, I/O pins in the high-impedance state
0*
0*
ns
dis(SHZ)
* This parameter is not production tested.
H3
H1
SHZ
(see Note A)
104
All I/O Pins
NOTE A: EnablingSHZ destroys ’C32 register and memory contents. Assert SHZ = 1 and reset the ’C32 to restore it to a knowncondition.
Figure 36. SHZ Pin Timing
Table 1. Thermal Resistance Characteristics for PCM package
PARAMETER
MIN
MAX
UNIT
R
R
Junction-to-free-air
Junction-to-case
39 °C/W
ΘJA
ΘJC
10.0 °C/W
41
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SMQ320C32
DIGITAL SIGNAL PROCESSOR
SGUS027B – APRIL 1998 – REVISED MARCH 19998
MECHANICAL DATA
PCM(S-PQFP-G***)
PLASTIC QUAD FLATPACK
144 PIN SHOWN
108
73
0,38
0,22
72
109
0,13
M
0,65 TYP
NO. OF PINS***
A
22,75 TYP
25,35 TYP
144
160
144
37
0,16 NOM
1
36
3,60
3,20
A
28,20
27,80
SQ
SQ
31,45
30,95
0,25 MIN
0°–7°
1,03
0,73
Seating Plane
0,10
4,10 MAX
(see Note C)
4040015/A–10/93
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-022
D. The 144PCM is identical to 160PCM except that 4 leads per corner are removed.
E. Foot length is measured from lead tip to a position on backside of lead 0,25 mm above seating plane (gage plane)
F. Preliminary drawing
42
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