SN0064HBE_技术文档

LMK04832-SP

ZHCSLT2C –MAY 2020 –REVISED NOVEMBER 2022

LMK04832-SP 符合JESD204B 标准的航天级、超低噪声、双环路时钟抖动清除

器

1 特性

3 说明

• SMD #5962R1723701VXC

LMK04832-SP 是支持 JEDEC JESD204B 的高性能时

钟调节器，适用于航天应用。

– 电离辐射总剂量100krad（无ELDRS）

– SEL 抗扰度> 120MeV × cm²/mg

– SEFI 抗扰度> 120MeV × cm²/mg

• 最高时钟输出频率：3255MHz

• 多模式：双PLL、单PLL 和时钟分配

• 6GHz 外部VCO 或分配输入

PLL2 可以配置 14 个时钟输出以驱动 7 个 JESD204B

转换器或其他逻辑器件（使用器件和 SYSREF 时

钟）。SYSREF 可以通过直流和交流耦合提供。14 个

输出中的每一个输出都可以单独配置为用于传统计时系

统的高性能输出（不限于JESD204B 应用）。

• 超低噪声（2500MHz 时）：

LMK04832-SP 可以配置在双 PLL、单 PLL 或时钟分

配模式下工作（使用或不使用 SYSREF 生成或重新计

时）。PLL2 可以使用内部或外部VCO 工作。

– 54fs RMS 抖动（12kHz 至20MHz）

– 64fs RMS 抖动（100Hz 至20MHz）

– –157.6dBc/Hz 本底噪声

• 超低噪声（3200MHz 时）：

高性能与多种特性（如功耗和性能权衡调节、双

VCO、动态数字延迟和保持）相结合，使 LMK04832-

SP 能够提供灵活的高性能时钟树。

– 61fs RMS 抖动（12kHz 至20MHz）

– 67fs RMS 抖动（100Hz 至100MHz）

– –156.5dBc/Hz 本底噪声

• PLL2

LMK04832-SP 采用 10.9mm × 10.9mm、64 引脚

CFP 封装。

– –230dBc/Hz PLL FOM

– –128dBc/Hz PLL 1/f

– 相位检测器频率高达320MHz

– 两个集成VCO：2440MHz 至2600MHz

和2945MHz 至3255MHz

封装信息

封装⁽¹⁾

器件型号

SN0064HBE

类型

机械采样⁽²⁾

64 引脚陶瓷，

带非导电连接杆

(HBE0064B)

工程样片⁽³⁾

耐辐射加固

LMK04832W/EM

• 多达14 个差分器件时钟

5962R1723701VXC

– CML、LVPECL、LCPECL、HSDS、LVDS 和

2xLVCMOS 可编程输出

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

• 最多1 个缓冲VCXO/XO 输出

(2) 这些器件只是封装，不包含裸片；它们仅用于评估目的

(3) 这些器件不适用于生产或飞行系统用途，仅用于工程评估。

– LVPECL、LVDS、2xLVCMOS 可编程输出

• 1-1023 CLKout 分频器

• 1-8191 SYSREF 分频器

• SYSREF 时钟25ps 阶跃模拟延迟

• 器件时钟和SYSREF 数字延迟和动态数字延迟

• PLL1 保持模式

CLKout10

VCXO

aµoš]‰oꢀ ^ꢁoꢀꢂv_ ꢁo}ꢁl•

at different and much

higher frequencies

LMX2615-SP

Recovered

—dirty“ clock

or clean clock

CLKout11

PLL+VCO

CLKin0

OSCout

CLKout8

CLKout9

FPGA

Backup

Reference

Clock

LMK04832-SP

CLKin1

CLKout4 &

CLKout6

CLKout5 &

CLKout7

• PLL1 或PLL2 0 延迟

• 环境温度范围：-55 °C 至125 °C

CLKout0 &

CLKout2

CLKout12,

CLKout13

D_DA_AC_C

ADC12DJ3200

QML-SP

CLKout1 &

CLKout3

Serializer/

Deserializer

2 应用

• 通信有效载荷

• 雷达成像有效载荷

• 命令和数据处理

简化原理图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNAS698

LMK04832-SP

ZHCSLT2C –MAY 2020 –REVISED NOVEMBER 2022

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Table of Contents

8.3 Feature Description...................................................23

8.4 Device Functional Modes..........................................35

8.5 Programming............................................................ 38

8.6 Register Maps...........................................................39

9 Application and Implementation..................................85

9.1 Application Information............................................. 85

9.2 Typical Application.................................................... 88

9.3 Power Supply Recommendations.............................89

9.4 Layout....................................................................... 91

10 Device and Documentation Support..........................94

10.1 Device Support....................................................... 94

10.2 Documentation Support.......................................... 94

10.3 接收文档更新通知................................................... 94

10.4 支持资源..................................................................94

10.5 Trademarks.............................................................94

10.6 Electrostatic Discharge Caution..............................94

10.7 术语表..................................................................... 94

11 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 6

6.1 绝对最大额定值...........................................................6

6.2 ESD 等级.................................................................... 6

6.3 建议运行条件.............................................................. 6

6.4 热性能信息..................................................................6

6.5 电气特性......................................................................7

6.6 时序要求....................................................................12

6.7 Timing Diagram.........................................................12

6.8 典型特性....................................................................13

7 Parameter Measurement Information..........................14

7.1 Charge Pump Current Specification Definitions........14

7.2 Differential Voltage Measurement Terminology........ 15

8 Detailed Description......................................................16

8.1 Overview...................................................................16

8.2 Functional Block Diagram.........................................20

Information.................................................................... 95

4 Revision History

Changes from Revision B (December 2020) to Revision C (November 2022)

Page

• 将器件信息表更改为封装信息...........................................................................................................................1

• Updated 节6.1 to include cold sparing considerations ratings...........................................................................6

• Updated 节6.6 to include t_CHWinformation........................................................................................................6

• Changed 图6-1 to include t_CHWin diagram......................................................................................................12

• Changed 图8-3 to include one-shot feature.....................................................................................................20

• Changed 表8-4 ............................................................................................................................................... 29

• Moved the Power Supply Recommendations and Layout sections to the Application and Implementation

section.............................................................................................................................................................. 89

• Added Cold Sparing Considerations section.................................................................................................... 89

• Explained the damage prevention details to unpowered device when cold sparing is used............................ 90

Changes from Revision A (August 2020) to Revision B (December 2020)

Page

• 将器件状态从“预告信息”更改为“量产数据”................................................................................................ 1

Changes from Revision * (March 2017) to Revision A (August 2020)

Page

• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1

• Added Layout section....................................................................................................................................... 91

2

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5 Pin Configuration and Functions

Clock Group 0

Clock Group 3

Status_LD2

Vcc10_PLL2

CPout2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

CLKout0

CLKout0*

CLKout1

1

2

3

Vcc9_CP2

OSCin*

CLKout1*

RESET/GPO

SYNC/SYSREF_REQ

GND

4

5

OSCin

6

Vcc8_OSCin

7

Fin0

OSCout*/CLKin2*

OSCout/CLKin2

Vcc7_OSCout

8

Top down view

Fin0*

9

Vcc1_VCO

LDObyp1

LDObyp2

CLKout3

10

11

12

13

14

15

16

CLKin0*

CLKin0

Vcc6_PLL1

CLKin1*/Fin1*/FBCLKin*

CLKin1/Fin1/FBCLKin

CLKout3*

CLKout2

DAP

Vcc5_DIG

CLKout2*

Clock Group 2

Clock Group 1

图5-1. HBD CFP Package 64-Pin CFP Top View

表5-1. Pin Functions

I/O

TYPE

DESCRIPTION

NO.

1

NAME

Clock output 0. For JESD204B systems suggest Device Clock.⁽²⁾

Programmable formats: CML, LVPECL, LCPECL, or LVDS.

CLKout0

CLKout0*

CLKout1

CLKout1*

O

Programmable

2

Clock output 1. For JESD204B systems suggest SYSREF Clock.⁽²⁾

Programmable formats: CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS.

3

4

5

RESET/GPO

I

CMOS

GND

Device reset input or GPO

SYNC/

SYSREF_REQ

6

Synchronization input or SYSREF_REQ for requesting continuous SYSREF.

This pin should be grounded.

7

GND

–

High-speed input for external VCO or clock distribution. Supports /2 for

frequency greater than 3250 MHz.

8, 9

Fin0/Fin0*

I

ANLG

10

11

12

13

14

15

16

17

Vcc1_VCO

LDObyp1

LDObyp2

CLKout3

PWR

ANLG

Power supply for VCO and clock distribution.

–

LDO Bypass, bypassed to ground with 10-µF capacitor.

LDO Bypass, bypassed to ground with a 0.1-µF capacitor.

Clock output 3. For JESD204B systems suggest SYSREF Clock.⁽²⁾

Programmable formats: CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS.

O

Programmable

CLKout3*

CLKout2

Clock output 2. For JESD204B systems suggest Device Clock.⁽²⁾

Programmable formats: CML, LVPECL, LCPECL, or LVDS.

O

Programmable

PWR

CLKout2*

Vcc2_CG1

Power supply for clock outputs 2 and 3.

–

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表5-1. Pin Functions (continued)

I/O

TYPE

DESCRIPTION

NO.

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

NAME

CS*

I

CMOS

PWR

Chip Select

SPI Clock

SPI Data

SCK

SDIO

I/O

–

Vcc3_SYSREF

CLKout5

CLKout5*

CLKout4

CLKout4*

Vcc4_CG2

CLKout6

CLKout6*

CLKout7

CLKout7*

Status_LD1

CPout1

Power supply for SYSREF divider and SYNC.

Clock output 5. For JESD204B systems suggest SYSREF Clock.⁽²⁾

Programmable formats: CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS.

O

Programmable

Clock output 4. For JESD204B systems suggest Device Clock.⁽²⁾

Programmable formats: CML, LVPECL, LCPECL, or LVDS.

Programmable

PWR

Power supply for clock outputs 4, 5, 6 and 7.

–

Clock output 6. For JESD204B systems suggest Device Clock.⁽²⁾

Programmable formats: CML, LVPECL, LCPECL, or LVDS.

O

Programmable

Clock output 7. For JESD204B systems suggest SYSREF Clock.⁽²⁾

Programmable formats: CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS.

O

Programmable

I/O

O

Programmable Programmable status pin.

ANLG

PWR

Charge pump 1 output.

Vcc5_DIG

CLKin1

Power supply for the digital circuitry.

–

Reference Clock Input Port 1 for PLL1.

34

35

FBCLKin

Fin1

I

ANLG

Feedback input for external clock feedback input (0–delay mode).

External VCO Input or clock distribution input.

Reference Clock Input Port 1 for PLL1.

CLKin1*

FBCLKin*

Fin1*

Feedback input for external clock feedback input (0–delay mode).

External VCO Input or clock distribution input.

Power supply for PLL1, charge pump 1, holdover DAC

36

37

38

39

Vcc6_PLL1

CLKin0

PWR

ANLG

–

I

Reference Clock Input Port 0 for PLL1.

CLKin0*

Vcc7_OSCout

OSCout

PWR

Power supply for OSCout port.

Buffered output of OSCin port.

Reference Clock Input Port 2 for PLL1.

Buffered output of OSCin port.

Reference Clock Input Port 2 for PLL1.

Power supply for OSCin

–

40

41

I/O

Programmable

CLKin2

OSCout*

CLKin2*

I/O

Programmable

PWR

42

43

44

45

46

47

48

49

50

51

52

53

54

55

Vcc8_OSCin

OSCin

–

I

ANLG

Feedback to PLL1 and reference input to PLL2. AC-coupled.

OSCin*

Vcc9_CP2

CPout2

PWR

ANLG

PWR

Power supply for PLL2 Charge Pump.

Charge pump 2 output.

–

O

Vcc10_PLL2

Status_LD2

CLKout9

CLKout9*

CLKout8

CLKout8*

Vcc11_CG3

CLKout10

CLKout10*

Power supply for PLL2.

–

I/O

Programmable Programmable status pin.

Clock output 9. For JESD204B systems suggest SYSREF Clock.⁽²⁾

Programmable formats: CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS.

O

Programmable

Clock output 8. For JESD204B systems suggest Device Clock.⁽²⁾

Programmable formats: CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS.

Programmable

PWR

Power supply for clock outputs 8, 9, 10, and 11.

–

Clock output 10. For JESD204B systems suggest Device Clock.⁽²⁾

Programmable formats: CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS.

O

Programmable

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表5-1. Pin Functions (continued)

I/O

TYPE

DESCRIPTION

NO.

56

NAME

Clock output 11. For JESD204B systems suggest SYSREF Clock.⁽²⁾

Programmable formats: CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS.

CLKout11

CLKout11*

O

Programmable

57

58

CLKin_SEL0

CLKin_SEL1

CLKout13

CLKout13*

CLKout12

CLKout12*

Vcc12_CG0

DAP

I/O

Programmable Programmable status pin.

59

Clock output 13. For JESD204B systems suggest SYSREF Clock.⁽²⁾

Programmable formats: CML, LVPECL, LCPECL, LVDS, or 2xLVCMOS.

60

O

Programmable

61

Clock output 12. For JESD204B systems suggest Device Clock.⁽²⁾

Programmable formats: CML, LVPECL, LCPECL, or LVDS.

62

63

64

PWR

GND

Power supply for clock outputs 0, 1, 12, and 13.

DIE ATTACH PAD, connect to GND.⁽¹⁾

–

DAP

(1) The metal lid is internally grounded and attached to the DAP.

(2) Actual best allocation of device clocks and SYSREF depends upon frequency planning to group common frequencies.

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6 Specifications

6.1 绝对最大额定值

在自然通风条件下的工作温度范围内测得（除非另有说明）⁽¹⁾

符号

参数

最小值

最大值

单位

V_DD、V_{DD_A}

-0.3

3.6

V

电源电压

输入电压⁽²⁾

–0.3

V_IN

V_DD+ 0.3

V

差分输入电流（CLKinX/X*、

OSCin/OSCin*、Fin）

I_IN

5

mA

T_J

150

7

°C

结温

T_stg

–65

存储温度

未上电时流入CLKin0 和SYNC 引脚的最大电流⁽³⁾

mA

小时

10

未上电接收器对外部输入的最大累积曝光

(1) 超出绝对最大额定值运行可能会对器件造成永久损坏。绝对最大额定值并不表示器件在这些条件下或在建议运行条件以外的任何其他条

件下能够正常运行。如果超出建议运行条件但在绝对最大额定值范围内使用，器件可能不会完全正常运行，这可能影响器件的可靠性、

功能和性能，并缩短器件寿命。

(2) 当器件处于未上电状态时，时钟输入引脚（CLKinX/FinX 和OSCin）可接受高达±400mV 的交流耦合信号。交流耦合时未上电器件输入

的绝对极限由引脚的±5mA (RMS) 电流限制决定。±400mV 信号通过0.01µF 电容在允许的工作频率范围内耦合，从而在整个工作结温

范围内满足交流耦合时钟输入的±5mA (RMS) 电流限制。对于较小的交流耦合电容器或较低的输入频率，可以接受较大的信号，以限制

输入引脚处的RMS 电流。

(3) 当外部上电发送器在短时间（器件寿命长达10 小时）内向未上电接收器发送信号时，LMK04832-SP 不会降低性能。使用最大VDD、

125°C 结温以及未上电时流入CLKin0 和SYNC 引脚的最大电流来执行特性评估。

6.2 ESD 等级

符号

参数

条件

值

单位

人体放电模型(HBM)，符合ANSI/ESDA/JEDEC JS-001，所

±2000

有引脚⁽¹⁾

V_(ESD)

V

静电放电

充电器件模型(CDM)，符合ANSI/ESDA/JEDEC JS-002 标

准，所有引脚⁽²⁾

±250

(1) JEDEC 文件JEP155 指出：500V HBM 可实现在标准ESD 控制流程下安全生产。

(2) JEDEC 文件JEP157 指出：250V CDM 可实现在标准ESD 控制流程下安全生产。

6.3 建议运行条件

在外壳温度范围内（除非另有说明）

符号

V_DD

V_{DD_A}

T_A

参数

最小值

3.135

标称值

最大值

3.465

125

单位

3.3

V

IO 电源电压

内核电源电压

环境温度

°C

–55

6.4 热性能信息

LMK04832-SP

热指标⁽¹⁾

HBD (CFP)

64 引脚

21.8

符号

单位

R_θJA

R_θJC(top)

R_θJB

Ψ_JT

°C/W

结至环境热阻

6.7

结至外壳（顶部）热阻

结至电路板热阻

7.4

1.3

结至顶部特征参数

结至电路板特征参数

7.1

Ψ_JB

6

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LMK04832-SP

热指标⁽¹⁾

HBD (CFP)

符号

单位

64 引脚

R_θJC(bot)

0.5

°C/W

结至外壳（底部）热阻

(1) 有关新旧热指标的更多信息，请参阅半导体和IC 封装热指标应用报告。

6.5 电气特性

VDD、VDD_A = 3.3V ± 5%，–55°C ≤TA ≤125°C。典型值是VDD = VDD_A = 3.3V、25°C 条件下的值（除非另有说明）

符号

参数

测试条件

最小值典型值最大值单位

电流消耗

3.3

5

关断电源电流

器件断电

旁路中4 个CML 32mA

时钟

3 个LVDS 时钟/12

4 个SYSREF 作为

LCPECL

1010

3 个SYSREF 作为

LVDS

旁路中4 个CML 32mA

时钟

PLL1 锁定到外部

VCXO，PLL2 锁定到

内部VCO

I_CC

mA

电源电流⁽¹⁾

3 个LVDS 时钟/12

4 个SYSREF 作为

LCPECL（低电平状态）

3 个SYSREF 作为

LVDS（低电平状态）

780

675

旁路中4 个CML 32mA

时钟

3 个LVDS 时钟/12

7 个SYSREF 输出断电

CLKin 规格

LOS_EN = 1

0.001

125

250

LOS 电路

CLKinX-

TYPE=1(MOS)

交流耦合输入

PLL1

CLKinX-TYPE=0（双

极）

0.001

750

500

f_CLKinX

MHz

V/ns

CLKinX_TYPE=0（双

极）

PLL2

带外部反馈的0 延迟

(CLKin1)

750

0 延迟

交流耦合输入

0.001

0.15

0.5

3250

仅CLKin1/Fin1 引脚

分配模式

输入压摆率⁽²⁾

SLEW_CLKin

V_CLKinX/Fin1

0.5

2.4 Vpp

输入引脚交流耦合；互补引脚交流耦合至GND

单端时钟输入电压

V_IDCLKinX/

Fin1

0.125

0.25

1.55

|V|

差分时钟输入电压⁽³⁾

交流耦合

V_SSCLKinX/

Fin1

3.1 Vpp

0

55

20

CLKin0/1/2（双极）

CLKin0/1 (MOS)

CLKin2 (MOS)

|VCLKinX-

offset|

CLKinx/CLKinx* 每个交流耦合引脚

之间的直流失调电压

|mV|

VCLKinVIH

VCLKinVIL

V_CLKin-V_IH

V_CLKin-V_IL

2

0

Vcc

0.4

V

高输入电压

低输入电压

直流耦合输入

Fin0 输入引脚

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6.5 电气特性(continued)

VDD、VDD_A = 3.3V ± 5%，–55°C ≤TA ≤125°C。典型值是VDD = VDD_A = 3.3V、25°C 条件下的值（除非另有说明）

符号

参数

测试条件

FIN0_DIV2_EN=1

FIN0_DIV2_EN=2

最小值典型值最大值单位

f_Fin0

1

3250 MHz

6400 MHz

1.55 Vpp

3.1 Vpp

交流耦合压摆率>

150V/us

外部输入频率

差分输入电压

V_IDFin0

V_SSFin0

PLL 1 规格

f_PD1

0.125

0.25

交流耦合

40 MHz

dBc/Hz

相位检测器频率

PLL1_CP_GAIN = 350µA

PLL1_CP_GAIN = 1550µA

PLL1_CP_GAIN = 350µA

PLL1_CP_GAIN = 1550µA

-117

-118

-221.5

-223

50

PLL 归一化1/f 噪声⁽⁴⁾

PLL 品质因数⁽⁵⁾

PN10kHz

PN FOM

PLL1_CP_GAIN=0

PLL1_CP_GAIN=1

PLL1_CP_GAIN=2

PLL1_CP_GAIN=4

PLL1_CP_GAIN=8

150

VCPout=Vcc/2（务必

告知客户，该器件适用

于0-15）

电荷泵电流⁽⁶⁾

I_CPOUT1

250

µA

450

850

V_CPout1= Vcc/2，T = V_CPout1= Vcc/2，T =

25°C 25°C

I_CPout1%MIS

1

4

10

%

电荷泵灌电流/拉电流不匹配

0.5V < V_CPout1< V_CC- 0.5V < V_CPout1< V_CC

-

电荷泵电流变化幅度与电荷泵电压间

的关系

I_CPout1V_TUNE

0.5V T_A= 25°C

I_CPout1%TEM

P

10

%

电荷泵电流与温度变化间的关系

I_CPOUT1TRI

nA

电荷泵TRI_STATE 漏电流

OSCin 输入

EN_PLL2_REF_2X=0

EN_PLL2_REF_2X=1

输入压摆率

0.001

0.15

0.2

500

320

f_OSCin

MHz

V/ns

SLEW_OSCin

V_OSCin

0.5

20

2.4 Vpp

OSCin 或OSCin* 的输入电压

交流耦合；单端；未使用的引脚交流耦合至GND

V_IDOSCin

V_SSOSCin

0.2

1.55

|V|

差分电压摆幅⁽³⁾

交流耦合

0.4

3.1 Vpp

V_CLKinXOffse

t

CLKinx/CLKinx* 每个交流耦合引脚

之间的直流失调电压

mV

320 MHz

dBc/Hz

PLL 2 规格

f_PD

相位检测器频率

PLL2_CP_GAIN = 1600uA

PLL2_CP_GAIN = 3200uA

PLL2_CP_GAIN = 1600uA

PLL2_CP_GAIN = 3200uA

-123

-128

PLL 归一化1/f 噪声⁽⁴⁾

PN10kHz

PN FOM

I_CPOUT

-226.5

-230

PLL 品质因数⁽⁵⁾

PLL2_CP_GAIN=2

VCPout=Vcc/2

1600

3200

电荷泵电流大小⁽⁶⁾

µA

PLL2_CP_GAIN=3

V_CPout1= Vcc/2，T = V_CPout1= Vcc/2，T =

I_CPout1%MIS

1

4

10

%

电荷泵灌电流/拉电流不匹配

25°C

0.5V < V_CPout1< V_CC- 0.5V < V_CPout1< V_CC

-

电荷泵电流变化幅度与电荷泵电压间

的关系

I_CPout1V_TUNE

0.5V T_A= 25°C

I_CPout1%TEM

P

10

%

电荷泵电流与温度变化间的关系

I_CPOUT1TRI

nA

电荷泵TRI_STATE 漏电流

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6.5 电气特性(continued)

VDD、VDD_A = 3.3V ± 5%，–55°C ≤TA ≤125°C。典型值是VDD = VDD_A = 3.3V、25°C 条件下的值（除非另有说明）

符号

参数

测试条件

最小值典型值最大值单位

内部VCO 规格

VCO0

VCO1

VCO0

2440

MHz

3255

f_VCO

VCO 频率范围

8 到11

K_VCO

MHz/V

VCO 调优灵敏度

17 至

VCO1

23

连续锁定的容许温漂⁽⁷⁾

VCO0

VCO1

10kHz

100 kHz

150

180

^oC

|ΔT_CL

|

-88.4

-117

800kHz

1MHz

-137.5

-139.7

-152.6

-85.7

2500MHz 时的VCO0

2590MHz 时的VCO0

2700MHz 时的VCO1

3200MHz 时的VCO1

10MHz

10kHz

100kHz

800kHz

1MHz

L(f)VCO

dBc/Hz

开环VCO 相位噪声

-115.8

-137

-138.6

-151.8

-82.6

10MHz

10kHz

100 kHz

800kHz

1MHz

-112.3

-134.9

-137.2

-151.1

-81

10MHz

10kHz

100kHz

800kHz

1MHz

L(f)VCO

dBc/Hz

开环VCO 相位噪声

-110.4

-134.3

-135.6

-149.3

10MHz

输出时钟延迟和时序

50

相同的器件时钟对和相同的格式

偶数到偶数或奇数到奇数，相同格式

偶数时钟到奇数时钟

SKEWCLKin

X

ps

输出到输出延迟

Fin 引脚在分配模式下的附加抖动（注6）

LVCMOS

LVDS

50

40

35

40

35

245.76MHz 输出频

LVPECL

L(f)CLKout

fs

附加抖动，无分频的分配模式

率，12kHz 至20MHz

集成带宽

LCPECL

HSDS

CML

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6.5 电气特性(continued)

VDD、VDD_A = 3.3V ± 5%，–55°C ≤TA ≤125°C。典型值是VDD = VDD_A = 3.3V、25°C 条件下的值（除非另有说明）

符号

参数

测试条件

最小值典型值最大值单位

LVCMOS 输出

f)_CLKout

250 MHz

5pF 负载

20MHz 偏移

频率

L(f)_CLKout

V_OH

245.76 MHz

dBc/Hz

V

–160

本底噪声

Vcc–

1mA 负载

输出高电压

0.1

V_OL

0.1

V

1mA 负载

FD=1.65V

Vd=1.65V

输出低电压

输出高电流

输出低电流

输出占空比

I_OH

-28

28

50

mA

%

I_OL

占空比

LVDS 时钟输出

L(f)CLKout

-159.5

175

dBc/Hz

ps

245.76MHz 输出

20MHz 偏移

本底噪声

T_R/T_F

V_OD

20% 至80% 上升/下降时间

差分输出电压

400

mV

V

-60

60

1.375

35

ΔV_OD

V_OS

针对互补输出状态的V_OD变化

输出失调电压

直流测量，交流耦合到接收器输入R_L= 100Ω差

分

1.125

1.25

mV

mA

ΔV_OS

针对互补输出状态的VOS 变化

I_{SA SB}

I

24

–24

短路输出电流

LCPECL 时钟输出

L(f)CLKout

-162.5

135

1.4

dBc/Hz

245.76MHz 输出

20MHz 偏移

本底噪声

T_R/T_F

V_OH

ps

V

20% 至80% 上升/下降时间

输出高电压

50Ω至0.5V 的直流测

量

V_OL

0.6

V

输出低电压

50Ω至0.5V 的直流测

量

V_OD

870

mV

差分输出电压

LVPECL 时钟输出

245.76MHz 输出，

L(f)CLKout

-163

dBc/Hz

ps

20MHz 偏移

本底噪声

LVPECL 2.0V

T_R/T_F

V_OH

135

Vcc-1

20% 至80% 上升/下降时间

LVPECL 1.6V

LVPECL 2.0V

V

输出高电压

直流测量端接50Ω至

Vcc-2V

Vcc–

LVPECL 1.6V

1.8

V_OL

输出低电压

LVPECL 2.0V

LVPECL 1.6V

Vcc–2

0.8

2.5GHz，Em = 120Ω

至GND，R_L= 交流耦

合100Ω

V_OD

V

差分输出电压

LVPECL 2.0V

1

HSDS 时钟输出

L(f)CLKout

dBc/Hz

ps

245.76MHz 输出

20MHz 偏移

–162

本底噪声

20% 至80% 上升/下降时间

T_R/T_F

170

10

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6.5 电气特性(continued)

VDD、VDD_A = 3.3V ± 5%，–55°C ≤TA ≤125°C。典型值是VDD = VDD_A = 3.3V、25°C 条件下的值（除非另有说明）

符号

参数

测试条件

最小值典型值最大值单位

Vcc–

HSDS 6mA

0.9

V_OH

V

输出高电压

Vcc–

0.95

HSDS 8mA

HSDS 6mA

HSDS 8mA

50Ω至0.5V 的直流测

量

Vcc–

1.5

V_OL

V

输出低电压

输出电压

Vcc–

1.7

HSDS 6mA

HSDS 8mA

HSDS 6mA

HSDS 8mA

0.6

V_OD

V

0.75

50Ω至0.5V 的直流测

量

-80

80

mV

ΔV_OD

针对互补输出状态的VOS 变化

115

–115

CML 输出

L(f)CLKout

-163

120

125

135

Vcc

dBc/Hz

20MHz 偏移

CML 16mA

CML 24mA

CML 32mA

本底噪声

T_R/T_F

V_OH

ps

V

20% 至80% 上升/下降时间

输出高电压

50Ω上拉至Vcc，直流测量

CML 16mA

Vcc–

0.84

50Ω上拉至Vcc，直

流测量

Vcc–

1.26

V_OL

CML 24mA

CML 32mA

V

输出低电压

Vcc–

1.66

CML 16mA

CML 24mA

CML 32mA

CML 16mA

CML 24mA

CML 32mA

840

1260

1660

550

50Ω上拉至Vcc，直

流测量

mV

V_OD

输出电压

50Ω上拉至Vcc，直

流测量，R_L= 交流耦

合100Ω，250MHz

815

1070

数字输出（CLKin_SELX、STATUS_LDX 和RESET/GPO、SDIO）

Vcc–

V_OH

V_OL

V

输出高电压

输出低电压

0.4

数字输入

V_IH

1.2

10

V

高电平输入电压

低电平输入电压

V_IL

0.5

80

25

5

CLKinX_SEL、RESET/GPO、SYNC、SCK、

SDIO、CS*

I_IH

uA

高电平输入电流

SYNC

V_IH= V_CC

CLKinX_SEL、RESET/GPO、SYNC、SCK、

SDIO、CS*

I_IL

-5

低电平输入电流

SYNC

V_IL= 0V

5

(1) 使用TICS Pro 工具计算特定配置的Icc

(2) 器件将以低至0.15V/ns 的压摆率运行，但建议使用0.5V/ns 或更高的压摆率，以获得出色的相位噪声性能。

(3) 有关VID 和VOD 电压的定义，请参阅“差分电压测量术语”。

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(4) PLL 带内相位噪声建模中的一个规格是1/f 闪烁噪声，即LPLL_flicker(f)，主要与载波相关。闪烁噪声具有10dB/十倍频程的斜率。

PN10kHz 归一化为10kHz 偏移和1GHz 载波频率。PN10kHz = LPLL_flicker(10kHz) - 20 log(Fout/1GHz)，其中LPLL_flicker(f) 是仅闪

烁噪声对总噪声L(f) 影响的单边带相位噪声。要测量LPLL_flicker(f)，务必具有接近载波的10dB/十倍频程斜率。高比较频率和干净的

晶体对于将此噪声源与总相位噪声L(f) 隔离非常重要。如果使用低功耗或高噪声源，则基准振荡器性能可以屏蔽LPLL_flicker(f)。总

PLL 带内相位噪声性能是LPLL_flicker(f) 和LPLL_flat(f) 的总和

(5) PLL 带内相位噪声建模规格。PLL 的归一化相位噪声影响（即LPLL_flat(f)）定义为：PN1 HZ = LPLL_flat(f) - 20 log(N) - 10

log(fPDX)。LPLL_flat(f) 是在1Hz 带宽内以偏移频率f 测量的单边带相位噪声，fPDX 是合成器的相位检测器频率。LPLL_flat(f) 会影响

总噪声L(f)。

(6) 该参数可编程为比电气规格中所示状态更多的状态

(7) 连续锁定的最大容许温漂是指在器件仍保持锁定状态的情况下，温度可以从上次使用PLL2_FCAL_DIS = 0 编程0x168 寄存器时的值向

任一方向漂移的距离。即使将0x168 寄存器编程为相同的值，也会激活频率校准例程。这意味着该器件将在整个频率范围内工作，但如

果温漂大于连续锁定的最大容许温漂，则需要重新加载相应的寄存器以确保其保持锁定状态。该参数是间接测试的。

6.6 时序要求

VDD，VDD_A = 3.3V ± 5%，–55°C ≤TA ≤125°C。典型值是VDD = VDD_A = 3.3V、25°C 条件下的值（除非另有说明）

符号

时序要求

td_S

参数

最小值

标称值

最大值

单位

40

20

ns

SDI 边沿到SCK 上升沿的设置时间

SDI 边沿到SCK 上升沿的保持时间

SCK 周期

td_H

t_SCK

t_HIGH

t_LOW

t_CS

400

120

40

SCK 的高宽度

SCK 的低宽度

CS* 下降沿到SCK 上升沿的设置时间

t_CH

40

从SCK 上升沿到CS* 上升沿的保持时间

CS* 的高宽度时间

t_CHW

t_DV

120

SCK 下降沿到有效读回数据

6.7 Timing Diagram

Register programming information on the SDIO pin is clocked into a shift register on each rising edge of the SCK

signal. On the rising edge of the CS* signal, the register is sent from the shift register to the register addressed.

A slew rate of at least 30 V/µs is recommended for these signals. After programming is complete the CS* signal

should be returned to a high state. If the SCK or SDIO lines are toggled while the VCO is in lock, as is

sometimes the case when these lines are shared with other parts, the phase noise may be degraded during this

programming.

4-wire mode read back has same timing as SDIO pin.

R/W bit = 0 is for SPI write. R/W bit = 1 is for SPI read.

SDIO

(WRITE)

A12 to A0,

D7 to D2

R/W

A14

A13

D1

D0

td_S

td_H

SCK

tc_H

tc_S

t_HIGH

t_LOW

t_SCK

SDIO

D7 to

D2

D1

D0

(Read)

td_V

tc_HW

CS*

图6-1. SPI Timing Diagram

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6.8 典型特性

100Hz 至100MHz 的抖动= 63.6fs rms。

100Hz 至100MHz 的抖动= 67fs rms。

输出为CLKout4，即CML 32mA，具有68nH 至20Ω直流偏

置。

输出为CLKout4，即CML 32mA，具有68nH 至20Ω直流偏

置。

其他设置包括CLKout4_5_IDL = 1 和CLKout4_5_BYP = 1。

PLL2 环路滤波器R2 = 470Ω，C2 = 150nF，电荷泵=

3200µA。

其他设置包括CLKout4_5_IDL = 1 和CLKout4_5_BYP = 1。

PLL2 环路滤波器R2 = 470Ω，C2 = 150nF，电荷泵=

3200µA。

基准是带SMAB - B711 选件的R&S SMA100B 信号发生器，

通过Prodyn BIB-100G 平衡-非平衡变压器连接到OSCin。

基准是带SMAB - B711 选件的R&S SMA100B 信号发生器，

通过Prodyn BIB-100G 平衡-非平衡变压器连接到OSCin。

图6-2. PLL2 具有VCO1 性能（2500MHz 频率下）和

312.5MHz OSCin/相位检测器频率

图6-3. PLL2 具有VCO1 性能（3200MHz 频率下）和

320MHz OSCin/相位检测器频率

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7 Parameter Measurement Information

7.1 Charge Pump Current Specification Definitions

I1 = Charge Pump Sink Current at V_CPout= V_CC- ΔV

I2 = Charge Pump Sink Current at V_CPout= V_CC/2

I3 = Charge Pump Sink Current at V_CPout= ΔV

I4 = Charge Pump Source Current at V_CPout= V_CC- ΔV

I5 = Charge Pump Source Current at V_CPout= V_CC/2

I6 = Charge Pump Source Current at V_CPout= ΔV

ΔV = Voltage offset from the positive and negative supply rails. Defined to be 0.5 V for this device.

7.1.1 Charge Pump Output Current Magnitude Variation vs Charge Pump Output Voltage

7.1.2 Charge Pump Sink Current vs Charge Pump Output Source Current Mismatch

7.1.3 Charge Pump Output Current Magnitude Variation vs Ambient Temperature

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7.2 Differential Voltage Measurement Terminology

The differential voltage of a differential signal can be described by two different definitions causing confusion

when reading data sheets or communicating with other engineers. This section will address the measurement

and description of a differential signal so that the reader will be able to understand and distinguish between the

two different definitions when used.

The first definition used to describe a differential signal is the absolute value of the voltage potential between the

inverting and noninverting signal. The symbol for this first measurement is typically V_IDor V_ODdepending on if

an input or output voltage is being described.

The second definition used to describe a differential signal is to measure the potential of the noninverting signal

with respect to the inverting signal. The symbol for this second measurement is V_SSand is a calculated

parameter. Nowhere in the IC does this signal exist with respect to ground, it only exists in reference to its

differential pair. V_SScan be measured directly by oscilloscopes with floating references, otherwise this value can

be calculated as twice the value of V_ODas described in the first description.

图 7-1 illustrates the two different definitions side-by-side for inputs and 图 7-2 illustrates the two different

definitions side-by-side for outputs. The V_IDand V_ODdefinitions show V_Aand V_BDC levels that the noninverting

and inverting signals toggle between with respect to ground. V_SSinput and output definitions show that if the

inverting signal is considered the voltage potential reference, the noninverting signal voltage potential is now

increasing and decreasing above and below the noninverting reference. Thus the peak-to-peak voltage of the

differential signal can be measured.

V_IDand V_ODare often defined as volts (V) and V_SSis often defined as volts peak-to-peak (V_PP).

V_IDDefinition

V_SSDefinition for Input

Noninverting Clock

V_A

V_B

2 × V_ID

V_ID

Inverting Clock

V_ID= | V_AV_B

|

V_SS= 2 × V_ID

GND

图7-1. Two Different Definitions for Differential Input Signals

V_ODDefinition

V_SSDefinition for Output

Non-Inverting Clock

V_A

V_B

2·V_OD

V_OD

Inverting Clock

V_OD= | V_A- V_B

|

V_SS= 2·V_OD

GND

图7-2. Two Different Definitions for Differential Output Signals

Refer to application note AN-912 Common Data Transmission Parameters and their Definitions (SNLA036) for

more information.

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8 Detailed Description

8.1 Overview

The LMK04832-SP device is very flexible to meet many application requirements. Use cases include dual loop,

dual loop 0-delay nested, dual loop 0-delay cascaded, single loop, single loop 0-delay, and clock distribution.

The device may be used in JESD204B systems by providing a device clock and SYSREF to target devices,

however traditional (non-JESD204B) systems are possible by programming pairs of outputs to share the clock

divider or any mix of JESD204B and traditional.

8.1.1 Differences Between LMK04832-SP and LMK04832

The LMK04832-SP is very similar to the LMK04832 commercial device, but it does have a few differences.

表8-1. LMK04832-SP vs. LMK04832

Attribute

Radiation Hardened

Temperature

LMK04832

No

LMK04832-SP

Yes

–40 ºC to +85 ºC

–55 ºC to +125 ºC

11 × 11 mm²(Disregarding Leads)

30 × 30 mm²(Including Leads)

Package Size

9 × 9 mm²

Package Composition

Pins 8/9

Plastic

NC

Ceramic

Fin0/Fin0* Input

GND

Pin 7

NC

Programming Speed

5 MHz

2.5 MHz

8.1.1.1 Jitter Cleaning

The dual loop PLL architecture provides the lowest jitter performance over a wide range of output frequencies

and phase noise integration bandwidths. The first stage PLL (PLL1) is driven by an external reference clock and

uses an external VCXO to provide a frequency accurate, low phase noise reference clock for the second stage

frequency multiplication PLL (PLL2).

PLL1 typically uses a narrow loop bandwidth (typically 10 Hz to 200 Hz) to retain the frequency accuracy of the

reference clock input signal while at the same time suppressing the higher offset frequency phase noise that the

reference clock may have accumulated along its path or from other circuits. This cleaned reference clock

provides the reference input to PLL2.

The low phase noise reference provided to PLL2 allows PLL2 to operate with a wide loop bandwidth (typically 50

kHz to 200 kHz). The loop bandwidth for PLL2 is chosen to take advantage of the superior high offset frequency

phase noise profile of the internal VCO and the good low offset frequency phase noise of the reference VCXO.

Ultra-low jitter is achieved by allowing the phase noise of the external VCXO to dominate the final output phase

noise at low offset frequencies and the phase noise of the internal VCO to dominate the final output phase noise

at high offset frequencies. This results in best overall phase noise and jitter performance.

8.1.1.2 JEDEC JESD204B Support

This device clocks up to 7 JESD204B targets using 7 device clocks and 7 SYSREF clocks and allows every

clock output to be configured as a device clock or SYSREF clock.

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8.1.2 Clock Inputs

备注

CLKin1 can be used as a reference for dual loop, single loop, or clock distribution mode, providing

flexibility configuring the device for different operation modes from one clock input.

8.1.2.1 Inputs for PLL1

CLKin0, CLKin1, and CLKin2 are the three redundant inputs with their own PLL1 R dividers that can be used as

a reference input to PLL1. The switching between these inputs can either be automatic or manual. For manual

switching, CLKin_SEL0 and CLKin_SEL1 pins can be used for faster speed. These input pins are also shared

for other functions.

• CLKin1 is shared for use as an external 0-delay feedback (FBCLKin), or for use with an external VCO (Fin).

• CLKin2 is shared for use as OSCout. To use CLKin2 as an input power down OSCout, see 节8.6.2.3.1.

8.1.2.2 Inputs for PLL2

In dual loop configurations, the PLL2 reference is from OSCin. However, in single PLL2 loop operation, it is also

possible to use any of the three CLKins of PLL1 as a reference to PLL2.

8.1.2.3 Inputs When Using Clock Distribution Mode

For clock distribution mode, a reference signal is may be applied to the Fin0 or Fin1 pins. CLKin0 can be used to

distribute a SYSREF signal through the device. In this use case, CLKin0 is re-clocked by CLKin1. The Fin0 pins

are generally recommended over the Fin1 pins because they allow higher frequency, use a lower noise path,

and cannot be used for other functions (like redundant input).

8.1.3 PLL1

PLL1 allows low offset jitter cleaning as well as the use of redundant inputs and frequency holdover.

8.1.3.1 Frequency Holdover

Frequency holdover keeps the clock outputs on frequency with minimum drift when the reference is lost until a

valid reference clock signal is re-established. This can only be used if PLL1 is used.

8.1.3.2 External VCXO for PLL1

When PLL1 is used, an external VCXO is required. The close-in noise performance of this VCXO is critcal for

good jitter cleaning performance. The LMK04832-SP also provides OSCout, which by power-on default is a

buffered copy of the PLL1 feedback and PLL2 reference input at OSCin. This reference input is typically a low

noise VCXO or XO. This output can be used to clock external devices such as microcontrollers, FPGAs, CPLDs,

and so forth, before the LMK04832-SP is programmed.

• The OSCout buffer output type is programmable to LVDS, LVPECL, or LVCMOS.

• The VCXO buffered output can be synchronized to the VCO clock distribution outputs by using Cascaded 0-

Delay Mode.

8.1.4 PLL2

8.1.4.1 Internal VCOs for PLL2

PLL2 has two internal VCOs. The output of the selected VCO is routed to the Clock Distribution Path. This same

selection is also fed back to the PLL2 phase detector through a prescaler and N-divider.

8.1.4.2 External VCO Mode

An external VCO can be used with PLL2 with the input for the external VCO coming through Fin0 or Fin1,

although Fin0 is generally preferred.

• Fin0/Fin0* input is generally recommended because it is lower noise, supports higher input frequency (up to 6

GHz if the div2 is used), and it leaves CLKin1 available for redundant inputs.

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Fin1/Fin1* inputs are generally NOT recommended, for the reasons stated above, although they can be used.

8.1.5 Clock Distribution

The LMK04832-SP features a total of 14 PLL2 clock outputs driven from the internal or external VCO.

All clock outputs have programmable output types. They can be programmed to CML, LVPECL, LVDS, HSDS, or

LCPECL. All odd clock outputs plus CLKout8 and CLKout10 may be programmed to LVCMOS.

If OSCout is included in the total number of clock outputs the LMK04832-SP is able to distribute up to 15

differential clocks. OSCout may be a buffered version of OSCin, DCLKout6, DCLKout8, or SYSREF. Its output

format is programmable to LVDS, LVPECL, or LVCMOS.

The following sections discuss specific features of the clock distribution channels that allow the user to control

various aspects of the output clocks.

8.1.5.1 Clock Divider

There are 7 clock dividers. In a traditional clocking system each divider can drive two outputs. The divider range

is 1 to 1023. Duty cycle correction may be enabled for the output. When the divider is used even clocks may not

output CML.

In a JESD204B system, one clock output is a device clock driven from the clock divider and the other paired

clock is from the SYSREF divider. For connectivity flexibility, either the even or odd clock output may be driven

by the clock divider or be the SYSREF output.

8.1.5.2 High Performance Divider Bypass Mode

Even clock outputs (CLKoutX) of the LMK04832-SP may bypass the clock divider to achieve the best possible

noise floor and output swing. In this mode, the only usable output format is CML.

8.1.5.3 SYSREF Clock Divider

The SYSREF divider supports a divide range of 8 to 8191 (even and odd). There is no duty cycle correction for

the SYSREF divider. The SYSREF output may be routed to all clock outputs.

8.1.5.4 Device Clock Delay

The device clocks support digital delay for phase adjustment of the clock outputs.

The digital delay allows outputs to be delayed from 8 to 1023 VCO cycles. The delay step can be as small as

half the period of the clock distribution path. For example, a 3.2-GHz VCO frequency results in 156.25-ps steps.

The digital delay value takes effect on the clock output phase after a SYNC event.

8.1.5.5 Dynamic Digital Delay

The device clock dividers support a dynamic digital delay feature which allows the clock to be delayed by one full

device clock cycle. With a single programming, an adjustment of up to 255 one cycle delays may occur. When

making a multi-step adjustment, the adjustments are periodically applied to reduce impact to the clock.

Dynamic phase adjustments of half a clock distribution cycle are possible by half step.

The SYSREF digital delay value is reused for dynamic digital delay. To achieve a one cycle delay program the

SYSREF digital delay value to one greater than half the SYSREF divide value.

8.1.5.6 SYSREF Delay: Global and Local

The SYSREF divider includes a digital delay block which allows a global phase shift with respect to the device

clocks.

Each clock output pair includes a local SYSREF analog and digital delay for unique phase adjustment of each

SYSREF clock.

The local analog delay allows for approximately 21-ps steps. Turning-on analog delay adds an additional 124 ps

of delay in the clock path. The digital delay step can be as small as half the period of the clock distribution path.

For example, a 3.2-GHz VCO frequency results in 156.25-ps steps.

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The local digital delay and half step allows a SYSREF output to be delayed from 1.5 to 11 clock distribution path

cycles.

8.1.5.7 Programmable Output Formats

All clock outputs can be programmed to an LVDS, HSDS, LVPECL, or LCPECL output type. Odd clock outputs

in addition to CLKout8 and CLKout10 may also be programmed to LVCMOS. All odd clock outputs can also be

programmed to CML. When in bypass mode the even clock output may only be CML.

The OSCout can be programmed to an LVDS, LVPECL, or LVCMOS output type.

Any HSDS output type can be programmed to 6-mA or 8-mA amplitude levels.

Any LVPECL output type can be programmed to 1600-mVpp or 2000-mVpp amplitude levels. The 2000-mVpp

LVPECL output type is a Texas Instruments proprietary configuration that produces a 2000-mVpp differential

swing for compatibility with many data converters and is also known as 2VPECL.

LCPECL allows for DC-coupling SYSREF to low voltage JESD204B targets.

8.1.5.8 Clock Output Synchronization

Using the SYNC input causes all active clock outputs to share a rising edge as programmed by fixed digital

delay.

The SYNC event must occur for digital delay values to take effect.

8.1.6 0-Delay

Two types of 0-delay mode are supported.

1. Cascaded 0-delay

2. Nested 0-delay

Cascaded 0-delay mode establishes a fixed deterministic phase relationship of the phase of the PLL2 input clock

(OSCin) to the phase of a clock selected by the feedback mux. The 0-delay feedback uses internal feedback

from the CLKout6, CLKout8, or SYSREF. The 0-delay feedback can also be from an external feedback through

the FBCLKin port. The FB_MUX selects the feedback source. Because OSCin has a fixed deterministic phase

relationship to the feedback clock, OSCout will also have a fixed deterministic phase relationship to the feedback

clock. In this mode, PLL1 input clock (CLKinX) also has a fixed deterministic phase relationship to PLL2 input

clock (OSCin); this results in a fixed deterministic phase relationship between all clocks from CLKinX to the clock

outputs.

Nested 0-delay mode establishes a fixed deterministic phase relationship of the phase of the PLL1 input clock

(CLKinX) to the phase of a clock selected by the feedback mux. The 0-delay feedback uses internal feedback

from the CLKout6, CLKout8, or SYSREF. The 0-delay feedback can also be from an external feedback through

the FBCLKin port. The FB_MUX selects the feedback source.

Without using 0-delay mode, there will be n possible fixed phase relationships from clock input to clock output

depending on the clock output divide value.

Using an external 0-delay feedback reduces the number of available clock inputs by one.

8.1.7 Status Pins

The status pins can be monitored for feedback or in some cases used for input depending upon device

programming. For example:

• The CLKin_SEL0 pin may indicate the LOS (loss-of-signal) for CLKin0.

• The CLKin_SEL1 pin may be an input for selecting the active clock input.

• The Status_LD1 pin may indicate if the device is locked.

• The Status_LD2 pin may indicate if PLL2 is locked.

The status pins can be programmed to a variety of other outputs including PLL divider outputs, combined PLL

lock detect signals, PLL1 Vtune railing, readback, and so forth. Refer to 节8.6 for more information.

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8.2 Functional Block Diagram

图8-1 illustrates the high level LMK04832-SP block diagram.

CLKin0 R

Divider

(1 to 16,383)

CLKin0

_OUT

_MUX

CLKin

MUX

CLKin0

CLKin0*

Phase

Detector

PLL1

CLKin1 R

Divider

(1 to 16,383)

CLKin0

CPout1

N1 Divider

(1 to 16,383)

CLKin2 R

Divider

(1 to 16,383)

CLKin1/Fin1/

FBCLKin

CLKin1

_OUT

_MUX

Fin1

FB Mux

Holdover

CLKin1*/Fin1*/

FBCLKin*

CLKout6

CLKout8

SYSREF Div

FB_

MUX

PLL1

_NCLK

_MUX

OSCout/

CLKin2

OSCout*/

CLKin2*

SPI

Selectable

2X

Partially

Integrated

Loop Filter

PLL2

_REF

_2X_EN

R2 Divider

(1 to 4,095)

Internal Dual

Core VCO

OSCin

OSCin*

Phase

Detector

PLL2

_NCLK

_MUX

N2 Divider

(1 to 262,143)

Status_LD1

Status_LD2

RESET/GPO

N2 Prescaler

(2 to 8)

SYNC

CLKin_SEL0

CLKin_SEL1

Device

Control

/2

Clock Distribution Path

VCO_

MUX

Fin0

Fin0*

SCK

SDIO

CS*

Control

Registers

SPI

Fin1

SYSREF/SYNC Control

Divider

(8 to 8191)

SYSREF/SYNC

Distribution Path

D

SYNC

Dig. Delay

Div (1 to 1023)

A. Delay

CLKout12

CLKin0

CLKout12*

Pulser

CLKout13

CLKout13*

Div (1 to 1023)

A. Delay

Dig. Delay

CLKout0

CLKout0*

Dig. Delay

Div (1 to 1023)

A. Delay

CLKout10

CLKout10*

CLKout1

CLKout1*

CLKout11

CLKout11*

Div (1 to 1023)

A. Delay

Dig. Delay

CLKout2

CLKout2*

Dig. Delay

Div (1 to 1023)

A. Delay

CLKout8

CLKout8*

CLKout3

CLKout3*

CLKout9

CLKout9*

Div (1 to 1023)

A. Delay

Dig. Delay

CLKout4

CLKout4*

Dig. Delay

Div (1 to 1023)

A. Delay

CLKout6

CLKout6*

CLKout5

CLKout5*

CLKout7

CLKout7*

图8-1. High Level LMK04832-SP Block Diagram

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CLKout0, 2, 4, 6, 8, 10, 12

CLKoutX_

FMT

CLKoutX_Y_PD

DCLKX_Y_PD

Device Clock (DCLK)

DCLKX

_BYP

DCLKX_Y_DDLY_PD

CML

DCLKX_Y

_POL

VCO

DCLKX_Y_ DCLKX_Y_

DIV

(1 to 1023)

CLKoutX_

SRC_MUX

DCLKX_Y_

HS

DDLY

(8 to 1023)

DCC

DCLKX_Y_

DCC

DDLYdX_Y_EN

DCLKout6/8 to FB_MUX

CLKoutX_Y_ODL

SYNC_

DIS_DCLKX_Y

CLKoutX_Y_IDL

SYSREF_GBL_PD

SDCLKoutY_DIS_MODE

SYSREF Clock (SCLK)

SCLKX_Y_PD

SCLKX_Y

_ADLY_EN

SYSREF/SYNC

SCLKX_Y_

DDLY

SCLKX_Y

_HS

Analog

DLY

CLKoutY_

SRC_MUX

CLKoutY_

FMT

SYSREF_CLR

CLKout1, 3, 5, 7, 9, 11, 13

X = Odd Numbers

Y = Even Numbers

Legend

SYSREF/SYNC Clock

VCO/Distribution Clock

SPI Register

图8-2. Device and SYSREF Clock Output Block

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SPI Register: SYNC_EN

Must Be Set To Enable Any

SYNC/SYSREF Functionality

CLKin0

CLKin0_

DEMUX

PLL1

D

SYNC_PLL1_DLD

PLL1_DLD

SYNC_PLL2_DLD

PLL2_DLD

SYSREF_REQ_EN

SYNC

_MODE

SYSREF_

MUX

SYNC

_POL

D

PULSER MODE

SYSREF_PULSE_CNT

One

Shot

Pulser

VCO0

SYSREF_PLSR_PD

SYNC/SYSREF

VCO1 VCO

_MUX

SYSREF

DDLY

SYSREF

Divider

SYSREF_

1SHOT_MUX

External

VCO

SYSREF_PD

SYSREF_DDLY_PD

DCLKout6

DCLKout8

OSCin

OSCout

_MUX

SYNC_

DISSYSREF

FB_MUX

OSCout

CLKin1

FB_MUX

PLL1

CLKin1_

DEMUX

DCLKout0, 2, 4, 6, 8, 10, 12

Clock

VCO Frequency

DDLY

(4 to 32) (1 to 32)

Divider

Analog

DLY

Output

DCC

Distribution Path

Buffer

SYNC_

DISX

SYSREF/SYNC

Digital

DLY

Analog

DLY

Output

Buffer

Legend

SYSREF_CLR

SYSREF/SYNC Clock

VCO/Distribution Clock

SPI Register

SDCLKout1, 3, 5, 7, 9, 11, 13

图8-3. SYNC/SYSREF Clocking Paths

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8.3 Feature Description

8.3.1 Synchronizing PLL R Dividers

In some cases, it is necessary to synchronize PLL R dividers to enable determinism of clocks outputs to inputs.

This typically is required when the fraction Total PLL N divide / Total PLL R divide does not reduce to N / 1.

8.3.1.1 PLL1 R Divider Synchronization

It is possible to use the CLKin0 or SYNC pin to synchronize the PLL1 R divider. In either case, the PLL1 R

divider is armed for reset, then the rising sync edge arrives from either SYNC pin or CLKin0. After the PLL1 R

divider is armed, PLL1 is unlocked until the synchronization edge arrives and allows the divider to operate and

the PLL to lock. The procedure to synchronize PLL1 R is as follows:

1. Setup device for synchronizing PLL1 R:

• PLL1R_SYNC_EN = 0x1

• PLL1R_SYNC_SRC = 0x1 (SYNC pin) or 0x2 (CLKin0)

• CLKin0_DEMUX = 0x2 (PLL1)

• CLKin1_DEMUX = 0x2 (PLL1)

• CLKin0_TYPE = 0x1 (MOS) for DC-coupled or CLKin0_TYPE = 0x0 (Bipolar) for AC-coupled

2. Arm PLL1 R divider for synchronization

• PLL1R_RST = 1, then 0.

• PLL1 is unlocked.

3. Send rising edge on SYNC pin or CLKin0.

• PLL1 R divider is released from reset and PLL1 relocks.

It is necessary to meet a setup and hold time when CLKin0 or SYNC pin goes high to ensure deterministic reset

of the PLL1 R divider.

The SYNC_POL bit has no effect on SYNC polarity for PLL1 R synchronization.

8.3.1.2 PLL2 R Divider Synchronization

The SYNC pin must be used to synchronized the PLL2 R divider. When PLL2R_SYNC_EN = 1, as long as the

SYNC pin is held high, the PLL2 R divider is held in reset. When the SYNC pin is returned low, the divider is

allowed to continue dividing. While PLL2R_SYNC_EN = 1 and SYNC pin is high PLL2 is unlocked.

It is necessary to meet a setup and hold time when SYNC pin goes low to ensure deterministic reset of the PLL2

R divider.

The SYNC_POL bit has no effect on SYNC polarity for PLL2 R synchronization.

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8.3.2 SYNC/SYSREF

The SYNC and SYSREF signals share the same SYNC/SYSREF Clock Distribution path. To properly use SYNC

and/or SYSREF for JESD204B it is important to understand the SYNC/SYSREF system. 图 8-2 illustrates the

detailed diagram of a clock output block with SYNC circuitry included. 图 8-3 illustrates the interconnects and

highlights some important registers used in controlling the device for SYNC/SYSREF purposes.

To reset or synchronize a divider, the following conditions must be met:

1. SYNC_EN must be set. This ensures proper operation of the SYNC circuitry.

2. SYSREF_MUX and SYNC_MODE must be set to a proper combination to provide a valid SYNC/SYSREF

signal.

• If SYSREF block is being used, the SYSREF_PD bit must be clear.

• If the SYSREF Pulser is being used, the SYSREF_PLSR_PD bit must be clear.

• For each CLKoutX or CLKoutY being used for SYSREF, the respective SCLKX_Y_PD bit must be

cleared.

3. DCLKX_Y_DDLY_PD and SYSREF_DDLY_PD bits must be clear to power up the digital delay circuitry used

during SYNC to cause deterministic phase between the device clock dividers and the global SYSREF

divider.

4. The SYNC_DISX bit must be clear to allow SYNC/SYSREF signal to divider circuit. The SYSREF_MUX

register selects the SYNC source which resets the SYSREF/CLKoutX dividers provided the corresponding

SYNC_DISX bit is clear.

5. Other bits which impact the operation of SYNC such as SYNC_1SHOT_EN may be set as desired.

6. After these dividers are synchronized, the DCLKX_Y_DDLY_PD and SYSREF_DDLY_PD bits may be set to

save current. Clearing them to power up may disrupt the output clock phase.

表8-2 illustrates the some possible combinations of SYSREF_MUX and SYNC_MODE.

表8-2. Some Possible SYNC Configurations

NAME

SYNC_MODE

SYSREF_MUX

OTHER

DESCRIPTION

No SYNC will occur.

SYNC Disabled

0

CLKin0_DEMUX ≠0

Basic SYNC functionality, SYNC pin polarity is

selected by SYNC_POL.

To achieve SYNC through SPI, toggle the SYNC_POL

bit.

Pin or SPI SYNC

1

0

CLKin0_DEMUX ≠0

Differential input

SYNC

X

2

0 or 1

2

CLKin0_DEMUX = 0

Differential CLKin0 now operates as SYNC input.

Produce SYSREF_PULSE_CNT programmed

number of pulses on pin transition. SYNC_POL can

be used to cause SYNC through SPI.

JESD204B Pulser

on pin transition.

SYSREF_PULSE_CNT

sets pulse count

JESD204B Pulser

on SPI

programming.

SYSREF_PULSE_CNT

sets pulse count

Programming SYSREF_PULSE_CNT register starts

sending the number of pulses.

3

1

2

1

SYSREF operational,

SYSREF Divider as

required for training frame for non-JESD converters such as LM97600.

size.

Allows precise SYNC for n-bit frame training patterns

Re-clocked SYNC

When SYNC pin is asserted, continuous SYSERF

External SYSREF

request

SYSREF_REQ_EN = 1

Pulser powered up

pulses occur. Turning on and off of the pulses is

synchronized to prevent runt pulses from occurring on

SYSREF.

0

2

3

SYSREF_PD = 0

SYSREF_DDLY_PD = 0

Continuous

SYSREF

X

Continuous SYSREF signal.

SYSREF_PLSR_PD = 1

(1)

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NAME

表8-2. Some Possible SYNC Configurations (continued)

SYNC_MODE

SYSREF_MUX

OTHER

DESCRIPTION

Re-clocked

SYSREF

distribution

SYSREF_DDLY_PD = 1

SYSREF_PLSR_PD = 1

SYSREF_PD = 1.

Fan-out of CLKin0 reclocked to the clock distribution

path.

0

(1) SCLKX_Y_PD = 0 as required per SYSREF output. This applies to any SYNC or SYSREF output on SCLKX_Y when SCLKX_Y_MUX

= 1 (SYSREF output)

备注

Because the SYNC/SYSREF signal is reclocked by the Clock Distribution Path, an active clock must

be present on the Clock Distribution Path (either from VCO or Fin0/Fin1 pins in distribution mode) for

SYNC to take effect.

备注

Any device clock divider or the SYSREF divider which does not have the SYNC_DISX bit or

SYNC_DISSYSREF bit set will reset while SYNC/SYSREF Distribution Path is high. This is especially

important for the SYSREF divider which has the ability to reset itself if the SYNC_DISSYSREF = 0! Be

sure to set SYNC_DISX/SYNC_DISSYSREF bits as required.

备注

While using Divide-by-2 or Divide-by-3 for DCLK_X_Y_DIV, SYNC procedure requires to first program

Divide-by-4 and then back to Divide-by-2 or Divide-by-3 before doing SYNC.

8.3.3 JEDEC JESD204B

8.3.3.1 How to Enable SYSREF

表8-3 summarizes the bits needed to make SYSREF functionality operational.

表8-3. SYSREF Bits

REGISTER

0x140

FIELD

VALUE

DESCRIPTION

SYSREF_PD

0

Must be clear, power-up SYSREF circuitry including the SYSREF divider.

SYSREF_DDLY

_PD

Must be clear to power-up digital delay circuitry. Must be powered up during initial SYNC

to ensure deterministic timing to other clock dividers.

0x140

0x143

0

1

SYNC_EN

Must be set, enable SYNC.

Do not hold local SYSREF DDLY block in reset except at start.

Anytime SYSREF_PD = 1 because of user programming or device RESET, it is necessary

to set SYSREF_CLR for 15 VCO clock cycles to clear the local SYSREF digital delay.

Once cleared, SYSREF_CLR must be cleared to allow SYSREF to operate.

0x143

SYSREF_CLR

1 →0

Enabling JESD204B operation involves synchronizing all the clock dividers with the SYSREF divider, then

configuring the actual SYSREF functionality.

8.3.3.1.1 Setup of SYSREF Example

The following procedure is a programming example for a system which is to operate with a 3000-MHz VCO

frequency. Use CLKout0 and CLKout2 to drive converters at 1500 MHz. Use CLKout4 to drive an FPGA at 150

MHz. Synchronize the converters and FPGA using a two SYSREF pulses at 10 MHz.

1. Program registers 0x000 to 0x555 (refer to 节8.5.1). Key to prepare for SYSREF operations:

a. Prepare for manual SYNC: SYNC_POL = 0, SYNC_MODE = 1, SYSREF_MUX = 0

b. Setup output dividers as per example: DCLK0_1_DIV and DCLK2_3_DIV = 2 for frequency of 1500

MHz. DCLK4_5_DIV = 20 for frequency of 150 MHz.

c. Setup output dividers as per example: SYSREF_DIV = 300 for 10-MHz SYSREF.

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d. Setup SYSREF: SYSREF_PD = 0, SYSREF_DDLY_PD = 0, DCLK0_1_DDLY_PD = 0,

DCLK2_3_DDLY_PD = 0, DCLK4_5_DDLY_PD = 0, SYNC_EN = 1, SYSREF_PLSR_PD = 0,

SYSREF_PULSE_CNT = 1 (2 pulses). SCLK0_1_PD = 0, SCLK2_3_PD = 0, SCLK4_5_PD = 0.

e. Clear Local SYSREF DDLY: SYSREF_CLR = 1.

2. Establish deterministic phase relationships between SYSREF and Device Clock for JESD204B:

a. Set device clock and SYSREF divider digital delays: DCLK0_1_DDLY, DCLK2_3_DDLY,

DCLK4_5_DDLY, and SYSREF_DDLY.

b. Set device clock digital delay half steps: DCLK0_1_HS, DCLK2_3_HS, DCLK4_5_HS.

c. Set SYSREF clock digital delay as required to achieve known phase relationships: SCLK0_1_DDLY,

SCLK2_3_DDLY, and SCLK4_5_DDLY. If half step adjustments are required SCLK0_1_HS,

SCLK2_3_HS, and SCLK4_5_HS.

d. To allow SYNC to affect dividers: SYNC_DIS0 = 0, SYNC_DIS2 = 0, SYNC_DIS4 = 0,

SYNC_DISSYSREF = 0.

e. Perform SYNC by toggling SYNC_POL = 1 then SYNC_POL = 0.

3. Now that dividers are synchronized, disable SYNC from resetting these dividers. It is not desired for

SYSREF to reset it's own divider or the dividers of the output clocks.

a. Prevent SYNC (SYSREF) from affecting dividers: SYNC_DIS0 = 1, SYNC_DIS2 = 1, SYNC_DIS4 = 1,

SYNC_DISSYSREF = 1.

4. Release reset of local SYSREF digital delay.

a. SYSREF_CLR = 0. Note this bit needs to be set for only 15 clock distribution path clocks after

SYSREF_PD = 0.

5. Set SYSREF operation.

a. Allow pin SYNC event to start pulser: SYNC_MODE = 2.

b. Select pulser as SYSREF signal: SYSREF_MUX = 2.

6. Complete! Now asserting the SYNC pin, or toggling SYNC_POL will result in a series of 2 SYSREF pulses.

8.3.3.1.2 SYSREF_CLR

The local digital delay of the SCLKX_Y_DDLY is implemented as a shift buffer. To ensure no unwanted pulses

occur at this SYSREF output at start-up, when using SYSREF, requires clearing the buffers by setting

SYSREF_CLR = 1 for 15 VCO clock cycles. After a reset, this bit is set, so it must be cleared before SYSREF

output is used.

If the SYSREF pulser is used. It is also required to set SYSREF_CLR = 1 for 15 VCO clock cycles after the

SYSREF pulser is powered up.

8.3.3.2 SYSREF Modes

8.3.3.2.1 SYSREF Pulser

This mode allows for the output of 1, 2, 4, or 8 SYSREF pulses for every SYNC pin event or SPI programming.

This implements the gapped periodic functionality of the JEDEC JESD204B specification.

When in SYSREF Pulser mode, programming the field SYSREF_PULSE_CNT in register 0x13E will result in the

pulser sending the programmed number of pulses.

8.3.3.2.2 Continuous SYSREF

This mode allows for continuous output of the SYSREF clock.

备注

Continuous operation of SYSREF is not recommended due to crosstalk from the SYSREF clock to

device clock. JESD204B is designed to operate with a single burst of pulses to initialize the system at

start-up, after which it is theoretically not required to send another SYSREF because the system will

continue to operate with deterministic phases.

8.3.3.2.3 SYSREF Request

This mode allows an external source to synchronously turn on or off a continuous stream of SYSREF pulses

using the SYNC/SYSREF_REQ pin.

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Setup the mode by programming SYSREF_REQ_EN = 1 and SYSREF_MUX = 2 (Pulser). The pulser does not

need to be powered for this mode of operation.

When the SYSREF_REQ pin is asserted, the SYSREF_MUX will synchronously be set to continuous mode

providing continuous pulses at the SYSREF frequency until the SYSREF_REQ pin is unasserted and the final

SYSREF pulse will complete sending synchronously.

8.3.4 Digital Delay

Digital (coarse) delay allows a group of outputs to be delayed by 8 to 1023 clock distribution path cycles. The

delay step can be as small as half the period of the clock distribution path cycle by using the DCLKX_Y_HS bit.

There are two different ways to use the digital delay:

1. Fixed digital delay

2. Dynamic digital delay

In both delay modes, the regular clock divider is substituted with an alternative divide value.

8.3.4.1 Fixed Digital Delay

Fixed digital delay value takes effect on the clock outputs after a SYNC event. As such, the outputs will be LOW

for a while during the SYNC event. Applications that cannot accept clock breakup when adjusting digital delay

during application run time should use dynamic digital delay to adjust phase.

8.3.4.1.1 Fixed Digital Delay Example

Assuming the device already has the following initial configurations, and the application should delay CLKout2

by one VCO cycle compared to CLKout0.

• VCO frequency = 2949.12 MHz

• CLKout0 = 368.64 MHz (DCLK0_1_DIV = 8, CLKout0_SRC_MUX = 0 (Device Clock))

• CLKout2 = 368.64 MHz (DCLK2_3_DIV = 8, CLKout2_SRC_MUX = 0 (Device Clock))

The following steps should be followed

1. Set DCLK0_1_DDLY = 8 and DCLK2_3_DDLY = 9. Static delay for each clock.

2. Set DCLK0_1_DDLY_PD = 0 and DCLK2_3_DDLY_PD = 0. Power up the digital delay circuit.

3. Set SYNC_DIS0 = 0 and SYNC_DIS2 = 0. Allow the outputs to be synchronized.

4. Perform SYNC by asserting, then unasserting SYNC. Either by using SYNC_POL bit or the SYNC pin.

5. Now that the SYNC is complete, to save power it is allowable to power down DCLK0_1_DDLY_PD = 1

and/or DCLK2_3_DDLY_PD = 1.

6. Set SYNC_DIS0 = 1 and SYNC_DIS2 = 1. Prevent the output from being synchronized, very important for

steady-state operation when using JESD204B.

No CLKout during SYNC

CLKout0

368.64 MHz

CLKout2

368.64 MHz

SYNC event

1 VCO cycle delay

图8-4. Fixed Digital Delay Example

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8.3.4.2 Dynamic Digital Delay

Dynamic digital delay allows the phase of clocks to be changed with respect to each other with little impact to the

clock signal.

For the device clock dividers this is accomplished by substituting the regular clock divider with an alternate divide

value of one larger than the regular divider for one cycle. This substitution will occur a number of times equal to

the value programmed into the DDLYd_STEP_CNT field for all outputs with DDLYdX_EN = 1.

For the SYSREF divider an alternate divide value will be substituted for the regular divide value. This substitution

will occur

a number of times equal to the value programmed into the DDLYd_STEP_CNT if

DDLYd_SYSREF_EN = 1. To achieve one cycle delay as is done for the device clock dividers, set the

SYSREF_DDLY value to one greater than SYSREF_DIV+SYSREF_DIV/2. For example, for a SYSREF divider

of 100, to achieve 1 cycle delay, SYSREF_DIV = 100 + 50 + 1 = 151.

While using the Dynamic Digital Delay feature, CLKin_OVERRIDE must be set to 0.

• By programming a larger alternate divider (delay) value, the phase of the adjusted outputs are delayed with

respect to the other clocks.

• By programming a smaller alternate divider (delay) value, the phase of the adjusted outputs are advanced

with respect to the other clocks.

8.3.4.3 Single and Multiple Dynamic Digital Delay Example

In this example, two separate adjustments are made to the device clocks. In the first adjustment, a single delay

of 1 VCO cycle occurs between CLKout2 and CLKout0. In the second adjustment, two delays of 1 VCO cycle

occur between CLKout2 and CLKout0. At this point in the example, CLKout2 is delayed 3 VCO cycles behind

CLKout0.

Assuming the device already has the following initial configurations:

• VCO frequency: 2949.12 MHz

• CLKout0 = 368.64 MHz, DCLK0_1_DIV = 8

• CLKout2 = 368.64 MHz, DCLK2_3_DIV = 8

The following steps illustrate the example above:

1. Set DCLK2_3_DDLY = 4. First part of delay for CLKout2.

2. Set DCLK2_3_DDLY_PD = 0. Enable the digital delay for CLKout2.

3. Set DDLYd0_EN = 0 and DDLYd2_EN = 1. Enable dynamic digital delay for CLKout2 but not CLKout0.

4. Set DDLYd_STEP_CNT = 1. This begins the first adjustment.

Before step 4, CLKout2 clock edge is aligned with CLKout0.

After step 4, CLKout2 counts nine clock distribution path cycles to the next rising edge, one greater than the

divider value, effectively delaying CLKout2 by one VCO cycle with respect to CLKout0. This is the first

adjustment.

5. Set DDLYd_STEP_CNT = 2. This begins the second adjustment.

Before step 5, CLKout2 clock edge was delayed 1 clock distribution path cycle from DCLKout0.

After step 5, CLKout2 counts nine clock distribution path cycles twice, each time one greater than the divide

value, effectively delaying CLKout2 by two clock distribution path cycles with respect to CLKout0. This is the

second adjustment.

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VCO

2949.12 MHz

CLKout0

368.64 MHz

CLKout2

368.64 MHz

First

Adjustment

DCLK2_3_DIV + 1

CLKout2

368.64 MHz

Second

Adjustment

DCLK2_3_DIV + 1

图8-5. Single and Multiple Adjustment Dynamic Digital Delay Example

8.3.5 SYSREF to Device Clock Alignment

To ensure proper JESD204B operation, the timing relationship between the SYSREF and the Device clock must

be adjusted for optimum setup and hold time as shown in 图 8-6. The global SYSREF digital delay

(SYSREF_DDLY), local SYSREF digital delay (SCLKX_Y_DDLY), local SYSREF half step (SCLKX_Y_HS), and

local SYSREF analog delay (SCLKX_Y_ADLY, SCLK2_3_ADLY_EN) can be adjusted to provide the required

setup and hold time between SYSREF and Device Clock. It is also possible to adjust the device clock digital

delay (DCLKX_Y_DDLY) and half step (DCLK0_1_HS, DCLK0_1_DCC) to adjust phase with respect to

SYSREF.

图8-6. SYSREF to Device Clock Timing alignment

Depending on the DCLKout_X path settings, local SCLK_X_Y_DDLY might need adjustment factor. Following

equation can be used to calculate the required Digital Delay Values to align SYSREF to the corresponding

DCLKout:

SYSREF_DDLY = DCLKX_Y_DDLY –1 + DCLK_DIV_ADJUST + DCLK_HS_ADJUST –SCLK_X_Y_DDLY

(1)

SYSREF_DDLY > 7; SCLK_X_Y_DDLY > 1.

表8-4. DCLK_DIV_ADJUST

DCLKX_Y_DIV

DCLK_DIV_ADJUST

>6

6

0

–1

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表8-4. DCLK_DIV_ADJUST (continued)

DCLKX_Y_DIV

DCLK_DIV_ADJUST

5

2

4

0

3 ⁽¹⁾

2 ⁽¹⁾

–2

(1) Refer to the SYNC requirement 节8.3.2

表8-5. DCLK_HS_ADJUST

DCLK & HS

DCLK_HS_ADJUST

0

1

0

1

For example: DCLKX_Y_DIV = 32, DCLKX_Y_DDLY = 10, DCC&HS = 1;

SYSREF_DDLY=10 –1 + 0 + 1 –2 = 8

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8.3.6 Input Clock Switching

Manual, pin select, and automatic are three different kinds clock input switching modes can be selected

according to the combination of bits as illustrated in 图8-7.

Input Clock Select

It is required for CLKin1

to be selected for

distribution mode.

CLKin_SEL_

AUTO_EN

Yes

No

Recommend using

CLKin_SEL_MANUAL

Active CLKin is set Auto

Mode State Machine

CLKin_SEL_

PIN_EN

Yes

No

Active CLKin is set by

CLKin_SEL_MANUAL

CLKin_SEL_

PIN_POL

Yes

No

Active CLKin is set by

CLKin_SEL# and Status_LD1

pins, inverted.

Active CLKin is set by

CLKin_SEL# and Status_LD1

pins.

图8-7. CLKinX Input Reference

The following sections provide information about how the active input clock is selected and what causes a

switching event in the various clock input selection modes.

8.3.6.1 Input Clock Switching - Manual Mode

When CLKin_SEL_AUTO_EN = 0 and CLKin_SEL_PIN_EN = 0, the active CLKin is selected by

CLKin_SEL_MANUAL. Programming a value of 0, 1, or 2 to CLKin_SEL_MANUAL causes CLKin0, CLKin1, or

CLKin2, respectively, to be the selected active input clock. In this mode, the EN_CLKinX bits are overriden such

that the CLKinX buffer operates even if CLKinX is disabled with EN_CLKinX = 0.

If holdover is entered in this mode by setting CLKin_SEL_MANUAL = 3, then the device will re-lock to the

selected CLKin upon holdover exit.

8.3.6.2 Input Clock Switching - Pin Select Mode

When CLKin_SEL_AUTO_EN = 0 and CLKin_SEL_PIN_EN = 1, the active CLKin is selected by the

CLKin_SEL# and Status_LD1 pins.

Configuring Pin Select Mode

The CLKin_SEL0_TYPE must be programmed to an input value for the CLKin_SEL0 pin to function as an input

for pin select mode.

The CLKin_SEL1_TYPE must be programmed to an input value for the CLKin_SEL1 pin to function as an input

for pin select mode.

The polarity of the clock input select pins can be inverted with the CLKin_SEL_PIN_POL bit.

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The pin select mode overrides the EN_CLKinX bits such that the CLKinX buffer operates even if CLKinX is

disabled with EN_CLKinX = 0. To switch as fast as possible, keep the clock input buffers (that could be used to

switch to) enabled (EN_CLKinX = 1).

8.3.6.3 Input Clock Switching - Automatic Mode

When CLKin_SEL_AUTO_EN = 1, LOS_EN = 1, and HOLDOVER_EXIT_MODE = 0 (Exit based on LOS), the

active clock is selected in priority order with CLKin0 being the highest priority, CLKin1 second, and CLKin2 third.

For a clock input to be eligible to be switched to, it must be enabled using EN_CLKinX. The LOS_TIMEOUT

should also be set to a frequency below the input frequency.

To ensure LOS is valid for AC-coupled inputs, the MOS mode must be set for the CLKin and no termination is

allowed to be between the pins unless the pins are DC.blocked. For example, no 100-Ω termination across

CLKin0 and CLKin0* pins on IC side of AC-coupling capacitors.

8.3.7 Digital Lock Detect

Both PLL1 and PLL2 support digital lock detect. Digital lock detect compares the phase between the reference

path (R) and the feedback path (N) of the PLL. When the time error, which is phase error, between the two

signals is less than a specified window size (ε) a lock detect count increments. When the lock detect count

reaches a user specified value, PLL1_DLD_CNT or PLL2_DLD_CNT, lock detect is asserted true. Once digital

lock detect is true, a single phase comparison outside the specified window will cause digital lock detect to be

asserted false. This is illustrated in 图8-8.

NO

PLLX

Lock Detected = False

Lock Count = 0

YES

Increment

PLLX Lock Count

PLLX

Lock Detected = True

PLLX Lock Count =

PLLX_DLD_CNT

START

Phase Error < g

YES

NO

图8-8. Digital Lock Detect Flowchart

This incremental lock detect count feature functions as a digital filter to ensure that lock detect is not asserted for

only a brief time when the phases of R and N are within the specified tolerance for only a brief time during initial

phase lock.

See 节 9.1.2 for more detailed information on programming the registers to achieve a specified frequency

accuracy in ppm with lock detect.

The digital lock detect signal can be monitored on the Status_LD1 or Status_LD2 pin. The pin may be

programmed to output the status of lock detect for PLL1, PLL2, or both PLL1 and PLL2.

8.3.7.1 Calculating Digital Lock Detect Frequency Accuracy

See 节 9.1.2 for more detailed information on programming the registers to achieve a specified frequency

accuracy in ppm with lock detect.

The digital lock detect feature can also be used with holdover to automatically exit holdover mode. See 节

8.3.8.3 for more information.

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8.3.8 Holdover

Holdover mode causes PLL2 to stay locked on frequency with minimal frequency drift when an input clock

reference to PLL1 becomes invalid. While in holdover mode, the PLL1 charge pump is TRI-STATED and a fixed

tuning voltage is set on CPout1 to operate PLL1 in open loop.

8.3.8.1 Enable Holdover

Program HOLDOVER_EN = 1 to enable holdover mode.

Holdover mode can be configured to set the CPout1 voltage upon holdover entry to a fixed user defined voltage

(EN_MAN_DAC = 1) or a tracked voltage (EN_MAN_DAC = 0).

8.3.8.1.1 Fixed (Manual) CPout1 Holdover Mode

By programming MAN_DAC_EN = 1, then the MAN_DAC value will be set on the CPout1 pin during holdover.

The user can optionally enable CPout1 voltage tracking (TRACK_EN = 1), read back the tracked DAC value,

then re-program MAN_DAC value to a user desired value based on information from previous DAC read backs.

This allows the most user control over the holdover CPout1 voltage, but also requires more user intervention.

8.3.8.1.2 Tracked CPout1 Holdover Mode

By programming MAN_DAC_EN = 0 and TRACK_EN = 1, the tracked voltage of CPout1 is set on the CPout1

pin during holdover. When the DAC has acquired the current CPout1 voltage, the DAC_Locked signal is set,

which may be observed on Status_LD1 or Status_LD2 pins by programming PLL1_LD_MUX or PLL2_LD_MUX,

respectively.

Updates to the DAC value for the Tracked CPout1 sub-mode occurs at the rate of the PLL1 phase detector

frequency divided by (DAC_CLK_MULT × DAC_CLK_CNTR).

The DAC update rate should be programmed for ≤100 kHz to ensure DAC holdover accuracy.

The ability to program slow DAC update rates, for example one DAC update per 4.08 seconds when using 1024-

kHz PLL1 phase detector frequency with DAC_CLK_MULT = 16,384 and DAC_CLK_CNTR = 255, allows the

device to look-back and set CPout1 at a previous good CPout1 tuning voltage values before the event which

caused holdover to occur.

The current voltage of DAC value can be read back using RB_DAC_VALUE, see 节8.6.2.9.6.

8.3.8.2 During Holdover

PLL1 is run in open-loop mode.

• PLL1 charge pump is set to TRI-STATE.

• PLL1 DLD is unasserted.

• The HOLDOVER status is asserted

• During holdover, if PLL2 was locked prior to entry of holdover mode, PLL2 DLD continues to be asserted.

• CPout1 voltage is set to:

– a voltage set in the MAN_DAC register (MAN_DAC_EN = 1).

– a voltage determined to be the last valid CPout1 voltage (MAN_DAC_EN = 0).

• PLL1 attempts to lock with the active clock input.

The HOLDOVER status signal can be monitored on the Status_LD1 or Status_LD2 pin by programming the

PLL1_DLD_MUX or PLL2_DLD_MUX register to Holdover Status.

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8.3.8.3 Exiting Holdover

Holdover mode can be exited in one of two ways.

• Manually, by programming the device from the host.

• Automatically, when the LOS signal unasserts for a clock that provides a valid input to PLL1.

8.3.8.4 Holdover Frequency Accuracy and DAC Performance

When in holdover mode, PLL1 runs in open loop and the DAC sets the CPout1 voltage. If fixed CPout1 mode is

used, then the output of the DAC is dependant upon the MAN_DAC register. If tracked CPout1 mode is used,

then the output of the DAC is approximately the same voltage at the CPout1 pin before holdover mode was

entered. When using Tracked mode and MAN_DAC_EN = 1, the DAC value during holdover is loaded with the

programmed value in MAN_DAC and not the tracked value.

When in Tracked CPout1 mode, the DAC has a worst-case tracking error of ±2 LSBs once PLL1 tuning voltage

is acquired. The step size is approximately 3.2 mV, therefore the VCXO frequency error during holdover mode

caused by the DAC tracking accuracy is ±6.4 mV × Kv, where Kv is the tuning sensitivity of the VCXO in use.

Therefore, the accuracy of the system when in holdover mode in ppm is:

6.4 mV × Kv × 1e6

Holdover accuracy (ppm) =

VCXO Frequency

(2)

As an example, consider a system with a 19.2-MHz clock input, a 153.6-MHz VCXO with a Kv of 17 kHz/V. The

accuracy of the system in holdover in ppm is:

±0.71 ppm = ±6.4 mV × 17 kHz/V × 1e6 / 153.6 MHz

(3)

It is important to account for this frequency error when determining the allowable frequency error window to

cause holdover mode to exit.

8.3.9 PLL2 Loop Filter

PLL2 has an integrated loop filter of C1i = 60 pF, R3 = 2400 Ω, C3 = 50 pF, R4 = 200 Ω and C4 = 10 pF as

shown in 图 8-9. Loop filter components C1, C2, and R2 can be solved using TI software. See 节 10.1 for more

information.

图8-9. PLL2 On-Chip Loop Filter

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8.4 Device Functional Modes

The LMK04832-SP is a flexible device that can be configured for many different use cases. The following

simplified block diagrams help show the user the different use cases of the device.

8.4.1 DUAL PLL

8.4.1.1 Dual Loop

图 8-10 illustrates the typical use case of dual loop mode. In dual loop mode, the reference to PLL1 is from

CLKin0, CLKin1, or CLKin2. An external VCXO is used to provide feedback for the first PLL and a reference to

the second PLL. This first PLL cleans the jitter with the VCXO by using a narrow loop bandwidth. The VCXO

may be buffered through the OSCout port. The VCXO is used as the reference to PLL2 and may be doubled

using the frequency doubler. The internal VCO drives up to seven divide/delay blocks which drive up to 14 clock

outputs.

Hitless switching and holdover functionality are optionally available when the input reference clock is lost.

Holdover works by forcing a DAC voltage to the tuning voltage of the VCXO.

It is also possible to use an external VCO in place of PLL2's internal VCO. In this case one less CLKin is

available as a reference as CLKin1 is used for external input.

PLL1

PLL2

Up to 1 OSCout

External

Loop Filter

OSCout

External

VCXO

Up to 14

Device or

SYSREF

Clocks

OSCout*

CLKinX

CLKinX*

Up to 3

inputs

CPout2

R

N

Phase

Detector

PLL1

7 blocks

External

Loop Filter

Dual Internal

VCOs

R

Device Clock

Divider

Digital Delay

Phase

Detector

PLL2

CLKoutX

CLKoutX*

Input

Buffer

N

7 blocks

SYSREF

Digital Delay

Analog Delay

CLKoutY

CLKoutY*

Global SYSREF

Divider and DDLY

LMK04832

图8-10. Simplified Functional Block Diagram for Dual Loop Mode

8.4.1.2 Dual Loop With Cascaded 0-Delay

图 8-11 illustrates the use case of cascaded 0-delay dual loop mode. This configuration differs from dual loop

mode 图8-10 in that the feedback for PLL2 is driven by a clock output instead of the VCO output directly.

It is also possible to use an external VCO in place of the internal VCO of the PLL2, but one less CLKin is

available as a reference and the external 0-delay feedback is not available.

PLL1

PLL2

Up to 1 OSCout

External

Loop Filter

OSCout

External

VCXO

Up to 14

Device or

SYSREF

Clocks

OSCout*

CLKinX

CLKinX*

Up to 3

inputs

CPout2

R

N

Phase

Detector

PLL1

7 blocks

External

Loop Filter

Dual Internal

VCOs

R

Device Clock

Divider

Digital Delay

Phase

Detector

PLL2

CLKoutX

CLKoutX*

Input

Buffer

N

7 blocks

SYSREF

Digital Delay

Analog Delay

CLKoutY

CLKoutY*

Global SYSREF

Divider and DDLY

Internal or external loopback, user programmable

LMK04832

图8-11. Simplified Functional Block Diagram for Cascaded 0-Delay Dual Loop Mode

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8.4.1.3 Dual Loop With Nested 0-Delay

图 8-12 illustrates the use case of nested 0-delay dual loop mode. This configuration is similar to the dual PLL in

图 8-10 except that the feedback to the first PLL is driven by a clock output. The PLL2 reference OSCin is not

deterministic to the CLKin or feedback clock.

PLL1

PLL2

Up to 1 OSCout

External

Loop Filter

OSCout

External

VCXO

Up to 14

Device or

SYSREF

Clocks

OSCout*

CLKinX

CLKinX*

Up to 3

inputs

CPout2

R

N

Phase

Detector

PLL1

7 blocks

External

Loop Filter

Dual Internal

VCOs

R

Device Clock

Divider

Digital Delay

Phase

Detector

PLL2

CLKoutX

CLKoutX*

Input

Buffer

N

7 blocks

SYSREF

Digital Delay

Analog Delay

CLKoutY

CLKoutY*

Global SYSREF

Divider and DDLY

Internal or external loopback, user programmable

LMK04832

图8-12. Simplified Functional Block Diagram for Nested 0-Delay Dual Loop Mode

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8.4.2 Single PLL

8.4.2.1 PLL2 Single Loop

图 8-13 illustrates the use case of PLL2 single loop mode. When used with a high-frequency clean reference

performance as good as dual loop mode may be achieved. Traditionally the OSCin is used as a reference to

PLL2, but it is also possible to use CLKinX as a reference to PLL2.

PLL2

Up to 1 OSCout

External

Loop Filter

OSCout

OSCout*

Up to 4

inputs

Up to 14

Device or

SYSREF

Clocks

CPout2

7 blocks

Dual Internal

VCOs

OSCin

OSCin*

R

N

Device Clock

Divider

Digital Delay

Phase

Detector

PLL2

CLKoutX

CLKoutX*

Input

Buffer

7 blocks

CLKinX

CLKinX*

SYSREF

Digital Delay

Analog Delay

CLKoutY

CLKoutY*

Global SYSREF

Divider and DDLY

LMK04832

图8-13. Simplified Functional Block Diagram for Single Loop Mode

8.4.2.2 PLL2 With External VCO

Adding an external VCO is possible using the Fin0/Fin1 input pins. The input may be single-ended or differential.

At high frequency the input impedance to Fin0/Fin1 is low, a resistive pad is recommended for matching.

External VCO

PLL2

Up to 1 OSCout

External

Loop Filter

OSCout

OSCout*

Up to 3

inputs

Up to 14

Device or

SYSREF

Clocks

CLKin1/Fin

CLKin1*/Fin*

CPout2

7 blocks

OSCin

OSCin*

R

N

Device Clock

Divider

Digital Delay

Phase

Detector

PLL2

CLKoutX

CLKoutX*

Input

Buffer

7 blocks

CLKinX

CLKinX*

SYSREF

Digital Delay

Analog Delay

CLKoutY

CLKoutY*

Global SYSREF

Divider and DDLY

LMK04832

图8-14. Simplified Functional Block Diagram for Single Loop Mode With External VCO

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8.4.3 Distribution Mode

图 8-15 illustrates the use case of distribution mode. As in all the other use cases, OSCin to OSCout can be

used as a buffer to OSCin or from clock distribution path through CLKout6, CLKout8, or the SYSREF divider.

At high frequency, the input impedance to Fin0/Fin1 is low and a resistive pad is recommended for matching.

OSCin

OSCout

OSCin*

OSCout*

7 blocks

CLKout6/8

Fin0

Fin0*

Device Clock

Divider

Digital Delay

CLKoutX

CLKoutX*

Fin1

Fin1*

7 blocks

SYSREF

Digital Delay

Analog Delay

CLKoutY

CLKoutY*

Global SYSREF

Divider and DDLY

CLKin0

CLKin0*

图8-15. Simplified Functional Block Diagram for Distribution Mode

8.5 Programming

The LMK04832 device is programmed using 24-bit registers. Each register consists of a 1-bit command field

(R/W), a 15-bit address field (A14 to A0) and a 8-bit data field (D7 to D0). The contents of each register is

clocked in MSB first (R/W), and the LSB (D0) last. During programming, the CS* signal is held low. The serial

data is clocked in on the rising edge of the SCK signal. After the LSB is clocked in, the CS* signal goes high to

latch the contents into the shift register. TI recommends to program registers in numeric order (for example,

0x000 to 0x555 with exceptions noted in the 节 8.5.1). Each register consists of one or more fields which control

the device functionality. See the 节6.5 section and 图6-1 for timing details.

8.5.1 Recommended Programming Sequence

Registers are generally programmed in numeric order with 0x000 being the first and 0x555 being the last register

programmed. The recommended programming sequence from POR involves:

1. Program register 0x000 with RESET = 1.

2. Program defined registers from 0x000 to 0x165.

3. If PLL2 is used, program 0x173 with PLL2_PD and PLL2_PRE_PD clear to allow PLL2 to lock after PLL2_N

is programmed.

4. Continue programming defined registers from 0x166 to 0x555.

备注

When using the internal VCO, PLL2_N registers 0x166, 0x167, and 0x168 must be programmed after

other PLL2 dividers are programed to ensure proper VCO frequency calibration. This is also true for

PLL2_N_CAL registers 0x163, 0x164, 0x165 when PLL2_NCLK_MUX = 1. So if any divider such as

PLL2_R is altered to change the VCO frequency, the VCO calibration must be run again by

programming PLL2_N.

Power up PLL2 by setting PLL2_PRE_PD = 0 and PLL2_PD = 0 in register 0x173 before

programming PLL2_N.

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8.6 Register Maps

8.6.1 Register Map for Device Programming

表 8-6 provides the register map for device programming. Any register can be read from the same data address

it is written to.

表8-6. Register Map

ADDRESS

DATA[7:0]

[14:0]

23:8

7

6

5

4

3

2

1

0

SPI_3WIRE

_DIS

0x000

RESET

0

POWER

DOWN

0x002

0

0x003

0x004

0x005

0x006

0x00C

0x00D

0x100

0x101

ID_DEVICE_TYPE

ID_PROD[15:8]

ID_PROD[7:0]

ID_MASKREV

ID_VNDR[15:8]

ID_VNDR[7:0]

DCLK0_1_DIV[7:0]

DCLK0_1_DDLY[7:0]

CLKout0_1_OD

L

DCLK0_1_DDLY

_PD

0x102

0x103

0x104

0x105

CLKout0_1_PD

CLKout0_1_IDL

DCLK0_1_DDLY[9:8]

DCLK0_1_BYP DCLK0_1_DCC DCLK0_1_POL

SCLK0_1_DIS_MODE SCLK0_1_POL

SCLK0_1_ADLY

SCLK0_1_DDLY

DCLK0_1_DIV[9:8]

CLKout0_SRC_

MUX

0

1

0

DCLK0_1_PD

SCLK0_1_PD

DCLK0_1_HS

SCLK0_1_HS

CLKout1_SRC_

MUX

SCLK0_1_ADLY

_EN

0

0x106

0x107

0x108

0x109

0

CLKout1_FMT

CLKout0_FMT

DCLK2_3_DIV[7:0]

DCLK2_3_DDLY[7:0]

DCLK2_3_DDLY

CLKout2_3_OD

L

0x10A

0x10B

0x10C

0x10D

CLKout2_3_PD

CLKout2_3_IDL

DCLK2_3_DDLY[9:8]

DCLK2_3_DIV[9:8]

_PD

CLKout2_SRC_

MUX

0

1

0

DCLK2_3_PD

DCLK2_3_BYP DCLK2_3_DCC DCLK2_3_POL

DCLK2_3_HS

SCLK2_3_HS

CLKout3_SRC_

MUX

SCLK2_3_PD

SCLK2_3_DIS_MODE

SCLK2_3_ADLY

SCLK2_3_DDLY

SCLK2_3_POL

SCLK2_3_ADLY

_EN

0

0x10E

0x10F

0x110

0x111

0

CLKout3_FMT

CLKout2_FMT

DCLK4_5_DIV[7:0]

DCLK4_5_DDLY[7:0]

DCLK4_5_DDLY

CLKout4_5_OD

L

0x112

0x113

0x114

0x115

CLKout4_5_PD

CLKout4_5_IDL

DCLK4_5_DDLY[9:8]

DCLK4_5_DIV[9:8]

_PD

CLKout4_SRC_

MUX

0

1

0

DCLK4_5_PD

DCLK4_5_BYP DCLK4_5_DCC DCLK4_5_POL

DCLK4_5_HS

SCLK4_5_HS

CLKout5_SRC_

MUX

SCLK4_5_PD

SCLK4_5_DIS_MODE

SCLK4_5_ADLY

SCLK4_5_POL

SCLK4_5_ADLY

_EN

0

0x116

0x117

0x118

0

SCLK4_5_DDLY

CLKout4_FMT

CLKout5_FMT

DCLK6_7_DIV[7:0]

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表8-6. Register Map (continued)

ADDRESS

[14:0]

DATA[7:0]

23:8

7

6

5

4

3

2

1

0

0x119

DCLK6_7_DDLY[7:0]

CLKout6_7_OD

L

DCLK6_7_DDLY

_PD

0x11A

0x11B

0x11C

0x11D

CLKout6_7_PD

CLKout6_7_IDL

DCLK6_7_DDLY[9:8]

DCLK6_7_BYP DCLK6_7_DCC DCLK6_7_POL

SCLK6_7_DIS_MODE SCLK6_7_POL

SCLK6_7_ADLY

SCLK6_7_DDLY

DCLK6_7_DIV[9:8]

CLKout6_SRC_

MUX

0

1

0

DCLK6_7_PD

SCLK6_7_PD

DCLK6_7_HS

SCLK6_7_HS

CLKout7_SRC_

MUX

SCLK6_7_ADLY

_EN

0

0x11E

0x11F

0x120

0x121

0

CLKout7_FMT

CLKout6_FMT

DCLK8_9_DIV[7:0]

DCLK8_9_DDLY[7:0]

DCLK8_9_DDLY

CLKout8_9_OD

L

0x122

0x123

0x124

0x125

CLKout8_9_PD

CLKout8_9_IDL

DCLK8_9_DDLY[9:8]

DCLK8_9_DIV[9:8]

_PD

CLKout8_SRC_

MUX

0

1

0

DCLK8_9_PD

DCLK8_9_BYP DCLK8_9_DCC DCLK8_9_POL

DCLK8_9_HS

SCLK8_9_HS

CLKout9_SRC_

MUX

SCLK8_9_PD

SCLK8_9_DIS_MODE

SCLK8_9_ADLY

SCLK8_9_POL

SCLK8_9_ADLY

_EN

0

0x126

0x127

0x128

0x129

0

SCLK8_9_DDLY

CLKout8_FMT

CLKout9_FMT

DCLK10_11_DIV[7:0]

DCLK10_11_DDLY[7:0]

CLKout10_11_P CLKout10_11_O CLKout10_11_I DCLK10_11_DD

0x12A

0x12B

0x12C

0x12D

DCLK10_11_DDLY[9:8]

DCLK10_11_DIV[9:8]

D

DL

LY_PD

CLKout10_SRC

_MUX

DCLK10_11_BY DCLK10_11_DC DCLK10_11_PO

0

1

DCLK10_11_PD

DCLK10_11_HS

SCLK10_11_HS

P

C

L

CLKout11_SRC

_MUX

SCLK10_11_PO

L

0

SCLK10_11_PD

SCLK10_11_DIS_MODE

SCLK10_11_ADLY

SCLK10_11_AD

LY_EN

0

0x12E

0x12F

0x130

0x131

0

SCLK10_11_DDLY

CLKout10_FMT

CLKout11_FMT

DCLK12_13_DIV[7:0]

DCLK12_13_DDLY[7:0]

CLKout12_13_P CLKout12_13_O CLKout12_13_I DCLK12_13_DD

0x132

0x133

0x134

0x135

DCLK12_13_DDLY[9:8]

DCLK12_13_DIV[9:8]

D

DL

LY_PD

CLKout12_SRC

_MUX

DCLK12_13_BY DCLK12_13_DC DCLK12_13_PO

0

1

DCLK12_13_PD

DCLK12_13_HS

SCLK12_13_HS

P

C

L

CLKout13_SRC

_MUX

SCLK12_13_PO

L

0

SCLK12_13_PD

SCLK12_13_DIS_MODE

SCLK12_13_ADLY

SCLK12_13_DDLY

SCLK12_13_AD

LY_EN

0

0x136

0x137

0x138

0

CLKout13_FMT

VCO_MUX

CLKout12_FMT

OSCout_FMT

0

OSCout_MUX

SYSREF_REQ_

EN

0x139

0

SYNC_BYPASS

0

SYSREF_MUX

0x13A

0x13B

0x13C

0x13D

SYSREF_DIV[12:8]

SYSREF_DIV[7:0]

0

SYSREF_DDLY[12:8]

SYSREF_DDLY[7:0]

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表8-6. Register Map (continued)

ADDRESS

[14:0]

DATA[7:0]

23:8

7

6

5

4

3

2

1

0

0x13E

0

SYSREF_PULSE_CNT

PLL2_RCLK_

MUX

PLL2_NCLK_

MUX

0x13F

0x140

0

PLL1_NCLK_MUX

FB_MUX

FB_MUX_EN

SYSREF_GBL_

PD

SYSREF_DDLY SYSREF_PLSR

PLL1_PD

VCO_LDO_PD

DDLYd12_EN

VCO_PD

OSCin_PD

SYSREF_PD

DDLYd4_EN

_PD

DDLYd_

SYSREF_EN

0x141

0x142

0x143

DDLYd10_EN

DDLYd8_EN

DDLYd6_EN

DDLYd2_EN

DDLYd0_EN

DDLYd_STEP_CNT

SYNC_1SHOT_

EN

SYNC_PLL2_

DLD

SYNC_PLL1_

DLD

SYSREF_CLR

SYNC_POL

SYNC_EN

SYNC_MODE

SYNC_DISSYS

REF

0x144

0x145

0x146

SYNC_DIS12

SYNC_DIS10

SYNC_DIS8

SYNC_DIS6

SYNC_DIS4

FIN0_DIV2_EN

CLKin2_TYPE

SYNC_DIS2

SYNC_DIS0

PLL1R_SYNC_

EN

PLL2R_SYNC_

EN

2

PLL1R_SYNC_SRC

FIN0_INPUT_TYPE

CLKin_SEL_PIN CLKin_SEL_PIN

CLKin2_EN

CLKin1_EN

CLKin0_EN

CLKin1_TYPE

CLKin0_TYPE

_EN

_POL

CLKin_SEL_

AUTO_

REVERT_EN

CLKin_SEL_

AUTO_EN

0x147

CLKin_SEL_MANUAL

CLKin1_DEMUX

CLKin0_DEMUX

0x148

0x149

0x14A

0x14B

0

CLKin_SEL0_MUX

CLKin_SEL1_MUX

RESET_MUX

CLKin_SEL0_TYPE

CLKin_SEL1_TYPE

RESET_TYPE

SDIO_RDBK_

TYPE

0

HOLDOVER_

FORCE

LOS_TIMEOUT

LOS_EN

TRACK_EN

MAN_DAC_EN

MAN_DAC[9:8]

0x14C

0x14D

0x14E

0x14F

MAN_DAC[7:0]

0

DAC_TRIP_LOW

DAC_TRIP_HIGH

DAC_CLK_MULT

DAC_CLK_CNTR

CLKin_OVERRI

DE

HOLDOVER_

EXIT_MODE

HOLDOVER_ LOS_EXTERNA HOLDOVER_ CLKin_SWITCH HOLDOVER_

0x150

0

PLL1_DET

L_INPUT

HOLDOVER_DLD_CNT[13:8]

HOLDOVER_DLD_CNT[7:0]

CLKin0_R[13:8]

VTUNE_DET

_CP_TRI

EN

0x151

0x152

0x153

0x154

0x155

0x156

0x157

0x158

0x159

0x15A

0x15B

0x15C

0x15D

0x15E

0x15F

0x160

0x161

0

CLKin0_R[7:0]

CLKin1_R[7:0]

CLKin2_R[7:0]

PLL1_N[7:0]

CLKin1_R[13:8]

CLKin2_R[13:8]

PLL1_N[13:8]

PLL1_WND_SIZE

PLL1_CP_TRI

PLL1_CP_POL

PLL1_CP_GAIN

PLL1_DLD_CNT[13:8]

0

PLL1_DLD_CNT[7:0]

0

HOLDOVER_EXIT_NADJ

PLL1_LD_TYPE

PLL2_R

PLL1_LD_MUX

0

PLL2_R

PLL2_REF_2X_

EN

0x162

PLL2_P

0

OSCin_FREQ

PLL2_XTAL_EN

0x163

0x164

0

PLL2_N_CAL[17:16]

PLL2_N_CAL[15:8]

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表8-6. Register Map (continued)

ADDRESS

[14:0]

DATA[7:0]

23:8

7

6

5

4

3

2

1

0

0x165

0x166

0x167

0x168

0x169

0x16A

0x16B

0x16C

0x173

0x177

PLL2_N_CAL[7:0]

0

PLL2_N[17:16]

PLL2_N[15:8]

PLL2_N[7:0]

0

PLL2_WND_SIZE

PLL2_CP_GAIN

PLL2_CP_POL

PLL2_CP_TRI

PLL2_DLD_EN

0

PLL2_DLD_CNT[13:8]

PLL2_DLD_CNT[7:0]

0

PLL2_PRE_PD

PLL2_PD

PLL1R_RST

FIN0_PD

CLR_PLL1_LD_ CLR_PLL2_LD_

0x182

0x183

0

LOST

RB_PLL1_DLD_

LOST

RB_PLL2_DLD_

LOST

RB_PLL1_DLD

RB_PLL2_DLD

RB_CLKin2_

SEL

RB_CLKin1_

SEL

RB_CLKin0_

SEL

RB_CLKin2_

LOS

RB_CLKin1_

LOS

RB_CLKin0_

LOS

0x184

0x185

0x188

0x555

RB_DAC_VALUE[9:8]

RB_DAC_VALUE[7:0]

RB_DAC_RAIL RB_DAC_HIGH RB_DAC_LOW

SPI_LOCK

RB_

HOLDOVER

RB_DAC_

LOCKED

0

X

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8.6.2 Device Register Descriptions

The following section details the fields of each register, the Power-On-Reset Defaults, and specific descriptions

of each bit.

In some cases similar fields are located in multiple registers. In this case specific outputs may be designated as

X or Y. In these cases, the X represents even numbers from 0 to 12 and the Y represents odd numbers from 1 to

13. In the case where X and Y are both used in a bit name, then Y = X + 1.

8.6.2.1 System Functions

8.6.2.1.1 RESET, SPI_3WIRE_DIS

This register contains the RESET function and the ability to turn off 3-wire SPI mode. To use a 4-wire SPI mode,

selecting SPI Read back in one of the output MUX settings. For example CLKin0_SEL_MUX or RESET_MUX. It

is possible to have 3-wire and 4-wire readback at the same time.

表8-7. Register 0x000

BIT

7

NAME

RESET

NA

POR DEFAULT

DESCRIPTION

0: Normal operation

1: Reset (automatically cleared)

0

6:5

Reserved

Disable 3-wire SPI mode.

0: 3 Wire Mode enabled

1: 3 Wire Mode disabled

4

SPI_3WIRE_DIS

NA

0

3:0

NA

Reserved

8.6.2.1.2 POWERDOWN

This register contains the POWERDOWN function.

表8-8. Register 0x002

BIT

7:1

NAME

POR DEFAULT

DESCRIPTION

NA

POWERDOWN

0

Reserved

0: Normal operation

1: Power down device.

0

8.6.2.1.3 ID_DEVICE_TYPE

This register contains the product device type. This is read only register.

表8-9. Register 0x003

BIT

NAME

POR DEFAULT

DESCRIPTION

7:0

ID_DEVICE_TYPE

6

PLL product device type.

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8.6.2.1.4 ID_PROD

These registers contain the product identifier. This is a read only register.

表8-10. ID_PROD Field Registers

MSB

LSB

0x004[7:0] / ID_PROD[15:8]

0x005[7:0] / ID_PROD[7:0]

表8-11. Registers 0x004 and 0x005

REGISTER

0x004

BIT

7:0

FIELD NAME

ID_PROD[15:8]

ID_PROD[7:0]

POR DEFAULT

DESCRIPTION

MSB of the product identifier.

LSB of the product identifier.

209 (0xD1)

99 (0x63)

0x005

8.6.2.1.5 ID_MASKREV

This register contains the IC version identifier. This is a read only register.

表8-12. Register 0x006

BIT

NAME

POR DEFAULT

DESCRIPTION

7:0

ID_MASKREV

112 (0x70)

IC version identifier

8.6.2.1.6 ID_VNDR

These registers contain the vendor identifier. This is a read only register.

表8-13. ID_VNDR Field Registers

MSB

LSB

0x00C[7:0] / ID_VNDR[15:8]

0x00D[7:0] / ID_VNDR[7:0]

表8-14. Registers 0x00C, 0x00D

REGISTER BIT

NAME

POR DEFAULT

DESCRIPTION

0x00C

0x00D

7:0

ID_VNDR[15:8]

ID_VNDR[7:0]

81 (0x51)

MSB of the vendor identifier.

LSB of the vendor identifier.

4 (0x04)

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8.6.2.2 (0x100 - 0x138) Device Clock and SYSREF Clock Output Controls

8.6.2.2.1 DCLKX_Y_DIV

The device clock divider can drive up to two outputs, an even (X) and an odd (Y) clock output. Divide is a 10 bit

number and split across two registers.

表8-15. DCLKX_Y_DIV Field Registers

MSB

LSB

0x0102[1:0] = DCLK0_1_DIV[9:8]

0x010A[1:0] = DCLK2_3_DIV[9:8]

0x0112[1:0] = DCLK4_5_DIV[9:8]

0x011A[1:0] = DCLK6_7_DIV[9:8]

0x0122[1:0] = DCLK8_9_DIV[9:8]

0x012A[1:0] = DCLK10_11_DIV[9:8]

0x0132[1:0] = DCLK12_13_DIV[9:8]

0x100[7:0] = DCLK0_1_DIV[7:0]

0x108[7:0] = DCLK2_3_DIV[7:0]

0x110[7:0] = DCLK4_5_DIV[7:0]

0x118[7:0] = DCLK6_7_DIV[7:0]

0x120[7:0] = DCLK8_9_DIV[7:0]

0x128[7:0] = DCLK10_11_DIV[7:0]

0x130[7:0] = DCLK12_13_DIV[7:0]

表8-16. Registers 0x100, 0x108, 0x110, 0x118, 0x120, 0x128, and 0x130

0x102, 0x10A, 0x112, 0x11A, 0x122, 0x12A, 0x132

REGISTER

BIT NAME

POR DEFAULT

DESCRIPTION

0x102,

0x10A,

0x112,

0x11A,

0x122,

DCLKX_Y_DIV sets the divide value for the clock output, the divide

may be even or odd. Both even or odd divides output a 50% duty

cycle clock if duty cycle correction (DCC) is enabled.

1:0

7:0

DCLKX_Y_DIV[9:8]

X_Y = 0_1 →2

X_Y = 2_3 →4

X_Y = 4_5 →8

X_Y = 6_7 →8

X_Y = 8_9 →8

X_Y = 10_11 →8

X_Y = 12_13 →2

Field Value

0 (0x00)

Divider Value

Reserved

1 ⁽¹⁾

0x12A, 0x132

1 (0x01)

0x100,

0x108,

0x110, 0x118,

0x120,

2 (0x02)

2

...

DCLKX_Y_DIV[7:0]

1022 (0x3FE)

1023 (0x3FF)

1022

1023

0x128, and

0x130

(1) Duty cycle correction must also be enabled, DCLKX_Y_DCC = 1.

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8.6.2.2.2 DCLKX_Y_DDLY

This register controls the digital delay for the device clock outputs.

表8-17. DCLKX_Y_DDLY Field Registers

MSB

LSB

0x0102[2:3] = DCLK0_1_DDLY[9:8]

0x010A[2:3] = DCLK2_3_DDLY[9:8]

0x0112[2:3] = DCLK4_5_DDLY[9:8]

0x011A[2:3] = DCLK6_7_DDLY[9:8]

0x0122[2:3] = DCLK8_9_DDLY[9:8]

0x012A[2:3] = DCLK10_11_DDLY[9:8]

0x0132[2:3] = DCLK12_13_DDLY[9:8]

0x101[7:0] = DCLK0_1_DDLY[7:0]

0x109[7:0] = DCLK2_3_DDLY[7:0]

0x111[7:0] = DCLK4_5_DDLY[7:0]

0x119[7:0] = DCLK6_7_DDLY[7:0]

0x121[7:0] = DCLK8_9_DDLY[7:0]

0x129[7:0] = DCLK10_11_DDLY[7:0]

0x131[7:0] = DCLK12_13_DDLY[7:0]

表8-18. Registers 0x101, 0x109, 0x111, 0x119, 0x121, 0x129, 0x131

0x102, 0x10A, 0x112, 0x11A, 0x122, 0x12A, 0x132

REGISTER

BIT NAME

POR DEFAULT

DESCRIPTION

0x102,

0x10A,

0x112,

0x11A,

0x122,

Static digital delay which takes effect after a SYNC.

Field Value

0 (0x00)

1 (0x01)

...

Delay Values

Reserved

2:3 DCLKX_Y_DDLY[9:8]

Reserved

0x12A, 0x132

...

10 (0x0A)

7 (0x07)

8 (0x08)

9 (0x09)

...

Reserved

0x101,

0x109, 0x111,

0x119,

8

9

7:0 DCLKX_Y_DDLY[7:0]

0x121,

...

0x129, 0x131

1022 (0x3FE)

1023 (0x3FF)

1022

1023

Depending on the DCLK divide value, there may be an adjustment in phase delay required. 表 8-19 illustrate the

impact of different divide values on the final digital delay.

表8-19. Digital Delay Adjustment based on Divide Values

DIVIDE VALUE

DIGITAL DELAY ADJUSTMENT

–2⁽¹⁾

0

2, 3

4, 7 to 1023

5

6

+2

+1

(1) Before SYNC, program divider to Divide-by-4, then back to Divide-by-2 or Divide-by-3 to ensure '-2' delay relationship.

For example, 表 8-20 illustrates a system with clock outputs having divide values /2,/4,/5 and /6 to share a

common edge.

表8-20. Digital Delay Adjustment Illustration

DIVIDE VALUE

PROGRAMMED DDLY

ACTUAL DDLY

2

4

5

6

13

11

8

11

10

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8.6.2.2.3 CLKoutX_Y_PD, CLKoutX_Y_ODL, CLKoutX_Y_IDL, DCLKX_Y_DDLY_PD, DCLKX_Y_DDLY[9:8],

DCLKX_Y_DIV[9:8]

表8-21. Registers 0x102, 0x10A, 0x112, 0x11A, 0x122, 0x12A, 0x132

BIT

NAME

POR DEFAULT

DESCRIPTION

Power down the clock group defined by X and Y.

0: Enabled

7

CLKoutX_Y_PD

1

1: Power down entire clock group including both CLKoutX and CLKoutY.

Sets output drive level for clocks. This has no impact for the even clock output

in bypass mode.

0: Normal operation

6

CLKoutX_Y_ODL

0

1: Higher current consumption and lower noise floor.

Sets input drive level for clocks.

0: Normal operation

1: Higher current consumption and lower noise floor.

5

4

CLKoutX_Y_IDL

0

Powerdown the device clock digital delay circuitry.

0: Enabled

DCLKX_Y_DDLY_PD

1: Power down static digital delay for device clock divider.

3:2

1:0

DCLKX_Y_DDLY[9:8]

DCLKX_Y_DIV[9:8]

0

MSB of static digital delay, see 节8.6.2.2.2.

MSB of device clock divide value, see 表8-16.

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8.6.2.2.4 CLKoutX_SRC_MUX, CLKoutX_Y_PD, DCLKX_Y_BYP, DCLKX_Y_DCC, DCLKX_Y_POL, DCLKX_Y_HS

These registers control the analog delay properties for the device clocks.

表8-22. Registers 0x103, 0x10B, 0x113, 0x11B, 0x123, 0x12B, 0x133

BIT

7

NAME

NA

POR DEFAULT

DESCRIPTION

0

1

Reserved

6

NA

Select CLKoutX clock source. Source must also be powered up.

5

4

CLKoutX_SRC_MUX

CLKoutX_Y_PD

0

0: Device Clock

1: SYSREF

Power down the clock group defined by X and Y.

0: Enabled

1: Power down enter clock group X_Y.

Enable high performance bypass path for even clock outputs.

0: CLKoutX not in high performance bypass mode. CML is not valid for

CLKoutX_FMT.

3

2

DCLKX_BYP

0

1: CLKoutX in high performance bypass mode. Only CML clock format is valid.

Duty cycle correction for device clock divider. Required for half step.

0: No duty cycle correction.

DCLKX_Y_DCC

1: Duty cycle correction enabled.

Invert polarity of device clock output. This also applies to CLKoutX in high

performance bypass mode. Polarity invert is a method to get a half-step phase

adjustment in high performance bypass mode or /1 divide value.

0: Normal polarity

1

0

DCLKX_Y_POL

DCLKX_Y_HS

0

1: Invert polarity

Sets the device clock half step value. Must be set to zero (0) for a divide of 1.

No effect if DCLKX_Y_DCC = 0.

0: No phase adjustment

1: Adjust device clock phase –0.5 clock distribution path cycles.

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8.6.2.2.5 CLKoutY_SRC_MUX, SCLKX_Y_PD, SCLKX_Y_DIS_MODE, SCLKX_Y_POL, SCLKX_Y_HS

These registers set the half step for the device clock, the SYSREF output MUX, the SYSREF clock digital delay,

and half step.

表8-23. Registers 0x104, 0x10C, 0x114, 0x11C, 0x124, 0x12C, 0x134

BIT

NAME

POR DEFAULT

DESCRIPTION

7:6

NA

0

Reserved

Select CLKoutX clock source. Source must also be powered up.

5

4

CLKoutY_SRC_MUX

SCLKX_Y_PD

0

1

0: Device Clock

1: SYSREF

Power down the SYSREF clock output circuitry.

0: SYSREF enabled

1: Power down SYSREF path for clock pair.

Set disable mode for clock outputs controlled by SYSREF. Some cases will

assert when SYSREF_GBL_PD = 1.

Field Value

0 (0x00)

Disable Mode

Active in normal operation

1 (0x01)

If SYSREF_GBL_PD = 1, the output is

a logic low, otherwise it is active.

3:2

SCLKX_Y_DIS_MODE

0

2 (0x02)

If SYSREF_GBL_PD = 1, the output is

a nominal Vcm voltage for odd clock

channels⁽¹⁾and low for even clocks.

Otherwise outputs are active.

3 (0x03)

Output is a nominal Vcm voltage⁽¹⁾

Sets the polarity of clock on SCLKX_Y when SYSREF clock output is selected

with CLKoutX_MUX or CLKoutY_MUX.

0: Normal

1: Inverted

1

0

SCLKX_Y_POL

SCLKX_Y_HS

0

Sets the local SYSREF clock half step value.

0: No phase adjustment

1: Adjust device SYSREF phase -0.5 clock distribution path cycles.

(1) If LVPECL mode is used with emitter resistors to ground, the output Vcm will be approximately 0 V, each pin will be approximately 0 V.

If CML mode is used with pullups to V_CC, the output V_CMwill be approximately V_CCV, each pin will be approximately V_CCV.

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8.6.2.2.6 SCLKX_Y_ADLY_EN, SCLKX_Y_ADLY

These registers set the analog delay parameters for the SYSREF outputs.

表8-24. Registers 0x105, 0x10D, 0x115, 0x11D, 0x125, 0x12D, 0x135

BIT

NAME

POR DEFAULT

DESCRIPTION

7:6

NA

0

Reserved

Enables analog delay for the SYSREF output.

0: Disabled

1: Enabled

SCLKX_Y

_ADLY_EN

5

0

SYSREF analog delay in approximately 21 ps steps. Selecting analog delay

adds an additional 125 ps in propagation delay. Range is 125 ps to 608 ps.

Field Value

0 (0x0)

1 (0x1)

2 (0x2)

3 (0x3)

...

Delay Value

125 ps

146 ps (+21 ps from 0x00)

167 ps (+42 ps from 0x00)

188 ps (+63 ps from 0x00)

...

SCLKX_Y

_ADLY

4:0

0

14 (0xE)

15 (0xF)

587 ps (+462 ps from 0x00)

608 ps (+483 ps from 0x00)

8.6.2.2.7 SCLKX_Y_DDLY

表8-25. Registers 0x106, 0x10E, 0x116, 0x11E, 0x126, 0x12E, 0x136

BIT

7:4

3:0

NAME

POR DEFAULT

DESCRIPTION

NA

0

Reserved

Set digital delay value for SYSREF clock (minimum 8)

SCLKX_Y_DDLY

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8.6.2.2.8 CLKoutY_FMT, CLKoutX_FMT

The difference in the tables is that some of the clock outputs have inverted CMOS polarity settings.

表8-26. Registers 0x107 (CLKout0_1), 0x11F (CLKout6_7), 0x12F (CLKout10_11)

BIT

NAME

POR DEFAULT

DESCRIPTION

Set CLKoutY clock format

Field Value

0 (0x00)

Output Format

Powerdown

1 (0x01)

LVDS

2 (0x02)

HSDS 6 mA

3 (0x03)

HSDS 8 mA

4 (0x04)

LVPECL 1600 mV

LVPECL 2000 mV

LCPECL

5 (0x05)

6 (0x06)

7:4

CLKoutY_FMT

0

7 (0x07)

CML 16 mA

8 (0x08)

CML 24 mA

9 (0x09)

CML 32 mA

10 (0x0A)

CMOS (Off/Inv)

CMOS (Norm/Off)

CMOS (Inv/Inv)

CMOS (Inv/Norm)

CMOS (Norm/Inv)

11 (0x0B)

12 (0x0C)

13 (0x0D)

14 (0x0E)

15 (0x0F)

CMOS (Norm/Norm)

Set CLKoutX clock format

Output Format

DCLKX_BYP = 0

Output Format

DCLKX_BYP = 1

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

4 (0x04)

5 (0x05)

6 (0x06)

7 (0x07)

8 (0x08)

9 (0x09)

10 (0x0A)

11 (0x0B)

12 (0x0C)

13 (0x0D)

14 (0x0E)

15 (0x0F)

Powerdown

Reserved

CML 16 mA

CML 24 mA

CML 32 mA

Reserved

LVDS

HSDS 6 mA

HSDS 8 mA

LVPECL 1600 mV

LVPECL 2000 mV

LCPECL

3:0

CLKoutX_FMT

0

Reserved

CMOS (Off/Inv)⁽¹⁾

CMOS (Norm/Off)⁽¹⁾

CMOS (Inv/Inv)⁽¹⁾

CMOS (Inv/Norm)⁽¹⁾

CMOS (Norm/Inv)⁽¹⁾

CMOS (Norm/Norm)⁽¹⁾

(1) Only valid for CLKout10.

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表8-27. Registers 0x10F (CLKout2_3), 0x117 (CLKout4_5), 0x127 (CLKout8_9), 0x137 (CLKout12_13)

BIT

NAME

POR DEFAULT

DESCRIPTION

Set CLKoutY clock format

Field Value

0 (0x00)

Output Format

Powerdown

1 (0x01)

LVDS

2 (0x02)

HSDS 6 mA

HSDS 8 mA

LVPECL 1600 mV

LVPECL 2000 mV

LCPECL

3 (0x03)

4 (0x04)

5 (0x05)

6 (0x06)

7:4

CLKoutY_FMT

0

7 (0x07)

CML 16 mA

8 (0x08)

CML 24 mA

9 (0x09)

CML 32 mA

10 (0x0A)

CMOS (Off/Norm)

CMOS (Inv/Off)

11 (0x0B)

12 (0x0C)

13 (0x0D)

14 (0x0E)

CMOS (Norm/Norm)

CMOS (Norm/Inv)

CMOS (Inv/Norm)

CMOS (Inv/Inv)

15 (0x0F)

Set CLKoutX clock format

Output Format

DCLKX_BYP = 0

Output Format

DCLKX_BYP = 1

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

4 (0x04)

5 (0x05)

6 (0x06)

7 (0x07)

8 (0x08)

9 (0x09)

10 (0x0A)

11 (0x0B)

12 (0x0C)

13 (0x0D)

14 (0x0E)

15 (0x0F)

Powerdown

Reserved

CML 16 mA

CML 24 mA

CML 32 mA

Reserved

LVDS

HSDS 6 mA

HSDS 8 mA

LVPECL 1600 mV

LVPECL 2000 mV

LCPECL

3:0

CLKoutX_FMT

0

Reserved

CMOS (Off/Norm)⁽¹⁾

CMOS (Inv/Off)⁽¹⁾

CMOS (Norm/Norm)⁽¹⁾

CMOS (Norm/Inv)⁽¹⁾

CMOS (Inv/Norm)⁽¹⁾

CMOS (Inv/Inv)⁽¹⁾

(1) Only valid for CLKout8.

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8.6.2.3 SYSREF, SYNC, and Device Config

8.6.2.3.1 VCO_MUX, OSCout_MUX, OSCout_FMT

表8-28. Register 0x138

BIT

NAME

POR DEFAULT

DESCRIPTION

7

NA

0

Reserved

Selects clock distribution path source from VCO0, VCO1, or CLKin (external

VCO)

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

VCO Selected

VCO 0

6:5

VCO_MUX

2

0

VCO 1

Fin1 / CLKin1 (external VCO)

Fin0

Select the source for OSCout:

0: Buffered OSCin

4

OSCout_MUX

1: Feedback Mux

Selects the output format of OSCout. When powered down, these pins may be

used as CLKin2.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

4 (0x04)

5 (0x05)

6 (0x06)

7 (0x07)

8 (0x08)

9 (0x09)

10 (0x0A)

11 (0x0B)

12 (0x0C)

13 (0x0D)

14 (0x0E)

OSCout Format

Power down (CLKin2)

LVDS

Reserved

LVPECL 1600 mVpp

LVPECL 2000 mVpp

LVCMOS (Norm / Inv)

LVCMOS (Inv / Norm)

LVCMOS (Norm / Norm)

LVCMOS (Inv / Inv)

LVCMOS (Off / Norm)

LVCMOS (Off / Inv)

LVCMOS (Norm / Off)

LVCMOS (Inv / Off)

LVCMOS (Off / Off)

3:0

OSCout_FMT

4

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8.6.2.3.2 SYSREF_REQ_EN, SYNC_BYPASS, SYSREF_MUX

This register sets the source for the SYSREF outputs. Refer to 图8-3 and 节8.3.2.

表8-29. Register 0x139

BIT

7:6

5

NAME

POR DEFAULT

DESCRIPTION

NA

0

Reserved

NA

Enables the SYNC/SYSREF_REQ pin to force the SYSREF_MUX = 3 for

continuous pulses. When using this feature enable pulser and set

SYSREF_MUX = 2 (Pulser).

4

SYSREF_REQ_EN

0

Bypass SYNC polarity invert and other circuitry.

0: Normal

1: SYNC signal is bypassed

3

2

SYNC_BYPASS

NA

0

Reserved

Selects the SYSREF source.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

SYSREF Source

Normal SYNC

1:0

SYSREF_MUX

0

Re-clocked

SYSREF Pulser

SYSREF Continuous

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8.6.2.3.3 SYSREF_DIV

These registers set the value of the SYSREF output divider.

表8-30. SYSREF_DIV[12:0]

MSB

LSB

0x13A[4:0] = SYSREF_DIV[12:8]

0x13B[7:0] = SYSREF_DIV[7:0]

表8-31. Registers 0x13A and 0x13B

REGISTER

BIT

NAME

POR DEFAULT

DESCRIPTION

0x13A

7:5

NA

0

Reserved

Divide value for the SYSREF outputs.

Field Value

0 to 7 (0x00 to 0x07)

8 (0x08)

Divide Value

0x13A

0x13B

4:0

7:0

SYSREF_DIV[12:8]

SYSREF_DIV[7:0]

12

0

Reserved

8

9

9 (0x09)

...

8190 (0x1FFE)

8191 (0X1FFF)

8190

8191

8.6.2.3.4 SYSREF_DDLY

These registers set the delay of the SYSREF digital delay value.

表8-32. SYSREF Digital Delay Register Configuration, SYSREF_DDLY[12:0]

MSB

LSB

0x13C[4:0] / SYSREF_DDLY[12:8]

0x13D[7:0] / SYSREF_DDLY[7:0]

表8-33. Registers 0X13C and 0X13D

REGISTER

BIT

NAME

POR DEFAULT

DESCRIPTION

0x13C

7:5

NA

0

Reserved

Sets the value of the SYSREF digital delay.

Field Value

0x00 to 0x07

8 (0x08)

Delay Value

0x13C

0x13D

4:0

7:0

SYSREF_DDLY[12:8]

SYSREF_DDLY[7:0]

0

8

Reserved

8

9

9 (0x09)

...

8190 (0x1FFE)

8191 (0X1FFF)

8190

8191

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8.6.2.3.5 SYSREF_PULSE_CNT

This register sets the number of SYSREF pulses if SYSREF is not in continuous mode. See 节 8.6.2.3.2 for

further description of SYSREF's outputs.

Programming the register causes the specified number of pulses to be output if "SYSREF Pulses" is selected by

SYSREF_MUX and SYSREF functionality is powered up.

表8-34. Register 0x13E

BIT

NAME

POR DEFAULT

DESCRIPTION

7:2

NA

0

Reserved

Sets the number of SYSREF pulses generated when not in continuous mode.

See 节8.6.2.3.2 for more information on SYSREF modes.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

Number of Pulses

1 pulse

1:0

SYSREF_PULSE_CNT

3

2 pulses

4 pulses

8 pulses

8.6.2.3.6 PLL2_RCLK_MUX, PLL2_NCLK_MUX, PLL1_NCLK_MUX, FB_MUX, FB_MUX_EN

This register controls the feedback feature.

表8-35. Register 0x13F

BIT

7

NAME

PLL2_RCLK_MUX

NA

POR DEFAULT

DESCRIPTION

Selects the source for PLL2 reference.

0

0: OSCin

1: Currently selected CLKin.

6

Reserved

Selects the input to the PLL2 N Divider

0: PLL2 Prescaler

5

PLL2_NCLK_MUX

1: Feedback Mux

Selects the input to the PLL1 N Divider.

0: OSCin

1: Feedback Mux

4:3

2:1

0

PLL1_NCLK_MUX

0

2: PLL2 Prescaler

When in 0-delay mode, the feedback mux selects the clock output to be fed

back into the PLL1 N Divider.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

Source

CLKout6

FB_MUX

CLKout8

SYSREF Divider

External

When using 0-delay, FB_MUX_EN must be set to 1 power up the feedback

mux.

0: Feedback mux powered down

1: Feedback mux enabled

FB_MUX_EN

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8.6.2.3.7 PLL1_PD, VCO_LDO_PD, VCO_PD, OSCin_PD, SYSREF_GBL_PD, SYSREF_PD, SYSREF_DDLY_PD,

SYSREF_PLSR_PD

This register contains power down controls for OSCin and SYSREF functions.

表8-36. Register 0x140

BIT

NAME

POR DEFAULT

DESCRIPTION

Power down PLL1

0: Normal operation

1: Power down

7

PLL1_PD

1

Power down VCO_LDO

0: Normal operation

1: Power down

6

5

4

VCO_LDO_PD

VCO_PD

1

0

Power down VCO

0: Normal operation

1: Power down

Power down the OSCin port.

0: Normal operation

1: Power down

OSCin_PD

Power down individual SYSREF outputs depending on the setting of

SCLKX_Y_DIS_MODE for each SYSREF output. SYSREF_GBL_PD allows

many SYSREF outputs to be controlled through a single bit.

0: Normal operation

3

2

SYSREF_GBL_PD

SYSREF_PD

0

1: Activate Power down Mode

Power down the SYSREF circuitry and divider. If powered down, SYSREF

output mode cannot be used. SYNC cannot be provided either.

0: SYSREF can be used as programmed by individual SYSREF output

registers.

1: Power down

Power down the SYSREF digital delay circuitry.

0: Normal operation, SYSREF digital delay may be used. Must be powered up

during SYNC for deterministic phase relationship with other clocks.

1: Power down

1

0

SYSREF_DDLY_PD

SYSREF_PLSR_PD

0

Powerdown the SYSREF pulse generator.

0: Normal operation

1: Powerdown

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8.6.2.3.8 DDLYdSYSREF_EN, DDLYdX_EN

This register enables dynamic digital delay for enabled device clocks and SYSREF when DDLYd_STEP_CNT is

programmed.

表8-37. Register 0x141

BIT

NAME

POR DEFAULT

DESCRIPTION

Enables dynamic digital delay on

SYSREF outputs

7

DDLYd _SYSREF_EN

0

Enables dynamic digital delay on

DCLKout12

6

5

4

3

2

1

0

DDLYd12_EN

DDLYd10_EN

DDLYd8_EN

DDLYd6_EN

DDLYd4_EN

DDLYd2_EN

DDLYd0_EN

0

Enables dynamic digital delay on

DCLKout10

Enables dynamic digital delay on

DCLKout8

0: Disabled

1: Enabled

Enables dynamic digital delay on

DCLKout6

Enables dynamic digital delay on

DCLKout4

Enables dynamic digital delay on

DCLKout2

Enables dynamic digital delay on

DCLKout0

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8.6.2.3.9 DDLYd_STEP_CNT

This register sets the number of dynamic digital delay adjustments occur. Upon programming, the dynamic

digital delay adjustment begins for each clock output with dynamic digital delay enabled. Dynamic digital delay

can only be started by SPI.

Other registers must be set: SYNC_MODE = 3

表8-38. Register 0x142

BIT

NAME

POR DEFAULT

DESCRIPTION

Sets the number of dynamic digital delay adjustments that will occur.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

...

Dynamic Digital Delay Adjustments

No Adjust

1 step

7:0

DDLYd_STEP_CNT

0

2 steps

3 steps

...

254 (0xFE)

255 (0xFF)

254 steps

255 steps

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8.6.2.3.10 SYSREF_CLR, SYNC_1SHOT_EN, SYNC_POL, SYNC_EN, SYNC_PLL2_DLD, SYNC_PLL1_DLD,

SYNC_MODE

This register sets general SYNC parameters such as polarization, and mode. Refer to 图 8-3 for block diagram.

Refer to 表8-2 for using SYNC_MODE for specific SYNC use cases.

表8-39. Register 0x143

BIT

NAME

POR DEFAULT

DESCRIPTION

Except during SYSREF Setup Procedure (see 节8.3.2), this bit should always

be programmed to 0. While this bit is set, extra current is used.

7

SYSREF_CLR

0

SYNC one shot enables edge sensitive SYNC.

0: SYNC is level sensitive and outputs will be held in SYNC as long as SYNC

is asserted.

6

SYNC_1SHOT_EN

0

1: SYNC is edge sensitive, outputs will be SYNCed on rising edge of SYNC.

This results in the clock being held in SYNC for a minimum amount of time.

Sets the polarity of the SYNC pin.

0: Normal

1: Inverted

5

4

SYNC_POL

SYNC_EN

0

Enables the SYNC functionality.

0: Disabled

1: Enabled

0: Off

3

2

SYNC_PLL2_DLD

SYNC_PLL1_DLD

0

1: Assert SYNC until PLL2 DLD = 1

0: Off

1: Assert SYNC until PLL1 DLD = 1

Sets the method of generating a SYNC event.

Field Value

SYNC Generation

Prevent SYNC Pin, SYNC_PLL1_DLD

flag, or SYNC_PLL2_DLD flag from

generating a SYNC event.

0 (0x00)

SYNC event generated from SYNC

pin or if enabled the

SYNC_PLL1_DLD flag or

SYNC_PLL2_DLD flag.

1 (0x01)

2 (0x02)

1:0

SYNC_MODE

1

For use with pulser - SYNC/SYSREF

pulses are generated by pulser block

via SYNC Pin or if enabled

SYNC_PLL1_DLD flag or

SYNC_PLL2_DLD flag.

For use with pulser - SYNC/SYSREF

pulses are generated by pulser block

when programming register 0x13E

(SYSREF_PULSE_CNT) is written to

(see 节8.6.2.3.5).

3 (0x03)

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8.6.2.3.11 SYNC_DISSYSREF, SYNC_DISX

SYNC_DISX will prevent a clock output from being synchronized or interrupted by a SYNC event or when

outputting SYSREF.

表8-40. Register 0x144

BIT

NAME

POR DEFAULT

DESCRIPTION

Prevent the SYSREF clocks from becoming synchronized during a SYNC

event. If SYNC_DISSYSREF is enabled it will continue to operate normally

during a SYNC event.

7

SYNC_DISSYSREF

0

6

5

4

3

2

1

0

SYNC_DIS12

SYNC_DIS10

SYNC_DIS8

SYNC_DIS6

SYNC_DIS4

SYNC_DIS2

SYNC_DIS0

0

Prevent the device clock output from becoming synchronized during a SYNC

event or SYSREF clock. If SYNC_DIS bit for a particular output is enabled then

it will continue to operate normally during a SYNC event or SYSREF clock.

8.6.2.3.12 PLL1R_SYNC_EN, PLL1R_SYNC_SRC, PLL2R_SYNC_EN, FIN0_DIV2_EN, FIN0_INPUT_TYPE

These bits are used when synchronizing PLL1 and PLL2 R dividers. Refer to (TBD) for more information on the

process to synchronize the PLL R dividers.

表8-41. Register 0x145

BIT

NAME

POR DEFAULT

DESCRIPTION

7

NA

0

Reserved

Enable synchronization for PLL1 R divider

0: Not enabled

6

PLL1R_SYNC_EN

0

1: Enabled

Select the source for PLL1 R divider synchronization

Field Value

Definition

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

Reserved

SYNC Pin

CLKin0

5:4

PLL1R_SYNC_SRC

0

Reserved

Enable synchronization for PLL2 R divider. Synchronization for PLL2 R always

comes from the SYNC pin.

0: Not enabled

1: Enabled

3

2

PLL2R_SYNC_EN

FIN0_DIV2_EN

0

Sets the input path to use or bypass the divide-by-2.

0: Bypassed (÷1)

1: Divided (÷2)

Program input type to hardware interface used.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

Definition

Differential Input

1:0

FIN0_INPUT_TYPE

0

Single Ended Input (Fin0)

Single Ended Input (Fin0*)

Reserved

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8.6.2.4 (0x146 - 0x149) CLKin Control

8.6.2.4.1 CLKin_SEL_PIN_EN, CLKin_SEL_PIN_POL, CLKin2_EN, CLKin1_EN, CLKin0_EN, CLKin2_TYPE,

CLKin1_TYPE, CLKin0_TYPE

This register has CLKin enable and type controls. See 节8.3.6 for more info on how clock input selection works.

表8-42. Register 0x146

BIT

NAME

POR DEFAULT

DESCRIPTION

7

CLKin_SEL_PIN_EN

0

Enables pin control according to 图8-7.

Inverts the CLKin polarity for use in pin select mode.

6

5

4

3

CLKin_SEL_PIN_POL

CLKin2_EN

0

1

0: Active High

1: Active Low

Enable CLKin2 to be used during auto-switching.

0: Not enabled for auto mode

1: Enabled for auto clock switching mode

Enable CLKin1 to be used during auto-switching.

0: Not enabled for auto mode

1: Enabled for auto clock switching mode

CLKin1_EN

Enable CLKin0 to be used during auto-switching.

0: Not enabled for auto mode

CLKin0_EN

1: Enabled for auto clock switching mode

2

1

CLKin2_TYPE

CLKin1_TYPE

0

There are two buffer types for CLKin0,

1, and 2: bipolar and CMOS. Bipolar is

recommended for differential inputs

like LVDS or LVPECL. CMOS is

recommended for DC-coupled single

ended inputs.

When using bipolar, CLKinX and

CLKinX* must be AC-coupled.

When using CMOS, CLKinX and

CLKinX* may be AC or DC-coupled if

the input signal is differential. If the

input signal is single-ended the used

input may be either AC or DC-coupled

and the unused input must AC

grounded.

0: Bipolar

1: MOS

0

CLKin0_TYPE

0

8.6.2.4.2 CLKin_SEL_AUTO_REVERT_EN, CLKin_SEL_AUTO_EN, CLKin_SEL_MANUAL, CLKin1_DEMUX,

CLKin0_DEMUX

表8-43. Register 0x147

BIT

7

NAME

POR DEFAULT

DESCRIPTION

When in auto clock switching mode. If active clock is detected on higher

priority clock, the clock input is immediately switched. Highest priority input is

lowest numbered active clock input.

CLKin_SEL_

AUTO_REVERT_EN

0

6

CLKin_SEL_AUTO_EN

CLKin_SEL_MANUAL

Enables pin control according to 图8-7.

Selects the clock input when in manual mode according to 图8-7.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

Definition

CLKin0

5:4

1

CLKin1

CLKin2

Holdover

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BIT

表8-43. Register 0x147 (continued)

NAME

POR DEFAULT

DESCRIPTION

Selects where the output of the CLKin1 buffer is directed.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

CLKin1 Destination

Fin

3:2

CLKin1_DEMUX

0

Feedback Mux (0-delay mode)

PLL1

Off

Selects where the output of the CLKin0 buffer is directed.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

CLKin0 Destination

SYSREF Mux

Reserved

PLL1

1:0

CLKin0_DEMUX

3

Off

8.6.2.4.3 CLKin_SEL0_MUX, CLKin_SEL0_TYPE

This register has CLKin_SEL0 controls.

表8-44. Register 0x148

BIT

NAME

POR DEFAULT

DESCRIPTION

7:6

NA

0

Reserved

This set the output value of the CLKin_SEL0 pin. This register only applies if

CLKin_SEL0_TYPE is set to an output mode

Field Value

Output Format

Logic Low

0 (0x00)

1 (0x01)

CLKin0 LOS

CLKin0 Selected

DAC Locked

DAC Low

2 (0x02)

5:3

CLKin_SEL0_MUX

0

3 (0x03)

4 (0x04)

5 (0x05)

DAC High

6 (0x06)

SPI Readback

Reserved

7 (0x07)

This sets the IO type of the CLKin_SEL0 pin.

Field Value

0 (0x00)

Configuration

Function

Input

Input mode, see 节

8.3.6.2 for description of

input mode.

1 (0x01)

Input with pullup resistor

Input with pulldown

resistor

2 (0x02)

3 (0x03)

4 (0x04)

2:0

CLKin_SEL0_TYPE

2

Output (push-pull)

Output modes; the

CLKin_SEL0_MUX

register for description of

outputs.

Output inverted (push-

pull)

5 (0x05)

6 (0x06)

Reserved

Output (open-drain)

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8.6.2.4.4 SDIO_RDBK_TYPE, CLKin_SEL1_MUX, CLKin_SEL1_TYPE

This register has CLKin_SEL1 controls and register readback SDIO pin type.

表8-45. Register 0x149

BIT

NAME

POR DEFAULT

DESCRIPTION

7

NA

0

Reserved

Sets the SDIO pin to open drain when during SPI readback in 3 wire mode.

6

SDIO_RDBK_TYPE

1

0: Output, push-pull

1: Output, open drain.

This set the output value of the CLKin_SEL1 pin. This register only applies if

CLKin_SEL1_TYPE is set to an output mode.

Field Value

Output Format

Logic Low

0 (0x00)

1 (0x01)

CLKin1 LOS

CLKin1 Selected

DAC Locked

DAC Low

2 (0x02)

5:3

CLKin_SEL1_MUX

0

3 (0x03)

4 (0x04)

5 (0x05)

DAC High

6 (0x06)

SPI Readback

Reserved

7 (0x07)

This sets the IO type of the CLKin_SEL1 pin.

Field Value

0 (0x00)

Configuration

Function

Input

Input mode, see 节

8.3.6.2 for description of

input mode.

1 (0x01)

Input with pullup resistor

Input with pulldown

resistor

2 (0x02)

3 (0x03)

4 (0x04)

2:0

CLKin_SEL1_TYPE

2

Output (push-pull)

Output modes; see the

CLKin_SEL1_MUX

register for description of

outputs.

Output inverted (push-

pull)

5 (0x05)

6 (0x06)

Reserved

Output (open-drain)

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8.6.2.5 RESET_MUX, RESET_TYPE

This register contains control of the RESET pin.

表8-46. Register 0x14A

BIT

NAME

POR DEFAULT

DESCRIPTION

7:6

NA

0

Reserved

This sets the output value of the RESET pin. This register only applies if

RESET_TYPE is set to an output mode.

Field Value

Output Format

Logic Low

0 (0x00)

1 (0x01)

Reserved

5:3

RESET_MUX

0

2 (0x02)

CLKin2 Selected

DAC Locked

DAC Low

3 (0x03)

4 (0x04)

5 (0x05)

DAC High

6 (0x06)

SPI Readback

This sets the IO type of the RESET pin.

Field Value

0 (0x00)

Configuration

Function

Input

1 (0x01)

Input with pullup resistor

Reset Mode

Reset pin high = Reset

Input with pulldown

resistor

2 (0x02)

3 (0x03)

4 (0x04)

2:0

RESET_TYPE

2

Output (push-pull)

Output inverted (push-

pull)

Output modes; see the

RESET_MUX register for

description of outputs.

5 (0x05)

6 (0x06)

Reserved

Output (open-drain)

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8.6.2.6 (0x14B - 0x152) Holdover

8.6.2.6.1 LOS_TIMEOUT, LOS_EN, TRACK_EN, HOLDOVER_FORCE, MAN_DAC_EN, MAN_DAC[9:8]

This register contains the holdover functions.

表8-47. Register 0x14B

BIT

NAME

POR DEFAULT

DESCRIPTION

This controls the amount of time in which no activity on a CLKin forces a clock

switch event.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

Timeout

5 MHz typical

25 MHz typical

100 MHz typical

200 MHz typical

7:6

LOS_TIMEOUT

0

Enables the LOS (Loss-of-Signal) timeout control. Valid for MOS clock inputs.

5

4

LOS_EN

0

0: Disabled

1: Enabled

Enable the DAC to track the PLL1 tuning voltage, optionally for use in holdover

mode. After device reset, tracking starts at DAC code = 512.

Tracking can be used to monitor PLL1 voltage in any mode.

0: Disabled

TRACK_EN

1: Enabled, will only track when PLL1 is locked.

This bit forces holdover mode. When holdover mode is forced, if

MAN_DAC_EN = 1, then the DAC will set the programmed MAN_DAC value.

Otherwise the tracked DAC value will set the DAC voltage.

0: Disabled

HOLDOVER

_FORCE

3

0

1: Enabled.

This bit enables the manual DAC mode.

2

MAN_DAC_EN

MAN_DAC[9:8]

1

2

0: Automatic

1: Manual

1:0

See 节8.6.2.6.2 for more information on the MAN_DAC settings.

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8.6.2.6.2 MAN_DAC

These registers set the value of the DAC in holdover mode when used manually.

表8-48. MAN_DAC[9:0]

MSB

LSB

0x14B[1:0]

0x14C[7:0]

REGISTER

BIT

NAME

POR DEFAULT

DESCRIPTION

0x14B

7:2

See 节8.6.2.6.1 for information on these bits.

Sets the value of the manual DAC when in manual DAC

mode.

Field Value

0 (0x00)

DAC Value

0x14B

0x14C

1:0

7:0

MAN_DAC[9:8]

2

0

1

1 (0x01)

2 (0x02)

2

...

MAN_DAC[7:0]

0

1022 (0x3FE)

1023 (0x3FF)

1022

1023

8.6.2.6.3 DAC_TRIP_LOW

This register contains the high value at which holdover mode is entered.

表8-49. Register 0x14D

BIT

NAME

POR DEFAULT

DESCRIPTION

7:6

NA

0

Reserved

Voltage from GND at which holdover is entered if HOLDOVER_VTUNE_DET

is enabled.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

...

DAC Trip Value

1 x Vcc / 64

2 x Vcc / 64

3 x Vcc / 64

4 x Vcc / 64

...

5:0

DAC_TRIP_LOW

0

61 (0x17)

62 (0x18)

63 (0x19)

62 x Vcc / 64

63 x Vcc / 64

64 x Vcc / 64

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8.6.2.6.4 DAC_CLK_MULT, DAC_TRIP_HIGH

This register contains the multiplier for the DAC clock counter and the low value at which holdover mode is

entered.

表8-50. Register 0x14E

BIT

NAME

POR DEFAULT

DESCRIPTION

This is the multiplier for the DAC_CLK_CNTR which sets the rate at which the

DAC value is tracked.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

DAC Multiplier Value

4

7:6

DAC_CLK_MULT

0

64

1024

16384

Voltage from Vcc at which holdover is entered if HOLDOVER_VTUNE_DET is

enabled.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

...

DAC Trip Value

1 x Vcc / 64

2 x Vcc / 64

3 x Vcc / 64

4 x Vcc / 64

...

5:0

DAC_TRIP_HIGH

0

61 (0x17)

62 (0x18)

63 (0x19)

62 x Vcc / 64

63 x Vcc / 64

64 x Vcc / 64

8.6.2.6.5 DAC_CLK_CNTR

This register contains the value of the DAC when in tracked mode.

表8-51. Register 0x14F

BIT

NAME

POR DEFAULT

DESCRIPTION

This with DAC_CLK_MULT set the rate at which the DAC is updated. The

update rate is = DAC_CLK_MULT * DAC_CLK_CNTR / PLL1 PDF

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

...

DAC Value

0

1

2

7:0

DAC_CLK_CNTR

127

3

...

253 (0xFD)

254 (0xFE)

255 (0xFF)

253

254

255

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8.6.2.6.6 CLKin_OVERRIDE, HOLDOVER_EXIT_MODE, HOLDOVER_PLL1_DET, LOS_EXTERNAL_INPUT,

HOLDOVER_VTUNE_DET, CLKin_SWITCH_CP_TRI, HOLDOVER_EN

This register has controls for enabling clock in switch events.

表8-52. Register 0x150

BIT

NAME

POR DEFAULT

DESCRIPTION

7

NA

0

Reserved

When manual clock select is enabled, then CLKin_SEL_MANUAL = 0/1/2

selects a manual clock input. CLKin_OVERRIDE = 1 will force that clock input.

CLKin_OVERRIDE = 1 is used with clock distribution mode for best

performance.

CLKin

_OVERRIDE

6

0

0: Normal, no override.

1: Force select of only CLKin0/1/2 as specified by CLKin_SEL_MANUAL in

manual mode. Dynamic digital delay will not operate.

0: Exit based on LOS status. If clock is active by LOS, then begin exit.

1: Exit based on PLL1 DLD. When the PLL1 phase detector confirming valid

clock.

HOLDOVER_

EXIT_MODE

5

4

0

This enables the HOLDOVER when PLL1 lock detect signal transitions from

high to low.

0: PLL1 DLD does not cause a clock switch event

1: PLL1 DLD causes a clock switch event

HOLDOVER

_PLL1_DET

Use external signals for LOS status instead of internal LOS circuitry.

CLKin_SEL0 pin is used for CLKin0 LOS, CLKin_SEL1 pin is used for CLKin1

LOS, and Status_LD1 is used for CLKin2 LOS. For any of these pins to be

valid, the corresponding _TYPE register must be programmed as an input.

0: Disabled

3

2

LOS_EXTERNAL_INPUT

0

1: Enabled

Enables the DAC Vtune rail detector. When the DAC achieves a specified

Vtune, if this bit is enabled, the current clock input is considered invalid and an

input clock switch event is generated.

0: Disabled

HOLDOVER_

VTUNE_DET

1: Enabled

Enable clock switching with tri-stated charge pump.

0: Not enabled.

1: PLL1 charge pump tri-states during clock switching.

1

0

CLKin_SWITCH_CP_TRI

HOLDOVER_EN

0

Sets whether holdover mode is active or not.

0: Disabled

1: Enabled

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8.6.2.6.7 HOLDOVER_DLD_CNT

表8-53. HOLDOVER_DLD_CNT[13:0]

MSB

LSB

0x151[5:0] / HOLDOVER_DLD_CNT[13:8]

0x152[7:0] / HOLDOVER_DLD_CNT[7:0]

This register has the number of valid clocks of PLL1 PDF before holdover is exited.

表8-54. Registers 0x151 and 0x152

REGISTER

BIT

NAME

POR DEFAULT

DESCRIPTION

0x151

7:6

NA

0

Reserved

The number of valid clocks of PLL1 PDF before holdover

mode is exited.

HOLDOVER

_DLD_CNT[13:8]

Field Value

0 (0x00)

Count Value

0x151

0x152

5:0

7:0

2

0

1

1 (0x01)

2 (0x02)

2

...

HOLDOVER

_DLD_CNT[7:0]

16382 (0x3FFE)

16383 (0x3FFF)

16382

16383

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8.6.2.7 (0x153 - 0x15F) PLL1 Configuration

8.6.2.7.1 CLKin0_R

表8-55. CLKin0_R[13:0]

MSB

LSB

0x153[5:0] / CLKin0_R[13:8]

0x154[7:0] / CLKin0_R[7:0]

These registers contain the value of the CLKin0 divider.

表8-56. Registers 0x153 and 0x154

REGISTER

BIT

NAME

POR DEFAULT

DESCRIPTION

0x153

7:6

NA

0

Reserved

The value of PLL1 N counter when CLKin0 is selected.

Field Value

0 (0x00)

Divide Value

0x153

0x154

5:0

7:0

CLKin0_R[13:8]

CLKin0_R[7:0]

0

Reserved

1 (0x01)

1

2

2 (0x02)

...

120

16382 (0x3FFE)

16383 (0x3FFF)

16382

16383

8.6.2.7.2 CLKin1_R

MSB

表8-57. CLKin1_R[13:0]

LSB

0x155[5:0] / CLKin1_R[13:8]

0x156[7:0] / CLKin1_R[7:0]

These registers contain the value of the CLKin1 R divider.

表8-58. Registers 0x155 and 0x156

REGISTER

BIT

NAME

POR DEFAULT

DESCRIPTION

0x155

7:6

NA

0

Reserved

The value of PLL1 N counter when CLKin1 is selected.

Field Value

0 (0x00)

Divide Value

0x155

0x156

5:0

7:0

CLKin1_R[13:8]

CLKin1_R[7:0]

0

Reserved

1 (0x01)

1

2

2 (0x02)

...

150

16382 (0x3FFE)

16383 (0x3FFF)

16382

16383

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8.6.2.7.3 CLKin2_R

表8-59. CLKin2_R[13:0]

MSB

LSB

0x157[5:0] / CLKin2_R[13:8]

0x158[7:0] / CLKin2_R[7:0]

表8-60. Registers 0x157 and 0x158

REGISTER

BIT

NAME

POR DEFAULT

DESCRIPTION

0x157

7:6

NA

0

Reserved

The value of PLL1 N counter when CLKin2 is selected.

Field Value

0 (0x00)

Divide Value

0x157

0x158

5:0

7:0

CLKin2_R[13:8]

CLKin2_R[7:0]

0

Reserved

1 (0x01)

1

2

2 (0x02)

...

150

16382 (0x3FFE)

16383 (0x3FFF)

16382

16383

8.6.2.7.4 PLL1_N

表8-61. PLL1_N[13:0]

MSB

LSB

0x159[5:0] / PLL1_N[13:8]

0x15A[7:0] / PLL1_N[7:0]

These registers contain the N divider value for PLL1.

表8-62. Registers 0x159 and 0x15A

REGISTER

BIT

NAME

POR DEFAULT

DESCRIPTION

0x159

7:6

NA

0

Reserved

The value of PLL1 N counter.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

...

Divide Value

0x159

0x15A

5:0

7:0

PLL1_N[13:8]

PLL1_N[7:0]

0

Not Valid

1

2

120

...

4,095 (0xFFF)

4,095

72

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8.6.2.7.5 PLL1_WND_SIZE, PLL1_CP_TRI, PLL1_CP_POL, PLL1_CP_GAIN

This register controls the PLL1 phase detector.

表8-63. Register 0x15B

BIT

NAME

POR DEFAULT

DESCRIPTION

PLL1_WND_SIZE sets the window size used for digital lock detect for PLL1. If

the phase error between the reference and feedback of PLL1 is less than

specified time, then the PLL1 lock counter increments.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

Definition

4 ns

7:6

PLL1_WND_SIZE

3

9 ns

19 ns

43 ns

This bit allows for the PLL1 charge pump output pin, CPout1, to be placed into

TRI-STATE.

0: PLL1 CPout1 is active

1: PLL1 CPout1 is at TRI-STATE

5

4

PLL1_CP_TRI

PLL1_CP_POL

0

1

PLL1_CP_POL sets the charge pump polarity for PLL1. Many VCXOs use

positive slope.

A positive slope VCXO increases output frequency with increasing voltage. A

negative slope VCXO decreases output frequency with increasing voltage.

0: Negative Slope VCO/VCXO

1: Positive Slope VCO/VCXO

This bit programs the PLL1 charge pump output current level.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

4 (0x04)

...

Gain

50 µA

150 µA

250 µA

350 µA

450 µA

...

3:0

PLL1_CP_GAIN

4

14 (0x0E)

15 (0x0F)

1450 µA

1550 µA

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8.6.2.7.6 PLL1_DLD_CNT

表8-64. PLL1_DLD_CNT[13:0]

MSB

LSB

0x15C[5:0] / PLL1_DLD_CNT[13:8]

0x15D[7:0] / PLL1_DLD_CNT[7:0]

This register contains the value of the PLL1 DLD counter.

表8-65. Registers 0x15C and 0x15D

REGISTER

BIT

NAME

POR DEFAULT

DESCRIPTION

0x15C

7:6

NA

0

Reserved

The reference and feedback of PLL1 must be within the

window of phase error as specified by PLL1_WND_SIZE for

this many phase detector cycles before PLL1 digital lock

detect is asserted.

PLL1_DLD

_CNT[13:8]

0x15C

0x15D

5:0

7:0

32

Field Value

0 (0x00)

Delay Value

Reserved

1 (0x01)

1

2 (0x02)

2

3

3 (0x03)

PLL1_DLD

_CNT[7:0]

0

...

16,382 (0x3FFE)

16,383 (0x3FFF)

16,382

16,383

8.6.2.7.7 HOLDOVER_EXIT_NADJ

表8-66. Register 0x15E

BIT

NAME

POR DEFAULT

DESCRIPTION

7:5

NA

0

Reserved

When holdover exists, PLL1 R counter and PLL1 N

counter are reset. HOLDOVER_EXIT_NADJ is a 2s

complement number which provides a relative timing

offset between PLL1 R and PLL1 N divider.

4:0

HOLDOVER_EXIT_NADJ

30

74

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8.6.2.7.8 PLL1_LD_MUX, PLL1_LD_TYPE

This register configures the PLL1 LD pin.

表8-67. Register 0x15F

BIT

NAME

POR DEFAULT

DESCRIPTION

This sets the output value of the Status_LD1 pin.

Field Value

0 (0x00)

MUX Value

Logic Low

PLL1 DLD

PLL2 DLD

PLL1 & PLL2 DLD

Holdover Status

DAC Locked

Reserved

1 (0x01)

2 (0x02)

3 (0x03)

4 (0x04)

5 (0x05)

6 (0x06)

7 (0x07)

SPI Readback

DAC Rail

7:3

PLL1_LD_MUX

1

8 (0x08)

9 (0x09)

DAC Low

10 (0x0A)

DAC High

11 (0x0B)

PLL1_N

12 (0x0C)

PLL1_N/2

13 (0x0D)

PLL2_N

14 (0x0E)

PLL2_N/2

15 (0x0F)

PLL1_R

16 (0x10)

PLL1_R/2

17 (0x11)

PLL2_R⁽¹⁾

PLL2_R/2⁽¹⁾

18 (0x12)

Sets the IO type of the Status_LD1 pin.

Field Value

TYPE

0 (0x00)

1 (0x01)

Input for External CLKin2 LOS

Input for External CLKin2 LOS (pullup)

Input for External CLKin2 LOS

(pulldwn)

2:0

PLL1_LD_TYPE

6

2 (0x02)

3 (0x03)

4 (0x04)

5 (0x05)

6 (0x06)

Output (push-pull)

Output inverted (push-pull)

Reserved

Output (open-drain)

(1) Only valid when PLL2_LD_MUX is not set to 2 (PLL2_DLD) or 3 (PLL1 & PLL2 DLD).

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8.6.2.8 (0x160 - 0x16E) PLL2 Configuration

8.6.2.8.1 PLL2_R

表8-68. PLL2_R[11:0]

MSB

LSB

0x160[3:0] / PLL2_R[11:8]

0x161[7:0] / PLL2_R[7:0]

This register contains the value of the PLL2 R divider.

表8-69. Registers 0x160 and 0x161

REGISTER

BIT

NAME

POR DEFAULT

DESCRIPTION

0x160

7:4

NA

0

Reserved

Valid values for the PLL2 R divider.

Field Value

0 (0x00)

Divide Value

0x160

0x161

3:0

7:0

PLL2_R[11:8]

PLL2_R[7:0]

0

2

Not Valid

1 (0x01)

1

2

2 (0x02)

3 (0x03)

3

...

4,094 (0xFFE)

4,095 (0xFFF)

4,094

4,095

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8.6.2.8.2 PLL2_P, OSCin_FREQ, PLL2_REF_2X_EN

This register sets other PLL2 functions.

表8-70. Register 0x162

BIT

NAME

POR DEFAULT

DESCRIPTION

The PLL2 N Prescaler divides the output of the VCO as selected by

Mode_MUX1 and is connected to the PLL2 N divider.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

4 (0x04)

5 (0x05)

6 (0x06)

7 (0x07)

Value

8

2

3

4

5

6

7

7:5

PLL2_P

2

The frequency of the PLL2 reference input to the PLL2 Phase Detector

(OSCin/OSCin* port) must be programmed in order to support proper

operation of the frequency calibration routine which locks the internal VCO to

the target frequency.

Field Value

0 (0x00)

OSCin Frequency

0 to 63 MHz

4:2

OSCin_FREQ

3

1 (0x01)

>63 MHz to 127 MHz

>127 MHz to 255 MHz

Reserved

2 (0x02)

3 (0x03)

4 (0x04)

>255 MHz to 500 MHz

Reserved

5 (0x05) to 7(0x07)

1

0

NA

0

1

Reserved

Enabling the PLL2 reference frequency doubler allows for higher phase

detector frequencies on PLL2 than would normally be allowed with the given

VCXO frequency.

Higher phase detector frequencies reduces the PLL2 N values which makes

the design of wider loop bandwidth filters possible.

0: Doubler Disabled

PLL2_REF_2X_EN

1: Doubler Enabled

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8.6.2.8.3 PLL2_N_CAL

PLL2_N_CAL[17:0]

PLL2 never uses 0-delay during frequency calibration. These registers contain the value of the PLL2 N divider

used with PLL2 pre-scaler during calibration for cascaded 0-delay mode. Once calibration is complete, PLL2 will

use PLL2_N value. Cascaded 0-delay mode occurs when PLL2_NCLK_MUX = 1.

表8-71. PLL2_N_CAL[17:0]

—

MSB

LSB

0x163[1:0] / PLL2_N_CAL[17:16]

0x164[7:0] / PLL2_N_CAL[15:8]

0x165[7:0] / PLL2_N_CAL[7:0]

表8-72. Registers 0x163, 0x164, and 0x165

REGISTER

BIT

NAME

POR DEFAULT

DESCRIPTION

0x163

7:2

NA

0

Reserved

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

...

Divide Value

0x163

0x164

0x165

1:0

7:0

PLL2_N _CAL[17:16]

PLL2_N_CAL[15:8]

PLL2_N_CAL[7:0]

0

Not Valid

1

2

0

...

12

262,143 (0x3FFFF)

262,143

8.6.2.8.4 PLL2_N

This register disables frequency calibration and sets the PLL2 N divider value. Programming register 0x168

starts a VCO calibration routine if PLL2_FCAL_DIS = 0.

表8-73. PLL2_N[17:0]

—

MSB

LSB

0x166[1:0] / PLL2_N[17:16]

0x167[7:0] / PLL2_N[15:8]

0x168[7:0] / PLL2_N[7:0]

表8-74. Registers 0x166, 0x167, and 0x168

REGISTER

BIT

NAME

POR DEFAULT

DESCRIPTION

0x166

7:3

NA

0

Reserved

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

...

Divide Value

0x166

1:0

7:0

PLL2_N[17:16]

0

Not Valid

1

2

0x167

0x168

PLL2_N[15:8]

PLL2_N[7:0]

0

...

12

262,143 (0x3FFFF)

262,143

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8.6.2.8.5 PLL2_WND_SIZE, PLL2_CP_GAIN, PLL2_CP_POL, PLL2_CP_TRI

This register controls the PLL2 phase detector.

表8-75. Register 0x169

BIT

NAME

POR DEFAULT

DESCRIPTION

7

NA

0

Reserved

PLL2_WND_SIZE sets the window size used for digital lock detect for PLL2. If

the phase error between the reference and feedback of PLL2 is less than

specified time, then the PLL2 lock counter increments.

Maximum Phase Detector

Field Value

Frequency / Window Size

6:5

PLL2_WND_SIZE

2

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

Reserved

320 MHz / 1 ns

240 MHz / 1.8 ns

160 MHz / 2.6 ns

This bit programs the PLL2 charge pump output current level. The table below

also illustrates the impact of the PLL2 TRISTATE bit in conjunction with

PLL2_CP_GAIN.

Field Value

0 (0x00)

1 (0x01)

2 (0x02)

3 (0x03)

Definition

Reserved

1600 µA

4:3

PLL2_CP_GAIN

3

3200 µA

PLL2_CP_POL sets the charge pump polarity for PLL2. The internal VCO

requires the negative charge pump polarity to be selected. Many VCOs use

positive slope.

A positive slope VCO increases output frequency with increasing voltage. A

negative slope VCO decreases output frequency with increasing voltage.

2

PLL2_CP_POL

0

Field Value

Description

0

1

Negative Slope VCO/VCXO

Positive Slope VCO/VCXO

PLL2_CP_TRI TRI-STATEs the output of the PLL2 charge pump.

1

0

PLL2_CP_TRI

PLL2_DLD_EN

0

0: Disabled

1: TRI-STATE

PLL2 DLD circuitry is enabled when the PLL2 DLD is used to provide an output

to a lock detect status pin. PLL2_DLD_EN allows enabling the PLL2 DLD

circuitry without needing to provide PLL2 DLD to a status pin. This enables

PLL2 DLD status to be read back using SPI while allowing the Status pins to

be used for other purposes.

0: PLL2 DLD circuitry is on only of PLL2 DLD or PLL1 + PLL2 DLD signal is

output from a Status_LD_MUX.

1: PLL2 DLD circuitry is forced on.

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8.6.2.8.6 PLL2_DLD_CNT

表8-76. PLL2_DLD_CNT[13:0]

MSB

LSB

0x16A[5:0] / PLL2_DLD_CNT[13:8]

0x16B[7:0] / PLL2_DLD_CNT[7:0]

This register has the value of the PLL2 DLD counter.

表8-77. Registers 0x16A and 0x16B

REGISTER

BIT

NAME

POR DEFAULT

DESCRIPTION

0x16A

7

NA

0

Reserved

The reference and feedback of PLL2 must be within the

window of phase error as specified by PLL2_WND_SIZE for

PLL2_DLD_CNT cycles before PLL2 digital lock detect is

asserted.

PLL2_DLD

_CNT[13:8]

0x16A

0x16B

5:0

7:0

32

Field Value

0 (0x00)

Divide Value

Not Valid

1 (0x01)

1

2 (0x02)

2

3

3 (0x03)

PLL2_DLD_CNT

0

...

16,382 (0x3FFE)

16,383 (0x3FFF)

16,382

16,383

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8.6.2.8.7 PLL2_LD_MUX, PLL2_LD_TYPE

This register sets the output value of the Status_LD2 pin.

表8-78. Register 0x16E

BIT

NAME

POR DEFAULT

DESCRIPTION

This sets the output value of the Status_LD2 pin.

Field Value

0 (0x00)

MUX Value

Logic Low

PLL1 DLD

PLL2 DLD

PLL1 & PLL2 DLD

Holdover Status

DAC Locked

Reserved

1 (0x01)

2 (0x02)

3 (0x03)

4 (0x04)

5 (0x05)

6 (0x06)

7 (0x07)

SPI Readback

DAC Rail

7:3

PLL2_LD_MUX

0

8 (0x08)

9 (0x09)

DAC Low

10 (0x0A)

11 (0x0B)

DAC High

PLL1_N

12 (0x0C)

13 (0x0D)

14 (0x0E)

15 (0x0F)

PLL1_N/2

PLL2_N

PLL2_N/2

PLL1_R

16 (0x10)

PLL1_R/2

17 (0x11)

PLL2_R⁽¹⁾

PLL2_R/2⁽¹⁾

18 (0x12)

Sets the IO type of the Status_LD2 pin.

Field Value

0 (0x00)

TYPE

Reserved

1 (0x01)

Reserved

2:0

PLL2_LD_TYPE

6

2 (0x02)

Reserved

3 (0x03)

Output (push-pull)

4 (0x04)

5 (0x05)

6 (0x06)

Output inverted (push-pull)

Reserved

Output (open drain)

(1) Only valid when PLL1_LD_MUX is not set to 2 (PLL2_DLD) or 3 (PLL1 & PLL2 DLD).

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8.6.2.9 (0x16F - 0x555) Misc Registers

8.6.2.9.1 PLL2_PRE_PD, PLL2_PD, FIN0_PD

表8-79. Register 0x173

BIT

NAME

POR DEFAULT

DESCRIPTION

7

N/A

0

Reserved

Powerdown PLL2 prescaler

0: Normal Operation

1: Powerdown

6

5

PLL2_PRE_PD

PLL2_PD

1

Powerdown PLL2

0: Normal Operation

1: Powerdown

Powerdown Fin0

0: Normal Operation

1: Powerdown

4

FIN0_PD

N/A

1

0

3:0

Reserved

8.6.2.9.2 PLL1R_RST

Refer to 节8.3.1.1 for more information on synchronizing PLL1 R divider.

表8-80. Register 0x177

BIT

NAME

POR DEFAULT

DESCRIPTION

7:6

NA

0

Reserved

When set, PLL1 R divider will be held in reset. PLL1 will never lock with

PLL1R_RST = 1. This bit is used in when synchronizing the PLL1 R divider.

0: PLL1 R divider normal operation.

5

PLL1R_RST

NA

0

1: PLL1 R divider held in reset.

4:0

Reserved

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8.6.2.9.3 CLR_PLL1_LD_LOST, CLR_PLL2_LD_LOST

表8-81. Register 0x182

BIT

NAME

POR DEFAULT

DESCRIPTION

7:2

NA

0

Reserved

To reset RB_PLL1_LD_LOST, write CLR_PLL1_LD_LOST with 1 and then 0.

0: RB_PLL1_LD_LOST will be set on next falling PLL1 DLD edge.

1: RB_PLL1_LD_LOST is held clear (0). User must clear this bit to allow

RB_PLL1_LD_LOST to become set again.

1

0

CLR_PLL1_LD_LOST

CLR_PLL2_LD_LOST

0

To reset RB_PLL2_LD_LOST, write CLR_PLL2_LD_LOST with 1 and then 0.

0: RB_PLL2_LD_LOST will be set on next falling PLL2 DLD edge.

1: RB_PLL2_LD_LOST is held clear (0). User must clear this bit to allow

RB_PLL2_LD_LOST to become set again.

8.6.2.9.4 RB_PLL1_LD_LOST, RB_PLL1_LD, RB_PLL2_LD_LOST, RB_PLL2_LD

For PLL2 DLD read back to be valid, either PLL2 DLD or PLL1 + PLL2 DLD signal must be output from the

status pins, or PLL2_DLD_EN bit must be set = 1.

表8-82. Register 0x183

BIT

NAME

POR DEFAULT

DESCRIPTION

7:4

N/A

0

Reserved

This is set when PLL1 DLD edge falls. Does not set if cleared while PLL1 DLD

is low.

3

2

1

RB_PLL1_LD_LOST

RB_PLL1_LD

0

Read back 0: PLL1 DLD is low.

Read back 1: PLL1 DLD is high.

This is set when PLL2 DLD edge falls. Does not set if cleared while PLL2 DLD

is low.

RB_PLL2_LD_LOST

PLL1_LD_MUX or PLL2_LD_MUX must select setting 2 (PLL2 DLD) for valid

reading of this bit.

Read back 0: PLL2 DLD is low.

0

RB_PLL2_LD

0

Read back 1: PLL2 DLD is high.

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8.6.2.9.5 RB_DAC_VALUE (MSB), RB_CLKinX_SEL, RB_CLKinX_LOS

This register provides read back access to CLKinX selection indicator and CLKinX LOS indicator. The 2 MSBs

are shared with the RB_DAC_VALUE. See RB_DAC_VALUE section.

表8-83. Register 0x184

BIT

NAME

POR DEFAULT

DESCRIPTION

7:6

RB_DAC_VALUE[9:8]

See RB_DAC_VALUE section.

Read back 0: CLKin2 is not selected for input to PLL1.

Read back 1: CLKin2 is selected for input to PLL1.

5

4

RB_CLKin2_SEL

RB_CLKin1_SEL

Read back 0: CLKin1 is not selected for input to PLL1.

Read back 1: CLKin1 is selected for input to PLL1.

Read back 0: CLKin0 is not selected for input to PLL1.

Read back 1: CLKin0 is selected for input to PLL1.

3

2

1

RB_CLKin0_SEL

N/A

Read back 1: CLKin1 LOS is active.

Read back 0: CLKin1 LOS is not active.

RB_CLKin1_LOS

Read back 1: CLKin0 LOS is active.

Read back 0: CLKin0 LOS is not active.

0

RB_CLKin0_LOS

8.6.2.9.6 RB_DAC_VALUE

Contains the value of the DAC for user readback.

表8-84. RB_DAC_VALUE[9:0]

MSB

LSB

0x184 [7:6] / RB_DAC_VALUE[9:8]

0x185 [7:0] / RB_DAC_VALUE[7:0]

表8-85. Registers 0x184 and 0x185

REGISTER

BIT

NAME

POR DEFAULT

RB_DAC_

VALUE[9:8]

0x184

7:6

2

DAC value is 512 on power on reset, if PLL1 locks upon

power-up the DAC value will change.

RB_DAC_

VALUE[7:0]

0x185

7:0

0

8.6.2.9.7 RB_HOLDOVER

表8-86. Register 0x188

BIT

NAME

POR DEFAULT

DESCRIPTION

7:5

N/A

Reserved

Read back 0: Not in HOLDOVER.

Read back 1: In HOLDOVER.

4

RB_HOLDOVER

N/A

3:0

Reserved

8.6.2.9.8 SPI_LOCK

Prevents SPI registers from being written to, except for 0x555.

This register cannot be read back.

表8-87. Register 0x555

BIT

NAME

POR DEFAULT

DESCRIPTION

0: Registers unlocked.

1 to 255: Registers locked.

7:0

SPI_LOCK

0

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9 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

9.1 Application Information

To assist customers in frequency planning and design of loop filters, Texas Instruments provides Clock Architect

and PLLatinum Sim and on ti.com.

9.1.1 Treatment of Unused Pins

Not all pins are needed for every application. In general, power down the unused feature in software. The

unused pin may be left floating or grounded through a 1-kΩ resistor.

表9-1. Treatment of Unused Pins

PINS

TREATMENT IF UNUSED

1 kΩto GND or float pin

CLKoutX/CLKoutX*

RESET/GPO

SYNC/SYSREF_REQ

Fin0/Fin0*

Status_LD1,Status_LD2

CPout1/CPout2

OSCout/CLKin2

OSCout*/CLKin2*

9.1.2 Digital Lock Detect Frequency Accuracy

The digital lock detect circuit is used to determine PLL1 locked, PLL2 locked, and holdover exit events. A

window size and lock count register are programmed to set a ppm frequency accuracy of reference to feedback

signals of the PLL for each event to occur. When a PLL digital lock event occurs, the digital lock detect of the

PLL is asserted true. When the holdover exit event occurs, the device will exit holdover mode when

HOLDOVER_EXIT_MODE = 1 (Exit based on DLD).

表9-2. Digital Lock Detect Related Fields

EVENT

PLL

PLL1

WINDOW SIZE

LOCK COUNT

PLL1 Locked

PLL2 Locked

Holdover exit

PLL1_WND_SIZE

PLL2_WND_SIZE

PLL1_WND_SIZE

PLL1_DLD_CNT

PLL2_DLD_CNT

PLL2

PLL1

HOLDOVER_DLD_CNT

For a digital lock detect event to occur, there must be a lock count number of phase detector cycles of PLLX

during which the time and phase error of the PLLX_R reference and PLLX_N feedback signal edges are within

the user programmable window size. Because there must be at least one lock count phase detector event before

a lock event occurs, a minimum digital lock event time can be calculated as lock count / f_PDXwhere X = 1 for

PLL1 or 2 for PLL2.

By using 方程式 4, values for a lock count and window size can be chosen to set the frequency accuracy

required by the system in ppm before the digital lock detect event occurs:

1e6 × PLLX_WND_SIZE × f_PDX

ppm =

PLLX_DLD_CNT

(4)

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The effect of the lock count value is that it shortens the effective lock window size by dividing the window size by

lock count.

If at any time the PLLX_R reference and PLLX_N feedback signals are outside the time window set by window

size, then the lock count value is reset to 0.

9.1.2.1 Minimum Lock Time Calculation Example

To calculate the minimum PLL2 digital lock time given a PLL2 phase detector frequency of 40 MHz and

PLL2_DLD_CNT = 10,000. Then, the minimum lock time of PLL2 will be 10,000 / 40 MHz = 250 µs.

9.1.3 Driving CLKin AND OSCin Inputs

9.1.3.1 Driving CLKin and OSCin PINS With a Differential Source

CLKin and OSCin pins can be driven by differential signals. TI recommends setting the input mode to bipolar

(CLKinX_BUF_TYPE = 0) when using differential reference clocks. The device internally biases the input pins so

the differential interface should be AC-coupled. The recommended circuits for driving the CLKin pins with either

LVDS or LVPECL are shown in 图9-1 and 图9-2.

CLKinX

0.1 mF

100-W Trace

(Differential)

LMK04832

Input

LVDS

0.1 mF

CLKinX*

图9-1. CLKinX/X* or OSCin Termination for an LVDS Reference Clock Source

CLKinX

0.1 mF

100-W Trace

(Differential)

LVPECL

Ref Clk

LMK04832

Input

CLKinX*

图9-2. CLKinX/X* or OSCin Termination for an LVPECL Reference Clock Source

Finally, a reference clock source that produces a differential sine wave output can drive the CLKin pins using the

following circuit. Note: the signal level must conform to the requirements for the CLKin pins listed in the 节6.5.

CLKinX

0.1 mF

100-W Trace

(Differential)

LMK04832

Input

0.1 mF

CLKinX*

Differential

Sinewave Clock

Source

图9-3. CLKinX/X* or OSCin Termination for a Differential Sinewave Reference Clock Source

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9.1.3.2 Driving CLKin Pins With a Single-Ended Source

The CLKin and OSCin pins can be driven using a single-ended reference clock source, for example, either a

sine wave source or an LVCMOS/LVTTL source. CLKin supports both AC coupling or DC coupling. OSCin must

use AC coupling. In the case of the sine wave source that is expecting a 50-Ω load, TI recommends using AC

coupling as shown in 图9-4 with a 50-Ωtermination.

备注

The signal level must conform to the requirements for the CLKin or OSCin pins listed in the 节6.5.

To support LOS functionality, CLKinX_BUF_TYPE must be set to MOS mode (CLKinX_BUF_TYPE =

1) when AC-coupled. When AC coupling, if the 100-Ω termination is placed on the IC side of the

blocking capacitors, then the LOS functionality will not be valid.

0.1 mF

50-W Trace

CLKinX

50 W

LMK04832

Clock Source

CLKinX*

0.1 mF

图9-4. CLKinX/X* Single-Ended Termination

If the CLKin pins are being driven with a single-ended LVCMOS/LVTTL source, either DC coupling or AC

coupling may be used. If DC coupling is used, the CLKinX_BUF_TYPE should be set to MOS buffer mode

(CLKinX_BUF_TYPE = 1) and the voltage swing of the source must meet the specifications for DC -oupled,

MOS-mode clock inputs given in the 节 6.5. If AC coupling is used, the CLKinX_BUF_TYPE should be set to the

bipolar buffer mode (CLKinX_BUF_TYPE = 0). The voltage swing at the input pins must meet the specifications

for AC-coupled, bipolar mode clock inputs given in the 节 6.5. In this case, some attenuation of the clock input

level may be required. A simple resistive divider circuit before the AC-coupling capacitor is sufficient.

50-W Trace

CLKinX

LMK04832

LVCMOS/LVTTL

Clock Source

CLKinX*

0.1 mF

图9-5. DC-Coupled LVCMOS/LVTTL Reference Clock

9.1.4 OSCin Doubler for Best Phase Noise Performance

PLL2 OSCin input path includes an on-chip Frequency Doubler. To have the best phase noise performance, TI

recommends to maximize the PLL2 phase detector frequency. For example, using 122.88-MHz VCXO, PLL2

phase detector frequency can be increased to 245.76 MHz by setting PLL2_REF_2X_EN. Doubler path is a high

performance path for OSCin clock. For configuration where doubler cannot be used, TI recomends to use

Doubler and PLL2_RDIV = 2. To have deterministic phase relationship between input clock and output clocks, 0-

delay modes should be used (nested 0-delay mode for dual loop configuration instead of cascaded 0-delay

mode).

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9.1.5 Radiation Environments

9.1.5.1 Total Ionizing Dose

Radiation Hardness assured (RHA) products are those part numbers with a total ionizing dose (TID) level

specified in the ordering information. Testing and qualification of these product is done on a wafer level

according to MIL-STD-883, test method 1019. Wafer level TID data are available with lot shipments.

9.1.5.2 Single Event Effect

One time single event effect (SEE), including single event latch-up (SEL), single event functional interrupt (SEFI)

and single event upset (SEU), testing was performed according to EIA/JEDEC Standard, EIA/JEDEC57. A test

report is available upon request.

9.2 Typical Application

This design example highlights using the available tools to design loop filters and create programming map.

CLKout10

VCXO

aµoš]‰oꢀ ^ꢁoꢀꢂv_ ꢁo}ꢁl•

at different and much

higher frequencies

LMX2615-SP

Recovered

—dirty“ clock

or clean clock

CLKout11

PLL+VCO

CLKin0

OSCout

CLKout8

CLKout9

FPGA

Backup

Reference

Clock

LMK04832-SP

CLKin1

CLKout4 &

CLKout6

CLKout5 &

CLKout7

CLKout0 &

CLKout2

CLKout12,

CLKout13

D_DA_AC_C

ADC12DJ3200

QML-SP

CLKout1 &

CLKout3

Serializer/

Deserializer

图9-6. Typical Application

9.2.1 Design Requirements

Clocks outputs:

• 1x 245.76-MHz clock for JESD204B ADC, LVPECL.

– This clock requires the best performance in this example.

• 2x 2949.12-MHz clock for JESD204B DAC, CML.

• 1x 122.88-MHz clock for JESD204B FPGA block, LVDS.

• 3x 10.24-MHz SYSREF for ADC (LVPECL), DAC (LVPECL), FPGA (LVDS).

• 2x 122.88-MHz clock for FPGA, LVDS.

For best performance, the highest possible phase detector frequency is used at PLL2. As such, a 122.88-MHz

VCXO is used.

9.2.2 Detailed Design Procedure

备注

This information is current as of the date of the release of this data sheet. Design tools receive

continuous improvements to add features and improve model accuracy. Refer to the software

instructions or training for latest features.

9.2.2.1 Device Selection

Enter the required frequencies into the tools. In this design, VCO0 and VCO1 both meet the design

requirements. VCO0 offers a relatively improved VCO performance over VCO1. In this case, choose VCO0 for

improved RMS jitter in the 12-kHz to 20-MHz integration range.

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9.2.2.1.1 Clock Architect

Under the advanced tab of the Clock Architect, filtering of specific parts can be done using regular expressions

in the Part Filter box. [LMK04832.*] will filter for only the LMK04832 device (without brackets). More detailed

filters can be given such as the entire part name LMK04832_VCO0 to force an LMK04832 using VCO0 solution

if one is available.

9.2.2.2 Device Configuration and Simulation

The tools automatically configure the simulation to meet the input and output frequency requirements given, and

make assumptions about other parameters to give some default simulations. However, the user may chose to

make adjustments for more accurate simulations to their application. For example:

• Entering the VCO Gain of the external VCXO or possible external VCO used device.

• Adjust the charge pump current to help with loop filter component selection. Lower charge pump currents

result in smaller components but may increase impacts of leakage and at the lowest values reduce PLL

phase nosie performance.

• Clock Architect allows loading a custom phase noise plot for reference or VCXO block. Typically, a custom

phase noise plot is entered for CLKin to match the reference phase noise to device; a phase noise plot for the

VCXO can additionally be provided to match the performance of VCXO used. For improved accuracy in

simulation and optimum loop filter design, be sure to load these custom noise profiles for use in application.

• PLLatinum Sim can also be used to design and simulate a loop filter.

9.2.2.3 Device Programming

Using the clock design tools configuration the TICS Pro software is manually updated with this information to

meet the required application.

Frequency planning for assignment of outputs:

• To minimize crosstalk perform frequency planning / CLKout assignments to keep common frequencies on

outputs close together.

• It is best to place common device clock output frequencies on outputs sharing the same V_CCgroup. For

example, these outputs share Vcc4_CG2. Refer to 节5 to see the V_CCgroupings the clock outputs.

In this example, the 245.76-MHz ADC output needs the best performance. CLKout2 provides the best noise

floor / performance. The 245.76 MHz is placed on CLKout2 with 10.24-MHz SYSREF on CLKout3.

• For best performance the input and output drive level bits may be set. Best noise floor performance is

achieved with CLKout2_3_IDL = 1 and CLKout2_3_ODL = 1.

• The CLKoutX_Y_ODL bit has no impact on even clock outputs in high performance bypass mode.

In this example, the 983.04-MHz DAC output is placed on CLKout4 and CLKout6 with 10.24-MHz SYSREF on

paired CLKout5 and CLKout7 outputs.

• These outputs share Vcc4_CG2.

In this example, the 122.88-MHz FPGA JESD204B output is placed on CLKout10 with 10.24-MHz SYSREF on

paired CLKout11 output.

Additionally, the 122.88-MHz FPGA non-JESD204B outputs are placed on CLKout8 and CLKout9.

• When frequency planning, consider PLL2 as a clock output at the phase detector frequency. As such, these

122.88-MHz outputs have been placed on the outputs close to the PLL2 and Charge Pump power supplies.

Once the device programming is completed as desired in the TICS Pro software, it is possible to export the

register settings from the Register tab for use in application.

9.3 Power Supply Recommendations

9.3.1 Cold Sparing Considerations

图9-7 below demonstrates how this part can be used for cold sparing

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VCC1 = 3.3V ± 0.3V

VCC2 = 0V

+

–

+

–

Output of LMK

Device configured

as CMOS

220 ꢀ

Unpowered LMK

Device

(acting as cold spare)

CLKINX or SYNC

Powered

LMK Device

CLKinX

图9-7. Cold Sparing Devices Setup

9.3.1.1 Damage Prevention Details to Unpowered Device

Setting two devices in a cold sparing setup leads to the unpowered device receiving DC-coupled LVCMOS

pulses on the CLKIN0 or SYNC inputs periodically throughout the lifetime of the unpowered device. The

cumulative lifetime limit for the unpowered device DC input current is 10 hours at maximum junction

temperature. Also, the device can remain within specifications for much longer than this limit if the typical cold-

spare junction temperature is lower than maximum junction temperature. However, by placing a 220-Ω in series

between the output of the poweredde to the inputs of the unpowered devP, even when connected to a 3.3-V or

3.6-V powered system, DC pulses from the powered device do not damage the unpowered device. DC-coupling

3.3V or 3.6-V I/O can occur without the transmitter for the SYNC signal failing high and destroying the receiver,

or any other circuitry within the unpowered device. Also, the 220-Ωresistor limits the current to about 7 mA, with

less than 12 mW dissipated onto the unpowered device.

Additionally, if CLKIN is damaged or fails short in one of the CLKIN paths with the 220-Ω resistor in series to

ground on the fault path, the current is limited. The initial damage won't short to the outputs of the transmitter

powered device, and therefore, no damage occurs to the rest of the system. The inputs and outputs of each

device have separate power supply pins that are not connected internally; therefore, if the unpowered device is

powered, no issues can occur to the outputs, even if one of the inputs is damaged over the lifetime of the

unpowered device.

When driving the CLKINx or OSCin inputs of an unpowered device, signal levels up to ± 400 mV can be AC-

coupled through 0.01 µF across the operating frequency range. Under these constraints, the magnitude of the

RMS currents injected into the CLKinX ESD structures is within acceptable power and current limits across the

full junction temperature range and won't cause long-term degradation of function. Larger amplitudes, higher

frequencies, or different coupling capacitors can be acceptable as long as the signal is AC-coupled and the

unpowered current limit of 7 mA going into or coming out of the CLKIN or OSCIN pins is observed.

CLKIN or OSCIN

Unpowered

Device

0.01 ꢀF

± 400 mV square

wave source

图9-8. AC-Coupled ± 400 mV Signal Inputted to Unpowered Device

9.3.2 Current Consumption

TI recommends using the TICS Pro software to calculate the current consumption estimate based on

programmed configuration.

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9.4 Layout

9.4.1 Layout Guidelines

9.4.1.1 Thermal Management

Power consumption of the LMK04832-SP can be high enough to require attention from thermal management.

For reliability and performance reasons the die temperature should be limited to a maximum of 125°C. That is,

as an estimate, T_A(ambient temperature) plus device power consumption times R_θJAshould not exceed 125°C.

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9.4.2 Layout Example

CLKouts/OSCouts - Differential signals should

be routed tightly coupled to minimize PCB

crosstalk.

For LVPECL/LCPECL/CML place components

resistors close to IC.

CLKin and OSCin - If differential input

(preferred) route traces tightly coupled. If single

ended, have at least 3-trace width (of CLKin/

OSCin trace) separation from other RF traces.

Place terminations close to IC. CLKin2 and

OSCout share pins and are programmable

for input or output.

OSCout shares pins with CLKin2 and is

programmable for input or output.

For CLKout Vccs in JESD204B application,

Place the ferrite beads then a 1-µF capacitor.

The 1-µF capacitor supports low-frequency

SYSREF switching/turning on.

Charge pump output - shorter traces are

better. Place all resistors and caps close to

the IC.

For CLKout Vccs in traditional applications,

place a ferrite bead on top layer close to pins

to choke high-frequency noise from the via.

图9-9. Top Layer

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A flexible termination / PCB layout for

either CML requiring a pullup to Vcc or

LVPECL/LCPECL requiring a pulldown to

ground, or the H configuration for any other

format as illustrated in layout above.

Expose copper under the PCB to

provide direct copper-to-air interface

to dissipate heat.

Provide areas of connect copper to

allow heat to escape from directly

below PCB. Do not let components

block all thermal escape from the

ground pad.

图9-10. Bottom Layer

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10 Device and Documentation Support

10.1 Device Support

10.1.1 Development Support

10.1.1.1 Clock Architect

Part selection, loop filter design, simulation.

To run the online Clock Architect tool, go to www.ti.com/clockarchitect.

10.1.1.2 PLLatinum Sim

Supports loop filter design and simulation. All simulation is for a single loop, to perform dual loop simulations, the

result of the first PLL sim must be loaded as a reference to the second PLL sim.

To download PLLatinum Sim tool, go to www.ti.com/tool/PLLATINUMSIM-SW

10.1.1.3 TICS Pro

EVM programming software. Can also be used to generate register map for programming and calculate current

consumption estimate.

For TICS Pro, go to www.ti.com/tool/TICSPRO-SW

10.2 Documentation Support

10.2.1 Related Documentation

For releated documentation, see the following:

• AN-912 Common Data Transmission Parameters and their Definitions (SNLA036)

10.3 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

10.4 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

10.5 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

10.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

10.7 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

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11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This data is subject to change

without notice and revision of this document.

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PACKAGE OUTLINE

HBE0064B

CFP - 3.53 mm max height

S

C

A

L

E

0

.

8

0

CERAMIC FLATPACK

29.36 0.38

11.03

10.77

64

49

29.36 0.38

SEAL RING

4X

(R0.75)

4X (3.43)

0.27

64X

0.17

1

48

10.16 0.08

4X 7.5 0.13

4X 9.5 0.13

33

16

60X 0.5 0.05

4X (45 X 0.3)

4X ( 0.38)

8X (R0.55)

64X 0.5 MAX

4X (1.78)

17

32

0.76 0.13

4X (1.1)

1.45 0.15

(0.3)

(0.2) TYP

3.53 MAX

1.5 0.1

(0.73) TYP

64X 0.15 0.05

(

8)

HEAT SINK

17

32

16

33

48

SYMM

8

0.13

HEAT SINK

1

PIN 1 ID

64

49

SYMM

BOTTOM VIEW

4225428/B 05/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This package is hermetically sealed with a metal lid.

4. Ground pad to be electronic connected to heat sink and seal ring.

5. The leads are gold plated and can be solder dipped.

www.ti.com

EXAMPLE BOARD LAYOUT

HBE0064B

CFP - 3.53 mm max height

CERAMIC FLATPACK

(

8)

(1.23)

TYP

(1.23) TYP

(

0.2) TYP

VIA

(R0.05) TYP

HEATSINK LAND PATTERN EXAMPLE

SCALE: 10X

4225428/B 05/2022

www.ti.com

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TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	SN0064HBE
厂家：	TEXAS INSTRUMENTS
描述：	耐辐射加固保障 (RHA)、超低噪声、3.2GHz、15 路输出时钟抖动清除器 \| HBE \| 64 \| 25 to 25 时钟
文件：	总101页 (文件大小：2706K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SN0064HBE [TI]

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