SN100KT5541NT [TI]
OCTAL ECL-TO-TTL TRANSLATOR WITH 3-STATE OUTPUTS;
| 型号： | SN100KT5541NT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OCTAL ECL-TO-TTL TRANSLATOR WITH 3-STATE OUTPUTS 光电二极管 输出元件 接口集成电路 锁存器 |
| 文件： | 总8页 (文件大小：121K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁ ꢂꢃ ꢃꢄ ꢅꢆꢆ ꢇꢂ
ꢈ ꢉꢅꢊꢋꢌꢍ ꢉꢋ ꢎꢅꢈ ꢎꢅ ꢅꢋꢌꢅ ꢏꢊ ꢁꢀ ꢋꢊꢅꢈ ꢏ
ꢐ ꢑꢅ ꢒꢌ ꢓ ꢎꢀꢅꢊꢅ ꢍꢌ ꢈ ꢔꢅ ꢕꢔ ꢅꢀ
SDZS004A − NOVEMBER 1989 − REVISED MAY 1990
DW OR NT PACKAGE
(T0P VIEW)
• 100K Compatible
• ECL and TTL Control Inputs
• Noninverting Outputs
Y1
Y2
Y3
Y4
A1
A2
A3
A4
1
24
23
22
21
20
19
18
17
16
15
14
13
2
• Flow-Through Architecture Optimizes PCB
3
4
Layout
V
OE2 (TTL)
5
CC
• Center Pin V , V , and GND
CC EE
GND
GND
GND
Y5
Y6
Y7
V
6
EE
Configurations Minimize High-Speed
GND
OE1 (ECL)
A5
A6
A7
A8
7
Switching Noise
8
9
• Package Options Include “Small Outline”
Packages and Standard Plastic 300-mil
DIPs
10
11
12
Y8
description
†
logic symbol
This octal ECL-to-TTL translator is designed to
provide a efficient translation between a 100K
ECL signal environment to a TTL signal
environment. This device is designed specifically
ECL/TTL
&
17
OE1
EN
20
OE2
to
the performance and density of ECL-to-TTL
CPU/bus-oriented functions such as
improve
24
1
2
ECL/TTL
A1
Y1
23
memory-address drivers, clock drivers, and
bus-oriented receivers and transmitters.
A2
Y2
Y3
Y4
22
3
4
9
A3
21
Two output-enable pins, OE1 and OE2 are
provided. These control inputs are ANDed
together with OE1 being ECL compatible and OE2
being TTL compatible. This offers the choice of
controlling the outputs of the device from either a
TTL or ECL signal environment.
A4
16
A5
Y5
Y6
Y7
Y8
15
10
11
12
A6
14
A7
13
A8
†
The SN100KT5541 is characterized for operation
from 0°C to 85°C.
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
FUNCTION TABLE
OUTPUT
ENABLE
DATA
OUTPUT
INPUT
(TTL)
OE1
OE2
A
X
X
L
Y
Z
Z
L
X
H
L
H
X
L
L
L
H
H
ꢕ
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ꢁ
ꢙ
ꢖ
ꢊ
ꢅ
ꢊ
ꢗ
ꢘ
ꢢ
ꢙ
ꢚ
ꢠ
ꢛ
ꢜ
ꢝ
ꢝ
ꢞ
ꢞ
ꢗ
ꢗ
ꢚ
ꢚ
ꢘ
ꢘ
ꢗ
ꢟ
ꢟ
ꢣ
ꢠ
ꢡ
ꢛ
ꢛ
ꢢ
ꢢ
ꢘ
ꢞ
ꢝ
ꢜ
ꢟ
ꢟ
ꢚ
ꢙ
ꢣ
ꢅꢢ
ꢡ
ꢤ
ꢟ
ꢥ
ꢗ
ꢠ
ꢝ
ꢟ
ꢞ
ꢗ
ꢞ
ꢚ
ꢛ
ꢘ
ꢡ
ꢦ
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ꢞ
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ꢧ
Copyright 1990, Texas Instruments Incorporated
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ꢨ
ꢞ
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ꢛ
ꢚ
ꢙ
ꢩ
ꢝ
ꢑ
ꢘ
ꢜ
ꢢ
ꢟ
ꢞ
ꢝ
ꢘ
ꢦ
ꢝ
ꢛ
ꢦ
ꢪ
ꢝ
ꢞ ꢢ ꢟ ꢞꢗ ꢘꢬ ꢚꢙ ꢝ ꢥꢥ ꢣꢝ ꢛ ꢝ ꢜ ꢢ ꢞ ꢢ ꢛ ꢟ ꢧ
ꢛ
ꢛ
ꢝ
ꢘ
ꢞ
ꢫ
ꢧ
ꢕ
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ꢦ
ꢡ
ꢠ
ꢞ
ꢗ
ꢚ
ꢘ
ꢣ
ꢛ
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ꢠ
ꢢ
ꢟ
ꢟ
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ꢘ
ꢬ
ꢦ
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ꢞ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃꢃ ꢄ ꢅ ꢆꢆ ꢇꢂ
ꢈ
ꢉ
ꢅ
ꢊ
ꢋ
ꢌ
ꢍ
ꢉ
ꢋ
ꢎ
ꢅ
ꢈ
ꢎ
ꢅ
ꢅ
ꢋ
ꢌ
ꢅ
ꢐꢑ ꢅ ꢒ ꢌꢓ ꢎꢀ ꢅꢊꢅꢍ ꢌ ꢈ ꢔꢅ ꢕꢔꢅ ꢀ
ꢏ
ꢊ
ꢁ
ꢀ
ꢋ
ꢊ
ꢅ
ꢈ
ꢏ
SDZS004A − NOVEMBER 1989 − REVISED MAY 1990
logic diagram (positive logic)
24
23
22
21
1
2
3
4
Y1
Y2
Y3
Y4
A1
ECL/TTL
ECL/TTL
ECL/TTL
ECL/TTL
A2
A3
A4
17
20
ECL/TTL
OE1 (ECL)
OE2 (TTL)
16
15
9
Y5
Y6
A5
A6
A7
A8
ECL/TTL
ECL/TTL
ECL/TTL
ECL/TTL
10
14
13
11
12
Y7
Y8
2
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂꢃ ꢃꢄ ꢅꢆꢆ ꢇꢂ
ꢈ ꢉꢅꢊꢋꢌꢍ ꢉꢋ ꢎꢅꢈ ꢎꢅ ꢅꢋꢌꢅ ꢏꢊ ꢁꢀ ꢋꢊꢅꢈ ꢏ
ꢐ ꢑꢅ ꢒꢌ ꢓ ꢎꢀꢅꢊꢅ ꢍꢌꢈ ꢔ ꢅꢕ ꢔꢅ ꢀ
SDZS004A − NOVEMBER 1989 − REVISED MAY 1990
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −8 V to 0 V
CC
EE
Input voltage range (TTL) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −1.2 V to 7 V
Input voltage range (ECL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V to 0 V
EE
Voltage applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
CC
Voltage applied to any output in the disabled or power-off state . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 5.5 V
Input current range (TTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −30 mA to 5 mA
Current into any output in the low state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 85°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The TTL input voltage ratings may be exceeded provided the input current ratings are observed.
recommended operating conditions
MIN
4.5
−4.2
2
NOM
5
MAX
5.5
UNIT
V
V
V
V
V
V
V
TTL supply voltage
CC
EE
IH
IL
ECL supply voltage
−4.5
−4.8
V
TTL high-level input voltage
TTL low-level input voltage
ECL high-level input voltage
V
0.8
−840
−1490
−18
V
‡
−1150
−1810
mV
mV
mA
mA
mA
°C
IH
IL
‡
ECL low-level input voltage
TTL input clamp current
High-level output current
Low-level output current
I
I
I
IK
−15
OH
OL
48
T
A
Operating free-air temperature
0
85
‡
The algebraic convention, in which the least positive (most negative) value is designated minimum, is used in this data sheet for logic levels only.
3
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃꢃ ꢄ ꢅ ꢆꢆ ꢇꢂ
ꢈꢉ ꢅꢊ ꢋꢌ ꢍꢉ ꢋ ꢎꢅꢈ ꢎꢅꢅꢋꢌ ꢅꢏ ꢊꢁ ꢀꢋ ꢊꢅꢈ ꢏ
ꢐꢑ ꢅ ꢒ ꢌꢓ ꢎꢀ ꢅꢊꢅꢍ ꢌ ꢈ ꢔꢅ ꢕꢔꢅ ꢀ
SDZS004A − NOVEMBER 1989 − REVISED MAY 1990
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
OE2 only
TEST CONDITIONS
= −4.2 V, I = −18 mA
I
MIN TYP
MAX
−1.2
0.1
UNIT
V
V
IK
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 4.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 4.5 V,
= 4.5 V,
= 4.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5 V,
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
I
I
I
I
I
OE2 only
= −4.8 V,
V = 7 V
I
mA
µA
mA
µA
I
OE2 only
= −4.8 V,
V = 2.7 V
I
20
IH
IL
IH
IL
OE2 only
= −4.8 V,
V = 0.5 V
I
−0.5
350
Data inputs and OE1
Data inputs and OE1
= −4.8 V,
V
V
= −840 mV
= −1810 mV
= −3 mA
= −15 mA
= 48 mA
= 2.7 V
IH
IL
= −4.8 V,
0.50
µA
= −4.5 V 0.3 V,
= −4.5 V 0.3 V,
= −4.5 V 0.3 V,
= −4.8 V,
I
I
I
2.4
2
3.3
3.1
OH
OH
OL
V
V
OH
V
OL
0.38
0.55
50
V
I
I
I
I
I
I
I
V
O
V
O
V
O
µA
µA
mA
mA
mA
mA
mA
pF
OZH
OZL
= −4.8 V,
= 0.5 V
−50
−225
97
‡
= −4.8 V,
= 0 V
−100
OS
= −4.8 V
64
80
77
−22
5
CCH
CCL
CCZ
EE
= −4.8 V
120
116
−33
= −4.8 V
= −4.8 V
C
= 4.5 V
i
C
= 5 V,
= 4.5 V
7
pF
o
†
‡
All typical values are at V
= 5 V, V
= −4.5 V, T = 25°C.
CC
EE A
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Figure 1)
C
= 50 pF,
L
FROM
TO
R1 = 500 Ω,
R2 = 500 Ω
PARAMETER
UNIT
(INPUT)
(OUTPUT)
§
MIN TYP
MAX
6.2
6.2
6.7
8.5
7.8
7.8
6.2
7.7
6.4
6.3
t
t
t
t
t
t
t
t
t
t
1.7
1.6
4
4
PLH
PHL
PZH
PZL
PHZ
PLZ
PZH
PZL
PHZ
PLZ
A
Y
ns
2.6
3.2
2.9
1.9
1.7
2.5
2.1
1.1
4.7
5.9
5.4
4.9
4
OE1
OE1
Y
Y
ns
ns
OE2
OE2
Y
Y
ns
ns
5.1
4.3
3.7
§
All typical values are at V
CC
= 5 V, V = −4.5 V, T = 25°C.
EE A
4
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂꢃ ꢃꢄ ꢅꢆꢆ ꢇꢂ
ꢈ ꢉꢅꢊꢋꢌꢍ ꢉꢋ ꢎꢅꢈ ꢎꢅ ꢅꢋꢌꢅ ꢏꢊ ꢁꢀ ꢋꢊꢅꢈ ꢏ
ꢐ ꢑꢅ ꢒꢌ ꢓ ꢎꢀꢅꢊꢅ ꢍꢌꢈ ꢔ ꢅꢕ ꢔꢅ ꢀ
SDZS004A − NOVEMBER 1989 − REVISED MAY 1990
THERMAL INFORMATION
Junction-to-Ambient
Thermal Resistance
vs
In digital system designs utilizing 100KT’ or 10KHT’
series logic level translators, good thermal
management is an important consideration for proper
circuit performance and extended reliability. The size of
the “small outline” package makes thermal
management even more important due to the increased
board and thermal densities.
Air Velocity
100
24-Pin DW Package
28-Pin DW Package
80
60
40
20
0
The thermal resistances in Figure 1 can be used to
approximate typical and maximum virtual junction
temperatures for the SN100KT’ and SN10KHT’
translators. The junction temperature of these devices
may be estimated using Equation 1.
24-Pin NT Package
28-Pin NT Package
0
200
400
600
800
1000
Air Velocity − linear ft/min
T = R
(V
• I
+ V • I + P
) + T
A
(1)
J
ΘJA CC CC
EE EE
DRIVER
where
T = virtual junction temperature
J
T = ambient air temperature
A
R
= thermal resistance, junction to ambient air
= TTL level supply current (from the databook)
= ECL supply current
ΘJA
I
I
CC
EE
V
V
= TTL level suply voltage (5 V for typical, 5.5 V for maximum)
= ECL level supply voltage:
CC
EE
SN10KHT’ − (−5.2 V Typ, −5.46 V Max)
SN100KHT’ − (−54.5 V Typ, −4.80 V Max)
P
= total power consumed by the output driver
DRIVER
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢐꢑ ꢅ ꢒ ꢌꢓ ꢎꢀ ꢅꢊꢅꢍ ꢌ ꢈ ꢔꢅ ꢕꢔꢅ ꢀ
SDZS004A − NOVEMBER 1989 − REVISED MAY 1990
PARAMETER MEASUREMENT INFORMATION
7 V
SWITCH POSITION TABLE
TEST
S1
Open
R1
S1
t
t
Open
Open
Open
Closed
Open
Closed
PLH
PHL
PZH
t
t
From Output
Under Test
Test
Point
t
PZL
PHZ
t
PLZ
C
R2
L
(See Note A)
LOAD CIRCUIT
t
t
r
f
−950 mV
−1690 mV
80%
50%
80%
50%
ECL Input
(See Note B)
20%
20%
t
PHL
t
PLH
1.5 V
V
OH
In-Phase
TTL Output
1.5 V
V
OL
ECL- INPUT PROPAGATION DELAY TIMES
−950 mV
3 V
ECL Output
Control
(Low-level
enabling)
TTL Output
Control
(Low-level
enabling)
(See Note B)
50%
50%
1.5 V
1.5 V
−1690 mV
0
t
t
PZL
t
PLZ
PZL
t
PLZ
3.5 V
3.5 V
Output
Waveform 1
(See Note D)
Output
Waveform 1
(See Note D)
50%
50%
50%
V
OL
0.3 V
0.3 V
V
V
OL
t
PZH
t
t
PHZ
t
PHZ
PZH
OH
Output
Waveform 2
(See Note D)
V
0
OH
0.3 V
Output
Waveform 2
(See Note D)
0.3 V
50%
0
TTL ENABLE AND DISABLE TIMES
ECL ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. For TTL inputs, input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns,
o
r
t ≤ 2.5 ns.
f
C. For ECL inputs, input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 1.5 ns,
o
r
t ≤ 1.5 ns.
f
D. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2
is for an output with internal conditions such that the output is high except when disabled by the output control.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
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PACKAGE OPTION ADDENDUM
www.ti.com
24-Jun-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
SOIC
PDIP
PDIP
Drawing
SN100KT5541DW
SN100KT5541NT
SN100KT5541NT
OBSOLETE
OBSOLETE
OBSOLETE
DW
24
24
24
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
NT
NT
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
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Addendum-Page 1
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