SN100KT5574DW [TI]
OCTAL ECL-TO-TTL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND 3-STATE OUTPUTS;
| 型号： | SN100KT5574DW |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OCTAL ECL-TO-TTL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND 3-STATE OUTPUTS 光电二极管 输出元件 接口集成电路 锁存器 |
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SN100KT5574
OCTAL ECL-TO-TTL TRANSLATOR WITH D-TYPE
EDGE-TRIGGERED FLIP-FLOPS AND 3-STATE OUTPUTS
SDZS009 – D3418, JANUARY 1990
DW OR NT PACKAGE
(TOP VIEW)
• 100K Compatible
• ECL Clock and TTL Control Inputs
• Flow-Through Architecture Optimizes PCB
1Q
2Q
3Q
4Q
1D
2D
3D
4D
1
24
23
22
21
20
19
18
17
16
15
14
13
Layout
2
• Center Pin V , V , and GND
3
CC EE
Configurations Minimize High-Speed
Switching Noise
4
V
OE(TTL)
5
CC
GND
V
• Package Options Include “Small Outline”
6
EE
GND
GND
5Q
6Q
7Q
GND
CLK(ECL)
5D
6D
7D
Packages and Standard Plastic DIPs
7
8
description
9
10
11
12
This octal ECL-to-TTL translator is designed to
provide efficient translation between a 100K ECL
signal environment and a TTL signal environment.
8Q
8D
This device is designed specifically to improve the performance and density of ECL-to-TTL CPU/bus-oriented
functions such as memory-address drivers, clock drivers, and bus-oriented receivers and transmitters.
The eight flip-flops of the SN100KT5574 are edge-triggered D-type flip-flops. On the positive transition of the
clock, the Q outputs are set to the logic levels that were set up at the D inputs.
A buffered output-enable input (OE) can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance third state and increased drive provide the capability to drive
bus lines without need for interface or pullup components.
The output-enable input OE does not affect the internal operations of the flip-flops. Old data can be retained
or new data can be entered while the outputs are off.
The SN100KT5574 is characterized for operation from 0°C to 85°C.
FUNCTION TABLE
OUTPUT
INPUTS
(TTL)
OE
L
CLK
D
L
Q
L
↑
↑
L
H
X
X
H
Q
L
L
X
o
H
Z
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard
warranty. Production processing does not necessarily include testing of all
parameters.
Copyright 1990, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN100KT5574
OCTAL ECL-TO-TTL TRANSLATOR WITH D-TYPE
EDGE-TRIGGERED FLIP-FLOPS AND 3-STATE OUTPUTS
†
logic symbol
logic diagram (positive logic)
17
ECL/TTL
CLK
20
17
C1
OE
20
EN
1D
OE
ECL/TTL
CLK
1
C1
1D
1Q
24
1
2
24
1D
ECL/TTL
1Q
2Q
3Q
1D
ECL/TTL
23
2D
2
3
22
3
4
C1
1D
2Q
3Q
4Q
3D
23
22
ECL/TTL
ECL/TTL
ECL/TTL
2D
3D
4D
21
4Q
5Q
4D
9
16
C1
1D
5D
10
11
12
15
6Q
7Q
8Q
6D
14
7D
4
C1
1D
13
21
16
15
8D
9
C1
1D
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
5Q
6Q
ECL/TTL
ECL/TTL
5D
6D
10
11
C1
1D
C1
1D
7Q
8Q
14
13
ECL/TTL
ECL/TTL
7D
8D
12
C1
1D
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2
SN100KT5574
OCTAL ECL-TO-TTL TRANSLATOR WITH D-TYPE
EDGE-TRIGGERED FLIP-FLOPS AND 3-STATE OUTPUTS
†
absolute maximum ratings over operating temperature range (unless otherwise noted)
Supply voltage range, V
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –8 V to 0 V
CC
EE
Input voltage range: TTL (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.2 V to 7 V
ECL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V to 0 V
EE
Voltage applied to any output in the disabled or power-off state . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
Voltage applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
CC
Input current range, TTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30 mA to 5 mA
Current into any output in the low state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 85°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The TTL input voltage ratings may be exceeded provided the input current ratings are observed.
recommended operating conditions
MIN
4.5
–4.2
2
NOM
5
MAX
5.5
UNIT
V
V
V
V
V
TTL supply voltage
CC
EE
IH
ECL supply voltage
–4.5
–4.8
V
TTL high-level input voltage
TTL low-level input voltage
TTL input clamp current
ECL high-level input voltage
V
0.8
–18
V
IL
I
IK
mA
mV
mV
mA
mA
°C
‡
V
IH
V
IL
–1150
–1810
–840
–1490
–15
‡
ECL low-level input voltage
High-level output current
Low-level output current
I
I
OH
48
OL
T
A
Operating temperature range
0
85
‡
The algebraic convention, in which the least positive (most negative) value is designated minimum, is used in this data sheet for logic levels only.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN100KT5574
OCTAL ECL-TO-TTL TRANSLATOR WITH D-TYPE
EDGE-TRIGGERED FLIP-FLOPS AND 3-STATE OUTPUTS
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
OE only
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 4.5 V,
= 4.5 V,
= 4.5 V,
= 4.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
= –4.2 V,
I = –18 mA
–1.2
V
IK
I
= –4.5 V ± 0.3 V,
= –4.5 V ± 0.3 V,
= –4.5 V ± 0.3 V,
= –4.8 V,
I
I
I
= –3 mA
= –15 mA
= 48 mA
2.4
2
3.3
3.1
OH
OH
OL
OH
V
V
OL
0.38
0.55
0.1
V
I
I
I
I
I
I
I
I
I
I
I
I
OE only
V = 7 V
I
V = 2.7 V
I
V = 0.5 V
I
mA
µA
mA
µA
µA
µA
µA
mA
mA
mA
mA
mA
pF
I
OE only
= –4.8 V,
20
IH
OE only
= –4.8 V,
–0.5
350
IL
Data inputs and CLK
Data inputs and CLK
= –4.8 V,
V
IH
V
IL
V
O
V
O
V
O
= –840 mV
= –1810 mV
= 2.7 V
IH
= –4.8 V,
0.50
IL
= –4.8 V,
50
–50
–225
95
OZH
= –4.8 V,
= 0.5 V
OZL
‡
= –4.8 V,
= 0 V
–100
OS
= –4.8 V
66
76
74
–43
5
CCH
CCL
CCZ
EE
= –4.8 V
110
= –4.8 V
106
–61
= –4.8 V
C
= –4.5 V
i
C
= –4.5 V
7
pF
o
†
‡
All typical values are at V
= 5 V, V
= –4.5 V, T = 25°C.
A
CC
EE
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
timing requirements
V
V
= 4.5 V to 5.5 V,
CC
= –4.2 V to –4.8 V,
§
= MIN to MAX
EE
UNIT
T
A
MIN
MAX
CLK high
CLK low
Data high
Data low
Data high
Data low
4
4
1
1
1
1
t
Pulse duration
w
ns
t
t
Hold time after CLK↑
h
ns
ns
Setup time before CLK↑
su
§
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4
SN100KT5574
OCTAL ECL-TO-TTL TRANSLATOR WITH D-TYPE
EDGE-TRIGGERED FLIP-FLOPS AND 3-STATE OUTPUTS
switching characteristics over recommended ranges of operating free-air temperature and supply
voltage (see Figure 1)
C
= 50 pF,
L
FROM
TO
R1 = 500 Ω,
R2 = 500 Ω
PARAMETER
UNIT
(INPUT)
(OUTPUT)
†
MIN TYP
MAX
f
t
t
t
t
t
t
200
2.3
2.9
1.9
2.7
2.1
0.5
300
4.1
4.6
3.6
4.8
3.9
3.4
MHz
ns
max
PLH
PHL
PZH
PZL
PHZ
PLZ
7
7.4
6.3
7.7
6.1
6.3
CLK
OE
Q
Q
Q
ns
ns
OE
†
All typical values are at V
= 5 V, V
= –4.5 V, T = 25°C.
EE A
CC
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN100KT5574
OCTAL ECL-TO-TTL TRANSLATOR WITH D-TYPE
EDGE-TRIGGERED FLIP-FLOPS AND 3-STATE OUTPUTS
PARAMETER MEASUREMENT INFORMATION
7 V
Open
SWITCH POSITION TABLE
S1
TEST
S1
t
t
t
t
t
t
Open
Open
Open
Closed
Open
Closed
PLH
PHL
PZH
PZL
PHZ
PLZ
R1
From Output
Under Test
Test Point
C
R2
L
(See Note A)
LOAD CIRCUIT
–950 mV
t
f
High-Level
t
50%
r
50%
50%
Input
–950 mV
–1690 mV
ECL Input
80% 80%
50%
50%
(See Note C)
t
w
20%
20%
–1690 mV
–950 mV
t
t
PLH
PHL
Low-Level
Input
50%
V
OH
–1690 mV
Out-of-Phase
TTL Output
1.5 V
PLH
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
V
OL
t
t
PHL
3 V
V
OH
Output
In-Phase
TTL Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
(Low-Level
Enabling)
V
OL
0
t
t
PZL
VOLTAGE WAVEFORMS
ECL-INPUT PROPAGATION DELAY TIMES
t
PLZ
3.5 V
Output
t
r
t
f
Waveform 1
(See Note D)
1.5 V
–950 mV
80% 80%
50% 50%
Timing
Input
V
OL
20%
20%
–1690 mV
t
0.3 V
PHZ
PZH
t
su
V
OH
t
h
Output
Waveform 2
(See Note D)
–950 mV
Data
1.5 V
0.3 V
0
80% 80%
50%
50%
20%
Input
20%
–1690 mV
t
r
VOLTAGE WAVEFORMS
TTL ENABLE AND DISABLE TIMES
t
f
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
NOTES: A.C includes probe and jig capacitance.
L
B.For TTL inputs, input pulses are supplied by generators having the following characteristics PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns,
o
r
t ≤ 2.5 ns.
f
C.For ECL inputs, input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 0.7 ns,
o
r
t
f
≤ 0.7 ns.
D.Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
E.The outputs are measured one at a time with one transition per measurement.
figure 1. load circuit and voltage waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
6
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jun-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
SOIC
PDIP
Drawing
SN100KT5574DW
SN100KT5574NT
OBSOLETE
OBSOLETE
DW
24
24
TBD
TBD
Call TI
Call TI
Call TI
Call TI
NT
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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