SN10501DGK [TI]
HIGH SPEED RAIL TO RAIL OUTPUT VIDEO AMPLIFIERS; 高速轨至轨输出视频放大器
| 型号： | SN10501DGK |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HIGH SPEED RAIL TO RAIL OUTPUT VIDEO AMPLIFIERS |
| 文件： | 总23页 (文件大小：552K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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www.ti.com
SLOS408A − MARCH 2003 − REVISED DECEMBER 2003
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FEATURES
APPLICATIONS
D
D
D
D
D
Video Line Driver
Imaging
D
D
High Speed
− 100 MHz Bandwidth (−3 dB, G= 2)
− 900 V/µs Slew Rate
DVD / CD ROM
Active Filtering
General Purpose Signal Chain Conditioning
Excellent Video Performance
− 50 MHz Bandwidth (0.1 dB, G = 2)
− 0.007% Differential Gain
VIDEO DRIVE CIRCUIT
− 0.007° Differential Phase
V
S+
D
Rail-to-Rail Output Swing
+
− V = −4.5 / 4.5 (R = 150 Ω)
O
L
10 µF
0.1 µF
75 Ω
Video In
D
D
High Output Drive, I = 100 mA (typ)
O
5
3
4
SN10501
1
+
V
O
Ultralow Distortion
− HD2 = −78 dBc (f = 5 MHz, R = 150Ω)
− HD3 = −85 dBc (f = 5 MHz, R = 150Ω)
75 Ω
−
L
L
2
75 Ω
+
10 µF
0.1 µF
D
Wide Range of Power Supplies
V
S−
− V = 3 V to 15 V
S
1.43 kΩ
1.43 kΩ
DESCRIPTION
The SN1050x family is a set of rail-to-rail output single,
dual, and triple low-voltage, high-output swing, low-
distortion high-speed amplifiers ideal for driving data
converters, video switching, or low distortion applications.
This family of voltage feedback amplifiers can operate
from a single 15-V power supply down to a single 3-V
power supply while consuming only 14 mA of quiescent
current per channel. In addition, the family offers excellent
ac performance with 100-MHz bandwidth, 900-V/µs slew
rate and harmonic distortion (THD) at –78 dBc at 5 MHz.
FREQUENCY RESPONSE
6.3
V
= 0.1 V
O
PP
6.2
−0.1 dB at 49 MHz
6.1
6.0
5.9
5.8
5.7
V
= 2 V
PP
O
−0.1 dB at 51 MHz
5.6
5.5
Gain = 2
R
L
= 150 Ω to GND
V
R
= 5 V
= 1.43 kΩ
S
F
5.4
5.3
DEVICE
SN10501
SN10502
SN10503
DESCRIPTION
Single
100 k
1 M
10 M
100 M
1 G
f − Frequency − Hz
Dual
Triple
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
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ꢋꢢ ꢡ ꢭꢨꢧ ꢥ ꢞꢡ ꢟ ꢪꢢ ꢡ ꢧ ꢩ ꢦ ꢦ ꢞꢟ ꢳ ꢭꢡ ꢩ ꢦ ꢟꢡꢥ ꢟꢩ ꢧꢩ ꢦꢦ ꢤꢢ ꢞꢬ ꢲ ꢞꢟꢧ ꢬꢨꢭ ꢩ ꢥꢩ ꢦꢥꢞ ꢟꢳ ꢡꢠ ꢤꢬ ꢬ ꢪꢤ ꢢ ꢤꢣ ꢩꢥꢩ ꢢ ꢦꢮ
Copyright 2003, Texas Instruments Incorporated
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www.ti.com
SLOS408A − MARCH 2003 − REVISED DECEMBER 2003
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handledwith appropriate precautions. Failure to observe
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
proper handling and installation procedures can cause damage.
UNIT
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
Supply voltage, V
18 V
S
Input voltage, V
I
V
S
(2)
Output current, I
150 mA
4 V
O
Differential input voltage, V
ID
PACKAGE DISSIPATION RATINGS
Continuous power dissipation
See Dissipation Rating Table
(2)
(1)
Θ
JA
POWER RATING
Θ
JC
(3)
Maximum junction temperature, T
150°C
J
PACKAGE
(°C/W)
(°C/W)
T
A
≤ 25°C = 85°C
T
A
Maximum junction temperature, continuous
(4)
125°C
DBV (5)
D (8)
55
255.4
97.5
66.6
260
391 mW
1.02 W
1.5 W
156 mW
410 mW
600 mW
154 mW
685 mW
1.07 W
operation, longterm reliability, T
J
38.3
26.9
54.2
4.7
Operating free-air temperature range, T
−40°C to 85°C
−65°C to 150°C
A
D (14)
Storage temperature range, T
stg
DGK (8)
DGN (8)
PWP (14)
385 mW
1.71 W
2.67 W
Lead temperature
1,6 mm (1/16 inch) from case for 10 seconds
300°C
58.4
37.5
(1)
2.07
Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not implied.
The SN1050x may incorporate a PowerPAD on the underside of
the chip. This acts as a heatsink and must be connected to a
thermally dissipative plane for proper power dissipation. Failure
to do so may result in exceeding the maximum junction
temperature which could permanently damage the device. See TI
technical brief SLMA002 and SLMA004 for more information
about utilizing the PowerPAD thermally enhanced package.
The absolute maximum temperature under any condition is
limited by the constraints of the silicon process.
(1)
This data was taken using the JEDEC standard High-K test PCB.
(2)
Power rating is determined with a junction temperature of 125°C.
This is the point where distortion starts to substantially increase.
Thermalmanagement of the final PCB should strive to keep the
junctiontemperature at or below 125°C for best performance and
long term reliability.
(2)
RECOMMENDED OPERATING CONDITIONS
(3)
(4)
MIN
MAX
UNIT
Dual supply
1.35
9
Supply voltage,
The maximum junction temperature for continuous operation is
limited by package constraints. Operation above this
temperaturemay result in reduced reliability and/or lifetime of the
device
V
Single
supply
(V and V
)
2.7
18
S+ S−
Input common-mode
voltage range
V
S−
+ 1.1
V
S+
− 1.1
V
PACKAGE/ORDERING INFORMATION
PACKAGED DEVICES
TRANSPORT
MEDIA, QUANTITY
TEMPERATURE
PACKAGE TYPE
SINGLE
SN10501DBVT
SN10501DBVR
SN10501DGK
SN10501DGKR
SN10501DGN
SN10501DGNR
SN10501D
DUAL
−−−
TRIPLE
−−−
SOT−23−5
SOT−23−5
MSOP−8
Tape and Reel, 250
Tape and Reel, 3000
Rails, 75
−−−
−−−
SN10502DGK
SN10502DGKR
SN10502DGN
SN10502DGNR
SN10502D
SN10502DR
−−−
−−−
−−−
MSOP−8
Tape and Reel, 2500
Rails, 75
−−−
MSOP−8−PP
MSOP−8−PP
SOIC
−40°C to 85°C
−−−
Tape and Reel, 2500
Rails, 75
SN10503D
SN10503DR
SN10503PWP
SN10503PWPR
SN10501DR
−−−
SOIC
Tape and Reel, 2500
Rails, 75
TSSOP−14−PP
TSSOP−14−PP
−−−
−−−
Tape and Reel, 2000
2
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SLOS408A − MARCH 2003 − REVISED DECEMBER 2003
ELECTRICAL CHARACTERISTICS
V
S
= 5 V, R = 150 Ω, and G = 2 unless otherwise noted
L
TYP
OVER TEMPERATURE
PARAMETER
TEST CONDITIONS
0°C to
70°C
−40°C to
85°C
MIN/
MAX
25°C
25°C
UNITS
AC PERFORMANCE
G = 1, V = 100 mV
PP
170
100
12
MHz
MHz
MHz
MHz
MHz
MHz
V/µs
ns
Typ
Typ
Typ
Typ
Typ
Typ
Min
Typ
Typ
O
G = 2, V = 100 mV , R = 1 kΩ
PP
Small signal bandwidth
O
f
G = 10, V = 100 mV , R = 1 kΩ
PP
O
f
0.1 dB flat bandwidth
G = 2, V = 100 mV , R = 1.43 kΩ
PP
50
O
f
Gain bandwidth product
G > 10, f = 1 MHz, R = 1 kΩ
120
57
f
(1)
Full-power bandwidth
G = 2, V
=
=
2.5 Vpp
2.5 Vpp
2 Vpp
O
O
Slew rate
G = 2, V
900
25
Settling time to 0.1%
G = −2, V
=
O
O
Settling time to 0.01%
G = −2, V
=
2 Vpp
52
ns
Harmonic distortion
G = 2, V = 2 V , f = 5 MHz
O
PP
Second harmonic distortion
Third harmonic distortion
Differential gain (NTSC, PAL)
R
R
= 150 Ω
−78
−85
0.007
0.007
13
dBc
dBc
%
Typ
Typ
Typ
Typ
Typ
Typ
Typ
L
= 150 Ω
L
G = 2, R = 150 Ω
Differential phase (NTSC, PAL) G = 2, R = 150 Ω
°
Input voltage noise
Input current noise
Crosstalk (dual and triple only)
(1)
f = 1 MHz
nV/√Hz
pA/√Hz
dB
f = 1 MHz
0.8
f = 5 MHz Ch-to-Ch
−90
Full-power bandwidth = SR / 2πVpp
DC PERFORMANCE
Open-loop voltage gain (A
Input offset voltage
Input bias current
)
V
V
V
V
=
2 V
= 0 V
= 0 V
= 0 V
100
12
80
25
3
75
30
5
75
30
5
dB
mV
µA
nA
Min
Max
Max
Max
OL
O
CM
CM
CM
0.9
100
Input offset current
500
700
700
INPUT CHARACTERISTICS
Common-mode input range
Common-mode rejection ratio
Input resistance
−4 / 4
94
−3.9 / 3.9
70
V
Min
Min
Typ
Max
V
=
2 V
65
65
dB
MΩ
pF
CM
33
Input capacitance
Common-mode / differential
1 / 0.5
OUTPUT CHARACTERISTICS
R
R
R
R
= 150 Ω
= 499 Ω
= 10 Ω
= 10 Ω
−4.5 / 4.5
V
V
Typ
Min
Min
Min
Typ
L
L
L
L
Output voltage swing
−4.7 / 4.7 −4.5 / 4.5 −4.4 / 4.4 −4.4 / 4.4
Output current (sourcing)
Output current (sinking)
Output impedance
100
−100
0.09
92
88
88
mA
mA
Ω
−92
−88
−88
f = 1 MHz
POWER SUPPLY
Specified operating voltage
Maximum quiescent current
Power supply rejection ( PSRR)
5
14
75
9
18
62
9
20
60
9
22
60
V
Max
Max
Min
Per channel
mA
dB
3
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SLOS408A − MARCH 2003 − REVISED DECEMBER 2003
ELECTRICAL CHARACTERISTICS
V
S
= 5 V, R = 150 Ω, and G = 2 unless otherwise noted
L
TYP
OVER TEMPERATURE
PARAMETER
TEST CONDITIONS
0°C to
70°C
−40°C to
85°C
MIN/
MAX
25°C
25°C
UNITS
AC PERFORMANCE
G = 1, V = 100 mV
PP
170
100
12
MHz
MHz
MHz
MHz
MHz
MHz
V/µs
ns
Typ
Typ
Typ
Typ
Typ
Typ
Min
Typ
Typ
O
G = 2, V = 100 mV , R = 1.5 kΩ
PP
Small signal bandwidth
O
f
G = 10, V = 100 mV , R = 1.5 kΩ
PP
O
f
0.1 dB flat bandwidth
G = 2, V = 100 mV , R = 1.24 kΩ
PP
50
O
f
Gain bandwidth product
G > 10, f = 1 MHz, R = 1.5 kΩ
120
60
f
(1)
Full-power bandwidth
G = 2, V = 4 V step
O
Slew rate
G = 2, V = 4 V step
750
27
O
Settling time to 0.1%
Settling time to 0.01%
Harmonic distortion
Second harmonic distortion
Third harmonic distortion
Differential gain (NTSC, PAL)
Differential phase (NTSC, PAL)
Input voltage noise
G = −2, V = 2 V step
O
G = −2, V = 2 Vpp
48
ns
O
G = 2, V = 2 V , f = 5 MHz
O
PP
R
R
= 150 Ω
−82
−88
0.014
0.011
13
dBc
dBc
%
Typ
Typ
Typ
Typ
Typ
Typ
Typ
L
= 150 Ω
L
G = 2, R = 150 Ω
G = 2, R = 150 Ω
f = 1 MHz
°
nV/√Hz
pA/√Hz
dB
Input current noise
f = 1 MHz
0.8
Crosstalk (dual and triple only)
(1)
f = 5 MHz Ch-to-Ch
−90
Full-power bandwidth = SR / 2πVpp
DC PERFORMANCE
Open-loop voltage gain (A
Input offset voltage
Input bias current
)
V
V
V
V
= 1.5 V to 3.5 V
100
12
80
25
3
75
30
5
75
30
5
dB
mV
µA
nA
Min
Max
Max
Max
OL
O
= 2.5 V
= 2.5 V
= 2.5 V
CM
CM
CM
0.9
100
Input offset current
500
700
700
INPUT CHARACTERISTICS
Common-mode input range
Common-mode rejection ratio
Input resistance
1 / 4
96
1.1 / 3.9
70
V
Min
Min
Typ
Max
V
= 1.5 V to 3.5 V
65
65
dB
MΩ
pF
CM
33
Input capacitance
Common-mode / differential
1 / 0.5
OUTPUT CHARACTERISTICS
R
R
R
R
= 150 Ω
= 499 Ω
= 10 Ω
= 10 Ω
0.5 / 4.5
0.2 / 4.8
95
V
V
Typ
Min
Min
Min
Typ
L
L
L
L
Output voltage swing
0.3 / 4.7
85
0.4 / 4.6
80
0.4 / 4.6
80
Output current (sourcing)
Output current (sinking)
Output impedance
mA
mA
Ω
−95
−85
−80
−80
f = 1 MHz
0.09
POWER SUPPLY
Specified operating voltage
Maximum quiescent current
Power supply rejection ( PSRR)
5
18
15
62
18
17
60
18
19
60
V
Max
Max
Min
Per channel
12
70
mA
dB
4
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SLOS408A − MARCH 2003 − REVISED DECEMBER 2003
PIN ASSIGNMENTS
PACKAGE DEVICES
SN10501
DBV PACKAGE
(TOP VIEW)
SN10501
D, DGK, DGN PACKAGE
(TOP VIEW)
SN10502
D, DGK, DGN PACKAGE
(TOP VIEW)
1
2
3
5
V
S+
V
NC
OUT
NC
V
1
2
3
4
8
7
6
5
1OUT
1IN−
1IN+
V +
S
1
2
3
4
8
7
6
5
IN−
IN+
2OUT
2IN−
2IN+
S+
V
S−
V
OUT
V
S−
NC
V
4
IN−
S−
IN+
NC − No internal connection
SN10503
D, PWP PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
NC
NC
NC
2OUT
2IN−
2IN+
V +
V
S
S−
1IN+
1IN−
3IN+
3IN−
3OUT
8
1OUT
NC − No internal connection
TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
FIGURE
1 − 8
9, 10
11
Frequency response
Small signal frequency response
Large signal frequency response
Slew rate vs Output voltage step
Harmonic distortion vs Frequency
Voltage and current noise vs Frequency
Differential gain vs Number of loads
Differential phase vs Number of loads
Quiescent current vs Supply voltage
Output voltage vs Load resistance
Open-loop gain and phase vs Frequency
Rejection ratio vs Frequency
12, 13
14, 15
16
17, 18
19, 20
21
22
23
24
Rejection ratio vs Case temperature
25
Common-mode rejection ratio vs Input common-mode range
Output impedance vs Frequency
26, 27
28, 29
30
Crosstalk vs Frequency
Input bias and offset current vs Case temperature
31, 32
5
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SLOS408A − MARCH 2003 − REVISED DECEMBER 2003
FREQUENCY RESPONSE
FREQUENCY RESPONSE
FREQUENCY RESPONSE
8
6.3
6.2
8
7
V
= 2 V
O
PP
V
= 2 V
V
= 0.1 V
O
PP
O
PP
7
−3 dB at 99 MHz
−3 dB at 99 MHz
−0.1 dB at 49 MHz
6
5
6.1
6.0
6
5
V
= 0.1 V
O
PP
4
3
2
5.9
5.8
5.7
4
3
2
−3 dB at 99 MHz
V
= 2 V
PP
O
V
= 0.1 V
PP
O
−0.1 dB at 51 MHz
−3 dB at 99 MHz
1
0
5.6
5.5
1
0
Gain = 2
Gain = 2
Gain = 2
R
V
= 150 Ω to GND
R
V
= 150 Ω to GND
L
S
R
V
= 150 Ω to GND
L
S
L
S
=
5 V
=
5 V
=
5 V
−1
−2
5.4
5.3
−1
−2
R
F
= 1.43 kΩ
R
F
= 1.43 kΩ
R
F
= 301 Ω
100 k
1 M
10 M
100 M
1 G
100 k
1 M
10 M
100 M
1 G
100 k
1 M
10 M
100 M
1 G
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − Hz
Figure 1
Figure 2
Figure 3
FREQUENCY RESPONSE
FREQUENCY RESPONSE
FREQUENCY RESPONSE
6.3
6.3
6.2
8
7
V
= 2 V
O
PP
V
= 2 V
O
PP
6.2
−3 dB at 99 MHz
V
= 2 V
O
PP
−0.1 dB at 14 MHz
−0.1 dB at 58 MHz
6.1
6.0
6.1
6.0
6
5
V
= 0.1 V
O
PP
5.9
5.8
5.7
−3 dB at 99 MHz
5.9
5.8
5.7
4
3
2
V
= 0.1 V
PP
O
V
= 0.1 V
PP
O
−0.1 dB at 14 MHz
−0.1 dB at 48 MHz
5.6
5.5
5.6
5.5
1
0
Gain = 2
Gain = 2
Gain = 2
R
V
= 150 Ω to V /2
S
= 5 V
R
V
= 150 Ω to GND
R
V
= 150 Ω to V /2
= 5 V
L
S
L
S
L
S
S
=
5 V
5.4
5.3
5.4
5.3
−1
−2
R
F
= 1.24 kΩ
R
F
= 301 Ω
R
F
= 1.24 kΩ
100 k
1 M
10 M
100 M
1 G
100 k
1 M
10 M
100 M
1 G
100 k
1 M
10 M
100 M
1 G
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − Hz
Figure 4
Figure 5
Figure 6
FREQUENCY RESPONSE
FREQUENCY RESPONSE
FREQUENCY RESPONSE
8
7
8
7
6.3
6.2
V
= 2 V
O
PP
−3 dB at 89 MHz
V
= 0.1 V
Gain = 2
O
PP
−0.1 dB at 16 MHz
6
5
6
5
6.1
6.0
R
R
V
V
= 150 Ω
= 1 kΩ
= 100 mV
L
V
= 0.1 V
O
PP
4
3
2
4
3
5.9
5.8
5.7
F
O
S
−3 dB at 84 MHz
PP
V
= 2 V
O
PP
=
5 V
−0.1 dB at 16 MHz
2
1
0
1
5.6
5.5
Gain = 2
Gain = 2
R
L
= 150 Ω to V /2
0
S
R
L
= 150 Ω to V /2
S
Gain = 1
V
= 5 V
S
V
= 5 V
S
−1
−2
−1
−2
5.4
5.3
R
F
= 301Ω
R
F
= 301 Ω
100 k
1 M
10 M
100 M
1 G
100 k
1 M
10 M
100 M
1 G
100 k
1 M
10 M
100 M
1 G
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − Hz
Figure 7
Figure 8
Figure 9
6
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SLOS408A − MARCH 2003 − REVISED DECEMBER 2003
SLEW RATE
vs
OUTPUT VOLTAGE STEP
FREQUENCY RESPONSE
FREQUENCY RESPONSE
1200
8
7
6
5
4
3
2
8
Gain = 2
V
= 5 V
7
6
5
4
3
2
S
R
R
V
= 150 Ω
= 1 kΩ
= 5 V
Gain = 2
L
F
S
1000
800
600
400
Rise
R
R
V
V
= 499 Ω
= 1.5 kΩ
= 100 mV
= 5 V
L
V
= 5 V
S
Fall
F
O
S
PP
Gain = 2
1
0
R
R
V
V
= 150 Ω
= 1 kΩ
L
F
O
S
200
0
= 2 V
PP
5 V
Gain = 1
1
0
=
−1
−2
100 k
1 M
10 M
100 M
1 G
0
1
2
3
4
5
6
7
8
100 k
1 M
10 M
100 M
1 G
f − Frequency − Hz
V
− Output Voltage Step − V
f − Frequency − Hz
O
Figure 10
Figure 11
Figure 12
HARMONIC DISTORTION
SLEW RATE
vs
OUTPUT VOLTAGE STEP
HARMONIC DISTORTION
vs
vs
FREQUENCY
FREQUENCY
0
0
800
700
Gain = 2
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
Gain = 2
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
Gain = 2
R
R
V
= 150 Ω
= 1 kΩ
= 5 V
R
V
= 150 Ω
= 2 V
L
F
S
R
L
V
= 150 Ω
= 2 V
PP
= 5 V
L
O
S
Fall
PP
O
S
600
500
400
300
200
100
0
V
= 5 V
V
Rise
HD2
HD3
HD2
HD3
10
0.1
1
100
0
0.5
1
1.5
2
2.5
3
3.5
4
100
0.1
1
10
f − Frequency − MHz
f − Frequency − MHz
V
− Output Voltage Step − V
O
Figure 13
Figure 14
Figure 15
DIFFERENTIAL PHASE
vs
NUMBER OF LOADS
DIFFERENTIAL GAIN
vs
NUMBER OF LOADS
VOLTAGE AND CURRENT NOISE
vs
FREQUENCY
0.4
0.20
0.18
0.16
10
100
Gain = 2
R = 1.5 kΩ
40 IRE − NTSC
Worst Case 100
Gain = 2
R = 1.5 kΩ
40 IRE − NTSC
Worst Case 100 IRE Ramp
0.35
0.3
f
f
0.14 IRE Ramp
0.25
0.2
V
n
0.12
0.10
0.08
0.06
0.04
V
= 5 V
S
10
1
V
= 5 V
S
0.15
0.1
I
n
V
= 5 V
S
V
3
= 5 V
S
0.05
0
0.02
0
0.1
10 M
1
0
1
2
3
4
5
0
1
2
4
5
1 k
10 k
100 k
1 M
Number of Loads − 150 Ω
Number of Loads − 150 Ω
f − Frequency − Hz
Figure 16
Figure 17
Figure 18
7
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SLOS408A − MARCH 2003 − REVISED DECEMBER 2003
DIFFERENTIAL PHASE
vs
NUMBER OF LOADS
DIFFERENTIAL GAIN
vs
NUMBER OF LOADS
QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
0.4
0.35
0.3
22
20
18
16
14
12
10
0.20
Gain = 2
R = 1.5 kΩ
40 IRE − PAL
Worst Case 100 IRE Ramp
Gain = 2
R = 1.5 kΩ
40 IRE − PAL
Worst Case 100 IRE Ramp
0.18
f
f
T
A
= 85°C
0.16
0.14
0.12
0.10
0.08
0.06
0.04
T
A
= 25°C
0.25
0.2
V
= 5 V
S
V
= 5 V
S
0.15
0.1
T
A
= −40°C
8
6
4
2
0
V
= 5 V
S
V
=
5 V
4
S
0.05
0
0.02
0
0
1
2
3
4
5
0
1
2
3
5
1.5
2
2.5
3
3.5
4
4.5
5
Number of Loads − 150 Ω
Number of Loads − 150 Ω
V
− Supply Voltage − V
S
Figure 19
Figure 20
Figure 21
OUTPUT VOLTAGE
vs
OPEN-LOOP GAIN AND PHASE
REJECTION RATIO
vs
vs
LOAD RESISTANCE
FREQUENCY
FREQUENCY
110
100
90
80
70
60
50
40
30
20
10
220
100
5
V
= 5 V, 5 V, and 3.3 V
200
180
160
140
120
100
80
S
V
=
5 V, 5 V,
S
4
3
90
80
70
60
50
40
30
and 3.3 V
2
1
CMMR
T
= −40 to 85°C
A
PSRR
0
−1
−2
−3
60
40
20
10
0
20
−4
−5
0
0
−10
−20
10
100
1 k
10 k
100 1 k 10 k 100 k 1 M 10 M 100 M 1 G
0.1
1
10
100
R
L
− Load Resistance − Ω
f − Frequency − Hz
f − Frequency − MHz
Figure 22
Figure 23
Figure 24
COMMON-MODE REJECTION RATIO
vs
REJECTION RATIO
vs
CASE TEMPERATURE
COMMON-MODE REJECTION RATIO
vs
INPUT COMMON-MODE RANGE
INPUT COMMON-MODE RANGE
100
100
100
V
=
5 V, 5 V, and 3.3 V
CMMR
S
90
80
70
60
50
40
30
20
90
80
70
60
50
40
30
20
10
0
90
80
PSRR
70
60
50
40
V
= 5 V
S
V
T
A
= 5 V
= 25°C
S
T
A
= 25°C
10
0
−40−30−20−10
0 10 20 30 40 50 60 70 80 90
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5 5
−6
−4
−2
0
2
4
6
V
− Input Common-Mode Voltage Range − V
T
C
− Case Temperature − °C
ICR
V
− Input Common-Mode Voltage Range − V
ICR
Figure 26
Figure 25
Figure 27
8
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SLOS408A − MARCH 2003 − REVISED DECEMBER 2003
CROSSTALK
vs
OUTPUT IMPEDANCE
OUTPUT IMPEDANCE
vs
vs
FREQUENCY
FREQUENCY
FREQUENCY
120
100
10
100
10
Gain = 2
Gain = 2
Crosstalk all Channels
R
L
= 150 Ω to GND
R
L
= 150 Ω to V /2
S
100
V
V
= 2 V
=
V
V
= 2 V
= 5 V
O
S
PP
5 V
O
S
PP
80
60
R
F
= 301 Ω
R
F
= 301 Ω
1
1
40
V
=
5 V, 5 V, and 3.3 V
S
Gain = 1
0.1
0.1
R
L
= 150 Ω
20
0
V
= −1 dB
IN
T = 25°C
A
R
F
= 1.43 kΩ
R
= 1.24 kΩ
F
0.01
100 k
0.01
100 k
100 k
1 M
10 M
100 M
1 G
1 M
10 M
100 M
1 G
1 M
10 M
100 M
1 G
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − Hz
Figure 28
Figure 29
Figure 30
INPUT BIAS AND OFFSET CURRENT
INPUT BIAS AND OFFSET CURRENT
vs
vs
CASE TEMPERATURE
CASE TEMPERATURE
0.9
0.88
0.86
5
0.84
0.82
10
5
V
=
5 V
V
= 5 V
S
S
0
I
OS
I
OS
−5
−10
0
0.8
I
IB+
I
IB+
0.78
−5
0.84
0.82
I
IB−
−10
−15
−15
−20
0.76
0.74
0.8
0.78
0.76
I
IB−
−25
−30
0.72
0.7
−20
−25
−40−30−20−10
0 10 20 30 40 50 60 70 80 90
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
Case Temperature − °C
Case Temperature − °C
Figure 31
Figure 32
9
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SLOS408A − MARCH 2003 − REVISED DECEMBER 2003
APPLICATION INFORMATION
5 V
+V
S
+
HIGH-SPEED OPERATIONAL AMPLIFIERS
100 pF
0.1 µF 6.8 µF
50 Ω Source
49.9 Ω
+
V
I
The SN1050x operational amplifiers are a family of single,
dual, and triple rail-to-rail output voltage feedback
amplifiers. The SN1050x family combines both a high slew
rate and a rail-to-rail output stage.
V
O
_
499 Ω
R
f
1.3 kΩ
1.3 kΩ
R
g
0.1 µF 6.8 µF
+
Applications Section Contents
100 pF
−V
S
−5 V
D
D
D
D
D
D
D
D
D
D
D
Wideband, Noninverting Operation
Wideband, Inverting Gain Operation
Video Drive Circuits
Single Supply Operation
Power Supply Decoupling Techniques and
Recommendations
Active Filtering With the SN1050x
Driving Capacitive Loads
Board Layout
Thermal Analysis
Additional Reference Material
Mechanical Package Drawings
Figure 33. Wideband, Noninverting Gain
Configuration
WIDEBAND, INVERTING OPERATION
Since the SN1050x family are general-purpose, wideband
voltage-feedback amplifiers, several familiar operational
amplifier applications circuits are available to the designer.
Figure 34 shows a typical inverting configuration where
the input and output impedances and noise gain from
Figure 33 are retained in an inverting circuit configuration.
Inverting operation is one of the more common
requirements and offers several performance benefits.
The inverting configuration shows improved slew rates
and distortion due to the pseudo-static voltage maintained
on the inverting input.
WIDEBAND, NONINVERTING OPERATION
5 V
+V
S
+
The SN1050x is a family of unity gain stable rail-to-rail
output voltage feedback operational amplifiers designed
to operate from a single 3-V to 15-V power supply.
100 pF
0.1 µF
6.8 µF
+
V
R
649 Ω
O
T
C
T
_
Figure 33 is the noninverting gain configuration of 2 V/V
used to demonstrate the typical performance curves.
0.1 µF
499 Ω
50 Ω Source
R
R
g
f
Voltage feedback amplifiers, unlike current feedback
designs, can use a wide range of resistors values to set
their gain with minimal impact on their stability and
frequency response. Larger-valued resistors decrease the
loading effect of the feedback network on the output of the
amplifier, but this enhancement comes at the expense of
additional noise and potentially lower bandwidth.
Feedback resistor values between 1 kΩ and 2 kΩ are
recommended for most situations.
V
1.3 kΩ
1.3 kΩ
I
R
M
0.1 µF
6.8 µF
52.3 Ω
+
100 pF
−V
S
−5 V
Figure 34. Wideband, Inverting Gain
Configuration
10
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+V
S
In the inverting configuration, some key design
considerations must be noted. One is that the gain resistor
(Rg) becomes part of the signal channel input impedance.
If the input impedance matching is desired (which is
beneficial whenever the signal is coupled through a cable,
twisted pair, long PC board trace, or other transmission
line conductors), Rg may be set equal to the required
termination value and Rf adjusted to give the desired gain.
However, care must be taken when dealing with low
inverting gains, as the resultant feedback resistor value
can present a significant load to the amplifier output. For
an inverting gain of 2, setting Rg to 49.9 Ω for input
matching eliminates the need for RM but requires a 100-Ω
feedback resistor. This has an advantage of the noise gain
becoming equal to 2 for a 50-Ω source impedance—the
same as the noninverting circuit in Figure 33. However, the
amplifier output now sees the 100-Ω feedback resistor in
parallel with the external load. To eliminate this excessive
loading, it is preferable to increase both Rg and Rf, values,
as shown in Figure 34, and then achieve the input
matching impedance with a third resistor (RM) to ground.
The total input impedance becomes the parallel
combination of Rg and RM.
50 Ω Source
+
_
V
I
V
R
49.9 Ω
O
T
499 Ω
+V
2
S
R
f
1.3 kΩ
R
g
1.3 kΩ
+V
2
S
R
f
1.3 kΩ
V
S
50 Ω Source
R
g
_
+
V
I
1.3 kΩ
T
V
52.3 Ω
R
O
499 Ω
+V
+V
2
S
S
2
Figure 35. DC-Coupled Single Supply Operation
VIDEO DRIVE CIRCUITS
The last major consideration to discuss in inverting
amplifier design is setting the bias current cancellation
resistor on the noninverting input. If the resistance is set
equal to the total dc resistance looking out of the inverting
terminal, the output dc error, due to the input bias currents,
is reduced to (input offset current) multiplied by Rf in
Figure 34, the dc source impedance looking out of the
inverting terminal is 1.3 kΩ || (1.3 kΩ + 25.6 Ω) = 649 Ω.
To reduce the additional high-frequency noise introduced
by the resistor at the noninverting input, and power-supply
feedback, RT is bypassed with a capacitor to ground.
Most video distribution systems are designed with 75-Ω
series resistors to drive a matched 75-Ω cable. In order to
deliver a net gain of 1 to the 75-Ω matched load, the
amplifier is typically set up for a voltage gain of +2,
compensating for the 6-dB attenuation of the voltage
divider formed by the series and shunt 75-Ω resistors at
either end of the cable. The circuit shown in Figure 36
applies to this requirement. Both the gain flatness and the
differential gain / phase performance of the SN1050x
provides exceptional results in video distribution
applications.
V
SINGLE SUPPLY OPERATION
S+
The SN1050x family is designed to operate from a single
3-V to 15-V power supply. When operating from a single
power supply, care must be taken to ensure the input
signal and amplifier are biased appropriately to allow for
the maximum output voltage swing. The circuits shown in
Figure 35 demonstrate methods to configure an amplifier
in a manner conducive for single supply operation.
+
10 µF
0.1 µF
Video In
5
3
4
+
75 Ω
1
75 Ω
−
V
O
2
75 Ω
+
10 µF
V
S−
0.1 µF
1.43 kΩ
1.43 kΩ
Figure 36. Cable Drive Application
11
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Differential gain and phase measure the change in overall
small-signal gain and phase for the color subcarrier
frequency (3.58 MHz in NTSC systems) vs changes in the
large-signal output level (which represents luminance
information in a composite video signal). The SN1050x,
with the typical 150-Ω load of a single matched video
cable, shows less than 0.007% / 0.007° differential
gain/phase errors over the standard luminance range for
the output voltage range will be the limiting factor in the
total system and both specifications must be taken into
account when designing a system.
1.24 kΩ
1.24 kΩ
5 V
Output Range
= 2 V to 4.5 V
V
Range
O
a
positive video (negative sync) signal. Similar
= 1 V to 2.25 V
75 Ω
Input Range
= 1 V to 2.25 V
−
+
performance is observed for negative video signals. In
practice, similar performance is achieved even with three
video loads as shown in Figure 37 due to the linear
high-frequency output impedance of the SN1050x.
75 Ω
R
T
V
S+
75 Ω
Figure 38. DC-Coupled Single-Supply Video
Amplifier
0.1 µF
V
O
+
10 µF
75 Ω
In most systems, this may be acceptable because most
receivers are ac-coupled and set the blank level to the
desired system value, typically 0 V (0-IRE). But, to ensure
full compatibility with any system, it is often desirable to
place an ac-coupling capacitor on the output as shown in
Figure 39. This eliminates the dc-bias voltage appearing
at the amplifier output. To minimize field tilt, the size of this
capacitor is typically 470 µF, although values as small as
220 µF have been utilized with acceptable results.
Video In
5
3
4
+
75 Ω
75 Ω
1
−
V
O
2
75 Ω
75 Ω
75 Ω
1.43 kΩ
1.43 kΩ
0.1 µF
10 µF
V
O
V
S−
+
1.24 kΩ
1.24 kΩ
5 V
Output Range
= 2 V to 4.5 V
Figure 37. Video Distribution
V
Range
O
= 0 V to 1.25V
75 Ω
Input Range
= 1 V to 2.25 V
−
+
The above circuit is suitable for driving video cables,
provided that the length does not exceed a few feet. If
longer cables are driven, the gain of the SN1050x can be
increased to accommodate cable drops.
470 µF
75 Ω
R
T
Configuring the SN1050x for single supply video
applications is easily done. But, attention must be made to
the bias voltages at the input and output to ensure the
system works as desired. Unlike some video amplifiers,
the input common-mode voltage range of the SN1050x
amplifiers do not include the negative power supply, but
rather it is about 1-V from each power supply. For split
supply configurations, this is very beneficial. But for
single-supply systems, there are some design constraints
that must be adhered to.
Figure 39. AC-Coupled Output Single-Supply
Video Amplifier
In some systems, the physical size and sometimes cost of
a 470-µF capacitor can be prohibitive. One way to
circumvent this issue is to utilize two smaller capacitors in
a feedback configuration as shown in Figure 40. This is
commonly known as SAG correction. This circuit
increases the gain of the amplifier up to 3 V/V at low
frequencies to counteract the increased impedance of the
capacitor placed at the amplifier output. One issue that
must be resolved is the gain at low frequencies is typically
limited by the power-supply voltage and the output swing
of the amplifier. Therefore, it is possible to saturate the
amplifier at these low frequencies if full analysis is not done
on this system which includes both input and output
requirements.
Figure 38 shows a single supply video configuration
illustrating the dc bias voltages acceptable for the
SN1050x. The lower end of the input common-mode range
is specified as 1 V. While the upper end is limited to 4 V with
the 5-V supply shown, the output range and gain of 2 limits
the highest acceptable input voltage to 4.5 V / 2 = 2.25 V.
The 4.5-V output is what is typically expected with a 150-Ω
load. It is easily seen that the input voltage range and/or
12
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SLOS408A − MARCH 2003 − REVISED DECEMBER 2003
1.24 kΩ 1.24 kΩ
5 V
68 µF
1.24 kΩ
1.24 kΩ
5 V
22 µF
Output Range
= 0.5 V to 4.5V
1.24
kΩ
5 V
V
Range
O
V
Range
= 0 V to 1.25V
O
75 Ω
Input Range
= 1 V to 2.25 V
DAC Output
= 0 V to 2V
−
+
= 0 V to 2V
75 Ω
−
+
3.01 kΩ
22 µF
470 µF
75 Ω
47 µF
75 Ω
R
Output Range
= 2 V to 4.5 V
T
3.01 kΩ
Input Range
= 1.5 V to 3.5V
Figure 40. AC-Coupled SAG Corrected Output
Single-Supply Video Amplifier
Figure 42. AC-Coupled Wide Output Swing
Single-Supply Video Amplifier
Many times the output of the video encoder or DAC does
not have the capability to output the 1-V to 2.25-V range,
but rather a 0-V to 1.25-V range. In this instance, the signal
must be ac-coupled to the amplifier input as shown in
Figure 41. Note that it does not matter what the voltage
output of the DAC is, but rather the voltage swing should
1.24 kΩ
1.24 kΩ
5 V
2.5 V
Output Range
= 0.5 V to 4.5V
5 V
V
Range
O
= 0 V to 2V
DAC Output
= 0 V to 2V
75 Ω
470 µF
−
+
3.01 kΩ
be kept less than 1.25 VPP
.
47 µF
75 Ω
3.01 kΩ
Input Range
= 1.5 V to 3.5V
1.24 kΩ
1.24 kΩ
5 V
Output Range
= 2 V to 4.5 V
Figure 43. AC-Coupled Wide Output Swing
Single-Supply Video Amplifier Utilizing Voltage
Reference
5 V
V
Range
O
= 0 V to 1.25V
DAC Output
75 Ω
470 µF
−
+
4.64 kΩ
= 0 V to 1.25V
Another configuration that can be beneficial is to utilize the
amplifier in an inverting configuration is shown in
Figure 44.
47 µF
75 Ω
2.26 kΩ
Input Range
= 1 V to 2.25V
68 µF
1.24 kΩ
2.49 kΩ
5 V
Figure 41. AC-Coupled Input and Output
Single-Supply Video Amplifier
Output Range
= 0.5 V to 4.5V
DAC Output
= 0 V to 2V
5 V
V
Range
O
= 0 V to 2V
75 Ω
−
+
10 kΩ
To have even more dynamic range at the output, the
dc-bias at the output should be centered around 2.5 V for
the 5-V system shown. But, to have a wide output range
the input must also have a wide range and should be
centered around 2.5 V. The best ways to accomplish this
is to either ac-couple the gain resistor or bias it at 2.5 V
utilizing a reference supply as shown in Figure 42 and
Figure 43.
470 µF
10 µF
10 kΩ
75 Ω
Input = 2.5 V
Figure 44. Inverting AC-Coupled Wide Output
Swing Single-Supply Video Amplifier
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SLOS408A − MARCH 2003 − REVISED DECEMBER 2003
Power Supply Decoupling Techniques and
Recommendations
APPLICATION CIRCUITS
Active Filtering With the SN1050x
Power supply decoupling is a critical aspect of any
high-performance amplifier design process. Careful
decoupling provides higher quality ac performance (most
notably improved distortion performance). The following
guidelines ensure the highest level of performance.
High-frequency active filtering with the SN1050x is
achievable due to the amplifier’s high slew rate, wide
bandwidth, and voltage feedback architecture. Several
options are available for high-pass, low-pass, bandpass,
and bandstop filters of varying orders. A simple two-pole
low pass filter is presented here as an example, with two
poles at 25 MHz.
1. Place decoupling capacitors as close to the power
supply inputs as possible, with the goal of minimizing
the inductance of the path from ground to the power
supply.
4.7 pF
50 Ω Source
1.3 kΩ
2. Placement priority should put the smallest valued
capacitors closest to the device.
V
I
1.3 kΩ
52.3 Ω
5 V
3. Use of solid power and ground planes is
recommended to reduce the inductance along power
supply return current paths, with the exception of the
areas underneath the input and output pins.
_
49.9 Ω
V
O
+
33 pF
4. Recommended values for power supply decoupling
include a bulk decoupling capacitor (6.8 to 22 µF), a
mid-range decoupling capacitor (0.1 µF) and a high
frequency decoupling capacitor (1000 pF) for each
supply. A 100 pF capacitor can be used across the
supplies as well for extremely high frequency return
currents, but often is not required.
−5 V
Figure 45. A Two-Pole Active Filter With Two
Poles Between 90 MHz and 100 MHz
Driving Capacitive Loads
One of the most demanding, and yet very common, load
conditions for an op amp is capacitive loading. Often, the
capacitive load is the input of an A/D converter, including
additional external capacitance, which may be
recommended to improve A/D linearity. A high-speed, high
open-loop gain amplifier like the SN1050x can be very
susceptible to decreased stability and closed-loop
response peaking when a capacitive load is placed directly
on the output pin. When the amplifier’s open-loop output
resistance is considered, this capacitive load introduces
an additional pole in the signal path that can decrease the
phase margin. When the primary considerations are
frequency response flatness, pulse response fidelity, or
distortion, the simplest and most effective solution is to
isolate the capacitive load from the feedback loop by
inserting a series isolation resistor between the amplifier
output and the capacitive load. This does not eliminate the
pole from the loop response, but rather shifts it and adds
a zero at a higher frequency. The additional zero acts to
cancel the phase lag from the capacitive load pole, thus
increasing the phase margin and improving stability.
14
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SLOS408A − MARCH 2003 − REVISED DECEMBER 2003
add a pole and/or a zero below 400 MHz that can
effect circuit operation. Keep resistor values as low as
possible, consistent with load driving considerations.
It has been suggested that a good starting point for
design is to set the Rf to 1.3 kΩ for low-gain,
noninverting applications. Doing this automatically
keeps the resistor noise terms low, and minimizes the
effect of their parasitic capacitance.
BOARD LAYOUT
Achieving optimum performance with a high frequency
amplifier like the SN1050x requires careful attention to
board layout parasitics and external component types.
Recommendations that will optimize performance include:
1. Minimize parasitic capacitance to any ac ground
for all of the signal I/O pins. Parasitic capacitance on
the output and inverting input pins can cause
instability: on the noninverting input, it can react with
the source impedance to cause unintentional band
limiting. To reduce unwanted capacitance, a window
around the signal I/O pins should be opened in all of
the ground and power planes around those pins.
Otherwise, ground and power planes should be
unbroken elsewhere on the board.
4. Connections to other wideband devices on the
board may be made with short direct traces or
through onboard transmission lines. For short
connections, consider the trace and the input to the
next device as a lumped capacitive load. Relatively
wide traces (50 mils to 100 mils) should be used,
preferably with ground and power planes opened up
around them. Estimate the total capacitive load and
set RISO from the plot of recommended RISO vs
Capacitive Load. Low parasitic capacitive loads
(<4 pF) may not need an R(ISO), since the SN1050x is
nominally compensated to operate with a 2-pF
parasitic load. Higher parasitic capacitive loads
without an R(ISO) are allowed as the signal gain
increases (increasing the unloaded phase margin). If
a long trace is required, and the 6-dB signal loss
intrinsic to a doubly-terminated transmission line is
2. Minimize the distance (< 0.25”) from the power
supply pins to high frequency 0.1-µF decoupling
capacitors. At the device pins, the ground and power
plane layout should not be in close proximity to the
signal I/O pins. Avoid narrow power and ground traces
to minimize inductance between the pins and the
decoupling capacitors. The power supply connections
should always be decoupled with these capacitors.
Larger (2.2-µF to 6.8-µF) decoupling capacitors,
effective at lower frequency, should also be used on
the main supply pins. These may be placed somewhat
farther from the device and may be shared among
several devices in the same area of the PC board.
acceptable, implement
a
matched impedance
transmission line using microstrip or stripline
techniques (consult an ECL design handbook for
microstrip and stripline layout techniques). A 50-Ω
environment is normally not necessary onboard, and
in fact a higher impedance environment improves
distortion as shown in the distortion versus load plots.
With a characteristic board trace impedance defined
based on board material and trace dimensions, a
matching series resistor into the trace from the output
of the SN1050x is used as well as a terminating shunt
resistor at the input of the destination device.
Remember also that the terminating impedance is the
parallel combination of the shunt resistor and the input
impedance of the destination device: this total
effective impedance should be set to match the trace
impedance. If the 6-dB attenuation of a doubly
terminated transmission line is unacceptable, a long
trace can be series-terminated at the source end only.
Treat the trace as a capacitive load in this case and set
the series resistor value as shown in the plot of R(ISO)
vs Capacitive Load. This setting does not preserve
signal integrity or a doubly-terminated line. If the input
impedance of the destination device is low, there is
some signal attenuation due to the voltage divider
formed by the series output into the terminating
impedance.
3. Careful selection and placement of external
components preserves the high frequency
performance of the SN1050x. Resistors should be a
very low reactance type. Surface-mount resistors
work best and allow a tighter overall layout. Metal-film
and carbon composition, axially-leaded resistors can
also provide good high frequency performance.
Again, keep their leads and PC board trace length as
short as possible. Never use wire wound type
resistors in a high frequency application. Since the
output pin and inverting input pin are the most
sensitive to parasitic capacitance, always position the
feedback and series output resistor, if any, as close as
possible to the output pin. Other network components,
such as noninverting input termination resistors,
should also be placed close to the package. Where
double-side component mounting is allowed, place
the feedback resistor directly under the package on
the other side of the board between the output and
inverting input pins. Even with a low parasitic
capacitance shunting the external resistors,
excessively high resistor values can create significant
time constants that can degrade performance. Good
axial metal-film or surface-mount resistors have
approximately 0.2 pF in shunt with the resistor. For
resistor values > 2.0 kΩ, this parasitic capacitance can
15
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SLOS408A − MARCH 2003 − REVISED DECEMBER 2003
1.5
5. Socketing a high speed part like the SN1050x is
not recommended. The additional lead length and
pin-to-pin capacitance introduced by the socket can
create a troublesome parasitic network which can
make it almost impossible to achieve a smooth, stable
frequency response. Best results are obtained by
soldering the SN1050x onto the board.
1.25
8-Pin D Package
1
0.75
5-Pin DBV Package
0.5
0.25
0
THERMAL ANALYSIS
The SN1050x family of devices does not incorporate
automatic thermal shutoff protection, so the designer must
take care to ensure that the design does not violate the
absolute maximum junction temperature of the device.
Failure may result if the absolute maximum junction
temperature of 150_ C is exceeded.
−40
−20
0
20
40
60
80
T
− Ambient Temperature − °C
A
θ
θ
T
= 170°C/W for 8-Pin SOIC (D)
JA
= 324.1°C/W for 5-Pin SOT−23 (DBV)
JA
= 150°C, No Airflow
J
Figure 46. Maximum Power Dissipation vs
Ambient Temperature
The thermal characteristics of the device are dictated by
the package and the PC board. Maximum power
dissipation for a given package can be calculated using the
following formula.
When determining whether or not the device satisfies the
maximum power dissipation requirement, it is important to
consider not only quiescent power dissipation, but also
dynamic power dissipation. Often maximum power
dissipation is difficult to quantify because the signal pattern
is inconsistent, but an estimate of the RMS power
dissipation can provide visibility into a possible problem.
Tmax–TA
qJA
PDmax
+
where:
P
T
is the maximum power dissipation in the amplifier (W).
is the absolute maximum junction temperature (°C).
Dmax
max
T is the ambient temperature (°C).
A
θ
θ
= θ + θ
JC CA
JA
is the thermal coefficient from the silicon junctions to the
JC
case (°C/W).
θ
is the thermal coefficient from the case to ambient air
CA
(°C/W).
16
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