SN3257QPWRQ1 [TI]
具有 1.8V 逻辑电平和断电保护的汽车类 5V、2:1 (SPDT)、4 通道开关 | PW | 16 | -40 to 125;
| 型号： | SN3257QPWRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 1.8V 逻辑电平和断电保护的汽车类 5V、2:1 (SPDT)、4 通道开关 | PW | 16 | -40 to 125 开关 光电二极管 |
| 文件： | 总38页 (文件大小：1889K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN3257-Q1
ZHCSK05D –JULY 2019 –REVISED OCTOBER 2022
SN3257-Q1 具有1.8V 逻辑电平的汽车类5V 低传播延迟、2:1 (SPDT)
4 通道开关
1 特性
3 说明
• 提供功能安全
SN3257-Q1 是一款汽车级互补金属氧化物半导体
(CMOS) 开关，支持高速信号，具有低传播延迟。
SN3257-Q1 提供具有 4 个通道的 2:1 (SPDT) 开关配
置，非常适合 SPI 和 I2S 等各通道协议。此器件可在
源极（SxA、SxB）和漏极 (Dx) 引脚上支持双向模拟
– 可帮助进行功能安全系统设计的文档
• 符合面向汽车应用的AEC-Q100 标准
– 温度等级1：-40°C 至+125°C，TA
• 宽电源电压范围：1.5V 至5.5V
• 低传播延迟：78 ps
和数字信号，并且能够传递高于电源电压（最高 VDD
2）的信号，最大输入和输出电压为5.5V。
x
• 低导通电阻：5Ω
• 高带宽：2 GHz
• 双向信号路径
• 支持超出电源的输入电压
• 兼容1.8V 逻辑电平
SN3257-Q1 具有一个低电平有效 EN 引脚，用于同时
启用和禁用所有通道。当EN 引脚为低电平时，会根据
SEL 引脚的状态选择两个开关路径之一。
• 逻辑引脚上带有集成下拉电阻器
• 失效防护逻辑
• 高达3.6V 信号的断电保护
SN3257-Q1 的信号路径上高达 3.6V 的关断保护功能
可在移除电源电压 (VDD = 0V) 时提供隔离。如果没有
该保护功能，开关可通过内部 ESD 二极管为电源轨进
行反向供电，从而对系统造成潜在损坏。
2 应用
失效防护逻辑电路允许在施加电源引脚上的电压之前，
先施加逻辑控制引脚上的电压，从而保护器件免受潜在
的损害。两个逻辑控制输入都具有兼容 1.8V 逻辑的阈
值，可确保 TTL 和CMOS 逻辑兼容性。逻辑引脚上带
有集成下拉电阻器，无需外部组件，可减小系统尺寸、
降低系统成本。
• SPI 多路复用
• I2S 多路复用
• eSIM 多路复用
• eMMC 多路复用
• 闪存存储器共享
• 电池管理系统(BMS)
• 远程信息处理控制单元(TCU)
• 智能远程信息处理网关
• 后座娱乐系统
• 数字驾驶舱处理单元
• 汽车音响主机
• 汽车导航
封装信息(1)
封装尺寸（标称值）
器件型号
封装
PW (TSSOP, 16)
5.00mm × 4.40mm
SN3257-Q1
DYY (SOT-23-THIN,16) 4.20mm × 2.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
• ADAS 域控制器
• 环视系统ECU
• 车载充电器(OBC) 和无线充电器
SN3257-Q1
S1A
D1
S1B
S2A
D2
S2B
VI/O
VDD
VDD
S3A
0.1µF
D3
S3B
VDD
Processor / MCU /
External Header #1
S4A
D4
S4B
S1A
S2A
S3A
S4A
LOGIC CONTROL*
SPI / eSIM / eMMC
Device
PORT
DEBUG,
SPI, GPIO
1.8V
Logic
I/O
SEL
EN
D1
MISO / CMD / GPIO
MOSI / CLK / GPIO
*Internal 6MO Pull-Down on Logic Pins
D2
D3
D4
方框图
Processor / MCU /
External Header #2
SCLK / DAT0 / GPIO
SS / DAT1 / GPIO
S1B
S2B
S3B
S4B
PORT
DEBUG,
SPI, GPIO
1.8V
Logic
I/O
SEL
EN
1.8V Control Logic
From Processor / MCU
GND
应用示例
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCDS411
SN3257-Q1
ZHCSK05D –JULY 2019 –REVISED OCTOBER 2022
www.ti.com.cn
Table of Contents
7.12 Capacitance............................................................16
7.13 Off Isolation.............................................................17
7.14 Channel-to-Channel Crosstalk................................17
7.15 Bandwidth............................................................... 19
8 Detailed Description......................................................20
8.1 Overview...................................................................20
8.2 Functional Block Diagram.........................................20
8.3 Feature Description...................................................20
8.4 Device Functional Modes..........................................22
9 Application and Implementation..................................23
9.1 Application Information............................................. 23
9.2 Typical Application.................................................... 23
10 Power Supply Recommendations..............................24
11 Layout...........................................................................25
11.1 Layout Guidelines................................................... 25
11.2 Layout Example...................................................... 26
12 Device and Documentation Support..........................27
12.1 Documentation Support.......................................... 27
12.2 接收文档更新通知................................................... 27
12.3 支持资源..................................................................27
12.4 Trademarks.............................................................27
12.5 Electrostatic Discharge Caution..............................27
12.6 术语表..................................................................... 27
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Dynamic Characteristics............................................. 6
6.7 Timing Requirements..................................................7
7 Parameter Measurement Information.......................... 11
7.1 On-Resistance.......................................................... 11
7.2 Off-Leakage Current..................................................11
7.3 On-Leakage Current................................................. 12
7.4 IPOFF Leakage Current..............................................12
7.5 Transition Time......................................................... 13
7.6 tON (EN) and tOFF (EN) Time......................................... 13
7.7 tON (VDD) and tOFF (VDD) Time..................................... 14
7.8 Break-Before-Make Delay.........................................14
7.9 Propagation Delay.................................................... 15
7.10 Skew....................................................................... 15
7.11 Charge Injection......................................................16
Information.................................................................... 27
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision C (December 2021) to Revision D (October 2022)
Page
• 将带宽规格从1.2GHz 更新为2GHz................................................................................................................... 1
Changes from Revision B (January 2020) to Revision C (December 2021)
Page
• 向特性部分添加了提供功能安全信息................................................................................................................ 1
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
Changes from Revision A (August 2016) to Revision B (January 2020)
Page
• 将文档状态从预告信息更改为量产数据.............................................................................................................1
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5 Pin Configuration and Functions
SEL
S1A
S1B
D1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
EN
SEL
S1A
S1B
D1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
EN
S4A
S4B
D4
S4A
S4B
D4
S2A
S2B
D2
S2A
S2B
D2
S3A
S3B
D3
S3A
S3B
D3
GND
GND
Not to scale
Not to scale
图5-2. DYY Package,
16-Pin SOT-23
(Top View)
图5-1. PW Package,
16-Pin TSSOP
(Top View)
表5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION(2)
NAME
NO.
1
SEL
S1A
S1B
D1
I
Select pin: controls state of switches according to 表8-1. Internal 6 MΩpull-down to GND.
Source pin 1A. Can be an input or output.
Source pin 1B. Can be an input or output.
Drain pin 1. Can be an input or output.
2
I/O
I/O
I/O
I/O
I/O
I/O
P
3
4
S2A
S2B
D2
5
Source pin 2A. Can be an input or output.
Source pin 2B. Can be an input or output.
Drain pin 2. Can be an input or output.
6
7
GND
D3
8
Ground (0 V) reference
9
I/O
I/O
I/O
I/O
I/O
I/O
Drain pin 3. Can be an input or output.
S3B
S3A
D4
10
11
12
13
14
Source pin 3B. Can be an input or output.
Source pin 3A. Can be an input or output.
Drain pin 4. Can be an input or output.
S4B
S4A
Source pin 4B. Can be an input or output.
Source pin 4A. Can be an input or output.
Active low enable: When this pin is high, all switches are turned off. When this pin is low, SEL pin
controls the signal path selection. Internal 6 MΩpull-down to GND.
EN
15
16
I
Positive power supply. This pin is the most positive power-supply potential. For reliable operation,
connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
VDD
P
(1) I = input, O = output, I/O = input and output, P = power
(2) Refer to 节8.4 for what to do with unused pins.
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1) (2) (3)
MIN
–0.5
–0.5
–30
–0.5
–25
–65
MAX
UNIT
V
VDD
Supply voltage
6
6
VSEL or VEN
ISEL or IEN
VS or VD
IS or ID (CONT)
Tstg
Logic control input pin voltage (SEL or EN)
Logic control input pin current (SEL or EN)
Source or drain pin voltage
V
30
6
mA
V
Source and drain pin continuous current: (SxA, SxB, Dx)
Storage temperature
25
150
150
mA
°C
°C
TJ
Junction temperature
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
(3) All voltages are with respect to ground, unless otherwise specified.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per AEC Q100-002(1)
HBM ESD Classification Level 2
±2000
Electrostatic
discharge
V(ESD)
V
Charged device model (CDM), per AEC Q100-011
CDM ESD Classification Level C4B
±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN
1.5
0
MAX
UNIT
V
VDD
Supply voltage
5.5
VDD x 2
3.6
Signal path input or output voltage (source or drain pin), VDD ≥1.5 V(1)
Signal path input or output voltage (source or drain pin), VDD < 1.5 V(2)
Logic control input voltage ( EN, SEL)
VS or VD
VS_off or VD_off
VSEL or VEN
IS or ID (CONT)
TA
V
0
V
0
5.5
V
Source and drain pin continuous current: (SxA, SxB, Dx)
Ambient temperature
25
mA
°C
–25
–40
125
(1) Device input/output can operate up to VDD x 2, with a maximum input/output voltage of 5.5 V.
(2) VS_off and VD_off refers to the voltage at the source or drain pins when supply is less than 1.5 V.
6.4 Thermal Information
DEVICE
DEVICE
DYY (SOT-23)
16 PINS
123.0
THERMAL METRIC(1)
PW (TSSOP)
16 PINS
117.4
47.9
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
70.5
63.7
50.4
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
6.9
5.0
ΨJT
63.1
50.3
ΨJB
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
VDD = 1.5 V to 5.5 V, GND = 0V, TA = –40°C to +125°C
Typical values are at VDD = 3.3 V, TA = 25°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
VDD
Power supply voltage
Active supply current
1.5
5.5
68
V
VSEL = 0 V, 1.4 V or VDD
VS = 0 V to 5.5 V
IDD
40
μA
VEN = 1.4 V or VDD
VS = 0 V to 5.5 V
IDD_STANDBY Supply current when disabled
7.5
15
µA
DC CHARACTERISTICS
VS = 0 V to VDD×2
VS(max) = 5.5 V
ISD = 8 mA
RON
On-resistance
2
5
Ω
Refer to ON-State Resistance Figure
VS = VDD
On-resistance match between channels
On-resistance flatness
ISD = 8 mA
Refer to ON-State Resistance Figure
0.07
1
0.8
2.5
ΔRON
Ω
Ω
VS = 0 V to VDD
ISD = 8 mA
Refer to ON-State Resistance Figure
RON (FLAT)
VDD = 0 V
VS = 0 V to 3.6 V
VD = 0 V
Refer to Ipoff Leakage Figure
IPOFF
Powered-off I/O pin leakage current
OFF leakage current
0.01
0.03
8
µA
nA
–8
Switch Off
IS(OFF)
ID(OFF)
VD = 0.8×VDD / 0.2×VDD
VS = 0.2×VDD / 0.8×VDD
Refer to Off Leakage Figure
900
–900
Switch On
VD = 0.8×VDD / 0.2×VDD, S pins floating
or
VS = 0.8×VDD / 0.2×VDD, D pins floating
Refer to On Leakage Figure
ID(ON)
IS(ON)
ON leakage current
0.01
900
nA
–900
LOGIC INPUTS
VIH
VIL
IIH
Input logic high
1.2
0
5.5
0.45
±2
V
Input logic low
V
Input high leakage current
Input low leakage current
Internal pull-down resistor on logic pins
VSEL = 1.8 V, VDD
VSEL = 0 V
1
0.2
6
μA
μA
MΩ
IIL
±2
RPD
VSEL = 0 V, 1.8 V or VDD
f = 1 MHz
CI
Logic input capacitance
3
pF
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6.6 Dynamic Characteristics
VDD = 1.5 V to 5.5 V, GND = 0 V, TA = –40°C to +125°C
Typical values are at VDD = 3.3 V, TA = 25°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VS = 2.5 V
VSEL= 0 V
f = 1 MHz
Switch
OFF
COFF
Source and drain off capacitance
4
pF
Refer to Capacitance Figure
VS = 2.5 V
VSEL= 0 V
f = 1 MHz
Refer to Capacitance Figure
Switch
ON
CON
Source and drain on capacitance
Charge Injection
8
pF
VS = VDD/2
RS = 0 Ω, CL =1 nF
Refer to Charge Injection Figure
Switch
ON
QC
3.5
–90
–75
pC
dB
dB
RL = 50 Ω
f = 100 kHz
Refer to Off Isolation Figure
Switch
OFF
OISO
Off isolation
RL = 50 Ω
f = 1 MHz
Refer to Off Isolation Figure
Switch
OFF
RL = 50 Ω
f = 100 kHz
Refer to Crosstalk Figure
Switch
ON
XTALK
BW
Channel to Channel crosstalk
Bandwidth
dB
GHz
dB
–90
2
Switch
ON
RL = 50 Ω
Refer to Bandwidth Figure
RL = 50 Ω
f = 1 MHz
Refer to Bandwidth Figure
Switch
ON
ILOSS
Insertion loss
–0.12
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6.7 Timing Requirements
VDD = 1.5 V to 5.5 V, GND = 0V, TA = –40°C to +125°C
Typical values are at VDD = 3.3 V, TA = 25°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
VDD = 2.5 V to 5.5 V
VS = VDD
RL = 200 Ω, CL = 15 pF
Refer to Transition Timing Figure
tTRAN
Transition time from control input
160
350
ns
VDD < 2.5 V
VS = VDD
RL = 200 Ω, CL = 15 pF
Refer to Transition Timing Figure
tTRAN
Transition time from control input
180
580
ns
VS = VDD
tON(EN)
Device turn on time from enable pin
Device turn off time from enable pin
12
50
35
95
µs
ns
RL = 200 Ω, CL = 15 pF
Refer to Ton(EN) and Toff(EN) Figure
VS = VDD
tOFF(EN)
RL = 200 Ω, CL = 15 pF
Refer to Ton(EN) and Toff(EN) Figure
VS = 3.6 V
VDD rise time = 1 µs
RL = 200 Ω, CL = 15 pF
Refer to Ton(vdd) and Toff(vdd) Figure
tON(VDD)
Device turn on time (VDD to output)
Device turn off time (VDD to output)
20
60
µs
VS = 3.6 V
VDD fall time = 1 µs
RL = 200 Ω, CL = 15 pF
Refer to Ton(vdd) and Toff(vdd) Figure
tOFF(VDD)
1.2
2.7
µs
ns
VS = 1 V
RL = 200 Ω, CL = 15 pF
Refer to Topen(BBM) Figure
tOPEN (BBM) Break before make time
0.5
tSK(P)
tSK(P)
tPD
Refer to Tsk Figure
Refer to Tsk Figure
Refer to Tpd Figure
Refer to Tpd Figure
10
18
78
95
ps
ps
ps
ps
Inter-channel skew –SOT-23 (DYY)
Inter-channel skew –TSSOP (PW)
Propagation delay –SOT-23 (DYY)
Propagation delay –TSSOP (PW)
tPD
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Typical Characteristics
At TA = 25°C, VDD = 3.3 V (unless otherwise noted).
5
4
3
5
4
3
2
1
0
TA = 125èC
TA = 85èC
VDD = 1.5 V
VDD = 5.5 V
2
1
0
TA = 25èC
VDD = 3.3 V
TA = -40èC
0
1
2
Source or Drain Voltage (V)
3
4
5
5.5
0
1
2
Source or Drain Voltage (V)
3
4
5
5.5
D001
D002
TA = 25°C
VDD = 5.5 V
图6-1. On-Resistance vs Source or Drain Voltage
图6-2. On-Resistance vs Source or Drain Voltage
4
3
2
1
0
4
3
2
1
0
TA = 125èC
TA = 85èC
TA = 125èC
TA = 85èC
TA = 25èC
TA = -40èC
TA = 25èC
TA = -40èC
1.5
Source or Drain Voltage (V)
0
0.5
1
2
2.5
3
3.5
0
0.5
Source or Drain Voltage (V)
1
1.5
D003
D004
VDD = 3.3 V
VDD = 1.5 V
图6-3. On-Resistance vs Source or Drain Voltage
图6-4. On-Resistance vs Source or Drain Voltage
65
60
55
50
45
40
35
30
25
60
55
50
45
40
35
30
TA = 125èC
TA = 85èC
VDD = 3.3 V
VDD = 5.5 V
TA = 25èC
VDD = 1.5 V
TA = -40èC
2.5
0
0.5
1
1.5
2
2.5
Logic Voltage (V)
3
3.5
4
4.5
5
5.5
1.5
2
3
3.5
Supply Voltage (V)
4
4.5
5
5.5
6
D005
D006
TA = 25°C
.
图6-5. Supply Current vs Logic Voltage
图6-6. Supply Current vs Supply Voltage
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Typical Characteristics
At TA = 25°C, VDD = 3.3 V (unless otherwise noted).
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
700
600
500
400
300
200
100
0
-100
0
0.5
1
1.5
Source Voltage (V)
2
2.5
3
3.5
4
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
D011
D013
TA = 25°C
.
VSource = 3.6 V
VDrain = 0 V
图6-7. IPOFF Leakage vs Source or Drain Voltage
图6-8. IPOFF Leakage vs Temperature
180
160
140
120
100
80
Transiton_Falling
Transiton_Rising
60
40
20
1.5
2
2.5
3
3.5
4
Supply Voltage (V)
4.5
5
5.5
6
D015
TA = 25°C
.
TA = 25°C
RL= 200 Ω
图6-10. TTRANSITION vs Supply Voltage
图6-9. IPOFF Leakage vs Source or Drain Voltage
220
25
20
15
10
5
Transiton_Falling
Transiton_Rising
195
170
145
120
95
70
45
20
0
-40
-20
0
20
40
60
80
100 120 140
1.5
2
2.5
3
Supply Voltage (V)
3.5
4
4.5
5
5.5
Temperature (èC)
D016
D018
VDD = 5.5 V
TA = 25°C
图6-11. TTRANSITION vs Temperature
图6-12. TON (EN) vs Supply Voltage
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Typical Characteristics
At TA = 25°C, VDD = 3.3 V (unless otherwise noted).
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
Propagation Delay - PW
Propagation Delay - DYY
Skew - PW
Skew - DYY
1.5
2
2.5
3
3.5
4
Supply Voltage (V)
4.5
5
5.5
1.5
2
2.5
3
3.5
4
Supply Voltage (V)
4.5
5
5.5
D019
D020
TA = 25°C
TA = 25°C
图6-13. TOFF (EN) vs Supply Voltage
图6-14. Skew and Propagation Delay vs Supply Voltage
0
0
Off Isolation
Crosstalk
-10
-20
-30
-1
-2
-3
-4
-5
-6
-40
-50
-60
-70
-80
-90
-100
-110
-120
100k
1M
10M
Frequency (Hz)
100M
1G
1M
10M
Frequency (Hz)
100M
1G
D023
D024
TA = 25°C
TA = 25°C
VDD = 3.3 V
VDD = 1.5 V to 5.5 V
图6-15. Off Isolation and Crosstalk vs Frequency
图6-16. On-Response vs Frequency
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7 Parameter Measurement Information
7.1 On-Resistance
The on-resistance of a device is the ohmic resistance between the source (Sx) and drain (Dx) pins of the device.
The on-resistance varies with input voltage and supply voltage. The symbol RON is used to denote on-
resistance. The measurement setup used to measure RON is shown in 图 7-1. Voltage (V) and current (ISD) are
measured using this setup, and RON is computed with RON = V / ISD as shown in the following figure.
V
ISD
Sx
Dx
VS
图7-1. On-Resistance Measurement Setup
7.2 Off-Leakage Current
Source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is
off. This current is denoted by the symbol IS (OFF)
.
Drain leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is off.
This current is denoted by the symbol ID (OFF)
.
The setup used to measure both off-leakage currents is shown in 图7-2.
VDD
VDD
IS (OFF)
A
VDD
VDD
ID (OFF)
S1A
S1B
S1A
D1
D1
A
S1B
VS
VD
VD
VD
VS
ID (OFF)
A
IS (OFF)
A
S4A
S4B
D4
S1A
S1B
D1
VD
VS
VS
VD
GND
GND
VD
图7-2. Off-Leakage Measurement Setup
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7.3 On-Leakage Current
Source on-leakage current is defined as the leakage current flowing into or out of the source pin when the switch
is on. This current is denoted by the symbol IS (ON)
.
Drain on-leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is
on. This current is denoted by the symbol ID (ON)
.
Either the source pin or drain pin is left floating during the measurement. 图 7-3 shows the circuit used for
measuring the on-leakage current, denoted by IS(ON) or ID(ON)
.
VDD
VDD
IS (ON)
VDD
VDD
ID (ON)
S1A
S1A
S1B
A
N.C.
D1
D1
A
N.C.
S1B
N.C.
N.C.
VS
VD
IS (ON)
ID (ON)
A
S4A
S4B
S4A
S4B
N.C.
N.C.
A
D4
D4
N.C.
N.C.
VS
VD
GND
GND
图7-3. On-Leakage Measurement Setup
7.4 IPOFF Leakage Current
IPOFF leakage current is defined as the leakage current flowing into or out of the source pin when the device is
powered off. This current is denoted by the symbol IPOFF
.
The setup used to measure both IPOFF leakage current is shown in 图7-4.
VDD
IPOFF
VDD
S1A
A
D1
S1B
N.C.
VS
VD
IPOFF
S4A
S4B
A
D4
N.C.
VS
VD
GND
图7-4. IPOFF Leakage Measurement Setup
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7.5 Transition Time
Transition time is defined as the time taken by the output of the device to rise or fall 10% after the select signal
has risen or fallen past the logic threshold. The 10% transition measurement is utilized to provide the timing of
the device. The time constant from the load resistance and load capacitance can be added to the transition time
to calculate system level timing. 图 7-5 shows the setup used to measure transition time, denoted by the symbol
tTRANSITION
.
VDD
0.1ꢀF
VDD
VDD
ADDRESS
DRIVE
tf < 5ns
tr < 5ns
VIH
S1A
S1B
(VSEL
)
VS
VIL
OUTPUT
RL
D1
D4
0 V
CL
tTRANSITION
tTRANSITION
S4A
S4B
VS
OUTPUT
RL
CL
90%
OUTPUT
SEL
GND
VSEL
10%
0 V
图7-5. Transition-Time Measurement Setup
7.6 tON (EN) and tOFF (EN) Time
The tON (EN) time is defined as the time taken by the output of the device to rise to 90% after the enable has
fallen past the logic threshold. The 90% measurement is used to provide the timing of the device being enabled
in the system. 图7-6 shows the setup used to measure the enable time, denoted by the symbol tON (EN)
.
The tOFF (EN) time is defined as the time taken by the output of the device to fall to 90% after the enable has
fallen past the logic threshold. The 90% measurement is used to provide the timing of the device being disabled
in the system. 图7-6 shows the setup used to measure enable time, denoted by the symbol tOFF (EN)
.
VDD
0.1ꢀF
VDD
VDD
VIH
ENABLE
VIL
DRIVE
(VEN)
S1A
S1B
VS
OUTPUT
RL
D1
D4
tr < 5ns
tf < 5ns
CL
0 V
S4A
S4B
VS
tOFF
tON
(EN)
(EN)
OUTPUT
RL
CL
90%
90%
OUTPUT
0 V
EN
VEN
GND
图7-6. tON (EN) and tOFF (EN) Time Measurement Setup
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7.7 tON (VDD) and tOFF (VDD) Time
The tON (VDD) time is defined as the time taken by the output of the device to rise to 90% after the supply has
risen past the supply threshold. The 90% measurement is used to provide the timing of the device turning on in
the system. 图7-7 shows the setup used to measure turn on time, denoted by the symbol tON (VDD)
.
The tOFF (VDD) time is defined as the time taken by the output of the device to fall to 90% after the supply has
fallen past the supply threshold. The 90% measurement is used to provide the timing of the device turning off in
the system. 图7-7 shows the setup used to measure turn off time, denoted by the symbol tOFF (VDD)
.
VDD
0.1ꢀF
VDD
VDD
VDD
Supply
Ramp
1.5 V
1.5 V
(VDD
)
S1A
S1B
VS
OUTPUT
D1
D4
0 V
CL
RL
tON
tOFF
(VDD)
(VDD)
S4A
S4B
90%
90%
VS
OUTPUT
RL
OUTPUT
0 V
CL
EN
GND
图7-7. tON (VDD) and tOFF (VDD) Time Measurement Setup
7.8 Break-Before-Make Delay
Break-before-make delay is a safety feature that prevents two inputs from connecting when the device is
switching. The output first breaks from the on-state switch before making the connection with the next on-state
switch. The time delay between the break and the make is known as break-before-make delay. 图7-8 shows the
setup used to measure break-before-make delay, denoted by the symbol tOPEN(BBM)
.
VDD
0.1ꢀF
VDD
VDD
VSEL
0 V
S1A
VS
OUTPUT
RL
D1
D4
tr < 5ns
tf < 5ns
S1B
CL
S4A
S4B
VS
OUTPUT
RL
90%
Output
0 V
tBBM
1
tBBM
2
CL
tOPEN (BBM) = min ( tBBM 1, tBBM 2)
SEL
VSEL
GND
图7-8. Break-Before-Make Delay Measurement Setup
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7.9 Propagation Delay
Propagation delay is defined as the time taken by the output of the device to rise or fall 50% after the input signal
has risen or fallen past the 50% threshold. 图 7-9 shows the setup used to measure propagation delay, denoted
by the symbol tPD
.
VDD
0.1ꢀF
VDD
250 mV
Input
(VS)
S1A
S1B
50%
50%
VS
VS
OUTPUT
D1
0 V
RL
50ꢁ
tPD 1
tPD 2
S4A
S4B
VS
VS
OUTPUT
D4
Output
0 V
50%
50%
RL
50ꢁ
GND
tProp Delay = max ( tPD 1, tPD 2
)
图7-9. Propagation Delay Measurement Setup
7.10 Skew
Skew is defined as the difference between propagation delays of any two outputs of the same device. The skew
measurement is taken from the output of one channel rising or falling past 50% to a second channel rising or
falling past the 50% threshold when the input signals are switched at the same time. 图 7-10 shows the setup
used to measure skew, denoted by the symbol tSK
.
VDD
0.1ꢀF
VDD
S1A
S1B
Output 1
50%
50%
VS
VS
OUTPUT
D1
0 V
RL
50ꢁ
tSK 1
tSK 2
S4A
S4B
VS
VS
OUTPUT
D4
Output 2
0 V
50%
50%
RL
50ꢁ
GND
tSKEW = max ( tSK 1, tSK 2
)
图7-10. Skew Measurement Setup
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7.11 Charge Injection
The amount of charge injected into the source or drain of the device during the falling or rising edge of the gate
signal is known as charge injection, and is denoted by the symbol QC. 图7-11 shows the setup used to measure
charge injection from source (Sx) to drain (Dx).
VDD
0.1ꢀF
VDD
VDD
S1A
VS
OUTPUT
D1
VOUT
CL
VEN
0 V
S1B
S4A
S4B
VS
Output
VS
OUTPUT
D4
VOUT
CL
VOUT
QC = CL
×
VOUT
EN
VEN
GND
图7-11. Charge-Injection Measurement Setup
7.12 Capacitance
The parasitic capacitance of the device is captured at the source (Sx), drain (Dx), and select (SELx) pins. The
capacitance is measured in both the ON and OFF state and is denoted by the symbol CON and COFF. 图 7-12
shows the setup used to measure capacitance.
VDD
VDD
S1A
S1B
D1
1 MHz
Capacitance
Meter
Capacitance is measured at SX, DX,
and logic pins during ON and OFF
conditions
S4A
D4
S4B
LOGIC CONTROL
SEL
EN
GND
图7-12. Capacitance Measurement Setup
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7.13 Off Isolation
Off isolation is defined as the ratio of the signal at the drain pin (Dx) of the device when a signal is applied to the
source pin (Sx) of an off-channel. The characteristic impedance, Z0, for the measurement is 50 Ω. 图 7-13
shows the setup used to measure off isolation. Use off isolation equation to compute off isolation.
0.1µF
NETWORK
VDD
ANALYZER
VS
S
D
50Ω
VSIG
VOUT
RL
SxA / SxB / Dx
50Ω
RL
GND
50Ω
图7-13. Off Isolation Measurement Setup
≈
∆
«
’
÷
◊
VOUT
VS
Off Isolation = 20 ∂ Log
(1)
7.14 Channel-to-Channel Crosstalk
Crosstalk is defined as the ratio of the signal at the drain pin (Dx) of a different channel, when a signal is applied
at the source pin (Sx) of an on-channel. The characteristic impedance, Z0, for the measurement is 50 Ω. 图7-14
shows the setup used to measure, and the equation used to compute crosstalk.
VDD
0.1µF
NETWORK
VDD
ANALYZER
D1
D4
S1A
VOUT
RL
RL
50Ω
50Ω
VS
S4A
RL
50Ω
50Ω
SxA / SxB / Dx
VSIG = 200 mVpp
VBIAS = VDD / 2
RL
50Ω
GND
图7-14. Channel-to-Channel Crosstalk Measurement Setup
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≈
∆
«
’
÷
◊
VOUT
VS
Channel-to-Channel Crosstalk = 20 ∂ Log
(2)
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7.15 Bandwidth
Bandwidth is defined as the range of frequencies that are attenuated by less than 3 dB when the input is applied
to the source pin (Sx) of an on-channel, and the output is measured at the drain pin (Dx) of the device. The
characteristic impedance, Z0, for the measurement is 50 Ω. 图 7-15 shows the setup used to measure
bandwidth.
VDD
0.1µF
NETWORK
VDD
ANALYZER
VS
50Ω
S
D
VSIG
VOUT
RL
50Ω
SxA / SxB / Dx
RL
GND
50Ω
图7-15. Bandwidth Measurement Setup
#PPAJQ=PEKJ = 20 × .KC (8
)
176
8
5
(3)
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8 Detailed Description
8.1 Overview
The SN3257-Q1 is an automotive qualified 2:1 (SPDT) 4-channel switch with powered-off protection up to 3.6 V.
Wide operating supply of 1.5 V to 5.5 V allows for use in applications where different supply voltages are
available. The device supports bidirectional analog and digital signals on the source (SxA, SxB) and drain (Dx)
pins. The wide bandwidth of this switch allows little or no attenuation of high-speed signals with minimum
propagation delay.
The enable (EN) pin is an active-low logic pin that controls the connection between the source (SxA, SxB) and
drain (Dx) pins of the device. The select pin (SEL) controls the state of all four channels of the SN3257-Q1 and
determines which source pin is connected to the drain. Fail-Safe Logic circuitry allows voltages on the logic
control pins to be applied before the supply pin, protecting the device from potential damage. All logic control
inputs have 1.8 V logic compatible thresholds, ensuring both TTL and CMOS logic compatibility when operating
in the valid supply voltage range.
Powered-off protection up to 3.6 V on the signal path of the SN3257-Q1 provides isolation when the supply
voltage is removed (VDD = 0 V). Without this protection feature, the system can back-power the supply rail
through an internal ESD diode and cause potential damage to the system.
8.2 Functional Block Diagram
SN3257-Q1
S1A
D1
S1B
S2A
D2
S2B
S3A
D3
S3B
S4A
D4
S4B
LOGIC CONTROL*
SEL
EN
*Internal 6MO Pull-Down on Logic Pins
8.3 Feature Description
8.3.1 Bidirectional Operation
The SN3257-Q1 conducts equally well from source (SxA, SxB) to drain (Dx) or from drain (Dx) to source (SxA,
SxB). Each channel has very similar characteristics in both directions and supports both analog and digital
signals.
8.3.2 Beyond Supply Operation
When the SN3257-Q1 is powered from 1.5 V to 5.5 V, the valid signal path input or output voltage ranges from
GND to VDD x 2, with a maximum input or output voltage of 5.5 V.
Example 1: If the SN3257-Q1 is powered at 1.5 V, the signal range is 0 V to 3 V.
Example 2: If the SN3257-Q1 is powered at 2.5 V, the signal range is 0 V to 5.0 V.
Example 2: If the SN3257-Q1 is powered at 3.6 V, the signal range is 0 V to 5.5 V.
Example 3: If the SN3257-Q1 is powered at 5.5 V, the signal range is 0 V to 5.5 V.
Other voltage levels not mentioned in the examples support Beyond Supply Operation as long as the supply
voltage falls within the recommended operation conditions of 1.5 V to 5.5 V.
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8.3.3 1.8 V Logic Compatible Inputs
The SN3257-Q1 has 1.8-V logic compatible control inputs. Regardless of the VDD voltage, the control input
thresholds remain fixed, allowing a 1.8-V processor GPIO to control the SN3257-Q1 without the need for an
external translator. This saves both space and BOM cost. For more information on 1.8 V logic implementations,
refer to Simplifying Design with 1.8 V logic Muxes and Switches.
8.3.4 Powered-off Protection
Powered-off protection up to 3.6 V on the signal path of the SN3257-Q1 provides isolation when the supply
voltage is removed (VDD = 0 V). When the SN3257-Q1 is powered-off, the I/Os of the device remain in a high-Z
state. Powered-off protection minimizes system complexity by removing the need for power supply sequencing
on the signal path. The device performance remains within the leakage performance mentioned in the Electrical
Specifications. For more information on powered-off protection, refer to Eliminate Power Sequencing with
Powered-off Protection Signal Switches.
8.3.5 Fail-Safe Logic
The SN3257-Q1 has Fail-Safe Logic on the control input pins (SELx) which allows for operation up to 5.5 V,
regardless of the state of the supply pin. This feature allows voltages on the control pins to be applied before the
supply pin, protecting the device from potential damage. Fail-Safe Logic minimizes system complexity by
removing the need for power supply sequencing on the logic control pins. For example, the Fail-Safe Logic
feature allows the select pins of the SN3257-Q1 to be ramped to 5.5 V while VDD = 0 V. Additionally, the feature
enables operation of the SN3257-Q1 with VDD = 1.5 V while allowing the select pins to interface with a logic level
of another device up to 5.5 V.
8.3.6 Integrated Pull-Down Resistors
The SN3257-Q1 has internal weak pull-down resistors (6 MΩ) to GND to ensure the logic pins are not left
floating. This feature integrates up to four external components and reduces system size and cost.
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8.4 Device Functional Modes
The enable (EN) pin is an active-low logic pin that controls the connection between the source (SxA, SxB) and
drain (Dx) pins of the device. When the enable pin is pulled high, all switches are turned off. When the enable
pin is pulled low, the select pin controls the signal path selection. The select pin (SEL) controls the state of all
four channels of the SN3257-Q1 and determines which source pin is connected to the drain pins. When the
select pin is pulled low, the SxA pin conducts to the corresponding Dx pins. When the select pin is pulled high,
the SxB pin conducts to the corresponding Dx pins. The SN3257-Q1 logic pins have internal weak pull-down
resistors (6 MΩ) to GND so that it powers-on in a known state.
The SN3257-Q1 can be operated without any external components except for the supply decoupling capacitors.
Unused logic control pins should be tied to GND or VDD to ensure the device does not consume additional
current as highlighted in Implications of Slow or Floating CMOS Inputs. Unused signal path inputs (SxA, SxB, or
Dx) should be connected to GND.
8.4.1 Truth Tables
表8-1. SN3257-Q1 Truth Table
INPUTS
Selected Source Pins Connected To Drain Pins
(Dx)
EN
SEL
S1A connected to D1
S2A connected to D2
S3A connected to D3
S4A connected to D4
0
0
S1B connected to D1
S2B connected to D2
S3B connected to D3
S4B connected to D4
0
1
1
X(1)
Hi-Z (OFF)
(1) X denotes do not care.
SN3257-Q1
S1A
S1B
D1
D2
D3
D4
S2A
S2B
S3A
S3B
S4A
S4B
LOGIC CONTROL*
SEL
EN
*Internal 6MO Pull-Down on Logic Pins
图8-1. SN3257-Q1 Functional Block Diagram
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The SN3257-Q1 operates across a wide supply 1.5 V to 5.5 V and operating temperature range
(–40°C to +125°C). The SN3257-Q1 supports a number of features that improve system performance such as
1.8 V logic compatibility, supports input voltages beyond supply, Fail-Safe Logic, and Powered-off Protetion up
to 3.6 V. These features reduce system complexity, board size, and overall system cost.
9.2 Typical Application
Common applications that require the features of the SN3257-Q1 include multiplexing various protocols from a
processor or MCU such as SPI, eMMC, I2S, or standard GPIO signals. The SN3257-Q1 provides superior
isolation performance when the device is powered. The added benefit of powered-off protection allows a system
to minimize complexity by eliminating the need for power sequencing in hot-swap and live insertion applications.
图9-1 shows how to use the SN3257-Q1 to multiplex an SPI bus to multiple flash memory devices.
1.8 V
3.3 V
3.3 V
0.1µF
FLASH Device #1
VI/O
VDD
VDD
Processor
S1A
S2A
S3A
S4A
MISO
MOSI
SCLK
SS
D1
D2
D3
D4
RAM
CPU
SPI PORT
FLASH Device #2
S1B
S2B
S3B
S4B
MISO
MOSI
SCLK
SS
Peripherals
1.8V Logic
I/O
SEL
EN
GND
GND
图9-1. Multiplexing Flash Memory
9.2.1 Design Requirements
For this design example, use the parameters listed in 表9-1.
表9-1. Design Parameters
PARAMETERS
VALUES
3.3 V
Supply (VDD
)
Input and Output signals
Control logic thresholds
0 V to 3.3 V SPI
1.8 V compatible
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9.2.2 Detailed Design Procedure
The SN3257-Q1 can be operated without any external components except for the supply decoupling capacitors.
The SN3257-Q1 has internal weak pull-down resistors (6 MΩ) to GND so that it powers-on with the switches in
a known state. All inputs signals passing through the switch must fall within the recommended operating
conditions of the SN3257-Q1 including signal range and continuous current. This design example can support
SPI signals that range from 0 V to 3.3 V when the device is powered. This example can also utilize the Powered-
off Protection feature and the inputs can range from 0 V to 3.6 V when VDD = 0 V. The maximum continuous
current can be 25 mA. Due to the voltage range and high speed capability, the SN3257-Q1 example is suitable
for use in SPI, JTAG, and I2S applications.
9.2.3 Application Curves
Two important specifications when using a switch or multiplexer to pass signals are the device propagation delay
and skew.
100
90
Propagation Delay - PW
80
70
Propagation Delay - DYY
60
50
40
Skew - PW
30
Skew - DYY
20
10
0
1.5
2
2.5
3
3.5
4
Supply Voltage (V)
4.5
5
5.5
D020
图9-2. Propagation Delay and Skew Measurement
10 Power Supply Recommendations
The SN3257-Q1 operates across a wide supply range of 1.5 V to 5.5 V. Do not exceed the absolute maximum
ratings because stresses beyond the listed ratings can cause permanent damage to the devices.
Power-supply bypassing improves noise margin and prevents switching noise propagation from the VDD supply
to other components. Good power-supply decoupling is important to achieve optimum performance. For
improved supply noise immunity, use a supply decoupling capacitor ranging from 0.1 μF to 10 μF from the VDD
to ground. Place the bypass capacitors as close to the power supply pins of the device as possible using low-
impedance connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs) that offer low
equivalent series resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling purposes.
For very sensitive systems, or for systems in harsh noise environments, avoiding the use of vias for connecting
the capacitors to the device pins may offer superior noise immunity. The use of multiple vias in parallel lowers
the overall inductance and is beneficial for connections to ground planes.
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11 Layout
11.1 Layout Guidelines
When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of
the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This
increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance
of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must
turn corners. 图 11-1 shows progressively better techniques of rounding corners. Only the last example (BEST)
maintains constant trace width and minimizes reflections.
WORST
BETTER
BEST
2W
1W min.
W
图11-1. Trace Example
Route the high-speed signals using a minimum of vias and corners which reduces signal reflections and
impedance changes. When a via must be used, increase the clearance size around it to minimize its
capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of
picking up interference from the other layers of the board. Be careful when designing test points, through-hole
pins are not recommended at high frequencies.
Do not route high speed signal traces under or near crystals, oscillators, clock signal generators, switching
regulators, mounting holes, magnetic devices or ICs that use or duplicate clock signals.
Avoid stubs on the high-speed signals traces because they cause signal reflections.
Route all high-speed signal traces over continuous GND planes, with no interruptions.
Avoid crossing over anti-etch, commonly found with plane splits.
When working with high frequencies, a printed circuit board with at least four layers is recommended; two signal
layers separated by a ground and power layer as shown in 图11-2.
Signal 1
GND Plane
Power Plane
Signal 2
图11-2. Example Layout
The majority of signal traces must run on a single layer, preferably Signal 1. Immediately next to this layer must
be the GND plane, which is solid with no cuts. Avoid running signal traces across a split in the ground or power
plane. When running across split planes is unavoidable, sufficient decoupling must be used. Minimizing the
number of signal vias reduces EMI by reducing inductance at high frequencies.
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图11-3 shows an example of a PCB layout with the SN3257-Q1. Some key considerations are:
Decouple the VDD pin with a 0.1-μF capacitor, placed as close to the pin as possible. Make sure that the
capacitor voltage rating is sufficient for the VDD supply.
High-speed switches require proper layout and design procedures for optimum performance.
Keep the input lines as short as possible.
Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.
Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
11.2 Layout Example
Wide (low inductance)
Via to
trace for power
GND plane
C
SEL
VDD
EN
S1A
S1B
D1
S4A
S4B
SN3257-Q1
S2A
D4
S3A
S3B
D3
S2B
D2
GND
图11-3. Example Layout
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documenation, see the following:
• Texas Instruments, SN3257-Q1 Functional Safety FIT Rate, FMD, and Pin FMA application report
• Texas Instruments, Eliminate Power Sequencing with Powered-off Protection Signal Switches application
briefs
• Texas Instruments, Simplifying Design with 1.8 V logic Muxes and Switches application brief
• Texas Instruments, System-Level Protection for High-Voltage Analog Multiplexers application reports
• Texas Instruments, Improve Stability Issues with Low CON Multiplexers application brief
• Texas Instruments, High-Speed Interface Layout Guidelines application report
• Texas Instruments, High-Speed Layout Guidelines application report
12.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
3-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN3257QDYYRQ1
SN3257QPWRQ1
ACTIVE SOT-23-THIN
DYY
PW
16
16
3000 RoHS & Green
2000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
SN3257
SN3257
Samples
Samples
ACTIVE
TSSOP
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
3-Oct-2022
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Oct-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN3257QDYYRQ1
SN3257QPWRQ1
SOT-23-
THIN
DYY
PW
16
16
3000
2000
330.0
12.4
4.8
3.6
1.6
8.0
12.0
Q3
TSSOP
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Oct-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN3257QDYYRQ1
SN3257QPWRQ1
SOT-23-THIN
TSSOP
DYY
PW
16
16
3000
2000
336.6
356.0
336.6
356.0
31.8
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
4.5
4.3
NOTE 4
1.2 MAX
0.19
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE
DYY0016A
C
3.36
3.16
SEATING PLANE
PIN 1 INDEX
AREA
A
0.1 C
14X 0.5
16
1
4.3
4.1
NOTE 3
2X
3.5
8
9
0.31
16X
0.11
0.1
C A
B
1.1 MAX
2.1
1.9
B
0.2
0.08
TYP
SEE DETAIL A
0.25
GAUGE PLANE
0°- 8°
0.1
0.0
0.63
0.33
DETAIL A
TYP
4224642/B 07/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed
0.15 per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.50 per side.
5. Reference JEDEC Registration MO-345, Variation AA
www.ti.com
EXAMPLE BOARD LAYOUT
SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE
DYY0016A
16X (1.05)
SYMM
16
1
16X (0.3)
SYMM
14X (0.5)
9
8
(R0.05) TYP
(3)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
NON- SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4224642/B 07/2021
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE
DYY0016A
16X (1.05)
SYMM
16
1
16X (0.3)
SYMM
14X (0.5)
9
8
(R0.05) TYP
(3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 20X
4224642/B 07/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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