SN5400_07_技术文档

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SDLS025B − DECEMBER 1983 − REVISED OCTOBER 2003

D

Package Options Include Plastic

Small-Outline (D, NS, PS), Shrink

Small-Outline (DB), and Ceramic Flat (W)

Packages, Ceramic Chip Carriers (FK), and

Standard Plastic (N) and Ceramic (J) DIPs

D

Also Available as Dual 2-Input

Positive-NAND Gate in Small-Outline (PS)

Package

SN5400 . . . J PACKAGE

SN54LS00, SN54S00 . . . J OR W PACKAGE

SN7400, SN74S00 . . . D, N, OR NS PACKAGE

SN74LS00 . . . D, DB, N, OR NS PACKAGE

(TOP VIEW)

SN74LS00, SN74S00 . . . PS PACKAGE

(TOP VIEW)

V

2B

2A

2Y

1A

1B

1Y

2A

2B

V

CC

1

2

3

4

5

6

7

14

13

12

11

10

9

1

2

3

4

8

7

6

5

1A

1B

1Y

CC

4B

4A

4Y

3B

3A

3Y

GND

2Y

GND

8

SN5400 . . . W PACKAGE

(TOP VIEW)

SN54LS00, SN54S00 . . . FK PACKAGE

(TOP VIEW)

1A

1B

1Y

4Y

4B

4A

GND

3B

1

2

3

4

5

6

7

14

13

12

11

10

9

3

2 1 20 19

18

4A

NC

4Y

NC

3B

1Y

NC

2A

4

5

6

7

8

V

17

16

15

14

CC

2Y

2A

2B

3A

3Y

NC

2B

8

9 10 11 12 13

NC − No internal connection

description/ordering information

These devices contain four independent 2-input NAND gates. The devices perform the Boolean function

Y = A • B or Y = A + B in positive logic.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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Copyright  2003, Texas Instruments Incorporated

ꢓ ꢘ ꢣ ꢛ ꢚꢦ ꢡꢠ ꢞꢟ ꢠꢚ ꢜꢣ ꢥꢗ ꢝꢘ ꢞ ꢞꢚ ꢭꢑ ꢆꢐ ꢍꢌ ꢮ ꢐꢯꢰꢂ ꢯꢂꢅ ꢝꢥꢥ ꢣꢝ ꢛ ꢝ ꢜꢢ ꢞꢢꢛ ꢟ ꢝ ꢛ ꢢ ꢞꢢ ꢟꢞꢢ ꢦ

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ꢞ ꢢ ꢟ ꢞꢗ ꢘꢬ ꢚꢙ ꢝ ꢥꢥ ꢣꢝ ꢛ ꢝ ꢜ ꢢ ꢞ ꢢ ꢛ ꢟ ꢧ

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ꢡ ꢘꢥ ꢢꢟꢟ ꢚ ꢞꢨꢢ ꢛ ꢪꢗ ꢟꢢ ꢘ ꢚꢞꢢ ꢦꢧ ꢓ ꢘ ꢝꢥ ꢥ ꢚ ꢞꢨꢢ ꢛ ꢣꢛ ꢚ ꢦꢡꢠ ꢞꢟ ꢅ ꢣꢛ ꢚ ꢦꢡꢠ ꢞꢗꢚ ꢘ

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1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄ ꢄ ꢅ ꢀꢁ ꢂ ꢃꢆ ꢀ ꢄ ꢄꢅ ꢀ ꢁꢂ ꢃ ꢀꢄ ꢄ

ꢀ ꢁꢇ ꢃꢄ ꢄ ꢅ ꢀꢁ ꢇ ꢃꢆ ꢀ ꢄ ꢄꢅ ꢀ ꢁꢇ ꢃ ꢀꢄ ꢄ

ꢈꢉ ꢊ ꢋꢌ ꢉ ꢍꢆ ꢎ ꢏ ꢐꢑ ꢁꢍ ꢉꢒ ꢍ ꢓꢀ ꢑ ꢒꢑ ꢔ ꢎꢐ ꢁꢊꢁ ꢋ ꢕ ꢊꢒ ꢎꢀ

SDLS025B − DECEMBER 1983 − REVISED OCTOBER 2003

description/ordering information (continued)

ORDERING INFORMATION

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

†

PACKAGE

T

A

SN7400N

SN74LS00N

SN74S00N

SN74LS00N

SN74S00N

PDIP − N

SOIC − D

SOP − NS

Tube

SN7400D

7400

LS00

S00

Tape and reel

Tube

SN7400DR

SN74LS00D

SN74LS00DR

SN74S00D

Tape and reel

Tube

0°C to 70°C

Tape and reel

SN74S00DR

SN7400NSR

SN74LS00NSR

SN74S00NSR

SN74LS00PSR

SN74S00PSR

SN74LS00DBR

SNJ5400J

SN7400

74LS00

Tape and reel

74S00

LS00

SOP − PS

Tape and reel

S00

SSOP − DB

LS00

SNJ5400J

SNJ54LS00J

SNJ54S00J

SNJ5400W

SNJ54LS00W

SNJ54S00W

SNJ54LS00FK

SNJ54LS00J

SNJ54S00J

SNJ5400W

CDIP − J

Tube

−55°C to 125°C

SNJ54LS00W

SNJ54S00W

SNJ54LS00FK

CFP − W

Tube

LCCC − FK

SNJ54S00FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines

are available at www.ti.com/sc/package.

FUNCTION TABLE

(each gate)

INPUTS

OUTPUT

Y

A

B

H

X

L

H

L

H

X

logic diagram, each gate (positive logic)

A

B

Y

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SDLS025B − DECEMBER 1983 − REVISED OCTOBER 2003

schematic

’00

V

CC

130 Ω

4 kΩ

1.6 kΩ

A

B

Y

1 kΩ

GND

’LS00

’S00

V

CC

V

CC

50 Ω

120 Ω

20 kΩ

8 kΩ

2.8 kΩ

900 Ω

A

B

3.5 kΩ

A

B

Y

12 kΩ

Y

4 kΩ

250 Ω

500 Ω

1.5 kΩ

3 kΩ

GND

Resistor values shown are nominal.

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄ ꢄ ꢅ ꢀꢁ ꢂ ꢃꢆ ꢀ ꢄ ꢄꢅ ꢀ ꢁꢂ ꢃ ꢀꢄ ꢄ

ꢀ ꢁꢇ ꢃꢄ ꢄ ꢅ ꢀꢁ ꢇ ꢃꢆ ꢀ ꢄ ꢄꢅ ꢀ ꢁꢇ ꢃ ꢀꢄ ꢄ

ꢈꢉ ꢊ ꢋꢌ ꢉ ꢍꢆ ꢎ ꢏ ꢐꢑ ꢁꢍ ꢉꢒ ꢍ ꢓꢀ ꢑ ꢒꢑ ꢔ ꢎꢐ ꢁꢊꢁ ꢋ ꢕ ꢊꢒ ꢎꢀ

SDLS025B − DECEMBER 1983 − REVISED OCTOBER 2003

†

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage, V

(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

CC

Input voltage: ’00, ’S00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V

’LS00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W

JA

DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W

N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W

NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W

PS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95°C/W

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. Voltage values are with respect to network ground terminal.

2. The package termal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions (see Note 3)

SN5400

MIN NOM

SN7400

UNIT

MAX

MIN NOM

MAX

V

Supply voltage

4.5

2

5

5.5

4.75

2

5

5.25

V

CC

High-level input voltage

Low-level input voltage

High-level output current

Low-level output current

Operating free-air temperature

IH

0.8

−0.4

16

0.8

−0.4

16

V

IL

I

mA

°C

OH

OL

T

A

−55

125

0

70

NOTE 3: All unused inputs of the device must be held at V

or GND to ensure proper device operation. Refer to the TI application report,

CC

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

SN5400

SN7400

‡

PARAMETER

UNIT

TEST CONDITIONS

I = −12 mA

§

MIN TYP

MAX

MIN TYP

MAX

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

= MIN,

= MAX,

= MAX

= MAX,

−1.5

V

IK

I

V

= 0.8 V,

= 2 V,

I

= −0.4 mA

= 16 mA

2.4

3.4

0.2

2.4

3.4

0.2

V

OH

OL

IL

OH

V

IH

0.4

1

0.4

1

V

OL

I

V = 5.5 V

I

mA

µA

mA

I

V = 2.4 V

I

40

IH

IL

V = 0.4 V

I

−1.6

−55

8

−1.6

−55

8

¶

−20

−18

OS

V = 0 V

I

4

CCH

CCL

V = 4.5 V

I

12

22

12

22

‡

§

¶

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

All typical values are at V = 5 V, T = 25°C.

Not more than one output should be shorted at a time.

CC

A

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SDLS025B − DECEMBER 1983 − REVISED OCTOBER 2003

switching characteristics, V

= 5 V, T = 25°C (see Figure 1)

CC

A

SN5400

SN7400

FROM

PARAMETER

TO

(OUTPUT)

TEST CONDITIONS

UNIT

(INPUT)

MIN

TYP

11

MAX

22

t

PLH

A or B

Y

R

= 400 Ω,

C

= 15 pF

L

ns

L

t

7

15

PHL

recommended operating conditions (see Note 4)

SN54LS00

MIN NOM

SN74LS00

UNIT

MAX

MIN NOM

MAX

V

Supply voltage

4.5

2

5

5.5

4.75

2

5

5.25

V

CC

High-level input voltage

Low-level input voltage

High-level output current

Low-level output current

Operating free-air temperature

IH

0.7

−0.4

4

0.8

−0.4

8

V

IL

I

mA

°C

OH

OL

T

A

−55

125

0

70

NOTE 4: All unused inputs of the device must be held at V

or GND to ensure proper device operation. Refer to the TI application report,

CC

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

SN54LS00

SN74LS00

†

PARAMETER

UNIT

TEST CONDITIONS

‡

MIN TYP

MAX

MIN TYP

MAX

V

= MIN,

I = −18 mA

−1.5

V

IK

CC

I

V

IL

= MAX,

= 2 V

I

= −0.4 mA

= 4 mA

2.5

3.4

2.7

3.4

0.25

0.35

OH

CC

OH

OL

0.25

0.4

0.5

V

OL

V

CC

= MIN,

V

IH

V

= 8mA

I

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

= MAX,

= MAX

= MAX,

V = 7 V

0.1

20

0.1

mA

µA

I

V = 2.7V

I

20

IH

IL

V = 0.4 V

I

−0.4

−100

1.6

−0.4

−100

1.6

mA

§

−20

OS

V = 0 V

I

0.8

2.4

0.8

2.4

CCH

CCL

V = 4.5 V

I

4.4

†

‡

§

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

All typical values are at V = 5 V, T = 25°C.

Not more than one output should be shorted at a time.

CC

A

switching characteristics, V

= 5 V, T = 25°C (see Figure 1)

CC

A

SN54LS00

SN74LS00

FROM

PARAMETER

TO

(OUTPUT)

TEST CONDITIONS

UNIT

(INPUT)

MIN

TYP

9

MAX

15

t

PLH

A or B

Y

R

= 2 kΩ,

C

= 15 pF

L

ns

L

t

10

15

PHL

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄ ꢄ ꢅ ꢀꢁ ꢂ ꢃꢆ ꢀ ꢄ ꢄꢅ ꢀ ꢁꢂ ꢃ ꢀꢄ ꢄ

ꢀ ꢁꢇ ꢃꢄ ꢄ ꢅ ꢀꢁ ꢇ ꢃꢆ ꢀ ꢄ ꢄꢅ ꢀ ꢁꢇ ꢃ ꢀꢄ ꢄ

ꢈꢉ ꢊ ꢋꢌ ꢉ ꢍꢆ ꢎ ꢏ ꢐꢑ ꢁꢍ ꢉꢒ ꢍ ꢓꢀ ꢑ ꢒꢑ ꢔ ꢎꢐ ꢁꢊꢁ ꢋ ꢕ ꢊꢒ ꢎꢀ

SDLS025B − DECEMBER 1983 − REVISED OCTOBER 2003

recommended operating conditions (see Note 5)

SN54S00

SN74S00

UNIT

MIN NOM

MAX

MIN NOM

MAX

V

Supply voltage

4.5

2

5

5.5

4.75

2

5

5.25

V

CC

High-level input voltage

Low-level input voltage

High-level output current

Low-level output current

Operating free-air temperature

IH

0.8

−1

0.8

−1

20

70

V

IL

I

mA

°C

OH

20

OL

T

A

−55

125

0

NOTE 5: All unused inputs of the device must be held at V

or GND to ensure proper device operation. Refer to the TI application report,

CC

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

SN54S00

SN74S00

†

PARAMETER

UNIT

TEST CONDITIONS

‡

MIN TYP

MAX

MIN TYP

MAX

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

= MIN,

= MAX,

= MAX

= MAX,

I = −18 mA

−1.2

V

IK

I

V

= 0.8 V,

= 2 V,

I

= −1 mA

= 20 mA

2.5

3.4

2.7

3.4

V

OH

OL

IL

OH

0.5

1

0.5

1

V

IH

OL

I

V = 5.5 V

I

mA

µA

mA

I

V = 2.7 V

I

50

IH

IL

V = 0.5V

I

−2

§

−40

−100

16

−40

−100

16

OS

V = 0 V

I

10

20

10

20

CCH

CCL

V = 4.5 V

I

36

†

‡

§

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

All typical values are at V = 5 V, T = 25°C.

Not more than one output should be shorted at a time.

CC

A

switching characteristics, V

= 5 V, T = 25°C (see Figure 1)

CC

A

SN54S00

SN74S00

FROM

PARAMETER

TO

(OUTPUT)

TEST CONDITIONS

UNIT

(INPUT)

MIN

TYP

3

MAX

4.5

5

t

PLH

A or B

Y

R

= 280 Ω,

C

= 15 pF

= 50 pF

ns

L

t

3

PHL

PLH

PHL

4.5

5

A or B

Y

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ

ꢁ

ꢇ

ꢉ

ꢂ

ꢃ

ꢒ

ꢃ

ꢄ

ꢍ

ꢄ

ꢅ

ꢓ

ꢅ

ꢀ

ꢁ

ꢇ

ꢑ

ꢂ

ꢃ

ꢔ

ꢃ

ꢆ

ꢎ

ꢆ

ꢀ

ꢐ

ꢀ

ꢄ

ꢁ

ꢄ

ꢊ

ꢄ

ꢅ

ꢁ

ꢅ

ꢀ

ꢋ

ꢁ

ꢂ

ꢃ

ꢀ

ꢄ

ꢁꢇ ꢃꢀ ꢄ

ꢄ

ꢀ

ꢁ

ꢀ

ꢁ

ꢈ

ꢉ

ꢊ

ꢋ

ꢌ

ꢉ

ꢍ

ꢆ

ꢎ

ꢏ

ꢐ

ꢑ

ꢁ

ꢍ

ꢀ

ꢑ

ꢒ

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ꢀ

SDLS025B − DECEMBER 1983 − REVISED OCTOBER 2003

PARAMETER MEASUREMENT INFORMATION

SERIES 54/74 DEVICES

V

CC

Test

Point

R

L

Test

Point

S1

V

CC

From Output

Under Test

V

CC

(see Note B)

R

L

C

L

(see Note A)

From Output

Under Test

1 kΩ

R

L

(see Note B)

From Output

Under Test

C

Test

Point

C

L

(see Note A)

L

(see Note A)

S2

LOAD CIRCUIT

FOR 2-STATE TOTEM-POLE OUTPUTS

FOR OPEN-COLLECTOR OUTPUTS

FOR 3-STATE OUTPUTS

3 V

High-Level

Timing

Input

1.5 V

Pulse

0 V

t

h

w

t

su

3 V

0 V

Low-Level

Pulse

Data

Input

1.5 V

VOLTAGE WAVEFORMS

PULSE DURATIONS

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

3 V

0 V

Output

Control

(low-level

enabling)

1.5 V

3 V

0 V

Input

1.5 V

t

PLZ

PZL

t

PHL

PLH

Waveform 1

(see Notes C

and D)

≈1.5 V

In-Phase

1.5 V

V

OH

Output

(see Note D)

V

OL

+ 0.5 V

1.5 V

V

OL

V

OL

t

PZH

PHZ

t

PLH

PHL

V

OH

Waveform 2

(see Notes C

and D)

V

OH

− 0.5 V

Out-of-Phase

Output

(see Note D)

V

OH

1.5 V

≈1.5 V

OL

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

NOTES: A.

C

includes probe and jig capacitance.

L

B. All diodes are 1N3064 or equivalent.

C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

D. S1 and S2 are closed for t

, t

, and t

; S1 is open and S2 is closed for t

PZH

; S1 is closed and S2 is open for t

.

PLH PHL PHZ

PLZ

PZL

E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z ≈ 50 Ω; t and t ≤ 7 ns for Series

O

r

f

54/74 devices and t and t ≤ 2.5 ns for Series 54S/74S devices.

r

f

F. The outputs are measured one at a time with one input transition per measurement.

Figure 1. Load Circuits and Voltage Waveforms

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

9-Oct-2007

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

CDIP

CFP

Drawing

JM38510/00104BCA

JM38510/00104BDA

JM38510/07001BCA

JM38510/07001BDA

JM38510/30001B2A

JM38510/30001BCA

JM38510/30001BDA

JM38510/30001SCA

JM38510/30001SDA

SN5400J

ACTIVE

J

W

J

14

20

14

1

TBD

A42 SNPB

A42

N / A for Pkg Type

CDIP

CFP

A42 SNPB

A42

W

FK

J

LCCC

CDIP

CFP

POST-PLATE N / A for Pkg Type

A42 SNPB

A42

N / A for Pkg Type

W

J

CDIP

CFP

A42 SNPB

A42

W

J

CDIP

SOIC

A42 SNPB

SN54LS00J

J

SN54S00J

J

SN7400D

D

50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN7400DE4

SN7400DG4

SN7400DR

ACTIVE

SOIC

PDIP

D

N

14

50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN7400DRE4

SN7400DRG4

SN7400N

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

25

Pb-Free

(RoHS)

CU NIPDAU N / A for Pkg Type

SN7400N3

OBSOLETE

ACTIVE

PDIP

N

14

TBD

Call TI

SN7400NE4

Pb-Free

(RoHS)

CU NIPDAU N / A for Pkg Type

SN7400NSR

SN7400NSRE4

SN7400NSRG4

SN74LS00D

ACTIVE

SO

NS

D

14

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SO

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SOIC

50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74LS00DBLE

SN74LS00DBR

OBSOLETE

ACTIVE

SSOP

DB

14

TBD

Call TI

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74LS00DBRE4

SN74LS00DBRG4

SN74LS00DE4

ACTIVE

SSOP

SOIC

DB

D

14

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74LS00DG4

D

50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

9-Oct-2007

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

no Sb/Br)

SN74LS00DR

SN74LS00DRE4

SN74LS00DRG4

ACTIVE

SOIC

D

14

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74LS00J

SN74LS00N

OBSOLETE

ACTIVE

CDIP

PDIP

J

14

TBD

Call TI

N

25

Pb-Free

(RoHS)

CU NIPDAU N / A for Pkg Type

SN74LS00NE4

SN74LS00NSR

SN74LS00NSRG4

SN74LS00PSR

SN74LS00PSRE4

SN74LS00PSRG4

SN74S00D

ACTIVE

PDIP

SO

N

NS

PS

D

14

8

Pb-Free

(RoHS)

CU NIPDAU N / A for Pkg Type

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SO

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SO

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SO

8

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SO

8

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SOIC

PDIP

14

50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74S00DE4

SN74S00DG4

SN74S00DR

D

50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

D

50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74S00DRE4

SN74S00DRG4

SN74S00N

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

N

25

Pb-Free

(RoHS)

CU NIPDAU N / A for Pkg Type

SN74S00N3

OBSOLETE

ACTIVE

PDIP

N

14

TBD

Call TI

SN74S00NE4

Pb-Free

(RoHS)

CU NIPDAU N / A for Pkg Type

SN74S00NSR

SN74S00NSRE4

SN74S00NSRG4

SN74S00PSR

ACTIVE

SO

NS

PS

14

8

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74S00PSRE4

SN74S00PSRG4

8

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

8

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

9-Oct-2007

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

CDIP

CFP

Drawing

SNJ5400J

SNJ5400W

ACTIVE

OBSOLETE

ACTIVE

J

W

WA

FK

J

14

20

14

20

14

1

TBD

A42 SNPB

A42

N / A for Pkg Type

SNJ5400WA

SNJ54LS00FK

SNJ54LS00J

SNJ54LS00W

SNJ54S00FK

SNJ54S00J

SNJ54S00W

CFP

A42

LCCC

CDIP

CFP

1

POST-PLATE N / A for Pkg Type

A42 SNPB

A42

N / A for Pkg Type

W

FK

J

LCCC

CDIP

CFP

POST-PLATE N / A for Pkg Type

A42 SNPB

A42

N / A for Pkg Type

W

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com

4-Oct-2007

TAPE AND REEL BOX INFORMATION

Device

Package Pins

Site

Reel

A0 (mm)

B0 (mm)

K0 (mm)

P1

W

Pin1

Diameter Width

(mm) (mm) Quadrant

(mm)

330

(mm)

16

SN7400DR

SN74LS00DBR

SN74LS00DR

SN74LS00NSR

SN74LS00PSR

SN74S00DR

D

14

8

SITE 41

6.5

8.2

6.5

8.2

6.5

8.2

9.0

6.6

2.1

2.5

2.1

2.5

2.1

2.5

8

16

Q1

DB

D

16

12

8

16

9.0

NS

PS

D

16

10.5

6.6

12

8

16

14

8

16

9.0

SN74S00NSR

SN74S00PSR

NS

PS

16

10.5

6.6

12

16

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

4-Oct-2007

Device

Package

Pins

Site

Length (mm) Width (mm) Height (mm)

SN7400DR

SN74LS00DBR

SN74LS00DR

SN74LS00NSR

SN74LS00PSR

SN74S00DR

D

14

8

SITE 41

346.0

33.0

DB

D

NS

PS

D

14

8

SN74S00NSR

SN74S00PSR

NS

PS

Pack Materials-Page 2

MECHANICAL DATA

MLCC006B – OCTOBER 1996

FK (S-CQCC-N**)

LEADLESS CERAMIC CHIP CARRIER

28 TERMINAL SHOWN

A

B

NO. OF

TERMINALS

**

18 17 16 15 14 13 12

MIN

MAX

MIN

MAX

0.342

(8,69)

0.358

(9,09)

0.307

(7,80)

0.358

(9,09)

19

20

11

10

9

20

28

44

52

68

84

0.442

(11,23)

0.458

(11,63)

0.406

(10,31)

0.458

(11,63)

21

B SQ

22

0.640

(16,26)

0.660

(16,76)

0.495

(12,58)

0.560

(14,22)

8

A SQ

23

0.739

(18,78)

0.761

(19,32)

0.495

(12,58)

0.560

(14,22)

7

24

25

6

0.938

(23,83)

0.962

(24,43)

0.850

(21,6)

0.858

(21,8)

5

1.141

(28,99)

1.165

(29,59)

1.047

(26,6)

1.063

(27,0)

26 27 28

1

2

3

4

0.080 (2,03)

0.064 (1,63)

0.020 (0,51)

0.010 (0,25)

0.020 (0,51)

0.010 (0,25)

0.055 (1,40)

0.045 (1,14)

0.035 (0,89)

0.045 (1,14)

0.035 (0,89)

0.028 (0,71)

0.022 (0,54)

0.050 (1,27)

4040140/D 10/96

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a metal lid.

D. The terminals are gold plated.

E. Falls within JEDEC MS-004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38

0,22

0,65

28

M

0,15

15

0,25

0,09

5,60

5,00

8,20

7,40

Gage Plane

1

14

0,25

A

0°–ā8°

0,95

0,55

Seating Plane

0,10

2,00 MAX

0,05 MIN

PINS **

14

16

20

24

28

30

38

DIM

6,50

5,90

6,50

5,90

7,50

8,50

7,90

10,50

9,90

10,50 12,90

A MAX

A MIN

6,90

9,90

12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-150

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements,

improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.

Customers should obtain the latest relevant information before placing orders and should verify that such information is current and

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s

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TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and

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TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are

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TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products

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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:

Products

Amplifiers

Data Converters

DSP

Applications

Audio

amplifier.ti.com

dataconverter.ti.com

dsp.ti.com

www.ti.com/audio

Automotive

Broadband

Digital Control

Military

www.ti.com/automotive

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/military

Interface

interface.ti.com

logic.ti.com

Logic

Power Mgmt

Microcontrollers

RFID

power.ti.com

Optical Networking

Security

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

microcontroller.ti.com

www.ti-rfid.com

www.ti.com/lpw

Telephony

Low Power

Wireless

Video & Imaging

Wireless

www.ti.com/wireless

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	SN5400_07
厂家：	TEXAS INSTRUMENTS
描述：	QUADRUPLE 2-INPUT POSITIVE-NAND GATES 四路2输入正与非门输入元件
文件：	总21页 (文件大小：738K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SN5400_07 [TI]

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