SN54147_15 [TI]
10-LINE TO 4-LINE AND 8-LINE PRIORITY ENCODERS;
| 型号： | SN54147_15 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 10-LINE TO 4-LINE AND 8-LINE PRIORITY ENCODERS 编码器 |
| 文件： | 总22页 (文件大小：621K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SDLS053B − OCTOBER 1976 − REVISED MAY 2004
’147, ’LS147
’148, ’LS148
D
D
Encode 10-Line Decimal to 4-Line BCD
D
D
Encode 8 Data Lines to 3-Line Binary
(Octal)
Applications Include:
− Keyboard Encoding
− Range Selection
Applications Include:
− n-Bit Encoding
− Code Converters and Generators
SN54147, SN54LS147 . . . J OR W PACKAGE
SN74147, SN74LS147 . . . D OR N PACKAGE
(TOP VIEW)
SN54148, SN54LS148 . . . J OR W PACKAGE
SN74148, SN74LS148 . . . D, N, OR NS PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
V
4
5
4
CC
CC
E0
GS
3
NC
D
3
5
6
6
7
7
8
2
2
EI
1
1
A2
A1
GND
C
0
9
B
A0
A
GND
SN54LS147 . . . FK PACKAGE
(TOP VIEW)
SN54LS148 . . . FK PACKAGE
(TOP VIEW)
3
2
1 20 19
18
3
2
1 20 19
18
GS
3
D
3
6
7
4
5
6
7
8
4
5
6
7
8
6
7
17
17
16
15
14
NC
2
16 NC
15
NC
8
NC
EI
2
1
14
1
C
A2
9 10 11 12 13
9 10 11 12 13
NC − No internal connection
TYPICAL
DATA
DELAY
TYPICAL
POWER
TYPE
’147
DISSIPATION
225 mW
190 mW
60 mW
10 ns
10 ns
15 ns
15 ns
’148
’LS147
’LS148
60 mW
NOTE: The SN54147, SN54LS147, SN54148, SN74147, SN74LS147, and SN74148 are obsolete and are no longer supplied.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2004, Texas Instruments Incorporated
ꢒ ꢜ ꢧ ꢟ ꢞꢪ ꢥꢤ ꢢꢣ ꢤꢞ ꢠꢧ ꢩꢛ ꢡꢜ ꢢ ꢢꢞ ꢌꢋ ꢈꢐ ꢖꢗ ꢱ ꢐꢕꢇꢂ ꢕꢂꢆ ꢡꢩꢩ ꢧꢡ ꢟ ꢡ ꢠꢦ ꢢꢦꢟ ꢣ ꢡ ꢟ ꢦ ꢢꢦ ꢣꢢꢦ ꢪ
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ꢢ ꢦ ꢣ ꢢꢛ ꢜꢰ ꢞꢝ ꢡ ꢩꢩ ꢧꢡ ꢟ ꢡ ꢠ ꢦ ꢢ ꢦ ꢟ ꢣ ꢫ
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ꢥ ꢜꢩ ꢦꢣꢣ ꢞ ꢢꢬꢦ ꢟ ꢮꢛ ꢣꢦ ꢜ ꢞꢢꢦ ꢪꢫ ꢒ ꢜ ꢡꢩ ꢩ ꢞ ꢢꢬꢦ ꢟ ꢧꢟ ꢞ ꢪꢥꢤ ꢢꢣ ꢆ ꢧꢟ ꢞ ꢪꢥꢤ ꢢꢛꢞ ꢜ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢀꢁ ꢂ ꢃꢄ ꢃ ꢇ ꢆ ꢀ ꢁꢂ ꢃ ꢈꢀ ꢄ ꢃꢅ ꢆ ꢀ ꢁꢂ ꢃ ꢈ ꢀꢄ ꢃ ꢇ
ꢀꢁ ꢅ ꢃꢄꢃ ꢇ ꢉꢊ ꢋ ꢌꢍ ꢍꢎ ꢅ ꢏꢆ ꢀ ꢁꢅ ꢃ ꢈꢀ ꢄꢃ ꢅ ꢆ ꢀꢁꢅ ꢃ ꢈ ꢀꢄ ꢃ ꢇ
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SDLS053B − OCTOBER 1976 − REVISED MAY 2004
description/ordering information
These TTL encoders feature priority decoding of the inputs to ensure that only the highest-order data line is
encoded. The ’147 and ’LS147 devices encode nine data lines to four-line (8-4-2-1) BCD. The implied decimal
zero condition requires no input condition, as zero is encoded when all nine data lines are at a high logic level.
The ’148 and ’LS148 devices encode eight data lines to three-line (4-2-1) binary (octal). Cascading circuitry
(enable input EI and enable output EO) has been provided to allow octal expansion without the need for external
circuitry. For all types, data inputs and outputs are active at the low logic level. All inputs are buffered to represent
one normalized Series 54/74 or 54/74LS load, respectively.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP − N
SOIC − D
Tube
SN74LS148N
SN74LS148D
SN74LS148DR
SN74LS148NSR
SNJ54LS148J
SNJ54LS148W
SNJ54LS148FK
SN74LS148N
Tube
0°C to 70°C
LS148
Tape and reel
Tape and reel
Tube
SOP − NS
CDIP − J
74LS148
SNJ54LS148J
SNJ54LS148W
SNJ54LS148FK
−55°C to 125°C
CFP − W
LCCC − FK
Tube
Tube
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE − ’147, ’LS147
INPUTS
OUTPUTS
1
H
X
X
X
X
X
X
2
H
X
X
X
X
X
X
3
H
X
X
X
X
X
X
4
H
X
X
X
X
X
L
5
H
X
X
X
X
L
6
H
X
X
X
L
7
H
X
X
L
8
H
X
L
9
H
L
D
H
L
C
H
H
H
L
B
H
H
H
L
A
H
L
H
H
H
H
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
L
L
H
L
H
H
L
H
H
H
L
H
X
X
L
X
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
H
L
H
H
H = high logic level, L = low logic level, X = irrelevant
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SDLS053B − OCTOBER 1976 − REVISED MAY 2004
FUNCTION TABLE − ’148, ’LS148
INPUTS
OUTPUTS
EI
H
L
0
X
H
X
X
X
X
X
1
X
H
X
X
X
X
X
2
X
H
X
X
X
X
X
3
X
H
X
X
X
X
L
4
X
H
X
X
X
L
5
X
H
X
X
L
6
X
H
X
L
7
X
H
L
A2
A1
H
H
L
A0
H
H
L
GS
H
H
L
EO
H
L
H
H
L
L
H
H
H
H
H
L
H
H
H
H
L
L
H
L
L
L
H
H
H
L
H
H
L
L
L
H
H
L
H
L
L
L
H
H
L
L
L
L
X
X
L
X
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
L
L
L
L
H
H
H
H
H
H = high logic level, L = low logic level, X = irrelevant
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢀꢁ ꢂ ꢃꢄ ꢃ ꢇ ꢆ ꢀ ꢁꢂ ꢃ ꢈꢀ ꢄ ꢃꢅ ꢆ ꢀ ꢁꢂ ꢃ ꢈ ꢀꢄ ꢃ ꢇ
ꢀꢁ ꢅ ꢃꢄꢃ ꢇ ꢉꢊ ꢋ ꢌꢍ ꢍꢎ ꢅ ꢏꢆ ꢀ ꢁꢅ ꢃ ꢈꢀ ꢄꢃ ꢅ ꢆ ꢀꢁꢅ ꢃ ꢈ ꢀꢄ ꢃ ꢇ
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SDLS053B − OCTOBER 1976 − REVISED MAY 2004
’147, ’LS147 logic diagram (positive logic)
(11)
1
(12)
2
(9)
A
(13)
3
(1)
4
(7)
B
(2)
5
(3)
6
(4)
7
(6)
C
(5)
8
(14)
D
(10)
9
Pin numbers shown are for D, J, N, and W packages.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SDLS053B − OCTOBER 1976 − REVISED MAY 2004
’148, ’LS148 logic diagram (positive logic)
(10)
0
(15)
EO
(14)
G5
(11)
1
(12)
2
(9)
A0
(13)
3
(1)
4
(7)
A1
(2)
5
(3)
6
(4)
7
(6)
A2
(5)
EI
Pin numbers shown are for D, J, N, NS, and W packages.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢀꢁ ꢂ ꢃꢄ ꢃ ꢇ ꢆ ꢀ ꢁꢂ ꢃ ꢈꢀ ꢄ ꢃꢅ ꢆ ꢀ ꢁꢂ ꢃ ꢈ ꢀꢄ ꢃ ꢇ
ꢀꢁ ꢅ ꢃꢄꢃ ꢇ ꢉꢊ ꢋ ꢌꢍ ꢍꢎ ꢅ ꢏꢆ ꢀ ꢁꢅ ꢃ ꢈꢀ ꢄꢃ ꢅ ꢆ ꢀꢁꢅ ꢃ ꢈ ꢀꢄ ꢃ ꢇ
ꢃꢄ
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SDLS053B − OCTOBER 1976 − REVISED MAY 2004
schematics of inputs and outputs
’147, ’148
EQUIVALENT OF EACH INPUT
CC
TYPICAL OF ALL OUTPUTS
V
V
CC
ꢀ ꢁ Ω NOM
R
eq
Input
Output
0 input (’148): R = 2 kΩ NOM
eq
All other inputs: R = 4 kΩ NOM
eq
’LS147, ’LS148
TYPICAL OF ALL OUTPUTS
EQUIVALENT OF ALL INPUTS
V
CC
V
CC
120 Ω NOM
R
eq
Input
Output
’LS148 inputs 1–7: R = 9 kΩ NOM
eq
All other inputs: R = 18 kΩ NOM
eq
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢍ
ꢕ
ꢄ
ꢎ
ꢃ
ꢅ
ꢋ
ꢇ
ꢆ
ꢀ
ꢀ
ꢑ
ꢁ
ꢂ
ꢃ
ꢗ
ꢃ
ꢈ
ꢈ
ꢀ
ꢀ
ꢄ
ꢗ
ꢄ
ꢃ
ꢃ
ꢅ
ꢘ
ꢅ
ꢆ
ꢆ
ꢀ
ꢀ
ꢁ
ꢁ
ꢙ
ꢂ
ꢅ
ꢒ
ꢃ
ꢃ
ꢈ
ꢈ
ꢔ
ꢀ
ꢀ
ꢑ
ꢄ
ꢄ
ꢗ
ꢃ
ꢃ
ꢀ
ꢇ
ꢇ
ꢀ
ꢁ
ꢅ
ꢃ
ꢄ
ꢃ
ꢅ
ꢆ
ꢀ
ꢁ
ꢊ
ꢋ
ꢏ
ꢆ
ꢁ
ꢅ
ꢄ
ꢎ
ꢐ
ꢈ
ꢋ
ꢁ
ꢑ
ꢊ ꢒ
ꢃ
ꢐ
ꢈ
ꢋ
ꢁ
ꢑ
ꢓ
ꢁ
ꢋ
ꢁ
ꢊ
ꢐ
ꢈ
ꢁ
ꢖ
ꢋ
ꢒ
ꢋ
ꢊ
ꢑ
ꢁ
SDLS053B − OCTOBER 1976 − REVISED MAY 2004
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage, V : ’147, ’148 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
I
’LS147, ’LS148 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Inter-emitter voltage: ’148 only (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Package thermal impedance θ (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
JA
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Storage temperature range, T
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Voltage values, except inter-emitter voltage, are with respect to the network ground terminal.
2. This is the voltage between two emitters of a multiple-emitter transistor. For ’148 circuits, this rating applies between any two of the
eight data lines, 0 through 7.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 4)
SN54’
SN74’
SN54LS’
SN74LS’
UNIT
MIN NOM MAX
MIN NOM MAX
MIN NOM MAX
MIN NOM MAX
V
Supply voltage
4.5
5
5.5 4.75
−800
5
5.25
−800
16
4.5
5
5.5 4.75
−400
5
5.25
−400
8
V
CC
OH
OL
I
I
High-level output current
Low-level output current
Operating free-air temperature
µA
mA
°C
16
4
T
A
−55
125
0
70
−55
125
0
70
NOTE 4: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢆ
ꢀꢁ ꢂ ꢃꢄ ꢃ ꢇ ꢆ ꢀ ꢁꢂ ꢃ ꢈꢀ ꢄ ꢃꢅ ꢆ ꢀ ꢁꢂ ꢃ ꢈ ꢀꢄ ꢃ ꢇ
ꢀꢁ ꢅ ꢃꢄꢃ ꢇ ꢉꢊ ꢋ ꢌꢍ ꢍꢎ ꢅ ꢏꢆ ꢀ ꢁꢅ ꢃ ꢈꢀ ꢄꢃ ꢅ ꢆ ꢀꢁꢅ ꢃ ꢈ ꢀꢄ ꢃ ꢇ
ꢃ
ꢄ
ꢄ
ꢎ
ꢐ
ꢈ
ꢋ
ꢁ
ꢑ
ꢊ
ꢒ
ꢃ
ꢐ
ꢈ
ꢋ
ꢁ
ꢑ
ꢓ
ꢁ
ꢔ
ꢇ
ꢐ
ꢈ
ꢋ
ꢁ
ꢑ
ꢊ ꢒ
ꢕ
ꢐ
ꢈ
ꢋ
ꢁ
ꢑ
ꢖ
ꢗ
ꢋ
ꢒ
ꢗ
ꢋ
ꢊ
ꢘ
ꢑ
ꢁ
ꢙ
ꢒ
ꢔ
ꢑ
ꢗ
ꢀ
SDLS053B − OCTOBER 1976 − REVISED MAY 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
’147
’148
†
PARAMETER
TEST CONDITIONS
UNIT
‡
‡
MIN TYP
MAX
MIN TYP
MAX
V
V
V
High-level input voltage
Low-level input voltage
Input clamp voltage
2
2
V
V
V
IH
0.8
0.8
IL
V
= MIN,
= MIN,
I = −12 mA
−1.5
−1.5
IK
CC
I
V
V
V
= 2 V,
= −800 µA
CC
IL
IH
V
OH
V
OL
High-level output voltage
Low-level output voltage
2.4
3.3
2.4
3.3
V
V
= 0.8 V,
I
OH
V
V
= MIN,
= 0.8 V,
V
= 2 V,
= 16 mA
CC
IL
IH
0.2
0.4
1
0.2
0.4
1
I
OL
Input current at maximum input
voltage
I
I
V
V
V
= MIN,
= MAX,
= MAX,
V = 5.5 V
I
mA
CC
0 input
40
80
High-level input
current
I
IH
V = 2.4 V
I
µA
CC
CC
Any input except 0
0 input
40
−1.6
−3.2
−85
60
Low-level input
current
I
I
I
V = 0.4 V
I
mA
mA
mA
IL
Any input except 0
−1.6
−85
70
§
Short-circuit output current
V
V
= MAX
= MAX
−35
−35
OS
CC
CC
Condition 1
Condition 2
50
42
40
35
CC
Supply current
(See Note 5)
62
55
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡
§
All typical values are at V
Not more than one output should be shorted at a time.
= 5 V, T = 25°C.
CC
A
NOTE 5: For ’147, I
(Condition 1) is measured with input 7 grounded, other inputs and outputs open; I
(Condition 2) is measured with all
CC
CC
CC
(Condition 1) is measured with inputs 7 and EI grounded, other inputs and outputs open; I
inputs and outputs open. For ’148, I
(Condition 2) is measured with all inputs and outputs open.
CC
SN54147, SN74147 switching characteristics, V
= 5 V, T = 255C (see Figure 1)
CC
A
FROM
TO
TEST
PARAMETER
WAVEFORM
MIN
TYP
MAX
UNIT
(INPUT)
(OUTPUT)
CONDITIONS
t
t
t
t
9
7
14
11
19
19
PLH
PHL
PLH
PHL
Any
Any
Any
Any
In-phase output
ns
ns
C
R
= 15 pF,
= 400 Ω
L
L
13
12
Out-of-phase output
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢌ
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ꢂ
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ꢍ
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ꢇ
ꢆ
ꢀ
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ꢈ
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ꢃ
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ꢆ
ꢆ
ꢀ
ꢀ
ꢁ
ꢁ
ꢙ
ꢂ
ꢅ
ꢒ
ꢃ
ꢃ
ꢈ
ꢈ
ꢔ
ꢀ
ꢀ
ꢑ
ꢄ
ꢄ
ꢗ
ꢃ
ꢃ
ꢀ
ꢇ
ꢇ
ꢀ
ꢁ
ꢅ
ꢃ
ꢄ
ꢃ
ꢅ
ꢆ
ꢀ
ꢁ
ꢊ
ꢋ
ꢏ
ꢆ
ꢁ
ꢅ
ꢄ
ꢎ
ꢐ
ꢈ
ꢋ
ꢁ
ꢑ
ꢊ
ꢒ
ꢃ
ꢐ
ꢈ
ꢋ
ꢁ
ꢑ
ꢓ
ꢁ
ꢋ
ꢁ
ꢊ
ꢐ
ꢈ
ꢁ
ꢖ
ꢋ
ꢒ
ꢋ
ꢊ
ꢑ
ꢁ
SDLS053B − OCTOBER 1976 − REVISED MAY 2004
SN54148, SN74148 switching characteristics, V
= 5 V, T = 255C (see Figure 1)
CC
A
FROM
TO
TEST
†
PARAMETER
WAVEFORM
In-phase output
Out-of-phase output
Out-of-phase output
In-phase output
In-phase output
In-phase output
In-phase output
MIN
TYP
MAX
UNIT
ns
(INPUT)
(OUTPUT)
CONDITIONS
t
t
t
t
t
t
t
t
t
t
t
t
t
t
10
9
15
14
19
19
10
25
30
25
15
15
12
15
15
30
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
1–7
1–7
0–7
0–7
EI
A0, A1, or A2
13
12
6
A0, A1, or A2
ns
EO
GS
ns
14
18
14
10
10
8
C
R
= 15 pF,
= 400 Ω
L
L
ns
A0, A1, or A2
GS
ns
EI
ns
10
10
17
EI
EO
ns
†
t
t
= propagation delay time, low-to-high-level output.
= propagation delay time, high-to-low-level output.
PLH
PHL
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LS’
SN74LS’
†
PARAMETER
TEST CONDITIONS
UNIT
‡
‡
MIN TYP
MAX
MIN TYP
MAX
V
V
V
High-level input voltage
Low-level input voltage
Input clamp voltage
2
2
V
V
V
IH
0.7
0.8
IL
V
= MIN,
= MIN,
I = −18 mA
−1.5
−1.5
IK
CC
I
V
V
V
= 2 V,
= −400 µA
CC
IL
IH
V
High-level output voltage
2.5
3.4
2.7
3.4
V
OH
OL
= 0.8 V,
I
OH
V
V
V
= MIN,
= 2 V,
I
= 4 mA
= 8 mA
0.25
0.4
0.25
0.35
0.4
0.5
0.2
0.1
CC
IH
IL
OL
OL
V
Low-level output voltage
V
I
= V MAX
IL
Input current at
maximum input
voltage
’LS148 inputs 1–7
All other inputs
0.2
0.1
I
I
V
CC
= MAX,
V = 7 V
I
mA
I
’LS148 inputs 1–7
All other inputs
40
20
40
20
High-level input
current
V
V
= MAX,
= MAX,
V = 2.7 V
I
µA
IH
CC
’LS148 inputs 1–7
All other inputs
−0.8
−0.4
−100
20
−0.8
−0.4
−100
20
Low-level input
current
I
I
I
V = 0.4 V
I
mA
mA
mA
IL
CC
§
Short-circuit output current
V
V
= MAX
= MAX
−20
−20
OS
CC
CC
Condition 1
Condition 2
12
10
12
10
CC
Supply current
(See Note 6)
17
17
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡
§
All typical values are at V
Not more than one output should be shorted at a time.
= 5 V, T = 25°C.
CC
A
NOTE 6: For ’LS147, I
CC
(Condition 1) is measured with input 7 grounded, other inputs and outputs open; I
(Condition 2) is measured with
CC
(Condition 1) is measured with inputs 7 and EI grounded, other inputs and outputs open;
all inputs and outputs open. For ’LS148, I
CC
I
(Condition 2) is measured with all inputs and outputs open.
CC
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢀꢁ ꢂ ꢃꢄ ꢃ ꢇ ꢆ ꢀ ꢁꢂ ꢃ ꢈꢀ ꢄ ꢃꢅ ꢆ ꢀ ꢁꢂ ꢃ ꢈ ꢀꢄ ꢃ ꢇ
ꢀꢁ ꢅ ꢃꢄꢃ ꢇ ꢉꢊ ꢋ ꢌꢍ ꢍꢎ ꢅ ꢏꢆ ꢀ ꢁꢅ ꢃ ꢈꢀ ꢄꢃ ꢅ ꢆ ꢀꢁꢅ ꢃ ꢈ ꢀꢄ ꢃ ꢇ
ꢃ
ꢄ
ꢄ
ꢎ
ꢐ
ꢈ
ꢋ
ꢁ
ꢑ
ꢊ
ꢒ
ꢃ
ꢐ
ꢈ
ꢋ
ꢁ
ꢑ
ꢓ
ꢁ
ꢔ
ꢇ
ꢐ
ꢈ
ꢋ
ꢁ
ꢑ
ꢊ ꢒ
ꢕ
ꢐ
ꢈꢋ
ꢁ
ꢑ
ꢖ
ꢗ
ꢋ
ꢒ
ꢗ
ꢋ
ꢊ
ꢘ
ꢑ
ꢁ
ꢙ
ꢒꢔ
ꢑ
ꢗ
ꢀ
SDLS053B − OCTOBER 1976 − REVISED MAY 2004
SN54LS147, SN74LS147 switching characteristics, V
= 5 V, T = 255C (see Figure 2)
CC
A
FROM
TO
TEST
PARAMETER
WAVEFORM
MIN
TYP
MAX
UNIT
ns
(INPUT)
(OUTPUT)
CONDITIONS
t
t
t
t
12
12
21
15
18
18
33
23
PLH
PHL
PLH
PHL
Any
Any
Any
Any
In-phase output
C
R
= 15 pF,
= 2 kΩ
L
L
Out-of-phase output
ns
SN54LS148, SN74LS148 switching characteristics, V
= 5 V, T = 255C (see Figure 2)
CC
A
FROM
TO
TEST
†
PARAMETER
WAVEFORM
MIN
TYP
MAX
UNIT
ns
(INPUT)
(OUTPUT)
CONDITIONS
t
t
t
t
t
t
t
t
t
t
t
t
t
t
14
15
20
16
7
18
25
36
29
18
40
55
21
25
25
17
36
21
35
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
1–7
1–7
0–7
0–7
EI
A0, A1, or A2
In-phase output
Out-of-phase output
Out-of-phase output
In-phase output
In-phase output
In-phase output
In-phase output
A0, A1, or A2
ns
EO
GS
ns
25
35
9
C
R
= 15 pF,
= 2 kΩ
L
L
ns
16
12
12
14
12
23
A0, A1, or A2
GS
ns
EI
ns
EI
EO
ns
†
t
t
= propagation delay time, low-to-high-level output
= propagation delay time, high-to-low-level output
PLH
PHL
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢈ
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ꢄ
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ꢄ
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ꢃ
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ꢆ
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ꢄ
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ꢃ
ꢃ
ꢀ
ꢇ
ꢇ
ꢀ
ꢁ
ꢅ
ꢃ
ꢄ
ꢃ
ꢅ
ꢆ
ꢀ
ꢁ
ꢊ
ꢋ
ꢏ
ꢆ
ꢁ
ꢅ
ꢄ
ꢎ
ꢐ
ꢈ
ꢋ
ꢁ
ꢑ
ꢊ
ꢒ
ꢃ
ꢐ
ꢈ
ꢋ
ꢁ
ꢑ
ꢓ
ꢁ
ꢋ
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ꢊ
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ꢈ
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SDLS053B − OCTOBER 1976 − REVISED MAY 2004
PARAMETER MEASUREMENT INFORMATION
SERIES 54/74 DEVICES
V
CC
Test
Point
R
L
Test
Point
S1
V
CC
From Output
Under Test
V
CC
(see Note B)
R
L
C
L
(see Note A)
From Output
Under Test
1 kΩ
R
L
(see Note B)
From Output
Under Test
C
Test
Point
C
L
(see Note A)
L
(see Note A)
S2
LOAD CIRCUIT
LOAD CIRCUIT
LOAD CIRCUIT
FOR 2-STATE TOTEM-POLE OUTPUTS
FOR OPEN-COLLECTOR OUTPUTS
FOR 3-STATE OUTPUTS
3 V
High-Level
Timing
Input
1.5 V
1.5 V
1.5 V
1.5 V
Pulse
0 V
t
t
h
w
t
su
3 V
0 V
Low-Level
Pulse
Data
Input
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
Output
Control
(low-level
enabling)
1.5 V
1.5 V
3 V
0 V
Input
1.5 V
1.5 V
t
t
PLZ
PZL
t
t
PHL
PLH
Waveform 1
(see Notes C
and D)
≈1.5 V
In-Phase
1.5 V
V
OH
Output
(see Note D)
V
OL
+ 0.5 V
1.5 V
1.5 V
1.5 V
V
OL
V
OL
t
t
PZH
PHZ
t
t
PLH
PHL
V
OH
Waveform 2
(see Notes C
and D)
V
OH
− 0.5 V
Out-of-Phase
Output
(see Note D)
V
V
OH
1.5 V
1.5 V
≈1.5 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A.
C
includes probe and jig capacitance.
L
B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
D. S1 and S2 are closed for t
, t
, t
, and t
; S1 is open, and S2 is closed for t
PZH
; S1 is closed, and S2 is open for t
.
PLH PHL PHZ
PLZ
PZL
E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z ≈ 50 Ω; t and t ≤ 7 ns for Series
O
r
f
54/74 devices and t and t ≤ 2.5 ns for Series 54S/74S devices.
r
f
F. The outputs are measured one at a time, with one input transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢆ
ꢀꢁ ꢂ ꢃꢄ ꢃ ꢇ ꢆ ꢀ ꢁꢂ ꢃ ꢈꢀ ꢄ ꢃꢅ ꢆ ꢀ ꢁꢂ ꢃ ꢈ ꢀꢄ ꢃ ꢇ
ꢀꢁ ꢅ ꢃꢄꢃ ꢇ ꢉꢊ ꢋ ꢌꢍ ꢍꢎ ꢅ ꢏꢆ ꢀ ꢁꢅ ꢃ ꢈꢀ ꢄꢃ ꢅ ꢆ ꢀꢁꢅ ꢃ ꢈ ꢀꢄ ꢃ ꢇ
ꢃ
ꢄ
ꢄ
ꢎ
ꢐ
ꢈ
ꢋ
ꢁ
ꢑ
ꢊ
ꢒ
ꢃ
ꢐ
ꢈ
ꢋ
ꢁ
ꢑ
ꢓ
ꢁ
ꢔ
ꢇ
ꢐ
ꢈ
ꢋ
ꢁ
ꢑ
ꢊ ꢒ
ꢕ
ꢐ
ꢈ
ꢋ
ꢁ
ꢑ
ꢖ
ꢗ
ꢋ
ꢒ
ꢗ
ꢋ
ꢊ
ꢘ
ꢑ
ꢁ
ꢙ
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ꢑ
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ꢀ
SDLS053B − OCTOBER 1976 − REVISED MAY 2004
PARAMETER MEASUREMENT INFORMATION
SERIES 54LS/74LS DEVICES
V
CC
Test
Point
R
L
Test
Point
S1
V
CC
From Output
Under Test
V
CC
(see Note B)
R
L
C
L
(see Note A)
From Output
Under Test
5 kΩ
R
L
(see Note B)
From Output
Under Test
C
Test
Point
C
L
(see Note A)
L
(see Note A)
S2
LOAD CIRCUIT
LOAD CIRCUIT
LOAD CIRCUIT
FOR 2-STATE TOTEM-POLE OUTPUTS
FOR OPEN-COLLECTOR OUTPUTS
FOR 3-STATE OUTPUTS
3 V
High-Level
Timing
Input
1.3 V
1.3 V
1.3 V
1.3 V
Pulse
0 V
t
t
h
w
t
su
3 V
0 V
Low-Level
Pulse
Data
Input
1.3 V
1.3 V
1.3 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
3 V
0 V
Control
(low-level
enabling)
1.3 V
1.3 V
3 V
0 V
Input
1.3 V
1.3 V
t
t
PLZ
PZL
t
t
PHL
PLH
Waveform 1
(see Notes C
and D)
≈1.5 V
In-Phase
Output
(see Note D)
1.3 V
V
V
OH
V
OL
+ 0.5 V
1.3 V
1.3 V
1.3 V
V
OL
t
PHZ
OL
t
PZH
t
t
PLH
PHL
V
OH
Waveform 2
(see Notes C
and D)
V
OH
− 0.5 V
Out-of-Phase
Output
(see Note D)
V
V
OH
1.3 V
1.3 V
≈1.5 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A.
C
includes probe and jig capacitance.
L
B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
D. S1 and S2 are closed for t
, t
, t
, and t
; S1 is open, and S2 is closed for t
; S1 is closed, and S2 is open for t .
PLH PHL PHZ
PLZ
PZH
PZL
E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples.
F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z ≈ 50 Ω, t ≤ 1.5 ns, t ≤ 2.6 ns.
O
r
f
G. The outputs are measured one at a time, with one input transition per measurement.
Figure 2. Load Circuits and Voltage Waveforms
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢁ
ꢅ
ꢔ
ꢂ
ꢃ
ꢇ
ꢃ
ꢄ
ꢐ
ꢄ
ꢃ
ꢈ
ꢃ
ꢇ
ꢅ
ꢆ
ꢉ
ꢑ
ꢀ
ꢁ
ꢌ
ꢒ
ꢂ
ꢍ
ꢃ
ꢍ
ꢕ
ꢄ
ꢎ
ꢃ
ꢅ
ꢋ
ꢇ
ꢆ
ꢀ
ꢀ
ꢑ
ꢁ
ꢂ
ꢃ
ꢗ
ꢃ
ꢈ
ꢈ
ꢀ
ꢀ
ꢄ
ꢗ
ꢄ
ꢃ
ꢃ
ꢅ
ꢘ
ꢅ
ꢆ
ꢆ
ꢀ
ꢀ
ꢁ
ꢁ
ꢙ
ꢂ
ꢅ
ꢒ
ꢃ
ꢃ
ꢈ
ꢈ
ꢔ
ꢀ
ꢀ
ꢑ
ꢄ
ꢄ
ꢗ
ꢃ
ꢃ
ꢀ
ꢇ
ꢇ
ꢀ
ꢁ
ꢅ
ꢃ
ꢄ
ꢃ
ꢅ
ꢆ
ꢀ
ꢁ
ꢊ
ꢋ
ꢏ
ꢆ
ꢁ
ꢅ
ꢄ
ꢎ
ꢐ
ꢈꢋ
ꢁ
ꢑ
ꢊ ꢒ
ꢃ
ꢐ
ꢈ
ꢋ
ꢁ
ꢑ
ꢓ
ꢁ
ꢋ
ꢁ
ꢊ
ꢐ
ꢈ
ꢁ
ꢖ
ꢋ
ꢒ
ꢋ
ꢊ
ꢑ
ꢁ
SDLS053B − OCTOBER 1976 − REVISED MAY 2004
APPLICATION INFORMATION
16-Line Data (active low)
0
0
1
1
2
2
3
3
4
5
5
6
6
7
8
0
9 10 11 12 13 14 15
Enable
(active low)
4
7 EI
1
2
3
4
5
6
7 EI
GS
’148/’LS148
A1
’148/LS148
EO A0
A2 GS
EO
A0
A1
A2
’08/’LS08
Priority Flag
(active low)
0
1
2
Encoded Data (active low)
16-Line Data (active low)
3
0
0
1
1
2
2
3
4
5
6
6
7
8
0
9 10 11 12 13 14 15
Enable
(active low)
3
4
5
7 EI
1
2
3
4
5
6
7 EI
GS
’148/’LS148
A1
’148/’LS148
EO A0
A2 GS
EO
A0
A1
A2
’HC00
Priority Flag
(active high)
0
1
2
3
Encoded Data (active high)
Figure 3. Priority Encoder for 16 Bits
Because the ’147/’LS147 and ’148/’LS148 devices are combinational logic circuits, wrong addresses can appear
during input transients. Moreover, for the ’148/’LS148 devices, a change from high to low at EI can cause a transient
low on GS when all inputs are high. This must be considered when strobing the outputs.
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
CFP
Drawing
78027012A
7802701EA
ACTIVE
ACTIVE
FK
J
20
16
16
20
16
16
16
16
16
16
16
16
16
16
16
1
1
1
1
1
1
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Call TI
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Call TI
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Call TI
7802701FA
ACTIVE
W
FK
J
JM38510/36001B2A
JM38510/36001BEA
JM38510/36001BFA
SN54148J
ACTIVE
LCCC
CDIP
CFP
ACTIVE
ACTIVE
W
J
OBSOLETE
ACTIVE
CDIP
CDIP
PDIP
CDIP
PDIP
PDIP
SOIC
PDIP
SOIC
SN54LS148J
SN74147N
J
1
Level-NC-NC-NC
Call TI
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
ACTIVE
N
J
SN74148J
Call TI
SN74148N
N
N
D
N
D
Call TI
SN74148N3
Call TI
SN74LS147DR
SN74LS147N
SN74LS148D
Call TI
Call TI
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LS148DE4
SN74LS148DR
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
D
D
D
16
16
16
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LS148DRE4
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LS148J
SN74LS148N
OBSOLETE
ACTIVE
CDIP
PDIP
J
16
16
TBD
Call TI
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N
25
25
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
SN74LS148N3
SN74LS148NE4
OBSOLETE
ACTIVE
PDIP
PDIP
N
N
16
16
TBD
Call TI
Call TI
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
SN74LS148NSR
ACTIVE
ACTIVE
SO
SO
NS
NS
16
16
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LS148NSRE4
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SNJ54148J
SNJ54148W
OBSOLETE
OBSOLETE
ACTIVE
CDIP
CFP
J
W
FK
J
16
16
20
16
16
TBD
TBD
TBD
TBD
TBD
Call TI
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SNJ54LS148FK
SNJ54LS148J
SNJ54LS148W
LCCC
CDIP
CFP
1
1
1
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
ACTIVE
ACTIVE
W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
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Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
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Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
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Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
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Amplifiers
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Logic
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microcontroller.ti.com
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Wireless
www.ti.com/wireless
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Post Office Box 655303 Dallas, Texas 75265
Copyright 2005, Texas Instruments Incorporated
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