SN54ABT16841WD [TI]
20-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS; 20位总线接口D类锁存器具有三态输出
| 型号： | SN54ABT16841WD |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 20-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS |
| 文件： | 总7页 (文件大小：112K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54ABT16841, SN74ABT16841
20-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS222C – SEPTEMBER 1992 – REVISED MAY 1997
SN54ABT16841 . . . WD PACKAGE
SN74ABT16841 . . . DL PACKAGE
(TOP VIEW)
Members of the Texas Instruments
Widebus Family
State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1OE
1Q1
1Q2
GND
1Q3
1Q4
1LE
1D1
1D2
GND
1D3
1D4
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
2
3
4
5
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
6
7
V
V
Typical V
< 0.8 V at V
(Output Ground Bounce)
CC
CC
OLP
8
1Q5
1Q6
1Q7
GND
1Q8
1Q9
1Q10
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6
1D5
1D6
1D7
GND
1D8
1D9
1D10
2D1
2D2
2D3
GND
2D4
2D5
2D6
= 5 V, T = 25°C
CC
A
9
High-Impedance State During Power Up
and Power Down
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Distributed V
Minimizes High-Speed Switching Noise
and GND Pin Configuration
CC
Flow-Through Architecture Optimizes PCB
Layout
High-Drive Outputs (–32-mA I , 64-mA I
)
OL
OH
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Package and
380-mil Fine-Pitch Ceramic Flat (WD)
Package Using 25-mil Center-to-Center
Spacings
V
V
CC
CC
description
2Q7
2Q8
GND
2Q9
2Q10
2OE
2D7
2D8
GND
2D9
2D10
2LE
These 20-bit latches feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The ’ABT16841 can be used as two 10-bit latches or one 20-bit latch. The 20 transparent D-type latches provide
true data at the outputs. While the latch-enable (1LE or 2LE) input is high, the Q outputs of the corresponding
10-bit latch follow the D inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D
inputs.
A buffered output-enable (1OE or 2OE) input can be used to place the outputs of the corresponding 10-bit latch
in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state,
the outputs neither load nor drive the bus lines significantly.
The output-enable input does not affect the internal operation of the latches. Old data can be retained or new
data can be entered while the outputs are in the high-impedance state.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT16841, SN74ABT16841
20-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS222C – SEPTEMBER 1992 – REVISED MAY 1997
description (continued)
When V
is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 2.1 V, OE should be tied to V
the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup resistor;
CC
The SN54ABT16841 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT16841 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 10-bit latch)
INPUTS
OUTPUT
Q
OE
L
LE
H
H
L
D
H
L
H
L
L
L
X
X
Q
0
H
X
Z
†
logic symbol
1
EN2
C1
1OE
1LE
56
28
29
EN4
C3
2OE
2LE
55
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
30
2
3
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
1D9
1D10
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
2D9
2D10
1D
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
1Q9
1Q10
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
2Q9
2Q10
2
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
26
27
4
3D
†
ThissymbolisinaccordancewithANSI/IEEEStd91-1984andIECPublication617-12.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT16841, SN74ABT16841
20-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS222C – SEPTEMBER 1992 – REVISED MAY 1997
logic diagram (positive logic)
1
28
1OE
2OE
56
29
42
1LE
2LE
2D1
C1
C1
1D
2
15
1Q1
2Q1
55
1D
1D1
To Nine Other Channels
To Nine Other Channels
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high or power-off state, V
. . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
O
Current into any output in the low state, I : SN54ABT16841 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
O
SN74ABT16841 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Package thermal impedance, θ (see Note 2): DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W
Storage temperature range, T
JA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
recommended operating conditions (see Note 3)
SN54ABT16841 SN74ABT16841
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
V
V
V
Supply voltage
5.5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
Input voltage
IH
0.8
0.8
V
IL
0
V
0
V
CC
V
I
CC
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Power-up ramp rate
–24
48
–32
64
mA
mA
ns/V
µs/V
°C
OH
OL
∆t/∆v
∆t/∆V
Outputs enabled
10
10
200
–55
200
–40
CC
T
Operating free-air temperature
125
85
A
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT16841, SN74ABT16841
20-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS222C – SEPTEMBER 1992 – REVISED MAY 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54ABT16841 SN74ABT16841
A
PARAMETER
TEST CONDITIONS
UNIT
†
MIN TYP
MAX
MIN
MAX
MIN
MAX
V
V
V
V
V
= 4.5 V,
= 4.5 V,
= 5 V,
I = –18 mA
–1.2
–1.2
–1.2
V
IK
CC
CC
CC
I
I
I
I
I
I
I
= –3 mA
= –3 mA
= –24 mA
= –32 mA
= 48 mA
= 64 mA
2.5
3
2.5
3
2.5
3
OH
OH
OH
OH
OL
OL
V
OH
2
2
V
= 4.5 V
= 4.5 V
CC
CC
2*
2
0.55
0.55
V
V
V
V
OL
0.55*
0.55
100
mV
µA
hys
V
V
= 0 to 5.5 V, V = V
or GND
CC
or GND
±1
±1
CC
CC
CC
I
I
I
= 5 V, V = V
I
±5
CC
V
V
= 0 to 2.1 V,
= 0.5 V to 2.7 V, OE = X
‡
±50
±50
10
±50
±50
±50
10
µA
µA
µA
µA
I
I
I
I
OZPU
OZPD
OZH
O
V
V
= 2.1 V to 0,
= 0.5 V to 2.7 V, OE = X
CC
O
‡
±50
10
V
V
= 2.1 V to 5.5 V,
= 2.7 V, OE ≥ 2 V
CC
O
V
V
= 2.1 V to 5.5 V,
= 0.5 V, OE ≥ 2 V
CC
O
–10
–10
–10
OZL
I
I
I
V
V
V
= 0,
V or V ≤ 4.5 V
±100
50
±100
50
µA
µA
off
CC
CC
CC
I
O
Outputs high
= 5.5 V,
= 5.5 V,
V
= 5.5 V
50
–180
0.5
CEX
O
O
§
V
= 2.5 V
–50
–100
–180
0.5
–50
–50
–180
mA
O
Outputs high
Outputs low
V
= 5.5 V, I = 0,
O
or GND
CC
CC
I
89
89
89
mA
CC
V = V
I
Outputs disabled
0.5
0.5
0.5
V
= 5.5 V, One input at 3.4 V,
CC
Other inputs at V
¶
1.5
1.5
1.5
mA
∆I
CC
or GND
CC
V = 2.5 V or 0.5 V
C
C
3.5
7.5
pF
pF
i
I
V
O
= 2.5 V or 0.5 V
o
* On products compliant to MIL-PRF-38535, this parameter does not apply.
†
‡
§
¶
All typical values are at V
= 5 V.
CC
This parameter is characterized, but not production tested.
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V or GND.
CC
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
SN54ABT16841
V
T
= 5 V,
= 25°C
CC
A
UNIT
MIN
MAX
MIN
4
MAX
t
w
t
su
t
h
Pulse duration, LE high or low
Setup time, data before LE↓
Hold time, data after LE↓
4
3
ns
ns
ns
3
2.6
2.6
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT16841, SN74ABT16841
20-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS222C – SEPTEMBER 1992 – REVISED MAY 1997
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
SN74ABT16841
V
T
= 5 V,
= 25°C
CC
A
UNIT
MIN
MAX
MIN
4
MAX
t
w
t
su
t
h
Pulse duration, LE high or low
Setup time, data before LE↓
Hold time, data after LE↓
4
1
2
ns
ns
ns
1
2
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (unless otherwise noted) (see Figure 1)
L
SN54ABT16841
= 5 V,
FROM
(INPUT)
TO
(OUTPUT)
V
CC
A
PARAMETER
UNIT
T
= 25°C
TYP
3.2
MIN
MAX
MIN
1.1
1.6
1.1
1.6
1.2
1.7
2.2
1.9
MAX
4.3
4.5
4.4
5
t
t
t
t
t
t
t
t
1.1
1.6
1.1
1.6
1.2
1.7
2.2
1.2
5.7
5.3
5.6
5.5
5.8
5.7
7.7
8.4
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
D
Q
Q
Q
Q
ns
ns
ns
ns
3.5
3.2
LE
3.4
3.2
4.7
5
OE
OE
3.6
4.1
6.6
5.8
4.4
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (unless otherwise noted) (see Figure 1)
L
SN74ABT16841
= 5 V,
FROM
(INPUT)
TO
(OUTPUT)
V
CC
A
PARAMETER
UNIT
T
= 25°C
TYP
3.2
MIN
MAX
MIN
1.1
1.6
1.1
1.6
1.2
1.7
2.2
1.9
MAX
4.3
4.5
4.4
4.6
4.7
5
t
t
t
t
t
t
t
t
1.1
1.6
1.1
1.6
1.2
1.7
2.2
1.9
5
5.1
5
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
D
Q
Q
Q
Q
ns
ns
ns
ns
3.5
3.2
LE
3.4
5
3.2
5.7
5.6
6.5
7.1
OE
OE
3.6
4.1
5.7
5.8
4.4
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT16841, SN74ABT16841
20-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS222C – SEPTEMBER 1992 – REVISED MAY 1997
PARAMETER MEASUREMENT INFORMATION
7 V
Open
TEST
/t
S1
S1
500 Ω
From Output
Under Test
t
Open
7 V
PLH PHL
GND
t
/t
PLZ PZL
C
= 50 pF
t
/t
Open
L
PHZ PZH
500 Ω
(see Note A)
3 V
0 V
LOAD CIRCUIT
Timing Input
Data Input
1.5 V
t
w
t
t
h
su
3 V
0 V
3 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
PZL
t
t
t
PHL
PLH
PHL
t
PLZ
Output
Waveform 1
S1 at 7 V
3.5 V
V
V
OH
1.5 V
1.5 V
1.5 V
1.5 V
Output
V
V
+ 0.3 V
OL
V
OL
OL
(see Note B)
t
PHZ
t
PLH
t
PZH
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
V
OH
– 0.3 V
OH
1.5 V
1.5 V
Output
≈ 0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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