SN54ABT2244 [TI]
OCTAL BUFFERS AND LINE/MOS DRIVERS WITH 3-STATE OUTPUTS; 八路缓冲器和线路/ MOS具有三态输出驱动程序
| 型号： | SN54ABT2244 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OCTAL BUFFERS AND LINE/MOS DRIVERS WITH 3-STATE OUTPUTS |
| 文件： | 总7页 (文件大小：107K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54ABT2244, SN74ABT2244
OCTAL BUFFERS AND LINE/MOS DRIVERS
WITH 3-STATE OUTPUTS
SCBS106B – JANUARY 1991 – REVISED JULY 1994
SN54ABT2244 . . . J PACKAGE
SN74ABT2244 . . . DB, DW, N, OR PW PACKAGE
(TOP VIEW)
• Output Ports Have Equivalent 25-Ω Series
Resistors, So No External Resistors Are
Required
• State-of-the-Art EPIC-ΙΙB BiCMOS Design
1OE
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Significantly Reduces Power Dissipation
2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
• Typical V
(Output Ground Bounce)
OLP
CC
< 1 V at V
= 5 V, T = 25°C
A
• Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK), and
Plastic (N) and Ceramic (J) DIPs
description
SN54ABT2244 . . . FK PACKAGE
(TOP VIEW)
These octal buffers and line drivers are designed
specifically to improve both the performance and
density of 3-state memory address drivers, clock
drivers, and bus-oriented receivers and
transmitters. Taken together with the ′ABT2240
and ′ABT2241, these devices provide the choice
of selected combinations of inverting and
noninverting outputs, symmetrical active-low
output-enable (OE) inputs, and complementary
OE and OE inputs. These devices feature high
fan-out and improved fan-in.
3
2
1
20 19
18
4
5
6
7
8
1Y1
2A4
1Y2
2A3
1Y3
1A2
2Y3
1A3
2Y2
1A4
17
16
15
14
9 10 11 12 13
The outputs, which are designed to sink up to
12 mA, include 25-Ω series resistors to reduce
overshoot and undershoot.
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74ABT2244 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54ABT2244 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT2244 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each buffer)
INPUTS
OUTPUT
Y
A
OE
L
H
L
H
L
L
H
X
Z
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
Copyright 1994, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
6–1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT2244, SN74ABT2244
OCTAL BUFFERS AND LINE/MOS DRIVERS
WITH 3-STATE OUTPUTS
SCBS106B – JANUARY 1991 – REVISED JULY 1994
†
logic symbol
logic diagram (positive logic)
1
1
1OE
1OE
EN
2
18
16
2
4
6
8
18
16
14
12
1A1
1Y1
1Y2
1
1A1
1A2
1A3
1A4
1Y1
1Y2
1Y3
1Y4
4
1A2
6
14
12
1A3
1Y3
1Y4
19
2OE
EN
8
1A4
11
13
15
17
9
7
5
3
1
2A1
2A2
2A3
2A4
2Y1
2Y2
2Y3
2Y4
19
2OE
11
9
7
2A1
†
2Y1
2Y2
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
13
2A2
schematic of Y outputs
15
5
3
2A3
2Y3
2Y4
V
CC
17
2A4
Output
GND
6–2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT2244, SN74ABT2244
OCTAL BUFFERS AND LINE/MOS DRIVERS
WITH 3-STATE OUTPUTS
SCBS106B – JANUARY 1991 – REVISED JULY 1994
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high state or power-off state, V
. . . . . . . . . . . . . –0.5 V to 5.5 V
O
Current into any output in the low state, I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
O
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
IK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
OK
O
Maximum power dissipation at T = 55°C (in still air) (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . 0.6 W
A
DW package . . . . . . . . . . . . . . . . . . . 1.6 W
N package . . . . . . . . . . . . . . . . . . . . . 1.3 W
PW package . . . . . . . . . . . . . . . . . . . 0.7 W
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils,
except for the N package, which has a trace length of zero. For more information, refer to the Package Thermal Considerations
application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B.
recommended operating conditions (see Note 3)
SN54ABT2244 SN74ABT2244
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
V
V
V
Supply voltage
5.5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
Input voltage
IH
0.8
0.8
V
IL
0
V
CC
0
V
CC
V
I
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Power-up ramp rate
–24
12
5
–32
12
5
mA
mA
ns/V
µs/V
°C
OH
OL
∆t/∆v
∆t/∆V
Outputs enabled
200
–55
200
–40
CC
T
Operating free-air temperature
125
85
A
NOTE 3: Unused or floating inputs must be held high or low.
6–3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT2244, SN74ABT2244
OCTAL BUFFERS AND LINE/MOS DRIVERS
WITH 3-STATE OUTPUTS
SCBS106B – JANUARY 1991 – REVISED JULY 1994
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54ABT2244 SN74ABT2244
A
PARAMETER
TEST CONDITIONS
UNIT
†
MIN TYP
MAX
MIN
MAX
MIN
MAX
V
V
V
V
V
V
= 4.5 V,
= 4.5 V,
= 5 V,
I = –18 mA
–1.2
–1.2
–1.2
V
IK
CC
CC
CC
I
I
I
I
I
I
= –3 mA
= –3 mA
= –24 mA
= –32 mA
= 12 mA
2.5
3
2.5
3
2.5
3
OH
OH
OH
OH
OL
V
OH
OL
2
2
V
CC
= 4.5 V
2*
2
V
V
V
V
V
V
V
= 4.5 V,
0.8
±1
0.8
±1
0.8
±1
V
CC
CC
CC
CC
CC
CC
CC
CC
I
I
I
I
I
I
= 0 to 5.5 V,
= 0 to 2.1 V,
= 2.1 V to 0,
= 2.1 V to 5.5 V,
= 2.1 V to 5.5 V,
= 0,
V = V or GND
I CC
µA
µA
µA
µA
µA
µA
I
V
O
V
O
V
O
V
O
= 0.5 to 2.7 V, OE = X
= 0.5 to 2.7 V, OE = X
= 2.7 V, OE ≥ 2 V
±50
±50
10
±50
±50
10
±50
±50
10
OZPU
OZPD
OZH
OZL
off
= 0.5 V, OE ≥ 2 V
–10
±100
–10
–10
±100
V or V ≤ 4.5 V
I
O
V
V
= 5.5 V,
= 5.5 V
I
Outputs high
50
50
50
µA
CEX
O
‡
I
V
= 5.5 V,
V
= 2.5 V
–50
–100 –180
–50
–180
250
30
–50
–180
250
30
mA
µA
O
CC
O
Outputs high
1
24
250
30
V
I
= 5.5 V,
= 0,
CC
O
I
Outputs low
mA
µA
CC
V = V
I
or GND
CC
Outputs disabled
Outputs enabled
0.5
250
1.5
250
1.5
250
1.5
V
CC
= 5.5 V,
Data
inputs
One input at 3.4 V,
§
∆I
Outputs disabled
0.05
1.5
0.05
1.5
0.05
1.5
mA
CC
Other inputs at
Control inputs
V
or GND
CC
V = 2.5 V or 0.5 V
C
C
3
pF
pF
i
I
V
O
= 2.5 V or 0.5 V
8.5
o
* On products compliant to MIL-STD-883, Class B, this parameter does not apply.
†
‡
§
All typical values are at V
= 5 V.
CC
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V or GND.
CC
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (unless otherwise noted) (see Figure 1)
L
V
T
= 5 V,
= 25°C
CC
A
SN54ABT2244 SN74ABT2244
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
1
TYP
3.4
4.5
3.8
6.3
4.5
4.3
MAX
4.3
5.3
4.8
7.3
5.6
5.3
MIN
1
MAX
5.3
6.8
6.5
10.2
7
MIN
1
MAX
4.7
5.6
5.5
8.3
6.6
5.8
t
t
t
t
t
t
PLH
PHL
PZH
PZL
PHZ
PLZ
A
Y
Y
Y
ns
ns
ns
1
1
1
1.1
2.1
2.1
1.7
1.1
2.1
2.1
1.7
1.1
2.1
2.1
1.7
OE
OE
7.4
6–4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT2244, SN74ABT2244
OCTAL BUFFERS AND LINE/MOS DRIVERS
WITH 3-STATE OUTPUTS
SCBS106B – JANUARY 1991 – REVISED JULY 1994
PARAMETER MEASUREMENT INFORMATION
7 V
Open
S1
500 Ω
From Output
Under Test
TEST
S1
GND
t
t
/t
Open
7 V
PLH PHL
/t
C
= 50 pF
L
t
500 Ω
PLZ PZL
/t
(see Note A)
Open
PHZ PZH
LOAD CIRCUIT FOR OUTPUTS
3 V
0 V
Timing Input
Data Input
1.5 V
t
w
t
t
h
su
3 V
0 V
3 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
0 V
Input
(see Note B)
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
t
PZL
t
t
PHL
PLH
t
PLZ
Output
Waveform 1
S1 at 7 V
V
V
3.5 V
OH
1.5 V
1.5 V
1.5 V
1.5 V
Output
V
V
+ 0.3 V
– 0.3 V
OL
V
OL
OL
(see Note C)
t
PHZ
t
PLH
t
t
PZH
PHL
Output
Waveform 2
S1 at Open
(see Note C)
V
OH
V
V
OH
OH
1.5 V
1.5 V
Output
0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A.
C includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6–5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
6–6
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
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party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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