SN54ABT245AFK [TI]
OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS; 八路总线收发器与3态输出
| 型号： | SN54ABT245AFK |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS |
| 文件： | 总7页 (文件大小：109K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54ABT245A, SN74ABT245B
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS081H – JANUARY 1991 – REVISED MAY 1997
SN54ABT245A . . . J OR W PACKAGE
SN74ABT245B . . . DB, DGV, DW, N, OR PW PACKAGE
(TOP VIEW)
State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
DIR
A1
V
CC
OE
B1
B2
B3
B4
B5
B6
B7
B8
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
A2
A3
A4
Typical V
(Output Ground Bounce) < 1 V
OLP
A5
at V
= 5 V, T = 25°C
CC
A
A6
High-Impedance State During Power Up
and Power Down
A7
A8
High-Drive Outputs (–32-mA I , 64-mA I
OH
)
OL
GND
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW), and
Thin Very Small-Outline (DGV) Packages,
Ceramic Chip Carriers (FK), Ceramic Flat
(W) Package, and Plastic (N) and
Ceramic (J) DIPs
SN54ABT245B . . . FK PACKAGE
(TOP VIEW)
3
2
1 20 19
18
A3
A4
A5
A6
A7
4
5
6
7
8
B1
B2
B3
B4
B5
description
17
16
15
14
These octal bus transceivers are designed for
asynchronous communication between data
buses. The devices transmit data from the A bus
to the B bus or from the B bus to the A bus,
depending on the logic level at the
direction-control (DIR) input. The output-enable
(OE) input can be used to disable the device so
the buses are effectively isolated.
9 10 11 12 13
When V
is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 2.1 V, OE should be tied to V
the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup resistor;
CC
The SN54ABT245A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT245B is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OPERATION
OE
L
DIR
L
B data to A bus
A data to B bus
Isolation
L
H
H
X
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT245A, SN74ABT245B
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS081H – JANUARY 1991 – REVISED MAY 1997
†
logic symbol
19
G3
OE
1
DIR
3 EN1 [BA]
3 EN2 [AB]
2
18
A1
1
B1
2
3
4
5
6
7
8
9
17
16
15
14
13
12
11
A2
A3
A4
A5
A6
A7
A8
B2
B3
B4
B5
B6
B7
B8
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1
2
DIR
19
OE
A1
18
B1
To Seven Other Channels
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT245A, SN74ABT245B
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS081H – JANUARY 1991 – REVISED MAY 1997
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage applied to any output in the high or power-off state, V . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
O
Current into any output in the low state, I : SN54ABT245A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
O
SN74ABT245B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Package thermal impedance, θ (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C/W
JA
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128°C/W
Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages,
which use a trace length of zero.
recommended operating conditions (see Note 3)
SN54ABT245A SN74ABT245B
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
V
V
V
Supply voltage
5.5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
Input voltage
IH
0.8
0.8
V
IL
0
V
CC
0
V
CC
V
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Power-up ramp rate
–24
48
5
–32
64
5
mA
mA
ns/V
µs/V
°C
OH
OL
I
∆t/∆v
∆t/∆V
200
–40
CC
T
Operating free-air temperature
–55
125
85
A
NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT245A, SN74ABT245B
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS081H – JANUARY 1991 – REVISED MAY 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54ABT245A SN74ABT245B
A
PARAMETER
TEST CONDITIONS
UNIT
†
MIN TYP
MAX
MIN
MAX
MIN
MAX
V
V
V
V
V
= 4.5 V,
I = –18 mA
–1.2
–1.2
–1.2
V
IK
CC
CC
CC
I
= 4.5 V,
= 5 V,
I
I
I
I
I
I
= –3 mA
= –3 mA
= –24 mA
= –32 mA
= 48 mA
= 64 mA
2.5
3
2.5
3
2.5
3
OH
OH
OH
OH
OL
OL
V
OH
2
2
V
= 4.5 V
= 4.5 V
CC
CC
2*
2
0.55
0.55
V
V
V
V
OL
0.55*
0.55
100
mV
hys
Control inputs
A or B ports
V
V
= 0 to 5.5 V, V = V
I
or GND
CC
±1
±1
±1
CC
I
I
µA
= 2.1 V to 5.5 V,
CC
±20
±100
±20
V = V
I
or GND
CC
V
V
= 0 to 2.1 V,
= 0.5 V to 2.7 V, OE = X
CC
O
‡
‡
±50
±50
10
±50
±50
10
±50
±50
10
µA
µA
µA
I
I
I
OZPU
V
V
= 2.1 V to 0,
= 0.5 V to 2.7 V, OE = X
CC
O
OZPD
V
V
= 2.1 V to 5.5 V,
= 2.7 V, OE ≥ 2 V
CC
O
§
OZH
V
V
= 2.1 V to 5.5 V,
= 0.5 V, OE ≥ 2 V
CC
O
§
–10
±100
50
–10
–10
±100
50
µA
µA
µA
I
I
I
I
OZL
V
CC
= 0,
V or V ≤ 4.5 V
I O
off
V
V
= 5.5 V,
= 5.5 V
CC
O
Outputs high
= 2.5 V
50
CEX
¶
V
CC
= 5.5 V,
V
O
–50
–140
5
–180
250
30
–50
–180
250
30
–50
–180
250
30
mA
µA
O
Outputs high
Outputs low
V
I
= 5.5 V,
= 0,
CC
O
I
A or B ports
22
1
mA
µA
CC
V = V
I
or GND
CC
Outputs disabled
250
250
250
V
= 5.5 V,
CC
Outputs enabled
Outputs disabled
1.5
50
1.5
50
1.5
50
mA
µA
One input at 3.4 V,
Other inputs at
Data inputs
#
∆I
CC
V
CC
or GND
V
= 5.5 V, One input at 3.4 V,
or GND
CC
Control inputs
1.5
1.5
1.5
mA
Other inputs at V
CC
C
C
Control inputs V = 2.5 V or 0.5 V
4
8
pF
pF
i
I
A or B ports
V
O
= 2.5 V or 0.5 V
io
* On products compliant to MIL-PRF-38535, this parameter does not apply.
†
‡
§
¶
#
All typical values are at V
= 5 V.
CC
This parameter is characterized, but not production tested.
The parameters I and I include the input leakage current.
OZH
OZL
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
or GND.
CC
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT245A, SN74ABT245B
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS081H – JANUARY 1991 – REVISED MAY 1997
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (unless otherwise noted) (see Figure 1)
L
V
T
= 5 V,
= 25°C
CC
A
SN54ABT245A SN74ABT245B
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
1
TYP
2
MAX
3.2
3.5
4.5
5.3
5.4
4
MIN
0.8
1
MAX
3.8
4.2
6.2
6.8
6.1
4.9
MIN
1
MAX
3.6
3.9
5.6
6.2
5.9
4.5
t
t
t
t
t
t
PLH
PHL
PZH
PZL
PHZ
PLZ
A or B
B or A
A or B
A or B
ns
ns
1
2.6
3.5
4
1
2
1.2
1.3
2.2
1.0
2
OE
OE
1.9
2.2
1.5
1.9
2.2
1.5
4.4
3
ns
ns
†
t
0.5
0.5
sk(o)
†
Skew between any two outputs of the same package switching in the same direction. This parameter is warranted but not production tested.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT245A, SN74ABT245B
OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS081H – JANUARY 1991 – REVISED MAY 1997
PARAMETER MEASUREMENT INFORMATION
7 V
Open
S1
500 Ω
From Output
Under Test
TEST
S1
GND
t
t
/t
Open
7 V
PLH PHL
/t
C
= 50 pF
L
t
500 Ω
PLZ PZL
/t
(see Note A)
Open
PHZ PZH
LOAD CIRCUIT
3 V
0 V
Timing Input
Data Input
1.5 V
t
w
t
t
h
su
3 V
0 V
3 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
0 V
Output
Control
1.5 V
1.5 V
Input
1.5 V
1.5 V
t
PZL
t
t
PHL
PLH
t
PLZ
Output
Waveform 1
S1 at 7 V
V
V
3.5 V
OH
1.5 V
1.5 V
1.5 V
1.5 V
Output
V
V
+ 0.3 V
– 0.3 V
OL
V
OL
OL
(see Note B)
t
PHZ
t
PLH
t
t
PZH
PHL
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
V
OH
OH
1.5 V
1.5 V
Output
≈ 0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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