SN54ABT3614PCB [TI]
64 】 36 】 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING; 64 】 36 】 2主频双向FIRST -IN ，具有总线匹配和字节交换先出存储器
| 型号： | SN54ABT3614PCB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 64 】 36 】 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING |
| 文件： | 总42页 (文件大小：644K) |
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SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
Free-Running CLKA and CLKB Can Be
Asynchronous or Coincident
EFB, FFB, AEB, and AFB Flags
Synchronized by CLKB
Two Independent 64 × 36 Clocked FIFOs
Passive Parity Checking on Each Port
Buffering Data in Opposite Directions
Parity Generation Can Be Selected for Each
Port
Mailbox-Bypass Register for Each FIFO
Dynamic Port-B Bus Sizing of 36 Bits (Long
Word), 18 Bits (Word), and 9 Bits (Byte)
Low-Power Advanced BiCMOS Technology
Supports Clock Frequencies up to 50 MHz
Fast Access Times of 12 ns
Selection of Big- or Little-Endian Format for
Word and Byte Bus Sizes
Released as DSCC SMD (Standard
Microcircuit Drawing) 5962-9560901QYA
and 5962-9560901NXD
Three Modes of Byte-Order Swapping on
Port B
Almost-Full and Almost-Empty Flags
Microprocessor Interface Control Logic
Package Options Include 132-Pin Ceramic
Quad Flat (HFP) and 120-Pin Plastic Quad
Flat (PCB) Packages
EFA, FFA, AEA, and AFA Flags
Synchronized by CLKA
description
The SN54ABT3614 is a high-speed, low-power BiCMOS bidirectional clocked FIFO memory. It supports clock
frequenciesupto50MHzandhasread-accesstimesasfastas12ns. Twoindependent64× 36dual-portSRAM
FIFOs in this device buffer data in opposite directions. Each FIFO has flags to indicate empty and full conditions
and two programmable flags (almost full and almost empty) to indicate when a selected number of words is
stored in memory. FIFO data on port B can be input and output in 36-bit, 18-bit, and 9-bit formats, with a choice
of big- or little-endian configurations. Three modes of byte-order swapping are possible with any bus-size
selection. Communication between each port can bypass the FIFOs via two 36-bit mailbox registers. Each
mailbox register has a flag to signal when new mail has been stored. Parity is checked passively on each port
and can be ignored if not desired. Parity generation can be selected for data read from each port.
The SN54ABT3614 is a clocked FIFO, which means each port employs a synchronous interface. All data
transfersthroughaportaregatedtothelow-to-hightransitionofacontinuous(free-running)portclockbyenable
signals. The continuous clocks for each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple bidirectional interface between
microprocessors and/or buses controlled by a synchronous interface.
The full flag and almost-full flag of a FIFO are two-stage synchronized to the port clock that writes data to its
array. The empty flag and almost-empty flag of a FIFO are two-stage synchronized to the port clock that reads
data from its array.
The SN54ABT3614 is characterized for operation over the full military temperature range of –55°C to 125°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2000, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
HFP PACKAGE
(TOP VIEW)
17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1 132 130 128 126 124 122 120 118
131 129 127 125 123 121 119 117
116
GND
AEA
EFA
A0
A1
A2
GND
A3
A4
A5
A6
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
GND
AEB
EFB
B0
B1
B2
GND
B3
B4
B5
B6
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
V
V
CC
CC
A7
A8
A9
GND
A10
A11
B7
B8
B9
GND
B10
B11
V
V
98
CC
CC
A12
A13
A14
GND
A15
A16
A17
A18
A19
A20
GND
A21
A22
A23
B12
B13
B14
GND
B15
B16
B17
B18
B19
B20
GND
B21
B22
B23
97
96
95
94
93
92
91
90
89
88
87
86
85
84
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 7576 7778 79 80 81 82 83
NC – No internal connection
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
PCB PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
90
89
88
87
86
85
A23
A22
A21
GND
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
GND
A9
B22
B21
GND
B20
B19
B18
B17
B16
B15
B14
B13
B12
B11
B10
GND
B9
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
B8
B7
A8
A7
V
B6
CC
V
CC
A6
B5
B4
B3
GND
B2
B1
B0
EFB
AEB
AFB
A5
A4
A3
GND
A2
A1
A0
EFA
AEA
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
functional block diagram
CLKA
CSA
W/RA
ENA
Port-A
Control
Logic
MBF1
PEFB
Parity
MBA
Gen/Check
Mail1
Register
PGB
64 × 36
SRAM
RST
36
Device
ODD/
EVEN
Control
Write
Pointer
Read
Pointer
Status-Flag
FFA
AFA
EFB
AEB
Logic
FIFO1
36
Programmable-Flag
Offset Register
FS0
FS1
B0–B35
A0–A35
FIFO2
Status-Flag
Logic
EFA
AEA
FFB
AFB
36
Read
Pointer
Write
Pointer
64 × 36
SRAM
PGA
Mail2
Register
Parity
Gen/Check
CLKB
PEFA
MBF2
CSB
W/RB
ENB
BE
Port-B
Control
Logic
SIZ0
SIZ1
SW0
SW1
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
Terminal Functions
TERMINAL
NAME
I/O
DESCRIPTION
A0–A35
AEA
I/O
O
Port-A data. The 36-bit bidirectional data port for side A.
Port-A almost-empty flag. Programmable flag synchronized to CLKA. AEA is low when the number of 36-bit words
(port A) in FIFO2 is less than or equal to value in offset register X.
Port-B almost-empty flag. Programmable flag synchronized to CLKB. AEB is low when the number of 36-bit words
(port B) in FIFO1 is less than or equal to value in offset register X.
Port-A almost-full flag. Programmable flag synchronized to CLKA. AFA is low when the number of 36-bit empty
(port A) locations in FIFO1 is less than or equal to the value in offset register X.
Port-B almost-full flag. Programmable flag synchronized to CLKB. AFB is low when the number of 36-bit empty
(port B) locations in FIFO2 is less than or equal to the value in offset register X.
O
AEB
AFA
O
O
AFB
B0–B35
BE
I/O
I
Port-B data. The 36-bit bidirectional data port for side B.
Big-endian select. Selects the bytes on port B used during byte or word data transfer. A low on BE selects the
most-significant bytes on B0–B35 for use, and a high selects the least-significant bytes.
Port-A clock. CLKA is a continuous clock that synchronizes all data transfers through port A and can be
asynchronous or coincident to CLKB. EFA, FFA, AFA, and AEA are synchronized to the low-to-high transition of
CLKA.
CLKA
CLKB
I
I
Port-B clock. CLKB is a continuous clock that synchronizes all data transfers through port B and can be
asynchronous or coincident to CLKA. Port-B byte swapping and data-port sizing operations are also synchronous
to the low-to-high transition of CLKB. EFB, FFB, AFB, and AEB are synchronized to the low-to-high transition of
CLKB.
Port-A chip select. CSA must be low to enable a low-to-high transition of CLKA to read or write data on port A. The
A0–A35 outputs are in the high-impedance state when CSA is high.
CSA
CSB
I
I
Port-B chip select. CSB must be low to enable a low-to-high transition of CLKB to read or write data on port B. The
B0–B35 outputs are in the high-impedance state when CSB is high.
Port-A empty flag. EFA is synchronized to the low-to-high transition of CLKA. When EFA is low, FIFO2 is empty and
reads from its memory are disabled. Data can be read from FIFO2 to the output register when EFA is high. EFA is
forced low when the device is reset and is set high by the second low-to-high transition of CLKA after data is loaded
into empty FIFO2 memory.
O
EFA
EFB
(port A)
Port-B empty flag. EFB is synchronized to the low-to-high transition of CLKB. When EFB is low, FIFO1 is empty and
reads from its memory are disabled. Data can be read from FIFO1 to the output register when EFB is high. EFB is
forced low when the device is reset and is set high by the second low-to-high transition of CLKB after data is loaded
into empty FIFO1 memory.
O
(port B)
ENA
ENB
I
I
Port-A enable. ENA must be high to enable a low-to-high transition of CLKA to read or write data on port A.
Port-B enable. ENB must be high to enable a low-to-high transition of CLKB to read or write data on port B.
Port-A full flag. FFA is synchronized to the low-to-high transition of CLKA. When FFA is low, FIFO1 is full and writes
to its memory are disabled. FFA is forced low when the device is reset and is set high by the second low-to-high
transition of CLKA after reset.
O
FFA
(port A)
Port-B full flag. FFB is synchronized to the low-to-high transition of CLKB. When FFB is low, FIFO2 is full and writes
to its memory are disabled. FFB is forced low when the device is reset and is set high by the second low-to-high
transition of CLKB after reset.
O
FFB
(port B)
Flag offset selects. The low-to-high transition of RST latches the values of FS0 and FS1, which selects one of four
preset values for the almost-empty flag and almost-full flag offset.
FS1, FS0
MBA
I
I
Port-A mailbox select. A high level on MBA chooses a mailbox register for a port-A read or write operation. When
the A0–A35 outputs are active, a high level on MBA selects data from the mail2 register for output and a low level
selects FIFO2 output register data for output.
Mail1 register flag. MBF1 is set low by the low-to-high transition of CLKA that writes data to the mail1 register. Writes
to the mail1 register are inhibited while MBF1 is low. MBF1 is set high by a low-to-high transition of CLKB when a
port-B read is selected and both SIZ1 and SIZ0 are high. MBF1 is set high when the device is reset.
MBF1
MBF2
O
O
Mail2 register flag. MBF2 is set low by the low-to-high transition of CLKB that writes data to the mail2 register. Writes
to the mail2 register are inhibited while MBF2 is low. MBF2 is set high by a low-to-high transition of CLKA when a
port-A read is selected and MBA is high. MBF2 is set high when the device is reset.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
Terminal Functions (Continued)
TERMINAL
NAME
I/O
DESCRIPTION
Odd/evenparityselect.OddparityischeckedoneachportwhenODD/EVENishighandevenparityischeckedwhen
ODD/EVEN is low. ODD/EVEN also selects the type of parity generated for each port if parity generation is enabled
for a read operation.
ODD/EVEN
I
Port-A parity-error flag. When any byte applied to terminals A0–A35 fails parity, PEFA is low. Bytes are organized
as A0–A8, A9–A17, A18–A26, and A27–A35, with the most-significant bit of each byte serving as the parity bit. The
type of parity checked is determined by the state of ODD/EVEN.
O
PEFA
PEFB
(port A)
The parity trees used to check the A0–A35 inputs are shared by the mail2 register to generate parity if parity
generation is selected by PGA; therefore, if a mail2 read with parity generation is set up by having W/RA low, MBA
high, and PGA high, the PEFA flag is forced high, regardless of the state of the A0–A35 inputs.
Port-B parity-error flag. When any valid byte applied to terminals B0–B35 fails parity, PEFB is low. Bytes are
organizedasB0–B8,B9–B17,B18–B26,andB27–B35,withthemost-significantbitofeachbyteservingastheparity
bit. A byte is valid when it is used by the bus size selected for port B. The type of parity checked is determined by
the state of ODD/EVEN.
O
(port B)
The parity trees used to check the B0–B35 inputs are shared by the mail1 register to generate parity if parity
generation is selected by PGB; therefore, if a mail1 read with parity generation is set up by having W/RB low, SIZ1
and SIZ0 high, and PGB high, the PEFB flag is forced high, regardless of the state of the B0–B35 inputs.
Port-A parity generation. Parity is generated for data reads from port A when PGA is high. The type of parity
generatedis selected by the state of ODD/EVEN. Bytes are organized as A0–A8, A9–A17, A18–A26, and A27–A35.
The generated parity bits are output in the most-significant bit of each byte.
PGA
PGB
I
I
Port-B parity generation. Parity is generated for data reads from port B when PGB is high. The type of parity
generatedis selected by the state of ODD/EVEN. Bytes are organized as B0–B8, B9–B17, B18–B26, and B27–B35.
The generated parity bits are output in the most-significant bit of each byte.
Reset. To reset the device, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must occur
while RST is low. This sets AFA, AFB, MBF1, and MBF2 high and EFA, EFB, AEA, AEB, FFA, and FFB low. The
low-to-hightransition of RST latches the status of the FS1 and FS0 inputs to select almost-full flag and almost-empty
flag offset.
RST
I
Port-B bus-size selects. The low-to-high transition of CLKB latches the states of SIZ0, SIZ1, and BE, and the
following low-to-high transition of CLKB implements the latched states as a port-B bus size. Port-B bus sizes can
be long word, word, or byte. A high on both SIZ0 and SIZ1 accesses the mailbox registers for a port-B 36-bit write
or read.
I
SIZ0, SIZ1
SW0, SW1
(port B)
Port-B byte-swap selects. At the beginning of each long-word transfer, one of four modes of byte-order swapping
is selected by SW0 and SW1. The four modes are no swap, byte swap, word swap, and byte-word swap. Byte-order
swapping is possible with any bus-size selection.
I
(port B)
Port-A write/read select. W/RA high selects a write operation and a low selects a read operation on port A for a
low-to-high transition of CLKA. The A0–A35 outputs are in the high-impedance state when W/RA is high.
W/RA
W/RB
I
I
Port-B write/read select. W/RB high selects a write operation and a low selects a read operation on port B for a
low-to-high transition of CLKB. The B0–B35 outputs are in the high-impedance state when W/RB is high.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
detailed description
reset
The SN54ABT3614 is reset by taking the reset (RST) input low for at least four port-A clock (CLKA) and four
port-B clock (CLKB) low-to-high transitions. The reset input can switch asynchronously to the clocks. A device
reset initializes the internal read and write pointers of each FIFO and forces the full flags (FFA, FFB) low, the
empty flags (EFA, EFB) low, the almost-empty flags (AEA, AEB) low, and the almost-full flags (AFA, AFB) high.
A reset also forces the mailbox flags (MBF1, MBF2) high. After a reset, FFA is set high after two low-to-high
transitions of CLKA and FFB is set high after two low-to-high transitions of CLKB. The device must be reset after
power up before data is written to its memory.
A low-to-high transition on RST loadsthealmost-fullandalmost-emptyoffsetregister(X)withthevalueselected
by the flag-select (FS0, FS1) inputs. The values that can be loaded into the register are shown in Table 1.
Table 1. Flag Programming
ALMOST-FULL AND
FS1
FS0
RST
ALMOST-EMPTY FLAG
OFFSET REGISTER (X)
H
H
L
H
L
↑
↑
↑
↑
16
12
8
H
L
L
4
FIFO write/read operation
The state of the port-A data (A0–A35) outputs is controlled by the port-A chip select (CSA) and the port-A
write/read select (W/RA). The A0–A35 outputs are in the high-impedance state when either CSA or W/RA is
high. The A0–A35 outputs are active when both CSA and W/RA are low. Data is loaded into FIFO1 from the
A0–A35 inputs on a low-to-high transition of CLKA when CSA is low, W/RA is high, ENA is high, MBA is low,
and FFA is high. Data is read from FIFO2 to the A0–A35 outputs by a low-to-high transition of CLKA when CSA
is low, W/RA is low, ENA is high, MBA is low, and EFA is high (see Table 2).
Table 2. Port-A Enable Function Table
CSA W/RA ENA
MBA CLKA
A0–A35 OUTPUTS
In high-impedance state
In high-impedance state
In high-impedance state
In high-impedance state
Active, FIFO2 output register
Active, FIFO2 output register
Active, mail2 register
PORT FUNCTION
None
H
L
L
L
L
L
L
L
X
H
H
H
L
X
L
X
X
L
X
X
↑
None
H
H
L
FIFO1 write
Mail1 write
None
H
L
↑
X
↑
L
H
L
L
FIFO2 read
None
L
H
H
X
↑
L
H
Active, mail2 register
Mail2 read (set MBF2 high)
The state of the port-B data (B0–B35) outputs is controlled by the port-B chip select (CSB) and the port-B
write/read select (W/RB). The B0–B35 outputs are in the high-impedance state when either CSB or W/RB is
high. The B0–B35 outputs are active when both CSB and W/RB are low. Data is loaded into FIFO2 from the
B0–B35 inputs on a low-to-high transition of CLKB when CSB is low, W/RB is high, ENB is high, FFB is high,
andeitherSIZ0orSIZ1islow. DataisreadfromFIFO1totheB0–B35outputsbyalow-to-hightransitionofCLKB
when CSB is low, W/RB is low, ENB is high, EFB is high, and either SIZ0 or SIZ1 is low (see Table 3).
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
FIFO write/read operation (continued)
Table 3. Port-B Enable Function Table
CSB W/RB ENB
SIZ1, SIZ0
X
CLKB
B0–B35 OUTPUTS
In high-impedance state
In high-impedance state
In high-impedance state
In high-impedance state
Active, FIFO1 output register
Active, FIFO1 output register
Active, mail1 register
PORT FUNCTION
None
H
L
L
L
L
L
L
L
X
H
H
H
L
X
L
X
X
↑
X
None
H
H
L
One, both low
Both high
One, both low
One, both low
Both high
Both high
FIFO2 write
Mail2 write
None
↑
X
↑
L
H
L
FIFO1 read
None
L
X
↑
L
H
Active, mail1 register
Mail1 read (set MBF1 high)
The setup- and hold-time constraints to the port clocks for the port chip selects (CSA, CSB) and write/read
selects (W/RA, W/RB) are only for enabling write and read operations and are not related to high-impedance
control of the data outputs. If a port enable is low during a clock cycle, the port chip select and write/read select
can change states during the setup- and hold-time window of the cycle.
synchronized FIFO flags
EachFIFOflagissynchronizedtoitsportclockthroughtwoflip-flopstages. Thisisdonetoimproveflagreliability
by reducing the probability of metastable events on the output when CLKA and CLKB operate asynchronously
to one another (see the application report Metastability Performance of Clocked FIFOs in the 1996
High-Performance FIFO Memories Data Book, literature number SCAD003). EFA, AEA, FFA, and AFA are
synchronized to CLKA. EFB, AEB, FFB, and AFB are synchronized to CLKB. Tables 4 and 5 show the
relationship of each port flag to FIFO1 and FIFO2.
Table 4. FIFO1 Flag Operation
SYNCHRONIZED
TO CLKB
SYNCHRONIZED
TO CLKA
NUMBER OF 36-BIT
WORDS IN FIFO1
†
EFB
L
AEB
L
AFA
H
FFA
H
0
1 to X
H
L
H
H
(X + 1) to [64 – (X + 1)]
(64 – X) to 63
64
H
H
H
H
H
H
L
H
H
H
L
L
†
Xisthevalueinthealmost-emptyflagandalmost-fullflagoffsetregister.
Table 5. FIFO2 Flag Operation
SYNCHRONIZED
TO CLKA
SYNCHRONIZED
TO CLKB
NUMBER OF 36-BIT
WORDS IN FIFO2
†
EFA
L
AEA
L
AFB
H
FFB
H
0
1 to X
H
L
H
H
(X + 1) to [64 – (X + 1)]
(64 – X) to 63
64
H
H
H
H
H
H
L
H
H
H
L
L
†
Xisthevalueinthealmost-emptyflagandalmost-fullflagoffsetregister.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
empty flags (EFA, EFB)
The empty flag of a FIFO is synchronized to the port clock that reads data from its array. When the empty flag
is high, new data can be read to the FIFO output register. When the empty flag is low, the FIFO is empty and
attempted FIFO reads are ignored. When reading FIFO1 with a byte or word size on port B, EFB is set low when
the fourth byte or second word of the last long word is read.
The read pointer of a FIFO is incremented each time a new word is clocked to the output register. The state
machine that controls an empty flag monitors a write-pointer and read-pointer comparator that indicates when
the FIFO SRAM status is empty, empty+1, or empty+2. A word written to a FIFO can be read to the FIFO output
register in a minimum of three cycles of the empty-flag synchronizing clock; therefore, an empty flag is low if
a word in memory is the next data to be sent to the FIFO output register and two cycles of the port clock that
reads data from the FIFO have not elapsed since the time the word was written. The empty flag of the FIFO is
set high by the second low-to-high transition of the synchronizing clock and the new data word can be read to
the FIFO output register in the following cycle.
A low-to-high transition on an empty-flag synchronizing clock begins the first synchronization cycle of a write
if the clock transition occurs at time t , or greater, after the write. Otherwise, the subsequent clock cycle can
sk1
be the first synchronization cycle (see Figures 13 and 14).
full flags (FFA, FFB)
The full flag of a FIFO is synchronized to the port clock that writes data to its array. When the full flag is high,
a memory location is free in the SRAM to receive new data. No memory locations are free when the full flag is
low and attempted writes to the FIFO are ignored.
Each time a word is written to a FIFO, the write pointer is incremented. The state machine that controls a full
flag monitors a write-pointer and read-pointer comparator that indicates when the FIFO SRAM status is full,
full–1, or full–2. From the time a word is read from a FIFO, the previous memory location is ready to be written
in a minimum of three cycles of the full-flag synchronizing clock; therefore, a full flag is low if less than two cycles
of the full-flag synchronizing clock have elapsed since the next memory write location has been read. The
second low-to-high transition on the full-flag synchronizing clock after the read sets the full flag high and data
can be written in the following clock cycle.
A low-to-high transition on a full-flag synchronizing clock begins the first synchronization cycle of a read if the
clock transition occurs at time t , or greater, after the read. Otherwise, the subsequent clock cycle can be the
sk1
first synchronization cycle (see Figures 15 and 16).
almost-empty flags (AEA, AEB)
The almost-empty flag of a FIFO is synchronized to the port clock that reads data from its array. The state
machine that controls an almost-empty flag monitors a write-pointer and read-pointer comparator that indicates
when the FIFO SRAM status is almost empty, almost empty+1, or almost empty+2. The almost-empty state is
defined by the value of the almost-full and almost-empty offset register (X). This register is loaded with one of
four preset values during a device reset (see reset). An almost-empty flag is low when the FIFO contains X or
fewer long words in memory and is high when the FIFO contains (X + 1) or more long words.
Two low-to-high transitions of the almost-empty flag synchronizing clock are required after a FIFO write for the
almost-empty flag to reflect the new level of fill; therefore, the almost-empty flag of a FIFO containing (X + 1)
or more long words remains low if two cycles of the synchronizing clock have not elapsed since the write that
filled the memory to the (X + 1) level. An almost-empty flag is set high by the second low-to-high transition of
the synchronizing clock after the FIFO write that fills memory to the (X + 1) level. A low-to-high transition of an
almost-empty flag synchronizing clock begins the first synchronization cycle if it occurs at time t , or greater,
sk2
after the write that fills the FIFO to (X + 1) long words. Otherwise, the subsequent synchronizing clock cycle can
be the first synchronization cycle (see Figures 17 and 18).
9
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64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
almost-full flags (AFA, AFB)
The almost-full flag of a FIFO is synchronized to the port clock that writes data to its array. The state machine
that controls an almost-full flag monitors a write-pointer and read-pointer comparator that indicates when the
FIFO SRAM status is almost full, almost full–1, or almost full–2. The almost-full state is defined by the value of
the almost-full and almost-empty offset register (X). This register is loaded with one of four preset values during
a device reset (see reset). An almost-full flag is low when the FIFO contains (64 – X) or more long words in
memory and is high when the FIFO contains [64 – (X + 1)] or fewer long words.
Two low-to-high transitions of the almost-full-flag synchronizing clock are required after a FIFO read for the
almost-full flag to reflect the new level of fill; therefore, the almost-full flag of a FIFO containing [64 – (X + 1)]
or fewer words remains low if two cycles of the synchronizing clock have not elapsed since the read that reduced
the number of long words in memory to [64 – (X + 1)]. An almost-full flag is set high by the second low-to-high
transition of the synchronizing clock after the FIFO read that reduces the number of long words in memory to
[64 – (X + 1)]. A low-to-high transition of an almost-full-flag synchronizing clock begins the first synchronization
cycle if it occurs at time t , or greater, after the read that reduces the number of long words in memory to
sk2
[64 – (X + 1)]. Otherwise, the subsequent synchronizing clock cycle can be the first synchronization cycle (see
Figures 19 and 20).
mailbox registers
Each FIFO has a 36-bit bypass register to pass command and control information between port A and port B
without putting it in queue. The mailbox-select (MBA, MBB) inputs choose between a mail register and a FIFO
for a port data-transfer operation. A low-to-high transition on CLKA writes A0–A35 data to the mail1 register
when a port-A write is selected by CSA, W/RA, and ENA, and MBA is high. A low-to-high transition on CLKB
writes B0–B35 data to the mail2 register when a port-B write is selected by CSB, W/RB, and ENB and both SIZ0
and SIZ1 are high. Writing data to a mail register sets the corresponding flag (MBF1 or MBF2) low. Attempted
writes to a mail register are ignored while the mail flag is low.
When the port-A data outputs (A0–A35) are active, the data on the bus comes from the FIFO2 output register
when MBA is low and from the mail2 register when MBA is high. When the port-B data outputs (B0–B35) are
active, the data on the bus comes from the FIFO1 output register when either one or both SIZ1 and SIZ0 are
low and from the mail2 register when both SIZ1 and SIZ0 are high. The mail1 register flag (MBF1) is set high
by a rising CLKB edge when a port-B read is selected by CSB, W/RB, and ENB and both port-B bus-size select
(SIZ1 and SIZ0) inputs are high. The mail2 register flag (MBF2) is set high by a rising CLKA edge when a port-A
read is selected by CSA, W/RA, and ENA and MBA is high. The data in the mail register remains intact after
it is read and changes only when new data is written to the register.
dynamic bus sizing
The port-B bus can be configured in a 36-bit long word, 18-bit word, or 9-bit byte format for data read from FIFO1
or written to FIFO2. Word- and byte-size bus selections can utilize the most-significant bytes of the bus (big
endian) or least-significant bytes of the bus (little endian). Port-B bus size can be changed dynamically and
synchronous to CLKB to communicate with peripherals of various bus widths.
The levels applied to SIZ0 and SIZ1 and the big-endian select (BE) input are stored on each CLKB low-to-high
transition. The stored port-B bus-size selection is implemented by the next rising edge on CLKB according to
Figure 1.
Only 36-bit long-word data is written to or read from the two FIFO memories on the SN54ABT3614.
Bus-matchingoperationsaredoneafterdataisreadfromtheFIFO1RAMandbeforedataiswrittentotheFIFO2
RAM. Port-B bus sizing does not apply to mail-register operations.
10
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64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
A35
A27 A26
A18 A17
A9 A8
A0
BYTE ORDER ON PORT A:
Write to FIFO1/Read From FIFO2
Read From FIFO1/Write to FIFO2
A
A
B
C
D
D
B35
B27 B26
B18 B17
B9 B8
B0
BE
X
SIZ1
L
SIZ0
L
B
C
(a) LONG WORD SIZE
B35
B35
B27 B26
B18 B17
B9 B8
B0
B0
BE
L
SIZ1
L
SIZ0
H
1st: Read From FIFO1/Write to FIFO2
2nd: Read From FIFO1/Write to FIFO2
A
C
B
D
B27 B26
B18 B17
B9 B8
(b) WORD SIZE – BIG ENDIAN
B35
B35
B27 B26
B18 B17
B18 B17
B9 B8
B0
B0
BE
H
SIZ1
L
SIZ0
H
1st: Read From FIFO1/Write to FIFO2
2nd: Read From FIFO1/Write to FIFO2
C
A
D
B
B27 B26
B9 B8
(c) WORD SIZE – LITTLE ENDIAN
B35
B35
B27 B26
B27 B26
B18 B17
B18 B17
B9 B8
B9 B8
B0
B0
BE
L
SIZ1
H
SIZ0
L
1st: Read From FIFO1/Write to FIFO2
2nd: Read From FIFO1/Write to FIFO2
3rd: Read From FIFO1/Write to FIFO2
4th: Read From FIFO1/Write to FIFO2
A
B
B35
B35
B27 B26
B27 B26
B18 B17
B18 B17
B9 B8
B9 B8
B0
B0
C
D
(d) BYTE SIZE – BIG ENDIAN
Figure 1. Dynamic Bus Sizing
11
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64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
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SGBS308F – AUGUST 1995 – REVISED MAY 2000
B35
B27 B26
B18 B17
B9 B8
B9 B8
B0
B0
BE
H
SIZ1
H
SIZ0
L
1st: Read From FIFO1/Write to FIFO2
2nd: Read From FIFO1/Write to FIFO2
D
C
B35
B27 B26
B18 B17
B35
B35
B27 B26
B27 B26
B18 B17
B18 B17
B9 B8
B9 B8
B0
B0
3rd: Read From FIFO1/Write to FIFO2
4th: Read From FIFO1/Write to FIFO2
B
A
(e) BYTE SIZE – LITTLE ENDIAN
Figure 1. Dynamic Bus Sizing (Continued)
bus-matching FIFO1 reads
Data is read from the FIFO1 RAM in 36-bit long-word increments. If a long-word bus size is implemented, the
entire long word immediately shifts to the FIFO1 output register. If byte or word size is implemented on port B,
only the first one or two bytes appear on the selected portion of the FIFO1 output register, with the rest of the
long word stored in auxiliary registers. In this case, subsequent FIFO1 reads with the same bus-size
implementation output the rest of the long word to the FIFO1 output register in the order shown by Figure 1.
Each FIFO1 read with a new bus-size implementation automatically unloads data from the FIFO1 RAM to its
output register and auxiliary registers. Therefore, implementing a new port-B bus size and performing a FIFO1
read before all bytes or words stored in the auxiliary registers have been read results in a loss of the unread
long-word data.
When reading data from FIFO1 in byte or word format, the unused B0–B35 outputs remain inactive but static
with the unused FIFO1 output register bits holding the last data value to decrease power consumption.
bus-matching FIFO2 writes
Data is written to the FIFO2 RAM in 36-bit long-word increments. FIFO2 writes, with a long-word bus size,
immediately store each long word in FIFO2 RAM. Data written to FIFO2 with a byte or word bus size stores the
initial bytes or words in auxiliary registers. The CLKB rising edge that writes the fourth byte or the second word
of long word to FIFO2 also stores the entire long word in FIFO2 RAM. The bytes are arranged in the manner
shown in Figure 1.
Each FIFO2 write with a new bus-size implementation resets the state machine that controls the data flow from
the auxiliary registers to the FIFO2 RAM. Therefore, implementing a new bus size and performing a FIFO2 write
before bytes or words stored in the auxiliary registers have been loaded to FIFO2 RAM results in a loss of data.
12
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64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
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SGBS308F – AUGUST 1995 – REVISED MAY 2000
port-B mail-register access
In addition to selecting port-B bus sizes for FIFO reads and writes, the port-B bus size select (SIZ0, SIZ1) inputs
also access the mail registers. When both SIZ0 and SIZ1 are high, the mail1 register is accessed for a port-B
long-word read and the mail2 register is accessed for a port-B long-word write. The mail register is accessed
immediately and any bus-sizing operation that can be underway is unaffected by the the mail-register access.
After the mail-register access is complete, the previous FIFO access can resume in the next CLKB cycle. The
logic diagram in Figure 2 shows that the previous bus-size selection is preserved when the mail registers are
accessed from port B. A port-B bus size is implemented on each rising CLKB edge according to the states of
SIZ0_Q, SIZ1_Q, and BE_Q.
CLKB
MUX
G1
1
SIZ0_Q
D
Q
SIZ1_Q
BE_Q
SIZ0
SIZ1
BE
1
Figure 2. Logic Diagram for SIZ0, SIZ1, and BE Register
byte swapping
The byte-order arrangement of data read from FIFO1 or data written to FIFO2 can be changed synchronous
to the rising edge of CLKB. Byte-order swapping is not available for mail-register data. Four modes of byte-order
swapping (including no swap) can be done with any data-port-size selection. The order of the bytes is
rearranged within the long word, but the bit order within the bytes remains constant.
Byte arrangement is chosen by the port-B swap select (SW0, SW1) inputs on a CLKB rising edge that reads
a new long word from FIFO1 or writes a new long word to FIFO2. The byte order chosen on the first byte or first
word of a new long-word read from FIFO1 or written to FIFO2 is maintained until the entire long word is
transferred, regardless of the SW0 and SW1 states during subsequent writes or reads. Figure 3 is an example
of the byte-order swapping available for long words. Performing a byte swap and bus size simultaneously for
a FIFO1 read rearranges the bytes as shown in Figure 3, then outputs the bytes as shown in Figure 1.
Simultaneous bus-sizing and byte-swapping operations for FIFO2 writes load the data according to Figure 1,
then swap the bytes as shown in Figure 3 when the long word is loaded to FIFO2 RAM.
13
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SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
A35
A27 A26
A18 A17
A9 A8
A0
SW1
L
SW0
L
A
A
B
B
C
C
D
D
B35
A35
B27 B26
B18 B17
A18 A17
B9 B8
A9 A8
B0
A0
(a) NO SWAP
A27 A26
B
SW1
L
SW0
H
A
D
C
B
D
A
C
B35
A35
B27 B26
B18 B17
B9 B8
A9 A8
B0
A0
(b) BYTE SWAP
A27 A26
A18 A17
SW1
H
SW0
L
A
B
C
A
D
B
C
D
B35
A35
B27 B26
B18 B17
B9 B8
A9 A8
B0
A0
(c) WORD SWAP
A27 A26
A18 A17
SW1
H
SW0
H
A
B
B
A
C
D
D
C
B35
B27 B26
B18 B17
B9 B8
B0
(d) BYTE-WORD SWAP
Figure 3. Byte Swapping (Long-Word Size Example)
14
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64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
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SGBS308F – AUGUST 1995 – REVISED MAY 2000
parity checking
The port-A data inputs (A0–A35) and port-B data inputs (B0–B35) each have four parity trees to check the parity
of incoming (or outgoing) data. A parity failure on one or more bytes of the port-A data bus is reported by a low
level on the port-A parity-error flag (PEFA). A parity failure on one or more bytes of the port-B data inputs that
are valid for the bus-size implementation is reported by a low level on the port-B parity-error flag (PEFB). Odd-
or even-parity checking can be selected, and the parity-error flags can be ignored if this feature is not desired.
Parity status is checked on each input bus according to the level of the odd/even parity (ODD/EVEN) select
input. A parity error on one or more valid bytes of a port is reported by a low level on the corresponding port
parity-error flag (PEFA, PEFB) output. Port-A bytes are arranged as A0–A8, A9–A17, A18–A26, and A27–A35.
Port-B bytes are arranged as B0–B8, B9–B17, B18–B26, and B27–B35, and its valid bytes are those used in
a port-B bus-size implementation. When odd/even parity is selected, a port parity-error flag (PEFA, PEFB) is
low if any valid byte on the port has an odd/even number of low levels applied to the bits.
The four parity trees used to check the A0–A35 inputs are shared by the mail2 register when parity generation
is selected for port-A reads (PGA = high). When a port-A read from the mail2 register with parity generation is
selected with CSA low, ENA high, W/RA low, MBA high, and PGA high, the port-A parity-error flag (PEFA) is
held high regardless of the levels applied to the A0–A35 inputs. Likewise, the parity trees used to check the
B0–B35inputsaresharedbythemail1registerwhenparitygenerationisselectedforport-Breads(PGB=high).
When a port-B read from the mail1 register with parity generation is selected with CSB low, ENB high, and W/RB
low, both SIZ0 and SIZ1 high, and PGB high, the port-B parity-error flag (PEFB) is held high, regardless of the
levels applied to the B0–B35 inputs.
parity generation
A high level on the port-A parity-generate select (PGA) or port-B parity-generate select (PGB) enables the
SN54ABT3614 to generate parity bits for port reads from a FIFO or mailbox register. Port-A bytes are arranged
as A0–A8, A9–A17, A18–A26, and A27–A35, with the most-significant bit of each byte used as the parity bit.
Port-B bytes are arranged as B0–B8, B9–B17, B18–B26, and B27–B35, with the most-significant bit of each
byte used as the parity bit. A write to a FIFO or mail register stores the levels applied to all nine inputs of a byte,
regardless of the state of the parity-generate select (PGA, PGB) inputs. When data is read from a port with parity
generation selected, the lower eight bits of each byte are used to generate a parity bit according to the level on
the ODD/EVEN select. The generated parity bits are substituted for the levels originally written to the
most-significant bits of each byte as the word is read to the data outputs.
Parity bits for FIFO data are generated after the data is read from SRAM and before the data is written to the
output register; therefore, the port-A parity-generate select (PGA) and odd/even parity select (ODD/EVEN)
have setup- and hold-time constraints to the port-A clock (CLKA) and the port-B parity generate select (PGB)
and ODD/EVEN have setup and hold-time constraints to the port-B clock (CLKB). These timing constraints only
apply for a rising clock edge used to read a new long word to the FIFO output register.
The circuit used to generate parity for the mail1 data is shared by the port-B bus (B0–B35) to check parity and
the circuit used to generate parity for the mail2 data is shared by the port-A bus (A0–A35) to check parity. The
shared parity trees of a port are used to generate parity bits for the data in a mail register when the port chip
select (CSA, CSB) is low, enable (ENA, ENB) is high, write/read select (W/RA, W/RB) input is low, the mail
register is selected (MBA is high for port A; both SIZ0 and SIZ1 are high for port B), and port parity-generate
select (PGA, PGB) is high. Generating parity for mail-register data does not change the contents of the register.
15
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SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
CLKA
t
h(RS)
CLKB
t
h(FS)
t
su(RS)
t
su(FS)
RST
FS1, FS0
FFA
0,1
t
t
pd(C-FF)
pd(C-FF)
t
pd(C-EF)
t
EFA
t
pd(C-FF)
pd(C-FF)
FFB
EFB
t
pd(C-EF)
t
pd(R-F)
MBF1,
MBF2
t
pd(C-AE)
AEA
AFA
AEB
AFB
t
pd(C-AF)
t
pd(C-AE)
t
pd(C-AF)
Figure 4. Device Reset Loading the X Register With the Value of Eight
16
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64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
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SGBS308F – AUGUST 1995 – REVISED MAY 2000
t
c
t
t
w(CLKL)
w(CLKH)
CLKA
FFA
High
t
t
t
su(EN)
su(EN)
h(EN)
CSA
t
t
h(EN)
h(EN)
W/RA
MBA
t
t
su(EN)
su(EN)
t
t
h(EN)
h(EN)
t
t
t
t
h(EN)
h(D)
su(EN)
su(EN)
ENA
t
su(D)
†
W1
†
W2
A0–A35
No Operation
ODD/
EVEN
t
t
pd(D-PE)
pd(D-PE)
PEFA
Valid
Valid
†
Written to FIFO1
Figure 5. Port-A Write Cycle for FIFO1
17
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SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
CLKB
FFB
CSB
High
t
t
su(EN)
su(EN)
W/RB
t
h(EN)
t
t
t
su(EN)
h(EN)
su(EN)
ENB
t
t
su(SW)
h(SW)
SW1,
SW0
t
t
t
su(SZ)
BE
h(SZ)
h(SZ)
t
su(SZ)
SIZ1,
SIZ0
(0, 0)
(0, 0)
†
Not (1, 1)
t
t
h(D)
su(D)
B0–B35
ODD/
EVEN
t
t
pd(D-PE)
pd(C-PE)
PEFB
Valid
Valid
†
SIZ0 = H and SIZ1 = H writes data to the mail2 register.
DATA SWAP TABLE FOR LONG-WORD WRITES TO FIFO2
SWAP MODE
DATA WRITTEN TO FIFO2
DATA READ FROM FIFO2
SW1
SW0 B35–B27 B26–B18 B17–B9
B8–B0
A35–A27 A26–A18 A17–A9
A8–A0
L
L
L
H
L
A
D
C
B
B
C
D
A
C
B
A
D
D
A
B
C
A
A
A
A
B
B
B
B
C
C
C
C
D
D
D
D
H
H
H
Figure 6. Port-B Long-Word Write Cycle for FIFO2
18
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SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
CLKB
High
FFB
CSB
t
t
t
h(EN)
su(EN)
su(EN)
W/RB
ENB
t
t
t
t
h(EN)
su(EN)
h(EN)
su(EN)
t
t
su(SW)
h(SW)
SW1, SW0
t
t
t
t
t
t
t
t
su(SZ)
su(SZ)
h(SZ)
h(SZ)
su(SZ)
su(SZ)
h(SZ)
h(SZ)
BE
†
Not (1, 1)
(0, 1)
(0, 1)
SIZ1, SIZ0
t
t
t
t
su(D)
su(D)
h(D)
h(D)
Little
Endian
B0–B17
Big
Endian
B18–B35
ODD/EVEN
t
t
pd(C-PE)
pd(D-PE)
Valid
Valid
PEFB
†
SIZ0 = H and SIZ1 = H writes data to the mail2 register.
NOTE A: PEFBindicates parity error forthefollowingbytes:B35–B27andB26–B18forbig-endianbus, andB17–B9andB8–B0forlittle-endian
bus.
DATA SWAP TABLE FOR WORD WRITES TO FIFO2
DATA WRITTEN TO FIFO2
SWAP MODE
DATA READ FROM FIFO2
WRITE
NO.
BIG ENDIAN
LITTLE ENDIAN
SW1
SW0
B35–B27 B26–B18 B17–B9
B8–B0
A35–A27 A26–A18 A17–A9
A8–A0
1
2
1
2
1
2
1
2
A
C
D
B
C
A
B
D
B
D
C
A
D
B
A
C
C
A
B
D
A
C
D
B
D
B
A
C
B
D
C
A
L
L
A
A
A
A
B
B
B
B
C
C
C
C
D
L
H
H
H
L
D
D
D
H
Figure 7. Port-B Word Write Cycle for FIFO2
19
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64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
CLKB
High
FFB
CSB
t
t
t
su(EN)
h(EN)
h(EN)
t
t
su(EN)
su(EN)
W/RB
ENB
t
t
t
su(EN)
h(EN)
h(EN)
t
su(SW)
SW1, SW0
t
t
t
h(SZ)
su(SZ)
t
t
su(SZ)
h(SZ)
BE
t
h(SZ)
su(SZ)
t
t
t
su(SZ)
h(SZ)
h(D)
(1, 0)
(1, 0)
(1, 0)
(1, 0)
SIZ1, SIZ0
B0–B8
†
Not (1, 1)
t
t
su(D)
su(D)
Little
Endian
t
h(D)
Big
Endian
B27–B35
ODD/EVEN
PEFB
t
t
t
t
pd(C-PE)
pd(D-PE)
pd(D-PE)
pd(D-PE)
Valid
Valid
Valid
Valid
†
SIZ0 = H and SIZ1 = H writes data to the mail2 register.
NOTE A: PEFB indicates parity error for the following bytes: B35–B27 for big-endian bus and B17–B9 for little-endian bus.
Figure 8. Port-B Byte Write Cycle for FIFO2
20
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64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
DATA SWAP TABLE FOR BYTE WRITES TO FIFO2
DATA WRITTEN
TO FIFO2
SWAP MODE
DATA READ FROM FIFO2
WRITE
NO.
BIG
LITTLE
ENDIAN
ENDIAN
SW1
SW0
B35–B27
B8–B0
A35–A27 A26–A18 A17–A9
A8–A0
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
A
B
C
D
D
C
B
A
C
D
A
B
B
A
D
C
D
C
B
A
A
B
C
D
B
A
D
C
C
D
A
B
L
L
A
A
A
A
B
B
B
B
C
C
C
C
D
L
H
H
H
L
D
D
D
H
Figure 8. Port-B Byte Write Cycle for FIFO2 (Continued)
21
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64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
CLKB
EFB
CSB
High
W/RB
t
t
t
t
h(EN)
su(EN)
h(EN)
su(EN)
ENB
No Operation
t
t
su(SW)
h(SW)
SW1,
SW0
t
t
t
su(SZ)
BE
h(SZ)
h(SZ)
t
su(SZ)
SIZ1,
SIZ0
†
†
t
(0, 0)
Not (1, 1)
(0, 0)
Not (1, 1)
t
t
h(PG)
su(PG)
PGB,
ODD/
EVEN
t
t
t
dis
en
a
a
‡
W1
‡
W2
B0–B35
Previous Data
†
‡
SIZ0 = H and SIZ1 = H selects the mail1 register for output on B0–B35.
Data read from FIFO1
DATA SWAP TABLE FOR LONG-WORD READS FROM FIFO1
DATA WRITTEN TO FIFO1 SWAP MODE DATA READ FROM FIFO1
A35–A27 A26–A18 A17–A9 A8–A0 SW1 SW0 B35–B27 B26–B18 B17–B9 B8–B0
A
A
A
A
B
B
B
B
C
C
C
C
D
D
D
D
L
L
L
H
L
A
D
C
B
B
C
D
A
C
B
A
D
D
A
B
C
H
H
H
Figure 9. Port-B Long-Word Read Cycle for FIFO1
22
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64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
CLKB
EFB
High
CSB
W/RB
t
t
su(EN)
h(EN)
ENB
No Operation
t
t
su(SW)
h(SW)
SW1,
SW0
t
t
t
su(SZ)
BE
h(SZ)
h(SZ)
t
su(SZ)
SIZ1,
SIZ0
†
†
Not (1, 1)
(0, 1)
Not (1, 1)
(0, 1)
t
t
h(PG)
su(PG)
PGB,
ODD/
EVEN
t
t
t
t
t
en
a
a
a
dis
Little
Endian
B0–B17
Previous Data
Read 1
Read 1
Read 2
‡
t
t
a
dis
Big
Endian
B18–B35
Previous Data
Read 2
‡
†
‡
SIZ0 = H and SIZ1 = H selects the mail1 register for output on B0–B35.
Unused word B0–B17 or B18–B35 holds last FIFO1 output register data for word-size reads.
DATA SWAP TABLE FOR WORD READS FROM FIFO1
DATA READ FROM FIFO1
BIG ENDIAN LITTLE ENDIAN
B35–B27 B26–B18 B17–B9
DATA WRITTEN TO FIFO1
SWAP MODE
READ
NO.
A35–A27 A26–A18 A17–A9
A8–A0
SW1
SW0
B8–B0
1
2
1
2
1
2
1
2
A
C
D
B
C
A
B
D
B
D
C
A
D
B
A
C
C
A
B
D
A
C
D
B
D
B
A
C
B
D
C
A
A
A
A
A
B
B
B
B
C
C
C
C
D
L
L
D
D
D
L
H
H
H
L
H
Figure 10. Port-B Word Read Cycle for FIFO1
23
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64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
CLKB
High
EFB
CSB
W/RB
t
t
t
su(EN)
h(EN)
h(SW)
ENB
No
Operation
t
su(SW)
SW1, SW0
t
t
t
su(SZ)
h(SZ)
h(SZ)
BE
t
su(SZ)
†
Not (1, 1)
SIZ1, SIZ0
(1, 0)
(1, 0)
(1, 0)
(1, 0)
†
†
†
Not (1, 1)
Not (1, 1)
Not (1, 1)
t
t
h(PG)
su(PG)
PGB,
ODD/EVEN
t
t
t
t
t
t
en
a
a
a
a
a
dis
B0–B8
Read 1
Read 2
Read 3
Read 4
Previous Data
t
t
t
t
t
a
a
a
dis
B27–B35
Read 1
Read 2
Read 3
Read 4
Previous Data
SIZ0 = H and SIZ1 = H selects the mail1 register for output on B0–B35.
NOTE A: Unused bytes hold last FIFO1 output register data for byte-size reads.
†
Figure 11. Port-B Byte Read Cycle for FIFO1
24
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64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
DATA SWAP TABLE FOR BYTE READS FROM FIFO1
DATA READ
FROM FIFO1
DATA WRITTEN TO FIFO1
SWAP MODE
READ
NO.
BIG
LITTLE
ENDIAN
ENDIAN
A35–A27 A26–A18 A17–A9
A8–A0
SW1
SW0
B35–B27
B8–B0
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
A
B
C
D
D
C
B
A
C
D
A
B
B
A
D
C
D
C
B
A
A
B
C
D
B
A
D
C
C
D
A
B
A
A
A
A
B
B
B
B
C
C
C
C
D
L
L
D
D
D
L
H
H
H
L
H
Figure 11. Port-B Byte Read Cycle for FIFO1 (Continued)
25
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64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
t
c
t
t
w(CLKL)
w(CLKH)
CLKA
EFA
CSA
High
W/RA
MBA
t
t
t
su(EN)
su(EN)
su(EN)
t
t
t
h(EN)
h(EN)
h(EN)
ENA
t
No
Operation
pd(M-DV)
t
t
dis
a
t
t
a
en
†
W1
†
W2
A0–A35
Previous Data
t
t
h(PG)
h(PG)
t
t
su(PG)
su(PG)
PGA,
ODD/EVEN
†
Read from FIFO2
Figure 12. Port-A Read Cycle for FIFO2
26
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64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
t
c
t
t
w(CLKL)
w(CLKH)
CLKA
Low
CSA
W/RA
High
t
su(EN)
t
t
h(EN)
MBA
ENA
t
su(EN)
h(EN)
High
FFA
t
su(D)
t
h(D)
A0–A35
W1
†
t
t
c
sk1
t
w(CLKL)
2
t
w(CLKH)
1
CLKB
EFB
t
t
pd(C-EF)
pd(C-EF)
FIFO1 Empty
CSB Low
W/RB
Low
SIZ1, SIZ0 Low
t
h(EN)
t
su(EN)
ENB
t
a
B0–B35
W1
†
t
is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition high in the next CLKB cycle. If the time
sk1
between the rising CLKA edge and rising CLKB edge is less than t
, the transition of EFB high may occur one CLKB cycle later than shown.
sk1
NOTE A: Port-B size of long word is selected for FIFO1 read by SIZ1 = L, SIZ0 = L. If port-B size is word or byte, EFB is set low by the last word
or byte read from FIFO1, respectively.
Figure 13. EFB-Flag Timing and First Data Read When FIFO1 Is Empty
27
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64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
t
c
t
t
w(CLKL)
w(CLKH)
CLKB
Low
CSB
W/RB
High
t
su(EN)
t
h(EN)
SIZ1, SIZ0
t
su(EN)
t
h(EN)
ENB
FFB
High
t
su(D)
t
h(D)
B0–B35
W1
t
c
†
t
sk1
t
w(CLKL)
2
t
w(CLKH)
1
CLKA
EFA
t
t
pd(C-EF)
pd(C-EF)
FIFO2 Empty
CSA Low
W/RA
Low
MBA Low
ENA
t
h(EN)
t
su(EN)
t
a
A0–A35
W1
†
t
is the minimum time between a rising CLKB edge and a rising CLKA edge for EFA to transition high in the next CLKA cycle. If the time
sk1
between the rising CLKB edge and rising CLKA edge is less than t
, the transition of EFA high may occur one CLKA cycle later than shown.
sk1
NOTE A: Port-B size of long word is selected for FIFO2 write by SIZ1 = L, SIZ0 = L. If port-B size is word or byte, t
CLKB edge that writes the last word or byte of the long word, respectively.
is referenced to the rising
sk1
Figure 14. EFA-Flag Timing and First Data Read When FIFO2 Is Empty
28
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64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
t
c
t
t
w(CLKL)
w(CLKH)
CLKB
Low
Low
Low
CSB
W/RB
SIZ1, SIZ0
t
t
h(EN)
su(EN)
ENB
EFB
High
t
a
B0–B35 Previous Word in FIFO1 Output Register
Next Word From FIFO1
†
t
sk1
t
c
t
t
w(CLKL)
w(CLKH)
1
2
CLKA
FFA
t
t
pd(C-FF)
pd(C-FF)
FIFO1 Full
CSA
Low
W/RA
High
t
t
t
h(EN)
su(EN)
MBA
ENA
t
su(EN)
h(EN)
h(D)
t
t
su(D)
A0–A35
To FIFO1
†
t
is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition high in the next CLKA cycle. If the time
sk1
between the rising CLKB edge and rising CLKA edge is less than t
, FFA may transition high one CLKA cycle later than shown.
sk1
NOTE A: Port-B size of long word is selected for the FIFO1 read by SIZ1 = L, SIZ0 = L. If port-B size is word or byte, t
the rising CLKB edge that reads the first word or byte of the long word, respectively.
is referenced from
sk1
Figure 15. FFA-Flag Timing and First Available Write When FIFO1 Is Full
29
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64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
t
c
t
t
w(CLKL)
w(CLKH)
CLKA
Low
Low
Low
CSA
W/RA
MBA
t
t
h(EN)
su(EN)
ENA
EFA
High
t
a
A0–A35 Previous Word in FIFO2 Output Register
Next Word From FIFO2
†
t
sk1
t
c
t
t
w(CLKH)
w(CLKL)
1
2
CLKB
FFB
t
t
pd(C-FF)
pd(C-FF)
FIFO2 Full
CSB
Low
High
W/RB
t
t
t
h(EN)
su(EN)
su(EN)
SIZ1, SIZ0
t
t
h(EN)
h(D)
ENB
t
su(D)
B0–B35
To FIFO2
is the minimum time between a rising CLKA edge and a rising CLKB edge for FFB to transition high in the next CLKB cycle. If the time
, FFB may transition high one CLKB cycle later than shown.
sk1
NOTE A: Port-B size of long word is selected for FIFO2 write by SIZ1 = L, SIZ0 = L. If port-B size is word or byte, FFB is set low by the last word
or byte write of the long word, respectively.
†
t
sk1
between the rising CLKA edge and rising CLKB edge is less than t
Figure 16. FFB-Flag Timing and First Available Write When FIFO2 Is Full
30
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64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
CLKA
ENA
t
h(EN)
†
t
su(EN)
t
sk2
CLKB
AEB
1
2
t
t
pd(C-AE)
pd(C-AE)
X Long Words in FIFO1
(X + 1) Long Words in FIFO1
t
h(EN)
t
su(EN)
ENB
†
t
is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition high in the next CLKB cycle. If the time
sk2
between the rising CLKA edge and rising CLKB edge is less than t
, AEB may transition high one CLKB cycle later than shown.
sk2
NOTES: A. FIFO1 write (CSA = L, W/RA = H, MBA = L), FIFO1 read (CSB = L, W/RB = L, MBB = L)
B. Port-B size of long word is selected for FIFO1 read by SIZ1 = L, SIZ0 = L. If port-B size is word or byte, AEB is set low by the first
word or byte read of the long word, respectively.
Figure 17. AEB When FIFO1 Is Almost Empty
CLKB
t
h(EN)
‡
t
su(EN)
ENB
t
sk2
CLKA
1
2
t
t
pd(C-AE)
pd(C-AE)
X Long Words in FIFO2
AEA
ENA
(X + 1) Long Words in FIFO2
t
h(EN)
t
su(EN)
‡
t
is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition high in the next CLKA cycle. If the time
sk2
between the rising CLKB edge and rising CLKA edge is less than t
, AEA may transition high one CLKA cycle later than shown.
sk2
NOTES: A. FIFO2 write (CSB = L, W/RB = H, MBB = L), FIFO2 read (CSA = L, W/RA = L, MBA = L)
B. Port-B size of long word is selected for FIFO2 write by SIZ1 = L, SIZ0 = L. If port-B size is word or byte, t
the rising CLKB edge that writes the last word or byte of the long word, respectively.
is referenced from
sk2
Figure 18. AEA When FIFO2 Is Almost Empty
31
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64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
†
t
sk2
CLKA
ENA
1
2
t
h(EN)
t
su(EN)
t
t
pd(C-AF)
pd(C-AF)
(64 – X) Long Words in FIFO1
AFA
[64 – (X + 1)] Long Words in FIFO1
CLKB
t
h(EN)
t
su(EN)
ENB
†
t
is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition high in the next CLKA cycle. If the time
sk2
between the rising CLKA edge and rising CLKB edge is less than t
, AFA may transition high one CLKB cycle later than shown.
sk2
NOTES: A. FIFO1 write (CSA = L, W/RA = H, MBA = L), FIFO1 read (CSB = L, W/RB = L, MBB = L)
B. Port-B size of long word is selected for FIFO1 read by SIZ1 = L, SIZ0 = L. If port-B size is word or byte, t
the first word or byte read of the long word, respectively.
is referenced from
sk2
Figure 19. AFA When FIFO1 Is Almost Full
‡
t
sk2
CLKB
ENB
1
2
t
h(EN)
t
su(EN)
t
t
pd(C-AF)
pd(C-AF)
(64 – X) Long Words in FIFO2
AFB
[64 – (X + 1)] Long Words in FIFO2
CLKA
t
h(EN)
t
su(EN)
ENA
‡
t
is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition high in the next CLKB cycle. If the time
sk2
between the rising CLKB edge and rising CLKA edge is less than t
, AFB may transition high one CLKA cycle later than shown.
sk2
NOTES: A. FIFO2 write (CSB = L, W/RB= H, MBB = L), FIFO2 read (CSA = L, W/RA = L, MBA = L)
B. Port-B size of long word is selected for FIFO2 write by SIZ1 = L, SIZ0 = L. If port-B size is word or byte, AFB is set low by the last
word or byte write of the long word, respectively.
Figure 20. AFB When FIFO2 Is Almost Full
32
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64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
CLKA
t
h(EN)
t
su(EN)
CSA
W/RA
MBA
ENA
t
h(D)
t
su(D)
A0–A35
W1
CLKB
MBF1
t
t
pd(C-MF)
pd(C-MF)
CSB
W/RB
SIZ1, SIZ0
ENB
t
h(EN)
t
su(EN)
t
pd(M-DV)
t
t
t
pd(C-MR)
dis
en
W1 (remains valid in mail1 register after read)
B0–B35
FIFO1 Output Register
NOTE A: Port-B parity generation off (PGB = L)
Figure 21. Mail1 Register and MBF1 Flag
33
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64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
CLKB
t
h(EN)
t
su(EN)
CSB
W/RB
t
h(SZ)
h(D)
t
su(SZ)
SIZ1, SIZ0
ENB
t
t
su(D)
B0–B35
W1
CLKA
MBF2
CSA
t
t
pd(C-MF)
pd(C-MF)
W/RA
MBA
t
h(EN)
t
su(EN)
ENA
t
pd(M-DV)
t
t
t
en
pd(C-MR)
dis
A0–A35
W1 (remains valid in mail2 register after read)
FIFO2 Output Register
NOTE A: Port-A parity generation off (PGA = L)
Figure 22. Mail2 Register and MBF2 Flag
34
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64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
ODD/EVEN
W/RA
MBA
PGA
t
t
t
t
pd(E-PE)
pd(O-PE)
Valid
pd(O-PE)
Valid
pd(E-PE)
Valid
Valid
PEFA
NOTE A: ENA is high and CSA is low.
Figure 23. ODD/EVEN, W/RA, MBA, and PGA to PEFA
ODD/EVEN
W/RB
SIZ1,
SIZ0
PGB
t
t
t
t
pd(E-PE)
pd(O-PE)
Valid
pd(O-PE)
Valid
pd(E-PE)
Valid
PEFB
Valid
NOTE A: ENB is high and CSB is low.
Figure 24. ODD/EVEN, W/RB, SIZ1, SIZ0, and PGB to PEFB
35
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SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
ODD/
EVEN
CSA
W/RA
MBA
Low
PGA
t
pd(E-PB)
pd(M-DV)
t
t
pd(O-PB)
pd(E-PB)
t
t
en
A8, A17,
A26, A35
Generated Parity
Generated Parity
Mail2 Data
Mail2
Data
NOTE A: ENA is high.
Figure 25. Parity-Generation Timing When Reading From the Mail2 Register
ODD/
EVEN
CSB
Low
W/RB
SIZ1,
SIZ0
PGB
t
pd(E-PB)
pd(M-DV)
t
t
pd(O-PB)
pd(E-PB)
t
t
en
B8, B17,
B26, B35
Generated Parity
Generated Parity
Mail1 Data
Mail1
Data
NOTE A: ENB is high.
Figure 26. Parity-Generation Timing When Reading From the Mail1 Register
36
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SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through V
Storage temperature range, T
O
O
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±500 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
CC
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
recommended operating conditions
MIN
MAX
UNIT
V
V
V
V
Supply voltage
4.5
2
5.5
CC
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Operating free-air temperature
V
IH
0.8
–4
V
IL
I
I
mA
mA
°C
OH
8
OL
T
A
–55
125
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
‡
PARAMETER
TEST CONDITIONS
= –4 mA
MIN TYP
MAX
UNIT
V
V
V
V
V
V
V
= 4.5 V,
= 4.5 V,
= 5.5 V,
= 5.5 V,
I
I
2.4
OH
CC
CC
CC
CC
OH
= 8 mA
or 0
0.5
±50
±50
30
V
OL
OL
I
I
V = V
µA
µA
I
CC
= V or 0
CC
I
V
OZ
O
Outputs high
Outputs low
§
I
V
CC
= 5.5 V,
I
O
= 0 mA,
V = V or GND
I CC
130
30
mA
CC
Outputs disabled
C
C
V = 0,
f = 1 MHz
f = 1 MHz
4
8
pF
pF
i
I
V
O
= 0,
o
‡
§
All typical values are at V
= 5 V, T = 25°C.
A
CC
is measured in the A-to-B direction.
I
CC
37
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64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Figures 4 through 27)
MIN
MAX
UNIT
MHz
ns
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Clock frequency, CLKA or CLKB
50
clock
Clock cycle time, CLKA or CLKB
20
8
c
Pulse duration, CLKA and CLKB high
ns
w(CLKH)
w(CLKL)
su(D)
Pulse duration, CLKA and CLKB low
8
ns
Setup time, A0–A35 before CLKA↑ and B0–B35 before CLKB↑
Setup time, CSA, W/RA, ENA, and MBA before CLKA↑; CSB, W/RB, and ENB before CLKB↑
Setup time, SIZ0, SIZ1, and BE before CLKB↑
Setup time, SW0 and SW1 before CLKB↑
5
ns
5
ns
su(EN)
su(SZ)
su(SW)
su(PG)
su(RS)
su(FS)
h(D)
5
ns
7
ns
†
Setup time, ODD/EVEN and PGA before CLKA↑; ODD/EVEN and PGB before CLKB↑
6
ns
‡
Setup time, RST low before CLKA↑ or CLKB↑
6
ns
Setup time, FS0 and FS1 before RST high
6
ns
Hold time, A0–A35 after CLKA↑ and B0–B35 after CLKB↑
3
ns
Hold time, CSA, W/RA, ENA, and MBA after CLKA↑; CSB, W/RB, and ENB after CLKB↑
Hold time, SIZ0, SIZ1, and BE after CLKB↑
3
ns
h(EN)
h(SZ)
2
ns
Hold time, SW0 and SW1 after CLKB↑
7
ns
h(SW)
h(PG)
h(RS)
h(FS)
†
Hold time, ODD/EVEN and PGA after CLKA↑; ODD/EVEN and PGB after CLKB↑
1
ns
‡
Hold time, RST low after CLKA↑ or CLKB↑
6
ns
Hold time, FS0 and FS1 after RST high
4
ns
§
Skew time between CLKA↑ and CLKB↑ for EFA, EFB, FFA, and FFB
Skew time between CLKA↑ and CLKB↑ for AEA, AEB, AFA, and AFB
8
ns
sk1
§
16
ns
sk2
†
‡
§
Applies only for a clock edge that does a FIFO read
Requirement to count the clock edge as one of at least four needed to reset a FIFO
Skew time is not a timing constraint for proper device operation and is included only to illustrate the timing relationship between CLKA cycle and
CLKB cycle.
38
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64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
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SGBS308F – AUGUST 1995 – REVISED MAY 2000
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 30 pF (see Figures 4 through 27)
L
PARAMETER
MIN
50
2
MAX
UNIT
MHz
ns
f
t
t
t
t
t
max
Access time, CLKA↑ to A0–A35 and CLKB↑ to B0–B35
Propagation delay time, CLKA↑ to FFA and CLKB↑ to FFB
Propagation delay time, CLKA↑ to EFA and CLKB↑ to EFB
Propagation delay time, CLKA↑ to AEA and CLKB↑ to AEB
Propagation delay time, CLKA↑ to AFA and CLKB↑ to AFB
12
12
12
12
12
a
2
ns
pd(C-FF)
pd(C-EF)
pd(C-AE)
pd(C-AF)
2
ns
2
ns
2
ns
Propagation delay time, CLKA↑ to MBF1 low or MBF2 high and
CLKB↑ to MBF2 low or MBF1 high
t
1
12
ns
pd(C-MF)
†
‡
t
t
t
t
t
t
Propagation delay time, CLKA↑ to B0–B35 and CLKB↑ to A0–A35
3
2
1
3
3
2
13
12
ns
ns
ns
ns
ns
ns
pd(C-MR)
§
Propagation delay time, CLKB↑ to PEFB
pd(C-PE)
pd(M-DV)
pd(D-PE)
pd(O-PE)
pd(O-PB)
Propagation delay time, MBA to A0–A35 valid and SIZ1, SIZ0 to B0–B35 valid
Propagation delay time, A0-A35 valid to PEFA valid; B0-B35 valid to PEFB valid
Propagation delay time, ODD/EVEN to PEFA and PEFB
11.5
12.5
14
Propagation delay time, ODD/EVEN to parity bits (A8, A17, A26, A35) and (B8, B17, B26, B35)
12
Propagation delay time, CSA, ENA, W/RA, MBA, or PGA to PEFA; CSB, ENB, W/RB, SIZ1,
SIZ0, or PGB to PEFB
t
1
23
ns
pd(E-PE)
Propagation delay time, MBA or PGA to parity bits (A8, A17, A26, A35); SIZ1, SIZ0, or PGB to
parity bits (B8, B17, B26, B35)
t
t
t
3
1
2
19
20
12
ns
ns
ns
pd(E-PB)
pd(R-F)
en
Propagation delay time, RST to (MBF1, MBF2) high
Enable time, CSA and W/RA low to A0–A35 active and
CSB low and W/RB high to B0–B35 active
Disable time, CSA or W/RA high to A0–A35 at high impedance and
CSB high or W/RB low to B0–B35 at high impedance
t
1
9
ns
dis
†
‡
§
¶
Writing data to the mail1 register when the B0–B35 outputs are active and SIZ1, SIZ0 are high
Writing data to the mail2 register when the A0–A35 outputs are active and MBA is high
Applies only when a new port-B bus size is implemented by the rising CLKB edge
Applies only when reading data from a mail register
39
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
PARAMETER MEASUREMENT INFORMATION
5 V
1.1 kΩ
From Output
Under Test
30 pF
680 Ω
(see Note A)
LOAD CIRCUIT
3 V
High-Level
Input
3 V
1.5 V
t
1.5 V
1.5 V
Timing
Input
1.5 V
GND
GND
3 V
w
t
h
t
su
3 V
Data,
Enable
Input
Low-Level
Input
1.5 V
1.5 V
1.5 V
GND
GND
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3 V
Output
Enable
1.5 V
1.5 V
GND
t
t
PZL
PLZ
≈ 3 V
Low-Level
Output
3 V
1.5 V
1.5 V
1.5 V
Input
V
V
OL
GND
t
PZH
t
t
pd
OH
pd
High-Level
Output
V
1.5 V
OH
In-Phase
Output
≈ 0 V
1.5 V
1.5 V
t
V
OL
PHZ
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
ENABLE AND DISABLE TIMES
NOTES: A. Includes probe and jig capacitance
B.
C.
t
t
and t
and t
are the same as t
are the same as t
PZL
PLZ
PZH
PHZ
en
dis
Figure 27. Load Circuit and Voltage Waveforms
40
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT3614
64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
WITH BUS MATCHING AND BYTE SWAPPING
SGBS308F – AUGUST 1995 – REVISED MAY 2000
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
CLOCK FREQUENCY
400
f
T
C
= 1/2 f
data
= 25°C
clock
V
CC
= 5.5 V
A
350
300
250
200
150
100
50
= 0 pF
L
V
CC
= 5 V
V
CC
= 4.5 V
0
0
10
20
30
40
50
60
70
80
f
– Clock Frequency – MHz
clock
Figure 28
41
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pertaining to warranty, patent infringement, and limitation of liability.
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