SN54ABTH32501 [TI]
36-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS; 具有三态输出的36位通用总线收发器
| 型号： | SN54ABTH32501 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 36-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS |
| 文件： | 总9页 (文件大小：137K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54ABTH32501, SN74ABTH32501
36-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS229F – JUNE 1992 – REVISED MAY 1997
Members of the Texas Instruments
Widebus+ Family
Typical V
< 0.8 V at V
(Output Ground Bounce)
OLP
= 5 V, T = 25°C
CC
A
High-Impedance State During Power Up
and Power Down
State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
Distributed V
Minimizes High-Speed Switching Noise
and GND Pin Configuration
UBT (Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, or Clocked Mode
CC
High-Drive Outputs (–32-mA I , 64-mA I
OH
)
OL
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Package Options Include 100-Pin Plastic
Thin Quad Flat (PZ) Package With
14 × 14-mm Body Using 0.5-mm Lead Pitch
and Space-Saving 100-Pin Ceramic Quad
Flat (HS) Package
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
Released as DSCC SMD 5962-9557601NXD
†
’ABTH32501 . . . PZ PACKAGE
(TOP VIEW)
1009998 9796 959493 929190898887868584 8382818079787776
2B10
2B9
GND
2B8
2B7
2B6
2B5
GND
2B4
2B3
2B2
2B1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
2A10
2A9
GND
2A8
2A7
2A6
2A5
GND
2A4
2A3
2A2
2A1
V
V
CC
CC
1B1
1B2
1B3
1B4
GND
1B5
1B6
1B7
1B8
GND
1B9
1B10
1A1
1A2
1A3
1A4
GND
1A5
1A6
1A7
1A8
GND
1A9
1A10
26272829303132333435363738394041424344454647484950
†
The HS package is not production released.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+, EPIC-ΙΙB, and UBT are trademarks of Texas Instruments Incorporated.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABTH32501, SN74ABTH32501
36-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS229F – JUNE 1992 – REVISED MAY 1997
†
SN54ABTH32501 . . . HS PACKAGE
(TOP VIEW)
2A13
2A12
2A11
2A10
2A9
GND
2A8
2A7
2A6
2A5
GND
2A4
2A3
2B12
2B11
2B10
2B9
GND
2B8
2B7
2B6
2B5
GND
2B4
2B3
2B2
2B1
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
2A2
V
2A1
CC
V
1B1
1B2
1B3
1B4
GND
1B5
1B6
1B7
1B8
GND
1B9
1B10
1B11
1B12
1B13
CC
1A1
1A2
1A3
1A4
GND
1A5
1A6
1A7
1A8
GND
1A9
1A10
1A11
1A12
†
For HS package availability, please contact the factory or your local TI Field Sales Office.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABTH32501, SN74ABTH32501
36-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS229F – JUNE 1992 – REVISED MAY 1997
description
These 36-bit UBTs combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, and
clocked modes.
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),
and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when
LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is
low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. Data flow for B to A is similar
to that of A to B, but uses OEBA, LEBA, and CLKBA.
Output-enable OEAB is active high. When OEAB is high, the outputs are active. When OEAB is low, the outputs
are in the high-impedance state. The output enables are complementary (OEAB is active high, and OEBA is
active low).
When V
is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 2.1 V, OE should be tied to V
through a pullup resistor
CC
and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by
the current-sinking/current-sourcing capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN54ABTH32501 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABTH32501 is characterized for operation from –40°C to 85°C.
†
FUNCTION TABLE
INPUTS
OUTPUT
B
OEAB
LEAB
CLKAB
A
X
L
L
X
H
H
L
X
X
X
↑
Z
L
H
H
H
H
H
H
H
L
H
L
L
↑
H
X
X
H
‡
B
0
§
B
0
L
H
L
L
†
‡
§
A-to-B data flow is shown: B-to-A flow is similar, but
uses OEBA, LEBA, and CLKBA.
Output level before the indicated steady-state input
conditions were established
Output level before the indicated steady-state input
conditions were established, provided that CLKAB
was low before LEAB went low
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABTH32501, SN74ABTH32501
36-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS229F – JUNE 1992 – REVISED MAY 1997
logic diagram (positive logic)
41
1OEAB
37
1CLKBA
36
1LEBA
35
1OEBA
39
1CLKAB
1LEAB
1A1
CLK
LE
40
14
62
1B1
D
CLK
LE
D
To 17 Other Channels
85
2OEAB
89
90
2CLKBA
2LEBA
2OEBA
2CLKAB
2LEAB
2A1
91
87
86
12
CLK
64
2B1
LE
D
CLK
LE
D
To 17 Other Channels
Pin numbers shown are for the PZ package.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABTH32501, SN74ABTH32501
36-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS229F – JUNE 1992 – REVISED MAY 1997
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high or power-off state, V
. . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
O
Current into any output in the low state, I : SN54ABTH32501 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
O
SN74ABTH32501 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Package thermal impedance, θ (see Note 2): PZ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50°C/W
Storage temperature range, T
JA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
recommended operating conditions (see Note 3)
SN54ABTH32501 SN74ABTH32501
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
V
V
V
Supply voltage
5.5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
Input voltage
IH
0.8
0.8
V
IL
0
V
0
V
CC
V
I
CC
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Power-up ramp rate
–24
48
–32
64
mA
mA
ns/V
µs/V
°C
OH
OL
∆t/∆v
∆t/∆V
Outputs enabled
10
10
200
–55
200
–40
CC
T
Operating free-air temperature
125
85
A
NOTE 3: Unused control pins must be held high or low to prevent them from floating.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABTH32501, SN74ABTH32501
36-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS229F – JUNE 1992 – REVISED MAY 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54ABTH32501
SN74ABTH32501
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
V
= 4.5 V,
= 4.5 V,
= 5 V,
I = –18 mA
–1.2
–1.2
V
IK
CC
CC
CC
I
I
I
I
I
I
I
= –3 mA
= –3 mA
= –24 mA
= –32 mA
= 48 mA
= 64 mA
2.5
3
2.5
3
OH
OH
OH
OH
OL
OL
V
OH
2
V
= 4.5 V
= 4.5 V
CC
CC
2
0.55
0.55
0.55
V
V
V
V
OL
100
100
mV
hys
Control inputs
A or B ports
Control inputs
A or B ports
V
V
= 0 to 5.5 V,
V = V
or GND
or GND
±1
CC
I
CC
CC
= 2.1 V to 5.5 V,
V = V
I
±20
CC
I
µA
µA
I
±5
V
CC
= 5.5 V,
= 4.5 V
V = V
I
or GND
CC
±50
V = 0.8 V
I
100
100
I
A or B ports
V
V
I(hold)
CC
V = 2 V
I
–100
–100
= 0 to 2.1 V, V = 0.5 V to 2.7 V,
CC
O
‡
±50
±50
±50
±50
µA
µA
I
I
OZPU
OE or OE = X
V
= 2.1 V to 0, V = 0.5 V to 2.7 V,
CC
OE or OE = X
O
‡
OZPD
I
I
I
V
V
V
= 0,
V or V ≤ 4.5 V
±100
50
µA
µA
off
CC
CC
CC
I
O
= 5.5 V, V = 5.5 V
O
Outputs high
= 2.5 V
50
–180
6
CEX
§
= 5.5 V,
V
O
–50
–100
–50
–100
–180
6
mA
O
Outputs high
Outputs low
V
= 5.5 V, I = 0,
O
or GND
CC
CC
I
90
90
mA
CC
V = V
I
Outputs disabled
6
6
V
= 5.5 V, One input at 3.4 V,
CC
Other inputs at V
¶
1
1
mA
∆I
CC
or GND
CC
Control inputs V = 2.5 V or 0.5 V
C
C
3.5
3.5
pF
pF
i
I
A or B ports
V
O
= 2.5 V or 0.5 V
11.5
11.5
io
†
‡
§
¶
All typical values are at V
This parameter is specified by characterization.
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V or GND.
= 5 V, T = 25°C.
A
CC
CC
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
SN54ABTH32501 SN74ABTH32501
UNIT
MIN
MAX
MIN
MAX
f
t
Clock frequency
Pulse duration
0
150
0
150
MHz
ns
clock
LE high
3.5
3.5
4.3
2.5
0.2
1.8
3.3
3.3
3.5
1.6
0
w
CLK high or low
A or B before CLK↑
A or B before LE↓
A or B after CLK↑
A or B after LE↓
t
t
Setup time
Hold time
ns
ns
su
h
1.6
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABTH32501, SN74ABTH32501
36-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS229F – JUNE 1992 – REVISED MAY 1997
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (unless otherwise noted) (see Figure 1)
L
SN54ABTH32501
†
SN74ABTH32501
†
MAX
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MHz
ns
MIN TYP
MAX
MIN TYP
f
t
t
t
t
t
t
t
t
t
t
150
150
max
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
0.5
0.5
0.7
0.7
0.5
0.7
0.5
0.5
0.7
0.7
2.9
5.2
5.8
5.7
5.9
5.7
5.8
6.2
6.6
7
1.3
1.4
1.6
1.9
1.5
1.7
1.2
1.5
1.8
1.7
2.9
4.8
5.4
5.3
5.5
5.3
5.4
5.6
6
A or B
B or A
A or B
A or B
A or B
A or B
2.7
3.4
3.6
3.2
3.3
3.2
3.6
3.6
3.5
2.7
3.4
3.6
3.2
3.3
3.2
3.6
3.6
3.5
LEAB or LEBA
CLKAB or CLKBA
ns
ns
ns
ns
OEAB or OEBA
OEAB or OEBA
5.9
5.6
6.1
†
All typical values are at V
= 5 V, T = 25°C.
A
CC
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABTH32501, SN74ABTH32501
36-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS229F – JUNE 1992 – REVISED MAY 1997
PARAMETER MEASUREMENT INFORMATION
7 V
Open
TEST
/t
S1
S1
500 Ω
From Output
Under Test
t
Open
7 V
PLH PHL
GND
t
/t
PLZ PZL
C
= 50 pF
t
/t
Open
L
PHZ PZH
500 Ω
(see Note A)
3 V
0 V
LOAD CIRCUIT
Timing Input
Data Input
1.5 V
t
w
t
t
h
su
3 V
0 V
3 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
PZL
t
t
t
PHL
PLH
PHL
t
PLZ
Output
Waveform 1
S1 at 7 V
3.5 V
V
V
OH
1.5 V
1.5 V
1.5 V
1.5 V
Output
V
V
+ 0.3 V
OL
V
OL
OL
(see Note B)
t
PHZ
t
PLH
t
PZH
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
V
OH
– 0.3 V
OH
1.5 V
1.5 V
Output
≈ 0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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Copyright 1998, Texas Instruments Incorporated
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