SN54ACT16373_13 [TI]
16-BIT D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS;
| 型号： | SN54ACT16373_13 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-BIT D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS 输出元件 |
| 文件： | 总6页 (文件大小：104K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54ACT16373, 74ACT16373
16-BIT D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS122C – MARCH 1990 – REVISED SEPTEMBER 1996
SN54ACT16373 . . . WD PACKAGE
74ACT16373 . . . DL PACKAGE
(TOP VIEW)
Members of the Texas Instruments
Widebus Family
Inputs Are TTL-Voltage Compatible
3-State Bus Driving True Outputs
Full Parallel Access for Loading
1OE
1Q1
1Q2
GND
1Q3
1Q4
1C
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
1D1
1D2
GND
1D3
1D4
2
3
Flow-Through Architecture Optimizes
PCB Layout
4
5
Distributed V
Minimizes High-Speed Switching Noise
and GND Pin Configuration
CC
6
V
V
7
CC
CC
EPIC (Enhanced-Performance Implanted
CMOS) 1- m Process
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
1D5
1D6
GND
1D7
1D8
2D1
2D2
8
9
500-mA Typical Latch-Up Immunity at
125°C
10
11
12
13
14
Package Options Include Shrink
Small-Outline (DL) 300-mil Packages Using
25-mil Center-to-Center Pin Spacings and
380-mil Fine-Pitch Ceramic Flat (WD)
Packages Using 25-mil Center-to-Center
Pin Spacings
GND 15
2Q3 16
2Q4 17
34 GND
33 2D3
32 2D4
18
19
20
21
22
23
24
31
30
29
28
27
26
25
V
V
CC
CC
description
2Q5
2Q6
GND
2Q7
2Q8
2OE
2D5
2D6
GND
2D7
2D8
2C
The SN54ACT16373 and 74ACT16373 are 16-bit
D-type transparent latches with 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers. These devices can be used as
two 8-bit latches or one 16-bit latch. The Q outputs
of the latches follow the data (D) inputs if enable
Cistakenhigh. WhenCistakenlow, theQoutputs
are latched at the levels set up at the D inputs.
A buffered output-enable (OE) input can be used to place the outputs in either a normal logic state (high or low
logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the
buslinessignificantly. Thehigh-impedancestateandtheincreaseddriveprovidethecapabilitytodrivebuslines
in a bus-organized system without need for interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
The 74ACT16373 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and
functionality of standard small-outline packages in the same printed-circuit-board area.
The SN54ACT16373 is characterized for operation over the full military temperature range of –55°C to 125°C.
The 74ACT16373 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ACT16373, 74ACT16373
16-BIT D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS122C – MARCH 1990 – REVISED SEPTEMBER 1996
FUNCTION TABLE
INPUTS
OUTPUT
Q
D
H
L
OE
L
C
H
H
L
H
L
L
L
X
X
Q
0
H
X
Z
†
logic symbol
1
1OE
1C
1EN
C1
48
24
25
2EN
C4
2OE
2C
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
2
3
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
1D
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
1
2
5
6
8
9
11
12
13
14
16
17
19
20
22
23
3D
1
4
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ACT16373, 74ACT16373
16-BIT D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS122C – MARCH 1990 – REVISED SEPTEMBER 1996
logic diagram (positive logic)
1
24
25
2OE
2C
1OE
48
1C
C1
C1
2
13
2Q1
1Q1
47
36
1D
2D1
1D1
1D
To Seven Other Channels
To Seven Other Channels
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through V
Maximum power dissipation at T = 55°C (in still air) (see Note 2): DL package . . . . . . . . . . . . . . . . . . . 1.2 W
Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±400 mA
A
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150 C and a board trace length of 750 mils.
recommended operating conditions (see Note 3)
SN54ACT16373 74ACT16373
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
V
V
V
V
Supply voltage (see Note 4)
High-level input voltage
Low-level input voltage
Input voltage
5.5
5.5
V
V
CC
IH
IL
0.8
0.8
V
0
0
V
V
0
0
V
V
V
I
CC
CC
Output voltage
V
O
CC
CC
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
–24
24
–24
24
mA
mA
ns/V
°C
OH
OL
t/ v
0
10
0
10
T
–55
125
–40
85
A
NOTES: 3. Unused inputs should be tied to V
through a pullup resistor of approximately 5 k or greater to prevent them from floating.
CC
4. All V
and GND pins must be connected to the proper voltage supply.
CC
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ACT16373, 74ACT16373
16-BIT D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS122C – MARCH 1990 – REVISED SEPTEMBER 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
SN54ACT16373
74ACT16373
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
4.4
TYP
MAX
MIN
4.4
MAX
MIN
4.4
5.4
3.8
4.8
MAX
4.5 V
5.5 V
4.5 V
5.5 V
5.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
I
I
= –50
A
OH
5.4
5.4
3.94
4.94
3.7
= –24 mA
V
OH
V
OH
4.7
3.85
I
I
= –50 mA
= –75 mA
OH
3.85
OH
0.1
0.1
0.1
0.1
0.1
0.1
I
I
= 50 A
OL
0.36
0.36
0.5
0.44
0.44
= 24 mA
V
OL
V
OL
0.5
1.65
I
I
= 50 mA
= 75 mA
OL
1.65
±1
OL
I
I
I
V = V
or GND
±0.1
±0.5
8
±1
±10
160
A
A
A
I
I
CC
V
= V
or GND
±5
OZ
CC
O
CC
V = V
or GND,
I
O
= 0
80
I
CC
One input at 3.4 V,
Other inputs at GND or V
5.5 V
0.9
1
1
mA
I
CC
CC
C
C
V = V
or GND
or GND
5 V
5 V
4.5
12
pF
pF
i
I
CC
CC
V = V
I
o
†
‡
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V to V
.
CC
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
T
= 25°C
SN54ACT16373
74ACT16373
A
UNIT
MIN
4
MAX
MIN
4
MAX
MIN
1
MAX
t
w
t
su
t
h
Pulse duration, LE high
Setup time, data before LE↓
Hold time, data after LE↓
ns
ns
ns
1
1
1
5
5
5
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
7.9
SN54ACT16373 74ACT16373
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
ns
MIN
3.8
3.1
4.6
4.5
3.1
3.8
5.3
4.3
MAX
9.4
MIN
3.8
3.1
4.6
4.5
3.1
3.8
5.3
4.3
MAX
11.8
13
MIN
3.8
3.1
4.6
4.5
3.1
3.8
5.3
4.3
MAX
11.1
12.3
12.8
12.2
12.1
14.2
10.7
9.4
t
t
t
t
t
t
t
t
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
D
Q
Q
Q
Q
8.2
9.7
9.3
10.8
10.5
9.5
13.7
13
LE
OE
OE
ns
9.1
8
13
ns
9.4
11.1
9.9
15.1
11
8.6
ns
7.4
8.7
9.8
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ACT16373, 74ACT16373
16-BIT D-TYPE TRANSPARENT LATCHES
WITH 3-STATE OUTPUTS
SCAS122C – MARCH 1990 – REVISED SEPTEMBER 1996
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
= 50 pF, f = 1 MHz
L
TYP
43
UNIT
Outputs enabled
Outputs disabled
C
Power dissipation capacitance per latch
C
pF
pd
4.5
PARAMETER MEASUREMENT INFORMATION
2 × V
CC
Open
GND
TEST
S1
Open
2 × V
S1
t
/t
PLH PHL
/t
500 Ω
From Output
Under Test
t
PLZ PZL
/t
CC
GND
t
PHZ PZH
C
= 50 pF
L
500 Ω
(see Note A)
LOAD CIRCUIT
3 V
1.5 V
Timing Input
Data Input
0 V
3 V
0 V
t
w
t
h
t
3 V
0 V
su
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
3 V
0 V
3 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
t
PZL
t
t
t
PHL
PLH
t
PLZ
Output
Waveform 1
V
OH
V
CC
In-Phase
Output
50% V
50% V
CC
50% V
50% V
CC
V
CC
20% V
S1 at 2 × V
(see Note B)
CC
CC
CC
V
V
OL
OL
t
PHZ
t
PLH
t
PHL
PZH
Output
Waveform 2
S1 at GND
V
OH
OH
0 V
Out-of-Phase
Output
80% V
50% V
50% V
CC
CC
CC
V
OL
(see Note B)
VOLTAGE WAVEFORMS
includes probe and jig capacitance.
VOLTAGE WAVEFORMS
NOTES: A.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 3 ns, t = 3 ns.
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
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BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
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party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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