SN54ACT8990FJR [TI]
SPECIALTY MICROPROCESSOR CIRCUIT, PQCC44;
| 型号： | SN54ACT8990FJR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQCC44 总线控制器 |
| 文件： | 总15页 (文件大小：303K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54ACT8990, SN74ACT8990
TEST-BUS CONTROLLERS
IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 16-BIT GENERIC HOST INTERFACES
SCAS190E – JUNE 1990 – REVISED JANUARY 1997
32
Members of the Texas Instruments
SCOPE Family of Testability Products
Execute Instructions for Up to 2 Clock
Cycles
Compatible With the IEEE Standard
1149.1-1990 (JTAG) Test Access Port and
Boundary-Scan Architecture
Each Device Includes Four Bidirectional
Event Pins for Additional Test Capability
Inputs Are TTL-Voltage Compatible
Control Operation of Up to Six Parallel
Target Scan Paths
EPIC (Enhanced-Performance Implanted
CMOS) 1-µm Process
Accommodate Pipeline Delay to Target of
Up to 31 Clock Cycles
Packaged in 44-Pin Plastic Leaded Chip
Carrier (FN), 68-Pin Ceramic Pin Grid Array
(GB), and 68-Pin Ceramic Quad Flat
Packages (HV)
32
Scan Data Up to 2 Clock Cycles
description
The ’ACT8990 test-bus controllers (TBC) are members of the Texas Instruments SCOPE testability
integrated-circuit family. This family of components supports IEEE Standard 1149.1-1990 (JTAG) boundary
scan to facilitate testing of complex circuit-board assemblies. The ’ACT8990 differ from other SCOPE
integrated circuits. Their function is to control the JTAG serial-test bus rather than being target
boundary-scannable devices.
TherequiredsignalsoftheJTAGserial-testbus–testclock(TCK), testmodeselect(TMS), testdatainput(TDI),
and test data output (TDO) can be connected from the TBC to a target device without additional logic. This is
done as a chain of IEEE Standard 1149.1-1990 boundary-scannable components that share the same
serial-testbus. TheTBCgeneratesTMSandTDIsignalsforitstarget(s), receivesTDOsignalsfromitstarget(s),
and buffers its test clock input (TCKI) to a test clock output (TCKO) for distribution to its target(s). The TMS, TDI,
and TDO signals can be connected to a target directly or via a pipeline, with a retiming delay of up to 31 bits.
Since the TBC can be configured to generate up to six separate TMS signals [TMS (5 –0)], it can be used to
control up to six target scan paths that are connected in parallel (i.e., sharing common TCK, TDI, and TDO
signals).
While most operations of the TBC are synchronous to TCKI, a test-off (TOFF) input is provided for output control
of the target interface, and a test-reset (TRST) input is provided for hardware/software reset of the TBC. In
addition, four event [EVENT (3–0)] I/Os are provided for asynchronous communication to target device(s).
Each event has its own event generation/detection logic, and detected events can be counted by two 16-bit
counters.
The TBC operates under the control of a host microprocessor/microcontroller via the 5-bit address bus
[ADRS (4–0)] and the 16-bit read/write data bus [DATA (15–0)]. Read (RD) and write (WR) strobes are
implemented such that the critical host-interface timing is independent of the TCKI period. Any one of
24 registers can be addressed for read and/or write operations. In addition to control and status registers, the
TBC contains two command registers, a read buffer, and a write buffer. Status of the TBC is transmitted to the
host via ready (RDY) and interrupt (INT) outputs.
Major commands can be issued by the host to cause the TBC to generate the TMS sequences necessary to
move the target(s) from any stable test-access-port (TAP) controller state to any other stable TAP state, to
execute instructions in the Run-Test/Idle TAP state, or to scan instruction or test data through the target(s). A
32-bit counter can be preset to allow a predetermined number of execution or scan operations.
Serial data that appears at the selected TDI input (TDI1 or TDI0) is transferred into the read buffer, which can
be read by the host to obtain up to 16 bits of the serial-data stream. Serial data that is transmitted from the TDO
output is written by the host to the write buffer.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SCOPE and EPIC are trademarks of Texas Instruments Incorporated.
Copyright 1997, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ACT8990, SN74ACT8990
TEST-BUS CONTROLLERS
IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 16-BIT GENERIC HOST INTERFACES
SCAS190E – JUNE 1990 – REVISED JANUARY 1997
description (continued)
The SN54ACT8990 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ACT8990 is characterized for operation from 0°C to 70°C.
SN54ACT8990 . . . HV PACKAGE
(TOP VIEW)
9
8
7
6
5
4
3
2
1 68 67 66 65 64 63 62 61
60
NC
DATA0
DATA1
NC
NC
10
TMS5/EVENT3
TMS4/EVENT2
NC
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
DATA2
DATA3
NC
TMS3/EVENT1
TMS2/EVENT0
NC
DATA4
GND
V
CC
GND
TMS1
NC
V
CC
NC
DATA5
DATA6
NC
TMS0
TDO
NC
DATA7
DATA8
NC
TCKO
TCKI
NC
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
NC – No internal connection
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ACT8990, SN74ACT8990
TEST-BUS CONTROLLERS
IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 16-BIT GENERIC HOST INTERFACES
SCAS190E – JUNE 1990 – REVISED JANUARY 1997
SN74ACT8990 . . . FN PACKAGE
(TOP VIEW)
6
5
4
3
2 1 44 43 42 41 40
7
DATA0
DATA1
DATA2
DATA3
DATA4
GND
39 TMS5/EVENT3
38 TMS4/EVENT2
8
9
37
TMS3/EVENT1
TMS2/EVENT0
10
11
12
13
14
15
16
17
36
35
34
33
32
31
30
29
V
CC
GND
V
TMS1
TMS0
TDO
TCKO
TCKI
CC
DATA5
DATA6
DATA7
DATA8
18 19 20 21 22 23 24 25 26 27 28
SN54ACT8990 . . . GB PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
G
H
J
K
L
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ACT8990, SN74ACT8990
TEST-BUS CONTROLLERS
IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 16-BIT GENERIC HOST INTERFACES
SCAS190E – JUNE 1990 – REVISED JANUARY 1997
Table 1. Terminal Assignments
TERMINAL
NAME
TERMINAL
NAME
TERMINAL
NAME
TERMINAL
NAME
NC
NO.
A2
A3
A4
A5
A6
A7
A8
A9
A10
B1
B2
B3
B4
B5
B6
B7
B8
B9
NO.
B10
B11
C1
NO.
F11
G1
G2
G10
G11
H1
NO.
K6
K7
K8
K9
K10
K11
L2
NC
ADRS4
NC
NC
NC
NC
DATA5
NC
V
CC
DATA2
DATA15
ADRS1
ADRS0
NC
C2
DATA1
NC
TDI0
NC
C3
NC
TMS1
NC
C10
C11
D1
TMS4/EVENT2
TMS5/EVENT3
DATA4
TCKI
DATA9
NC
INT
H2
DATA6
TDO
RD
H10
H11
J1
L3
TRST
DATA0
NC
D2
DATA3
TMS0
DATA8
DATA7
TCKO
NC
L4
DATA12
DATA13
NC
D10
D11
E1
TMS3/EVENT1
NC
L5
J2
L6
ADRS3
ADRS2
NC
NC
J10
J11
K1
L7
DATA14
TOFF
TDI1
E2
GND
L8
E10
E11
F1
V
NC
L9
CC
TMS2/EVENT0
NC
K2
NC
L10
NC
GND
RDY
WR
V
CC
K3
DATA10
DATA11
NC
F2
NC
K4
F10
GND
K5
NC – No internal connection
functional block diagram
Target
Host
Interface
Interface
Read Data Bus
Write Data Bus
16
16
16
5
†
DATA(15–0)
ADRS(4–0)
RD
TMS(5–2)/
EVENT(3–0)
4
Counter Block
†
Event
Block
WR
RDY
INT
Host
Block
Command Block
Serial Block
2
2
TMS(1–0)
†
Sequencer
Block
TDI(1–0)
TDO
†
TOFF
TCKO
TCKI
†
TRST
Inputs have internal pullup resistors.
†
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ACT8990, SN74ACT8990
TEST-BUS CONTROLLERS
IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 16-BIT GENERIC HOST INTERFACES
SCAS190E – JUNE 1990 – REVISED JANUARY 1997
Terminal Functions
TERMINAL NAME
I/O
DESCRIPTION
Address inputs. ADRS4– ADRS0 form the 5-bit address bus that interfaces the TBC to its host. These inputs
specify the TBC register to be read from or written to.
ADRS4– ADRS0
I
Data inputs and outputs. DATA15–DATA0 form the 16-bit bidirectional data bus that interfaces the TBC to its
host. Data is read from or written to the TBC register using this data bus.
DATA15–DATA0
I/O
O
GND
INT
NC
Ground
Interrupt. INT transmits an interrupt signal to the host. When the TBC requires service from the host, INT is
asserted (low). INT will remain asserted (low) until the host has completed the required service.
No connection
Read strobe. RD is the active low output enable for the data bus. RD is used as the strobe for reading data from
the selected TBC register.
RD
I
Ready. RDY transmits a status signal to the host. When the TBC is ready to accept a read or write operation
from the host, RDY is asserted (low). RDY is not asserted (high) when the TBC is in recovery from a read, write,
command, or reset operation.
RDY
TCKI
TCKO
O
Test clock input. TCKI is the clock input for the TBC. Most operations of the TBC are synchronous to TCKI.
When enabled, all target interface outputs change on the falling edge of TCKI. Sampling of target interface
inputs are configured to occur on either the rising edge or falling edge of TCKI.
I
Testclockoutput. TCKOdistributesTCKtothetarget(s). TheTCKOisconfiguredtobedisabled, constantzero,
constant one, or to follow TCKI. When TCKO follows TCKI, it is delayed to match the delay of generating the
TDO and TMS signals.
O
Test data inputs. The TDI1–TDI0 serial inputs are used for shifting test data from the target(s). The TDI inputs
can be directly connected to the TDO pin(s) of the target(s).
TDI1–TDI0
TDO
I
Test data output. TDO is used for shifting test data into the target(s). TDO can be directly connected to the TDI
terminal(s) of the target(s).
O
Test mode select outputs. These parallel outputs transmit TMS signals to the target(s), which direct them
through their TAP controller states. TMS1–TMS0 can be directly connected to the TMS terminals of the
target(s).
TMS1–TMS0
O
Test mode select outputs or event inputs/outputs. These I/Os can be configured for use as either TMS outputs
or event inputs/outputs. As TMS outputs, they function similarly to TMS1–TMS0 above. As event I/Os, they
can be used to receive/transmit interrupt signals to/from the target(s).
TMS5–TMS2/
EVENT3–EVENT0
I/O
Test-off input. TOFF is the active low output disable for all outputs and I/Os of the target interface (TCKO, TDO,
TMS, TMS/EVENT).
TOFF
TRST
WR
I
I
I
Test-reset input. TRST is used to initiate hardware and software reset operations of the TBC. Hardware reset
begins when TRST is asserted (low). Software reset begins when TRST is released (high) and proceeds
synchronously to TCKI to completion in a predetermined number of cycles.
Write input. WR is the strobe for writing data to a TBC data register. Signals present at the data and address
buses are captured on the rising edge of WR.
V
CC
Supply voltage
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ACT8990, SN74ACT8990
TEST-BUS CONTROLLERS
IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 16-BIT GENERIC HOST INTERFACES
SCAS190E – JUNE 1990 – REVISED JANUARY 1997
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
I
CC
CC
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Maximum power dissipation at T = 55°C (in still air) (see Note 2): FN package . . . . . . . . . . . . . . . . . . . 1.5W
Storage temperature range, T
O
O
CC
A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 75 mils.
Formoreinformation, refertothePackageThermalConsiderationsapplicationnoteintheABTAdvancedBiCMOSTechnologyData
Book, literature number SCBD002.
recommended operating conditions
SN54ACT8990
SN74ACT8990
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
V
V
V
V
Supply voltage
5.5
5.5
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
Input voltage
0.8
0.8
V
0
0
V
V
0
0
V
V
V
I
CC
CC
Output voltage
V
O
CC
–8
CC
–8
I
I
High-level output current
Low-level output current
Operating free-air temperature
mA
mA
°C
OH
8
8
OL
T
A
–55
125
0
70
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ACT8990, SN74ACT8990
TEST-BUS CONTROLLERS
IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 16-BIT GENERIC HOST INTERFACES
SCAS190E – JUNE 1990 – REVISED JANUARY 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54ACT8990
SN74ACT8990
A
PARAMETER
TEST CONDITIONS
UNIT
†
MIN TYP
MAX
MIN
4.4
3.7
5.4
4.7
MAX
MIN
4.4
3.7
5.4
4.7
MAX
I
I
I
I
I
I
= –20 µA
= –8 mA
= –20 µA
= –8 mA
= 20 µA
4.4
3.7
5.4
4.7
OH
OH
OH
OH
OL
OL
V
= 4.5 V
CC
V
V
V
OH
V
V
= 5.5 V
= 4.5 V
CC
0.1
0.5
0.1
0.5
0.1
0.5
CC
V
OL
to 5.5 V
= 8 mA
ADRS, RD,
WR, TCKI
V
V
V
= 5.5 V,
= 5.5 V
= 5.5 V,
V = V
or GND
±1
±1
±1
CC
CC
CC
I
CC
CC
I
µA
I
V = V
I
±1
±1
±1
TDI, TOFF,
TRST
V = GND
I
–35
–35
–70
–250
–35
–35
–250
–35
–35
–250
INT, RDY, TCKO,
TDO, TMS
V
O
= V
or GND
±10
±10
±10
CC
CC
‡
µA
I
OZ
CC
V
V
= V
±10
±10
±10
DATA,
TMS/EVENT
O
V
V
= 5.5 V
= 5.5 V,
CC
= GND
–70
100
–250
–250
–250
O
CC
V = V
or GND
450*
450
450
µA
I
CC
= 50 pF
L
I
O
= 0,
I
V
CC
= 5.5 V,
C
mA
f
= 30 MHz
clock
*
C
C
C
V = V
or GND
or GND
or GND
5
pF
pF
pF
i
I
CC
CC
CC
9*
8*
V = V
I
io
o
V = V
I
* On products compliant to MIL-PRF-38535, this parameter does not apply.
†
‡
Typical values are at V
For I/O ports, the parameter I
OZ
= 5 V.
CC
includes the input leakage.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ACT8990, SN74ACT8990
TEST-BUS CONTROLLERS
IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 16-BIT GENERIC HOST INTERFACES
SCAS190E – JUNE 1990 – REVISED JANUARY 1997
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Figure 1)
SN54ACT8990
SN74ACT8990
UNIT
MIN
MAX
MIN
0
MAX
f
Clock frequency
Pulse duration
0
30
30
MHz
ns
clock
w
†
RD low
5.5
5.5
8
WR low
5.5
8
t
EVENT high or low
TCKI high or low
TRST low
ns
ns
10.5
6
10.5
6
†
ADRS before RD↑
6.5
6.5
6
ADRS before WR↑
DATA before WR↑
EVENT before TCKI↑
EVENT before TCKI↓
TDI before TCKI↑
TDI before TCKI↓
6.5
6
t
su
Setup time
6
5.5
5
ns
ns
ns
5
2
2
2
2
†
ADRS after RD↑
5
ADRS after WR↑
DATA after WR↑
EVENT after TCKI↑
EVENT after TCKI↓
TDI after TCKI↑
5.5
5.5
5.5
5
5
5.5
5
t
h
Hold time
5
4
2.5
2.5
TDI after TCKI↓
4
†
Applies only in the case where ADRS (4-0) = 10110 (read buffer).
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ACT8990, SN74ACT8990
TEST-BUS CONTROLLERS
IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 16-BIT GENERIC HOST INTERFACES
SCAS190E – JUNE 1990 – REVISED JANUARY 1997
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Figure 1)
SN54ACT8990
SN74ACT8990
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MHz
ns
MIN
30
MAX
MIN
30
MAX
f
t
t
max
PLH
PHL
8
43
43
17
16
16
15
15
17
19
17
19
20
19
19
19
20
21
28
19
19
23
20
22
20
23
20
21
20
16
14
15
14
16.2
16.7
19.5
19.5
5.3
2.5
3.7
5.5
4.4
3.3
2.3
3.6
2.9
5.2
3.1
5.1
1.5
3.5
3.8
6.8
4.9
3.6
4.1
4.8
4.3
5
39.3
39.3
13.8
13
ADRS
DATA
8
RD↑
5.3
2.5
3.7
5.5
4.4
3.3
2.3
3.6
2.9
5.2
3.1
5.1
1.5
3.5
3.8
6.8
4.9
3.6
4.1
4.8
4.3
5
t
ns
ns
RDY
INT
PLH
WR↑
t
t
t
t
t
t
t
t
t
t
t
t
t
t
12.9
13.1
13.4
14.1
15.9
15.6
17.5
17.9
17.5
18.2
17.5
18.9
17.6
22.6
15.3
15.3
19.2
17.4
19.5
17.7
19.9
18.5
18.8
18.7
12.2
10.3
12.2
10.8
14.7
13.6
PLH
PHL
PHL
PLH
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
TCKI↑
TCKI↑
TCKI↑
RDY
ns
ns
TCKO
TCKI↓
TCKI↓
TCKI↓
TCKI↓
RD↓
TCKO
TDO
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TMS
TMS/EVENT
DATA
INT
t
TCKI↑
TCKI↓
PZH
RDY
t
t
t
t
t
t
t
t
t
t
t
t
t
t
PZH
PZL
PZH
PZL
PZH
PZL
PZH
PZL
PZH
PZL
PZH
PZL
PZH
PZL
TCKO
TDO
TCKI↓
TCKI↓
TCKI↓
4.6
5.1
2
4.6
5.1
2
TMS
TMS/EVENT
TCKO
TDO
3.2
4.6
3.1
4.4
3.5
3.1
1.9
3.2
4.6
3.1
4.4
3.5
3.1
1.9
TOFF↑
TOFF↑
TOFF↑
TMS
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ACT8990, SN74ACT8990
TEST-BUS CONTROLLERS
IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 16-BIT GENERIC HOST INTERFACES
SCAS190E – JUNE 1990 – REVISED JANUARY 1997
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (continued) (see Figure 1)
SN54ACT8990
SN74ACT8990
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MIN
2.3
2.7
3.8
4.1
6.7
4.8
5.1
5
MAX
15.3
16.4
18.4
17.1
20.4
21.1
21.7
20.7
22.4
20.6
22.5
20.5
15.6
15.5
16.6
15.4
19.1
17
MIN
2.3
2.7
3.8
4.1
6.7
4.8
5.1
5
MAX
13.8
13.9
15.4
14.8
19.8
20.4
21.3
20.3
21.9
20.1
22.1
20.1
15.4
15.3
16.5
15.4
17.1
15.8
17.3
16.2
20.8
20
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
PZH
PZL
PHZ
PLZ
PHZ
PLZ
PHZ
PLZ
PHZ
PLZ
PHZ
PLZ
PHZ
PLZ
PHZ
PLZ
PHZ
PLZ
PHZ
PLZ
PHZ
PLZ
PHZ
PLZ
PHZ
PLZ
PHZ
PLZ
TMS/EVENT
DATA
TOFF↑
RD↑
TCKI↓
TCKI↓
TCKI↓
TCKI↓
TCKO
TDO
6.9
4.6
4.7
2.8
5
6.9
4.6
4.7
2.8
5
TMS
TMS/EVENT
TCKO
TOFF↓
TOFF↓
TOFF↓
TOFF↓
TRST↓
TRST↓
TRST↓
TRST↓
4.4
5.6
4.6
4.8
4.4
4.5
2.4
5.7
4.2
6
4.4
5.6
4.6
4.8
4.4
4.5
2.4
5.7
4.2
8
TDO
TMS
18.8
17.1
23
TMS/EVENT
DATA
20.3
19.6
18
19.5
17.8
18.7
17.8
21.1
19.9
INT
RDY
6.1
6.5
4.8
6
6.1
6.5
4.8
6
18.8
17.8
21.1
20
TMS/EVENT
4.2
4.2
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ACT8990, SN74ACT8990
TEST-BUS CONTROLLERS
IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 16-BIT GENERIC HOST INTERFACES
SCAS190E – JUNE 1990 – REVISED JANUARY 1997
PARAMETER MEASUREMENT INFORMATION
V
CC
Open
GND
TEST
S1
S1
1 kΩ
t
t
/t
Open
PLH PHL
From Output
Under Test
t
/t
V
GND
PLZ PZL
CC
/t
PHZ PZH
C
= 50 pF
L
(see Note A)
t
w
LOAD CIRCUIT
3 V
0 V
Input
1.5 V
1.5 V
3 V
Timing Input
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
0 V
t
t
h
su
3 V
0 V
1.5 V
1.5 V
3 V
0 V
Data Input
Output
Control
(high-level
enabling)
1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
PZL
t
PLZ
≈ V
3 V
0 V
CC
Output
Waveform 1
Input
t
1.5 V
1.5 V
50% V
t
CC
10% V
CC
CC
S1 at V
(see Note B)
CC
V
OL
OH
PLH
PHZ
t
PHL
t
PZH
Output
Waveform 2
S1 at GND
V
V
OH
90% V
50% V
50% V
Output
CC
CC
V
50% V
CC
(see Note B)
OL
≈ 0 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
For testing pulse duration: t = t = 1 to 3 ns. Pulse polarity can be either high-to-low-to-high or low-to-high-to-low.
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
5962-9322801MXA
5962-9322801MYA
SN74ACT8990FN
SN74ACT8990FNR
SNJ54ACT8990GB
SNJ54ACT8990HV
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
CFP
HV
68
68
44
44
68
68
1
1
TBD
TBD
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
Level-3-220C-168 HR
Level-3-220C-168 HR
Level-NC-NC-NC
Level-NC-NC-NC
CPGA
PLCC
PLCC
CPGA
CFP
GB
FN
26
500
1
FN
GB
HV
1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPLC004A – OCTOBER 1994
FN (S-PQCC-J**)
PLASTIC J-LEADED CHIP CARRIER
20 PIN SHOWN
Seating Plane
0.004 (0,10)
0.180 (4,57) MAX
0.120 (3,05)
D
0.090 (2,29)
D1
0.020 (0,51) MIN
3
1
19
0.032 (0,81)
0.026 (0,66)
4
18
D2/E2
D2/E2
E
E1
8
14
0.021 (0,53)
0.013 (0,33)
0.050 (1,27)
9
13
0.007 (0,18)
M
0.008 (0,20) NOM
D/E
D1/E1
D2/E2
NO. OF
PINS
**
MIN
0.385 (9,78)
MAX
MIN
MAX
MIN
MAX
0.395 (10,03)
0.350 (8,89)
0.356 (9,04)
0.141 (3,58)
0.191 (4,85)
0.291 (7,39)
0.341 (8,66)
0.169 (4,29)
0.219 (5,56)
0.319 (8,10)
0.369 (9,37)
20
28
44
52
68
84
0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58)
0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66)
0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20)
0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91)
1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45)
4040005/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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