SN54AHC04_08 [TI]
HEX INVERTERS; 六路反向器
| 型号： | SN54AHC04_08 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HEX INVERTERS |
| 文件： | 总13页 (文件大小：277K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LVCZ161284A
19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER
WITH ERROR-FREE POWER UP
www.ti.com
SCES358B–SEPTEMBER 2001–REVISED MAY 2005
FEATURES
DGG PACKAGE
(TOP VIEW)
•
Power-On Reset (POR) Prevents Printer
Errors When Printer Is Turned On, But No
Valid Signal Is at Pins A9–A13
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
HD
A9
DIR
Y9
2
•
•
Operates From 3 V to 3.6 V
3
A10
A11
A12
A13
Y10
Y11
Y12
Y13
1.4-kΩ Pullup Resistors Integrated on All
Open-Drain Outputs Eliminate the Need for
Discrete Resistors
4
5
6
•
Designed for IEEE Std 1284-I (Level-1 Type)
and IEEE Std 1284-II (Level-2 Type) Electrical
Specifications
7
V
V
CABLE
CC
CC
8
A1
A2
B1
B2
9
•
•
•
•
Flow-Through Architecture Optimizes PCB
Layout
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
GND
A3
A4
GND
B3
B4
Ioff and Power-Up 3-State Support Hot
Insertion
A5
B5
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
A6
GND
A7
B6
GND
B7
B8
V
ESD Protection Exceeds JESD 22
– 4000-V Human-Body Model (A114-A)
– 350-V Machine Model (A115-A)
A8
V
CABLE
CC
CC
PERI LOGIC IN
PERI LOGIC OUT
C14
C15
C16
– 1500-V Charged-Device Model (C101)
A14
A15
A16
A17
DESCRIPTION/ORDERING INFORMATION
C17
The SN74LVCZ161284A is designed for 3-V to 3.6-V
VCC operation. This device provides asynchronous
two-way communication between data buses. The
control-function implementation minimizes external
timing requirements.
HOST LOGIC OUT
HOST LOGIC IN
This device has eight bidirectional bits; data can flow in the A-to-B direction when the direction-control (DIR) input
is high and in the B-to-A direction when DIR is low. This device also has five drivers that drive the cable side and
four receivers. The SN74LVCZ161284A has one receiver dedicated to the HOST LOGIC line and a driver to
drive the PERI LOGIC line.
The output drive mode is determined by the high-drive (HD) control pin. When HD is high, the outputs are in a
totem-pole configuration and in an open-drain configuration when HD is low. This meets the drive requirements
as specified in the IEEE Std 1284-I (level-1 type) and IEEE Std 1284-II (level-2 type) parallel peripheral-interface
specifications. Except for HOST LOGIC IN and peripheral logic out (PERI LOGIC OUT), all cable-side pins have
a 1.4-kΩ integrated pullup resistor. The pullup resistor is switched off if the associated output driver is in the low
state or if the output voltage is above VCC CABLE. If VCC CABLE is off, PERI LOGIC OUT is set to low.
The device has two supply voltages. VCC is designed for 3-V to 3.6-V operation. VCC CABLE supplies the inputs
and output buffers of the cable side only and is designed for 3-V to 3.6-V and for 4.7-V to 5.5-V operation. Even
when VCC CABLE is 3 V to 3.6 V, the cable-side I/O pins are 5-V tolerant.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
LVCZ161284A
0°C to 70°C
TSSOP – DGG
Tape and reel
SN74LVCZ161284AGR
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2001–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74LVCZ161284A
19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER
WITH ERROR-FREE POWER UP
www.ti.com
SCES358B–SEPTEMBER 2001–REVISED MAY 2005
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
The power-on reset (POR) ensures that the Y outputs (Y9–Y13) stay in the high state after power on until an
associated input (A9–A13) goes high. When an associated input goes high, all Y outputs are activated, and
noninverting signals of the associated inputs are driven through Y outputs. This special feature prevents printer
system errors caused by deasserting the BUSY signal in the cable at power on.
FUNCTION TABLE
INPUTS
OUTPUT
MODE
DIR
HD
Open drain
Totem pole
Totem pole
Open drain
Totem pole
Totem pole
A9–A13 to Y9–Y13 and PERI LOGIC IN to PERI LOGIC OUT
L
L
B1–B8 to A1–A8 and C14–C17 to A14–A17
L
H
B1–B8 to A1–A8, A9–A13 to Y9–Y13, PERI LOGIC IN to PERI LOGIC OUT, and C14–C17 to A14–A17
A1–A8 to B1–B8, A9–A13 to Y9–Y13, and PERI LOGIC IN to PERI LOGIC OUT
C14–C17 to A14–A17
H
L
H
H
A1–A8 to B1–B8, A9–A13 to Y9–Y13, C14–C17 to A14–A17, and PERI LOGIC IN to PERI LOGIC OUT
2
SN74LVCZ161284A
19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER
WITH ERROR-FREE POWER UP
www.ti.com
SCES358B–SEPTEMBER 2001–REVISED MAY 2005
LOGIC DIAGRAM
42
48
V
CC
CABLE
DIR
See Note A
See Note A
1
HD
See Note B
B1–B8
A1–A8
A9–A13
Y9–Y13
See
Note C
19
24
30
25
PERI LOGIC IN
PERI LOGIC OUT
A14–A17
C14–C17
HOST LOGIC OUT
HOST LOGIC IN
NOTES: A. The PMOS transistors prevent backdriving current from the signal pins to V CABLE when V CABLE is open or at GND. The
CC
CC
PMOS transistor is turned off when the associated driver is in the low state.
B. The PMOS transistor prevents backdriving current from the signal pins to V CABLE when V CABLE is open or at GND.
CC
CC
C. Active input detection circuit forces Y9–Y13 to the high state after power on, until one of the A9–A13 pins goes high (see below).
D
C
Q
OUT
A9
A10
A11
A12
A13
Timer
R
Power-On
Reset
Active Input Detection Circuit
3
SN74LVCZ161284A
19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER
WITH ERROR-FREE POWER UP
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SCES358B–SEPTEMBER 2001–REVISED MAY 2005
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–2
MAX
UNIT
V
VCC CABLE
VCC
Supply voltage range
Supply voltage range
7
4.6
7
V
Cable side(2)(3)
Peripheral side(2)
VI < 0
VI
VO
Input and output voltage range
V
–0.5 VCC + 0.5
IIK
Input clamp current
Output clamp current
–20
–50
±50
±100
±200
65
mA
mA
IOK
VO < 0
Except PERI LOGIC OUT
PERI LOGIC OUT
IO
Continuous output current
mA
Continuous current through each VCC or GND
Output high sink current
mA
mA
ISK
VO = 5.5 V and VCC CABLE = 3 V
θJA
Tstg
Package thermal impedance(4)
70
°C/W
°C
Storage temperature range
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The ac input voltage pulse duration is limited to 40 ns if the amplitude is greater than –0.5 V.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions(1)
MIN
3
MAX UNIT
VCC CABLE
VCC
Supply voltage for the cable side, VCC CABLE ≥ VCC
5.5
3.6
V
V
Supply voltage
3
A, B, DIR, and HD
C14–C17
2
2.3
2.6
2
VIH
High-level input voltage
Low-level input voltage
V
V
HOST LOGIC IN
PERI LOGIC IN
A, B, DIR, and HD
C14–C17
0.8
0.8
1.6
0.8
VCC
5.5
5.5
–14
–4
VIL
HOST LOGIC IN
PERI LOGIC IN
Peripheral side
0
0
0
VI
Input voltage
V
V
Cable side
VO
Open-drain output voltage
HD low
HD high, B and Y outputs
A outputs and HOST LOGIC OUT
PERI LOGIC OUT
B and Y outputs
A outputs and HOST LOGIC OUT
PERI LOGIC OUT
IOH
High-level output current
mA
–0.5
14
IOL
Low-level output current
4
mA
°C
84
TA
Operating free-air temperature
0
70
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
SN74LVCZ161284A
19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER
WITH ERROR-FREE POWER UP
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SCES358B–SEPTEMBER 2001–REVISED MAY 2005
Electrical Characteristics
over recommended operating free-air temperature range, VCC CABLE = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN TYP(1)
MAX UNIT
All inputs except
C inputs and HOST LOGIC IN
0.4
∆Vt
Hysteresis
3.3 V
V
HOST LOGIC IN
C inputs
0.2
0.8
(VT+ – VT–
)
3 V
3.3 V(2)
2.23
2.4
HD high, B and Y outputs
IOH = –14 mA
IOH = –4 mA
2.4
HD high, A outputs, and
HOST LOGIC OUT
VOH
3 V
V
IOH = –50 µA
2.8
3.15 V
3.3 V(2)
3.1
PERI LOGIC OUT
B and Y outputs
IOH = –0.5 mA
4.5
IOL = 14 mA
0.77
IOL = 50 µA
0.2
V
VOL
A outputs and HOST LOGIC OUT
PERI LOGIC OUT
C inputs
3 V
IOL = 4 mA
0 4
IOL = 84 mA
0.9
VI = VCC
50
–3.5
±1
µA
mA
µA
3.6 V(3)
II
VI = GND (pullup resistors)
VI = VCC or GND
VO = VCC or GND
VO = VCC CABLE
VO = GND (pullup resistors)
VO = GND (pullup resistors)
VO = 5.5 V
All inputs except B or C inputs
A1–A8
3.6 V
3.6 V
±20
50
µA
3.6 V
µA
IOZ
B outputs
3.6 V(3)
3.6 V(3)
–3.5
–3.5
350
–5
mA
mA
µA
Open-drain Y outputs
B and Y outputs
IOZPU
0 to 1.5 V(4)
0 to 1.5 V(4)
VO = GND
mA
µA
VO = 5.5 V
350
–5
IOZPD
B and Y outputs
VO = GND
mA
Power-down input leakage,
except A1–A8 or B1–B8 inputs
VI or VO = 0 to 3.6 V
VI or VO = 0 to 5.5 V
100
100
Ioff
0(3)
µA
Power-down output leakage,
B1–B8 and Y9–Y13 outputs
3.6 V(5)
3.6 V
3.6 V
3.3 V
3.3 V
3.3 V
3.3 V
45
70
VI = GND (12 × pullup)
ICC
mA
VI = VCC
,
IO = 0
0.8
Ci
All inputs
I/O ports
VI = VCC or GND
VO = VCC or GND
IOH = –35 mA
3
pF
pF
Ω
Cio
7
ZO
Cable side
Cable side
45
R pullup
VO = 0 V (in high-impedance state)
1.15
1.65
kΩ
(1) Typical values are measured at VCC = 3.3 V, VCC CABLE = 5 V, and TA = 25°C.
(2) VCC CABLE = 4.7 V
(3) VCC CABLE = 3.6 V
(4) Connect the VCC pin and the VCC CABLE pin.
(5) VCC CABLE = 4.7 V
5
SN74LVCZ161284A
19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER
WITH ERROR-FREE POWER UP
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SCES358B–SEPTEMBER 2001–REVISED MAY 2005
Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 2 and
Figure 3)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
Totem pole
MIN TYP(1) MAX UNIT
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tslew
tPZH
tPHZ
ten–tdis
tPHZ
tPLZ
tr, tf
1
1
22
22
20
20
10
10
11
11
13
13
13
13
0.4
20
15
15
15
15
120
10
A1–A8
A9–A13
B1–B8
Y9–Y13
ns
ns
ns
ns
ns
1
Totem pole
Totem pole
Totem pole
Totem pole
1
1
B1–B8
A1–A8
1
1
C14–C17
A14–A17
1
1
PERI LOGIC IN
HOST LOGIC IN
PERI LOGIC OUT
HOST LOGIC OUT
1
1
Totem pole
Totem pole
ns
V/ns
ns
1
B1–B8 and Y9–Y13 outputs
0.05
1
B1–B8, Y9–Y13, and
PERI LOGIC OUT
HD
DIR
DIR
1
A1–A8
B1–B8
1
ns
1
ns
1
Open drain
A1–A13
B1–B8 or Y9–Y13
B1–B8 or A1–A8
1
ns
ns
(2)
tsk(o)
A1–A8 or B1–B8
2.5
(1) Typical values are measured at VCC = 3.3 V, VCC CABLE = 5 V, and TA = 25°C.
(2) Skew is measured at 1/2 (VOH + VOL) for signals switching in the same direction.
Operating Characteristics
VCC = 3.3 V, TA = 25°C
PARAMETER
TEST CONDITIONS
TYP UNIT
45 pF
Cpd
Power dissipation capacitance
Outputs enabled
CL = 0,
f = 10 MHz
V
CC
V
CC
= 3.3 V
CABLE = 5 V
V
CC
and V CABLE
CC
T
A
= 25°C
TYP = 80 ns
A
n
(one of A9–A13)
50% V
CC
Initial Activation Time
Y9–Y13, Other Than Y
50% V CABLE
CC
n
One of pins A9–A13 is switched as shown above, and the other four inputs are forced at low state.
Figure 1. Error-Free Circuit Timing
6
SN74LVCZ161284A
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WITH ERROR-FREE POWER UP
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SCES358B–SEPTEMBER 2001–REVISED MAY 2005
PARAMETER MEASUREMENT INFORMATION
V
CC
CABLE
2.7 V
0 V
Input
(see Note B)
C
= 50 pF
L
62 Ω
(see Note A)
t
t
f1
TP1
Sink Load
From
B or Y Output
Under Test
95% (V CABLE = 5 V"0.5 V)
CC
Output
(see Note B)
50% (V CABLE = 5 V"0.5 V)
CC
Source Load
r1
Output
(see Note B)
1.9 V (V CABLE = 5 V"0.5 V)
0.4 V
CC
C
= 50 pF
L
62 Ω
(see Note A)
VOLTAGE WAVEFORMS MEASURED AT TP1
SLEW RATE WAVEFORMS (B8−B1 AND Y13−Y9)
SLEW RATE A-TO-B OR A-TO-Y LOAD (TOTEM POLE)
V
CC
CABLE
2.7 V
0 V
Input
1.4 V
1.4 V
(see Note C)
TP1
500 Ω
V
OH
OL
2 V
0.8 V
2 V
0.8 V
Output
(see Note C)
From
B or Y Output
V
C
L
= 50 pF
(see Note A)
t
r
t
f
VOLTAGE WAVEFORMS MEASURED AT TP1, B SIDE
A-TO-B LOAD OR A-TO-Y LOAD (OPEN DRAIN)
NOTES: A. C includes probe and jig capacitance.
L
B. When V CABLE is 3.3 V " 0.3 V, slew rate is measured between 0.4 V and 0.9 V for the rising edge and between 2.4 V and
CC
1.9 V for the falling edge. When V CABLE is 5 V " 0.5 V, slew rate is measured between 0.4 V and 1.9 V for the rising edge and
CC
between 95% V CABLE and 50% V CABLE for the falling edge.
CC
CC
95% * 50%
1.9 V – 0.4 V
tr1
ǒ
Ǔ
rise + ǒ
Ǔ
tslew fall + VCC
tslew
tf1
C. Input rise (t ) and fall (t ) times are 3 ns. Rise and fall times (open drain) are <120 ns.
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
Figure 2. Load Circuits and Voltage Waveforms
7
SN74LVCZ161284A
19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER
WITH ERROR-FREE POWER UP
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SCES358B–SEPTEMBER 2001–REVISED MAY 2005
PARAMETER MEASUREMENT INFORMATION
V
CC
× 2 V
When Measuring the Cable Side, V CABLE × 2 V
CC
S1
Open
500 Ω
TEST
S1
Open
× 2 V
From Output
Under Test
t
/t
GND
PLH PHL
t
t
/t
V
PLZ PZL
CC
C = 50 pF
L
/t
GND
500 Ω
PHZ PZH
(see Note A)
2.7 V
0 V
LOAD CIRCUIT
Output
Control
1.4 V
1.4 V
t
t
PLZ
PZL
2.7 V
0 V
Input
(see Note B)
Output
Waveform 1
V
V
OH
1.4 V
1.4 V
1.4 V
V
V
+ 0.3 V
OL
S1 at V × 2 V
CC
OL
(see Note C)
t
t
PHL
PLH
t
t
PZH
PHZ
Output
Waveform 2
S1 at GND
V
V
OH
V
OH
− 0.3 V
OH
50% V
50% V
1.4 V
Output
CC
CC
0 V
OL
(see Note C)
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
PROPAGATION DELAY TIMES (B to A)
B-TO-A LOAD (TOTEM POLE)
V
CC
CABLE
C
= 50 pF
L
t
w
500 Ω
(see Note A)
2.7 V
0 V
Input
(see Note D)
1.4 V
1.4 V
TP1
Sink Load
From
B or Y Output
Under Test
t
PHL
t
t
PHL
PLH
t
PLH
V
OH
Source Load
Output
V
OL
+ 1.4 V
V
OH
− 1.4 V
C
= 50 pF
L
V
OL
500 Ω
(see Note A)
VOLTAGE WAVEFORMS MEASURED AT TP1
PROPAGATION DELAY TIMES (A to B)
A-TO-B LOAD OR A-TO-Y LOAD (TOTEM POLE)
NOTES: A. C includes probe and jig capacitance.
L
B. Input rise and fall times are 3 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
D. Input rise and fall times are 3 ns. Pulse duration is 150 ns < t < 10 µs.
w
E. The outputs are measured one at a time, with one transition per measurement.
F.
G.
H.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
PZH
are the same as t
en
are the same as t .
pd
PHL
Figure 3. Load Circuits and Voltage Waveforms
8
PACKAGE OPTION ADDENDUM
www.ti.com
27-Sep-2007
PACKAGING INFORMATION
Orderable Device
74LVCZ161284AGRG4
SN74LVCZ161284AGR
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
DGG
48
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
DGG
48
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Jan-2008
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
(mm)
SN74LVCZ161284AGR
DGG
48
SITE 41
330
24
8.6
15.8
1.8
12
24
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Jan-2008
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
SN74LVCZ161284AGR
DGG
48
SITE 41
346.0
346.0
41.0
Pack Materials-Page 2
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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