SN54AHC595FK [TI]
8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS; 8位移位寄存器具有三态输出寄存器
| 型号： | SN54AHC595FK |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS |
| 文件： | 总17页 (文件大小：444K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SCLS373I − MAY 1997 − REVISED JUNE 2004
SN54AHC595 . . . J OR W PACKAGE
SN74AHC595 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
D
D
D
D
Operating Range 2-V to 5.5-V V
CC
8-Bit Serial-In, Parallel-Out Shift
Shift Register Has Direct Clear
Q
Q
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
B
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
Q
C
D
A
Q
SER
OE
D
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
Q
E
Q
12 RCLK
F
11
10
9
Q
SRCLK
SRCLR
G
− 1000-V Charged-Device Model (C101)
Q
H
GND
Q
H′
description/ordering information
The ’AHC595 devices contain an 8-bit serial-in,
parallel-out shift register that feeds an 8-bit D-type
storage register. The storage register has parallel
3-state outputs. Separate clocks are provided for
both the shift and storage registers. The shift
register has a direct overriding clear (SRCLR)
input, serial (SER) input, and a serial output for
cascading. When the output-enable (OE) input is
SN54AHC595 . . . FK PACKAGE
(TOP VIEW)
3
2
1 20 19
18
SER
OE
Q
4
5
6
7
8
D
Q
17
16
E
NC
NC
high, all outputs, except Q , are in the
H′
15 RCLK
14
9 10 11 12 13
Q
F
high-impedance state.
SRCLK
Q
G
Both the shift-register clock (SRCLK) and
storage-register clock (RCLK) are positive-edge
triggered. If both clocks are connected together,
the shift register always is one clock pulse ahead
of the storage register.
NC − No internal connection
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP − N
SOIC − D
Tube
SN74AHC595N
SN74AHC595N
Tube
SN74AHC595D
AHC595
Tape and reel
Tape and reel
Tape and reel
Tube
SN74AHC595DR
SN74AHC595NSR
SN74AHC595DBR
SN74AHC595PW
SN74AHC595PWR
SNJ54AHC959J
SNJ54AHC595W
SNJ54AHC595FK
−40°C to 85°C
SOP − NS
AHC595
HA595
SSOP − DB
TSSOP − PW
HA595
Tape and reel
Tube
CDIP − J
CFP − W
LCCC − FK
SNJ54AHC595J
SNJ54AHC595W
SNJ54AHC595FK
Tube
−55°C to 125°C
Tube
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2004, Texas Instruments Incorporated
ꢖ ꢁ ꢘꢑꢀꢀ ꢕ ꢎꢅ ꢑꢐꢓ ꢍꢀ ꢑ ꢁ ꢕꢎꢑꢙ ꢚꢛ ꢜꢝ ꢞꢟꢠ ꢡꢢꢣ ꢤꢚ ꢠꢟ ꢤꢚꢥ ꢜꢤꢝ ꢗꢐ ꢕ ꢙ ꢖ ꢆꢎ ꢍꢕ ꢁ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢂ ꢇ ꢂꢈ ꢀ ꢁꢉ ꢃ ꢄꢅꢆ ꢂ ꢇꢂ
ꢊꢋ ꢌꢍ ꢎ ꢀꢅ ꢍ ꢏ ꢎ ꢐ ꢑꢒ ꢍꢀ ꢎꢑ ꢐꢀ
ꢓꢍ ꢎ ꢅ ꢔ ꢋꢀꢎꢄꢎ ꢑ ꢕꢖꢎ ꢗꢖ ꢎ ꢐꢑ ꢒ ꢍꢀ ꢎꢑ ꢐꢀ
SCLS373I − MAY 1997 − REVISED JUNE 2004
FUNCTION TABLE
INPUTS
SER SRCLK SRCLR RCLK
FUNCTION
Outputs Q −Q are disabled.
OE
H
X
X
X
X
X
X
X
X
L
X
X
X
A
H
L
Outputs Q −Q are enabled.
A H
X
Shift register is cleared.
First stage of the shift register goes low.
Other stages store the data of previous stage, respectively.
L
↑
H
X
X
First stage of the shift register goes high.
Other stages store the data of previous stage, respectively.
H
X
↑
H
X
X
X
X
X
↑
Shift-register data is stored into the storage register.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCLS373I − MAY 1997 − REVISED JUNE 2004
logic diagram (positive logic)
13
OE
12
RCLK
10
SRCLR
11
SRCLK
14
SER
Q
Q
1D
C1
R
3D
C3
15
Q
Q
Q
A
B
2D
C2
3D
C3
1
2
3
Q
Q
Q
R
2D
C2
R
3D
C3
Q
Q
Q
Q
C
D
2D
C2
3D
C3
R
2D
C2
R
3D
C3
Q
Q
Q
4
5
6
Q
Q
Q
Q
Q
Q
E
F
2D
C2
R
3D
C3
2D
C2
3D
C3
G
R
2D
C2
R
3D
C3
Q
7
9
Q
Q
Q
H
H′
Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages.
3
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ꢊꢋ ꢌꢍ ꢎ ꢀꢅ ꢍ ꢏ ꢎ ꢐ ꢑꢒ ꢍꢀ ꢎꢑ ꢐꢀ
ꢓꢍ ꢎ ꢅ ꢔ ꢋꢀꢎꢄꢎ ꢑ ꢕꢖꢎ ꢗꢖ ꢎ ꢐꢑ ꢒ ꢍꢀ ꢎꢑ ꢐꢀ
SCLS373I − MAY 1997 − REVISED JUNE 2004
timing diagram
SRCLK
SER
RCLK
SRCLR
OE
Q
Q
A
B
Q
Q
C
D
Q
E
Q
F
Q
G
Q
H
Q
H′
NOTE:
implies that the output is in 3-State mode.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCLS373I − MAY 1997 − REVISED JUNE 2004
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
IK
I
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 mA
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
JA
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54AHC595 SN74AHC595
UNIT
MIN
2
MAX
MIN
2
MAX
V
V
Supply voltage
5.5
5.5
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
1.5
2.1
3.85
1.5
2.1
3.85
= 3 V
High-level input voltage
V
V
IH
= 5.5 V
= 2 V
0.5
0.9
0.5
0.9
= 3 V
V
IL
Low-level input voltage
= 5.5 V
1.65
5.5
1.65
5.5
V
V
Input voltage
0
0
0
0
V
V
I
Output voltage
V
V
CC
O
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
−50
−4
−8
50
4
−50
−4
−8
50
4
mA
= 3.3 V 0.3 V
= 5 V 0.5 V
= 2 V
I
High-level output current
Low-level output current
OH
mA
mA
= 3.3 V 0.3 V
= 5 V 0.5 V
= 3.3 V 0.3 V
= 5 V 0.5 V
I
OL
mA
8
8
100
20
125
100
20
85
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
ns/V
T
−55
−40
°C
A
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
CC
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ꢠ ꢛꢥ ꢤ ꢯꢣ ꢟꢧ ꢞꢜ ꢝ ꢠ ꢟꢤ ꢚꢜ ꢤꢡꢣ ꢚ ꢛꢣ ꢝ ꢣ ꢨꢧ ꢟꢞ ꢡꢠꢚ ꢝ ꢭ ꢜꢚꢛ ꢟꢡꢚ ꢤꢟꢚ ꢜꢠꢣ ꢫ
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5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢂ ꢇ ꢂꢈ ꢀ ꢁꢉ ꢃ ꢄꢅꢆ ꢂ ꢇꢂ
ꢊꢋ ꢌꢍ ꢎ ꢀꢅ ꢍ ꢏ ꢎ ꢐ ꢑꢒ ꢍꢀ ꢎꢑ ꢐꢀ
ꢓꢍ ꢎ ꢅ ꢔ ꢋꢀꢎꢄꢎ ꢑ ꢕꢖꢎ ꢗꢖ ꢎ ꢐꢑ ꢒ ꢍꢀ ꢎꢑ ꢐꢀ
SCLS373I − MAY 1997 − REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
TYP
2
SN54AHC595 SN74AHC595
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
1.9
MAX
MIN
1.9
MAX
MIN
1.9
MAX
2 V
3 V
2.9
3
2.9
2.9
I
= −50 mA
OH
4.5 V
3 V
4.4
4.5
4.4
4.4
V
V
V
OH
OL
2.58
2.48
2.48
I
I
= −4 mA
= −8 mA
OH
4.5 V
2 V
3.94
3.8
3.8
OH
0.1
0.1
0.1
0.1
0.1
0.5
0.1
0.1
3 V
I
= 50 mA
OL
4.5 V
3 V
0.1
0.1
V
0.36
0.44
I
I
= 4 mA
= 8 mA
OL
4.5 V
0.36
0.1
0.5
1*
0.44
1
OL
I
I
I
V = 5.5 V or GND
0 V to 5.5 V
mA
mA
I
I
V = V
V
OE = V or V
IH IL
or GND,
CC
= V or GND,
CC
I
O
Q −Q
H
5.5 V
0.25
2.5
40
2.5
OZ
CC
A
V = V
or GND,
or GND
I = 0
O
5.5 V
5 V
4
40
10
mA
pF
pF
I
CC
C
C
V = V
3
10
i
I
CC
V
= V
O CC
or GND
5 V
5.5
o
* On products compliant to MIL-PRF-38535, this parameter is not production tested at V
= 0 V.
CC
timing requirements over recommended operating free-air temperature range,
= 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)
V
CC
T
= 25°C
SN54AHC595 SN74AHC595
A
UNIT
MIN
5
MAX
MIN
5
MAX
MIN
5
MAX
SRCLK high or low
RCLK high or low
SRCLR low
5
5
5
t
w
Pulse duration
ns
5
5
5
SER before SRCLK↑
SRCLK↑ before RCLK↑
3.5
8
3.5
8.5
9
3.5
8.5
9
†
Setup time
Hold time
t
t
ns
ns
su
SRCLR low before RCLK↑
SRCLR high (inactive) before SRCLK↑
SER after SRCLK↑
8
3
3
3
1.5
1.5
1.5
h
†
This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift
register is one clock pulse ahead of the storage register.
ꢗ
ꢐ
ꢕ
ꢙ
ꢖ
ꢆ
ꢎ
ꢗ
ꢐ
ꢑ
ꢰ
ꢍ
ꢑ
ꢓ
ꢜ
ꢤ
ꢦ
ꢟ
ꢧ
ꢢ
ꢥ
ꢚ
ꢜ
ꢟ
ꢤ
ꢠ
ꢟ
ꢤ
ꢠ
ꢣ
ꢧ
ꢤ
ꢝ
ꢨ
ꢧ
ꢟ
ꢞ
ꢡ
ꢠ
ꢞ ꢣ ꢝ ꢜ ꢯ ꢤ ꢨꢛ ꢥ ꢝ ꢣ ꢟꢦ ꢞꢣ ꢱ ꢣ ꢪ ꢟꢨ ꢢꢣ ꢤ ꢚꢫ ꢆ ꢛꢥ ꢧꢥ ꢠꢚ ꢣꢧ ꢜꢝ ꢚꢜ ꢠ ꢞꢥ ꢚꢥ ꢥꢤ ꢞ ꢟꢚ ꢛꢣꢧ
ꢚ
ꢝ
ꢜ
ꢤ
ꢚ
ꢛ
ꢣ
ꢦ
ꢟ
ꢧ
ꢢ
ꢥ
ꢚ
ꢜ
ꢱ
ꢣ
ꢟ
ꢧ
ꢝ
ꢨ
ꢣ
ꢠ
ꢜ
ꢦ
ꢜ
ꢠ
ꢥ
ꢚ
ꢜ
ꢟ
ꢤ
ꢝ
ꢥ
ꢧ
ꢣ
ꢞ
ꢣ
ꢝ
ꢜ
ꢯ
ꢤ
ꢯ
ꢟ
ꢥ
ꢪ
ꢝ
ꢫ
ꢎ
ꢣ
ꢬ
ꢥ
ꢝ
ꢍ
ꢤ
ꢝ
ꢚ
ꢧ
ꢡ
ꢢ
ꢣ
ꢤ
ꢠ ꢛ ꢥ ꢤ ꢯꢣ ꢟꢧ ꢞꢜ ꢝ ꢠ ꢟꢤ ꢚꢜ ꢤꢡ ꢣ ꢚ ꢛꢣ ꢝ ꢣ ꢨꢧ ꢟ ꢞꢡꢠ ꢚꢝ ꢭ ꢜꢚꢛ ꢟꢡꢚ ꢤꢟꢚ ꢜꢠꢣ ꢫ
ꢚ
ꢝ
ꢧ
ꢣ
ꢝ
ꢣ
ꢧ
ꢱ
ꢣ
ꢝ
ꢚ
ꢛ
ꢣ
ꢧ
ꢜ
ꢯ
ꢛ
ꢚ
ꢚ
ꢟ
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢁ
ꢂ
ꢊ
ꢎ
ꢃ
ꢄ
ꢍ
ꢕ
ꢅ
ꢎ
ꢖ
ꢆ
ꢀ
ꢎ
ꢂ
ꢅ
ꢗ
ꢇ
ꢍ
ꢂ
ꢏ
ꢖ
ꢈ
ꢎ
ꢎ
ꢀ
ꢐ
ꢐ
ꢁ
ꢉ
ꢑ
ꢑ
ꢃ
ꢒ
ꢒ
ꢄ
ꢅ
ꢎ
ꢎ
ꢆ
ꢑ
ꢑ
ꢂ
ꢐ
ꢐ
ꢇ
ꢂ
ꢀ
ꢀ
ꢋ
ꢌ
ꢍ
ꢀ
ꢓ
ꢍ
ꢎ
ꢅ
ꢔ
ꢋ
ꢀ
ꢎ
ꢄ
ꢑ
ꢍꢀ
SCLS373I − MAY 1997 − REVISED JUNE 2004
timing requirements over recommended operating free-air temperature range,
V
= 5 V 0.5 V (unless otherwise noted) (see Figure 1)
CC
T
= 25°C
SN54AHC595 SN74AHC595
A
UNIT
MIN
5
MAX
MIN
5
MAX
MIN
5
MAX
SRCLK high or low
RCLK high or low
SRCLR low
5
5
5
t
w
Pulse duration
ns
5
5
5
SER before SRCLK↑
SRCLK↑ before RCLK↑
3
3
3
†
5
5
5
Setup time
Hold time
t
t
ns
ns
su
SRCLR low before RCLK↑
SRCLR high (inactive) before SRCLK↑
SER after SRCLK↑
5
5
5
2.5
2
2.5
2
2.5
2
h
†
This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift
register is one clock pulse ahead of the storage register.
switching characteristics over recommended operating free-air temperature range,
V
= 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
SN54AHC595 SN74AHC595
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MHz
ns
MIN
80*
55
MAX
MIN
70*
50
MAX
MIN
70
50
1
MAX
C
C
= 15 pF
= 50 pF
120*
105
L
L
f
max
t
t
t
t
t
t
t
t
t
t
t
t
6* 11.9*
6* 11.9*
1* 13.5*
1* 13.5*
13.5
13.5
15
PLH
PHL
PLH
PHL
PHL
PZH
PZL
PLH
PHL
PLH
PHL
PHL
C
= 15 pF
RCLK
Q −Q
A
L
H
1
6.6*
6.6*
13*
13*
1*
1*
15*
15*
1
C
C
= 15 pF
= 15 pF
ns
ns
SRCLK
SRCLR
Q
Q
L
L
H′
H′
1
15
6.2* 12.8*
6* 11.5*
1* 13.7*
1* 13.5*
1* 13.5*
1
13.7
13.5
13.5
17
1
C
C
= 15 pF
= 50 pF
ns
ns
OE
Q −Q
A
L
L
H
7.8* 11.5*
1
7.9
7.9
9.2
9.2
9
15.4
15.4
16.5
16.5
16.3
1
1
1
1
1
17
17
1
RCLK
Q −Q
A
H
1
17
18.5
18.5
17.2
1
18.5
18.5
17.2
C
C
= 50 pF
= 50 pF
ns
ns
SRCLK
SRCLR
Q
L
L
H′
1
1
Q
H′
t
t
t
t
7.8
9.6
8.1
9.3
15
15
1
1
1
1
17
17
1
1
1
1
17
17
PZH
PZL
PHZ
PLZ
C
C
= 50 pF
= 50 pF
ns
ns
OE
OE
Q −Q
A
L
L
H
15.7
15.7
16.2
16.2
16.2
16.2
Q −Q
A
H
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
ꢗ
ꢐ
ꢕ
ꢙ
ꢖ
ꢆ
ꢎ
ꢗ
ꢐ
ꢑ
ꢰ
ꢍ
ꢑ
ꢓ
ꢜ
ꢤ
ꢦ
ꢟ
ꢧ
ꢢ
ꢥ
ꢚ
ꢜ
ꢟ
ꢤ
ꢠ
ꢟ
ꢤ
ꢠ
ꢣ
ꢧ
ꢤ
ꢝ
ꢨ
ꢧ
ꢟ
ꢞ
ꢡ
ꢞꢣ ꢝ ꢜ ꢯꢤ ꢨꢛ ꢥ ꢝ ꢣ ꢟꢦ ꢞꢣ ꢱ ꢣ ꢪꢟ ꢨꢢꢣ ꢤꢚꢫ ꢆ ꢛꢥ ꢧꢥ ꢠꢚ ꢣꢧ ꢜꢝ ꢚꢜ ꢠ ꢞꢥ ꢚꢥ ꢥꢤ ꢞ ꢟꢚ ꢛꢣꢧ
ꢠ
ꢚ
ꢝ
ꢜ
ꢤ
ꢚ
ꢛ
ꢣ
ꢦ
ꢟ
ꢧ
ꢢ
ꢥ
ꢚ
ꢜ
ꢱ
ꢣ
ꢟ
ꢧ
ꢝ
ꢨ
ꢣ
ꢠ
ꢜ
ꢦ
ꢜ
ꢠ
ꢥ
ꢚ
ꢜ
ꢟ
ꢤ
ꢝ
ꢥ
ꢧ
ꢣ
ꢞ
ꢣ
ꢝ
ꢜ
ꢯ
ꢤ
ꢯ
ꢟ
ꢥ
ꢪ
ꢝ
ꢫ
ꢎ
ꢣ
ꢬ
ꢥ
ꢝ
ꢍ
ꢤ
ꢝ
ꢚ
ꢧ
ꢡ
ꢢ
ꢣ
ꢤ
ꢠ ꢛꢥ ꢤ ꢯꢣ ꢟꢧ ꢞꢜ ꢝ ꢠ ꢟꢤ ꢚꢜ ꢤꢡꢣ ꢚ ꢛꢣ ꢝ ꢣ ꢨꢧ ꢟꢞ ꢡꢠꢚ ꢝ ꢭ ꢜꢚꢛ ꢟꢡꢚ ꢤꢟꢚ ꢜꢠꢣ ꢫ
ꢚ
ꢝ
ꢧ
ꢣ
ꢝ
ꢣ
ꢧ
ꢱ
ꢣ
ꢝ
ꢚ
ꢛ
ꢣ
ꢧ
ꢜ
ꢯ
ꢛ
ꢚ
ꢚ
ꢟ
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢂ ꢇ ꢂꢈ ꢀ ꢁꢉ ꢃ ꢄꢅꢆ ꢂ ꢇꢂ
ꢊꢋ ꢌꢍ ꢎ ꢀꢅ ꢍ ꢏ ꢎ ꢐ ꢑꢒ ꢍꢀ ꢎꢑ ꢐꢀ
ꢓꢍ ꢎ ꢅ ꢔ ꢋꢀꢎꢄꢎ ꢑ ꢕꢖꢎ ꢗꢖ ꢎ ꢐꢑ ꢒ ꢍꢀ ꢎꢑ ꢐꢀ
SCLS373I − MAY 1997 − REVISED JUNE 2004
switching characteristics over recommended operating free-air temperature range,
V
= 5 V 0.5 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
170*
140
4.3*
4.3*
4.5*
4.5*
4.5*
4.3*
5.4*
5.6
SN54AHC595 SN74AHC595
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MHz
ns
MIN
135*
95
MAX
MIN
115*
85
1*
1*
1*
1*
1*
1*
1*
1
MAX
MIN
115
85
1
MAX
C
C
= 15 pF
= 50 pF
L
L
f
max
t
t
t
t
t
t
t
t
t
t
t
t
7.4*
7.4*
8.2*
8.2*
8*
8.5*
8.5*
9.4*
9.4*
9.1*
10*
8.5
8.5
PLH
PHL
PLH
PHL
PHL
PZH
PZL
PLH
PHL
PLH
PHL
PHL
C
= 15 pF
RCLK
Q −Q
A
L
H
1
1
9.4
C
C
= 15 pF
= 15 pF
ns
ns
SRCLK
SRCLR
Q
Q
L
L
H′
H′
1
9.4
1
9.1
8.6*
8.6*
9.4
1
10
C
C
= 15 pF
= 50 pF
ns
ns
OE
Q −Q
A
L
L
H
10*
1
10
10.5
10.5
11.4
11.4
11.1
1
10.5
10.5
11.4
11.4
11.1
RCLK
Q −Q
A
H
5.6
9.4
1
1
6.4
10.2
10.2
10
1
1
C
C
= 50 pF
= 50 pF
ns
ns
SRCLK
SRCLR
Q
L
L
H′
6.4
1
1
6.4
1
1
Q
H′
t
t
t
t
5.7
6.8
3.5
3.4
10.6
10.6
10.3
10.3
1
1
1
1
12
12
11
11
1
1
1
1
12
12
11
11
PZH
PZL
PHZ
PLZ
C
C
= 50 pF
= 50 pF
ns
ns
OE
OE
Q −Q
A
L
L
H
Q −Q
A
H
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
No load, f = 1 MHz
TYP
UNIT
C
Power dissipation capacitance
25.2
pF
pd
ꢗ
ꢐ
ꢕ
ꢙ
ꢖ
ꢆ
ꢎ
ꢗ
ꢐ
ꢑ
ꢰ
ꢍ
ꢑ
ꢓ
ꢜ
ꢤ
ꢦ
ꢟ
ꢧ
ꢢ
ꢥ
ꢚ
ꢜ
ꢟ
ꢤ
ꢠ
ꢟ
ꢤ
ꢠ
ꢣ
ꢧ
ꢤ
ꢝ
ꢨ
ꢧ
ꢟ
ꢞ
ꢡ
ꢠ
ꢞ ꢣ ꢝ ꢜ ꢯ ꢤ ꢨꢛ ꢥ ꢝ ꢣ ꢟꢦ ꢞꢣ ꢱ ꢣ ꢪ ꢟꢨ ꢢꢣ ꢤ ꢚꢫ ꢆ ꢛꢥ ꢧꢥ ꢠꢚ ꢣꢧ ꢜꢝ ꢚꢜ ꢠ ꢞꢥ ꢚꢥ ꢥꢤ ꢞ ꢟꢚ ꢛꢣꢧ
ꢚ
ꢝ
ꢜ
ꢤ
ꢚ
ꢛ
ꢣ
ꢦ
ꢟ
ꢧ
ꢢ
ꢥ
ꢚ
ꢜ
ꢱ
ꢣ
ꢟ
ꢧ
ꢝ
ꢨ
ꢣ
ꢠ
ꢜ
ꢦ
ꢜ
ꢠ
ꢥ
ꢚ
ꢜ
ꢟ
ꢤ
ꢝ
ꢥ
ꢧ
ꢣ
ꢞ
ꢣ
ꢝ
ꢜ
ꢯ
ꢤ
ꢯ
ꢟ
ꢥ
ꢪ
ꢝ
ꢫ
ꢎ
ꢣ
ꢬ
ꢥ
ꢝ
ꢍ
ꢤ
ꢝ
ꢚ
ꢧ
ꢡ
ꢢ
ꢣ
ꢤ
ꢠ ꢛ ꢥ ꢤ ꢯꢣ ꢟꢧ ꢞꢜ ꢝ ꢠ ꢟꢤ ꢚꢜ ꢤꢡ ꢣ ꢚ ꢛꢣ ꢝ ꢣ ꢨꢧ ꢟ ꢞꢡꢠ ꢚꢝ ꢭ ꢜꢚꢛ ꢟꢡꢚ ꢤꢟꢚ ꢜꢠꢣ ꢫ
ꢚ
ꢝ
ꢧ
ꢣ
ꢝ
ꢣ
ꢧ
ꢱ
ꢣ
ꢝ
ꢚ
ꢛ
ꢣ
ꢧ
ꢜ
ꢯ
ꢛ
ꢚ
ꢚ
ꢟ
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢁ
ꢂ
ꢊ
ꢎ
ꢃ
ꢄ
ꢍ
ꢕ
ꢅ
ꢎ
ꢖ
ꢆ
ꢀ
ꢎ
ꢂ
ꢅ
ꢗ
ꢇ
ꢍ
ꢂ
ꢏ
ꢖ
ꢈ
ꢎ
ꢎ
ꢀ
ꢐ
ꢐ
ꢁ
ꢉ
ꢑ
ꢑ
ꢃ
ꢒ
ꢒ
ꢄ
ꢅ
ꢎ
ꢎ
ꢆ
ꢑ
ꢑ
ꢂ
ꢐ
ꢐ
ꢇ
ꢂ
ꢀ
ꢀ
ꢋ
ꢌ
ꢍꢀ
ꢓ
ꢍ
ꢎ
ꢅ
ꢔ
ꢋ
ꢀ
ꢎ
ꢄ
ꢑ
ꢍꢀ
SCLS373I − MAY 1997 − REVISED JUNE 2004
PARAMETER MEASUREMENT INFORMATION
V
CC
Open
GND
S1
R
= 1 kΩ
L
TEST
S1
From Output
Under Test
Test
Point
From Output
Under Test
t
t
/t
Open
PLH PHL
/t
C
C
L
t
V
CC
L
PLZ PZL
/t
(see Note A)
(see Note A)
GND
PHZ PZH
Open Drain
V
CC
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
V
CC
50% V
CC
Timing Input
0 V
t
w
t
h
t
su
V
CC
V
CC
50% V
CC
50% V
CC
Input
50% V
CC
50% V
CC
Data Input
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
CC
CC
Output
Control
50% V
CC
50% V
CC
50% V
CC
50% V
t
Input
CC
0 V
0 V
t
PZL
t
t
t
PLZ
PLH
PHL
Output
Waveform 1
V
OH
≈V
CC
In-Phase
Output
50% V
50% V
CC
50% V
CC
CC
V
S1 at V
(see Note B)
V
OL
+ 0.3 V
CC
V
OL
OL
t
t
t
PHL
PLH
PZH
PHZ
Output
Waveform 2
S1 at GND
V
V
OH
OH
Out-of-Phase
Output
V
OH
− 0.3 V
50% V
CC
50% V
50% V
CC
CC
V
≈0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
D. The outputs are measured one at a time, with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
9-Aug-2005
PACKAGING INFORMATION
Orderable Device
SN74AHC595D
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
16
16
16
16
16
16
16
16
16
16
16
16
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74AHC595DBR
SN74AHC595DBRE4
SN74AHC595DE4
SN74AHC595DR
SSOP
SSOP
SOIC
SOIC
SOIC
PDIP
DB
DB
D
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74AHC595DRE4
SN74AHC595N
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
N
25
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
SN74AHC595NSR
SN74AHC595NSRE4
SN74AHC595PW
SN74AHC595PWE4
SN74AHC595PWR
SN74AHC595PWRG4
SO
NS
NS
PW
PW
PW
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
9-Aug-2005
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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