SN54ALS113AFK [TI]

ALS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CQCC20, CERAMIC, LCC-20;


型号：	SN54ALS113AFK
厂家：	TEXAS INSTRUMENTS
描述：	ALS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CQCC20, CERAMIC, LCC-20 输出元件逻辑集成电路触发器
文件：	总4页 (文件大小：55K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SN54ALS113A, SN74ALS113A

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS

WITH PRESET

SDAS200 – D2661, APRIL 1982 – REVISED MAY 1986

• Fully Buffered to Offer Maximum isolation

SN54ALS113A . . . J PACKAGE

SN74ALS113A . . . D OR N PACKAGE

from External Disturbance

(TOP VIEW)

• Package Options Include Plastic Small

Outline Packages, Ceramic Chip Carriers,

and Standard Plastic and Ceramic 300-mil

DIPs

1 CLK

1PRE

2CLK

2PRE

• Dependable Texas Instruments Quality and

Reliability

GND

TYPICAL POWER

DISSIPATION

PER FLIP-FLOP

TYPICAL MAXIMUM

CLOCK FREQUENCY

TYPE

’ALS113A

40 MHz (C =15 pF)

6 mW

SN54ALS113A . . . FK PACKAGE

(TOP VIEW)

description

These devices contain two independent J-K

negative-edge-triggered flip-flops. A low level at

the Preset input sets the outputs regardless of the

levels of the other inputs. When Preset PRE is

inactive (high), data at the J and K inputs meeting

the setup time requirements are transferred to the

outputs on the negative-going edge of the clock

pulse. Clock triggering occurs at a voltage level

and is not directly related to the fall time of the

clock pulse. Following the hold time interval, data

at the J and K inputs may be changed without

affecting the levels at the outputs. These versatile

flip-flops can perform as toggle flip-flops by tying

J and K high.

20 19

1PRE

2PRE

9 10 11 12 13

NC–No internal connection

†

logic symbol

The SN54ALS113A is characterized for operation

over the full military temperature range of –55°C

to 125°C. The SN74ALS113A is characterized for

operation from 0°C to 70°C.

1PRE

1CLK

FUNCTION TABLE

INPUTS

OUTPUTS

PRE

CLK

2PRE

↓

2CLK

↓

TOGGLE

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and

IEC Publication 617-12.

Pin numbers shown are for D, J, and N packages.

5BASIC

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ALS113A, SN74ALS113A

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS

WITH PRESET

SDAS200 – D2661, APRIL 1982 – REVISED MAY 1986

logic diagram (positive logic)

PRE

CLK

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

Operating free-air temperature range: SN54ALS113A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C

SN74ALS113A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

recommended operating conditions

SN54ALS113A

MIN NOM MAX

SN74ALS113A

MIN NOM MAX

UNIT

Supply voltage

4.5

5.5

4.5

5.5

High-level input voltage

Low-level input voltage

High-level output current

Low-level output current

Clock frequency

0.7

–0.4

0.8

–0.4

mHz

clock

PRE low

CLK high

CLK low

Data

Pulse duration

16.5

Setup time before CLK↓

PRE inactive

Hold time, data after CLK↓

Operating free-air temperature

–55

125

°C

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ALS113A, SN74ALS113A

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS

WITH PRESET

SDAS200 – D2661, APRIL 1982 – REVISED MAY 1986

electrical characteristic over recommended operating free-air temperature range (unless

otherwise noted)

SN54ALS113A

SN74ALS113A

PARAMETER

TEST CONDITIONS

UNIT

†

TYP

†

TYP

MIN

MAX

MIN

MAX

= 4.5 V,

I = –18 mA

–1.5

= 4.5 V to 5.5 V,

= 4.5 V,

= –0.4 mA

= 4 mA

–2

0.25

0.4

0.25

0.35

0.4

0.5

= 4.5 V,

= 8 mA

J, K, or CLK

PRE

0.1

0.2

0.1

= 5.5 V,

V = 7 V

0.2

J, K, or CLK

PRE

V = 2.7 V

µA

J, K, or CLK

PRE

–0.2

–0.4

–112

4.5

–0.2

–0.4

–112

4.5

V = 0.4 V

‡

= 5.5 V,

V = 2.25 V

See Note 1

–30

2.5

†

‡

All typical values are at V

= 5 V, T = 25°C.

The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I

NOTE 1:

is measured with J, K, CLK, and PRE grounded, then with J, K, CLK, and CLR grounded.

switching characteristics (see Note 2)

= 4.5 V to 5.5 V,

= 50 pF,

FROM

= 500 Ω,

PARAMETER

UNIT

(INPUT)

(OUTPUT)

= MIN to MAX

SN54ALS113A SN74ALS113A

MIN

MAX

MIN

MAX

MHz

max

PLH

PHL

PLH

PHL

Q or Q

PRE

CLK

NOTE 2: Load circuit and voltage waveforms are shown in Section 1.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

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