SN54ALS161B_15 [TI]
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS;
| 型号： | SN54ALS161B_15 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS |
| 文件： | 总14页 (文件大小：222K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276 – DECEMBER 1994
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161,
• Internal Look-Ahead Circuitry for Fast
SN54AS163 . . . J PACKAGE
SN74ALS161B, SN74ALS163B, SN74AS161,
SN74AS163 . . . D OR N PACKAGE
(TOP VIEW)
Counting
• Carry Output for n-Bit Cascading
• Synchronous Counting
• Synchronously Programmable
• Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
CLR
CLK
A
V
CC
RCO
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Q
A
B
C
D
Q
B
Q
C
Q
D
ENT
description
ENP
GND
LOAD
These synchronous, presettable, 4-bit decade
and binary counters feature an internal carry
look-ahead circuitry for application in high-speed
counting designs. The SN54ALS162B is a 4-bit
decade counter. The ′ALS161B, ′ALS163B,
′AS161, and ′AS163 are 4-bit binary counters.
Synchronous operation is provided by having all
flip-flops clocked simultaneously so that the
outputs change coincidentally with each other
when instructed by the count-enable (ENP, ENT)
inputs and internal gating. This mode of operation
eliminates the output counting spikes normally
associated with asynchronous (ripple-clock)
counters. A buffered clock (CLK) input triggers the
four flip-flops on the rising (positive-going) edge of
the clock input waveform.
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161,
SN54AS163 . . . FK PACKAGE
(TOP VIEW)
3
2
1
20 19
18
A
B
Q
Q
4
5
6
7
8
A
B
17
16
15
14
NC
C
NC
Q
C
D
Q
D
9 10 11 12 13
These counters are fully programmable; they may
be preset to any number between 0 and 9 or 15.
Because presetting is synchronous, setting up a
low level at the load (LOAD) input disables the
counter and causes the outputs to agree with the
setup data after the next clock pulse, regardless of
the levels of the enable inputs.
NC – No internal connection
The clear function for the ′ALS161B and ′AS161 is asynchronous. A low level at the clear (CLR) input sets all
four of the flip-flop outputs low, regardless of the levels of the CLK, LOAD, or enable inputs. The clear function
for the SN54ALS162B, ′ALS163B, and ′AS163 is synchronous, and a low level at CLR sets all four of the flip-flop
outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear
allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The
active-low output of the gate used for decoding is connected to CLR to synchronously clear the counter to
0000 (LLLL).
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without
additional gating. ENP and ENT inputs and a ripple-carry (RCO) output are instrumental in accomplishing this
function. Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. RCO, thus enabled,
produces a high-level pulse while the count is maximum (9 or 15 with Q high). The high-level overflow
A
ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed,
regardless of the level of CLK.
Copyright 1994, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276 – DECEMBER 1994
description (continued)
These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of
the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the
stable setup and hold times.
The SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, and SN54AS163 are characterized for
operation over the full military temperature range of –55°C to 125°C. The SN74ALS161B, SN74ALS163B,
SN74AS161, and SN74AS163 are characterized for operation from 0°C to 70°C.
†
logic symbols
′ALS161B AND ′AS161 BINARY COUNTERS
′ALS163B AND ′AS163 BINARY COUNTERS
WITH DIRECT CLEAR
WITH SYNCHRONOUS CLEAR
CTRDIV16
CTRDIV16
1
1
CT=0
5CT=0
CLR
CLR
9
9
M1
M2
G3
M1
M2
G3
LOAD
LOAD
15
15
3CT=15
RCO
3CT=15
RCO
10
10
ENT
ENT
7
2
7
2
ENP
CLK
G4
ENP
CLK
G4
C5/2,3,4+
C5/2,3,4+
3
4
5
6
14
13
12
11
3
4
5
6
14
13
12
11
[1]
[2]
[4]
[8]
Q
A
[1]
[2]
[4]
[8]
Q
A
A
B
C
D
1, 5D
A
B
C
D
1, 5D
Q
B
Q
B
Q
C
Q
C
Q
D
Q
D
SN54ALS162B DECADE COUNTER
WITH SYNCHRONOUS CLEAR
CTRDIV10
5CT=0
1
9
CLR
M1
LOAD
15
M2
3CT=9
RCO
10
ENT
G3
7
2
ENP
CLK
G4
C5/2,3,4+
3
4
5
6
14
13
12
11
Q
A
[1]
[2]
[4]
[8]
A
B
C
D
1, 5D
Q
B
Q
C
Q
D
†
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276 – DECEMBER 1994
logic diagram (positive logic)
SN54ALS162B
9
LOAD
10
7
15
ENT
ENP
RCO
1
CLR
2
CLK
14
C1
1D
Q
A
3
A
13
C1
1D
Q
B
4
B
12
Q
C1
1D
C
5
C
11
C1
1D
Q
D
6
D
Pin numbers shown are for the J package.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276 – DECEMBER 1994
logic diagram (positive logic)
′ALS163B and ′AS163
1
CLR
9
LOAD
10
ENT
15
7
RCO
ENP
2
CLK
14
13
12
C1
1D
Q
Q
Q
A
B
C
3
A
C1
1D
4
B
C1
1D
5
C
11
C1
1D
Q
D
6
D
Pin numbers shown are for the D, J, and N packages.
′ALS161B and ′AS161 synchronous binary counters are similar; however, CLR is asynchronous.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276 – DECEMBER 1994
typical clear, preset, count, and inhibit sequences
SN54ALS162B
The following sequence is illustrated below:
1. Clear outputs to zero (SN54ALS162B is synchronous)
2. Preset to BCD 7
3. Count to 8, 9, 0, 1, 2, and 3
4. Inhibit
CLR
LOAD
A
B
Data
Inputs
C
D
CLK
ENP
ENT
Q
A
Q
Q
Q
B
C
D
Data
Outputs
RCO
7
8
9
0
1
2
3
Count
Inhibit
Sync Preset
Clear
Async
Clear
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276 – DECEMBER 1994
typical clear, preset, count, and inhibit sequences
′ALS161B, ′AS161, ′ALS163B, and ′AS163
The following sequence is illustrated below:
1. Clear outputs to zero (′ALS161B and ′AS161 are asynchronous; ′ALS163B and ′AS163 are
synchronous.)
2. Preset to binary 12
3. Count to 13, 14, 15, 0, 1, and 2
4. Inhibit
CLR
LOAD
A
B
Data
Inputs
C
D
CLK
ENP
ENT
Q
A
Q
Q
Q
B
C
D
Data
Outputs
RCO
12
13
14
15
0
1
2
Count
Inhibit
Sync Preset
Clear
Async
Clear
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276 – DECEMBER 1994
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
I
Operating free-air temperature range, T : SN54ALS161B, SN54ALS162B,
A
SN54ALS163B . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
SN74ALS161B, SN74ALS163B . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54ALS161B
SN54ALS162B
SN54ALS163B
SN74ALS161B
SN74ALS163B
UNIT
MIN NOM
MAX
MIN NOM
MAX
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Clock frequency
IH
0.7
–0.4
4
0.8
–0.4
8
V
IL
I
I
f
mA
mA
MHz
OH
OL
clock
0
20
20
50
20
25
20
10
20
20
0
22
0
12.5
15
15
15
15
15
10
15
10
0
40
CLR high or low
t
w
Pulse duration
ns
′ALS161B
CLR low
A, B, C, D
LOAD
′ALS161B
ENP, ENT
Setup time
before CLK↑
t
t
SN54ALS162B, ′ALS163B
′ALS161B
ns
su
CLR inactive
CLR low
SN54ALS162B, ′ALS163B
CLR high
Hold time, all synchronous inputs after CLK↑
ns
h
T
A
Operating free-air temperature
–55
125
0
70
°C
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276 – DECEMBER 1994
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54ALS161B
SN74ALS161B
SN54ALS162B
SN74ALS163B
PARAMETER
TEST CONDITIONS
UNIT
SN54ALS163B
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
= 4.5 V,
I = –18 mA
–1.5
–1.5
V
V
IK
CC
I
= 4.5 V to 5.5 V,
I
I
I
= –0.4 mA
= 4 mA
V
CC
–2
V
CC
–2
OH
CC
OH
OL
OL
0.25
0.4
0.25
0.35
0.4
0.5
V
OL
V
CC
= 4.5 V
V
= 8 mA
I
I
I
I
I
V
CC
V
CC
V
CC
V
CC
V
CC
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V
V = 7 V
0.1
20
0.1
mA
µA
I
I
V = 2.7 V
I
20
IH
IL
V = 0.4 V
I
–0.2
–112
21
–0.2
–112
21
mA
mA
mA
‡
V
O
= 2.25 V
–20
–30
O
12
12
CC
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I
.
OS
switching characteristics (see Figure 3)
V
C
R
= 4.5 V to 5.5 V,
= 50 pF,
CC
L
L
= 500 Ω,
FROM
TO
(OUTPUT)
§
PARAMETER
(INPUT)
UNIT
T
A
= MIN to MAX
SN54ALS161B SN74ALS161B
MIN
22
5
MAX
MIN
40
5
MAX
f
t
t
t
t
t
t
MHz
ns
max
PLH
PHL
PLH
PHL
PLH
PHL
34
27
19
25
18
17
27
32
20
20
15
20
13
13
24
23
CLK
CLK
RCO
Any Q
RCO
5
5
4
4
ns
ns
ns
6
6
3
3
ENT
CLR
3
3
Any Q
RCO
8
8
t
PHL
11
11
§
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276 – DECEMBER 1994
switching characteristics (see Figure 3)
V
C
R
= 4.5 V to 5.5 V,
= 50 pF,
CC
L
L
= 500 Ω,
†
FROM
TO
(OUTPUT)
T
A
= MIN to MAX
PARAMETER
(INPUT)
UNIT
SN54ALS162B
SN54ALS163B
SN74ALS163B
MIN
35
5
MAX
MIN
40
5
MAX
f
t
t
t
t
t
t
MHz
ns
max
PLH
PHL
PLH
PHL
PLH
PHL
25
25
18
25
16
16
20
20
15
20
13
13
CLK
CLK
ENT
RCO
Any Q
RCO
5
5
4
4
ns
ns
6
6
3
3
3
3
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
I
Operating free-air temperature range, T : SN54AS161, SN54AS163 . . . . . . . . . . . . . . . . . . –55°C to 125°C
A
SN74AS161, SN74AS163 . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
SN54AS161
SN54AS163
SN74AS161
SN74AS163
UNIT
MIN NOM
MAX
MIN NOM
MAX
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Clock frequency
IH
0.8
–2
20
65
0.8
–2
20
75
V
IL
I
I
f
mA
mA
MHz
OH
OL
clock
*
0
7.7
10
10
10
10
10
14
10
2
0
6.7
8
CLR high or low
t *
w
Pulse duration
ns
′AS161
CLR low
A, B, C, D
LOAD
8
8
ENP, ENT
′AS161
8
Setup time
before CLK↑
t
su
*
ns
CLR inactive
CLR low
8
12
9
′AS163
CLR high (inactive)
t *
h
Hold time, all synchronous inputs after CLK↑
0
ns
T
A
Operating free-air temperature
–55
125
0
70
°C
* On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested.
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276 – DECEMBER 1994
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54AS161
SN54AS163
SN74AS161
SN74AS163
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
V
V
= 4.5 V,
I = –18 mA
–1.2
–1.2
V
V
V
IK
CC
CC
CC
I
= 4.5 V to 5.5 V,
= 4.5 V,
I
= –2 mA
= 20 mA
V
CC
–2
V
CC
–2
OH
OL
OH
OL
I
0.25
0.5
0.3
0.2
0.1
60
0.25
0.5
0.3
0.2
0.1
60
LOAD
ENT
I
I
I
V
CC
V
CC
V
CC
= 5.5 V,
= 5.5 V,
= 5.5 V,
V = 7 V
I
mA
µA
I
All others
LOAD
ENT
V = 2.7 V
I
40
40
IH
IL
All others
LOAD
ENT
20
20
–1.5
–1
–1.5
–1
V = 0.4 V
I
mA
All others
–0.5
–112
53
–0.5
–112
53
‡
I
I
V
V
= 5.5 V,
= 5.5 V
V = 2.25 V
O
–30
–30
mA
mA
O
CC
35
35
CC
CC
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I
.
OS
switching characteristics (see Figure 3)
V
C
R
= 4.5 V to 5.5 V,
= 50 pF,
CC
L
L
= 500 Ω,
FROM
TO
(OUTPUT)
§
PARAMETER
(INPUT)
UNIT
T
A
= MIN to MAX
SN54AS161
SN74AS161
MIN
65
1
MAX
MIN
75
1
MAX
f
t
*
MHz
ns
max
RCO (with LOAD high)
RCO (with LOAD low)
RCO
8.5
17.5
14
8
16.5
12.5
7
PLH
CLK
CLK
3
3
t
t
t
t
t
2
2
PHL
PLH
PHL
PLH
PHL
1
7.5
14
1
Any Q
RCO
ns
ns
ns
2
2
13
1.5
1
10
1.5
1
9
ENT
CLR
9.5
14
8.5
13
Any Q
RCO
2
2
t
PHL
2
14
2
12.5
* On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested.
§
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276 – DECEMBER 1994
switching characteristics (see Figure 3)
V
C
R
= 4.5 V to 5.5 V,
= 50 pF,
CC
L
L
= 500 Ω,
FROM
TO
(OUTPUT)
†
PARAMETER
(INPUT)
UNIT
T
A
= MIN to MAX
SN54AS163
SN74AS163
MIN
65
1
MAX
MIN
75
1
MAX
f
t
*
MHz
ns
max
RCO (with LOAD high)
RCO (with LOAD low)
RCO
8.5
17.5
14
8
16.5
12.5
7
PLH
CLK
3
3
t
t
t
t
t
2
2
PHL
PLH
PHL
PLH
PHL
1
7.5
14
1
CLK
ENT
Any Q
RCO
ns
ns
2
2
13
1.5
1
10
1.5
1
9
9.5
8.5
* On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested.
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276 – DECEMBER 1994
APPLICATION INFORMATION
n-bit synchronous counters
This application demonstrates how the ripple-mode carry circuit (see Figure 1) and the carry-look-ahead circuit
(see Figure 2) can be used to implement a high-speed n-bit counter. The SN54ALS162B counts in BCD. The
′ALS161B, ′AS161, ′ALS163B, and ′AS163 count in binary. When additional stages are added, the f
decreases in Figure 1, but remains unchanged in Figure 2.
max
LSB
CTR
LSB
CTR
CLR
LOAD
ENT
ENP
CLK
CLR
LOAD
ENT
ENP
CLK
CT=0
M1
G3
CT=0
M1
G3
Clear (L)
Clear (L)
Count (H)
Disable (L)
Count (H)
Disable (L)
RCO
RCO
3CT=MAX
3CT=MAX
G4
G4
Clock
C5/T,3,4+
C5/T,3,4+
A
B
C
D
A
B
C
D
1,5D
1,5D
Q
A
Q
A
Load (L)
Load (L)
Q
Q
Q
Q
Q
Q
B
C
D
B
C
D
Count (H)
Disable (L)
Clock
CLR
LOAD
ENT
ENP
CLK
CLR
LOAD
ENT
ENP
CLK
CTR
CTR
CT=0
M1
G3
CT=0
M1
G3
RCO
RCO
3CT=MAX
3CT=MAX
G4
G4
C5/T,3,4+
C5/T,3,4+
A
B
C
A
B
C
1,5D
1,5D
Q
Q
Q
Q
A
B
A
B
Q
Q
Q
C
D
C
D
D
D
Q
CLR
LOAD
ENT
ENP
CLK
CLR
LOAD
ENT
ENP
CLK
CTR
CTR
CT=0
M1
G3
CT=0
M1
G3
RCO
RCO
3CT=MAX
3CT=MAX
G4
G4
C5/T,3,4+
C5/T,3,4+
A
B
C
A
B
C
1,5D
1,5D
Q
Q
Q
Q
A
B
A
B
Q
Q
Q
C
D
C
D
D
D
Q
CLR
LOAD
ENT
ENP
CLK
CLR
LOAD
ENT
ENP
CLK
CTR
CTR
CT=0
M1
G3
CT=0
M1
G3
RCO
RCO
3CT=MAX
3CT=MAX
G4
G4
C5/T,3,4+
C5/T,3,4+
A
B
C
A
B
C
1,5D
1,5D
Q
Q
Q
Q
A
B
A
B
Q
Q
Q
C
D
C
D
D
D
Q
To More Significant Stages
= 1/(CLK to RCO t ) + (ENT to RCO t ) (N – 2) + (ENT t
To More Significant Stages
= 1/(CLK to RCO t ) + (ENP t
f
)
su
f
)
su
max
PLH PLH
max
PLH
Figure 1. Ripple-Mode Carry Circuit
Figure 2. Carry-Look-Ahead Circuit
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163
SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163
SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS
SDAS276 – DECEMBER 1994
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7 V
R
= R1 = R2
V
CC
L
S1
R1
R
L
Test
Point
From Output
Under Test
From Output
Under Test
Test
Point
Test
Point
From Output
Under Test
C
C
L
R
L
R2
L
C
L
(see Note A)
(see Note A)
(see Note A)
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
3.5 V
3.5 V
Timing
Input
High-Level
1.3 V
1.3 V
1.3 V
Pulse
0.3 V
0.3 V
t
h
t
w
t
su
3.5 V
3.5 V
0.3 V
Data
Input
Low-Level
1.3 V
1.3 V
1.3 V
1.3 V
Pulse
0.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
0.3 V
Output
Control
(low-level
enabling)
1.3 V
1.3 V
3.5 V
t
PZL
Input
1.3 V
1.3 V
t
PLZ
0.3 V
PHL
3.5 V
t
Waveform 1
S1 Closed
(see Note B)
t
PLH
1.3 V
V
OH
In-Phase
Output
1.3 V
1.3 V
1.3 V
V
OL
0.3 V
V
OL
t
PHZ
t
PLH
t
PZH
t
PHL
V
OH
V
Waveform 2
S1 Open
(see Note B)
OH
OL
Out-of-Phase
Output
(see Note C)
1.3 V
1.3 V
0.3 V
V
0 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, t = t = 2 ns, duty cycle = 50%.
r
f
E. The outputs are measured one at a time with one transition per measurement.
Figure 3. Load Circuits and Voltage Waveforms
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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Copyright 1998, Texas Instruments Incorporated
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TI
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