SN54ALS169B_15 [TI]

SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS;
SN54ALS169B_15
型号: SN54ALS169B_15
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS

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ꢀ ꢁꢂ ꢃ ꢄꢅ ꢀꢆ ꢇ ꢈ ꢉꢊꢋ ꢀꢁꢂ ꢃ ꢄ ꢀꢆ ꢇ ꢈ ꢄꢊꢋ ꢀꢁꢌ ꢃ ꢄ ꢅ ꢀꢆ ꢇ ꢈ ꢉꢊ ꢋ ꢀ ꢁꢌꢃ ꢄꢀ ꢆꢇ ꢈꢄ  
ꢀꢍ ꢁꢎꢏꢐꢑ ꢁꢑ ꢒꢀ ꢋꢃ ꢓꢉꢔꢕ ꢋ ꢒꢖꢗꢘ ꢑꢙ ꢁꢋꢉꢔ ꢁꢄꢐꢍꢋꢎ ꢑꢒ ꢁꢕ ꢚꢐ ꢀ  
SDAS125B − MARCH 1984 − REVISED DECEMBER 1994  
SN54ALS169B, SN54AS169A . . . J PACKAGE  
SN74ALS169B, SN74AS169A . . . D OR N PACKAGE  
(TOP VIEW)  
Fully Synchronous Operation for Counting  
and Programming  
Internal Carry Look-Ahead Circuitry for  
Fast Counting  
U/D  
CLK  
A
V
CC  
RCO  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
Carry Output for n-Bit Cascading  
Fully Independent Clock Circuit  
Q
A
B
C
D
Q
B
Package Options Include Plastic  
Small-Outline (D) Packages, Ceramic Chip  
Carriers (FK), and Standard Plastic (N) and  
Ceramic (J) 300-mil DIPs  
Q
C
Q
D
ENT  
ENP  
GND  
LOAD  
description  
SN54ALS169B, SN54AS169A . . . FK PACKAGE  
(TOP VIEW)  
These synchronous 4-bit up/down binary  
presettable counters feature an internal carry  
look-ahead circuitry for cascading in high-speed  
counting applications. Synchronous operation is  
provided by having all flip-flops clocked  
simultaneously so that the outputs change  
coincident with each other when so instructed by  
the count-enable (ENP, ENT) inputs and internal  
gating. This mode of operation eliminates the  
output counting spikes normally associated with  
asynchronous (ripple-clock) counters. A buffered  
clock (CLK) input triggers the four flip-flops on the  
rising (positive-going) edge of the clock waveform.  
3
2
1
20 19  
18  
A
B
Q
Q
4
5
6
7
8
A
B
17  
16  
15  
14  
NC  
C
NC  
Q
Q
C
D
D
9 10 11 12 13  
These counters are fully programmable; that is,  
they may be preset to either level. The load-input  
circuitry allows loading with the carry-enable  
output of cascaded counters. Because loading is  
synchronous, setting up a low level at the load  
(LOAD) input disables the counter and causes the  
outputs to agree with the data inputs after the next  
clock pulse.  
NC − No internal connection  
The internal carry look-ahead circuitry provides for cascading counters for n-bit synchronous application without  
additional gating. ENP and ENT inputs and a ripple-carry output (RCO) are instrumental in accomplishing this  
function. Both ENP and ENT must be low to count. The direction of the count is determined by the level of the  
up/down (U/D) input. When U/D is high, the counter counts up; when low, it counts down. ENT is fed forward  
to enable RCO. RCO, thus enabled, produces a low-level pulse while the count is zero (all inputs low) counting  
down or maximum (15) counting up. This low-level overflow ripple-carry pulse can be used to enable successive  
cascaded stages. Transitions at ENP or ENT are allowed regardless of the level of the clock input. All inputs  
are diode clamped to minimize transmission-line effects, thereby simplifying system design.  
These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, LOAD, or U/D)  
that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function  
of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the  
stable setup and hold times.  
The SN54ALS169B and SN54AS169A are characterized for operation over the full military temperature range  
of −55°C to 125°C. The SN74ALS169B and SN74AS169A are characterized for operation from 0°C to 70°C.  
ꢕꢦ  
Copyright 1994, Texas Instruments Incorporated  
ꢢ ꢦ ꢣ ꢢꢛ ꢜꢰ ꢞꢝ ꢡ ꢩꢩ ꢧꢡ ꢟ ꢡ ꢠ ꢦ ꢢ ꢦ ꢟ ꢣ ꢫ  
2−1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  
ꢁ ꢂ ꢃꢄ ꢅ ꢀꢆ ꢇ ꢈꢉ ꢊ ꢋ ꢀꢁ ꢂꢃ ꢄꢀ ꢆ ꢇ ꢈ ꢄꢊ ꢋ ꢀꢁ ꢌ ꢃꢄ ꢅ ꢀꢆ ꢇ ꢈ ꢉꢊ ꢋ ꢀꢁꢌ ꢃꢄꢀ ꢆ ꢇꢈ ꢄ  
ꢍ ꢁꢎ ꢏ ꢐ ꢑꢁ ꢑꢒ ꢀꢋ ꢃ ꢓꢉꢔ ꢕ ꢋꢒꢖ ꢗ ꢘꢑꢙꢁ ꢋ ꢉꢔꢁꢄ ꢐꢍꢋꢎ ꢑꢒ ꢁꢕꢚ ꢐꢀ  
SDAS125B − MARCH 1984 − REVISED DECEMBER 1994  
logic symbol  
CTRDIV16  
9
M1 [LOAD]  
M2 [COUNT]  
LOAD  
1
M3 [UP]  
U/D  
M4 [DOWN]  
15  
10  
RCO  
3,5CT=15  
4,5CT=0  
G5  
ENT  
7
ENP  
2
G6  
CLK  
2,3,5,6+/C7  
2,4,5,6 −  
3
14  
13  
12  
11  
Q
A
1
2
4
8
A
4
1, 7D  
Q
B
B
5
Q
C
C
6
Q
D
D
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.  
Pin numbers shown are for the D, J, and N packages.  
2−2  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢀ ꢆꢇ ꢈ ꢉꢊ ꢋꢀ ꢁꢂ ꢃ ꢄꢀꢆ ꢇ ꢈ ꢄ ꢊꢋꢀ ꢁꢌ ꢃ ꢄꢅ ꢀꢆ ꢇ ꢈ ꢉ ꢊꢋ ꢀ ꢁꢌ ꢃꢄꢀ ꢆ ꢇꢈꢄ  
ꢀꢍ ꢁꢎꢏꢐꢑ ꢁꢑ ꢒꢀ ꢋꢃ ꢓꢉꢔꢕ ꢋ ꢒꢖꢗꢘ ꢑꢙ ꢁꢋꢉꢔ ꢁꢄꢐꢍꢋꢎꢑ ꢒ ꢁꢕ ꢚꢐ ꢀ  
SDAS125B − MARCH 1984 − REVISED DECEMBER 1994  
logic diagram (positive logic)  
9
LOAD  
1
15  
U/D  
RCO  
10  
ENT  
7
ENP  
C1  
1D  
2
14  
CLK  
Q
Q
Q
A
B
C
3
A
C1  
1D  
13  
12  
11  
4
B
C1  
1D  
5
C
C1  
1D  
Q
D
6
D
Pin numbers shown are for the D, J, and N packages.  
2−3  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  
ꢍ ꢁꢎ ꢏ ꢐ ꢑꢁ ꢑꢒ ꢀꢋ ꢃ ꢓꢉꢔ ꢕ ꢋꢒꢖ ꢗ ꢘꢑꢙꢁ ꢋ ꢉꢔꢁꢄ ꢐꢍꢋꢎ ꢑꢒ ꢁꢕꢚ ꢐꢀ  
ꢇꢈ  
SDAS125B − MARCH 1984 − REVISED DECEMBER 1994  
typical load, count, and inhibit sequences  
The following sequence is illustrated below:  
1. Load (preset) to binary 13  
2. Count up to 14, 15 (maximum), 0, 1, and 2  
3. Inhibit  
4. Count down to 1, 0 (minimum), 15, 14, and 13  
LOAD  
A
B
Data  
Inputs  
C
D
CLK  
U/D  
ENP and ENT  
Q
A
Q
Q
Q
B
C
D
Data  
Outputs  
RCO  
13  
14  
15  
0
1
2
2
2
1
0
15  
14  
13  
Count Up  
Inhibit  
Count Down  
Load  
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)  
Supply voltage, V  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V  
CC  
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V  
I
Operating free-air temperature range, T : SN54ALS169B . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C  
A
SN74ALS169B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C  
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C  
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
2−4  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  
ꢁꢂ ꢃ ꢄꢅ ꢀ ꢆꢇ ꢈ ꢉꢊ ꢋꢀ ꢁꢂ ꢃ ꢄꢀꢆ ꢇ ꢈ ꢄ ꢊꢋꢀ ꢁꢌ ꢃ ꢄꢅ ꢀꢆ ꢇ ꢈ ꢉ ꢊꢋ ꢀ ꢁꢌ ꢃꢄꢀ ꢆ ꢇꢈꢄ  
ꢀꢍ ꢁꢎꢏꢐꢑ ꢁꢑ ꢒꢀ ꢋꢃ ꢓꢉꢔꢕ ꢋ ꢒꢖꢗꢘ ꢑꢙ ꢁꢋꢉꢔ ꢁꢄꢐꢍꢋꢎꢑ ꢒ ꢁꢕ ꢚꢐ ꢀ  
SDAS125B − MARCH 1984 − REVISED DECEMBER 1994  
recommended operating conditions  
SN54ALS169B  
SN74ALS169B  
MIN NOM MAX  
UNIT  
MIN NOM  
MAX  
V
V
V
Supply voltage  
4.5  
2
5
5.5  
4.5  
2
5
5.5  
V
V
CC  
High-level input voltage  
Low-level input voltage  
High-level output current  
Low-level output current  
Clock frequency  
IH  
0.7  
0.4  
4
0.8  
0.4  
8
V
IL  
I
I
f
t
mA  
mA  
MHz  
ns  
OH  
OL  
clock  
w
0
14  
20  
25  
20  
28  
0
22  
0
12.5  
15  
15  
15  
15  
0
40  
Pulse duration, CLK high or low  
A, B, C, or D  
ENP or ENT  
LOAD  
t
Setup time before CLK↑  
ns  
su  
h
U/D  
t
Hold time, data after CLK↑  
ns  
T
A
Operating free-air temperature  
55  
125  
0
70  
°C  
electrical characteristics over recommended operating free-air temperature range (unless  
otherwise noted)  
SN54ALS169B  
SN74ALS169B  
PARAMETER  
TEST CONDITIONS  
I = 18 mA  
UNIT  
MIN TYP  
MAX  
MIN TYP  
MAX  
V
V
V
V
= 4.5 V,  
1.5  
1.5  
V
V
IK  
CC  
I
= 4.5 V to 5.5 V,  
I
I
I
= 0.4 mA  
= 4 mA  
V
−2  
V
−2  
OH  
CC  
OH  
OL  
OL  
CC  
CC  
0.25  
0.4  
0.25  
0.35  
0.4  
0.5  
V
OL  
V
CC  
= 4.5 V  
V
= 8 mA  
I
I
I
I
I
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
= 5.5 V,  
= 5.5 V,  
= 5.5 V,  
= 5.5 V,  
= 5.5 V  
V = 7 V  
0.1  
20  
0.1  
mA  
µA  
I
I
V = 2.7 V  
I
20  
IH  
IL  
V = 0.4 V  
I
0.2  
112  
25  
0.2  
112  
25  
mA  
mA  
mA  
V
O
= 2.25 V  
20  
30  
O
15  
15  
CC  
All typical values are at V  
= 5 V, T = 25°C.  
A
CC  
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I  
.
OS  
2−5  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  
ꢁ ꢂ ꢃꢄ ꢅ ꢀꢆ ꢇ ꢈꢉ ꢊ ꢋ ꢀꢁ ꢂꢃ ꢄꢀ ꢆ ꢇ ꢈ ꢄꢊ ꢋ ꢀꢁ ꢌ ꢃꢄ ꢅ ꢀꢆ ꢇ ꢈ ꢉꢊ ꢋ ꢀꢁꢌ ꢃꢄꢀ ꢆ ꢇꢈ ꢄ  
ꢍ ꢁꢎ ꢏ ꢐ ꢑꢁ ꢑꢒ ꢀꢋ ꢃ ꢓꢉꢔ ꢕ ꢋꢒꢖ ꢗ ꢘꢑꢙꢁ ꢋ ꢉꢔꢁꢄ ꢐꢍꢋꢎ ꢑꢒ ꢁꢕꢚ ꢐꢀ  
SDAS125B − MARCH 1984 − REVISED DECEMBER 1994  
switching characteristics (see Figure 1)  
V
C
R
= 4.5 V to 5.5 V,  
= 50 pF,  
CC  
L
L
= 500 ,  
FROM  
TO  
(OUTPUT)  
PARAMETER  
(INPUT)  
UNIT  
T
A
= MIN to MAX  
SN54ALS169B SN74ALS169B  
MIN  
22  
3
MAX  
MIN  
40  
3
MAX  
f
t
t
t
t
t
t
t
t
MHz  
ns  
max  
PLH  
PHL  
PLH  
PHL  
PLH  
PHL  
PLH  
PHL  
20  
25  
20  
23  
16  
24  
22  
26  
20  
20  
15  
20  
13  
16  
19  
19  
CLK  
CLK  
ENT  
U/D  
RCO  
Any Q  
RCO  
RCO  
6
6
2
2
ns  
ns  
ns  
5
5
2
2
3
3
4
5
5
5
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.  
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)  
Supply voltage, V  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V  
CC  
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V  
I
Operating free-air temperature range, T : SN54AS169A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C  
A
SN74AS169A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C  
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C  
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
recommended operating conditions  
SN54AS169A  
MIN NOM MAX  
SN74AS169A  
MIN NOM MAX  
UNIT  
V
V
V
Supply voltage  
4.5  
2
5
5.5  
4.5  
2
5
5.5  
V
V
CC  
High-level input voltage  
Low-level input voltage  
High-level output current  
Low-level output current  
Clock frequency  
IH  
0.8  
−2  
20  
60  
0.8  
−2  
20  
75  
V
IL  
I
I
f
mA  
mA  
MHz  
ns  
OH  
OL  
clock  
*
0
7.7  
10  
0
6.7  
8
t *  
w
Pulse duration, CLK high or low  
A, B, C, or D  
ENP or ENT  
LOAD  
10  
8
t
su  
*
Setup time before CLK↑  
ns  
10  
8
U/D  
14  
11  
0
t *  
h
Hold time, data after CLK↑  
2
ns  
T
A
Operating free-air temperature  
55  
125  
0
70  
°C  
* On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested.  
2−6  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢀ ꢆꢇ ꢈ ꢉꢊ ꢋꢀ ꢁꢂ ꢃ ꢄꢀꢆ ꢇ ꢈ ꢄ ꢊꢋꢀ ꢁꢌ ꢃ ꢄꢅ ꢀꢆ ꢇ ꢈ ꢉ ꢊꢋ ꢀ ꢁꢌ ꢃꢄꢀ ꢆ ꢇꢈꢄ  
ꢀꢍ ꢁꢎꢏꢐꢑ ꢁꢑ ꢒꢀ ꢋꢃ ꢓꢉꢔꢕ ꢋ ꢒꢖꢗꢘ ꢑꢙ ꢁꢋꢉꢔ ꢁꢄꢐꢍꢋꢎꢑ ꢒ ꢁꢕ ꢚꢐ ꢀ  
SDAS125B − MARCH 1984 − REVISED DECEMBER 1994  
electrical characteristics over recommended operating free-air temperature range (unless  
otherwise noted)  
SN54AS169A  
SN74AS169A  
PARAMETER  
TEST CONDITIONS  
UNIT  
MIN TYP  
MAX  
MIN TYP  
MAX  
V
V
V
V
V
V
= 4.5 V,  
I = 18 mA  
1.2  
1.2  
V
V
V
IK  
CC  
CC  
CC  
I
= 4.5 V to 5.5 V,  
= 4.5 V,  
I
= 2 mA  
= 20 mA  
V
CC  
−2  
V
CC  
−2  
OH  
OL  
OH  
OL  
I
0.25  
0.5  
0.2  
0.25  
0.5  
0.2  
LOAD, ENT, U/D  
All others  
I
I
I
V
CC  
V
CC  
V
CC  
= 5.5 V,  
= 5.5 V,  
= 5.5 V,  
V = 7 V  
I
mA  
µA  
I
0.1  
0.1  
LOAD, ENT, U/D  
All others  
40  
40  
V = 2.7 V  
I
IH  
20  
20  
LOAD, ENT, U/D  
All others  
−1  
−1  
V = 0.4 V  
I
mA  
IL  
0.5  
112  
63  
0.5  
112  
63  
I
I
V
V
= 5.5 V,  
= 5.5 V  
V = 2.25 V  
O
30  
30  
mA  
mA  
O
CC  
41  
41  
CC  
CC  
All typical values are at V  
CC  
= 5 V, T = 25°C.  
A
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I  
.
OS  
switching characteristics (see Figure 1)  
V
C
R
= 4.5 V to 5.5 V,  
= 50 pF,  
CC  
L
L
= 500 ,  
FROM  
TO  
(OUTPUT)  
§
PARAMETER  
(INPUT)  
UNIT  
T
A
= MIN to MAX  
SN54AS169A SN74AS169A  
MIN  
60  
3
MAX  
MIN  
75  
3
MAX  
f
t
t
t
t
t
t
t
t
*
MHz  
ns  
max  
17.5  
14  
16.5  
13  
7
PLH  
PHL  
PLH  
PHL  
PLH  
PHL  
PLH  
PHL  
RCO  
(LOAD high or low)  
CLK  
CLK  
ENT  
U/D  
2
2
1
7.5  
14  
1
Any Q  
RCO  
RCO  
ns  
ns  
ns  
2
2
13  
9
1.5  
1.5  
2
10  
1.5  
1.5  
2
10  
9
14  
12  
13  
2
14.5  
2
* On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested.  
§
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.  
2−7  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  
ꢁ ꢂ ꢃꢄ ꢅ ꢀꢆ ꢇ ꢈꢉ ꢊ ꢋ ꢀꢁ ꢂꢃ ꢄꢀ ꢆ ꢇ ꢈ ꢄꢊ ꢋ ꢀꢁ ꢌ ꢃꢄ ꢅ ꢀꢆ ꢇ ꢈ ꢉꢊ ꢋ ꢀꢁꢌ ꢃꢄꢀ ꢆ ꢇꢈ ꢄ  
ꢍ ꢁꢎ ꢏ ꢐ ꢑꢁ ꢑꢒ ꢀꢋ ꢃ ꢓꢉꢔ ꢕ ꢋꢒꢖ ꢗ ꢘꢑꢙꢁ ꢋ ꢉꢔꢁꢄ ꢐꢍꢋꢎ ꢑꢒ ꢁꢕꢚ ꢐꢀ  
SDAS125B − MARCH 1984 − REVISED DECEMBER 1994  
PARAMETER MEASUREMENT INFORMATION  
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES  
7 V  
R
= R1 = R2  
V
CC  
L
S1  
R1  
R
L
Test  
Point  
From Output  
Under Test  
From Output  
Under Test  
Test  
Point  
Test  
Point  
From Output  
Under Test  
C
C
L
R
L
R2  
L
C
L
(see Note A)  
(see Note A)  
(see Note A)  
LOAD CIRCUIT FOR  
BI-STATE  
TOTEM-POLE OUTPUTS  
LOAD CIRCUIT  
FOR OPEN-COLLECTOR OUTPUTS  
LOAD CIRCUIT  
FOR 3-STATE OUTPUTS  
3.5 V  
3.5 V  
Timing  
Input  
High-Level  
1.3 V  
1.3 V  
1.3 V  
Pulse  
0.3 V  
0.3 V  
t
t
w
h
t
su  
3.5 V  
3.5 V  
0.3 V  
Data  
Input  
Low-Level  
1.3 V  
1.3 V  
1.3 V  
1.3 V  
Pulse  
0.3 V  
VOLTAGE WAVEFORMS  
SETUP AND HOLD TIMES  
VOLTAGE WAVEFORMS  
PULSE DURATIONS  
3.5 V  
Output  
Control  
(low-level  
enabling)  
1.3 V  
1.3 V  
0.3 V  
3.5 V  
t
PZL  
Input  
1.3 V  
1.3 V  
t
PLZ  
0.3 V  
PHL  
[3.5 V  
t
Waveform 1  
S1 Closed  
(see Note B)  
t
PLH  
1.3 V  
V
OH  
In-Phase  
Output  
1.3 V  
1.3 V  
1.3 V  
V
OL  
V
OL  
0.3 V  
t
PHZ  
t
PLH  
t
PZH  
t
PHL  
V
OH  
V
Waveform 2  
S1 Open  
(see Note B)  
OH  
OL  
Out-of-Phase  
Output  
(see Note C)  
1.3 V  
1.3 V  
0.3 V  
V
[0 V  
VOLTAGE WAVEFORMS  
VOLTAGE WAVEFORMS  
PROPAGATION DELAY TIMES  
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS  
NOTES: A. includes probe and jig capacitance.  
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.  
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.  
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.  
D. All input pulses have the following characteristics: PRR 1 MHz, t = t = 2 ns, duty cycle = 50%.  
r
f
E. The outputs are measured one at a time with one transition per measurement.  
Figure 1. Load Circuits and Voltage Waveforms  
2−8  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  
PACKAGE OPTION ADDENDUM  
www.ti.com  
9-Oct-2007  
PACKAGING INFORMATION  
Orderable Device  
Status (1)  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
LCCC  
CDIP  
CFP  
Drawing  
83025012A  
8302501EA  
ACTIVE  
ACTIVE  
FK  
J
20  
16  
16  
20  
16  
16  
16  
16  
1
1
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
POST-PLATE N / A for Pkg Type  
A42 SNPB  
Call TI  
N / A for Pkg Type  
Call TI  
8302501FA  
OBSOLETE  
ACTIVE  
W
FK  
J
JM38510/38003B2A  
JM38510/38003BEA  
SN54ALS169BJ  
SN54AS169AJ  
SN74ALS169BD  
LCCC  
CDIP  
CDIP  
CDIP  
SOIC  
1
1
1
POST-PLATE N / A for Pkg Type  
ACTIVE  
A42 SNPB  
A42 SNPB  
Call TI  
N / A for Pkg Type  
N / A for Pkg Type  
Call TI  
ACTIVE  
J
OBSOLETE  
ACTIVE  
J
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SN74ALS169BDE4  
SN74ALS169BDG4  
SN74ALS169BDR  
SN74ALS169BDRE4  
SN74ALS169BDRG4  
SN74ALS169BN  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
PDIP  
PDIP  
SO  
D
D
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
16  
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
N
25  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
SN74ALS169BNE4  
SN74ALS169BNSR  
SN74ALS169BNSRE4  
SN74ALS169BNSRG4  
SN74AS169AD  
N
25  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
NS  
NS  
NS  
D
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SO  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SO  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
PDIP  
PDIP  
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SN74AS169ADE4  
SN74AS169ADG4  
SN74AS169ADR  
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SN74AS169ADRE4  
SN74AS169ADRG4  
SN74AS169AN  
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
N
25  
Pb-Free  
(RoHS)  
CU NIPDAU N / A for Pkg Type  
CU NIPDAU N / A for Pkg Type  
POST-PLATE N / A for Pkg Type  
SN74AS169ANE4  
N
25  
Pb-Free  
(RoHS)  
SNJ54ALS169BFK  
SNJ54ALS169BJ  
SNJ54AS169AFK  
ACTIVE  
ACTIVE  
LCCC  
CDIP  
LCCC  
FK  
J
20  
16  
20  
1
1
TBD  
TBD  
TBD  
A42 SNPB  
Call TI  
N / A for Pkg Type  
Call TI  
OBSOLETE  
FK  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
9-Oct-2007  
Orderable Device  
Status (1)  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
SNJ54AS169AJ  
OBSOLETE  
CDIP  
J
16  
TBD  
Call TI  
Call TI  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
4-Oct-2007  
TAPE AND REEL BOX INFORMATION  
Device  
Package Pins  
Site  
Reel  
Reel  
A0 (mm)  
B0 (mm)  
K0 (mm)  
P1  
W
Pin1  
Diameter Width  
(mm) (mm) Quadrant  
(mm)  
330  
(mm)  
16  
SN74ALS169BDR  
SN74ALS169BNSR  
SN74AS169ADR  
D
NS  
D
16  
16  
16  
SITE 27  
SITE 41  
SITE 27  
6.5  
8.2  
6.5  
10.3  
10.5  
10.3  
2.1  
2.5  
2.1  
8
12  
8
16  
16  
16  
Q1  
Q1  
Q1  
330  
16  
330  
16  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
4-Oct-2007  
Device  
Package  
Pins  
Site  
Length (mm) Width (mm) Height (mm)  
SN74ALS169BDR  
SN74ALS169BNSR  
SN74AS169ADR  
D
NS  
D
16  
16  
16  
SITE 27  
SITE 41  
SITE 27  
342.9  
346.0  
342.9  
336.6  
346.0  
336.6  
28.58  
33.0  
28.58  
Pack Materials-Page 2  
MECHANICAL DATA  
MLCC006B – OCTOBER 1996  
FK (S-CQCC-N**)  
LEADLESS CERAMIC CHIP CARRIER  
28 TERMINAL SHOWN  
A
B
NO. OF  
TERMINALS  
**  
18 17 16 15 14 13 12  
MIN  
MAX  
MIN  
MAX  
0.342  
(8,69)  
0.358  
(9,09)  
0.307  
(7,80)  
0.358  
(9,09)  
19  
20  
11  
10  
9
20  
28  
44  
52  
68  
84  
0.442  
(11,23)  
0.458  
(11,63)  
0.406  
(10,31)  
0.458  
(11,63)  
21  
B SQ  
22  
0.640  
(16,26)  
0.660  
(16,76)  
0.495  
(12,58)  
0.560  
(14,22)  
8
A SQ  
23  
0.739  
(18,78)  
0.761  
(19,32)  
0.495  
(12,58)  
0.560  
(14,22)  
7
24  
25  
6
0.938  
(23,83)  
0.962  
(24,43)  
0.850  
(21,6)  
0.858  
(21,8)  
5
1.141  
(28,99)  
1.165  
(29,59)  
1.047  
(26,6)  
1.063  
(27,0)  
26 27 28  
1
2
3
4
0.080 (2,03)  
0.064 (1,63)  
0.020 (0,51)  
0.010 (0,25)  
0.020 (0,51)  
0.010 (0,25)  
0.055 (1,40)  
0.045 (1,14)  
0.045 (1,14)  
0.035 (0,89)  
0.045 (1,14)  
0.035 (0,89)  
0.028 (0,71)  
0.022 (0,54)  
0.050 (1,27)  
4040140/D 10/96  
NOTES: A. All linear dimensions are in inches (millimeters).  
B. This drawing is subject to change without notice.  
C. This package can be hermetically sealed with a metal lid.  
D. The terminals are gold plated.  
E. Falls within JEDEC MS-004  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
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Copyright © 2007, Texas Instruments Incorporated  

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