SN54ALS190 [TI]
SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS; 同步4位向上/向下十年和二进制计数器
| 型号： | SN54ALS190 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS |
| 文件： | 总8页 (文件大小：142K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54ALS190, SN54ALS191, SN74ALS190, SN74ALS191
SYNCHRONOUS 4-BIT UP/DOWN DECADE AND BINARY COUNTERS
SDAS210 – D2661, DECEMBER 1982 – REVISED MAY 1986
SN54ALS190, SN54ALS191 . . . J PACKAGE
SN74ALS190, SN74ALS191 . . . D OR N PACKAGE
• Single Down/Up Count Control Line
• Look-Ahead Circuitry Enhances Speed of
(TOP VIEW)
Cascaded Counters
• Fully Synchronous in Count Modes
V
A
B
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CC
• Asynchronously Presettable With Load
Q
Q
B
A
Control
CLK
RCO
MAX/MIN
LOAD
C
CTEN
D/U
• Package Options Include Plastic Small
Outline Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
Q
C
Q
D
D
GND
• Dependable Texas Instruments Quality and
Reliability
SN54ALS190, SN54ALS191 . . . FK PACKAGE
(TOP VIEW)
description
The ’ALS190 and ’ALS191 are synchronous,
reversible up/down counters. The ’ALSL90 is a
4-bit decade counter and the ’ALS191 is a 4-bit
binary counter. Synchronous counting operation
is provided by having all flip-flops clocked
simultaneously so that the outputs change
coincident with each other when so instructed by
the steering logic. This mode of operation
eliminates the output counting spikes normally
associated with asynchronous (ripple clock)
counters.
3
2
1
20 19
18
CLK
Q
4
5
6
7
8
A
RCO
CTEN
NC
17
16
15
14
NC
MAX/MIN
LOAD
D/U
Q
C
9 10 11 12 13
The outputs of the four flip-flops are triggered on
a low-to-high-level transition of the clock input if
the enable input CTEN is low. A high at CTEN
inhibits counting. The direction of the count is
determined by the level of the down/up D/U input.
When D/U is low, the counter counts up and when
D/U is high, it counts down.
NC–No internal connection
These counters feature a fully independent clock circuit. Changes at the control inputs (CTEN and D/U) that will
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of
the counter will be dictated solely by the condition meeting the stable setup and hold times.
These counters are fully programmable; that is, the outputs may each be preset to either level by placing a low
on the load input and entering the desired data at the data inputs. The output will change to agree with the data
inputs independently of the level of the clock input. This feature allows the counters to be used as modulo-N
dividers by simply modifying the count length with the preset inputs.
The CLK, D/U, and LOAD inputs are buffered to lower the drive requirement, which significantly reduces the
loading on, or current required by, clock drivers, etc., for long parallel words.
Two outputs have been made available to perform the cascading function: ripple clock and maximum/minimum
count. The latter output produces a high-level output pulse with a duration approximately equal to one complete
cycle of the clock while the count is zero (all outputs low) counting down or maximum (9 or 15) counting up. The
ripple clock output produces a low-level output pulse under those same conditions but only while the clock input
is low. The counters can be easily cascaded by feeding the ripple clock output to the enable input of the
succeeding counter if parallel clocking is used, or to the clock input if parallel enabling is used. The
maximum/minimum count output can be used to accomplish look-ahead for high-speed operation.
The SN54ALS190 and SN54ALS191 are characterized for operation over the full military temperature range
of –55°C to 125°C. The SN74ALS190 and SN74ALS191 are characterized for operation from 0°C to 70°C.
Copyright 1986, Texas Instruments Incorporated
5BASIC
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS190, SN54ALS190
SYNCHRONOUS 4-BIT UP/DOWN DECADE COUNTERS
SDAS210 – D2661, DECEMBER 1982 – REVISED MAY 1986
†
’ALS190 logic symbol
CTRDIV10
4
CTEN
D/U
G1
12
13
5
M2 (DOWN)
2(CT=0)Z6
3(CT=9)Z6
MAX/MIN
RCO
M3 (UP)
1,2–/1,3+
G4
14
11
CLK
6,1,4
LOAD
C5
3
2
15
1
A
B
1,5D
[1]
[2]
Q
A
B
Q
Q
Q
6
7
10
9
C
D
[4]
[8]
C
D
’ALS190 logic diagram (positive logic)
12
13
MAX/MIN
RCO
4
CTEN
5
D/U
14
CLK
11
LOAD
15
3
2
A
S
Q
Q
A
B
C1
1D
R
1
B
S
C1
1D
R
10
C
6
S
Q
C
C1
1D
R
9
D
7
S
Q
D
C1
1D
R
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for D, J, and N packages.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS191, SN54ALS191
SYNCHRONOUS 4-BIT UP/DOWN DECADE COUNTERS
SDAS210 – D2661, DECEMBER 1982 – REVISED MAY 1986
†
’ALS191 logic symbol
CTRDIV10
4
5
CTEN
D/U
G1
12
M2 (DOWN)
2(CT=0)Z6
3(CT=9)Z6
MAX/MIN
RCO
M3 (UP)
14
11
+
CLK
1,2–/1,3
G4
13
6,1,4
LOAD
C5
3
2
15
1
A
B
5D
[1]
[2]
Q
Q
A
B
6
7
10
9
C
D
[4]
[8]
Q
Q
C
D
’ALS191 logic diagram (positive logic)
12
13
MAX/MIN
RCO
4
CTEN
5
D/U
14
CLK
11
LOAD
15
3
2
A
S
Q
Q
A
B
C1
1D
R
1
B
S
C1
1D
R
10
C
6
S
Q
C
C1
1D
R
9
D
7
S
Q
D
C1
1D
R
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for D, J, and N packages.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS190, SN54ALS190
SYNCHRONOUS 4-BIT UP/DOWN DECADE COUNTERS
SDAS210 – D2661, DECEMBER 1982 – REVISED MAY 1986
typical load, count, and inhibit sequences
’ALS190
Illustrated below is the following sequence:
1. Load (preset) to BCD seven
2. Count up to eight, nine (maximum), zero, one, and two
3. Inhibit
4. Count down to one, zero (minimum), nine, eight, and seven
LOAD
A
B
Data
Inputs
C
D
CLOCK
D/U
CTEN
Q
Q
A
B
Q
Q
C
D
MAX/MIN
RCO
7
8
9
0
1
2
2
2
1
0
9
8
7
Count Up
Inhibit
Count Down
Load
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS191, SN54ALS191
SYNCHRONOUS 4-BIT UP/DOWN DECADE COUNTERS
SDAS210 – D2661, DECEMBER 1982 – REVISED MAY 1986
typical load, count, and inhibit sequences
’ALS191
Illustrated below is the following sequence:
1. Load (preset) to BCD seven
2. Count up to eight, nine (maximum), zero, one, and two
3. Inhibit
4. Count down to one, zero (minimum), nine, eight, and seven
LOAD
A
B
Data
Inputs
C
D
CLOCK
D/U
CTEN
Q
Q
A
B
Q
Q
C
D
MAX/MIN
RCO
7
8
9
0
1
2
2
2
1
0
9
8
7
Count Up
Inhibit
Count Down
Load
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS190, SN54ALS191, SN74ALS190, SN74ALS191
SYNCHRONOUS 4-BIT UP/DOWN DECADE COUNTERS
SDAS210 – D2661, DECEMBER 1982 – REVISED MAY 1986
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Operating free-air temperature range: SN54ALS190, SN54ALS191 . . . . . . . . . . . . . . . . . . . –55°C to 125°C
SN74ALS190, SN74ALS191 . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
recommended operating conditions
SN54ALS190
SN54ALS191
SN74ALS190
SN74ALS191
UNIT
MIN NOM
MAX
MIN NOM
MAX
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
IH
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
0.7
–0.4
4
0.8
–0.4
8
V
IL
I
I
mA
mA
OH
OL
’ALS190
’ALS191
0
0
20
0
0
25
f
Clock frequency
MHz
clock
20
30
’AS190
‘AS191
25
20
25
25
45
45
20
5
20
16.5
20
20
20
20
20
5
CLK high or low
t
Pulse duration
ns
w
LOAD low
Data before LOAD↑
CTEN before CLK↑
D/U before CLK↑
t
t
Setup time
ns
su
LOAD inactive before CLK↑
Data after LOAD↑
CTEN after CLK↑
Hold time
0
0
ns
su
D/U after CLK↑
0
0
T
A
Operating free-air temperature
–55
125
0
70
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54ALS190
SN54ALS191
SN74AAL190
SN74ALS191
PARAMETER
TEST CONDITIONS
UNIT
†
TYP
†
TYP
MIN
MAX
MIN
MAX
V
V
V
V
V
V
V
V
= 4.5 V,
I = –18 mA
–1.5
–1.5
V
V
IK
CC
I
= 4.5 V to 5.5 V,
= 4.5 V,
I
I
I
= –0.4 mA
= 4 mA
V
–2
V
–2
OH
OL
CC
OH
OL
OL
CC
CC
0.25
0.5
0.25
0.35
0.4
0.5
CC
V
V
= 4.5 V,
= 8 mA
CC
I
I
5.5 V,
V = 7 V
I
V = 2.7 V
I
0.1
20
0.1
mA
I
CC =
= 5.5 V,
20
µA
IH
CC
CC
CTEN OR CLK
All others
–0.2
–0.1
–112
22
–0.2
–0.1
– 112
22
I
IL
V
= 5.5 V,
V = 0.4 V
I
mA
‡
I
I
V
CC
V
CC
= 5.5 V,
= 5.5 V,
V = 2.25 V
O
All inputs at 0 V
–30
–30
mA
mA
O
12
12
CC
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I
.
OS
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS190, SN54ALS191, SN74ALS190, SN74ALS191
SYNCHRONOUS 4-BIT UP/DOWN DECADE COUNTERS
SDAS210 – D2661, DECEMBER 1982 – REVISED MAY 1986
switching characteristics (see Note 1)
V
CC
= 4.5 V to 5.5 V,
C
= 50 pF,
L
R
= 500 Ω,
L
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
T
A
= MIN to MAX
UNIT
SN54ALS190
SN54ALS191
SN74ALS190
SN74ALS191
MIN
20
20
7
MAX
MIN
25
30
8
MAX
’ALS190
f
MHz
ns
max
’ALS191
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
37
34
25
25
24
25
26
22
37
34
45
36
35
30
21
23
30
30
21
21
20
20
18
18
31
31
37
28
25
25
18
18
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
LOAD
A, B, C, D
CLK
Any Q
Any Q
RCO
8
8
4
4
ns
4
5
5
5
ns
5
5
3
3
CLK
CLK
D/U
Any Q
MAX/MIN
RCO
ns
ns
ns
3
3
8
8
8
8
12
10
8
15
10
8
D/U
MAX/MIN
RCO
ns
ns
8
8
4
4
CTEN
4
4
NOTE 1: Load circuit and voltage waveforms are shown in Section 1.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
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party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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