SN54ALS541_16 [TI]
OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS;
| 型号： | SN54ALS541_16 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS 驱动 输出元件 |
| 文件： | 总16页 (文件大小：510K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54ALS541, SN74ALS540, SN74ALS541
OCTAL BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SDAS025D – APRIL 1982 – REVISED MARCH 2002
SN54ALS541 . . . J PACKAGE
SN74ALS540 . . . DW, N, OR NS PACKAGE
SN74ALS541 . . . DB, DW, N, OR NS PACKAGE
(TOP VIEW)
3-State Outputs Drive Bus Lines or Buffer
Memory Address Registers
pnp Inputs Reduce dc Loading
Data Flowthrough Pinout (All Inputs on
Opposite Side From Outputs)
OE1
A1
A2
A3
A4
A5
A6
A7
A8
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
description
These octal buffers and line drivers are designed
to have the performance of the popular
SN54ALS240A/SN74ALS240A series and, at
the same time, offer a pinout with inputs and
outputs on opposite sides of the package. This
arrangement greatly facilitates printed circuit
board layout.
GND
The 3-state control gate is a 2-input NOR gate
such that, if either output-enable (OE1 or OE2)
input is high, all eight outputs are in the
high-impedance state.
SN54ALS541 . . . FK PACKAGE
(TOP VIEW)
The SN74ALS540 provides inverted data. The
’ALS541 provide true data at the outputs.
3
2
1
20 19
18
Y1
Y2
Y3
Y4
Y5
A3
A4
A5
A6
A7
4
5
6
7
8
17
16
15
14
The -1 versions of SN74ALS540 and
SN74ALS541 are identical to the standard
versions, except that the recommended
maximum I is increased to 48 mA. There is no
OL
9 10 11 12 13
-1 version of the SN54ALS541.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS541, SN74ALS540, SN74ALS541
OCTAL BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SDAS025D – APRIL 1982 – REVISED MARCH 2002
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
SN74ALS540N
SN74ALS540N
SN74ALS540-1N
SN74ALS541N
SN74ALS541-1N
SN74ALS540-1N
SN74ALS541N
PDIP – N
Tube
SN74ALS541-1N
SN74ALS540DW
SN74ALS540DWR
SN74ALS540-1DW
SN74ALS541DW
SN74ALS541DWR
SN74ALS541-1DW
SN74ALS541-1DWR
SN74ALS540NSR
SN74ALS540-1NSR
SN74ALS541NSR
SN74ALS541-1NSR
SN74ALS541DBR
SN74ALS541-1DBR
SNJ54ALS541J
Tube
ALS540
ALS540-1
ALS541
Tape and reel
Tube
SOIC – DW
Tube
0°C to 70°C
Tape and reel
Tube
ALS541-1
Tape and reel
Tape and reel
ALS540
ALS540-1
ALS541
SOP – NS
Tape and reel
ALS541-1
G541
SSOP – DB
Tape and reel
G541-1
CDIP – J
Tube
Tube
SNJ54ALS541J
SNJ54ALS541FK
–55°C to 125°C
LCCC – FK
SNJ54ALS541FK
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
logic diagrams (positive logic)
SN74ALS540
′ALS541
1
1
OE1
OE1
OE2
19
19
OE2
2
2
18
18
A1
A1
Y1
Y1
To Seven Other Channels
To Seven Other Channels
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS541, SN74ALS540, SN74ALS541
OCTAL BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SDAS025D – APRIL 1982 – REVISED MARCH 2002
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
I
Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Package thermal impedance, θ (see Note 1): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
JA
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions
SN74ALS540
SN74ALS541
SN54ALS541
UNIT
MIN NOM
MAX
MIN NOM
MAX
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
High-level output current
IH
0.7
–12
12
0.8
–15
24
V
IL
I
mA
OH
I
Low-level output current
mA
OL
†
48
70
T
A
Operating free-air temperature
–55
125
0
°C
†
Applies only to the -1 version and only if V
CC
is between 4.75 V and 5.25 V
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS541, SN74ALS540, SN74ALS541
OCTAL BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SDAS025D – APRIL 1982 – REVISED MARCH 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN74ALS540
SN54ALS541
SN74ALS541
PARAMETER
TEST CONDITIONS
UNIT
‡
‡
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
= 4.5 V,
I = –18 mA
–1.2
–1.2
V
IK
CC
I
= 4.5 V to 5.5 V,
I
I
I
I
I
I
I
= –0.4 mA
= –3 mA
= –12 mA
= –15 mA
= 12 mA
V
–2
V
–2
CC
OH
OH
OH
OH
OL
OL
OL
CC
2.4
CC
2.4
3.2
3.2
V
OH
V
= 4.5 V
= 4.5 V
2
CC
CC
2
0.25
0.4
0.25
0.35
0.35
0.4
0.5
0.5
20
V
OL
V
= 24 mA
V
†
= 48 mA
= 2.7 V
= 0.4 V
I
I
I
I
I
I
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
V
20
–20
0.1
µA
µA
OZH
OZL
I
O
O
V
–20
0.1
20
V = 7 V
I
mA
µA
V = 2.7 V
I
20
IH
V = 0.4 V
I
–0.2
–112
–0.1
–112
10
mA
mA
IL
§
V
O
= 2.25 V
–20
–30
O
Outputs high
Outputs low
5
13
SN74ALS540
V
V
= 5.5 V
= 5.5 V
22
CC
Outputs disabled
Outputs high
11
19
I
mA
CC
6
15
14
25
32
6
14
’ALS541
Outputs low
15
25
CC
Outputs disabled
13.5
13.5
22
†
‡
§
Applies only to the -1 version and only if V
CC
is between 4.75 V and 5.25 V
= 5 V, T = 25°C.
All typical values are at V
CC
The output conditions have been chosen to produce a current that closely approximates one-half of the true short-circuit output current, I
A
.
OS
switching characteristics (see Figure 1)
V
C
= 4.5 V to 5.5 V,
= 50 pF,
CC
L
R1 = 500 Ω,
R2 = 500 Ω,
T
A
FROM
PARAMETER
TO
(OUTPUT)
UNIT
¶
= MIN to MAX
(INPUT)
SN54ALS541 SN74ALS540 SN74ALS541
MIN
4
MAX
17
MIN
2
MAX
12
9
MIN
4
MAX
14
t
t
t
t
t
t
PLH
PHL
PZH
PZL
PHZ
PLZ
A
ns
ns
ns
Y
Y
Y
2
14
2
2
10
5
18
5
15
20
10
12
5
15
OE
OE
8
28
8
8
20
1
12
1
1
10
2
14
2
2
12
¶
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ALS541, SN74ALS540, SN74ALS541
OCTAL BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SDAS025D – APRIL 1982 – REVISED MARCH 2002
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7 V
R
= R1 = R2
V
CC
L
S1
R1
R
L
Test
Point
From Output
Under Test
From Output
Under Test
Test
Point
Test
Point
From Output
Under Test
C
C
L
R
L
R2
L
C
L
(see Note A)
(see Note A)
(see Note A)
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
3.5 V
3.5 V
Timing
Input
High-Level
1.3 V
1.3 V
1.3 V
Pulse
0.3 V
0.3 V
t
t
w
h
t
su
3.5 V
3.5 V
0.3 V
Data
Input
Low-Level
1.3 V
1.3 V
1.3 V
1.3 V
Pulse
0.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
Output
Control
(low-level
enabling)
1.3 V
1.3 V
0.3 V
3.5 V
t
PZL
Input
1.3 V
1.3 V
t
PLZ
0.3 V
PHL
≈3.5 V
t
Waveform 1
S1 Closed
(see Note B)
t
PLH
1.3 V
V
OH
In-Phase
Output
1.3 V
1.3 V
1.3 V
V
OL
V
OL
0.3 V
t
PHZ
t
PLH
t
PZH
t
PHL
V
OH
0.3 V
≈0 V
V
Waveform 2
S1 Open
(see Note B)
OH
OL
Out-of-Phase
Output
(see Note C)
1.3 V
1.3 V
V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, t = t = 2 ns, duty cycle = 50%.
r
f
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
CFP
Drawing
5962-89602012A
5962-8960201RA
5962-8960201SA
SN54ALS541J
ACTIVE
ACTIVE
FK
J
20
20
20
20
20
1
1
TBD
TBD
TBD
TBD
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Level-NC-NC-NC
Level-NC-NC-NC
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OBSOLETE
ACTIVE
W
J
CDIP
SOIC
1
Level-NC-NC-NC
SN74ALS540-1DW
ACTIVE
DW
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74ALS540-1DWE4
ACTIVE
SOIC
DW
20
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74ALS540-1DWR
SN74ALS540-1N
OBSOLETE
ACTIVE
SOIC
PDIP
DW
N
20
20
TBD
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20
20
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
SN74ALS540-1NE4
SN74ALS540-1NSR
SN74ALS540-1NSRE4
SN74ALS540DW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PDIP
SO
N
20
20
20
20
20
20
20
20
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
NS
NS
DW
DW
DW
DW
N
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
SOIC
SOIC
SOIC
PDIP
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74ALS540DWG4
SN74ALS540DWR
SN74ALS540DWRG4
SN74ALS540N
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
20
20
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
SN74ALS540N3
SN74ALS540NE4
OBSOLETE
ACTIVE
PDIP
PDIP
N
N
20
20
TBD
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Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
SN74ALS540NSR
SN74ALS540NSRE4
SN74ALS541-1DBR
SN74ALS541-1DBRE4
SN74ALS541-1DW
SN74ALS541-1DWE4
SN74ALS541-1DWR
SN74ALS541-1DWRE4
SN74ALS541-1N
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SO
NS
NS
DB
DB
DW
DW
DW
DW
N
20
20
20
20
20
20
20
20
20
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SSOP
SSOP
SOIC
SOIC
SOIC
SOIC
PDIP
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
20
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
Orderable Device
SN74ALS541-1NE4
SN74ALS541-1NSR
SN74ALS541-1NSRE4
SN74ALS541DBR
SN74ALS541DBRE4
SN74ALS541DW
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
PDIP
N
20
20
20
20
20
20
20
20
20
20
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
SO
NS
NS
DB
DB
DW
DW
DW
N
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SSOP
SSOP
SOIC
SOIC
SOIC
PDIP
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74ALS541DWR
SN74ALS541DWRE4
SN74ALS541N
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
20
20
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
SN74ALS541N3
SN74ALS541NE4
OBSOLETE
ACTIVE
PDIP
PDIP
N
N
20
20
TBD
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Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
SN74ALS541NSR
ACTIVE
ACTIVE
SO
SO
NS
NS
20
20
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74ALS541NSRE4
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SNJ54ALS541FK
SNJ54ALS541J
ACTIVE
ACTIVE
LCCC
CDIP
FK
J
20
20
1
1
TBD
TBD
Call TI
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Level-NC-NC-NC
Level-NC-NC-NC
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 3
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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